diff --git a/src/adc.rs b/src/adc.rs index ba68c8111..896431762 100644 --- a/src/adc.rs +++ b/src/adc.rs @@ -32,10 +32,7 @@ impl RegisterBlock { pub const fn fifo(&self) -> &FIFO { &self.fifo } - #[doc = "0x10 - Clock divider. If non-zero, CS_START_MANY will start conversions - at regular intervals rather than back-to-back. - The divider is reset when either of these fields are written. - Total period is 1 + INT + FRAC / 256"] + #[doc = "0x10 - Clock divider. If non-zero, CS_START_MANY will start conversions at regular intervals rather than back-to-back. The divider is reset when either of these fields are written. Total period is 1 + INT + FRAC / 256"] #[inline(always)] pub const fn div(&self) -> &DIV { &self.div @@ -70,9 +67,9 @@ module"] pub type CS = crate::Reg; #[doc = "ADC Control and Status"] pub mod cs; -#[doc = "RESULT (r) register accessor: Result of most recent ADC conversion +#[doc = "RESULT (rw) register accessor: Result of most recent ADC conversion -You can [`read`](crate::generic::Reg::read) this register and get [`result::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`result::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`result::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@result`] module"] @@ -88,33 +85,27 @@ module"] pub type FCS = crate::Reg; #[doc = "FIFO control and status"] pub mod fcs; -#[doc = "FIFO (r) register accessor: Conversion result FIFO +#[doc = "FIFO (rw) register accessor: Conversion result FIFO -You can [`read`](crate::generic::Reg::read) this register and get [`fifo::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`fifo::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@fifo`] module"] pub type FIFO = crate::Reg; #[doc = "Conversion result FIFO"] pub mod fifo; -#[doc = "DIV (rw) register accessor: Clock divider. If non-zero, CS_START_MANY will start conversions - at regular intervals rather than back-to-back. - The divider is reset when either of these fields are written. - Total period is 1 + INT + FRAC / 256 +#[doc = "DIV (rw) register accessor: Clock divider. If non-zero, CS_START_MANY will start conversions at regular intervals rather than back-to-back. The divider is reset when either of these fields are written. Total period is 1 + INT + FRAC / 256 You can [`read`](crate::generic::Reg::read) this register and get [`div::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`div::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@div`] module"] pub type DIV = crate::Reg; -#[doc = "Clock divider. If non-zero, CS_START_MANY will start conversions - at regular intervals rather than back-to-back. - The divider is reset when either of these fields are written. - Total period is 1 + INT + FRAC / 256"] +#[doc = "Clock divider. If non-zero, CS_START_MANY will start conversions at regular intervals rather than back-to-back. The divider is reset when either of these fields are written. Total period is 1 + INT + FRAC / 256"] pub mod div; -#[doc = "INTR (r) register accessor: Raw Interrupts +#[doc = "INTR (rw) register accessor: Raw Interrupts -You can [`read`](crate::generic::Reg::read) this register and get [`intr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`intr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@intr`] module"] @@ -139,9 +130,9 @@ module"] pub type INTF = crate::Reg; #[doc = "Interrupt Force"] pub mod intf; -#[doc = "INTS (r) register accessor: Interrupt status after masking & forcing +#[doc = "INTS (rw) register accessor: Interrupt status after masking & forcing -You can [`read`](crate::generic::Reg::read) this register and get [`ints::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`ints::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ints::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@ints`] module"] diff --git a/src/adc/cs.rs b/src/adc/cs.rs index 4f22e80f2..69141b4b2 100644 --- a/src/adc/cs.rs +++ b/src/adc/cs.rs @@ -2,26 +2,21 @@ pub type R = crate::R; #[doc = "Register `CS` writer"] pub type W = crate::W; -#[doc = "Field `EN` reader - Power on ADC and enable its clock. - 1 - enabled. 0 - disabled."] +#[doc = "Field `EN` reader - Power on ADC and enable its clock. 1 - enabled. 0 - disabled."] pub type EN_R = crate::BitReader; -#[doc = "Field `EN` writer - Power on ADC and enable its clock. - 1 - enabled. 0 - disabled."] +#[doc = "Field `EN` writer - Power on ADC and enable its clock. 1 - enabled. 0 - disabled."] pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `TS_EN` reader - Power on temperature sensor. 1 - enabled. 0 - disabled."] pub type TS_EN_R = crate::BitReader; #[doc = "Field `TS_EN` writer - Power on temperature sensor. 1 - enabled. 0 - disabled."] pub type TS_EN_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `START_ONCE` reader - Start a single conversion. Self-clearing. Ignored if start_many is asserted."] -pub type START_ONCE_R = crate::BitReader; #[doc = "Field `START_ONCE` writer - Start a single conversion. Self-clearing. Ignored if start_many is asserted."] pub type START_ONCE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `START_MANY` reader - Continuously perform conversions whilst this bit is 1. A new conversion will start immediately after the previous finishes."] pub type START_MANY_R = crate::BitReader; #[doc = "Field `START_MANY` writer - Continuously perform conversions whilst this bit is 1. A new conversion will start immediately after the previous finishes."] pub type START_MANY_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `READY` reader - 1 if the ADC is ready to start a new conversion. Implies any previous conversion has completed. - 0 whilst conversion in progress."] +#[doc = "Field `READY` reader - 1 if the ADC is ready to start a new conversion. Implies any previous conversion has completed. 0 whilst conversion in progress."] pub type READY_R = crate::BitReader; #[doc = "Field `ERR` reader - The most recent ADC conversion encountered an error; result is undefined or noisy."] pub type ERR_R = crate::BitReader; @@ -33,19 +28,12 @@ pub type ERR_STICKY_W<'a, REG> = crate::BitWriter1C<'a, REG>; pub type AINSEL_R = crate::FieldReader; #[doc = "Field `AINSEL` writer - Select analog mux input. Updated automatically in round-robin mode."] pub type AINSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; -#[doc = "Field `RROBIN` reader - Round-robin sampling. 1 bit per channel. Set all bits to 0 to disable. - Otherwise, the ADC will cycle through each enabled channel in a round-robin fashion. - The first channel to be sampled will be the one currently indicated by AINSEL. - AINSEL will be updated after each conversion with the newly-selected channel."] +#[doc = "Field `RROBIN` reader - Round-robin sampling. 1 bit per channel. Set all bits to 0 to disable. Otherwise, the ADC will cycle through each enabled channel in a round-robin fashion. The first channel to be sampled will be the one currently indicated by AINSEL. AINSEL will be updated after each conversion with the newly-selected channel."] pub type RROBIN_R = crate::FieldReader; -#[doc = "Field `RROBIN` writer - Round-robin sampling. 1 bit per channel. Set all bits to 0 to disable. - Otherwise, the ADC will cycle through each enabled channel in a round-robin fashion. - The first channel to be sampled will be the one currently indicated by AINSEL. - AINSEL will be updated after each conversion with the newly-selected channel."] +#[doc = "Field `RROBIN` writer - Round-robin sampling. 1 bit per channel. Set all bits to 0 to disable. Otherwise, the ADC will cycle through each enabled channel in a round-robin fashion. The first channel to be sampled will be the one currently indicated by AINSEL. AINSEL will be updated after each conversion with the newly-selected channel."] pub type RROBIN_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; impl R { - #[doc = "Bit 0 - Power on ADC and enable its clock. - 1 - enabled. 0 - disabled."] + #[doc = "Bit 0 - Power on ADC and enable its clock. 1 - enabled. 0 - disabled."] #[inline(always)] pub fn en(&self) -> EN_R { EN_R::new((self.bits & 1) != 0) @@ -55,18 +43,12 @@ impl R { pub fn ts_en(&self) -> TS_EN_R { TS_EN_R::new(((self.bits >> 1) & 1) != 0) } - #[doc = "Bit 2 - Start a single conversion. Self-clearing. Ignored if start_many is asserted."] - #[inline(always)] - pub fn start_once(&self) -> START_ONCE_R { - START_ONCE_R::new(((self.bits >> 2) & 1) != 0) - } #[doc = "Bit 3 - Continuously perform conversions whilst this bit is 1. A new conversion will start immediately after the previous finishes."] #[inline(always)] pub fn start_many(&self) -> START_MANY_R { START_MANY_R::new(((self.bits >> 3) & 1) != 0) } - #[doc = "Bit 8 - 1 if the ADC is ready to start a new conversion. Implies any previous conversion has completed. - 0 whilst conversion in progress."] + #[doc = "Bit 8 - 1 if the ADC is ready to start a new conversion. Implies any previous conversion has completed. 0 whilst conversion in progress."] #[inline(always)] pub fn ready(&self) -> READY_R { READY_R::new(((self.bits >> 8) & 1) != 0) @@ -86,18 +68,14 @@ impl R { pub fn ainsel(&self) -> AINSEL_R { AINSEL_R::new(((self.bits >> 12) & 7) as u8) } - #[doc = "Bits 16:20 - Round-robin sampling. 1 bit per channel. Set all bits to 0 to disable. - Otherwise, the ADC will cycle through each enabled channel in a round-robin fashion. - The first channel to be sampled will be the one currently indicated by AINSEL. - AINSEL will be updated after each conversion with the newly-selected channel."] + #[doc = "Bits 16:20 - Round-robin sampling. 1 bit per channel. Set all bits to 0 to disable. Otherwise, the ADC will cycle through each enabled channel in a round-robin fashion. The first channel to be sampled will be the one currently indicated by AINSEL. AINSEL will be updated after each conversion with the newly-selected channel."] #[inline(always)] pub fn rrobin(&self) -> RROBIN_R { RROBIN_R::new(((self.bits >> 16) & 0x1f) as u8) } } impl W { - #[doc = "Bit 0 - Power on ADC and enable its clock. - 1 - enabled. 0 - disabled."] + #[doc = "Bit 0 - Power on ADC and enable its clock. 1 - enabled. 0 - disabled."] #[inline(always)] #[must_use] pub fn en(&mut self) -> EN_W { @@ -133,10 +111,7 @@ impl W { pub fn ainsel(&mut self) -> AINSEL_W { AINSEL_W::new(self, 12) } - #[doc = "Bits 16:20 - Round-robin sampling. 1 bit per channel. Set all bits to 0 to disable. - Otherwise, the ADC will cycle through each enabled channel in a round-robin fashion. - The first channel to be sampled will be the one currently indicated by AINSEL. - AINSEL will be updated after each conversion with the newly-selected channel."] + #[doc = "Bits 16:20 - Round-robin sampling. 1 bit per channel. Set all bits to 0 to disable. Otherwise, the ADC will cycle through each enabled channel in a round-robin fashion. The first channel to be sampled will be the one currently indicated by AINSEL. AINSEL will be updated after each conversion with the newly-selected channel."] #[inline(always)] #[must_use] pub fn rrobin(&mut self) -> RROBIN_W { diff --git a/src/adc/div.rs b/src/adc/div.rs index 4bd141132..0d12c8019 100644 --- a/src/adc/div.rs +++ b/src/adc/div.rs @@ -36,10 +36,7 @@ impl W { INT_W::new(self, 8) } } -#[doc = "Clock divider. If non-zero, CS_START_MANY will start conversions - at regular intervals rather than back-to-back. - The divider is reset when either of these fields are written. - Total period is 1 + INT + FRAC / 256 +#[doc = "Clock divider. If non-zero, CS_START_MANY will start conversions at regular intervals rather than back-to-back. The divider is reset when either of these fields are written. Total period is 1 + INT + FRAC / 256 You can [`read`](crate::generic::Reg::read) this register and get [`div::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`div::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DIV_SPEC; diff --git a/src/adc/fifo.rs b/src/adc/fifo.rs index 981838117..cbae53178 100644 --- a/src/adc/fifo.rs +++ b/src/adc/fifo.rs @@ -1,8 +1,14 @@ #[doc = "Register `FIFO` reader"] pub type R = crate::R; -#[doc = "Field `VAL` reader - "] +#[doc = "Register `FIFO` writer"] +pub type W = crate::W; +#[doc = "Field `VAL` reader - + +The field is **modified** in some way after a read operation."] pub type VAL_R = crate::FieldReader; -#[doc = "Field `ERR` reader - 1 if this particular sample experienced a conversion error. Remains in the same location if the sample is shifted."] +#[doc = "Field `ERR` reader - 1 if this particular sample experienced a conversion error. Remains in the same location if the sample is shifted. + +The field is **modified** in some way after a read operation."] pub type ERR_R = crate::BitReader; impl R { #[doc = "Bits 0:11"] @@ -16,15 +22,22 @@ impl R { ERR_R::new(((self.bits >> 15) & 1) != 0) } } +impl W {} #[doc = "Conversion result FIFO -You can [`read`](crate::generic::Reg::read) this register and get [`fifo::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`fifo::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FIFO_SPEC; impl crate::RegisterSpec for FIFO_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`fifo::R`](R) reader structure"] impl crate::Readable for FIFO_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fifo::W`](W) writer structure"] +impl crate::Writable for FIFO_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets FIFO to value 0"] impl crate::Resettable for FIFO_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/adc/inte.rs b/src/adc/inte.rs index 48ddb4a7f..d3e2ad17e 100644 --- a/src/adc/inte.rs +++ b/src/adc/inte.rs @@ -2,23 +2,19 @@ pub type R = crate::R; #[doc = "Register `INTE` writer"] pub type W = crate::W; -#[doc = "Field `FIFO` reader - Triggered when the sample FIFO reaches a certain level. - This level can be programmed via the FCS_THRESH field."] +#[doc = "Field `FIFO` reader - Triggered when the sample FIFO reaches a certain level. This level can be programmed via the FCS_THRESH field."] pub type FIFO_R = crate::BitReader; -#[doc = "Field `FIFO` writer - Triggered when the sample FIFO reaches a certain level. - This level can be programmed via the FCS_THRESH field."] +#[doc = "Field `FIFO` writer - Triggered when the sample FIFO reaches a certain level. This level can be programmed via the FCS_THRESH field."] pub type FIFO_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { - #[doc = "Bit 0 - Triggered when the sample FIFO reaches a certain level. - This level can be programmed via the FCS_THRESH field."] + #[doc = "Bit 0 - Triggered when the sample FIFO reaches a certain level. This level can be programmed via the FCS_THRESH field."] #[inline(always)] pub fn fifo(&self) -> FIFO_R { FIFO_R::new((self.bits & 1) != 0) } } impl W { - #[doc = "Bit 0 - Triggered when the sample FIFO reaches a certain level. - This level can be programmed via the FCS_THRESH field."] + #[doc = "Bit 0 - Triggered when the sample FIFO reaches a certain level. This level can be programmed via the FCS_THRESH field."] #[inline(always)] #[must_use] pub fn fifo(&mut self) -> FIFO_W { diff --git a/src/adc/intf.rs b/src/adc/intf.rs index aec4073f3..97205fa98 100644 --- a/src/adc/intf.rs +++ b/src/adc/intf.rs @@ -2,23 +2,19 @@ pub type R = crate::R; #[doc = "Register `INTF` writer"] pub type W = crate::W; -#[doc = "Field `FIFO` reader - Triggered when the sample FIFO reaches a certain level. - This level can be programmed via the FCS_THRESH field."] +#[doc = "Field `FIFO` reader - Triggered when the sample FIFO reaches a certain level. This level can be programmed via the FCS_THRESH field."] pub type FIFO_R = crate::BitReader; -#[doc = "Field `FIFO` writer - Triggered when the sample FIFO reaches a certain level. - This level can be programmed via the FCS_THRESH field."] +#[doc = "Field `FIFO` writer - Triggered when the sample FIFO reaches a certain level. This level can be programmed via the FCS_THRESH field."] pub type FIFO_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { - #[doc = "Bit 0 - Triggered when the sample FIFO reaches a certain level. - This level can be programmed via the FCS_THRESH field."] + #[doc = "Bit 0 - Triggered when the sample FIFO reaches a certain level. This level can be programmed via the FCS_THRESH field."] #[inline(always)] pub fn fifo(&self) -> FIFO_R { FIFO_R::new((self.bits & 1) != 0) } } impl W { - #[doc = "Bit 0 - Triggered when the sample FIFO reaches a certain level. - This level can be programmed via the FCS_THRESH field."] + #[doc = "Bit 0 - Triggered when the sample FIFO reaches a certain level. This level can be programmed via the FCS_THRESH field."] #[inline(always)] #[must_use] pub fn fifo(&mut self) -> FIFO_W { diff --git a/src/adc/intr.rs b/src/adc/intr.rs index 1d93d17f0..a0f9bf83f 100644 --- a/src/adc/intr.rs +++ b/src/adc/intr.rs @@ -1,25 +1,32 @@ #[doc = "Register `INTR` reader"] pub type R = crate::R; -#[doc = "Field `FIFO` reader - Triggered when the sample FIFO reaches a certain level. - This level can be programmed via the FCS_THRESH field."] +#[doc = "Register `INTR` writer"] +pub type W = crate::W; +#[doc = "Field `FIFO` reader - Triggered when the sample FIFO reaches a certain level. This level can be programmed via the FCS_THRESH field."] pub type FIFO_R = crate::BitReader; impl R { - #[doc = "Bit 0 - Triggered when the sample FIFO reaches a certain level. - This level can be programmed via the FCS_THRESH field."] + #[doc = "Bit 0 - Triggered when the sample FIFO reaches a certain level. This level can be programmed via the FCS_THRESH field."] #[inline(always)] pub fn fifo(&self) -> FIFO_R { FIFO_R::new((self.bits & 1) != 0) } } +impl W {} #[doc = "Raw Interrupts -You can [`read`](crate::generic::Reg::read) this register and get [`intr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`intr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTR_SPEC; impl crate::RegisterSpec for INTR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`intr::R`](R) reader structure"] impl crate::Readable for INTR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`intr::W`](W) writer structure"] +impl crate::Writable for INTR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets INTR to value 0"] impl crate::Resettable for INTR_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/adc/ints.rs b/src/adc/ints.rs index e96b7e85e..cd1b9269a 100644 --- a/src/adc/ints.rs +++ b/src/adc/ints.rs @@ -1,25 +1,32 @@ #[doc = "Register `INTS` reader"] pub type R = crate::R; -#[doc = "Field `FIFO` reader - Triggered when the sample FIFO reaches a certain level. - This level can be programmed via the FCS_THRESH field."] +#[doc = "Register `INTS` writer"] +pub type W = crate::W; +#[doc = "Field `FIFO` reader - Triggered when the sample FIFO reaches a certain level. This level can be programmed via the FCS_THRESH field."] pub type FIFO_R = crate::BitReader; impl R { - #[doc = "Bit 0 - Triggered when the sample FIFO reaches a certain level. - This level can be programmed via the FCS_THRESH field."] + #[doc = "Bit 0 - Triggered when the sample FIFO reaches a certain level. This level can be programmed via the FCS_THRESH field."] #[inline(always)] pub fn fifo(&self) -> FIFO_R { FIFO_R::new((self.bits & 1) != 0) } } +impl W {} #[doc = "Interrupt status after masking & forcing -You can [`read`](crate::generic::Reg::read) this register and get [`ints::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`ints::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ints::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTS_SPEC; impl crate::RegisterSpec for INTS_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`ints::R`](R) reader structure"] impl crate::Readable for INTS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ints::W`](W) writer structure"] +impl crate::Writable for INTS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets INTS to value 0"] impl crate::Resettable for INTS_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/adc/result.rs b/src/adc/result.rs index f7d77826f..f94116eed 100644 --- a/src/adc/result.rs +++ b/src/adc/result.rs @@ -1,5 +1,7 @@ #[doc = "Register `RESULT` reader"] pub type R = crate::R; +#[doc = "Register `RESULT` writer"] +pub type W = crate::W; #[doc = "Field `RESULT` reader - "] pub type RESULT_R = crate::FieldReader; impl R { @@ -9,15 +11,22 @@ impl R { RESULT_R::new((self.bits & 0x0fff) as u16) } } +impl W {} #[doc = "Result of most recent ADC conversion -You can [`read`](crate::generic::Reg::read) this register and get [`result::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`result::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`result::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RESULT_SPEC; impl crate::RegisterSpec for RESULT_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`result::R`](R) reader structure"] impl crate::Readable for RESULT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`result::W`](W) writer structure"] +impl crate::Writable for RESULT_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets RESULT to value 0"] impl crate::Resettable for RESULT_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/busctrl.rs b/src/busctrl.rs index 308d0eda9..e8d9b56e7 100644 --- a/src/busctrl.rs +++ b/src/busctrl.rs @@ -73,9 +73,9 @@ module"] pub type BUS_PRIORITY = crate::Reg; #[doc = "Set the priority of each master for bus arbitration."] pub mod bus_priority; -#[doc = "BUS_PRIORITY_ACK (r) register accessor: Bus priority acknowledge +#[doc = "BUS_PRIORITY_ACK (rw) register accessor: Bus priority acknowledge -You can [`read`](crate::generic::Reg::read) this register and get [`bus_priority_ack::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`bus_priority_ack::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bus_priority_ack::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@bus_priority_ack`] module"] diff --git a/src/busctrl/bus_priority_ack.rs b/src/busctrl/bus_priority_ack.rs index 6384115fb..766a60e5f 100644 --- a/src/busctrl/bus_priority_ack.rs +++ b/src/busctrl/bus_priority_ack.rs @@ -1,27 +1,32 @@ #[doc = "Register `BUS_PRIORITY_ACK` reader"] pub type R = crate::R; -#[doc = "Field `BUS_PRIORITY_ACK` reader - Goes to 1 once all arbiters have registered the new global priority levels. - Arbiters update their local priority when servicing a new nonsequential access. - In normal circumstances this will happen almost immediately."] +#[doc = "Register `BUS_PRIORITY_ACK` writer"] +pub type W = crate::W; +#[doc = "Field `BUS_PRIORITY_ACK` reader - Goes to 1 once all arbiters have registered the new global priority levels. Arbiters update their local priority when servicing a new nonsequential access. In normal circumstances this will happen almost immediately."] pub type BUS_PRIORITY_ACK_R = crate::BitReader; impl R { - #[doc = "Bit 0 - Goes to 1 once all arbiters have registered the new global priority levels. - Arbiters update their local priority when servicing a new nonsequential access. - In normal circumstances this will happen almost immediately."] + #[doc = "Bit 0 - Goes to 1 once all arbiters have registered the new global priority levels. Arbiters update their local priority when servicing a new nonsequential access. In normal circumstances this will happen almost immediately."] #[inline(always)] pub fn bus_priority_ack(&self) -> BUS_PRIORITY_ACK_R { BUS_PRIORITY_ACK_R::new((self.bits & 1) != 0) } } +impl W {} #[doc = "Bus priority acknowledge -You can [`read`](crate::generic::Reg::read) this register and get [`bus_priority_ack::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`bus_priority_ack::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bus_priority_ack::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct BUS_PRIORITY_ACK_SPEC; impl crate::RegisterSpec for BUS_PRIORITY_ACK_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`bus_priority_ack::R`](R) reader structure"] impl crate::Readable for BUS_PRIORITY_ACK_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bus_priority_ack::W`](W) writer structure"] +impl crate::Writable for BUS_PRIORITY_ACK_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets BUS_PRIORITY_ACK to value 0"] impl crate::Resettable for BUS_PRIORITY_ACK_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/busctrl/perfctr0.rs b/src/busctrl/perfctr0.rs index 24c7eef13..849fd3655 100644 --- a/src/busctrl/perfctr0.rs +++ b/src/busctrl/perfctr0.rs @@ -2,27 +2,19 @@ pub type R = crate::R; #[doc = "Register `PERFCTR0` writer"] pub type W = crate::W; -#[doc = "Field `PERFCTR0` reader - Busfabric saturating performance counter 0 - Count some event signal from the busfabric arbiters. - Write any value to clear. Select an event to count using PERFSEL0"] +#[doc = "Field `PERFCTR0` reader - Busfabric saturating performance counter 0 Count some event signal from the busfabric arbiters. Write any value to clear. Select an event to count using PERFSEL0"] pub type PERFCTR0_R = crate::FieldReader; -#[doc = "Field `PERFCTR0` writer - Busfabric saturating performance counter 0 - Count some event signal from the busfabric arbiters. - Write any value to clear. Select an event to count using PERFSEL0"] +#[doc = "Field `PERFCTR0` writer - Busfabric saturating performance counter 0 Count some event signal from the busfabric arbiters. Write any value to clear. Select an event to count using PERFSEL0"] pub type PERFCTR0_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; impl R { - #[doc = "Bits 0:23 - Busfabric saturating performance counter 0 - Count some event signal from the busfabric arbiters. - Write any value to clear. Select an event to count using PERFSEL0"] + #[doc = "Bits 0:23 - Busfabric saturating performance counter 0 Count some event signal from the busfabric arbiters. Write any value to clear. Select an event to count using PERFSEL0"] #[inline(always)] pub fn perfctr0(&self) -> PERFCTR0_R { PERFCTR0_R::new(self.bits & 0x00ff_ffff) } } impl W { - #[doc = "Bits 0:23 - Busfabric saturating performance counter 0 - Count some event signal from the busfabric arbiters. - Write any value to clear. Select an event to count using PERFSEL0"] + #[doc = "Bits 0:23 - Busfabric saturating performance counter 0 Count some event signal from the busfabric arbiters. Write any value to clear. Select an event to count using PERFSEL0"] #[inline(always)] #[must_use] pub fn perfctr0(&mut self) -> PERFCTR0_W { diff --git a/src/busctrl/perfctr1.rs b/src/busctrl/perfctr1.rs index 5d755ae07..744f9f282 100644 --- a/src/busctrl/perfctr1.rs +++ b/src/busctrl/perfctr1.rs @@ -2,27 +2,19 @@ pub type R = crate::R; #[doc = "Register `PERFCTR1` writer"] pub type W = crate::W; -#[doc = "Field `PERFCTR1` reader - Busfabric saturating performance counter 1 - Count some event signal from the busfabric arbiters. - Write any value to clear. Select an event to count using PERFSEL1"] +#[doc = "Field `PERFCTR1` reader - Busfabric saturating performance counter 1 Count some event signal from the busfabric arbiters. Write any value to clear. Select an event to count using PERFSEL1"] pub type PERFCTR1_R = crate::FieldReader; -#[doc = "Field `PERFCTR1` writer - Busfabric saturating performance counter 1 - Count some event signal from the busfabric arbiters. - Write any value to clear. Select an event to count using PERFSEL1"] +#[doc = "Field `PERFCTR1` writer - Busfabric saturating performance counter 1 Count some event signal from the busfabric arbiters. Write any value to clear. Select an event to count using PERFSEL1"] pub type PERFCTR1_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; impl R { - #[doc = "Bits 0:23 - Busfabric saturating performance counter 1 - Count some event signal from the busfabric arbiters. - Write any value to clear. Select an event to count using PERFSEL1"] + #[doc = "Bits 0:23 - Busfabric saturating performance counter 1 Count some event signal from the busfabric arbiters. Write any value to clear. Select an event to count using PERFSEL1"] #[inline(always)] pub fn perfctr1(&self) -> PERFCTR1_R { PERFCTR1_R::new(self.bits & 0x00ff_ffff) } } impl W { - #[doc = "Bits 0:23 - Busfabric saturating performance counter 1 - Count some event signal from the busfabric arbiters. - Write any value to clear. Select an event to count using PERFSEL1"] + #[doc = "Bits 0:23 - Busfabric saturating performance counter 1 Count some event signal from the busfabric arbiters. Write any value to clear. Select an event to count using PERFSEL1"] #[inline(always)] #[must_use] pub fn perfctr1(&mut self) -> PERFCTR1_W { diff --git a/src/busctrl/perfctr2.rs b/src/busctrl/perfctr2.rs index d93cd401b..9ace73081 100644 --- a/src/busctrl/perfctr2.rs +++ b/src/busctrl/perfctr2.rs @@ -2,27 +2,19 @@ pub type R = crate::R; #[doc = "Register `PERFCTR2` writer"] pub type W = crate::W; -#[doc = "Field `PERFCTR2` reader - Busfabric saturating performance counter 2 - Count some event signal from the busfabric arbiters. - Write any value to clear. Select an event to count using PERFSEL2"] +#[doc = "Field `PERFCTR2` reader - Busfabric saturating performance counter 2 Count some event signal from the busfabric arbiters. Write any value to clear. Select an event to count using PERFSEL2"] pub type PERFCTR2_R = crate::FieldReader; -#[doc = "Field `PERFCTR2` writer - Busfabric saturating performance counter 2 - Count some event signal from the busfabric arbiters. - Write any value to clear. Select an event to count using PERFSEL2"] +#[doc = "Field `PERFCTR2` writer - Busfabric saturating performance counter 2 Count some event signal from the busfabric arbiters. Write any value to clear. Select an event to count using PERFSEL2"] pub type PERFCTR2_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; impl R { - #[doc = "Bits 0:23 - Busfabric saturating performance counter 2 - Count some event signal from the busfabric arbiters. - Write any value to clear. Select an event to count using PERFSEL2"] + #[doc = "Bits 0:23 - Busfabric saturating performance counter 2 Count some event signal from the busfabric arbiters. Write any value to clear. Select an event to count using PERFSEL2"] #[inline(always)] pub fn perfctr2(&self) -> PERFCTR2_R { PERFCTR2_R::new(self.bits & 0x00ff_ffff) } } impl W { - #[doc = "Bits 0:23 - Busfabric saturating performance counter 2 - Count some event signal from the busfabric arbiters. - Write any value to clear. Select an event to count using PERFSEL2"] + #[doc = "Bits 0:23 - Busfabric saturating performance counter 2 Count some event signal from the busfabric arbiters. Write any value to clear. Select an event to count using PERFSEL2"] #[inline(always)] #[must_use] pub fn perfctr2(&mut self) -> PERFCTR2_W { diff --git a/src/busctrl/perfctr3.rs b/src/busctrl/perfctr3.rs index 6946cf253..782baf64f 100644 --- a/src/busctrl/perfctr3.rs +++ b/src/busctrl/perfctr3.rs @@ -2,27 +2,19 @@ pub type R = crate::R; #[doc = "Register `PERFCTR3` writer"] pub type W = crate::W; -#[doc = "Field `PERFCTR3` reader - Busfabric saturating performance counter 3 - Count some event signal from the busfabric arbiters. - Write any value to clear. Select an event to count using PERFSEL3"] +#[doc = "Field `PERFCTR3` reader - Busfabric saturating performance counter 3 Count some event signal from the busfabric arbiters. Write any value to clear. Select an event to count using PERFSEL3"] pub type PERFCTR3_R = crate::FieldReader; -#[doc = "Field `PERFCTR3` writer - Busfabric saturating performance counter 3 - Count some event signal from the busfabric arbiters. - Write any value to clear. Select an event to count using PERFSEL3"] +#[doc = "Field `PERFCTR3` writer - Busfabric saturating performance counter 3 Count some event signal from the busfabric arbiters. Write any value to clear. Select an event to count using PERFSEL3"] pub type PERFCTR3_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; impl R { - #[doc = "Bits 0:23 - Busfabric saturating performance counter 3 - Count some event signal from the busfabric arbiters. - Write any value to clear. Select an event to count using PERFSEL3"] + #[doc = "Bits 0:23 - Busfabric saturating performance counter 3 Count some event signal from the busfabric arbiters. Write any value to clear. Select an event to count using PERFSEL3"] #[inline(always)] pub fn perfctr3(&self) -> PERFCTR3_R { PERFCTR3_R::new(self.bits & 0x00ff_ffff) } } impl W { - #[doc = "Bits 0:23 - Busfabric saturating performance counter 3 - Count some event signal from the busfabric arbiters. - Write any value to clear. Select an event to count using PERFSEL3"] + #[doc = "Bits 0:23 - Busfabric saturating performance counter 3 Count some event signal from the busfabric arbiters. Write any value to clear. Select an event to count using PERFSEL3"] #[inline(always)] #[must_use] pub fn perfctr3(&mut self) -> PERFCTR3_W { diff --git a/src/clocks.rs b/src/clocks.rs index 92a0dda46..feeb30b97 100644 --- a/src/clocks.rs +++ b/src/clocks.rs @@ -20,7 +20,7 @@ pub struct RegisterBlock { clk_sys_div: CLK_SYS_DIV, clk_sys_selected: CLK_SYS_SELECTED, clk_peri_ctrl: CLK_PERI_CTRL, - _reserved19: [u8; 0x04], + clk_peri_div: CLK_PERI_DIV, clk_peri_selected: CLK_PERI_SELECTED, clk_usb_ctrl: CLK_USB_CTRL, clk_usb_div: CLK_USB_DIV, @@ -63,8 +63,7 @@ impl RegisterBlock { pub const fn clk_gpout0_div(&self) -> &CLK_GPOUT0_DIV { &self.clk_gpout0_div } - #[doc = "0x08 - Indicates which SRC is currently selected by the glitchless mux (one-hot). - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."] + #[doc = "0x08 - Indicates which SRC is currently selected by the glitchless mux (one-hot)."] #[inline(always)] pub const fn clk_gpout0_selected(&self) -> &CLK_GPOUT0_SELECTED { &self.clk_gpout0_selected @@ -79,8 +78,7 @@ impl RegisterBlock { pub const fn clk_gpout1_div(&self) -> &CLK_GPOUT1_DIV { &self.clk_gpout1_div } - #[doc = "0x14 - Indicates which SRC is currently selected by the glitchless mux (one-hot). - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."] + #[doc = "0x14 - Indicates which SRC is currently selected by the glitchless mux (one-hot)."] #[inline(always)] pub const fn clk_gpout1_selected(&self) -> &CLK_GPOUT1_SELECTED { &self.clk_gpout1_selected @@ -95,8 +93,7 @@ impl RegisterBlock { pub const fn clk_gpout2_div(&self) -> &CLK_GPOUT2_DIV { &self.clk_gpout2_div } - #[doc = "0x20 - Indicates which SRC is currently selected by the glitchless mux (one-hot). - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."] + #[doc = "0x20 - Indicates which SRC is currently selected by the glitchless mux (one-hot)."] #[inline(always)] pub const fn clk_gpout2_selected(&self) -> &CLK_GPOUT2_SELECTED { &self.clk_gpout2_selected @@ -111,8 +108,7 @@ impl RegisterBlock { pub const fn clk_gpout3_div(&self) -> &CLK_GPOUT3_DIV { &self.clk_gpout3_div } - #[doc = "0x2c - Indicates which SRC is currently selected by the glitchless mux (one-hot). - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."] + #[doc = "0x2c - Indicates which SRC is currently selected by the glitchless mux (one-hot)."] #[inline(always)] pub const fn clk_gpout3_selected(&self) -> &CLK_GPOUT3_SELECTED { &self.clk_gpout3_selected @@ -127,8 +123,7 @@ impl RegisterBlock { pub const fn clk_ref_div(&self) -> &CLK_REF_DIV { &self.clk_ref_div } - #[doc = "0x38 - Indicates which SRC is currently selected by the glitchless mux (one-hot). - The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s."] + #[doc = "0x38 - Indicates which SRC is currently selected by the glitchless mux (one-hot)."] #[inline(always)] pub const fn clk_ref_selected(&self) -> &CLK_REF_SELECTED { &self.clk_ref_selected @@ -143,8 +138,7 @@ impl RegisterBlock { pub const fn clk_sys_div(&self) -> &CLK_SYS_DIV { &self.clk_sys_div } - #[doc = "0x44 - Indicates which SRC is currently selected by the glitchless mux (one-hot). - The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s."] + #[doc = "0x44 - Indicates which SRC is currently selected by the glitchless mux (one-hot)."] #[inline(always)] pub const fn clk_sys_selected(&self) -> &CLK_SYS_SELECTED { &self.clk_sys_selected @@ -154,8 +148,12 @@ impl RegisterBlock { pub const fn clk_peri_ctrl(&self) -> &CLK_PERI_CTRL { &self.clk_peri_ctrl } - #[doc = "0x50 - Indicates which SRC is currently selected by the glitchless mux (one-hot). - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."] + #[doc = "0x4c - Clock divisor, can be changed on-the-fly"] + #[inline(always)] + pub const fn clk_peri_div(&self) -> &CLK_PERI_DIV { + &self.clk_peri_div + } + #[doc = "0x50 - Indicates which SRC is currently selected by the glitchless mux (one-hot)."] #[inline(always)] pub const fn clk_peri_selected(&self) -> &CLK_PERI_SELECTED { &self.clk_peri_selected @@ -170,8 +168,7 @@ impl RegisterBlock { pub const fn clk_usb_div(&self) -> &CLK_USB_DIV { &self.clk_usb_div } - #[doc = "0x5c - Indicates which SRC is currently selected by the glitchless mux (one-hot). - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."] + #[doc = "0x5c - Indicates which SRC is currently selected by the glitchless mux (one-hot)."] #[inline(always)] pub const fn clk_usb_selected(&self) -> &CLK_USB_SELECTED { &self.clk_usb_selected @@ -186,8 +183,7 @@ impl RegisterBlock { pub const fn clk_adc_div(&self) -> &CLK_ADC_DIV { &self.clk_adc_div } - #[doc = "0x68 - Indicates which SRC is currently selected by the glitchless mux (one-hot). - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."] + #[doc = "0x68 - Indicates which SRC is currently selected by the glitchless mux (one-hot)."] #[inline(always)] pub const fn clk_adc_selected(&self) -> &CLK_ADC_SELECTED { &self.clk_adc_selected @@ -202,8 +198,7 @@ impl RegisterBlock { pub const fn clk_rtc_div(&self) -> &CLK_RTC_DIV { &self.clk_rtc_div } - #[doc = "0x74 - Indicates which SRC is currently selected by the glitchless mux (one-hot). - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."] + #[doc = "0x74 - Indicates which SRC is currently selected by the glitchless mux (one-hot)."] #[inline(always)] pub const fn clk_rtc_selected(&self) -> &CLK_RTC_SELECTED { &self.clk_rtc_selected @@ -233,20 +228,17 @@ impl RegisterBlock { pub const fn fc0_max_khz(&self) -> &FC0_MAX_KHZ { &self.fc0_max_khz } - #[doc = "0x8c - Delays the start of frequency counting to allow the mux to settle - Delay is measured in multiples of the reference clock period"] + #[doc = "0x8c - Delays the start of frequency counting to allow the mux to settle Delay is measured in multiples of the reference clock period"] #[inline(always)] pub const fn fc0_delay(&self) -> &FC0_DELAY { &self.fc0_delay } - #[doc = "0x90 - The test interval is 0.98us * 2**interval, but let's call it 1us * 2**interval - The default gives a test interval of 250us"] + #[doc = "0x90 - The test interval is 0.98us * 2**interval, but let's call it 1us * 2**interval The default gives a test interval of 250us"] #[inline(always)] pub const fn fc0_interval(&self) -> &FC0_INTERVAL { &self.fc0_interval } - #[doc = "0x94 - Clock sent to frequency counter, set to 0 when not required - Writing to this register initiates the frequency count"] + #[doc = "0x94 - Clock sent to frequency counter, set to 0 when not required Writing to this register initiates the frequency count"] #[inline(always)] pub const fn fc0_src(&self) -> &FC0_SRC { &self.fc0_src @@ -330,16 +322,14 @@ module"] pub type CLK_GPOUT0_DIV = crate::Reg; #[doc = "Clock divisor, can be changed on-the-fly"] pub mod clk_gpout0_div; -#[doc = "CLK_GPOUT0_SELECTED (r) register accessor: Indicates which SRC is currently selected by the glitchless mux (one-hot). - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. +#[doc = "CLK_GPOUT0_SELECTED (rw) register accessor: Indicates which SRC is currently selected by the glitchless mux (one-hot). -You can [`read`](crate::generic::Reg::read) this register and get [`clk_gpout0_selected::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`clk_gpout0_selected::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gpout0_selected::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@clk_gpout0_selected`] module"] pub type CLK_GPOUT0_SELECTED = crate::Reg; -#[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot). - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."] +#[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot)."] pub mod clk_gpout0_selected; #[doc = "CLK_GPOUT1_CTRL (rw) register accessor: Clock control, can be changed on-the-fly (except for auxsrc) @@ -359,16 +349,14 @@ module"] pub type CLK_GPOUT1_DIV = crate::Reg; #[doc = "Clock divisor, can be changed on-the-fly"] pub mod clk_gpout1_div; -#[doc = "CLK_GPOUT1_SELECTED (r) register accessor: Indicates which SRC is currently selected by the glitchless mux (one-hot). - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. +#[doc = "CLK_GPOUT1_SELECTED (rw) register accessor: Indicates which SRC is currently selected by the glitchless mux (one-hot). -You can [`read`](crate::generic::Reg::read) this register and get [`clk_gpout1_selected::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`clk_gpout1_selected::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gpout1_selected::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@clk_gpout1_selected`] module"] pub type CLK_GPOUT1_SELECTED = crate::Reg; -#[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot). - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."] +#[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot)."] pub mod clk_gpout1_selected; #[doc = "CLK_GPOUT2_CTRL (rw) register accessor: Clock control, can be changed on-the-fly (except for auxsrc) @@ -388,16 +376,14 @@ module"] pub type CLK_GPOUT2_DIV = crate::Reg; #[doc = "Clock divisor, can be changed on-the-fly"] pub mod clk_gpout2_div; -#[doc = "CLK_GPOUT2_SELECTED (r) register accessor: Indicates which SRC is currently selected by the glitchless mux (one-hot). - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. +#[doc = "CLK_GPOUT2_SELECTED (rw) register accessor: Indicates which SRC is currently selected by the glitchless mux (one-hot). -You can [`read`](crate::generic::Reg::read) this register and get [`clk_gpout2_selected::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`clk_gpout2_selected::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gpout2_selected::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@clk_gpout2_selected`] module"] pub type CLK_GPOUT2_SELECTED = crate::Reg; -#[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot). - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."] +#[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot)."] pub mod clk_gpout2_selected; #[doc = "CLK_GPOUT3_CTRL (rw) register accessor: Clock control, can be changed on-the-fly (except for auxsrc) @@ -417,16 +403,14 @@ module"] pub type CLK_GPOUT3_DIV = crate::Reg; #[doc = "Clock divisor, can be changed on-the-fly"] pub mod clk_gpout3_div; -#[doc = "CLK_GPOUT3_SELECTED (r) register accessor: Indicates which SRC is currently selected by the glitchless mux (one-hot). - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. +#[doc = "CLK_GPOUT3_SELECTED (rw) register accessor: Indicates which SRC is currently selected by the glitchless mux (one-hot). -You can [`read`](crate::generic::Reg::read) this register and get [`clk_gpout3_selected::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`clk_gpout3_selected::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gpout3_selected::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@clk_gpout3_selected`] module"] pub type CLK_GPOUT3_SELECTED = crate::Reg; -#[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot). - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."] +#[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot)."] pub mod clk_gpout3_selected; #[doc = "CLK_REF_CTRL (rw) register accessor: Clock control, can be changed on-the-fly (except for auxsrc) @@ -446,16 +430,14 @@ module"] pub type CLK_REF_DIV = crate::Reg; #[doc = "Clock divisor, can be changed on-the-fly"] pub mod clk_ref_div; -#[doc = "CLK_REF_SELECTED (r) register accessor: Indicates which SRC is currently selected by the glitchless mux (one-hot). - The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s. +#[doc = "CLK_REF_SELECTED (rw) register accessor: Indicates which SRC is currently selected by the glitchless mux (one-hot). -You can [`read`](crate::generic::Reg::read) this register and get [`clk_ref_selected::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`clk_ref_selected::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_ref_selected::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@clk_ref_selected`] module"] pub type CLK_REF_SELECTED = crate::Reg; -#[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot). - The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s."] +#[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot)."] pub mod clk_ref_selected; #[doc = "CLK_SYS_CTRL (rw) register accessor: Clock control, can be changed on-the-fly (except for auxsrc) @@ -475,16 +457,14 @@ module"] pub type CLK_SYS_DIV = crate::Reg; #[doc = "Clock divisor, can be changed on-the-fly"] pub mod clk_sys_div; -#[doc = "CLK_SYS_SELECTED (r) register accessor: Indicates which SRC is currently selected by the glitchless mux (one-hot). - The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s. +#[doc = "CLK_SYS_SELECTED (rw) register accessor: Indicates which SRC is currently selected by the glitchless mux (one-hot). -You can [`read`](crate::generic::Reg::read) this register and get [`clk_sys_selected::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`clk_sys_selected::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_sys_selected::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@clk_sys_selected`] module"] pub type CLK_SYS_SELECTED = crate::Reg; -#[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot). - The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s."] +#[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot)."] pub mod clk_sys_selected; #[doc = "CLK_PERI_CTRL (rw) register accessor: Clock control, can be changed on-the-fly (except for auxsrc) @@ -495,16 +475,23 @@ module"] pub type CLK_PERI_CTRL = crate::Reg; #[doc = "Clock control, can be changed on-the-fly (except for auxsrc)"] pub mod clk_peri_ctrl; -#[doc = "CLK_PERI_SELECTED (r) register accessor: Indicates which SRC is currently selected by the glitchless mux (one-hot). - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. +#[doc = "CLK_PERI_DIV (rw) register accessor: Clock divisor, can be changed on-the-fly + +You can [`read`](crate::generic::Reg::read) this register and get [`clk_peri_div::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_peri_div::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@clk_peri_div`] +module"] +pub type CLK_PERI_DIV = crate::Reg; +#[doc = "Clock divisor, can be changed on-the-fly"] +pub mod clk_peri_div; +#[doc = "CLK_PERI_SELECTED (rw) register accessor: Indicates which SRC is currently selected by the glitchless mux (one-hot). -You can [`read`](crate::generic::Reg::read) this register and get [`clk_peri_selected::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`clk_peri_selected::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_peri_selected::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@clk_peri_selected`] module"] pub type CLK_PERI_SELECTED = crate::Reg; -#[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot). - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."] +#[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot)."] pub mod clk_peri_selected; #[doc = "CLK_USB_CTRL (rw) register accessor: Clock control, can be changed on-the-fly (except for auxsrc) @@ -524,16 +511,14 @@ module"] pub type CLK_USB_DIV = crate::Reg; #[doc = "Clock divisor, can be changed on-the-fly"] pub mod clk_usb_div; -#[doc = "CLK_USB_SELECTED (r) register accessor: Indicates which SRC is currently selected by the glitchless mux (one-hot). - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. +#[doc = "CLK_USB_SELECTED (rw) register accessor: Indicates which SRC is currently selected by the glitchless mux (one-hot). -You can [`read`](crate::generic::Reg::read) this register and get [`clk_usb_selected::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`clk_usb_selected::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_usb_selected::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@clk_usb_selected`] module"] pub type CLK_USB_SELECTED = crate::Reg; -#[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot). - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."] +#[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot)."] pub mod clk_usb_selected; #[doc = "CLK_ADC_CTRL (rw) register accessor: Clock control, can be changed on-the-fly (except for auxsrc) @@ -553,16 +538,14 @@ module"] pub type CLK_ADC_DIV = crate::Reg; #[doc = "Clock divisor, can be changed on-the-fly"] pub mod clk_adc_div; -#[doc = "CLK_ADC_SELECTED (r) register accessor: Indicates which SRC is currently selected by the glitchless mux (one-hot). - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. +#[doc = "CLK_ADC_SELECTED (rw) register accessor: Indicates which SRC is currently selected by the glitchless mux (one-hot). -You can [`read`](crate::generic::Reg::read) this register and get [`clk_adc_selected::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`clk_adc_selected::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_adc_selected::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@clk_adc_selected`] module"] pub type CLK_ADC_SELECTED = crate::Reg; -#[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot). - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."] +#[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot)."] pub mod clk_adc_selected; #[doc = "CLK_RTC_CTRL (rw) register accessor: Clock control, can be changed on-the-fly (except for auxsrc) @@ -582,16 +565,14 @@ module"] pub type CLK_RTC_DIV = crate::Reg; #[doc = "Clock divisor, can be changed on-the-fly"] pub mod clk_rtc_div; -#[doc = "CLK_RTC_SELECTED (r) register accessor: Indicates which SRC is currently selected by the glitchless mux (one-hot). - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. +#[doc = "CLK_RTC_SELECTED (rw) register accessor: Indicates which SRC is currently selected by the glitchless mux (one-hot). -You can [`read`](crate::generic::Reg::read) this register and get [`clk_rtc_selected::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`clk_rtc_selected::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_rtc_selected::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@clk_rtc_selected`] module"] pub type CLK_RTC_SELECTED = crate::Reg; -#[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot). - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."] +#[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot)."] pub mod clk_rtc_selected; #[doc = "CLK_SYS_RESUS_CTRL (rw) register accessor: @@ -602,9 +583,9 @@ module"] pub type CLK_SYS_RESUS_CTRL = crate::Reg; #[doc = ""] pub mod clk_sys_resus_ctrl; -#[doc = "CLK_SYS_RESUS_STATUS (r) register accessor: +#[doc = "CLK_SYS_RESUS_STATUS (rw) register accessor: -You can [`read`](crate::generic::Reg::read) this register and get [`clk_sys_resus_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`clk_sys_resus_status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_sys_resus_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@clk_sys_resus_status`] module"] @@ -638,51 +619,45 @@ module"] pub type FC0_MAX_KHZ = crate::Reg; #[doc = "Maximum pass frequency in kHz. This is optional. Set to 0x1ffffff if you are not using the pass/fail flags"] pub mod fc0_max_khz; -#[doc = "FC0_DELAY (rw) register accessor: Delays the start of frequency counting to allow the mux to settle - Delay is measured in multiples of the reference clock period +#[doc = "FC0_DELAY (rw) register accessor: Delays the start of frequency counting to allow the mux to settle Delay is measured in multiples of the reference clock period You can [`read`](crate::generic::Reg::read) this register and get [`fc0_delay::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fc0_delay::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@fc0_delay`] module"] pub type FC0_DELAY = crate::Reg; -#[doc = "Delays the start of frequency counting to allow the mux to settle - Delay is measured in multiples of the reference clock period"] +#[doc = "Delays the start of frequency counting to allow the mux to settle Delay is measured in multiples of the reference clock period"] pub mod fc0_delay; -#[doc = "FC0_INTERVAL (rw) register accessor: The test interval is 0.98us * 2**interval, but let's call it 1us * 2**interval - The default gives a test interval of 250us +#[doc = "FC0_INTERVAL (rw) register accessor: The test interval is 0.98us * 2**interval, but let's call it 1us * 2**interval The default gives a test interval of 250us You can [`read`](crate::generic::Reg::read) this register and get [`fc0_interval::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fc0_interval::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@fc0_interval`] module"] pub type FC0_INTERVAL = crate::Reg; -#[doc = "The test interval is 0.98us * 2**interval, but let's call it 1us * 2**interval - The default gives a test interval of 250us"] +#[doc = "The test interval is 0.98us * 2**interval, but let's call it 1us * 2**interval The default gives a test interval of 250us"] pub mod fc0_interval; -#[doc = "FC0_SRC (rw) register accessor: Clock sent to frequency counter, set to 0 when not required - Writing to this register initiates the frequency count +#[doc = "FC0_SRC (rw) register accessor: Clock sent to frequency counter, set to 0 when not required Writing to this register initiates the frequency count You can [`read`](crate::generic::Reg::read) this register and get [`fc0_src::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fc0_src::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@fc0_src`] module"] pub type FC0_SRC = crate::Reg; -#[doc = "Clock sent to frequency counter, set to 0 when not required - Writing to this register initiates the frequency count"] +#[doc = "Clock sent to frequency counter, set to 0 when not required Writing to this register initiates the frequency count"] pub mod fc0_src; -#[doc = "FC0_STATUS (r) register accessor: Frequency counter status +#[doc = "FC0_STATUS (rw) register accessor: Frequency counter status -You can [`read`](crate::generic::Reg::read) this register and get [`fc0_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`fc0_status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fc0_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@fc0_status`] module"] pub type FC0_STATUS = crate::Reg; #[doc = "Frequency counter status"] pub mod fc0_status; -#[doc = "FC0_RESULT (r) register accessor: Result of frequency measurement, only valid when status_done=1 +#[doc = "FC0_RESULT (rw) register accessor: Result of frequency measurement, only valid when status_done=1 -You can [`read`](crate::generic::Reg::read) this register and get [`fc0_result::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`fc0_result::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fc0_result::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@fc0_result`] module"] @@ -725,27 +700,27 @@ module"] pub type SLEEP_EN1 = crate::Reg; #[doc = "enable clock in sleep mode"] pub mod sleep_en1; -#[doc = "ENABLED0 (r) register accessor: indicates the state of the clock enable +#[doc = "ENABLED0 (rw) register accessor: indicates the state of the clock enable -You can [`read`](crate::generic::Reg::read) this register and get [`enabled0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`enabled0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enabled0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@enabled0`] module"] pub type ENABLED0 = crate::Reg; #[doc = "indicates the state of the clock enable"] pub mod enabled0; -#[doc = "ENABLED1 (r) register accessor: indicates the state of the clock enable +#[doc = "ENABLED1 (rw) register accessor: indicates the state of the clock enable -You can [`read`](crate::generic::Reg::read) this register and get [`enabled1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`enabled1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enabled1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@enabled1`] module"] pub type ENABLED1 = crate::Reg; #[doc = "indicates the state of the clock enable"] pub mod enabled1; -#[doc = "INTR (r) register accessor: Raw Interrupts +#[doc = "INTR (rw) register accessor: Raw Interrupts -You can [`read`](crate::generic::Reg::read) this register and get [`intr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`intr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@intr`] module"] @@ -770,9 +745,9 @@ module"] pub type INTF = crate::Reg; #[doc = "Interrupt Force"] pub mod intf; -#[doc = "INTS (r) register accessor: Interrupt status after masking & forcing +#[doc = "INTS (rw) register accessor: Interrupt status after masking & forcing -You can [`read`](crate::generic::Reg::read) this register and get [`ints::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`ints::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ints::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@ints`] module"] diff --git a/src/clocks/clk_adc_ctrl.rs b/src/clocks/clk_adc_ctrl.rs index b22f652f0..1f817f803 100644 --- a/src/clocks/clk_adc_ctrl.rs +++ b/src/clocks/clk_adc_ctrl.rs @@ -123,17 +123,13 @@ pub type KILL_W<'a, REG> = crate::BitWriter<'a, REG>; pub type ENABLE_R = crate::BitReader; #[doc = "Field `ENABLE` writer - Starts and stops the clock generator cleanly"] pub type ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `PHASE` reader - This delays the enable signal by up to 3 cycles of the input clock - This must be set before the clock is enabled to have any effect"] +#[doc = "Field `PHASE` reader - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] pub type PHASE_R = crate::FieldReader; -#[doc = "Field `PHASE` writer - This delays the enable signal by up to 3 cycles of the input clock - This must be set before the clock is enabled to have any effect"] +#[doc = "Field `PHASE` writer - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] pub type PHASE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `NUDGE` reader - An edge on this signal shifts the phase of the output by 1 cycle of the input clock - This can be done at any time"] +#[doc = "Field `NUDGE` reader - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] pub type NUDGE_R = crate::BitReader; -#[doc = "Field `NUDGE` writer - An edge on this signal shifts the phase of the output by 1 cycle of the input clock - This can be done at any time"] +#[doc = "Field `NUDGE` writer - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] pub type NUDGE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 5:7 - Selects the auxiliary clock source, will glitch when switching"] @@ -151,14 +147,12 @@ impl R { pub fn enable(&self) -> ENABLE_R { ENABLE_R::new(((self.bits >> 11) & 1) != 0) } - #[doc = "Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock - This must be set before the clock is enabled to have any effect"] + #[doc = "Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] #[inline(always)] pub fn phase(&self) -> PHASE_R { PHASE_R::new(((self.bits >> 16) & 3) as u8) } - #[doc = "Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock - This can be done at any time"] + #[doc = "Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] #[inline(always)] pub fn nudge(&self) -> NUDGE_R { NUDGE_R::new(((self.bits >> 20) & 1) != 0) @@ -183,15 +177,13 @@ impl W { pub fn enable(&mut self) -> ENABLE_W { ENABLE_W::new(self, 11) } - #[doc = "Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock - This must be set before the clock is enabled to have any effect"] + #[doc = "Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] #[inline(always)] #[must_use] pub fn phase(&mut self) -> PHASE_W { PHASE_W::new(self, 16) } - #[doc = "Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock - This can be done at any time"] + #[doc = "Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] #[inline(always)] #[must_use] pub fn nudge(&mut self) -> NUDGE_W { diff --git a/src/clocks/clk_adc_selected.rs b/src/clocks/clk_adc_selected.rs index d3b7133a4..5cef8e802 100644 --- a/src/clocks/clk_adc_selected.rs +++ b/src/clocks/clk_adc_selected.rs @@ -1,25 +1,32 @@ #[doc = "Register `CLK_ADC_SELECTED` reader"] pub type R = crate::R; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) - } -} -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +#[doc = "Register `CLK_ADC_SELECTED` writer"] +pub type W = crate::W; +#[doc = "Field `CLK_ADC_SELECTED` reader - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."] +pub type CLK_ADC_SELECTED_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."] + #[inline(always)] + pub fn clk_adc_selected(&self) -> CLK_ADC_SELECTED_R { + CLK_ADC_SELECTED_R::new(self.bits) } } +impl W {} #[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot). - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. -You can [`read`](crate::generic::Reg::read) this register and get [`clk_adc_selected::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`clk_adc_selected::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_adc_selected::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLK_ADC_SELECTED_SPEC; impl crate::RegisterSpec for CLK_ADC_SELECTED_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`clk_adc_selected::R`](R) reader structure"] impl crate::Readable for CLK_ADC_SELECTED_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk_adc_selected::W`](W) writer structure"] +impl crate::Writable for CLK_ADC_SELECTED_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets CLK_ADC_SELECTED to value 0x01"] impl crate::Resettable for CLK_ADC_SELECTED_SPEC { const RESET_VALUE: u32 = 0x01; diff --git a/src/clocks/clk_gpout0_ctrl.rs b/src/clocks/clk_gpout0_ctrl.rs index 4edce962e..20c78fdba 100644 --- a/src/clocks/clk_gpout0_ctrl.rs +++ b/src/clocks/clk_gpout0_ctrl.rs @@ -192,17 +192,13 @@ pub type ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; pub type DC50_R = crate::BitReader; #[doc = "Field `DC50` writer - Enables duty cycle correction for odd divisors"] pub type DC50_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `PHASE` reader - This delays the enable signal by up to 3 cycles of the input clock - This must be set before the clock is enabled to have any effect"] +#[doc = "Field `PHASE` reader - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] pub type PHASE_R = crate::FieldReader; -#[doc = "Field `PHASE` writer - This delays the enable signal by up to 3 cycles of the input clock - This must be set before the clock is enabled to have any effect"] +#[doc = "Field `PHASE` writer - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] pub type PHASE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `NUDGE` reader - An edge on this signal shifts the phase of the output by 1 cycle of the input clock - This can be done at any time"] +#[doc = "Field `NUDGE` reader - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] pub type NUDGE_R = crate::BitReader; -#[doc = "Field `NUDGE` writer - An edge on this signal shifts the phase of the output by 1 cycle of the input clock - This can be done at any time"] +#[doc = "Field `NUDGE` writer - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] pub type NUDGE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 5:8 - Selects the auxiliary clock source, will glitch when switching"] @@ -225,14 +221,12 @@ impl R { pub fn dc50(&self) -> DC50_R { DC50_R::new(((self.bits >> 12) & 1) != 0) } - #[doc = "Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock - This must be set before the clock is enabled to have any effect"] + #[doc = "Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] #[inline(always)] pub fn phase(&self) -> PHASE_R { PHASE_R::new(((self.bits >> 16) & 3) as u8) } - #[doc = "Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock - This can be done at any time"] + #[doc = "Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] #[inline(always)] pub fn nudge(&self) -> NUDGE_R { NUDGE_R::new(((self.bits >> 20) & 1) != 0) @@ -263,15 +257,13 @@ impl W { pub fn dc50(&mut self) -> DC50_W { DC50_W::new(self, 12) } - #[doc = "Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock - This must be set before the clock is enabled to have any effect"] + #[doc = "Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] #[inline(always)] #[must_use] pub fn phase(&mut self) -> PHASE_W { PHASE_W::new(self, 16) } - #[doc = "Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock - This can be done at any time"] + #[doc = "Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] #[inline(always)] #[must_use] pub fn nudge(&mut self) -> NUDGE_W { diff --git a/src/clocks/clk_gpout0_selected.rs b/src/clocks/clk_gpout0_selected.rs index 461264479..9e18043fa 100644 --- a/src/clocks/clk_gpout0_selected.rs +++ b/src/clocks/clk_gpout0_selected.rs @@ -1,25 +1,32 @@ #[doc = "Register `CLK_GPOUT0_SELECTED` reader"] pub type R = crate::R; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) - } -} -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +#[doc = "Register `CLK_GPOUT0_SELECTED` writer"] +pub type W = crate::W; +#[doc = "Field `CLK_GPOUT0_SELECTED` reader - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."] +pub type CLK_GPOUT0_SELECTED_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."] + #[inline(always)] + pub fn clk_gpout0_selected(&self) -> CLK_GPOUT0_SELECTED_R { + CLK_GPOUT0_SELECTED_R::new(self.bits) } } +impl W {} #[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot). - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. -You can [`read`](crate::generic::Reg::read) this register and get [`clk_gpout0_selected::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`clk_gpout0_selected::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gpout0_selected::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLK_GPOUT0_SELECTED_SPEC; impl crate::RegisterSpec for CLK_GPOUT0_SELECTED_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`clk_gpout0_selected::R`](R) reader structure"] impl crate::Readable for CLK_GPOUT0_SELECTED_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk_gpout0_selected::W`](W) writer structure"] +impl crate::Writable for CLK_GPOUT0_SELECTED_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets CLK_GPOUT0_SELECTED to value 0x01"] impl crate::Resettable for CLK_GPOUT0_SELECTED_SPEC { const RESET_VALUE: u32 = 0x01; diff --git a/src/clocks/clk_gpout1_ctrl.rs b/src/clocks/clk_gpout1_ctrl.rs index eab13e0a1..5429c9072 100644 --- a/src/clocks/clk_gpout1_ctrl.rs +++ b/src/clocks/clk_gpout1_ctrl.rs @@ -192,17 +192,13 @@ pub type ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; pub type DC50_R = crate::BitReader; #[doc = "Field `DC50` writer - Enables duty cycle correction for odd divisors"] pub type DC50_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `PHASE` reader - This delays the enable signal by up to 3 cycles of the input clock - This must be set before the clock is enabled to have any effect"] +#[doc = "Field `PHASE` reader - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] pub type PHASE_R = crate::FieldReader; -#[doc = "Field `PHASE` writer - This delays the enable signal by up to 3 cycles of the input clock - This must be set before the clock is enabled to have any effect"] +#[doc = "Field `PHASE` writer - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] pub type PHASE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `NUDGE` reader - An edge on this signal shifts the phase of the output by 1 cycle of the input clock - This can be done at any time"] +#[doc = "Field `NUDGE` reader - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] pub type NUDGE_R = crate::BitReader; -#[doc = "Field `NUDGE` writer - An edge on this signal shifts the phase of the output by 1 cycle of the input clock - This can be done at any time"] +#[doc = "Field `NUDGE` writer - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] pub type NUDGE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 5:8 - Selects the auxiliary clock source, will glitch when switching"] @@ -225,14 +221,12 @@ impl R { pub fn dc50(&self) -> DC50_R { DC50_R::new(((self.bits >> 12) & 1) != 0) } - #[doc = "Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock - This must be set before the clock is enabled to have any effect"] + #[doc = "Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] #[inline(always)] pub fn phase(&self) -> PHASE_R { PHASE_R::new(((self.bits >> 16) & 3) as u8) } - #[doc = "Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock - This can be done at any time"] + #[doc = "Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] #[inline(always)] pub fn nudge(&self) -> NUDGE_R { NUDGE_R::new(((self.bits >> 20) & 1) != 0) @@ -263,15 +257,13 @@ impl W { pub fn dc50(&mut self) -> DC50_W { DC50_W::new(self, 12) } - #[doc = "Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock - This must be set before the clock is enabled to have any effect"] + #[doc = "Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] #[inline(always)] #[must_use] pub fn phase(&mut self) -> PHASE_W { PHASE_W::new(self, 16) } - #[doc = "Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock - This can be done at any time"] + #[doc = "Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] #[inline(always)] #[must_use] pub fn nudge(&mut self) -> NUDGE_W { diff --git a/src/clocks/clk_gpout1_selected.rs b/src/clocks/clk_gpout1_selected.rs index 2735720a5..b21730f21 100644 --- a/src/clocks/clk_gpout1_selected.rs +++ b/src/clocks/clk_gpout1_selected.rs @@ -1,25 +1,32 @@ #[doc = "Register `CLK_GPOUT1_SELECTED` reader"] pub type R = crate::R; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) - } -} -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +#[doc = "Register `CLK_GPOUT1_SELECTED` writer"] +pub type W = crate::W; +#[doc = "Field `CLK_GPOUT1_SELECTED` reader - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."] +pub type CLK_GPOUT1_SELECTED_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."] + #[inline(always)] + pub fn clk_gpout1_selected(&self) -> CLK_GPOUT1_SELECTED_R { + CLK_GPOUT1_SELECTED_R::new(self.bits) } } +impl W {} #[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot). - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. -You can [`read`](crate::generic::Reg::read) this register and get [`clk_gpout1_selected::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`clk_gpout1_selected::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gpout1_selected::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLK_GPOUT1_SELECTED_SPEC; impl crate::RegisterSpec for CLK_GPOUT1_SELECTED_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`clk_gpout1_selected::R`](R) reader structure"] impl crate::Readable for CLK_GPOUT1_SELECTED_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk_gpout1_selected::W`](W) writer structure"] +impl crate::Writable for CLK_GPOUT1_SELECTED_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets CLK_GPOUT1_SELECTED to value 0x01"] impl crate::Resettable for CLK_GPOUT1_SELECTED_SPEC { const RESET_VALUE: u32 = 0x01; diff --git a/src/clocks/clk_gpout2_ctrl.rs b/src/clocks/clk_gpout2_ctrl.rs index 25badf597..c4be48666 100644 --- a/src/clocks/clk_gpout2_ctrl.rs +++ b/src/clocks/clk_gpout2_ctrl.rs @@ -192,17 +192,13 @@ pub type ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; pub type DC50_R = crate::BitReader; #[doc = "Field `DC50` writer - Enables duty cycle correction for odd divisors"] pub type DC50_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `PHASE` reader - This delays the enable signal by up to 3 cycles of the input clock - This must be set before the clock is enabled to have any effect"] +#[doc = "Field `PHASE` reader - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] pub type PHASE_R = crate::FieldReader; -#[doc = "Field `PHASE` writer - This delays the enable signal by up to 3 cycles of the input clock - This must be set before the clock is enabled to have any effect"] +#[doc = "Field `PHASE` writer - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] pub type PHASE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `NUDGE` reader - An edge on this signal shifts the phase of the output by 1 cycle of the input clock - This can be done at any time"] +#[doc = "Field `NUDGE` reader - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] pub type NUDGE_R = crate::BitReader; -#[doc = "Field `NUDGE` writer - An edge on this signal shifts the phase of the output by 1 cycle of the input clock - This can be done at any time"] +#[doc = "Field `NUDGE` writer - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] pub type NUDGE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 5:8 - Selects the auxiliary clock source, will glitch when switching"] @@ -225,14 +221,12 @@ impl R { pub fn dc50(&self) -> DC50_R { DC50_R::new(((self.bits >> 12) & 1) != 0) } - #[doc = "Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock - This must be set before the clock is enabled to have any effect"] + #[doc = "Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] #[inline(always)] pub fn phase(&self) -> PHASE_R { PHASE_R::new(((self.bits >> 16) & 3) as u8) } - #[doc = "Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock - This can be done at any time"] + #[doc = "Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] #[inline(always)] pub fn nudge(&self) -> NUDGE_R { NUDGE_R::new(((self.bits >> 20) & 1) != 0) @@ -263,15 +257,13 @@ impl W { pub fn dc50(&mut self) -> DC50_W { DC50_W::new(self, 12) } - #[doc = "Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock - This must be set before the clock is enabled to have any effect"] + #[doc = "Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] #[inline(always)] #[must_use] pub fn phase(&mut self) -> PHASE_W { PHASE_W::new(self, 16) } - #[doc = "Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock - This can be done at any time"] + #[doc = "Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] #[inline(always)] #[must_use] pub fn nudge(&mut self) -> NUDGE_W { diff --git a/src/clocks/clk_gpout2_selected.rs b/src/clocks/clk_gpout2_selected.rs index a479a11e8..125886324 100644 --- a/src/clocks/clk_gpout2_selected.rs +++ b/src/clocks/clk_gpout2_selected.rs @@ -1,25 +1,32 @@ #[doc = "Register `CLK_GPOUT2_SELECTED` reader"] pub type R = crate::R; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) - } -} -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +#[doc = "Register `CLK_GPOUT2_SELECTED` writer"] +pub type W = crate::W; +#[doc = "Field `CLK_GPOUT2_SELECTED` reader - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."] +pub type CLK_GPOUT2_SELECTED_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."] + #[inline(always)] + pub fn clk_gpout2_selected(&self) -> CLK_GPOUT2_SELECTED_R { + CLK_GPOUT2_SELECTED_R::new(self.bits) } } +impl W {} #[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot). - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. -You can [`read`](crate::generic::Reg::read) this register and get [`clk_gpout2_selected::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`clk_gpout2_selected::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gpout2_selected::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLK_GPOUT2_SELECTED_SPEC; impl crate::RegisterSpec for CLK_GPOUT2_SELECTED_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`clk_gpout2_selected::R`](R) reader structure"] impl crate::Readable for CLK_GPOUT2_SELECTED_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk_gpout2_selected::W`](W) writer structure"] +impl crate::Writable for CLK_GPOUT2_SELECTED_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets CLK_GPOUT2_SELECTED to value 0x01"] impl crate::Resettable for CLK_GPOUT2_SELECTED_SPEC { const RESET_VALUE: u32 = 0x01; diff --git a/src/clocks/clk_gpout3_ctrl.rs b/src/clocks/clk_gpout3_ctrl.rs index b5b5ed98d..c91adb542 100644 --- a/src/clocks/clk_gpout3_ctrl.rs +++ b/src/clocks/clk_gpout3_ctrl.rs @@ -192,17 +192,13 @@ pub type ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; pub type DC50_R = crate::BitReader; #[doc = "Field `DC50` writer - Enables duty cycle correction for odd divisors"] pub type DC50_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `PHASE` reader - This delays the enable signal by up to 3 cycles of the input clock - This must be set before the clock is enabled to have any effect"] +#[doc = "Field `PHASE` reader - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] pub type PHASE_R = crate::FieldReader; -#[doc = "Field `PHASE` writer - This delays the enable signal by up to 3 cycles of the input clock - This must be set before the clock is enabled to have any effect"] +#[doc = "Field `PHASE` writer - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] pub type PHASE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `NUDGE` reader - An edge on this signal shifts the phase of the output by 1 cycle of the input clock - This can be done at any time"] +#[doc = "Field `NUDGE` reader - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] pub type NUDGE_R = crate::BitReader; -#[doc = "Field `NUDGE` writer - An edge on this signal shifts the phase of the output by 1 cycle of the input clock - This can be done at any time"] +#[doc = "Field `NUDGE` writer - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] pub type NUDGE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 5:8 - Selects the auxiliary clock source, will glitch when switching"] @@ -225,14 +221,12 @@ impl R { pub fn dc50(&self) -> DC50_R { DC50_R::new(((self.bits >> 12) & 1) != 0) } - #[doc = "Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock - This must be set before the clock is enabled to have any effect"] + #[doc = "Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] #[inline(always)] pub fn phase(&self) -> PHASE_R { PHASE_R::new(((self.bits >> 16) & 3) as u8) } - #[doc = "Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock - This can be done at any time"] + #[doc = "Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] #[inline(always)] pub fn nudge(&self) -> NUDGE_R { NUDGE_R::new(((self.bits >> 20) & 1) != 0) @@ -263,15 +257,13 @@ impl W { pub fn dc50(&mut self) -> DC50_W { DC50_W::new(self, 12) } - #[doc = "Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock - This must be set before the clock is enabled to have any effect"] + #[doc = "Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] #[inline(always)] #[must_use] pub fn phase(&mut self) -> PHASE_W { PHASE_W::new(self, 16) } - #[doc = "Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock - This can be done at any time"] + #[doc = "Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] #[inline(always)] #[must_use] pub fn nudge(&mut self) -> NUDGE_W { diff --git a/src/clocks/clk_gpout3_selected.rs b/src/clocks/clk_gpout3_selected.rs index 7eddbc580..3160a47fd 100644 --- a/src/clocks/clk_gpout3_selected.rs +++ b/src/clocks/clk_gpout3_selected.rs @@ -1,25 +1,32 @@ #[doc = "Register `CLK_GPOUT3_SELECTED` reader"] pub type R = crate::R; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) - } -} -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +#[doc = "Register `CLK_GPOUT3_SELECTED` writer"] +pub type W = crate::W; +#[doc = "Field `CLK_GPOUT3_SELECTED` reader - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."] +pub type CLK_GPOUT3_SELECTED_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."] + #[inline(always)] + pub fn clk_gpout3_selected(&self) -> CLK_GPOUT3_SELECTED_R { + CLK_GPOUT3_SELECTED_R::new(self.bits) } } +impl W {} #[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot). - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. -You can [`read`](crate::generic::Reg::read) this register and get [`clk_gpout3_selected::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`clk_gpout3_selected::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gpout3_selected::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLK_GPOUT3_SELECTED_SPEC; impl crate::RegisterSpec for CLK_GPOUT3_SELECTED_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`clk_gpout3_selected::R`](R) reader structure"] impl crate::Readable for CLK_GPOUT3_SELECTED_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk_gpout3_selected::W`](W) writer structure"] +impl crate::Writable for CLK_GPOUT3_SELECTED_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets CLK_GPOUT3_SELECTED to value 0x01"] impl crate::Resettable for CLK_GPOUT3_SELECTED_SPEC { const RESET_VALUE: u32 = 0x01; diff --git a/src/clocks/clk_peri_div.rs b/src/clocks/clk_peri_div.rs new file mode 100644 index 000000000..3d3b61f56 --- /dev/null +++ b/src/clocks/clk_peri_div.rs @@ -0,0 +1,57 @@ +#[doc = "Register `CLK_PERI_DIV` reader"] +pub type R = crate::R; +#[doc = "Register `CLK_PERI_DIV` writer"] +pub type W = crate::W; +#[doc = "Field `FRAC` reader - Fractional component of the divisor"] +pub type FRAC_R = crate::FieldReader; +#[doc = "Field `FRAC` writer - Fractional component of the divisor"] +pub type FRAC_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `INT` reader - Integer component of the divisor, 0 -> divide by 2^16"] +pub type INT_R = crate::FieldReader; +#[doc = "Field `INT` writer - Integer component of the divisor, 0 -> divide by 2^16"] +pub type INT_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; +impl R { + #[doc = "Bits 0:7 - Fractional component of the divisor"] + #[inline(always)] + pub fn frac(&self) -> FRAC_R { + FRAC_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:31 - Integer component of the divisor, 0 -> divide by 2^16"] + #[inline(always)] + pub fn int(&self) -> INT_R { + INT_R::new((self.bits >> 8) & 0x00ff_ffff) + } +} +impl W { + #[doc = "Bits 0:7 - Fractional component of the divisor"] + #[inline(always)] + #[must_use] + pub fn frac(&mut self) -> FRAC_W { + FRAC_W::new(self, 0) + } + #[doc = "Bits 8:31 - Integer component of the divisor, 0 -> divide by 2^16"] + #[inline(always)] + #[must_use] + pub fn int(&mut self) -> INT_W { + INT_W::new(self, 8) + } +} +#[doc = "Clock divisor, can be changed on-the-fly + +You can [`read`](crate::generic::Reg::read) this register and get [`clk_peri_div::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_peri_div::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CLK_PERI_DIV_SPEC; +impl crate::RegisterSpec for CLK_PERI_DIV_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`clk_peri_div::R`](R) reader structure"] +impl crate::Readable for CLK_PERI_DIV_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk_peri_div::W`](W) writer structure"] +impl crate::Writable for CLK_PERI_DIV_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CLK_PERI_DIV to value 0x0100"] +impl crate::Resettable for CLK_PERI_DIV_SPEC { + const RESET_VALUE: u32 = 0x0100; +} diff --git a/src/clocks/clk_peri_selected.rs b/src/clocks/clk_peri_selected.rs index 414c9b912..e11c78b2c 100644 --- a/src/clocks/clk_peri_selected.rs +++ b/src/clocks/clk_peri_selected.rs @@ -1,25 +1,32 @@ #[doc = "Register `CLK_PERI_SELECTED` reader"] pub type R = crate::R; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) - } -} -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +#[doc = "Register `CLK_PERI_SELECTED` writer"] +pub type W = crate::W; +#[doc = "Field `CLK_PERI_SELECTED` reader - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."] +pub type CLK_PERI_SELECTED_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."] + #[inline(always)] + pub fn clk_peri_selected(&self) -> CLK_PERI_SELECTED_R { + CLK_PERI_SELECTED_R::new(self.bits) } } +impl W {} #[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot). - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. -You can [`read`](crate::generic::Reg::read) this register and get [`clk_peri_selected::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`clk_peri_selected::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_peri_selected::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLK_PERI_SELECTED_SPEC; impl crate::RegisterSpec for CLK_PERI_SELECTED_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`clk_peri_selected::R`](R) reader structure"] impl crate::Readable for CLK_PERI_SELECTED_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk_peri_selected::W`](W) writer structure"] +impl crate::Writable for CLK_PERI_SELECTED_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets CLK_PERI_SELECTED to value 0x01"] impl crate::Resettable for CLK_PERI_SELECTED_SPEC { const RESET_VALUE: u32 = 0x01; diff --git a/src/clocks/clk_ref_selected.rs b/src/clocks/clk_ref_selected.rs index e9f9a7ea6..303f70084 100644 --- a/src/clocks/clk_ref_selected.rs +++ b/src/clocks/clk_ref_selected.rs @@ -1,25 +1,32 @@ #[doc = "Register `CLK_REF_SELECTED` reader"] pub type R = crate::R; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) - } -} -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +#[doc = "Register `CLK_REF_SELECTED` writer"] +pub type W = crate::W; +#[doc = "Field `CLK_REF_SELECTED` reader - The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s."] +pub type CLK_REF_SELECTED_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s."] + #[inline(always)] + pub fn clk_ref_selected(&self) -> CLK_REF_SELECTED_R { + CLK_REF_SELECTED_R::new(self.bits) } } +impl W {} #[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot). - The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s. -You can [`read`](crate::generic::Reg::read) this register and get [`clk_ref_selected::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`clk_ref_selected::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_ref_selected::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLK_REF_SELECTED_SPEC; impl crate::RegisterSpec for CLK_REF_SELECTED_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`clk_ref_selected::R`](R) reader structure"] impl crate::Readable for CLK_REF_SELECTED_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk_ref_selected::W`](W) writer structure"] +impl crate::Writable for CLK_REF_SELECTED_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets CLK_REF_SELECTED to value 0x01"] impl crate::Resettable for CLK_REF_SELECTED_SPEC { const RESET_VALUE: u32 = 0x01; diff --git a/src/clocks/clk_rtc_ctrl.rs b/src/clocks/clk_rtc_ctrl.rs index 6adf1f9a7..30a649f5c 100644 --- a/src/clocks/clk_rtc_ctrl.rs +++ b/src/clocks/clk_rtc_ctrl.rs @@ -123,17 +123,13 @@ pub type KILL_W<'a, REG> = crate::BitWriter<'a, REG>; pub type ENABLE_R = crate::BitReader; #[doc = "Field `ENABLE` writer - Starts and stops the clock generator cleanly"] pub type ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `PHASE` reader - This delays the enable signal by up to 3 cycles of the input clock - This must be set before the clock is enabled to have any effect"] +#[doc = "Field `PHASE` reader - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] pub type PHASE_R = crate::FieldReader; -#[doc = "Field `PHASE` writer - This delays the enable signal by up to 3 cycles of the input clock - This must be set before the clock is enabled to have any effect"] +#[doc = "Field `PHASE` writer - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] pub type PHASE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `NUDGE` reader - An edge on this signal shifts the phase of the output by 1 cycle of the input clock - This can be done at any time"] +#[doc = "Field `NUDGE` reader - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] pub type NUDGE_R = crate::BitReader; -#[doc = "Field `NUDGE` writer - An edge on this signal shifts the phase of the output by 1 cycle of the input clock - This can be done at any time"] +#[doc = "Field `NUDGE` writer - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] pub type NUDGE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 5:7 - Selects the auxiliary clock source, will glitch when switching"] @@ -151,14 +147,12 @@ impl R { pub fn enable(&self) -> ENABLE_R { ENABLE_R::new(((self.bits >> 11) & 1) != 0) } - #[doc = "Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock - This must be set before the clock is enabled to have any effect"] + #[doc = "Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] #[inline(always)] pub fn phase(&self) -> PHASE_R { PHASE_R::new(((self.bits >> 16) & 3) as u8) } - #[doc = "Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock - This can be done at any time"] + #[doc = "Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] #[inline(always)] pub fn nudge(&self) -> NUDGE_R { NUDGE_R::new(((self.bits >> 20) & 1) != 0) @@ -183,15 +177,13 @@ impl W { pub fn enable(&mut self) -> ENABLE_W { ENABLE_W::new(self, 11) } - #[doc = "Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock - This must be set before the clock is enabled to have any effect"] + #[doc = "Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] #[inline(always)] #[must_use] pub fn phase(&mut self) -> PHASE_W { PHASE_W::new(self, 16) } - #[doc = "Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock - This can be done at any time"] + #[doc = "Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] #[inline(always)] #[must_use] pub fn nudge(&mut self) -> NUDGE_W { diff --git a/src/clocks/clk_rtc_selected.rs b/src/clocks/clk_rtc_selected.rs index b6d5dd9f0..5a07fc286 100644 --- a/src/clocks/clk_rtc_selected.rs +++ b/src/clocks/clk_rtc_selected.rs @@ -1,25 +1,32 @@ #[doc = "Register `CLK_RTC_SELECTED` reader"] pub type R = crate::R; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) - } -} -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +#[doc = "Register `CLK_RTC_SELECTED` writer"] +pub type W = crate::W; +#[doc = "Field `CLK_RTC_SELECTED` reader - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."] +pub type CLK_RTC_SELECTED_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."] + #[inline(always)] + pub fn clk_rtc_selected(&self) -> CLK_RTC_SELECTED_R { + CLK_RTC_SELECTED_R::new(self.bits) } } +impl W {} #[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot). - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. -You can [`read`](crate::generic::Reg::read) this register and get [`clk_rtc_selected::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`clk_rtc_selected::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_rtc_selected::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLK_RTC_SELECTED_SPEC; impl crate::RegisterSpec for CLK_RTC_SELECTED_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`clk_rtc_selected::R`](R) reader structure"] impl crate::Readable for CLK_RTC_SELECTED_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk_rtc_selected::W`](W) writer structure"] +impl crate::Writable for CLK_RTC_SELECTED_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets CLK_RTC_SELECTED to value 0x01"] impl crate::Resettable for CLK_RTC_SELECTED_SPEC { const RESET_VALUE: u32 = 0x01; diff --git a/src/clocks/clk_sys_resus_ctrl.rs b/src/clocks/clk_sys_resus_ctrl.rs index b1551c978..bddd995ec 100644 --- a/src/clocks/clk_sys_resus_ctrl.rs +++ b/src/clocks/clk_sys_resus_ctrl.rs @@ -2,11 +2,9 @@ pub type R = crate::R; #[doc = "Register `CLK_SYS_RESUS_CTRL` writer"] pub type W = crate::W; -#[doc = "Field `TIMEOUT` reader - This is expressed as a number of clk_ref cycles - and must be >= 2x clk_ref_freq/min_clk_tst_freq"] +#[doc = "Field `TIMEOUT` reader - This is expressed as a number of clk_ref cycles and must be >= 2x clk_ref_freq/min_clk_tst_freq"] pub type TIMEOUT_R = crate::FieldReader; -#[doc = "Field `TIMEOUT` writer - This is expressed as a number of clk_ref cycles - and must be >= 2x clk_ref_freq/min_clk_tst_freq"] +#[doc = "Field `TIMEOUT` writer - This is expressed as a number of clk_ref cycles and must be >= 2x clk_ref_freq/min_clk_tst_freq"] pub type TIMEOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; #[doc = "Field `ENABLE` reader - Enable resus"] pub type ENABLE_R = crate::BitReader; @@ -21,8 +19,7 @@ pub type CLEAR_R = crate::BitReader; #[doc = "Field `CLEAR` writer - For clearing the resus after the fault that triggered it has been corrected"] pub type CLEAR_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { - #[doc = "Bits 0:7 - This is expressed as a number of clk_ref cycles - and must be >= 2x clk_ref_freq/min_clk_tst_freq"] + #[doc = "Bits 0:7 - This is expressed as a number of clk_ref cycles and must be >= 2x clk_ref_freq/min_clk_tst_freq"] #[inline(always)] pub fn timeout(&self) -> TIMEOUT_R { TIMEOUT_R::new((self.bits & 0xff) as u8) @@ -44,8 +41,7 @@ impl R { } } impl W { - #[doc = "Bits 0:7 - This is expressed as a number of clk_ref cycles - and must be >= 2x clk_ref_freq/min_clk_tst_freq"] + #[doc = "Bits 0:7 - This is expressed as a number of clk_ref cycles and must be >= 2x clk_ref_freq/min_clk_tst_freq"] #[inline(always)] #[must_use] pub fn timeout(&mut self) -> TIMEOUT_W { diff --git a/src/clocks/clk_sys_resus_status.rs b/src/clocks/clk_sys_resus_status.rs index 90d4144e1..c1d864852 100644 --- a/src/clocks/clk_sys_resus_status.rs +++ b/src/clocks/clk_sys_resus_status.rs @@ -1,5 +1,7 @@ #[doc = "Register `CLK_SYS_RESUS_STATUS` reader"] pub type R = crate::R; +#[doc = "Register `CLK_SYS_RESUS_STATUS` writer"] +pub type W = crate::W; #[doc = "Field `RESUSSED` reader - Clock has been resuscitated, correct the error then send ctrl_clear=1"] pub type RESUSSED_R = crate::BitReader; impl R { @@ -9,15 +11,22 @@ impl R { RESUSSED_R::new((self.bits & 1) != 0) } } +impl W {} #[doc = " -You can [`read`](crate::generic::Reg::read) this register and get [`clk_sys_resus_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`clk_sys_resus_status::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_sys_resus_status::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLK_SYS_RESUS_STATUS_SPEC; impl crate::RegisterSpec for CLK_SYS_RESUS_STATUS_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`clk_sys_resus_status::R`](R) reader structure"] impl crate::Readable for CLK_SYS_RESUS_STATUS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk_sys_resus_status::W`](W) writer structure"] +impl crate::Writable for CLK_SYS_RESUS_STATUS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets CLK_SYS_RESUS_STATUS to value 0"] impl crate::Resettable for CLK_SYS_RESUS_STATUS_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/clocks/clk_sys_selected.rs b/src/clocks/clk_sys_selected.rs index 8002b6a02..b1a074f24 100644 --- a/src/clocks/clk_sys_selected.rs +++ b/src/clocks/clk_sys_selected.rs @@ -1,25 +1,32 @@ #[doc = "Register `CLK_SYS_SELECTED` reader"] pub type R = crate::R; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) - } -} -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +#[doc = "Register `CLK_SYS_SELECTED` writer"] +pub type W = crate::W; +#[doc = "Field `CLK_SYS_SELECTED` reader - The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s."] +pub type CLK_SYS_SELECTED_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s."] + #[inline(always)] + pub fn clk_sys_selected(&self) -> CLK_SYS_SELECTED_R { + CLK_SYS_SELECTED_R::new(self.bits) } } +impl W {} #[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot). - The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s. -You can [`read`](crate::generic::Reg::read) this register and get [`clk_sys_selected::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`clk_sys_selected::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_sys_selected::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLK_SYS_SELECTED_SPEC; impl crate::RegisterSpec for CLK_SYS_SELECTED_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`clk_sys_selected::R`](R) reader structure"] impl crate::Readable for CLK_SYS_SELECTED_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk_sys_selected::W`](W) writer structure"] +impl crate::Writable for CLK_SYS_SELECTED_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets CLK_SYS_SELECTED to value 0x01"] impl crate::Resettable for CLK_SYS_SELECTED_SPEC { const RESET_VALUE: u32 = 0x01; diff --git a/src/clocks/clk_usb_ctrl.rs b/src/clocks/clk_usb_ctrl.rs index b67c9bbb3..527d3d4fb 100644 --- a/src/clocks/clk_usb_ctrl.rs +++ b/src/clocks/clk_usb_ctrl.rs @@ -123,17 +123,13 @@ pub type KILL_W<'a, REG> = crate::BitWriter<'a, REG>; pub type ENABLE_R = crate::BitReader; #[doc = "Field `ENABLE` writer - Starts and stops the clock generator cleanly"] pub type ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `PHASE` reader - This delays the enable signal by up to 3 cycles of the input clock - This must be set before the clock is enabled to have any effect"] +#[doc = "Field `PHASE` reader - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] pub type PHASE_R = crate::FieldReader; -#[doc = "Field `PHASE` writer - This delays the enable signal by up to 3 cycles of the input clock - This must be set before the clock is enabled to have any effect"] +#[doc = "Field `PHASE` writer - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] pub type PHASE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `NUDGE` reader - An edge on this signal shifts the phase of the output by 1 cycle of the input clock - This can be done at any time"] +#[doc = "Field `NUDGE` reader - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] pub type NUDGE_R = crate::BitReader; -#[doc = "Field `NUDGE` writer - An edge on this signal shifts the phase of the output by 1 cycle of the input clock - This can be done at any time"] +#[doc = "Field `NUDGE` writer - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] pub type NUDGE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 5:7 - Selects the auxiliary clock source, will glitch when switching"] @@ -151,14 +147,12 @@ impl R { pub fn enable(&self) -> ENABLE_R { ENABLE_R::new(((self.bits >> 11) & 1) != 0) } - #[doc = "Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock - This must be set before the clock is enabled to have any effect"] + #[doc = "Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] #[inline(always)] pub fn phase(&self) -> PHASE_R { PHASE_R::new(((self.bits >> 16) & 3) as u8) } - #[doc = "Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock - This can be done at any time"] + #[doc = "Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] #[inline(always)] pub fn nudge(&self) -> NUDGE_R { NUDGE_R::new(((self.bits >> 20) & 1) != 0) @@ -183,15 +177,13 @@ impl W { pub fn enable(&mut self) -> ENABLE_W { ENABLE_W::new(self, 11) } - #[doc = "Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock - This must be set before the clock is enabled to have any effect"] + #[doc = "Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] #[inline(always)] #[must_use] pub fn phase(&mut self) -> PHASE_W { PHASE_W::new(self, 16) } - #[doc = "Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock - This can be done at any time"] + #[doc = "Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] #[inline(always)] #[must_use] pub fn nudge(&mut self) -> NUDGE_W { diff --git a/src/clocks/clk_usb_selected.rs b/src/clocks/clk_usb_selected.rs index ade608791..0840e2078 100644 --- a/src/clocks/clk_usb_selected.rs +++ b/src/clocks/clk_usb_selected.rs @@ -1,25 +1,32 @@ #[doc = "Register `CLK_USB_SELECTED` reader"] pub type R = crate::R; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) - } -} -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +#[doc = "Register `CLK_USB_SELECTED` writer"] +pub type W = crate::W; +#[doc = "Field `CLK_USB_SELECTED` reader - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."] +pub type CLK_USB_SELECTED_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."] + #[inline(always)] + pub fn clk_usb_selected(&self) -> CLK_USB_SELECTED_R { + CLK_USB_SELECTED_R::new(self.bits) } } +impl W {} #[doc = "Indicates which SRC is currently selected by the glitchless mux (one-hot). - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. -You can [`read`](crate::generic::Reg::read) this register and get [`clk_usb_selected::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`clk_usb_selected::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_usb_selected::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLK_USB_SELECTED_SPEC; impl crate::RegisterSpec for CLK_USB_SELECTED_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`clk_usb_selected::R`](R) reader structure"] impl crate::Readable for CLK_USB_SELECTED_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk_usb_selected::W`](W) writer structure"] +impl crate::Writable for CLK_USB_SELECTED_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets CLK_USB_SELECTED to value 0x01"] impl crate::Resettable for CLK_USB_SELECTED_SPEC { const RESET_VALUE: u32 = 0x01; diff --git a/src/clocks/enabled0.rs b/src/clocks/enabled0.rs index cb44fc420..82288ea9b 100644 --- a/src/clocks/enabled0.rs +++ b/src/clocks/enabled0.rs @@ -1,68 +1,70 @@ #[doc = "Register `ENABLED0` reader"] pub type R = crate::R; -#[doc = "Field `clk_sys_clocks` reader - "] +#[doc = "Register `ENABLED0` writer"] +pub type W = crate::W; +#[doc = "Field `CLK_SYS_CLOCKS` reader - "] pub type CLK_SYS_CLOCKS_R = crate::BitReader; -#[doc = "Field `clk_adc_adc` reader - "] +#[doc = "Field `CLK_ADC_ADC` reader - "] pub type CLK_ADC_ADC_R = crate::BitReader; -#[doc = "Field `clk_sys_adc` reader - "] +#[doc = "Field `CLK_SYS_ADC` reader - "] pub type CLK_SYS_ADC_R = crate::BitReader; -#[doc = "Field `clk_sys_busctrl` reader - "] +#[doc = "Field `CLK_SYS_BUSCTRL` reader - "] pub type CLK_SYS_BUSCTRL_R = crate::BitReader; -#[doc = "Field `clk_sys_busfabric` reader - "] +#[doc = "Field `CLK_SYS_BUSFABRIC` reader - "] pub type CLK_SYS_BUSFABRIC_R = crate::BitReader; -#[doc = "Field `clk_sys_dma` reader - "] +#[doc = "Field `CLK_SYS_DMA` reader - "] pub type CLK_SYS_DMA_R = crate::BitReader; -#[doc = "Field `clk_sys_i2c0` reader - "] +#[doc = "Field `CLK_SYS_I2C0` reader - "] pub type CLK_SYS_I2C0_R = crate::BitReader; -#[doc = "Field `clk_sys_i2c1` reader - "] +#[doc = "Field `CLK_SYS_I2C1` reader - "] pub type CLK_SYS_I2C1_R = crate::BitReader; -#[doc = "Field `clk_sys_io` reader - "] +#[doc = "Field `CLK_SYS_IO` reader - "] pub type CLK_SYS_IO_R = crate::BitReader; -#[doc = "Field `clk_sys_jtag` reader - "] +#[doc = "Field `CLK_SYS_JTAG` reader - "] pub type CLK_SYS_JTAG_R = crate::BitReader; -#[doc = "Field `clk_sys_vreg_and_chip_reset` reader - "] +#[doc = "Field `CLK_SYS_VREG_AND_CHIP_RESET` reader - "] pub type CLK_SYS_VREG_AND_CHIP_RESET_R = crate::BitReader; -#[doc = "Field `clk_sys_pads` reader - "] +#[doc = "Field `CLK_SYS_PADS` reader - "] pub type CLK_SYS_PADS_R = crate::BitReader; -#[doc = "Field `clk_sys_pio0` reader - "] +#[doc = "Field `CLK_SYS_PIO0` reader - "] pub type CLK_SYS_PIO0_R = crate::BitReader; -#[doc = "Field `clk_sys_pio1` reader - "] +#[doc = "Field `CLK_SYS_PIO1` reader - "] pub type CLK_SYS_PIO1_R = crate::BitReader; -#[doc = "Field `clk_sys_pll_sys` reader - "] +#[doc = "Field `CLK_SYS_PLL_SYS` reader - "] pub type CLK_SYS_PLL_SYS_R = crate::BitReader; -#[doc = "Field `clk_sys_pll_usb` reader - "] +#[doc = "Field `CLK_SYS_PLL_USB` reader - "] pub type CLK_SYS_PLL_USB_R = crate::BitReader; -#[doc = "Field `clk_sys_psm` reader - "] +#[doc = "Field `CLK_SYS_PSM` reader - "] pub type CLK_SYS_PSM_R = crate::BitReader; -#[doc = "Field `clk_sys_pwm` reader - "] +#[doc = "Field `CLK_SYS_PWM` reader - "] pub type CLK_SYS_PWM_R = crate::BitReader; -#[doc = "Field `clk_sys_resets` reader - "] +#[doc = "Field `CLK_SYS_RESETS` reader - "] pub type CLK_SYS_RESETS_R = crate::BitReader; -#[doc = "Field `clk_sys_rom` reader - "] +#[doc = "Field `CLK_SYS_ROM` reader - "] pub type CLK_SYS_ROM_R = crate::BitReader; -#[doc = "Field `clk_sys_rosc` reader - "] +#[doc = "Field `CLK_SYS_ROSC` reader - "] pub type CLK_SYS_ROSC_R = crate::BitReader; -#[doc = "Field `clk_rtc_rtc` reader - "] +#[doc = "Field `CLK_RTC_RTC` reader - "] pub type CLK_RTC_RTC_R = crate::BitReader; -#[doc = "Field `clk_sys_rtc` reader - "] +#[doc = "Field `CLK_SYS_RTC` reader - "] pub type CLK_SYS_RTC_R = crate::BitReader; -#[doc = "Field `clk_sys_sio` reader - "] +#[doc = "Field `CLK_SYS_SIO` reader - "] pub type CLK_SYS_SIO_R = crate::BitReader; -#[doc = "Field `clk_peri_spi0` reader - "] +#[doc = "Field `CLK_PERI_SPI0` reader - "] pub type CLK_PERI_SPI0_R = crate::BitReader; -#[doc = "Field `clk_sys_spi0` reader - "] +#[doc = "Field `CLK_SYS_SPI0` reader - "] pub type CLK_SYS_SPI0_R = crate::BitReader; -#[doc = "Field `clk_peri_spi1` reader - "] +#[doc = "Field `CLK_PERI_SPI1` reader - "] pub type CLK_PERI_SPI1_R = crate::BitReader; -#[doc = "Field `clk_sys_spi1` reader - "] +#[doc = "Field `CLK_SYS_SPI1` reader - "] pub type CLK_SYS_SPI1_R = crate::BitReader; -#[doc = "Field `clk_sys_sram0` reader - "] +#[doc = "Field `CLK_SYS_SRAM0` reader - "] pub type CLK_SYS_SRAM0_R = crate::BitReader; -#[doc = "Field `clk_sys_sram1` reader - "] +#[doc = "Field `CLK_SYS_SRAM1` reader - "] pub type CLK_SYS_SRAM1_R = crate::BitReader; -#[doc = "Field `clk_sys_sram2` reader - "] +#[doc = "Field `CLK_SYS_SRAM2` reader - "] pub type CLK_SYS_SRAM2_R = crate::BitReader; -#[doc = "Field `clk_sys_sram3` reader - "] +#[doc = "Field `CLK_SYS_SRAM3` reader - "] pub type CLK_SYS_SRAM3_R = crate::BitReader; impl R { #[doc = "Bit 0"] @@ -226,15 +228,22 @@ impl R { CLK_SYS_SRAM3_R::new(((self.bits >> 31) & 1) != 0) } } +impl W {} #[doc = "indicates the state of the clock enable -You can [`read`](crate::generic::Reg::read) this register and get [`enabled0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`enabled0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enabled0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ENABLED0_SPEC; impl crate::RegisterSpec for ENABLED0_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`enabled0::R`](R) reader structure"] impl crate::Readable for ENABLED0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`enabled0::W`](W) writer structure"] +impl crate::Writable for ENABLED0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets ENABLED0 to value 0"] impl crate::Resettable for ENABLED0_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/clocks/enabled1.rs b/src/clocks/enabled1.rs index 3db69c4a2..82b356e0a 100644 --- a/src/clocks/enabled1.rs +++ b/src/clocks/enabled1.rs @@ -1,34 +1,36 @@ #[doc = "Register `ENABLED1` reader"] pub type R = crate::R; -#[doc = "Field `clk_sys_sram4` reader - "] +#[doc = "Register `ENABLED1` writer"] +pub type W = crate::W; +#[doc = "Field `CLK_SYS_SRAM4` reader - "] pub type CLK_SYS_SRAM4_R = crate::BitReader; -#[doc = "Field `clk_sys_sram5` reader - "] +#[doc = "Field `CLK_SYS_SRAM5` reader - "] pub type CLK_SYS_SRAM5_R = crate::BitReader; -#[doc = "Field `clk_sys_syscfg` reader - "] +#[doc = "Field `CLK_SYS_SYSCFG` reader - "] pub type CLK_SYS_SYSCFG_R = crate::BitReader; -#[doc = "Field `clk_sys_sysinfo` reader - "] +#[doc = "Field `CLK_SYS_SYSINFO` reader - "] pub type CLK_SYS_SYSINFO_R = crate::BitReader; -#[doc = "Field `clk_sys_tbman` reader - "] +#[doc = "Field `CLK_SYS_TBMAN` reader - "] pub type CLK_SYS_TBMAN_R = crate::BitReader; -#[doc = "Field `clk_sys_timer` reader - "] +#[doc = "Field `CLK_SYS_TIMER` reader - "] pub type CLK_SYS_TIMER_R = crate::BitReader; -#[doc = "Field `clk_peri_uart0` reader - "] +#[doc = "Field `CLK_PERI_UART0` reader - "] pub type CLK_PERI_UART0_R = crate::BitReader; -#[doc = "Field `clk_sys_uart0` reader - "] +#[doc = "Field `CLK_SYS_UART0` reader - "] pub type CLK_SYS_UART0_R = crate::BitReader; -#[doc = "Field `clk_peri_uart1` reader - "] +#[doc = "Field `CLK_PERI_UART1` reader - "] pub type CLK_PERI_UART1_R = crate::BitReader; -#[doc = "Field `clk_sys_uart1` reader - "] +#[doc = "Field `CLK_SYS_UART1` reader - "] pub type CLK_SYS_UART1_R = crate::BitReader; -#[doc = "Field `clk_sys_usbctrl` reader - "] +#[doc = "Field `CLK_SYS_USBCTRL` reader - "] pub type CLK_SYS_USBCTRL_R = crate::BitReader; -#[doc = "Field `clk_usb_usbctrl` reader - "] +#[doc = "Field `CLK_USB_USBCTRL` reader - "] pub type CLK_USB_USBCTRL_R = crate::BitReader; -#[doc = "Field `clk_sys_watchdog` reader - "] +#[doc = "Field `CLK_SYS_WATCHDOG` reader - "] pub type CLK_SYS_WATCHDOG_R = crate::BitReader; -#[doc = "Field `clk_sys_xip` reader - "] +#[doc = "Field `CLK_SYS_XIP` reader - "] pub type CLK_SYS_XIP_R = crate::BitReader; -#[doc = "Field `clk_sys_xosc` reader - "] +#[doc = "Field `CLK_SYS_XOSC` reader - "] pub type CLK_SYS_XOSC_R = crate::BitReader; impl R { #[doc = "Bit 0"] @@ -107,15 +109,22 @@ impl R { CLK_SYS_XOSC_R::new(((self.bits >> 14) & 1) != 0) } } +impl W {} #[doc = "indicates the state of the clock enable -You can [`read`](crate::generic::Reg::read) this register and get [`enabled1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`enabled1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enabled1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ENABLED1_SPEC; impl crate::RegisterSpec for ENABLED1_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`enabled1::R`](R) reader structure"] impl crate::Readable for ENABLED1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`enabled1::W`](W) writer structure"] +impl crate::Writable for ENABLED1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets ENABLED1 to value 0"] impl crate::Resettable for ENABLED1_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/clocks/fc0_delay.rs b/src/clocks/fc0_delay.rs index de0b8cf10..f56fee991 100644 --- a/src/clocks/fc0_delay.rs +++ b/src/clocks/fc0_delay.rs @@ -21,8 +21,7 @@ impl W { FC0_DELAY_W::new(self, 0) } } -#[doc = "Delays the start of frequency counting to allow the mux to settle - Delay is measured in multiples of the reference clock period +#[doc = "Delays the start of frequency counting to allow the mux to settle Delay is measured in multiples of the reference clock period You can [`read`](crate::generic::Reg::read) this register and get [`fc0_delay::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fc0_delay::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FC0_DELAY_SPEC; diff --git a/src/clocks/fc0_interval.rs b/src/clocks/fc0_interval.rs index 596f6a01b..c4f44683f 100644 --- a/src/clocks/fc0_interval.rs +++ b/src/clocks/fc0_interval.rs @@ -21,8 +21,7 @@ impl W { FC0_INTERVAL_W::new(self, 0) } } -#[doc = "The test interval is 0.98us * 2**interval, but let's call it 1us * 2**interval - The default gives a test interval of 250us +#[doc = "The test interval is 0.98us * 2**interval, but let's call it 1us * 2**interval The default gives a test interval of 250us You can [`read`](crate::generic::Reg::read) this register and get [`fc0_interval::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fc0_interval::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FC0_INTERVAL_SPEC; diff --git a/src/clocks/fc0_result.rs b/src/clocks/fc0_result.rs index b135bee61..19f8ce124 100644 --- a/src/clocks/fc0_result.rs +++ b/src/clocks/fc0_result.rs @@ -1,5 +1,7 @@ #[doc = "Register `FC0_RESULT` reader"] pub type R = crate::R; +#[doc = "Register `FC0_RESULT` writer"] +pub type W = crate::W; #[doc = "Field `FRAC` reader - "] pub type FRAC_R = crate::FieldReader; #[doc = "Field `KHZ` reader - "] @@ -16,15 +18,22 @@ impl R { KHZ_R::new((self.bits >> 5) & 0x01ff_ffff) } } +impl W {} #[doc = "Result of frequency measurement, only valid when status_done=1 -You can [`read`](crate::generic::Reg::read) this register and get [`fc0_result::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`fc0_result::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fc0_result::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FC0_RESULT_SPEC; impl crate::RegisterSpec for FC0_RESULT_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`fc0_result::R`](R) reader structure"] impl crate::Readable for FC0_RESULT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fc0_result::W`](W) writer structure"] +impl crate::Writable for FC0_RESULT_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets FC0_RESULT to value 0"] impl crate::Resettable for FC0_RESULT_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/clocks/fc0_src.rs b/src/clocks/fc0_src.rs index bfcf72e23..5be91eb4a 100644 --- a/src/clocks/fc0_src.rs +++ b/src/clocks/fc0_src.rs @@ -234,8 +234,7 @@ impl W { FC0_SRC_W::new(self, 0) } } -#[doc = "Clock sent to frequency counter, set to 0 when not required - Writing to this register initiates the frequency count +#[doc = "Clock sent to frequency counter, set to 0 when not required Writing to this register initiates the frequency count You can [`read`](crate::generic::Reg::read) this register and get [`fc0_src::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fc0_src::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FC0_SRC_SPEC; diff --git a/src/clocks/fc0_status.rs b/src/clocks/fc0_status.rs index 6d65590f6..41e01c150 100644 --- a/src/clocks/fc0_status.rs +++ b/src/clocks/fc0_status.rs @@ -1,5 +1,7 @@ #[doc = "Register `FC0_STATUS` reader"] pub type R = crate::R; +#[doc = "Register `FC0_STATUS` writer"] +pub type W = crate::W; #[doc = "Field `PASS` reader - Test passed"] pub type PASS_R = crate::BitReader; #[doc = "Field `DONE` reader - Test complete"] @@ -58,15 +60,22 @@ impl R { DIED_R::new(((self.bits >> 28) & 1) != 0) } } +impl W {} #[doc = "Frequency counter status -You can [`read`](crate::generic::Reg::read) this register and get [`fc0_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`fc0_status::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fc0_status::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FC0_STATUS_SPEC; impl crate::RegisterSpec for FC0_STATUS_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`fc0_status::R`](R) reader structure"] impl crate::Readable for FC0_STATUS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fc0_status::W`](W) writer structure"] +impl crate::Writable for FC0_STATUS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets FC0_STATUS to value 0"] impl crate::Resettable for FC0_STATUS_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/clocks/intr.rs b/src/clocks/intr.rs index e277eca51..7f4eb1f56 100644 --- a/src/clocks/intr.rs +++ b/src/clocks/intr.rs @@ -1,5 +1,7 @@ #[doc = "Register `INTR` reader"] pub type R = crate::R; +#[doc = "Register `INTR` writer"] +pub type W = crate::W; #[doc = "Field `CLK_SYS_RESUS` reader - "] pub type CLK_SYS_RESUS_R = crate::BitReader; impl R { @@ -9,15 +11,22 @@ impl R { CLK_SYS_RESUS_R::new((self.bits & 1) != 0) } } +impl W {} #[doc = "Raw Interrupts -You can [`read`](crate::generic::Reg::read) this register and get [`intr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`intr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTR_SPEC; impl crate::RegisterSpec for INTR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`intr::R`](R) reader structure"] impl crate::Readable for INTR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`intr::W`](W) writer structure"] +impl crate::Writable for INTR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets INTR to value 0"] impl crate::Resettable for INTR_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/clocks/ints.rs b/src/clocks/ints.rs index 4b65451ca..fffa4a1af 100644 --- a/src/clocks/ints.rs +++ b/src/clocks/ints.rs @@ -1,5 +1,7 @@ #[doc = "Register `INTS` reader"] pub type R = crate::R; +#[doc = "Register `INTS` writer"] +pub type W = crate::W; #[doc = "Field `CLK_SYS_RESUS` reader - "] pub type CLK_SYS_RESUS_R = crate::BitReader; impl R { @@ -9,15 +11,22 @@ impl R { CLK_SYS_RESUS_R::new((self.bits & 1) != 0) } } +impl W {} #[doc = "Interrupt status after masking & forcing -You can [`read`](crate::generic::Reg::read) this register and get [`ints::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`ints::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ints::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTS_SPEC; impl crate::RegisterSpec for INTS_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`ints::R`](R) reader structure"] impl crate::Readable for INTS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ints::W`](W) writer structure"] +impl crate::Writable for INTS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets INTS to value 0"] impl crate::Resettable for INTS_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/clocks/sleep_en0.rs b/src/clocks/sleep_en0.rs index 5104a40f9..4231f1553 100644 --- a/src/clocks/sleep_en0.rs +++ b/src/clocks/sleep_en0.rs @@ -2,133 +2,133 @@ pub type R = crate::R; #[doc = "Register `SLEEP_EN0` writer"] pub type W = crate::W; -#[doc = "Field `clk_sys_clocks` reader - "] +#[doc = "Field `CLK_SYS_CLOCKS` reader - "] pub type CLK_SYS_CLOCKS_R = crate::BitReader; -#[doc = "Field `clk_sys_clocks` writer - "] +#[doc = "Field `CLK_SYS_CLOCKS` writer - "] pub type CLK_SYS_CLOCKS_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_adc_adc` reader - "] +#[doc = "Field `CLK_ADC_ADC` reader - "] pub type CLK_ADC_ADC_R = crate::BitReader; -#[doc = "Field `clk_adc_adc` writer - "] +#[doc = "Field `CLK_ADC_ADC` writer - "] pub type CLK_ADC_ADC_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_sys_adc` reader - "] +#[doc = "Field `CLK_SYS_ADC` reader - "] pub type CLK_SYS_ADC_R = crate::BitReader; -#[doc = "Field `clk_sys_adc` writer - "] +#[doc = "Field `CLK_SYS_ADC` writer - "] pub type CLK_SYS_ADC_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_sys_busctrl` reader - "] +#[doc = "Field `CLK_SYS_BUSCTRL` reader - "] pub type CLK_SYS_BUSCTRL_R = crate::BitReader; -#[doc = "Field `clk_sys_busctrl` writer - "] +#[doc = "Field `CLK_SYS_BUSCTRL` writer - "] pub type CLK_SYS_BUSCTRL_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_sys_busfabric` reader - "] +#[doc = "Field `CLK_SYS_BUSFABRIC` reader - "] pub type CLK_SYS_BUSFABRIC_R = crate::BitReader; -#[doc = "Field `clk_sys_busfabric` writer - "] +#[doc = "Field `CLK_SYS_BUSFABRIC` writer - "] pub type CLK_SYS_BUSFABRIC_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_sys_dma` reader - "] +#[doc = "Field `CLK_SYS_DMA` reader - "] pub type CLK_SYS_DMA_R = crate::BitReader; -#[doc = "Field `clk_sys_dma` writer - "] +#[doc = "Field `CLK_SYS_DMA` writer - "] pub type CLK_SYS_DMA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_sys_i2c0` reader - "] +#[doc = "Field `CLK_SYS_I2C0` reader - "] pub type CLK_SYS_I2C0_R = crate::BitReader; -#[doc = "Field `clk_sys_i2c0` writer - "] +#[doc = "Field `CLK_SYS_I2C0` writer - "] pub type CLK_SYS_I2C0_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_sys_i2c1` reader - "] +#[doc = "Field `CLK_SYS_I2C1` reader - "] pub type CLK_SYS_I2C1_R = crate::BitReader; -#[doc = "Field `clk_sys_i2c1` writer - "] +#[doc = "Field `CLK_SYS_I2C1` writer - "] pub type CLK_SYS_I2C1_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_sys_io` reader - "] +#[doc = "Field `CLK_SYS_IO` reader - "] pub type CLK_SYS_IO_R = crate::BitReader; -#[doc = "Field `clk_sys_io` writer - "] +#[doc = "Field `CLK_SYS_IO` writer - "] pub type CLK_SYS_IO_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_sys_jtag` reader - "] +#[doc = "Field `CLK_SYS_JTAG` reader - "] pub type CLK_SYS_JTAG_R = crate::BitReader; -#[doc = "Field `clk_sys_jtag` writer - "] +#[doc = "Field `CLK_SYS_JTAG` writer - "] pub type CLK_SYS_JTAG_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_sys_vreg_and_chip_reset` reader - "] +#[doc = "Field `CLK_SYS_VREG_AND_CHIP_RESET` reader - "] pub type CLK_SYS_VREG_AND_CHIP_RESET_R = crate::BitReader; -#[doc = "Field `clk_sys_vreg_and_chip_reset` writer - "] +#[doc = "Field `CLK_SYS_VREG_AND_CHIP_RESET` writer - "] pub type CLK_SYS_VREG_AND_CHIP_RESET_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_sys_pads` reader - "] +#[doc = "Field `CLK_SYS_PADS` reader - "] pub type CLK_SYS_PADS_R = crate::BitReader; -#[doc = "Field `clk_sys_pads` writer - "] +#[doc = "Field `CLK_SYS_PADS` writer - "] pub type CLK_SYS_PADS_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_sys_pio0` reader - "] +#[doc = "Field `CLK_SYS_PIO0` reader - "] pub type CLK_SYS_PIO0_R = crate::BitReader; -#[doc = "Field `clk_sys_pio0` writer - "] +#[doc = "Field `CLK_SYS_PIO0` writer - "] pub type CLK_SYS_PIO0_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_sys_pio1` reader - "] +#[doc = "Field `CLK_SYS_PIO1` reader - "] pub type CLK_SYS_PIO1_R = crate::BitReader; -#[doc = "Field `clk_sys_pio1` writer - "] +#[doc = "Field `CLK_SYS_PIO1` writer - "] pub type CLK_SYS_PIO1_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_sys_pll_sys` reader - "] +#[doc = "Field `CLK_SYS_PLL_SYS` reader - "] pub type CLK_SYS_PLL_SYS_R = crate::BitReader; -#[doc = "Field `clk_sys_pll_sys` writer - "] +#[doc = "Field `CLK_SYS_PLL_SYS` writer - "] pub type CLK_SYS_PLL_SYS_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_sys_pll_usb` reader - "] +#[doc = "Field `CLK_SYS_PLL_USB` reader - "] pub type CLK_SYS_PLL_USB_R = crate::BitReader; -#[doc = "Field `clk_sys_pll_usb` writer - "] +#[doc = "Field `CLK_SYS_PLL_USB` writer - "] pub type CLK_SYS_PLL_USB_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_sys_psm` reader - "] +#[doc = "Field `CLK_SYS_PSM` reader - "] pub type CLK_SYS_PSM_R = crate::BitReader; -#[doc = "Field `clk_sys_psm` writer - "] +#[doc = "Field `CLK_SYS_PSM` writer - "] pub type CLK_SYS_PSM_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_sys_pwm` reader - "] +#[doc = "Field `CLK_SYS_PWM` reader - "] pub type CLK_SYS_PWM_R = crate::BitReader; -#[doc = "Field `clk_sys_pwm` writer - "] +#[doc = "Field `CLK_SYS_PWM` writer - "] pub type CLK_SYS_PWM_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_sys_resets` reader - "] +#[doc = "Field `CLK_SYS_RESETS` reader - "] pub type CLK_SYS_RESETS_R = crate::BitReader; -#[doc = "Field `clk_sys_resets` writer - "] +#[doc = "Field `CLK_SYS_RESETS` writer - "] pub type CLK_SYS_RESETS_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_sys_rom` reader - "] +#[doc = "Field `CLK_SYS_ROM` reader - "] pub type CLK_SYS_ROM_R = crate::BitReader; -#[doc = "Field `clk_sys_rom` writer - "] +#[doc = "Field `CLK_SYS_ROM` writer - "] pub type CLK_SYS_ROM_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_sys_rosc` reader - "] +#[doc = "Field `CLK_SYS_ROSC` reader - "] pub type CLK_SYS_ROSC_R = crate::BitReader; -#[doc = "Field `clk_sys_rosc` writer - "] +#[doc = "Field `CLK_SYS_ROSC` writer - "] pub type CLK_SYS_ROSC_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_rtc_rtc` reader - "] +#[doc = "Field `CLK_RTC_RTC` reader - "] pub type CLK_RTC_RTC_R = crate::BitReader; -#[doc = "Field `clk_rtc_rtc` writer - "] +#[doc = "Field `CLK_RTC_RTC` writer - "] pub type CLK_RTC_RTC_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_sys_rtc` reader - "] +#[doc = "Field `CLK_SYS_RTC` reader - "] pub type CLK_SYS_RTC_R = crate::BitReader; -#[doc = "Field `clk_sys_rtc` writer - "] +#[doc = "Field `CLK_SYS_RTC` writer - "] pub type CLK_SYS_RTC_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_sys_sio` reader - "] +#[doc = "Field `CLK_SYS_SIO` reader - "] pub type CLK_SYS_SIO_R = crate::BitReader; -#[doc = "Field `clk_sys_sio` writer - "] +#[doc = "Field `CLK_SYS_SIO` writer - "] pub type CLK_SYS_SIO_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_peri_spi0` reader - "] +#[doc = "Field `CLK_PERI_SPI0` reader - "] pub type CLK_PERI_SPI0_R = crate::BitReader; -#[doc = "Field `clk_peri_spi0` writer - "] +#[doc = "Field `CLK_PERI_SPI0` writer - "] pub type CLK_PERI_SPI0_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_sys_spi0` reader - "] +#[doc = "Field `CLK_SYS_SPI0` reader - "] pub type CLK_SYS_SPI0_R = crate::BitReader; -#[doc = "Field `clk_sys_spi0` writer - "] +#[doc = "Field `CLK_SYS_SPI0` writer - "] pub type CLK_SYS_SPI0_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_peri_spi1` reader - "] +#[doc = "Field `CLK_PERI_SPI1` reader - "] pub type CLK_PERI_SPI1_R = crate::BitReader; -#[doc = "Field `clk_peri_spi1` writer - "] +#[doc = "Field `CLK_PERI_SPI1` writer - "] pub type CLK_PERI_SPI1_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_sys_spi1` reader - "] +#[doc = "Field `CLK_SYS_SPI1` reader - "] pub type CLK_SYS_SPI1_R = crate::BitReader; -#[doc = "Field `clk_sys_spi1` writer - "] +#[doc = "Field `CLK_SYS_SPI1` writer - "] pub type CLK_SYS_SPI1_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_sys_sram0` reader - "] +#[doc = "Field `CLK_SYS_SRAM0` reader - "] pub type CLK_SYS_SRAM0_R = crate::BitReader; -#[doc = "Field `clk_sys_sram0` writer - "] +#[doc = "Field `CLK_SYS_SRAM0` writer - "] pub type CLK_SYS_SRAM0_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_sys_sram1` reader - "] +#[doc = "Field `CLK_SYS_SRAM1` reader - "] pub type CLK_SYS_SRAM1_R = crate::BitReader; -#[doc = "Field `clk_sys_sram1` writer - "] +#[doc = "Field `CLK_SYS_SRAM1` writer - "] pub type CLK_SYS_SRAM1_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_sys_sram2` reader - "] +#[doc = "Field `CLK_SYS_SRAM2` reader - "] pub type CLK_SYS_SRAM2_R = crate::BitReader; -#[doc = "Field `clk_sys_sram2` writer - "] +#[doc = "Field `CLK_SYS_SRAM2` writer - "] pub type CLK_SYS_SRAM2_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_sys_sram3` reader - "] +#[doc = "Field `CLK_SYS_SRAM3` reader - "] pub type CLK_SYS_SRAM3_R = crate::BitReader; -#[doc = "Field `clk_sys_sram3` writer - "] +#[doc = "Field `CLK_SYS_SRAM3` writer - "] pub type CLK_SYS_SRAM3_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0"] diff --git a/src/clocks/sleep_en1.rs b/src/clocks/sleep_en1.rs index cd786cf31..02b4cc46f 100644 --- a/src/clocks/sleep_en1.rs +++ b/src/clocks/sleep_en1.rs @@ -2,65 +2,65 @@ pub type R = crate::R; #[doc = "Register `SLEEP_EN1` writer"] pub type W = crate::W; -#[doc = "Field `clk_sys_sram4` reader - "] +#[doc = "Field `CLK_SYS_SRAM4` reader - "] pub type CLK_SYS_SRAM4_R = crate::BitReader; -#[doc = "Field `clk_sys_sram4` writer - "] +#[doc = "Field `CLK_SYS_SRAM4` writer - "] pub type CLK_SYS_SRAM4_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_sys_sram5` reader - "] +#[doc = "Field `CLK_SYS_SRAM5` reader - "] pub type CLK_SYS_SRAM5_R = crate::BitReader; -#[doc = "Field `clk_sys_sram5` writer - "] +#[doc = "Field `CLK_SYS_SRAM5` writer - "] pub type CLK_SYS_SRAM5_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_sys_syscfg` reader - "] +#[doc = "Field `CLK_SYS_SYSCFG` reader - "] pub type CLK_SYS_SYSCFG_R = crate::BitReader; -#[doc = "Field `clk_sys_syscfg` writer - "] +#[doc = "Field `CLK_SYS_SYSCFG` writer - "] pub type CLK_SYS_SYSCFG_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_sys_sysinfo` reader - "] +#[doc = "Field `CLK_SYS_SYSINFO` reader - "] pub type CLK_SYS_SYSINFO_R = crate::BitReader; -#[doc = "Field `clk_sys_sysinfo` writer - "] +#[doc = "Field `CLK_SYS_SYSINFO` writer - "] pub type CLK_SYS_SYSINFO_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_sys_tbman` reader - "] +#[doc = "Field `CLK_SYS_TBMAN` reader - "] pub type CLK_SYS_TBMAN_R = crate::BitReader; -#[doc = "Field `clk_sys_tbman` writer - "] +#[doc = "Field `CLK_SYS_TBMAN` writer - "] pub type CLK_SYS_TBMAN_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_sys_timer` reader - "] +#[doc = "Field `CLK_SYS_TIMER` reader - "] pub type CLK_SYS_TIMER_R = crate::BitReader; -#[doc = "Field `clk_sys_timer` writer - "] +#[doc = "Field `CLK_SYS_TIMER` writer - "] pub type CLK_SYS_TIMER_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_peri_uart0` reader - "] +#[doc = "Field `CLK_PERI_UART0` reader - "] pub type CLK_PERI_UART0_R = crate::BitReader; -#[doc = "Field `clk_peri_uart0` writer - "] +#[doc = "Field `CLK_PERI_UART0` writer - "] pub type CLK_PERI_UART0_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_sys_uart0` reader - "] +#[doc = "Field `CLK_SYS_UART0` reader - "] pub type CLK_SYS_UART0_R = crate::BitReader; -#[doc = "Field `clk_sys_uart0` writer - "] +#[doc = "Field `CLK_SYS_UART0` writer - "] pub type CLK_SYS_UART0_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_peri_uart1` reader - "] +#[doc = "Field `CLK_PERI_UART1` reader - "] pub type CLK_PERI_UART1_R = crate::BitReader; -#[doc = "Field `clk_peri_uart1` writer - "] +#[doc = "Field `CLK_PERI_UART1` writer - "] pub type CLK_PERI_UART1_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_sys_uart1` reader - "] +#[doc = "Field `CLK_SYS_UART1` reader - "] pub type CLK_SYS_UART1_R = crate::BitReader; -#[doc = "Field `clk_sys_uart1` writer - "] +#[doc = "Field `CLK_SYS_UART1` writer - "] pub type CLK_SYS_UART1_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_sys_usbctrl` reader - "] +#[doc = "Field `CLK_SYS_USBCTRL` reader - "] pub type CLK_SYS_USBCTRL_R = crate::BitReader; -#[doc = "Field `clk_sys_usbctrl` writer - "] +#[doc = "Field `CLK_SYS_USBCTRL` writer - "] pub type CLK_SYS_USBCTRL_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_usb_usbctrl` reader - "] +#[doc = "Field `CLK_USB_USBCTRL` reader - "] pub type CLK_USB_USBCTRL_R = crate::BitReader; -#[doc = "Field `clk_usb_usbctrl` writer - "] +#[doc = "Field `CLK_USB_USBCTRL` writer - "] pub type CLK_USB_USBCTRL_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_sys_watchdog` reader - "] +#[doc = "Field `CLK_SYS_WATCHDOG` reader - "] pub type CLK_SYS_WATCHDOG_R = crate::BitReader; -#[doc = "Field `clk_sys_watchdog` writer - "] +#[doc = "Field `CLK_SYS_WATCHDOG` writer - "] pub type CLK_SYS_WATCHDOG_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_sys_xip` reader - "] +#[doc = "Field `CLK_SYS_XIP` reader - "] pub type CLK_SYS_XIP_R = crate::BitReader; -#[doc = "Field `clk_sys_xip` writer - "] +#[doc = "Field `CLK_SYS_XIP` writer - "] pub type CLK_SYS_XIP_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_sys_xosc` reader - "] +#[doc = "Field `CLK_SYS_XOSC` reader - "] pub type CLK_SYS_XOSC_R = crate::BitReader; -#[doc = "Field `clk_sys_xosc` writer - "] +#[doc = "Field `CLK_SYS_XOSC` writer - "] pub type CLK_SYS_XOSC_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0"] diff --git a/src/clocks/wake_en0.rs b/src/clocks/wake_en0.rs index b1c0edb48..975e105d7 100644 --- a/src/clocks/wake_en0.rs +++ b/src/clocks/wake_en0.rs @@ -2,133 +2,133 @@ pub type R = crate::R; #[doc = "Register `WAKE_EN0` writer"] pub type W = crate::W; -#[doc = "Field `clk_sys_clocks` reader - "] +#[doc = "Field `CLK_SYS_CLOCKS` reader - "] pub type CLK_SYS_CLOCKS_R = crate::BitReader; -#[doc = "Field `clk_sys_clocks` writer - "] +#[doc = "Field `CLK_SYS_CLOCKS` writer - "] pub type CLK_SYS_CLOCKS_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_adc_adc` reader - "] +#[doc = "Field `CLK_ADC_ADC` reader - "] pub type CLK_ADC_ADC_R = crate::BitReader; -#[doc = "Field `clk_adc_adc` writer - "] +#[doc = "Field `CLK_ADC_ADC` writer - "] pub type CLK_ADC_ADC_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_sys_adc` reader - "] +#[doc = "Field `CLK_SYS_ADC` reader - "] pub type CLK_SYS_ADC_R = crate::BitReader; -#[doc = "Field `clk_sys_adc` writer - "] +#[doc = "Field `CLK_SYS_ADC` writer - "] pub type CLK_SYS_ADC_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_sys_busctrl` reader - "] +#[doc = "Field `CLK_SYS_BUSCTRL` reader - "] pub type CLK_SYS_BUSCTRL_R = crate::BitReader; -#[doc = "Field `clk_sys_busctrl` writer - "] +#[doc = "Field `CLK_SYS_BUSCTRL` writer - "] pub type CLK_SYS_BUSCTRL_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_sys_busfabric` reader - "] +#[doc = "Field `CLK_SYS_BUSFABRIC` reader - "] pub type CLK_SYS_BUSFABRIC_R = crate::BitReader; -#[doc = "Field `clk_sys_busfabric` writer - "] +#[doc = "Field `CLK_SYS_BUSFABRIC` writer - "] pub type CLK_SYS_BUSFABRIC_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_sys_dma` reader - "] +#[doc = "Field `CLK_SYS_DMA` reader - "] pub type CLK_SYS_DMA_R = crate::BitReader; -#[doc = "Field `clk_sys_dma` writer - "] +#[doc = "Field `CLK_SYS_DMA` writer - "] pub type CLK_SYS_DMA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_sys_i2c0` reader - "] +#[doc = "Field `CLK_SYS_I2C0` reader - "] pub type CLK_SYS_I2C0_R = crate::BitReader; -#[doc = "Field `clk_sys_i2c0` writer - "] +#[doc = "Field `CLK_SYS_I2C0` writer - "] pub type CLK_SYS_I2C0_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_sys_i2c1` reader - "] +#[doc = "Field `CLK_SYS_I2C1` reader - "] pub type CLK_SYS_I2C1_R = crate::BitReader; -#[doc = "Field `clk_sys_i2c1` writer - "] +#[doc = "Field `CLK_SYS_I2C1` writer - "] pub type CLK_SYS_I2C1_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_sys_io` reader - "] +#[doc = "Field `CLK_SYS_IO` reader - "] pub type CLK_SYS_IO_R = crate::BitReader; -#[doc = "Field `clk_sys_io` writer - "] +#[doc = "Field `CLK_SYS_IO` writer - "] pub type CLK_SYS_IO_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_sys_jtag` reader - "] +#[doc = "Field `CLK_SYS_JTAG` reader - "] pub type CLK_SYS_JTAG_R = crate::BitReader; -#[doc = "Field `clk_sys_jtag` writer - "] +#[doc = "Field `CLK_SYS_JTAG` writer - "] pub type CLK_SYS_JTAG_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_sys_vreg_and_chip_reset` reader - "] +#[doc = "Field `CLK_SYS_VREG_AND_CHIP_RESET` reader - "] pub type CLK_SYS_VREG_AND_CHIP_RESET_R = crate::BitReader; -#[doc = "Field `clk_sys_vreg_and_chip_reset` writer - "] +#[doc = "Field `CLK_SYS_VREG_AND_CHIP_RESET` writer - "] pub type CLK_SYS_VREG_AND_CHIP_RESET_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_sys_pads` reader - "] +#[doc = "Field `CLK_SYS_PADS` reader - "] pub type CLK_SYS_PADS_R = crate::BitReader; -#[doc = "Field `clk_sys_pads` writer - "] +#[doc = "Field `CLK_SYS_PADS` writer - "] pub type CLK_SYS_PADS_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_sys_pio0` reader - "] +#[doc = "Field `CLK_SYS_PIO0` reader - "] pub type CLK_SYS_PIO0_R = crate::BitReader; -#[doc = "Field `clk_sys_pio0` writer - "] +#[doc = "Field `CLK_SYS_PIO0` writer - "] pub type CLK_SYS_PIO0_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_sys_pio1` reader - "] +#[doc = "Field `CLK_SYS_PIO1` reader - "] pub type CLK_SYS_PIO1_R = crate::BitReader; -#[doc = "Field `clk_sys_pio1` writer - "] +#[doc = "Field `CLK_SYS_PIO1` writer - "] pub type CLK_SYS_PIO1_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_sys_pll_sys` reader - "] +#[doc = "Field `CLK_SYS_PLL_SYS` reader - "] pub type CLK_SYS_PLL_SYS_R = crate::BitReader; -#[doc = "Field `clk_sys_pll_sys` writer - "] +#[doc = "Field `CLK_SYS_PLL_SYS` writer - "] pub type CLK_SYS_PLL_SYS_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_sys_pll_usb` reader - "] +#[doc = "Field `CLK_SYS_PLL_USB` reader - "] pub type CLK_SYS_PLL_USB_R = crate::BitReader; -#[doc = "Field `clk_sys_pll_usb` writer - "] +#[doc = "Field `CLK_SYS_PLL_USB` writer - "] pub type CLK_SYS_PLL_USB_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_sys_psm` reader - "] +#[doc = "Field `CLK_SYS_PSM` reader - "] pub type CLK_SYS_PSM_R = crate::BitReader; -#[doc = "Field `clk_sys_psm` writer - "] +#[doc = "Field `CLK_SYS_PSM` writer - "] pub type CLK_SYS_PSM_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_sys_pwm` reader - "] +#[doc = "Field `CLK_SYS_PWM` reader - "] pub type CLK_SYS_PWM_R = crate::BitReader; -#[doc = "Field `clk_sys_pwm` writer - "] +#[doc = "Field `CLK_SYS_PWM` writer - "] pub type CLK_SYS_PWM_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_sys_resets` reader - "] +#[doc = "Field `CLK_SYS_RESETS` reader - "] pub type CLK_SYS_RESETS_R = crate::BitReader; -#[doc = "Field `clk_sys_resets` writer - "] +#[doc = "Field `CLK_SYS_RESETS` writer - "] pub type CLK_SYS_RESETS_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_sys_rom` reader - "] +#[doc = "Field `CLK_SYS_ROM` reader - "] pub type CLK_SYS_ROM_R = crate::BitReader; -#[doc = "Field `clk_sys_rom` writer - "] +#[doc = "Field `CLK_SYS_ROM` writer - "] pub type CLK_SYS_ROM_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_sys_rosc` reader - "] +#[doc = "Field `CLK_SYS_ROSC` reader - "] pub type CLK_SYS_ROSC_R = crate::BitReader; -#[doc = "Field `clk_sys_rosc` writer - "] +#[doc = "Field `CLK_SYS_ROSC` writer - "] pub type CLK_SYS_ROSC_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_rtc_rtc` reader - "] +#[doc = "Field `CLK_RTC_RTC` reader - "] pub type CLK_RTC_RTC_R = crate::BitReader; -#[doc = "Field `clk_rtc_rtc` writer - "] +#[doc = "Field `CLK_RTC_RTC` writer - "] pub type CLK_RTC_RTC_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_sys_rtc` reader - "] +#[doc = "Field `CLK_SYS_RTC` reader - "] pub type CLK_SYS_RTC_R = crate::BitReader; -#[doc = "Field `clk_sys_rtc` writer - "] +#[doc = "Field `CLK_SYS_RTC` writer - "] pub type CLK_SYS_RTC_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_sys_sio` reader - "] +#[doc = "Field `CLK_SYS_SIO` reader - "] pub type CLK_SYS_SIO_R = crate::BitReader; -#[doc = "Field `clk_sys_sio` writer - "] +#[doc = "Field `CLK_SYS_SIO` writer - "] pub type CLK_SYS_SIO_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_peri_spi0` reader - "] +#[doc = "Field `CLK_PERI_SPI0` reader - "] pub type CLK_PERI_SPI0_R = crate::BitReader; -#[doc = "Field `clk_peri_spi0` writer - "] +#[doc = "Field `CLK_PERI_SPI0` writer - "] pub type CLK_PERI_SPI0_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_sys_spi0` reader - "] +#[doc = "Field `CLK_SYS_SPI0` reader - "] pub type CLK_SYS_SPI0_R = crate::BitReader; -#[doc = "Field `clk_sys_spi0` writer - "] +#[doc = "Field `CLK_SYS_SPI0` writer - "] pub type CLK_SYS_SPI0_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_peri_spi1` reader - "] +#[doc = "Field `CLK_PERI_SPI1` reader - "] pub type CLK_PERI_SPI1_R = crate::BitReader; -#[doc = "Field `clk_peri_spi1` writer - "] +#[doc = "Field `CLK_PERI_SPI1` writer - "] pub type CLK_PERI_SPI1_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_sys_spi1` reader - "] +#[doc = "Field `CLK_SYS_SPI1` reader - "] pub type CLK_SYS_SPI1_R = crate::BitReader; -#[doc = "Field `clk_sys_spi1` writer - "] +#[doc = "Field `CLK_SYS_SPI1` writer - "] pub type CLK_SYS_SPI1_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_sys_sram0` reader - "] +#[doc = "Field `CLK_SYS_SRAM0` reader - "] pub type CLK_SYS_SRAM0_R = crate::BitReader; -#[doc = "Field `clk_sys_sram0` writer - "] +#[doc = "Field `CLK_SYS_SRAM0` writer - "] pub type CLK_SYS_SRAM0_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_sys_sram1` reader - "] +#[doc = "Field `CLK_SYS_SRAM1` reader - "] pub type CLK_SYS_SRAM1_R = crate::BitReader; -#[doc = "Field `clk_sys_sram1` writer - "] +#[doc = "Field `CLK_SYS_SRAM1` writer - "] pub type CLK_SYS_SRAM1_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_sys_sram2` reader - "] +#[doc = "Field `CLK_SYS_SRAM2` reader - "] pub type CLK_SYS_SRAM2_R = crate::BitReader; -#[doc = "Field `clk_sys_sram2` writer - "] +#[doc = "Field `CLK_SYS_SRAM2` writer - "] pub type CLK_SYS_SRAM2_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_sys_sram3` reader - "] +#[doc = "Field `CLK_SYS_SRAM3` reader - "] pub type CLK_SYS_SRAM3_R = crate::BitReader; -#[doc = "Field `clk_sys_sram3` writer - "] +#[doc = "Field `CLK_SYS_SRAM3` writer - "] pub type CLK_SYS_SRAM3_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0"] diff --git a/src/clocks/wake_en1.rs b/src/clocks/wake_en1.rs index 9e4eca31a..810bccd9f 100644 --- a/src/clocks/wake_en1.rs +++ b/src/clocks/wake_en1.rs @@ -2,65 +2,65 @@ pub type R = crate::R; #[doc = "Register `WAKE_EN1` writer"] pub type W = crate::W; -#[doc = "Field `clk_sys_sram4` reader - "] +#[doc = "Field `CLK_SYS_SRAM4` reader - "] pub type CLK_SYS_SRAM4_R = crate::BitReader; -#[doc = "Field `clk_sys_sram4` writer - "] +#[doc = "Field `CLK_SYS_SRAM4` writer - "] pub type CLK_SYS_SRAM4_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_sys_sram5` reader - "] +#[doc = "Field `CLK_SYS_SRAM5` reader - "] pub type CLK_SYS_SRAM5_R = crate::BitReader; -#[doc = "Field `clk_sys_sram5` writer - "] +#[doc = "Field `CLK_SYS_SRAM5` writer - "] pub type CLK_SYS_SRAM5_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_sys_syscfg` reader - "] +#[doc = "Field `CLK_SYS_SYSCFG` reader - "] pub type CLK_SYS_SYSCFG_R = crate::BitReader; -#[doc = "Field `clk_sys_syscfg` writer - "] +#[doc = "Field `CLK_SYS_SYSCFG` writer - "] pub type CLK_SYS_SYSCFG_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_sys_sysinfo` reader - "] +#[doc = "Field `CLK_SYS_SYSINFO` reader - "] pub type CLK_SYS_SYSINFO_R = crate::BitReader; -#[doc = "Field `clk_sys_sysinfo` writer - "] +#[doc = "Field `CLK_SYS_SYSINFO` writer - "] pub type CLK_SYS_SYSINFO_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_sys_tbman` reader - "] +#[doc = "Field `CLK_SYS_TBMAN` reader - "] pub type CLK_SYS_TBMAN_R = crate::BitReader; -#[doc = "Field `clk_sys_tbman` writer - "] +#[doc = "Field `CLK_SYS_TBMAN` writer - "] pub type CLK_SYS_TBMAN_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_sys_timer` reader - "] +#[doc = "Field `CLK_SYS_TIMER` reader - "] pub type CLK_SYS_TIMER_R = crate::BitReader; -#[doc = "Field `clk_sys_timer` writer - "] +#[doc = "Field `CLK_SYS_TIMER` writer - "] pub type CLK_SYS_TIMER_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_peri_uart0` reader - "] +#[doc = "Field `CLK_PERI_UART0` reader - "] pub type CLK_PERI_UART0_R = crate::BitReader; -#[doc = "Field `clk_peri_uart0` writer - "] +#[doc = "Field `CLK_PERI_UART0` writer - "] pub type CLK_PERI_UART0_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_sys_uart0` reader - "] +#[doc = "Field `CLK_SYS_UART0` reader - "] pub type CLK_SYS_UART0_R = crate::BitReader; -#[doc = "Field `clk_sys_uart0` writer - "] +#[doc = "Field `CLK_SYS_UART0` writer - "] pub type CLK_SYS_UART0_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_peri_uart1` reader - "] +#[doc = "Field `CLK_PERI_UART1` reader - "] pub type CLK_PERI_UART1_R = crate::BitReader; -#[doc = "Field `clk_peri_uart1` writer - "] +#[doc = "Field `CLK_PERI_UART1` writer - "] pub type CLK_PERI_UART1_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_sys_uart1` reader - "] +#[doc = "Field `CLK_SYS_UART1` reader - "] pub type CLK_SYS_UART1_R = crate::BitReader; -#[doc = "Field `clk_sys_uart1` writer - "] +#[doc = "Field `CLK_SYS_UART1` writer - "] pub type CLK_SYS_UART1_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_sys_usbctrl` reader - "] +#[doc = "Field `CLK_SYS_USBCTRL` reader - "] pub type CLK_SYS_USBCTRL_R = crate::BitReader; -#[doc = "Field `clk_sys_usbctrl` writer - "] +#[doc = "Field `CLK_SYS_USBCTRL` writer - "] pub type CLK_SYS_USBCTRL_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_usb_usbctrl` reader - "] +#[doc = "Field `CLK_USB_USBCTRL` reader - "] pub type CLK_USB_USBCTRL_R = crate::BitReader; -#[doc = "Field `clk_usb_usbctrl` writer - "] +#[doc = "Field `CLK_USB_USBCTRL` writer - "] pub type CLK_USB_USBCTRL_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_sys_watchdog` reader - "] +#[doc = "Field `CLK_SYS_WATCHDOG` reader - "] pub type CLK_SYS_WATCHDOG_R = crate::BitReader; -#[doc = "Field `clk_sys_watchdog` writer - "] +#[doc = "Field `CLK_SYS_WATCHDOG` writer - "] pub type CLK_SYS_WATCHDOG_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_sys_xip` reader - "] +#[doc = "Field `CLK_SYS_XIP` reader - "] pub type CLK_SYS_XIP_R = crate::BitReader; -#[doc = "Field `clk_sys_xip` writer - "] +#[doc = "Field `CLK_SYS_XIP` writer - "] pub type CLK_SYS_XIP_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clk_sys_xosc` reader - "] +#[doc = "Field `CLK_SYS_XOSC` reader - "] pub type CLK_SYS_XOSC_R = crate::BitReader; -#[doc = "Field `clk_sys_xosc` writer - "] +#[doc = "Field `CLK_SYS_XOSC` writer - "] pub type CLK_SYS_XOSC_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0"] diff --git a/src/dma.rs b/src/dma.rs index 388108620..39b2d1a0b 100644 --- a/src/dma.rs +++ b/src/dma.rs @@ -7,7 +7,7 @@ pub struct RegisterBlock { inte0: INTE0, intf0: INTF0, ints0: INTS0, - _reserved5: [u8; 0x04], + intr1: INTR1, inte1: INTE1, intf1: INTF1, ints1: INTS1, @@ -18,44 +18,44 @@ pub struct RegisterBlock { multi_chan_trigger: MULTI_CHAN_TRIGGER, sniff_ctrl: SNIFF_CTRL, sniff_data: SNIFF_DATA, - _reserved15: [u8; 0x04], + _reserved16: [u8; 0x04], fifo_levels: FIFO_LEVELS, chan_abort: CHAN_ABORT, n_channels: N_CHANNELS, - _reserved18: [u8; 0x03b4], + _reserved19: [u8; 0x03b4], ch0_dbg_ctdreq: CH0_DBG_CTDREQ, ch0_dbg_tcr: CH0_DBG_TCR, - _reserved20: [u8; 0x38], + _reserved21: [u8; 0x38], ch1_dbg_ctdreq: CH1_DBG_CTDREQ, ch1_dbg_tcr: CH1_DBG_TCR, - _reserved22: [u8; 0x38], + _reserved23: [u8; 0x38], ch2_dbg_ctdreq: CH2_DBG_CTDREQ, ch2_dbg_tcr: CH2_DBG_TCR, - _reserved24: [u8; 0x38], + _reserved25: [u8; 0x38], ch3_dbg_ctdreq: CH3_DBG_CTDREQ, ch3_dbg_tcr: CH3_DBG_TCR, - _reserved26: [u8; 0x38], + _reserved27: [u8; 0x38], ch4_dbg_ctdreq: CH4_DBG_CTDREQ, ch4_dbg_tcr: CH4_DBG_TCR, - _reserved28: [u8; 0x38], + _reserved29: [u8; 0x38], ch5_dbg_ctdreq: CH5_DBG_CTDREQ, ch5_dbg_tcr: CH5_DBG_TCR, - _reserved30: [u8; 0x38], + _reserved31: [u8; 0x38], ch6_dbg_ctdreq: CH6_DBG_CTDREQ, ch6_dbg_tcr: CH6_DBG_TCR, - _reserved32: [u8; 0x38], + _reserved33: [u8; 0x38], ch7_dbg_ctdreq: CH7_DBG_CTDREQ, ch7_dbg_tcr: CH7_DBG_TCR, - _reserved34: [u8; 0x38], + _reserved35: [u8; 0x38], ch8_dbg_ctdreq: CH8_DBG_CTDREQ, ch8_dbg_tcr: CH8_DBG_TCR, - _reserved36: [u8; 0x38], + _reserved37: [u8; 0x38], ch9_dbg_ctdreq: CH9_DBG_CTDREQ, ch9_dbg_tcr: CH9_DBG_TCR, - _reserved38: [u8; 0x38], + _reserved39: [u8; 0x38], ch10_dbg_ctdreq: CH10_DBG_CTDREQ, ch10_dbg_tcr: CH10_DBG_TCR, - _reserved40: [u8; 0x38], + _reserved41: [u8; 0x38], ch11_dbg_ctdreq: CH11_DBG_CTDREQ, ch11_dbg_tcr: CH11_DBG_TCR, } @@ -91,6 +91,11 @@ impl RegisterBlock { pub const fn ints0(&self) -> &INTS0 { &self.ints0 } + #[doc = "0x410 - Interrupt Status (raw)"] + #[inline(always)] + pub const fn intr1(&self) -> &INTR1 { + &self.intr1 + } #[doc = "0x414 - Interrupt Enables for IRQ 1"] #[inline(always)] pub const fn inte1(&self) -> &INTE1 { @@ -106,26 +111,22 @@ impl RegisterBlock { pub const fn ints1(&self) -> &INTS1 { &self.ints1 } - #[doc = "0x420 - Pacing (X/Y) Fractional Timer - The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less."] + #[doc = "0x420 - Pacing (X/Y) Fractional Timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less."] #[inline(always)] pub const fn timer0(&self) -> &TIMER0 { &self.timer0 } - #[doc = "0x424 - Pacing (X/Y) Fractional Timer - The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less."] + #[doc = "0x424 - Pacing (X/Y) Fractional Timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less."] #[inline(always)] pub const fn timer1(&self) -> &TIMER1 { &self.timer1 } - #[doc = "0x428 - Pacing (X/Y) Fractional Timer - The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less."] + #[doc = "0x428 - Pacing (X/Y) Fractional Timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less."] #[inline(always)] pub const fn timer2(&self) -> &TIMER2 { &self.timer2 } - #[doc = "0x42c - Pacing (X/Y) Fractional Timer - The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less."] + #[doc = "0x42c - Pacing (X/Y) Fractional Timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less."] #[inline(always)] pub const fn timer3(&self) -> &TIMER3 { &self.timer3 @@ -140,8 +141,7 @@ impl RegisterBlock { pub const fn sniff_ctrl(&self) -> &SNIFF_CTRL { &self.sniff_ctrl } - #[doc = "0x438 - Data accumulator for sniff hardware - Write an initial seed value here before starting a DMA transfer on the channel indicated by SNIFF_CTRL_DMACH. The hardware will update this register each time it observes a read from the indicated channel. Once the channel completes, the final result can be read from this register."] + #[doc = "0x438 - Data accumulator for sniff hardware"] #[inline(always)] pub const fn sniff_data(&self) -> &SNIFF_DATA { &self.sniff_data @@ -323,6 +323,15 @@ module"] pub type INTS0 = crate::Reg; #[doc = "Interrupt Status for IRQ 0"] pub mod ints0; +#[doc = "INTR1 (rw) register accessor: Interrupt Status (raw) + +You can [`read`](crate::generic::Reg::read) this register and get [`intr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@intr1`] +module"] +pub type INTR1 = crate::Reg; +#[doc = "Interrupt Status (raw)"] +pub mod intr1; #[doc = "INTE1 (rw) register accessor: Interrupt Enables for IRQ 1 You can [`read`](crate::generic::Reg::read) this register and get [`inte1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`inte1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). @@ -350,49 +359,41 @@ module"] pub type INTS1 = crate::Reg; #[doc = "Interrupt Status (masked) for IRQ 1"] pub mod ints1; -#[doc = "TIMER0 (rw) register accessor: Pacing (X/Y) Fractional Timer - The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. +#[doc = "TIMER0 (rw) register accessor: Pacing (X/Y) Fractional Timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. You can [`read`](crate::generic::Reg::read) this register and get [`timer0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timer0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@timer0`] module"] pub type TIMER0 = crate::Reg; -#[doc = "Pacing (X/Y) Fractional Timer - The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less."] +#[doc = "Pacing (X/Y) Fractional Timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less."] pub mod timer0; -#[doc = "TIMER1 (rw) register accessor: Pacing (X/Y) Fractional Timer - The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. +#[doc = "TIMER1 (rw) register accessor: Pacing (X/Y) Fractional Timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. You can [`read`](crate::generic::Reg::read) this register and get [`timer1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timer1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@timer1`] module"] pub type TIMER1 = crate::Reg; -#[doc = "Pacing (X/Y) Fractional Timer - The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less."] +#[doc = "Pacing (X/Y) Fractional Timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less."] pub mod timer1; -#[doc = "TIMER2 (rw) register accessor: Pacing (X/Y) Fractional Timer - The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. +#[doc = "TIMER2 (rw) register accessor: Pacing (X/Y) Fractional Timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. You can [`read`](crate::generic::Reg::read) this register and get [`timer2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timer2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@timer2`] module"] pub type TIMER2 = crate::Reg; -#[doc = "Pacing (X/Y) Fractional Timer - The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less."] +#[doc = "Pacing (X/Y) Fractional Timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less."] pub mod timer2; -#[doc = "TIMER3 (rw) register accessor: Pacing (X/Y) Fractional Timer - The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. +#[doc = "TIMER3 (rw) register accessor: Pacing (X/Y) Fractional Timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. You can [`read`](crate::generic::Reg::read) this register and get [`timer3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timer3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@timer3`] module"] pub type TIMER3 = crate::Reg; -#[doc = "Pacing (X/Y) Fractional Timer - The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less."] +#[doc = "Pacing (X/Y) Fractional Timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less."] pub mod timer3; #[doc = "MULTI_CHAN_TRIGGER (rw) register accessor: Trigger one or more channels simultaneously @@ -413,19 +414,17 @@ pub type SNIFF_CTRL = crate::Reg; #[doc = "Sniffer Control"] pub mod sniff_ctrl; #[doc = "SNIFF_DATA (rw) register accessor: Data accumulator for sniff hardware - Write an initial seed value here before starting a DMA transfer on the channel indicated by SNIFF_CTRL_DMACH. The hardware will update this register each time it observes a read from the indicated channel. Once the channel completes, the final result can be read from this register. You can [`read`](crate::generic::Reg::read) this register and get [`sniff_data::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sniff_data::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@sniff_data`] module"] pub type SNIFF_DATA = crate::Reg; -#[doc = "Data accumulator for sniff hardware - Write an initial seed value here before starting a DMA transfer on the channel indicated by SNIFF_CTRL_DMACH. The hardware will update this register each time it observes a read from the indicated channel. Once the channel completes, the final result can be read from this register."] +#[doc = "Data accumulator for sniff hardware"] pub mod sniff_data; -#[doc = "FIFO_LEVELS (r) register accessor: Debug RAF, WAF, TDF levels +#[doc = "FIFO_LEVELS (rw) register accessor: Debug RAF, WAF, TDF levels -You can [`read`](crate::generic::Reg::read) this register and get [`fifo_levels::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`fifo_levels::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo_levels::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@fifo_levels`] module"] @@ -441,9 +440,9 @@ module"] pub type CHAN_ABORT = crate::Reg; #[doc = "Abort an in-progress transfer sequence on one or more channels"] pub mod chan_abort; -#[doc = "N_CHANNELS (r) register accessor: The number of channels this DMA instance is equipped with. This DMA supports up to 16 hardware channels, but can be configured with as few as one, to minimise silicon area. +#[doc = "N_CHANNELS (rw) register accessor: The number of channels this DMA instance is equipped with. This DMA supports up to 16 hardware channels, but can be configured with as few as one, to minimise silicon area. -You can [`read`](crate::generic::Reg::read) this register and get [`n_channels::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`n_channels::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`n_channels::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@n_channels`] module"] @@ -459,9 +458,9 @@ module"] pub type CH0_DBG_CTDREQ = crate::Reg; #[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake."] pub mod ch0_dbg_ctdreq; -#[doc = "CH0_DBG_TCR (r) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer +#[doc = "CH0_DBG_TCR (rw) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer -You can [`read`](crate::generic::Reg::read) this register and get [`ch0_dbg_tcr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`ch0_dbg_tcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch0_dbg_tcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@ch0_dbg_tcr`] module"] @@ -477,9 +476,9 @@ module"] pub type CH1_DBG_CTDREQ = crate::Reg; #[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake."] pub mod ch1_dbg_ctdreq; -#[doc = "CH1_DBG_TCR (r) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer +#[doc = "CH1_DBG_TCR (rw) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer -You can [`read`](crate::generic::Reg::read) this register and get [`ch1_dbg_tcr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`ch1_dbg_tcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch1_dbg_tcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@ch1_dbg_tcr`] module"] @@ -495,9 +494,9 @@ module"] pub type CH2_DBG_CTDREQ = crate::Reg; #[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake."] pub mod ch2_dbg_ctdreq; -#[doc = "CH2_DBG_TCR (r) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer +#[doc = "CH2_DBG_TCR (rw) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer -You can [`read`](crate::generic::Reg::read) this register and get [`ch2_dbg_tcr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`ch2_dbg_tcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch2_dbg_tcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@ch2_dbg_tcr`] module"] @@ -513,9 +512,9 @@ module"] pub type CH3_DBG_CTDREQ = crate::Reg; #[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake."] pub mod ch3_dbg_ctdreq; -#[doc = "CH3_DBG_TCR (r) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer +#[doc = "CH3_DBG_TCR (rw) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer -You can [`read`](crate::generic::Reg::read) this register and get [`ch3_dbg_tcr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`ch3_dbg_tcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch3_dbg_tcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@ch3_dbg_tcr`] module"] @@ -531,9 +530,9 @@ module"] pub type CH4_DBG_CTDREQ = crate::Reg; #[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake."] pub mod ch4_dbg_ctdreq; -#[doc = "CH4_DBG_TCR (r) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer +#[doc = "CH4_DBG_TCR (rw) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer -You can [`read`](crate::generic::Reg::read) this register and get [`ch4_dbg_tcr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`ch4_dbg_tcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch4_dbg_tcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@ch4_dbg_tcr`] module"] @@ -549,9 +548,9 @@ module"] pub type CH5_DBG_CTDREQ = crate::Reg; #[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake."] pub mod ch5_dbg_ctdreq; -#[doc = "CH5_DBG_TCR (r) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer +#[doc = "CH5_DBG_TCR (rw) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer -You can [`read`](crate::generic::Reg::read) this register and get [`ch5_dbg_tcr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`ch5_dbg_tcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch5_dbg_tcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@ch5_dbg_tcr`] module"] @@ -567,9 +566,9 @@ module"] pub type CH6_DBG_CTDREQ = crate::Reg; #[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake."] pub mod ch6_dbg_ctdreq; -#[doc = "CH6_DBG_TCR (r) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer +#[doc = "CH6_DBG_TCR (rw) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer -You can [`read`](crate::generic::Reg::read) this register and get [`ch6_dbg_tcr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`ch6_dbg_tcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch6_dbg_tcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@ch6_dbg_tcr`] module"] @@ -585,9 +584,9 @@ module"] pub type CH7_DBG_CTDREQ = crate::Reg; #[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake."] pub mod ch7_dbg_ctdreq; -#[doc = "CH7_DBG_TCR (r) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer +#[doc = "CH7_DBG_TCR (rw) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer -You can [`read`](crate::generic::Reg::read) this register and get [`ch7_dbg_tcr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`ch7_dbg_tcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch7_dbg_tcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@ch7_dbg_tcr`] module"] @@ -603,9 +602,9 @@ module"] pub type CH8_DBG_CTDREQ = crate::Reg; #[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake."] pub mod ch8_dbg_ctdreq; -#[doc = "CH8_DBG_TCR (r) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer +#[doc = "CH8_DBG_TCR (rw) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer -You can [`read`](crate::generic::Reg::read) this register and get [`ch8_dbg_tcr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`ch8_dbg_tcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch8_dbg_tcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@ch8_dbg_tcr`] module"] @@ -621,9 +620,9 @@ module"] pub type CH9_DBG_CTDREQ = crate::Reg; #[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake."] pub mod ch9_dbg_ctdreq; -#[doc = "CH9_DBG_TCR (r) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer +#[doc = "CH9_DBG_TCR (rw) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer -You can [`read`](crate::generic::Reg::read) this register and get [`ch9_dbg_tcr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`ch9_dbg_tcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch9_dbg_tcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@ch9_dbg_tcr`] module"] @@ -639,9 +638,9 @@ module"] pub type CH10_DBG_CTDREQ = crate::Reg; #[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake."] pub mod ch10_dbg_ctdreq; -#[doc = "CH10_DBG_TCR (r) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer +#[doc = "CH10_DBG_TCR (rw) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer -You can [`read`](crate::generic::Reg::read) this register and get [`ch10_dbg_tcr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`ch10_dbg_tcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch10_dbg_tcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@ch10_dbg_tcr`] module"] @@ -657,9 +656,9 @@ module"] pub type CH11_DBG_CTDREQ = crate::Reg; #[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake."] pub mod ch11_dbg_ctdreq; -#[doc = "CH11_DBG_TCR (r) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer +#[doc = "CH11_DBG_TCR (rw) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer -You can [`read`](crate::generic::Reg::read) this register and get [`ch11_dbg_tcr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`ch11_dbg_tcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch11_dbg_tcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@ch11_dbg_tcr`] module"] diff --git a/src/dma/ch.rs b/src/dma/ch.rs index d00408bfd..a89b66564 100644 --- a/src/dma/ch.rs +++ b/src/dma/ch.rs @@ -19,26 +19,17 @@ pub struct CH { ch_al3_read_addr_trig: CH_AL3_READ_ADDR_TRIG, } impl CH { - #[doc = "0x00 - DMA Channel 0 Read Address pointer - This register updates automatically each time a read completes. The current value is the next address to be read by this channel."] + #[doc = "0x00 - DMA Channel 0 Read Address pointer"] #[inline(always)] pub const fn ch_read_addr(&self) -> &CH_READ_ADDR { &self.ch_read_addr } - #[doc = "0x04 - DMA Channel 0 Write Address pointer - This register updates automatically each time a write completes. The current value is the next address to be written by this channel."] + #[doc = "0x04 - DMA Channel 0 Write Address pointer"] #[inline(always)] pub const fn ch_write_addr(&self) -> &CH_WRITE_ADDR { &self.ch_write_addr } - #[doc = "0x08 - DMA Channel 0 Transfer Count - Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). - - When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. - - Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. - - The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD."] + #[doc = "0x08 - DMA Channel 0 Transfer Count"] #[inline(always)] pub const fn ch_trans_count(&self) -> &CH_TRANS_COUNT { &self.ch_trans_count @@ -63,9 +54,7 @@ impl CH { pub const fn ch_al1_write_addr(&self) -> &CH_AL1_WRITE_ADDR { &self.ch_al1_write_addr } - #[doc = "0x1c - Alias for channel 0 TRANS_COUNT register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel."] + #[doc = "0x1c - Alias for channel 0 TRANS_COUNT register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel."] #[inline(always)] pub const fn ch_al1_trans_count_trig(&self) -> &CH_AL1_TRANS_COUNT_TRIG { &self.ch_al1_trans_count_trig @@ -85,9 +74,7 @@ impl CH { pub const fn ch_al2_read_addr(&self) -> &CH_AL2_READ_ADDR { &self.ch_al2_read_addr } - #[doc = "0x2c - Alias for channel 0 WRITE_ADDR register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel."] + #[doc = "0x2c - Alias for channel 0 WRITE_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel."] #[inline(always)] pub const fn ch_al2_write_addr_trig(&self) -> &CH_AL2_WRITE_ADDR_TRIG { &self.ch_al2_write_addr_trig @@ -107,58 +94,38 @@ impl CH { pub const fn ch_al3_trans_count(&self) -> &CH_AL3_TRANS_COUNT { &self.ch_al3_trans_count } - #[doc = "0x3c - Alias for channel 0 READ_ADDR register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel."] + #[doc = "0x3c - Alias for channel 0 READ_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel."] #[inline(always)] pub const fn ch_al3_read_addr_trig(&self) -> &CH_AL3_READ_ADDR_TRIG { &self.ch_al3_read_addr_trig } } #[doc = "CH_READ_ADDR (rw) register accessor: DMA Channel 0 Read Address pointer - This register updates automatically each time a read completes. The current value is the next address to be read by this channel. You can [`read`](crate::generic::Reg::read) this register and get [`ch_read_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_read_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@ch_read_addr`] module"] pub type CH_READ_ADDR = crate::Reg; -#[doc = "DMA Channel 0 Read Address pointer - This register updates automatically each time a read completes. The current value is the next address to be read by this channel."] +#[doc = "DMA Channel 0 Read Address pointer"] pub mod ch_read_addr; #[doc = "CH_WRITE_ADDR (rw) register accessor: DMA Channel 0 Write Address pointer - This register updates automatically each time a write completes. The current value is the next address to be written by this channel. You can [`read`](crate::generic::Reg::read) this register and get [`ch_write_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_write_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@ch_write_addr`] module"] pub type CH_WRITE_ADDR = crate::Reg; -#[doc = "DMA Channel 0 Write Address pointer - This register updates automatically each time a write completes. The current value is the next address to be written by this channel."] +#[doc = "DMA Channel 0 Write Address pointer"] pub mod ch_write_addr; #[doc = "CH_TRANS_COUNT (rw) register accessor: DMA Channel 0 Transfer Count - Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). - - When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. - - Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. - - The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. You can [`read`](crate::generic::Reg::read) this register and get [`ch_trans_count::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_trans_count::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@ch_trans_count`] module"] pub type CH_TRANS_COUNT = crate::Reg; -#[doc = "DMA Channel 0 Transfer Count - Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). - - When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. - - Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. - - The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD."] +#[doc = "DMA Channel 0 Transfer Count"] pub mod ch_trans_count; #[doc = "CH_CTRL_TRIG (rw) register accessor: DMA Channel 0 Control and Status @@ -196,9 +163,7 @@ module"] pub type CH_AL1_WRITE_ADDR = crate::Reg; #[doc = "Alias for channel 0 WRITE_ADDR register"] pub mod ch_al1_write_addr; -#[doc = "CH_AL1_TRANS_COUNT_TRIG (rw) register accessor: Alias for channel 0 TRANS_COUNT register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. +#[doc = "CH_AL1_TRANS_COUNT_TRIG (rw) register accessor: Alias for channel 0 TRANS_COUNT register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. You can [`read`](crate::generic::Reg::read) this register and get [`ch_al1_trans_count_trig::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_al1_trans_count_trig::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). @@ -206,9 +171,7 @@ For information about available fields see [`mod@ch_al1_trans_count_trig`] module"] pub type CH_AL1_TRANS_COUNT_TRIG = crate::Reg; -#[doc = "Alias for channel 0 TRANS_COUNT register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel."] +#[doc = "Alias for channel 0 TRANS_COUNT register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel."] pub mod ch_al1_trans_count_trig; #[doc = "CH_AL2_CTRL (rw) register accessor: DMA Channel 0 Control and Status @@ -237,18 +200,14 @@ module"] pub type CH_AL2_READ_ADDR = crate::Reg; #[doc = "Alias for channel 0 READ_ADDR register"] pub mod ch_al2_read_addr; -#[doc = "CH_AL2_WRITE_ADDR_TRIG (rw) register accessor: Alias for channel 0 WRITE_ADDR register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. +#[doc = "CH_AL2_WRITE_ADDR_TRIG (rw) register accessor: Alias for channel 0 WRITE_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. You can [`read`](crate::generic::Reg::read) this register and get [`ch_al2_write_addr_trig::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_al2_write_addr_trig::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@ch_al2_write_addr_trig`] module"] pub type CH_AL2_WRITE_ADDR_TRIG = crate::Reg; -#[doc = "Alias for channel 0 WRITE_ADDR register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel."] +#[doc = "Alias for channel 0 WRITE_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel."] pub mod ch_al2_write_addr_trig; #[doc = "CH_AL3_CTRL (rw) register accessor: DMA Channel 0 Control and Status @@ -277,16 +236,12 @@ module"] pub type CH_AL3_TRANS_COUNT = crate::Reg; #[doc = "Alias for channel 0 TRANS_COUNT register"] pub mod ch_al3_trans_count; -#[doc = "CH_AL3_READ_ADDR_TRIG (rw) register accessor: Alias for channel 0 READ_ADDR register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. +#[doc = "CH_AL3_READ_ADDR_TRIG (rw) register accessor: Alias for channel 0 READ_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. You can [`read`](crate::generic::Reg::read) this register and get [`ch_al3_read_addr_trig::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_al3_read_addr_trig::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@ch_al3_read_addr_trig`] module"] pub type CH_AL3_READ_ADDR_TRIG = crate::Reg; -#[doc = "Alias for channel 0 READ_ADDR register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel."] +#[doc = "Alias for channel 0 READ_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel."] pub mod ch_al3_read_addr_trig; diff --git a/src/dma/ch/ch_al1_ctrl.rs b/src/dma/ch/ch_al1_ctrl.rs index 36865c3d9..c17b4ca31 100644 --- a/src/dma/ch/ch_al1_ctrl.rs +++ b/src/dma/ch/ch_al1_ctrl.rs @@ -2,19 +2,13 @@ pub type R = crate::R; #[doc = "Register `CH_AL1_CTRL` writer"] pub type W = crate::W; -#[doc = "Field `EN` reader - DMA Channel Enable. - When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"] +#[doc = "Field `EN` reader - DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"] pub type EN_R = crate::BitReader; -#[doc = "Field `EN` writer - DMA Channel Enable. - When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"] +#[doc = "Field `EN` writer - DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"] pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `HIGH_PRIORITY` reader - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. - - This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."] +#[doc = "Field `HIGH_PRIORITY` reader - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."] pub type HIGH_PRIORITY_R = crate::BitReader; -#[doc = "Field `HIGH_PRIORITY` writer - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. - - This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."] +#[doc = "Field `HIGH_PRIORITY` writer - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."] pub type HIGH_PRIORITY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. @@ -90,25 +84,15 @@ where self.variant(DATA_SIZE_A::SIZE_WORD) } } -#[doc = "Field `INCR_READ` reader - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. - - Generally this should be disabled for peripheral-to-memory transfers."] +#[doc = "Field `INCR_READ` reader - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers."] pub type INCR_READ_R = crate::BitReader; -#[doc = "Field `INCR_READ` writer - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. - - Generally this should be disabled for peripheral-to-memory transfers."] +#[doc = "Field `INCR_READ` writer - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers."] pub type INCR_READ_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `INCR_WRITE` reader - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. - - Generally this should be disabled for memory-to-peripheral transfers."] +#[doc = "Field `INCR_WRITE` reader - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers."] pub type INCR_WRITE_R = crate::BitReader; -#[doc = "Field `INCR_WRITE` writer - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. - - Generally this should be disabled for memory-to-peripheral transfers."] +#[doc = "Field `INCR_WRITE` writer - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers."] pub type INCR_WRITE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. - - Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. +#[doc = "Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. Value on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -126,9 +110,7 @@ impl From for u8 { impl crate::FieldSpec for RING_SIZE_A { type Ux = u8; } -#[doc = "Field `RING_SIZE` reader - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. - - Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] +#[doc = "Field `RING_SIZE` reader - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] pub type RING_SIZE_R = crate::FieldReader; impl RING_SIZE_R { #[doc = "Get enumerated values variant"] @@ -145,9 +127,7 @@ impl RING_SIZE_R { *self == RING_SIZE_A::RING_NONE } } -#[doc = "Field `RING_SIZE` writer - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. - - Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] +#[doc = "Field `RING_SIZE` writer - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] pub type RING_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 4, RING_SIZE_A>; impl<'a, REG> RING_SIZE_W<'a, REG> where @@ -160,11 +140,9 @@ where self.variant(RING_SIZE_A::RING_NONE) } } -#[doc = "Field `RING_SEL` reader - Select whether RING_SIZE applies to read or write addresses. - If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."] +#[doc = "Field `RING_SEL` reader - Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."] pub type RING_SEL_R = crate::BitReader; -#[doc = "Field `RING_SEL` writer - Select whether RING_SIZE applies to read or write addresses. - If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."] +#[doc = "Field `RING_SEL` writer - Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."] pub type RING_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `CHAIN_TO` reader - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. Reset value is 0, which means for channels 1 and above the default will be to chain to channel 0 - set this field to avoid this behaviour."] @@ -172,9 +150,7 @@ pub type CHAIN_TO_R = crate::FieldReader; #[doc = "Field `CHAIN_TO` writer - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. Reset value is 0, which means for channels 1 and above the default will be to chain to channel 0 - set this field to avoid this behaviour."] pub type CHAIN_TO_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Select a Transfer Request signal. - The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). - 0x0 to 0x3a -> select DREQ n as TREQ +#[doc = "Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ Value on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -280,9 +256,7 @@ impl From for u8 { impl crate::FieldSpec for TREQ_SEL_A { type Ux = u8; } -#[doc = "Field `TREQ_SEL` reader - Select a Transfer Request signal. - The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). - 0x0 to 0x3a -> select DREQ n as TREQ"] +#[doc = "Field `TREQ_SEL` reader - Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ"] pub type TREQ_SEL_R = crate::FieldReader; impl TREQ_SEL_R { #[doc = "Get enumerated values variant"] @@ -563,9 +537,7 @@ impl TREQ_SEL_R { *self == TREQ_SEL_A::PERMANENT } } -#[doc = "Field `TREQ_SEL` writer - Select a Transfer Request signal. - The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). - 0x0 to 0x3a -> select DREQ n as TREQ"] +#[doc = "Field `TREQ_SEL` writer - Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ"] pub type TREQ_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6, TREQ_SEL_A>; impl<'a, REG> TREQ_SEL_W<'a, REG> where @@ -798,56 +770,37 @@ where self.variant(TREQ_SEL_A::PERMANENT) } } -#[doc = "Field `IRQ_QUIET` reader - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. - - This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."] +#[doc = "Field `IRQ_QUIET` reader - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."] pub type IRQ_QUIET_R = crate::BitReader; -#[doc = "Field `IRQ_QUIET` writer - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. - - This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."] +#[doc = "Field `IRQ_QUIET` writer - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."] pub type IRQ_QUIET_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BSWAP` reader - Apply byte-swap transformation to DMA data. - For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."] +#[doc = "Field `BSWAP` reader - Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."] pub type BSWAP_R = crate::BitReader; -#[doc = "Field `BSWAP` writer - Apply byte-swap transformation to DMA data. - For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."] +#[doc = "Field `BSWAP` writer - Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."] pub type BSWAP_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SNIFF_EN` reader - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. - - This allows checksum to be enabled or disabled on a per-control- block basis."] +#[doc = "Field `SNIFF_EN` reader - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis."] pub type SNIFF_EN_R = crate::BitReader; -#[doc = "Field `SNIFF_EN` writer - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. - - This allows checksum to be enabled or disabled on a per-control- block basis."] +#[doc = "Field `SNIFF_EN` writer - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis."] pub type SNIFF_EN_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BUSY` reader - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. - - To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT."] +#[doc = "Field `BUSY` reader - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT."] pub type BUSY_R = crate::BitReader; -#[doc = "Field `WRITE_ERROR` reader - If 1, the channel received a write bus error. Write one to clear. - WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)"] +#[doc = "Field `WRITE_ERROR` reader - If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)"] pub type WRITE_ERROR_R = crate::BitReader; -#[doc = "Field `WRITE_ERROR` writer - If 1, the channel received a write bus error. Write one to clear. - WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)"] +#[doc = "Field `WRITE_ERROR` writer - If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)"] pub type WRITE_ERROR_W<'a, REG> = crate::BitWriter1C<'a, REG>; -#[doc = "Field `READ_ERROR` reader - If 1, the channel received a read bus error. Write one to clear. - READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)"] +#[doc = "Field `READ_ERROR` reader - If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)"] pub type READ_ERROR_R = crate::BitReader; -#[doc = "Field `READ_ERROR` writer - If 1, the channel received a read bus error. Write one to clear. - READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)"] +#[doc = "Field `READ_ERROR` writer - If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)"] pub type READ_ERROR_W<'a, REG> = crate::BitWriter1C<'a, REG>; #[doc = "Field `AHB_ERROR` reader - Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag."] pub type AHB_ERROR_R = crate::BitReader; impl R { - #[doc = "Bit 0 - DMA Channel Enable. - When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"] + #[doc = "Bit 0 - DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"] #[inline(always)] pub fn en(&self) -> EN_R { EN_R::new((self.bits & 1) != 0) } - #[doc = "Bit 1 - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. - - This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."] + #[doc = "Bit 1 - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."] #[inline(always)] pub fn high_priority(&self) -> HIGH_PRIORITY_R { HIGH_PRIORITY_R::new(((self.bits >> 1) & 1) != 0) @@ -857,29 +810,22 @@ impl R { pub fn data_size(&self) -> DATA_SIZE_R { DATA_SIZE_R::new(((self.bits >> 2) & 3) as u8) } - #[doc = "Bit 4 - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. - - Generally this should be disabled for peripheral-to-memory transfers."] + #[doc = "Bit 4 - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers."] #[inline(always)] pub fn incr_read(&self) -> INCR_READ_R { INCR_READ_R::new(((self.bits >> 4) & 1) != 0) } - #[doc = "Bit 5 - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. - - Generally this should be disabled for memory-to-peripheral transfers."] + #[doc = "Bit 5 - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers."] #[inline(always)] pub fn incr_write(&self) -> INCR_WRITE_R { INCR_WRITE_R::new(((self.bits >> 5) & 1) != 0) } - #[doc = "Bits 6:9 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. - - Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] + #[doc = "Bits 6:9 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] #[inline(always)] pub fn ring_size(&self) -> RING_SIZE_R { RING_SIZE_R::new(((self.bits >> 6) & 0x0f) as u8) } - #[doc = "Bit 10 - Select whether RING_SIZE applies to read or write addresses. - If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."] + #[doc = "Bit 10 - Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."] #[inline(always)] pub fn ring_sel(&self) -> RING_SEL_R { RING_SEL_R::new(((self.bits >> 10) & 1) != 0) @@ -890,48 +836,37 @@ impl R { pub fn chain_to(&self) -> CHAIN_TO_R { CHAIN_TO_R::new(((self.bits >> 11) & 0x0f) as u8) } - #[doc = "Bits 15:20 - Select a Transfer Request signal. - The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). - 0x0 to 0x3a -> select DREQ n as TREQ"] + #[doc = "Bits 15:20 - Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ"] #[inline(always)] pub fn treq_sel(&self) -> TREQ_SEL_R { TREQ_SEL_R::new(((self.bits >> 15) & 0x3f) as u8) } - #[doc = "Bit 21 - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. - - This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."] + #[doc = "Bit 21 - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."] #[inline(always)] pub fn irq_quiet(&self) -> IRQ_QUIET_R { IRQ_QUIET_R::new(((self.bits >> 21) & 1) != 0) } - #[doc = "Bit 22 - Apply byte-swap transformation to DMA data. - For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."] + #[doc = "Bit 22 - Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."] #[inline(always)] pub fn bswap(&self) -> BSWAP_R { BSWAP_R::new(((self.bits >> 22) & 1) != 0) } - #[doc = "Bit 23 - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. - - This allows checksum to be enabled or disabled on a per-control- block basis."] + #[doc = "Bit 23 - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis."] #[inline(always)] pub fn sniff_en(&self) -> SNIFF_EN_R { SNIFF_EN_R::new(((self.bits >> 23) & 1) != 0) } - #[doc = "Bit 24 - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. - - To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT."] + #[doc = "Bit 24 - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT."] #[inline(always)] pub fn busy(&self) -> BUSY_R { BUSY_R::new(((self.bits >> 24) & 1) != 0) } - #[doc = "Bit 29 - If 1, the channel received a write bus error. Write one to clear. - WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)"] + #[doc = "Bit 29 - If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)"] #[inline(always)] pub fn write_error(&self) -> WRITE_ERROR_R { WRITE_ERROR_R::new(((self.bits >> 29) & 1) != 0) } - #[doc = "Bit 30 - If 1, the channel received a read bus error. Write one to clear. - READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)"] + #[doc = "Bit 30 - If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)"] #[inline(always)] pub fn read_error(&self) -> READ_ERROR_R { READ_ERROR_R::new(((self.bits >> 30) & 1) != 0) @@ -943,16 +878,13 @@ impl R { } } impl W { - #[doc = "Bit 0 - DMA Channel Enable. - When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"] + #[doc = "Bit 0 - DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"] #[inline(always)] #[must_use] pub fn en(&mut self) -> EN_W { EN_W::new(self, 0) } - #[doc = "Bit 1 - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. - - This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."] + #[doc = "Bit 1 - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."] #[inline(always)] #[must_use] pub fn high_priority(&mut self) -> HIGH_PRIORITY_W { @@ -964,32 +896,25 @@ impl W { pub fn data_size(&mut self) -> DATA_SIZE_W { DATA_SIZE_W::new(self, 2) } - #[doc = "Bit 4 - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. - - Generally this should be disabled for peripheral-to-memory transfers."] + #[doc = "Bit 4 - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers."] #[inline(always)] #[must_use] pub fn incr_read(&mut self) -> INCR_READ_W { INCR_READ_W::new(self, 4) } - #[doc = "Bit 5 - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. - - Generally this should be disabled for memory-to-peripheral transfers."] + #[doc = "Bit 5 - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers."] #[inline(always)] #[must_use] pub fn incr_write(&mut self) -> INCR_WRITE_W { INCR_WRITE_W::new(self, 5) } - #[doc = "Bits 6:9 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. - - Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] + #[doc = "Bits 6:9 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] #[inline(always)] #[must_use] pub fn ring_size(&mut self) -> RING_SIZE_W { RING_SIZE_W::new(self, 6) } - #[doc = "Bit 10 - Select whether RING_SIZE applies to read or write addresses. - If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."] + #[doc = "Bit 10 - Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."] #[inline(always)] #[must_use] pub fn ring_sel(&mut self) -> RING_SEL_W { @@ -1002,46 +927,37 @@ impl W { pub fn chain_to(&mut self) -> CHAIN_TO_W { CHAIN_TO_W::new(self, 11) } - #[doc = "Bits 15:20 - Select a Transfer Request signal. - The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). - 0x0 to 0x3a -> select DREQ n as TREQ"] + #[doc = "Bits 15:20 - Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ"] #[inline(always)] #[must_use] pub fn treq_sel(&mut self) -> TREQ_SEL_W { TREQ_SEL_W::new(self, 15) } - #[doc = "Bit 21 - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. - - This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."] + #[doc = "Bit 21 - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."] #[inline(always)] #[must_use] pub fn irq_quiet(&mut self) -> IRQ_QUIET_W { IRQ_QUIET_W::new(self, 21) } - #[doc = "Bit 22 - Apply byte-swap transformation to DMA data. - For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."] + #[doc = "Bit 22 - Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."] #[inline(always)] #[must_use] pub fn bswap(&mut self) -> BSWAP_W { BSWAP_W::new(self, 22) } - #[doc = "Bit 23 - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. - - This allows checksum to be enabled or disabled on a per-control- block basis."] + #[doc = "Bit 23 - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis."] #[inline(always)] #[must_use] pub fn sniff_en(&mut self) -> SNIFF_EN_W { SNIFF_EN_W::new(self, 23) } - #[doc = "Bit 29 - If 1, the channel received a write bus error. Write one to clear. - WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)"] + #[doc = "Bit 29 - If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)"] #[inline(always)] #[must_use] pub fn write_error(&mut self) -> WRITE_ERROR_W { WRITE_ERROR_W::new(self, 29) } - #[doc = "Bit 30 - If 1, the channel received a read bus error. Write one to clear. - READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)"] + #[doc = "Bit 30 - If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)"] #[inline(always)] #[must_use] pub fn read_error(&mut self) -> READ_ERROR_W { diff --git a/src/dma/ch/ch_al1_read_addr.rs b/src/dma/ch/ch_al1_read_addr.rs index 006c80538..50cabd0f1 100644 --- a/src/dma/ch/ch_al1_read_addr.rs +++ b/src/dma/ch/ch_al1_read_addr.rs @@ -2,17 +2,25 @@ pub type R = crate::R; #[doc = "Register `CH_AL1_READ_ADDR` writer"] pub type W = crate::W; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) +#[doc = "Field `CH0_AL1_READ_ADDR` reader - "] +pub type CH0_AL1_READ_ADDR_R = crate::FieldReader; +#[doc = "Field `CH0_AL1_READ_ADDR` writer - "] +pub type CH0_AL1_READ_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn ch0_al1_read_addr(&self) -> CH0_AL1_READ_ADDR_R { + CH0_AL1_READ_ADDR_R::new(self.bits) } } -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn ch0_al1_read_addr(&mut self) -> CH0_AL1_READ_ADDR_W { + CH0_AL1_READ_ADDR_W::new(self, 0) } } -impl W {} #[doc = "Alias for channel 0 READ_ADDR register You can [`read`](crate::generic::Reg::read) this register and get [`ch_al1_read_addr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_al1_read_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] diff --git a/src/dma/ch/ch_al1_trans_count_trig.rs b/src/dma/ch/ch_al1_trans_count_trig.rs index 37ed300d8..007bf3403 100644 --- a/src/dma/ch/ch_al1_trans_count_trig.rs +++ b/src/dma/ch/ch_al1_trans_count_trig.rs @@ -2,20 +2,28 @@ pub type R = crate::R; #[doc = "Register `CH_AL1_TRANS_COUNT_TRIG` writer"] pub type W = crate::W; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) +#[doc = "Field `CH0_AL1_TRANS_COUNT_TRIG` reader - "] +pub type CH0_AL1_TRANS_COUNT_TRIG_R = crate::FieldReader; +#[doc = "Field `CH0_AL1_TRANS_COUNT_TRIG` writer - "] +pub type CH0_AL1_TRANS_COUNT_TRIG_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn ch0_al1_trans_count_trig(&self) -> CH0_AL1_TRANS_COUNT_TRIG_R { + CH0_AL1_TRANS_COUNT_TRIG_R::new(self.bits) } } -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn ch0_al1_trans_count_trig( + &mut self, + ) -> CH0_AL1_TRANS_COUNT_TRIG_W { + CH0_AL1_TRANS_COUNT_TRIG_W::new(self, 0) } } -impl W {} -#[doc = "Alias for channel 0 TRANS_COUNT register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. +#[doc = "Alias for channel 0 TRANS_COUNT register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. You can [`read`](crate::generic::Reg::read) this register and get [`ch_al1_trans_count_trig::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_al1_trans_count_trig::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CH_AL1_TRANS_COUNT_TRIG_SPEC; diff --git a/src/dma/ch/ch_al1_write_addr.rs b/src/dma/ch/ch_al1_write_addr.rs index 749156fec..7d15cb5ed 100644 --- a/src/dma/ch/ch_al1_write_addr.rs +++ b/src/dma/ch/ch_al1_write_addr.rs @@ -2,17 +2,25 @@ pub type R = crate::R; #[doc = "Register `CH_AL1_WRITE_ADDR` writer"] pub type W = crate::W; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) +#[doc = "Field `CH0_AL1_WRITE_ADDR` reader - "] +pub type CH0_AL1_WRITE_ADDR_R = crate::FieldReader; +#[doc = "Field `CH0_AL1_WRITE_ADDR` writer - "] +pub type CH0_AL1_WRITE_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn ch0_al1_write_addr(&self) -> CH0_AL1_WRITE_ADDR_R { + CH0_AL1_WRITE_ADDR_R::new(self.bits) } } -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn ch0_al1_write_addr(&mut self) -> CH0_AL1_WRITE_ADDR_W { + CH0_AL1_WRITE_ADDR_W::new(self, 0) } } -impl W {} #[doc = "Alias for channel 0 WRITE_ADDR register You can [`read`](crate::generic::Reg::read) this register and get [`ch_al1_write_addr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_al1_write_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] diff --git a/src/dma/ch/ch_al2_ctrl.rs b/src/dma/ch/ch_al2_ctrl.rs index dcf6e4082..89a575694 100644 --- a/src/dma/ch/ch_al2_ctrl.rs +++ b/src/dma/ch/ch_al2_ctrl.rs @@ -2,19 +2,13 @@ pub type R = crate::R; #[doc = "Register `CH_AL2_CTRL` writer"] pub type W = crate::W; -#[doc = "Field `EN` reader - DMA Channel Enable. - When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"] +#[doc = "Field `EN` reader - DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"] pub type EN_R = crate::BitReader; -#[doc = "Field `EN` writer - DMA Channel Enable. - When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"] +#[doc = "Field `EN` writer - DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"] pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `HIGH_PRIORITY` reader - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. - - This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."] +#[doc = "Field `HIGH_PRIORITY` reader - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."] pub type HIGH_PRIORITY_R = crate::BitReader; -#[doc = "Field `HIGH_PRIORITY` writer - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. - - This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."] +#[doc = "Field `HIGH_PRIORITY` writer - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."] pub type HIGH_PRIORITY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. @@ -90,25 +84,15 @@ where self.variant(DATA_SIZE_A::SIZE_WORD) } } -#[doc = "Field `INCR_READ` reader - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. - - Generally this should be disabled for peripheral-to-memory transfers."] +#[doc = "Field `INCR_READ` reader - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers."] pub type INCR_READ_R = crate::BitReader; -#[doc = "Field `INCR_READ` writer - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. - - Generally this should be disabled for peripheral-to-memory transfers."] +#[doc = "Field `INCR_READ` writer - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers."] pub type INCR_READ_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `INCR_WRITE` reader - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. - - Generally this should be disabled for memory-to-peripheral transfers."] +#[doc = "Field `INCR_WRITE` reader - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers."] pub type INCR_WRITE_R = crate::BitReader; -#[doc = "Field `INCR_WRITE` writer - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. - - Generally this should be disabled for memory-to-peripheral transfers."] +#[doc = "Field `INCR_WRITE` writer - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers."] pub type INCR_WRITE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. - - Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. +#[doc = "Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. Value on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -126,9 +110,7 @@ impl From for u8 { impl crate::FieldSpec for RING_SIZE_A { type Ux = u8; } -#[doc = "Field `RING_SIZE` reader - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. - - Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] +#[doc = "Field `RING_SIZE` reader - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] pub type RING_SIZE_R = crate::FieldReader; impl RING_SIZE_R { #[doc = "Get enumerated values variant"] @@ -145,9 +127,7 @@ impl RING_SIZE_R { *self == RING_SIZE_A::RING_NONE } } -#[doc = "Field `RING_SIZE` writer - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. - - Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] +#[doc = "Field `RING_SIZE` writer - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] pub type RING_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 4, RING_SIZE_A>; impl<'a, REG> RING_SIZE_W<'a, REG> where @@ -160,11 +140,9 @@ where self.variant(RING_SIZE_A::RING_NONE) } } -#[doc = "Field `RING_SEL` reader - Select whether RING_SIZE applies to read or write addresses. - If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."] +#[doc = "Field `RING_SEL` reader - Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."] pub type RING_SEL_R = crate::BitReader; -#[doc = "Field `RING_SEL` writer - Select whether RING_SIZE applies to read or write addresses. - If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."] +#[doc = "Field `RING_SEL` writer - Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."] pub type RING_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `CHAIN_TO` reader - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. Reset value is 0, which means for channels 1 and above the default will be to chain to channel 0 - set this field to avoid this behaviour."] @@ -172,9 +150,7 @@ pub type CHAIN_TO_R = crate::FieldReader; #[doc = "Field `CHAIN_TO` writer - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. Reset value is 0, which means for channels 1 and above the default will be to chain to channel 0 - set this field to avoid this behaviour."] pub type CHAIN_TO_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Select a Transfer Request signal. - The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). - 0x0 to 0x3a -> select DREQ n as TREQ +#[doc = "Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ Value on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -280,9 +256,7 @@ impl From for u8 { impl crate::FieldSpec for TREQ_SEL_A { type Ux = u8; } -#[doc = "Field `TREQ_SEL` reader - Select a Transfer Request signal. - The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). - 0x0 to 0x3a -> select DREQ n as TREQ"] +#[doc = "Field `TREQ_SEL` reader - Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ"] pub type TREQ_SEL_R = crate::FieldReader; impl TREQ_SEL_R { #[doc = "Get enumerated values variant"] @@ -563,9 +537,7 @@ impl TREQ_SEL_R { *self == TREQ_SEL_A::PERMANENT } } -#[doc = "Field `TREQ_SEL` writer - Select a Transfer Request signal. - The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). - 0x0 to 0x3a -> select DREQ n as TREQ"] +#[doc = "Field `TREQ_SEL` writer - Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ"] pub type TREQ_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6, TREQ_SEL_A>; impl<'a, REG> TREQ_SEL_W<'a, REG> where @@ -798,56 +770,37 @@ where self.variant(TREQ_SEL_A::PERMANENT) } } -#[doc = "Field `IRQ_QUIET` reader - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. - - This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."] +#[doc = "Field `IRQ_QUIET` reader - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."] pub type IRQ_QUIET_R = crate::BitReader; -#[doc = "Field `IRQ_QUIET` writer - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. - - This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."] +#[doc = "Field `IRQ_QUIET` writer - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."] pub type IRQ_QUIET_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BSWAP` reader - Apply byte-swap transformation to DMA data. - For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."] +#[doc = "Field `BSWAP` reader - Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."] pub type BSWAP_R = crate::BitReader; -#[doc = "Field `BSWAP` writer - Apply byte-swap transformation to DMA data. - For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."] +#[doc = "Field `BSWAP` writer - Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."] pub type BSWAP_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SNIFF_EN` reader - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. - - This allows checksum to be enabled or disabled on a per-control- block basis."] +#[doc = "Field `SNIFF_EN` reader - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis."] pub type SNIFF_EN_R = crate::BitReader; -#[doc = "Field `SNIFF_EN` writer - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. - - This allows checksum to be enabled or disabled on a per-control- block basis."] +#[doc = "Field `SNIFF_EN` writer - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis."] pub type SNIFF_EN_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BUSY` reader - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. - - To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT."] +#[doc = "Field `BUSY` reader - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT."] pub type BUSY_R = crate::BitReader; -#[doc = "Field `WRITE_ERROR` reader - If 1, the channel received a write bus error. Write one to clear. - WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)"] +#[doc = "Field `WRITE_ERROR` reader - If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)"] pub type WRITE_ERROR_R = crate::BitReader; -#[doc = "Field `WRITE_ERROR` writer - If 1, the channel received a write bus error. Write one to clear. - WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)"] +#[doc = "Field `WRITE_ERROR` writer - If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)"] pub type WRITE_ERROR_W<'a, REG> = crate::BitWriter1C<'a, REG>; -#[doc = "Field `READ_ERROR` reader - If 1, the channel received a read bus error. Write one to clear. - READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)"] +#[doc = "Field `READ_ERROR` reader - If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)"] pub type READ_ERROR_R = crate::BitReader; -#[doc = "Field `READ_ERROR` writer - If 1, the channel received a read bus error. Write one to clear. - READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)"] +#[doc = "Field `READ_ERROR` writer - If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)"] pub type READ_ERROR_W<'a, REG> = crate::BitWriter1C<'a, REG>; #[doc = "Field `AHB_ERROR` reader - Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag."] pub type AHB_ERROR_R = crate::BitReader; impl R { - #[doc = "Bit 0 - DMA Channel Enable. - When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"] + #[doc = "Bit 0 - DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"] #[inline(always)] pub fn en(&self) -> EN_R { EN_R::new((self.bits & 1) != 0) } - #[doc = "Bit 1 - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. - - This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."] + #[doc = "Bit 1 - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."] #[inline(always)] pub fn high_priority(&self) -> HIGH_PRIORITY_R { HIGH_PRIORITY_R::new(((self.bits >> 1) & 1) != 0) @@ -857,29 +810,22 @@ impl R { pub fn data_size(&self) -> DATA_SIZE_R { DATA_SIZE_R::new(((self.bits >> 2) & 3) as u8) } - #[doc = "Bit 4 - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. - - Generally this should be disabled for peripheral-to-memory transfers."] + #[doc = "Bit 4 - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers."] #[inline(always)] pub fn incr_read(&self) -> INCR_READ_R { INCR_READ_R::new(((self.bits >> 4) & 1) != 0) } - #[doc = "Bit 5 - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. - - Generally this should be disabled for memory-to-peripheral transfers."] + #[doc = "Bit 5 - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers."] #[inline(always)] pub fn incr_write(&self) -> INCR_WRITE_R { INCR_WRITE_R::new(((self.bits >> 5) & 1) != 0) } - #[doc = "Bits 6:9 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. - - Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] + #[doc = "Bits 6:9 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] #[inline(always)] pub fn ring_size(&self) -> RING_SIZE_R { RING_SIZE_R::new(((self.bits >> 6) & 0x0f) as u8) } - #[doc = "Bit 10 - Select whether RING_SIZE applies to read or write addresses. - If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."] + #[doc = "Bit 10 - Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."] #[inline(always)] pub fn ring_sel(&self) -> RING_SEL_R { RING_SEL_R::new(((self.bits >> 10) & 1) != 0) @@ -890,48 +836,37 @@ impl R { pub fn chain_to(&self) -> CHAIN_TO_R { CHAIN_TO_R::new(((self.bits >> 11) & 0x0f) as u8) } - #[doc = "Bits 15:20 - Select a Transfer Request signal. - The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). - 0x0 to 0x3a -> select DREQ n as TREQ"] + #[doc = "Bits 15:20 - Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ"] #[inline(always)] pub fn treq_sel(&self) -> TREQ_SEL_R { TREQ_SEL_R::new(((self.bits >> 15) & 0x3f) as u8) } - #[doc = "Bit 21 - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. - - This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."] + #[doc = "Bit 21 - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."] #[inline(always)] pub fn irq_quiet(&self) -> IRQ_QUIET_R { IRQ_QUIET_R::new(((self.bits >> 21) & 1) != 0) } - #[doc = "Bit 22 - Apply byte-swap transformation to DMA data. - For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."] + #[doc = "Bit 22 - Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."] #[inline(always)] pub fn bswap(&self) -> BSWAP_R { BSWAP_R::new(((self.bits >> 22) & 1) != 0) } - #[doc = "Bit 23 - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. - - This allows checksum to be enabled or disabled on a per-control- block basis."] + #[doc = "Bit 23 - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis."] #[inline(always)] pub fn sniff_en(&self) -> SNIFF_EN_R { SNIFF_EN_R::new(((self.bits >> 23) & 1) != 0) } - #[doc = "Bit 24 - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. - - To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT."] + #[doc = "Bit 24 - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT."] #[inline(always)] pub fn busy(&self) -> BUSY_R { BUSY_R::new(((self.bits >> 24) & 1) != 0) } - #[doc = "Bit 29 - If 1, the channel received a write bus error. Write one to clear. - WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)"] + #[doc = "Bit 29 - If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)"] #[inline(always)] pub fn write_error(&self) -> WRITE_ERROR_R { WRITE_ERROR_R::new(((self.bits >> 29) & 1) != 0) } - #[doc = "Bit 30 - If 1, the channel received a read bus error. Write one to clear. - READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)"] + #[doc = "Bit 30 - If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)"] #[inline(always)] pub fn read_error(&self) -> READ_ERROR_R { READ_ERROR_R::new(((self.bits >> 30) & 1) != 0) @@ -943,16 +878,13 @@ impl R { } } impl W { - #[doc = "Bit 0 - DMA Channel Enable. - When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"] + #[doc = "Bit 0 - DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"] #[inline(always)] #[must_use] pub fn en(&mut self) -> EN_W { EN_W::new(self, 0) } - #[doc = "Bit 1 - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. - - This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."] + #[doc = "Bit 1 - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."] #[inline(always)] #[must_use] pub fn high_priority(&mut self) -> HIGH_PRIORITY_W { @@ -964,32 +896,25 @@ impl W { pub fn data_size(&mut self) -> DATA_SIZE_W { DATA_SIZE_W::new(self, 2) } - #[doc = "Bit 4 - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. - - Generally this should be disabled for peripheral-to-memory transfers."] + #[doc = "Bit 4 - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers."] #[inline(always)] #[must_use] pub fn incr_read(&mut self) -> INCR_READ_W { INCR_READ_W::new(self, 4) } - #[doc = "Bit 5 - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. - - Generally this should be disabled for memory-to-peripheral transfers."] + #[doc = "Bit 5 - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers."] #[inline(always)] #[must_use] pub fn incr_write(&mut self) -> INCR_WRITE_W { INCR_WRITE_W::new(self, 5) } - #[doc = "Bits 6:9 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. - - Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] + #[doc = "Bits 6:9 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] #[inline(always)] #[must_use] pub fn ring_size(&mut self) -> RING_SIZE_W { RING_SIZE_W::new(self, 6) } - #[doc = "Bit 10 - Select whether RING_SIZE applies to read or write addresses. - If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."] + #[doc = "Bit 10 - Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."] #[inline(always)] #[must_use] pub fn ring_sel(&mut self) -> RING_SEL_W { @@ -1002,46 +927,37 @@ impl W { pub fn chain_to(&mut self) -> CHAIN_TO_W { CHAIN_TO_W::new(self, 11) } - #[doc = "Bits 15:20 - Select a Transfer Request signal. - The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). - 0x0 to 0x3a -> select DREQ n as TREQ"] + #[doc = "Bits 15:20 - Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ"] #[inline(always)] #[must_use] pub fn treq_sel(&mut self) -> TREQ_SEL_W { TREQ_SEL_W::new(self, 15) } - #[doc = "Bit 21 - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. - - This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."] + #[doc = "Bit 21 - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."] #[inline(always)] #[must_use] pub fn irq_quiet(&mut self) -> IRQ_QUIET_W { IRQ_QUIET_W::new(self, 21) } - #[doc = "Bit 22 - Apply byte-swap transformation to DMA data. - For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."] + #[doc = "Bit 22 - Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."] #[inline(always)] #[must_use] pub fn bswap(&mut self) -> BSWAP_W { BSWAP_W::new(self, 22) } - #[doc = "Bit 23 - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. - - This allows checksum to be enabled or disabled on a per-control- block basis."] + #[doc = "Bit 23 - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis."] #[inline(always)] #[must_use] pub fn sniff_en(&mut self) -> SNIFF_EN_W { SNIFF_EN_W::new(self, 23) } - #[doc = "Bit 29 - If 1, the channel received a write bus error. Write one to clear. - WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)"] + #[doc = "Bit 29 - If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)"] #[inline(always)] #[must_use] pub fn write_error(&mut self) -> WRITE_ERROR_W { WRITE_ERROR_W::new(self, 29) } - #[doc = "Bit 30 - If 1, the channel received a read bus error. Write one to clear. - READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)"] + #[doc = "Bit 30 - If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)"] #[inline(always)] #[must_use] pub fn read_error(&mut self) -> READ_ERROR_W { diff --git a/src/dma/ch/ch_al2_read_addr.rs b/src/dma/ch/ch_al2_read_addr.rs index 0dd73092b..5425a3c98 100644 --- a/src/dma/ch/ch_al2_read_addr.rs +++ b/src/dma/ch/ch_al2_read_addr.rs @@ -2,17 +2,25 @@ pub type R = crate::R; #[doc = "Register `CH_AL2_READ_ADDR` writer"] pub type W = crate::W; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) +#[doc = "Field `CH0_AL2_READ_ADDR` reader - "] +pub type CH0_AL2_READ_ADDR_R = crate::FieldReader; +#[doc = "Field `CH0_AL2_READ_ADDR` writer - "] +pub type CH0_AL2_READ_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn ch0_al2_read_addr(&self) -> CH0_AL2_READ_ADDR_R { + CH0_AL2_READ_ADDR_R::new(self.bits) } } -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn ch0_al2_read_addr(&mut self) -> CH0_AL2_READ_ADDR_W { + CH0_AL2_READ_ADDR_W::new(self, 0) } } -impl W {} #[doc = "Alias for channel 0 READ_ADDR register You can [`read`](crate::generic::Reg::read) this register and get [`ch_al2_read_addr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_al2_read_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] diff --git a/src/dma/ch/ch_al2_trans_count.rs b/src/dma/ch/ch_al2_trans_count.rs index 2053f2ddb..8683edbdc 100644 --- a/src/dma/ch/ch_al2_trans_count.rs +++ b/src/dma/ch/ch_al2_trans_count.rs @@ -2,17 +2,25 @@ pub type R = crate::R; #[doc = "Register `CH_AL2_TRANS_COUNT` writer"] pub type W = crate::W; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) +#[doc = "Field `CH0_AL2_TRANS_COUNT` reader - "] +pub type CH0_AL2_TRANS_COUNT_R = crate::FieldReader; +#[doc = "Field `CH0_AL2_TRANS_COUNT` writer - "] +pub type CH0_AL2_TRANS_COUNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn ch0_al2_trans_count(&self) -> CH0_AL2_TRANS_COUNT_R { + CH0_AL2_TRANS_COUNT_R::new(self.bits) } } -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn ch0_al2_trans_count(&mut self) -> CH0_AL2_TRANS_COUNT_W { + CH0_AL2_TRANS_COUNT_W::new(self, 0) } } -impl W {} #[doc = "Alias for channel 0 TRANS_COUNT register You can [`read`](crate::generic::Reg::read) this register and get [`ch_al2_trans_count::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_al2_trans_count::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] diff --git a/src/dma/ch/ch_al2_write_addr_trig.rs b/src/dma/ch/ch_al2_write_addr_trig.rs index a3b75870c..301ff4d05 100644 --- a/src/dma/ch/ch_al2_write_addr_trig.rs +++ b/src/dma/ch/ch_al2_write_addr_trig.rs @@ -2,20 +2,28 @@ pub type R = crate::R; #[doc = "Register `CH_AL2_WRITE_ADDR_TRIG` writer"] pub type W = crate::W; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) +#[doc = "Field `CH0_AL2_WRITE_ADDR_TRIG` reader - "] +pub type CH0_AL2_WRITE_ADDR_TRIG_R = crate::FieldReader; +#[doc = "Field `CH0_AL2_WRITE_ADDR_TRIG` writer - "] +pub type CH0_AL2_WRITE_ADDR_TRIG_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn ch0_al2_write_addr_trig(&self) -> CH0_AL2_WRITE_ADDR_TRIG_R { + CH0_AL2_WRITE_ADDR_TRIG_R::new(self.bits) } } -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn ch0_al2_write_addr_trig( + &mut self, + ) -> CH0_AL2_WRITE_ADDR_TRIG_W { + CH0_AL2_WRITE_ADDR_TRIG_W::new(self, 0) } } -impl W {} -#[doc = "Alias for channel 0 WRITE_ADDR register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. +#[doc = "Alias for channel 0 WRITE_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. You can [`read`](crate::generic::Reg::read) this register and get [`ch_al2_write_addr_trig::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_al2_write_addr_trig::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CH_AL2_WRITE_ADDR_TRIG_SPEC; diff --git a/src/dma/ch/ch_al3_ctrl.rs b/src/dma/ch/ch_al3_ctrl.rs index f4ea5fd08..a7fb3fa71 100644 --- a/src/dma/ch/ch_al3_ctrl.rs +++ b/src/dma/ch/ch_al3_ctrl.rs @@ -2,19 +2,13 @@ pub type R = crate::R; #[doc = "Register `CH_AL3_CTRL` writer"] pub type W = crate::W; -#[doc = "Field `EN` reader - DMA Channel Enable. - When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"] +#[doc = "Field `EN` reader - DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"] pub type EN_R = crate::BitReader; -#[doc = "Field `EN` writer - DMA Channel Enable. - When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"] +#[doc = "Field `EN` writer - DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"] pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `HIGH_PRIORITY` reader - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. - - This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."] +#[doc = "Field `HIGH_PRIORITY` reader - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."] pub type HIGH_PRIORITY_R = crate::BitReader; -#[doc = "Field `HIGH_PRIORITY` writer - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. - - This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."] +#[doc = "Field `HIGH_PRIORITY` writer - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."] pub type HIGH_PRIORITY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. @@ -90,25 +84,15 @@ where self.variant(DATA_SIZE_A::SIZE_WORD) } } -#[doc = "Field `INCR_READ` reader - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. - - Generally this should be disabled for peripheral-to-memory transfers."] +#[doc = "Field `INCR_READ` reader - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers."] pub type INCR_READ_R = crate::BitReader; -#[doc = "Field `INCR_READ` writer - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. - - Generally this should be disabled for peripheral-to-memory transfers."] +#[doc = "Field `INCR_READ` writer - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers."] pub type INCR_READ_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `INCR_WRITE` reader - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. - - Generally this should be disabled for memory-to-peripheral transfers."] +#[doc = "Field `INCR_WRITE` reader - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers."] pub type INCR_WRITE_R = crate::BitReader; -#[doc = "Field `INCR_WRITE` writer - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. - - Generally this should be disabled for memory-to-peripheral transfers."] +#[doc = "Field `INCR_WRITE` writer - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers."] pub type INCR_WRITE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. - - Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. +#[doc = "Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. Value on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -126,9 +110,7 @@ impl From for u8 { impl crate::FieldSpec for RING_SIZE_A { type Ux = u8; } -#[doc = "Field `RING_SIZE` reader - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. - - Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] +#[doc = "Field `RING_SIZE` reader - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] pub type RING_SIZE_R = crate::FieldReader; impl RING_SIZE_R { #[doc = "Get enumerated values variant"] @@ -145,9 +127,7 @@ impl RING_SIZE_R { *self == RING_SIZE_A::RING_NONE } } -#[doc = "Field `RING_SIZE` writer - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. - - Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] +#[doc = "Field `RING_SIZE` writer - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] pub type RING_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 4, RING_SIZE_A>; impl<'a, REG> RING_SIZE_W<'a, REG> where @@ -160,11 +140,9 @@ where self.variant(RING_SIZE_A::RING_NONE) } } -#[doc = "Field `RING_SEL` reader - Select whether RING_SIZE applies to read or write addresses. - If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."] +#[doc = "Field `RING_SEL` reader - Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."] pub type RING_SEL_R = crate::BitReader; -#[doc = "Field `RING_SEL` writer - Select whether RING_SIZE applies to read or write addresses. - If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."] +#[doc = "Field `RING_SEL` writer - Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."] pub type RING_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `CHAIN_TO` reader - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. Reset value is 0, which means for channels 1 and above the default will be to chain to channel 0 - set this field to avoid this behaviour."] @@ -172,9 +150,7 @@ pub type CHAIN_TO_R = crate::FieldReader; #[doc = "Field `CHAIN_TO` writer - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. Reset value is 0, which means for channels 1 and above the default will be to chain to channel 0 - set this field to avoid this behaviour."] pub type CHAIN_TO_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Select a Transfer Request signal. - The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). - 0x0 to 0x3a -> select DREQ n as TREQ +#[doc = "Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ Value on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -280,9 +256,7 @@ impl From for u8 { impl crate::FieldSpec for TREQ_SEL_A { type Ux = u8; } -#[doc = "Field `TREQ_SEL` reader - Select a Transfer Request signal. - The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). - 0x0 to 0x3a -> select DREQ n as TREQ"] +#[doc = "Field `TREQ_SEL` reader - Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ"] pub type TREQ_SEL_R = crate::FieldReader; impl TREQ_SEL_R { #[doc = "Get enumerated values variant"] @@ -563,9 +537,7 @@ impl TREQ_SEL_R { *self == TREQ_SEL_A::PERMANENT } } -#[doc = "Field `TREQ_SEL` writer - Select a Transfer Request signal. - The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). - 0x0 to 0x3a -> select DREQ n as TREQ"] +#[doc = "Field `TREQ_SEL` writer - Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ"] pub type TREQ_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6, TREQ_SEL_A>; impl<'a, REG> TREQ_SEL_W<'a, REG> where @@ -798,56 +770,37 @@ where self.variant(TREQ_SEL_A::PERMANENT) } } -#[doc = "Field `IRQ_QUIET` reader - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. - - This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."] +#[doc = "Field `IRQ_QUIET` reader - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."] pub type IRQ_QUIET_R = crate::BitReader; -#[doc = "Field `IRQ_QUIET` writer - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. - - This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."] +#[doc = "Field `IRQ_QUIET` writer - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."] pub type IRQ_QUIET_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BSWAP` reader - Apply byte-swap transformation to DMA data. - For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."] +#[doc = "Field `BSWAP` reader - Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."] pub type BSWAP_R = crate::BitReader; -#[doc = "Field `BSWAP` writer - Apply byte-swap transformation to DMA data. - For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."] +#[doc = "Field `BSWAP` writer - Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."] pub type BSWAP_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SNIFF_EN` reader - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. - - This allows checksum to be enabled or disabled on a per-control- block basis."] +#[doc = "Field `SNIFF_EN` reader - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis."] pub type SNIFF_EN_R = crate::BitReader; -#[doc = "Field `SNIFF_EN` writer - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. - - This allows checksum to be enabled or disabled on a per-control- block basis."] +#[doc = "Field `SNIFF_EN` writer - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis."] pub type SNIFF_EN_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BUSY` reader - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. - - To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT."] +#[doc = "Field `BUSY` reader - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT."] pub type BUSY_R = crate::BitReader; -#[doc = "Field `WRITE_ERROR` reader - If 1, the channel received a write bus error. Write one to clear. - WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)"] +#[doc = "Field `WRITE_ERROR` reader - If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)"] pub type WRITE_ERROR_R = crate::BitReader; -#[doc = "Field `WRITE_ERROR` writer - If 1, the channel received a write bus error. Write one to clear. - WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)"] +#[doc = "Field `WRITE_ERROR` writer - If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)"] pub type WRITE_ERROR_W<'a, REG> = crate::BitWriter1C<'a, REG>; -#[doc = "Field `READ_ERROR` reader - If 1, the channel received a read bus error. Write one to clear. - READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)"] +#[doc = "Field `READ_ERROR` reader - If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)"] pub type READ_ERROR_R = crate::BitReader; -#[doc = "Field `READ_ERROR` writer - If 1, the channel received a read bus error. Write one to clear. - READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)"] +#[doc = "Field `READ_ERROR` writer - If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)"] pub type READ_ERROR_W<'a, REG> = crate::BitWriter1C<'a, REG>; #[doc = "Field `AHB_ERROR` reader - Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag."] pub type AHB_ERROR_R = crate::BitReader; impl R { - #[doc = "Bit 0 - DMA Channel Enable. - When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"] + #[doc = "Bit 0 - DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"] #[inline(always)] pub fn en(&self) -> EN_R { EN_R::new((self.bits & 1) != 0) } - #[doc = "Bit 1 - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. - - This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."] + #[doc = "Bit 1 - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."] #[inline(always)] pub fn high_priority(&self) -> HIGH_PRIORITY_R { HIGH_PRIORITY_R::new(((self.bits >> 1) & 1) != 0) @@ -857,29 +810,22 @@ impl R { pub fn data_size(&self) -> DATA_SIZE_R { DATA_SIZE_R::new(((self.bits >> 2) & 3) as u8) } - #[doc = "Bit 4 - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. - - Generally this should be disabled for peripheral-to-memory transfers."] + #[doc = "Bit 4 - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers."] #[inline(always)] pub fn incr_read(&self) -> INCR_READ_R { INCR_READ_R::new(((self.bits >> 4) & 1) != 0) } - #[doc = "Bit 5 - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. - - Generally this should be disabled for memory-to-peripheral transfers."] + #[doc = "Bit 5 - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers."] #[inline(always)] pub fn incr_write(&self) -> INCR_WRITE_R { INCR_WRITE_R::new(((self.bits >> 5) & 1) != 0) } - #[doc = "Bits 6:9 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. - - Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] + #[doc = "Bits 6:9 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] #[inline(always)] pub fn ring_size(&self) -> RING_SIZE_R { RING_SIZE_R::new(((self.bits >> 6) & 0x0f) as u8) } - #[doc = "Bit 10 - Select whether RING_SIZE applies to read or write addresses. - If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."] + #[doc = "Bit 10 - Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."] #[inline(always)] pub fn ring_sel(&self) -> RING_SEL_R { RING_SEL_R::new(((self.bits >> 10) & 1) != 0) @@ -890,48 +836,37 @@ impl R { pub fn chain_to(&self) -> CHAIN_TO_R { CHAIN_TO_R::new(((self.bits >> 11) & 0x0f) as u8) } - #[doc = "Bits 15:20 - Select a Transfer Request signal. - The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). - 0x0 to 0x3a -> select DREQ n as TREQ"] + #[doc = "Bits 15:20 - Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ"] #[inline(always)] pub fn treq_sel(&self) -> TREQ_SEL_R { TREQ_SEL_R::new(((self.bits >> 15) & 0x3f) as u8) } - #[doc = "Bit 21 - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. - - This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."] + #[doc = "Bit 21 - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."] #[inline(always)] pub fn irq_quiet(&self) -> IRQ_QUIET_R { IRQ_QUIET_R::new(((self.bits >> 21) & 1) != 0) } - #[doc = "Bit 22 - Apply byte-swap transformation to DMA data. - For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."] + #[doc = "Bit 22 - Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."] #[inline(always)] pub fn bswap(&self) -> BSWAP_R { BSWAP_R::new(((self.bits >> 22) & 1) != 0) } - #[doc = "Bit 23 - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. - - This allows checksum to be enabled or disabled on a per-control- block basis."] + #[doc = "Bit 23 - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis."] #[inline(always)] pub fn sniff_en(&self) -> SNIFF_EN_R { SNIFF_EN_R::new(((self.bits >> 23) & 1) != 0) } - #[doc = "Bit 24 - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. - - To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT."] + #[doc = "Bit 24 - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT."] #[inline(always)] pub fn busy(&self) -> BUSY_R { BUSY_R::new(((self.bits >> 24) & 1) != 0) } - #[doc = "Bit 29 - If 1, the channel received a write bus error. Write one to clear. - WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)"] + #[doc = "Bit 29 - If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)"] #[inline(always)] pub fn write_error(&self) -> WRITE_ERROR_R { WRITE_ERROR_R::new(((self.bits >> 29) & 1) != 0) } - #[doc = "Bit 30 - If 1, the channel received a read bus error. Write one to clear. - READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)"] + #[doc = "Bit 30 - If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)"] #[inline(always)] pub fn read_error(&self) -> READ_ERROR_R { READ_ERROR_R::new(((self.bits >> 30) & 1) != 0) @@ -943,16 +878,13 @@ impl R { } } impl W { - #[doc = "Bit 0 - DMA Channel Enable. - When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"] + #[doc = "Bit 0 - DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"] #[inline(always)] #[must_use] pub fn en(&mut self) -> EN_W { EN_W::new(self, 0) } - #[doc = "Bit 1 - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. - - This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."] + #[doc = "Bit 1 - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."] #[inline(always)] #[must_use] pub fn high_priority(&mut self) -> HIGH_PRIORITY_W { @@ -964,32 +896,25 @@ impl W { pub fn data_size(&mut self) -> DATA_SIZE_W { DATA_SIZE_W::new(self, 2) } - #[doc = "Bit 4 - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. - - Generally this should be disabled for peripheral-to-memory transfers."] + #[doc = "Bit 4 - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers."] #[inline(always)] #[must_use] pub fn incr_read(&mut self) -> INCR_READ_W { INCR_READ_W::new(self, 4) } - #[doc = "Bit 5 - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. - - Generally this should be disabled for memory-to-peripheral transfers."] + #[doc = "Bit 5 - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers."] #[inline(always)] #[must_use] pub fn incr_write(&mut self) -> INCR_WRITE_W { INCR_WRITE_W::new(self, 5) } - #[doc = "Bits 6:9 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. - - Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] + #[doc = "Bits 6:9 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] #[inline(always)] #[must_use] pub fn ring_size(&mut self) -> RING_SIZE_W { RING_SIZE_W::new(self, 6) } - #[doc = "Bit 10 - Select whether RING_SIZE applies to read or write addresses. - If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."] + #[doc = "Bit 10 - Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."] #[inline(always)] #[must_use] pub fn ring_sel(&mut self) -> RING_SEL_W { @@ -1002,46 +927,37 @@ impl W { pub fn chain_to(&mut self) -> CHAIN_TO_W { CHAIN_TO_W::new(self, 11) } - #[doc = "Bits 15:20 - Select a Transfer Request signal. - The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). - 0x0 to 0x3a -> select DREQ n as TREQ"] + #[doc = "Bits 15:20 - Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ"] #[inline(always)] #[must_use] pub fn treq_sel(&mut self) -> TREQ_SEL_W { TREQ_SEL_W::new(self, 15) } - #[doc = "Bit 21 - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. - - This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."] + #[doc = "Bit 21 - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."] #[inline(always)] #[must_use] pub fn irq_quiet(&mut self) -> IRQ_QUIET_W { IRQ_QUIET_W::new(self, 21) } - #[doc = "Bit 22 - Apply byte-swap transformation to DMA data. - For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."] + #[doc = "Bit 22 - Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."] #[inline(always)] #[must_use] pub fn bswap(&mut self) -> BSWAP_W { BSWAP_W::new(self, 22) } - #[doc = "Bit 23 - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. - - This allows checksum to be enabled or disabled on a per-control- block basis."] + #[doc = "Bit 23 - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis."] #[inline(always)] #[must_use] pub fn sniff_en(&mut self) -> SNIFF_EN_W { SNIFF_EN_W::new(self, 23) } - #[doc = "Bit 29 - If 1, the channel received a write bus error. Write one to clear. - WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)"] + #[doc = "Bit 29 - If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)"] #[inline(always)] #[must_use] pub fn write_error(&mut self) -> WRITE_ERROR_W { WRITE_ERROR_W::new(self, 29) } - #[doc = "Bit 30 - If 1, the channel received a read bus error. Write one to clear. - READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)"] + #[doc = "Bit 30 - If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)"] #[inline(always)] #[must_use] pub fn read_error(&mut self) -> READ_ERROR_W { diff --git a/src/dma/ch/ch_al3_read_addr_trig.rs b/src/dma/ch/ch_al3_read_addr_trig.rs index ce54935ae..9fa536809 100644 --- a/src/dma/ch/ch_al3_read_addr_trig.rs +++ b/src/dma/ch/ch_al3_read_addr_trig.rs @@ -2,20 +2,28 @@ pub type R = crate::R; #[doc = "Register `CH_AL3_READ_ADDR_TRIG` writer"] pub type W = crate::W; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) +#[doc = "Field `CH0_AL3_READ_ADDR_TRIG` reader - "] +pub type CH0_AL3_READ_ADDR_TRIG_R = crate::FieldReader; +#[doc = "Field `CH0_AL3_READ_ADDR_TRIG` writer - "] +pub type CH0_AL3_READ_ADDR_TRIG_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn ch0_al3_read_addr_trig(&self) -> CH0_AL3_READ_ADDR_TRIG_R { + CH0_AL3_READ_ADDR_TRIG_R::new(self.bits) } } -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn ch0_al3_read_addr_trig( + &mut self, + ) -> CH0_AL3_READ_ADDR_TRIG_W { + CH0_AL3_READ_ADDR_TRIG_W::new(self, 0) } } -impl W {} -#[doc = "Alias for channel 0 READ_ADDR register - This is a trigger register (0xc). Writing a nonzero value will - reload the channel counter and start the channel. +#[doc = "Alias for channel 0 READ_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. You can [`read`](crate::generic::Reg::read) this register and get [`ch_al3_read_addr_trig::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_al3_read_addr_trig::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CH_AL3_READ_ADDR_TRIG_SPEC; diff --git a/src/dma/ch/ch_al3_trans_count.rs b/src/dma/ch/ch_al3_trans_count.rs index 7cef663be..a73ccf63f 100644 --- a/src/dma/ch/ch_al3_trans_count.rs +++ b/src/dma/ch/ch_al3_trans_count.rs @@ -2,17 +2,25 @@ pub type R = crate::R; #[doc = "Register `CH_AL3_TRANS_COUNT` writer"] pub type W = crate::W; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) +#[doc = "Field `CH0_AL3_TRANS_COUNT` reader - "] +pub type CH0_AL3_TRANS_COUNT_R = crate::FieldReader; +#[doc = "Field `CH0_AL3_TRANS_COUNT` writer - "] +pub type CH0_AL3_TRANS_COUNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn ch0_al3_trans_count(&self) -> CH0_AL3_TRANS_COUNT_R { + CH0_AL3_TRANS_COUNT_R::new(self.bits) } } -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn ch0_al3_trans_count(&mut self) -> CH0_AL3_TRANS_COUNT_W { + CH0_AL3_TRANS_COUNT_W::new(self, 0) } } -impl W {} #[doc = "Alias for channel 0 TRANS_COUNT register You can [`read`](crate::generic::Reg::read) this register and get [`ch_al3_trans_count::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_al3_trans_count::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] diff --git a/src/dma/ch/ch_al3_write_addr.rs b/src/dma/ch/ch_al3_write_addr.rs index d69813fe0..ee577c9a0 100644 --- a/src/dma/ch/ch_al3_write_addr.rs +++ b/src/dma/ch/ch_al3_write_addr.rs @@ -2,17 +2,25 @@ pub type R = crate::R; #[doc = "Register `CH_AL3_WRITE_ADDR` writer"] pub type W = crate::W; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) +#[doc = "Field `CH0_AL3_WRITE_ADDR` reader - "] +pub type CH0_AL3_WRITE_ADDR_R = crate::FieldReader; +#[doc = "Field `CH0_AL3_WRITE_ADDR` writer - "] +pub type CH0_AL3_WRITE_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn ch0_al3_write_addr(&self) -> CH0_AL3_WRITE_ADDR_R { + CH0_AL3_WRITE_ADDR_R::new(self.bits) } } -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn ch0_al3_write_addr(&mut self) -> CH0_AL3_WRITE_ADDR_W { + CH0_AL3_WRITE_ADDR_W::new(self, 0) } } -impl W {} #[doc = "Alias for channel 0 WRITE_ADDR register You can [`read`](crate::generic::Reg::read) this register and get [`ch_al3_write_addr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_al3_write_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] diff --git a/src/dma/ch/ch_ctrl_trig.rs b/src/dma/ch/ch_ctrl_trig.rs index af5e735ef..00a450158 100644 --- a/src/dma/ch/ch_ctrl_trig.rs +++ b/src/dma/ch/ch_ctrl_trig.rs @@ -2,19 +2,13 @@ pub type R = crate::R; #[doc = "Register `CH_CTRL_TRIG` writer"] pub type W = crate::W; -#[doc = "Field `EN` reader - DMA Channel Enable. - When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"] +#[doc = "Field `EN` reader - DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"] pub type EN_R = crate::BitReader; -#[doc = "Field `EN` writer - DMA Channel Enable. - When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"] +#[doc = "Field `EN` writer - DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"] pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `HIGH_PRIORITY` reader - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. - - This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."] +#[doc = "Field `HIGH_PRIORITY` reader - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."] pub type HIGH_PRIORITY_R = crate::BitReader; -#[doc = "Field `HIGH_PRIORITY` writer - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. - - This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."] +#[doc = "Field `HIGH_PRIORITY` writer - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."] pub type HIGH_PRIORITY_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. @@ -90,25 +84,15 @@ where self.variant(DATA_SIZE_A::SIZE_WORD) } } -#[doc = "Field `INCR_READ` reader - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. - - Generally this should be disabled for peripheral-to-memory transfers."] +#[doc = "Field `INCR_READ` reader - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers."] pub type INCR_READ_R = crate::BitReader; -#[doc = "Field `INCR_READ` writer - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. - - Generally this should be disabled for peripheral-to-memory transfers."] +#[doc = "Field `INCR_READ` writer - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers."] pub type INCR_READ_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `INCR_WRITE` reader - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. - - Generally this should be disabled for memory-to-peripheral transfers."] +#[doc = "Field `INCR_WRITE` reader - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers."] pub type INCR_WRITE_R = crate::BitReader; -#[doc = "Field `INCR_WRITE` writer - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. - - Generally this should be disabled for memory-to-peripheral transfers."] +#[doc = "Field `INCR_WRITE` writer - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers."] pub type INCR_WRITE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. - - Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. +#[doc = "Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. Value on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -126,9 +110,7 @@ impl From for u8 { impl crate::FieldSpec for RING_SIZE_A { type Ux = u8; } -#[doc = "Field `RING_SIZE` reader - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. - - Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] +#[doc = "Field `RING_SIZE` reader - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] pub type RING_SIZE_R = crate::FieldReader; impl RING_SIZE_R { #[doc = "Get enumerated values variant"] @@ -145,9 +127,7 @@ impl RING_SIZE_R { *self == RING_SIZE_A::RING_NONE } } -#[doc = "Field `RING_SIZE` writer - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. - - Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] +#[doc = "Field `RING_SIZE` writer - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] pub type RING_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 4, RING_SIZE_A>; impl<'a, REG> RING_SIZE_W<'a, REG> where @@ -160,11 +140,9 @@ where self.variant(RING_SIZE_A::RING_NONE) } } -#[doc = "Field `RING_SEL` reader - Select whether RING_SIZE applies to read or write addresses. - If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."] +#[doc = "Field `RING_SEL` reader - Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."] pub type RING_SEL_R = crate::BitReader; -#[doc = "Field `RING_SEL` writer - Select whether RING_SIZE applies to read or write addresses. - If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."] +#[doc = "Field `RING_SEL` writer - Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."] pub type RING_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `CHAIN_TO` reader - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. Reset value is 0, which means for channels 1 and above the default will be to chain to channel 0 - set this field to avoid this behaviour."] @@ -172,9 +150,7 @@ pub type CHAIN_TO_R = crate::FieldReader; #[doc = "Field `CHAIN_TO` writer - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. Reset value is 0, which means for channels 1 and above the default will be to chain to channel 0 - set this field to avoid this behaviour."] pub type CHAIN_TO_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Select a Transfer Request signal. - The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). - 0x0 to 0x3a -> select DREQ n as TREQ +#[doc = "Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ Value on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -280,9 +256,7 @@ impl From for u8 { impl crate::FieldSpec for TREQ_SEL_A { type Ux = u8; } -#[doc = "Field `TREQ_SEL` reader - Select a Transfer Request signal. - The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). - 0x0 to 0x3a -> select DREQ n as TREQ"] +#[doc = "Field `TREQ_SEL` reader - Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ"] pub type TREQ_SEL_R = crate::FieldReader; impl TREQ_SEL_R { #[doc = "Get enumerated values variant"] @@ -563,9 +537,7 @@ impl TREQ_SEL_R { *self == TREQ_SEL_A::PERMANENT } } -#[doc = "Field `TREQ_SEL` writer - Select a Transfer Request signal. - The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). - 0x0 to 0x3a -> select DREQ n as TREQ"] +#[doc = "Field `TREQ_SEL` writer - Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ"] pub type TREQ_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6, TREQ_SEL_A>; impl<'a, REG> TREQ_SEL_W<'a, REG> where @@ -798,56 +770,37 @@ where self.variant(TREQ_SEL_A::PERMANENT) } } -#[doc = "Field `IRQ_QUIET` reader - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. - - This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."] +#[doc = "Field `IRQ_QUIET` reader - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."] pub type IRQ_QUIET_R = crate::BitReader; -#[doc = "Field `IRQ_QUIET` writer - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. - - This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."] +#[doc = "Field `IRQ_QUIET` writer - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."] pub type IRQ_QUIET_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BSWAP` reader - Apply byte-swap transformation to DMA data. - For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."] +#[doc = "Field `BSWAP` reader - Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."] pub type BSWAP_R = crate::BitReader; -#[doc = "Field `BSWAP` writer - Apply byte-swap transformation to DMA data. - For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."] +#[doc = "Field `BSWAP` writer - Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."] pub type BSWAP_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SNIFF_EN` reader - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. - - This allows checksum to be enabled or disabled on a per-control- block basis."] +#[doc = "Field `SNIFF_EN` reader - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis."] pub type SNIFF_EN_R = crate::BitReader; -#[doc = "Field `SNIFF_EN` writer - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. - - This allows checksum to be enabled or disabled on a per-control- block basis."] +#[doc = "Field `SNIFF_EN` writer - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis."] pub type SNIFF_EN_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `BUSY` reader - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. - - To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT."] +#[doc = "Field `BUSY` reader - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT."] pub type BUSY_R = crate::BitReader; -#[doc = "Field `WRITE_ERROR` reader - If 1, the channel received a write bus error. Write one to clear. - WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)"] +#[doc = "Field `WRITE_ERROR` reader - If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)"] pub type WRITE_ERROR_R = crate::BitReader; -#[doc = "Field `WRITE_ERROR` writer - If 1, the channel received a write bus error. Write one to clear. - WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)"] +#[doc = "Field `WRITE_ERROR` writer - If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)"] pub type WRITE_ERROR_W<'a, REG> = crate::BitWriter1C<'a, REG>; -#[doc = "Field `READ_ERROR` reader - If 1, the channel received a read bus error. Write one to clear. - READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)"] +#[doc = "Field `READ_ERROR` reader - If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)"] pub type READ_ERROR_R = crate::BitReader; -#[doc = "Field `READ_ERROR` writer - If 1, the channel received a read bus error. Write one to clear. - READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)"] +#[doc = "Field `READ_ERROR` writer - If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)"] pub type READ_ERROR_W<'a, REG> = crate::BitWriter1C<'a, REG>; #[doc = "Field `AHB_ERROR` reader - Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag."] pub type AHB_ERROR_R = crate::BitReader; impl R { - #[doc = "Bit 0 - DMA Channel Enable. - When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"] + #[doc = "Bit 0 - DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"] #[inline(always)] pub fn en(&self) -> EN_R { EN_R::new((self.bits & 1) != 0) } - #[doc = "Bit 1 - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. - - This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."] + #[doc = "Bit 1 - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."] #[inline(always)] pub fn high_priority(&self) -> HIGH_PRIORITY_R { HIGH_PRIORITY_R::new(((self.bits >> 1) & 1) != 0) @@ -857,29 +810,22 @@ impl R { pub fn data_size(&self) -> DATA_SIZE_R { DATA_SIZE_R::new(((self.bits >> 2) & 3) as u8) } - #[doc = "Bit 4 - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. - - Generally this should be disabled for peripheral-to-memory transfers."] + #[doc = "Bit 4 - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers."] #[inline(always)] pub fn incr_read(&self) -> INCR_READ_R { INCR_READ_R::new(((self.bits >> 4) & 1) != 0) } - #[doc = "Bit 5 - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. - - Generally this should be disabled for memory-to-peripheral transfers."] + #[doc = "Bit 5 - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers."] #[inline(always)] pub fn incr_write(&self) -> INCR_WRITE_R { INCR_WRITE_R::new(((self.bits >> 5) & 1) != 0) } - #[doc = "Bits 6:9 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. - - Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] + #[doc = "Bits 6:9 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] #[inline(always)] pub fn ring_size(&self) -> RING_SIZE_R { RING_SIZE_R::new(((self.bits >> 6) & 0x0f) as u8) } - #[doc = "Bit 10 - Select whether RING_SIZE applies to read or write addresses. - If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."] + #[doc = "Bit 10 - Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."] #[inline(always)] pub fn ring_sel(&self) -> RING_SEL_R { RING_SEL_R::new(((self.bits >> 10) & 1) != 0) @@ -890,48 +836,37 @@ impl R { pub fn chain_to(&self) -> CHAIN_TO_R { CHAIN_TO_R::new(((self.bits >> 11) & 0x0f) as u8) } - #[doc = "Bits 15:20 - Select a Transfer Request signal. - The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). - 0x0 to 0x3a -> select DREQ n as TREQ"] + #[doc = "Bits 15:20 - Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ"] #[inline(always)] pub fn treq_sel(&self) -> TREQ_SEL_R { TREQ_SEL_R::new(((self.bits >> 15) & 0x3f) as u8) } - #[doc = "Bit 21 - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. - - This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."] + #[doc = "Bit 21 - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."] #[inline(always)] pub fn irq_quiet(&self) -> IRQ_QUIET_R { IRQ_QUIET_R::new(((self.bits >> 21) & 1) != 0) } - #[doc = "Bit 22 - Apply byte-swap transformation to DMA data. - For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."] + #[doc = "Bit 22 - Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."] #[inline(always)] pub fn bswap(&self) -> BSWAP_R { BSWAP_R::new(((self.bits >> 22) & 1) != 0) } - #[doc = "Bit 23 - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. - - This allows checksum to be enabled or disabled on a per-control- block basis."] + #[doc = "Bit 23 - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis."] #[inline(always)] pub fn sniff_en(&self) -> SNIFF_EN_R { SNIFF_EN_R::new(((self.bits >> 23) & 1) != 0) } - #[doc = "Bit 24 - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. - - To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT."] + #[doc = "Bit 24 - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT."] #[inline(always)] pub fn busy(&self) -> BUSY_R { BUSY_R::new(((self.bits >> 24) & 1) != 0) } - #[doc = "Bit 29 - If 1, the channel received a write bus error. Write one to clear. - WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)"] + #[doc = "Bit 29 - If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)"] #[inline(always)] pub fn write_error(&self) -> WRITE_ERROR_R { WRITE_ERROR_R::new(((self.bits >> 29) & 1) != 0) } - #[doc = "Bit 30 - If 1, the channel received a read bus error. Write one to clear. - READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)"] + #[doc = "Bit 30 - If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)"] #[inline(always)] pub fn read_error(&self) -> READ_ERROR_R { READ_ERROR_R::new(((self.bits >> 30) & 1) != 0) @@ -943,16 +878,13 @@ impl R { } } impl W { - #[doc = "Bit 0 - DMA Channel Enable. - When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"] + #[doc = "Bit 0 - DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"] #[inline(always)] #[must_use] pub fn en(&mut self) -> EN_W { EN_W::new(self, 0) } - #[doc = "Bit 1 - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. - - This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."] + #[doc = "Bit 1 - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."] #[inline(always)] #[must_use] pub fn high_priority(&mut self) -> HIGH_PRIORITY_W { @@ -964,32 +896,25 @@ impl W { pub fn data_size(&mut self) -> DATA_SIZE_W { DATA_SIZE_W::new(self, 2) } - #[doc = "Bit 4 - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. - - Generally this should be disabled for peripheral-to-memory transfers."] + #[doc = "Bit 4 - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers."] #[inline(always)] #[must_use] pub fn incr_read(&mut self) -> INCR_READ_W { INCR_READ_W::new(self, 4) } - #[doc = "Bit 5 - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. - - Generally this should be disabled for memory-to-peripheral transfers."] + #[doc = "Bit 5 - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers."] #[inline(always)] #[must_use] pub fn incr_write(&mut self) -> INCR_WRITE_W { INCR_WRITE_W::new(self, 5) } - #[doc = "Bits 6:9 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. - - Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] + #[doc = "Bits 6:9 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] #[inline(always)] #[must_use] pub fn ring_size(&mut self) -> RING_SIZE_W { RING_SIZE_W::new(self, 6) } - #[doc = "Bit 10 - Select whether RING_SIZE applies to read or write addresses. - If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."] + #[doc = "Bit 10 - Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."] #[inline(always)] #[must_use] pub fn ring_sel(&mut self) -> RING_SEL_W { @@ -1002,46 +927,37 @@ impl W { pub fn chain_to(&mut self) -> CHAIN_TO_W { CHAIN_TO_W::new(self, 11) } - #[doc = "Bits 15:20 - Select a Transfer Request signal. - The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). - 0x0 to 0x3a -> select DREQ n as TREQ"] + #[doc = "Bits 15:20 - Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ"] #[inline(always)] #[must_use] pub fn treq_sel(&mut self) -> TREQ_SEL_W { TREQ_SEL_W::new(self, 15) } - #[doc = "Bit 21 - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. - - This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."] + #[doc = "Bit 21 - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."] #[inline(always)] #[must_use] pub fn irq_quiet(&mut self) -> IRQ_QUIET_W { IRQ_QUIET_W::new(self, 21) } - #[doc = "Bit 22 - Apply byte-swap transformation to DMA data. - For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."] + #[doc = "Bit 22 - Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."] #[inline(always)] #[must_use] pub fn bswap(&mut self) -> BSWAP_W { BSWAP_W::new(self, 22) } - #[doc = "Bit 23 - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. - - This allows checksum to be enabled or disabled on a per-control- block basis."] + #[doc = "Bit 23 - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis."] #[inline(always)] #[must_use] pub fn sniff_en(&mut self) -> SNIFF_EN_W { SNIFF_EN_W::new(self, 23) } - #[doc = "Bit 29 - If 1, the channel received a write bus error. Write one to clear. - WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)"] + #[doc = "Bit 29 - If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)"] #[inline(always)] #[must_use] pub fn write_error(&mut self) -> WRITE_ERROR_W { WRITE_ERROR_W::new(self, 29) } - #[doc = "Bit 30 - If 1, the channel received a read bus error. Write one to clear. - READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)"] + #[doc = "Bit 30 - If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)"] #[inline(always)] #[must_use] pub fn read_error(&mut self) -> READ_ERROR_W { diff --git a/src/dma/ch/ch_read_addr.rs b/src/dma/ch/ch_read_addr.rs index f40b0adec..7d81a2554 100644 --- a/src/dma/ch/ch_read_addr.rs +++ b/src/dma/ch/ch_read_addr.rs @@ -2,19 +2,26 @@ pub type R = crate::R; #[doc = "Register `CH_READ_ADDR` writer"] pub type W = crate::W; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) +#[doc = "Field `CH0_READ_ADDR` reader - This register updates automatically each time a read completes. The current value is the next address to be read by this channel."] +pub type CH0_READ_ADDR_R = crate::FieldReader; +#[doc = "Field `CH0_READ_ADDR` writer - This register updates automatically each time a read completes. The current value is the next address to be read by this channel."] +pub type CH0_READ_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - This register updates automatically each time a read completes. The current value is the next address to be read by this channel."] + #[inline(always)] + pub fn ch0_read_addr(&self) -> CH0_READ_ADDR_R { + CH0_READ_ADDR_R::new(self.bits) } } -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +impl W { + #[doc = "Bits 0:31 - This register updates automatically each time a read completes. The current value is the next address to be read by this channel."] + #[inline(always)] + #[must_use] + pub fn ch0_read_addr(&mut self) -> CH0_READ_ADDR_W { + CH0_READ_ADDR_W::new(self, 0) } } -impl W {} #[doc = "DMA Channel 0 Read Address pointer - This register updates automatically each time a read completes. The current value is the next address to be read by this channel. You can [`read`](crate::generic::Reg::read) this register and get [`ch_read_addr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_read_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CH_READ_ADDR_SPEC; diff --git a/src/dma/ch/ch_trans_count.rs b/src/dma/ch/ch_trans_count.rs index 0868b3baa..e423dc5ff 100644 --- a/src/dma/ch/ch_trans_count.rs +++ b/src/dma/ch/ch_trans_count.rs @@ -2,25 +2,26 @@ pub type R = crate::R; #[doc = "Register `CH_TRANS_COUNT` writer"] pub type W = crate::W; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) +#[doc = "Field `CH0_TRANS_COUNT` reader - Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD."] +pub type CH0_TRANS_COUNT_R = crate::FieldReader; +#[doc = "Field `CH0_TRANS_COUNT` writer - Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD."] +pub type CH0_TRANS_COUNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD."] + #[inline(always)] + pub fn ch0_trans_count(&self) -> CH0_TRANS_COUNT_R { + CH0_TRANS_COUNT_R::new(self.bits) } } -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +impl W { + #[doc = "Bits 0:31 - Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD."] + #[inline(always)] + #[must_use] + pub fn ch0_trans_count(&mut self) -> CH0_TRANS_COUNT_W { + CH0_TRANS_COUNT_W::new(self, 0) } } -impl W {} #[doc = "DMA Channel 0 Transfer Count - Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). - - When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. - - Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. - - The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. You can [`read`](crate::generic::Reg::read) this register and get [`ch_trans_count::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_trans_count::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CH_TRANS_COUNT_SPEC; diff --git a/src/dma/ch/ch_write_addr.rs b/src/dma/ch/ch_write_addr.rs index 2aef1f437..7ecd4f39a 100644 --- a/src/dma/ch/ch_write_addr.rs +++ b/src/dma/ch/ch_write_addr.rs @@ -2,19 +2,26 @@ pub type R = crate::R; #[doc = "Register `CH_WRITE_ADDR` writer"] pub type W = crate::W; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) +#[doc = "Field `CH0_WRITE_ADDR` reader - This register updates automatically each time a write completes. The current value is the next address to be written by this channel."] +pub type CH0_WRITE_ADDR_R = crate::FieldReader; +#[doc = "Field `CH0_WRITE_ADDR` writer - This register updates automatically each time a write completes. The current value is the next address to be written by this channel."] +pub type CH0_WRITE_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - This register updates automatically each time a write completes. The current value is the next address to be written by this channel."] + #[inline(always)] + pub fn ch0_write_addr(&self) -> CH0_WRITE_ADDR_R { + CH0_WRITE_ADDR_R::new(self.bits) } } -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +impl W { + #[doc = "Bits 0:31 - This register updates automatically each time a write completes. The current value is the next address to be written by this channel."] + #[inline(always)] + #[must_use] + pub fn ch0_write_addr(&mut self) -> CH0_WRITE_ADDR_W { + CH0_WRITE_ADDR_W::new(self, 0) } } -impl W {} #[doc = "DMA Channel 0 Write Address pointer - This register updates automatically each time a write completes. The current value is the next address to be written by this channel. You can [`read`](crate::generic::Reg::read) this register and get [`ch_write_addr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_write_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CH_WRITE_ADDR_SPEC; diff --git a/src/dma/ch0_dbg_tcr.rs b/src/dma/ch0_dbg_tcr.rs index 6678dbc78..5459f808d 100644 --- a/src/dma/ch0_dbg_tcr.rs +++ b/src/dma/ch0_dbg_tcr.rs @@ -1,24 +1,32 @@ #[doc = "Register `CH0_DBG_TCR` reader"] pub type R = crate::R; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) - } -} -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +#[doc = "Register `CH0_DBG_TCR` writer"] +pub type W = crate::W; +#[doc = "Field `CH0_DBG_TCR` reader - "] +pub type CH0_DBG_TCR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn ch0_dbg_tcr(&self) -> CH0_DBG_TCR_R { + CH0_DBG_TCR_R::new(self.bits) } } +impl W {} #[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer -You can [`read`](crate::generic::Reg::read) this register and get [`ch0_dbg_tcr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`ch0_dbg_tcr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch0_dbg_tcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CH0_DBG_TCR_SPEC; impl crate::RegisterSpec for CH0_DBG_TCR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`ch0_dbg_tcr::R`](R) reader structure"] impl crate::Readable for CH0_DBG_TCR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch0_dbg_tcr::W`](W) writer structure"] +impl crate::Writable for CH0_DBG_TCR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets CH0_DBG_TCR to value 0"] impl crate::Resettable for CH0_DBG_TCR_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/dma/ch10_dbg_tcr.rs b/src/dma/ch10_dbg_tcr.rs index 446be4624..34a3fee5a 100644 --- a/src/dma/ch10_dbg_tcr.rs +++ b/src/dma/ch10_dbg_tcr.rs @@ -1,24 +1,32 @@ #[doc = "Register `CH10_DBG_TCR` reader"] pub type R = crate::R; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) - } -} -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +#[doc = "Register `CH10_DBG_TCR` writer"] +pub type W = crate::W; +#[doc = "Field `CH10_DBG_TCR` reader - "] +pub type CH10_DBG_TCR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn ch10_dbg_tcr(&self) -> CH10_DBG_TCR_R { + CH10_DBG_TCR_R::new(self.bits) } } +impl W {} #[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer -You can [`read`](crate::generic::Reg::read) this register and get [`ch10_dbg_tcr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`ch10_dbg_tcr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch10_dbg_tcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CH10_DBG_TCR_SPEC; impl crate::RegisterSpec for CH10_DBG_TCR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`ch10_dbg_tcr::R`](R) reader structure"] impl crate::Readable for CH10_DBG_TCR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch10_dbg_tcr::W`](W) writer structure"] +impl crate::Writable for CH10_DBG_TCR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets CH10_DBG_TCR to value 0"] impl crate::Resettable for CH10_DBG_TCR_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/dma/ch11_dbg_tcr.rs b/src/dma/ch11_dbg_tcr.rs index a69c787ff..066b2461b 100644 --- a/src/dma/ch11_dbg_tcr.rs +++ b/src/dma/ch11_dbg_tcr.rs @@ -1,24 +1,32 @@ #[doc = "Register `CH11_DBG_TCR` reader"] pub type R = crate::R; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) - } -} -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +#[doc = "Register `CH11_DBG_TCR` writer"] +pub type W = crate::W; +#[doc = "Field `CH11_DBG_TCR` reader - "] +pub type CH11_DBG_TCR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn ch11_dbg_tcr(&self) -> CH11_DBG_TCR_R { + CH11_DBG_TCR_R::new(self.bits) } } +impl W {} #[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer -You can [`read`](crate::generic::Reg::read) this register and get [`ch11_dbg_tcr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`ch11_dbg_tcr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch11_dbg_tcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CH11_DBG_TCR_SPEC; impl crate::RegisterSpec for CH11_DBG_TCR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`ch11_dbg_tcr::R`](R) reader structure"] impl crate::Readable for CH11_DBG_TCR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch11_dbg_tcr::W`](W) writer structure"] +impl crate::Writable for CH11_DBG_TCR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets CH11_DBG_TCR to value 0"] impl crate::Resettable for CH11_DBG_TCR_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/dma/ch1_dbg_tcr.rs b/src/dma/ch1_dbg_tcr.rs index f7646ddc9..30c81cc2d 100644 --- a/src/dma/ch1_dbg_tcr.rs +++ b/src/dma/ch1_dbg_tcr.rs @@ -1,24 +1,32 @@ #[doc = "Register `CH1_DBG_TCR` reader"] pub type R = crate::R; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) - } -} -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +#[doc = "Register `CH1_DBG_TCR` writer"] +pub type W = crate::W; +#[doc = "Field `CH1_DBG_TCR` reader - "] +pub type CH1_DBG_TCR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn ch1_dbg_tcr(&self) -> CH1_DBG_TCR_R { + CH1_DBG_TCR_R::new(self.bits) } } +impl W {} #[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer -You can [`read`](crate::generic::Reg::read) this register and get [`ch1_dbg_tcr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`ch1_dbg_tcr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch1_dbg_tcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CH1_DBG_TCR_SPEC; impl crate::RegisterSpec for CH1_DBG_TCR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`ch1_dbg_tcr::R`](R) reader structure"] impl crate::Readable for CH1_DBG_TCR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch1_dbg_tcr::W`](W) writer structure"] +impl crate::Writable for CH1_DBG_TCR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets CH1_DBG_TCR to value 0"] impl crate::Resettable for CH1_DBG_TCR_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/dma/ch2_dbg_tcr.rs b/src/dma/ch2_dbg_tcr.rs index 3ba047943..d7d5edf8f 100644 --- a/src/dma/ch2_dbg_tcr.rs +++ b/src/dma/ch2_dbg_tcr.rs @@ -1,24 +1,32 @@ #[doc = "Register `CH2_DBG_TCR` reader"] pub type R = crate::R; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) - } -} -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +#[doc = "Register `CH2_DBG_TCR` writer"] +pub type W = crate::W; +#[doc = "Field `CH2_DBG_TCR` reader - "] +pub type CH2_DBG_TCR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn ch2_dbg_tcr(&self) -> CH2_DBG_TCR_R { + CH2_DBG_TCR_R::new(self.bits) } } +impl W {} #[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer -You can [`read`](crate::generic::Reg::read) this register and get [`ch2_dbg_tcr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`ch2_dbg_tcr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch2_dbg_tcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CH2_DBG_TCR_SPEC; impl crate::RegisterSpec for CH2_DBG_TCR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`ch2_dbg_tcr::R`](R) reader structure"] impl crate::Readable for CH2_DBG_TCR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch2_dbg_tcr::W`](W) writer structure"] +impl crate::Writable for CH2_DBG_TCR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets CH2_DBG_TCR to value 0"] impl crate::Resettable for CH2_DBG_TCR_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/dma/ch3_dbg_tcr.rs b/src/dma/ch3_dbg_tcr.rs index 14336b066..98917e43a 100644 --- a/src/dma/ch3_dbg_tcr.rs +++ b/src/dma/ch3_dbg_tcr.rs @@ -1,24 +1,32 @@ #[doc = "Register `CH3_DBG_TCR` reader"] pub type R = crate::R; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) - } -} -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +#[doc = "Register `CH3_DBG_TCR` writer"] +pub type W = crate::W; +#[doc = "Field `CH3_DBG_TCR` reader - "] +pub type CH3_DBG_TCR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn ch3_dbg_tcr(&self) -> CH3_DBG_TCR_R { + CH3_DBG_TCR_R::new(self.bits) } } +impl W {} #[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer -You can [`read`](crate::generic::Reg::read) this register and get [`ch3_dbg_tcr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`ch3_dbg_tcr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch3_dbg_tcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CH3_DBG_TCR_SPEC; impl crate::RegisterSpec for CH3_DBG_TCR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`ch3_dbg_tcr::R`](R) reader structure"] impl crate::Readable for CH3_DBG_TCR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch3_dbg_tcr::W`](W) writer structure"] +impl crate::Writable for CH3_DBG_TCR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets CH3_DBG_TCR to value 0"] impl crate::Resettable for CH3_DBG_TCR_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/dma/ch4_dbg_tcr.rs b/src/dma/ch4_dbg_tcr.rs index d505fc107..2f23b883c 100644 --- a/src/dma/ch4_dbg_tcr.rs +++ b/src/dma/ch4_dbg_tcr.rs @@ -1,24 +1,32 @@ #[doc = "Register `CH4_DBG_TCR` reader"] pub type R = crate::R; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) - } -} -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +#[doc = "Register `CH4_DBG_TCR` writer"] +pub type W = crate::W; +#[doc = "Field `CH4_DBG_TCR` reader - "] +pub type CH4_DBG_TCR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn ch4_dbg_tcr(&self) -> CH4_DBG_TCR_R { + CH4_DBG_TCR_R::new(self.bits) } } +impl W {} #[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer -You can [`read`](crate::generic::Reg::read) this register and get [`ch4_dbg_tcr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`ch4_dbg_tcr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch4_dbg_tcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CH4_DBG_TCR_SPEC; impl crate::RegisterSpec for CH4_DBG_TCR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`ch4_dbg_tcr::R`](R) reader structure"] impl crate::Readable for CH4_DBG_TCR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch4_dbg_tcr::W`](W) writer structure"] +impl crate::Writable for CH4_DBG_TCR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets CH4_DBG_TCR to value 0"] impl crate::Resettable for CH4_DBG_TCR_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/dma/ch5_dbg_tcr.rs b/src/dma/ch5_dbg_tcr.rs index e6c36ad63..32910b9eb 100644 --- a/src/dma/ch5_dbg_tcr.rs +++ b/src/dma/ch5_dbg_tcr.rs @@ -1,24 +1,32 @@ #[doc = "Register `CH5_DBG_TCR` reader"] pub type R = crate::R; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) - } -} -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +#[doc = "Register `CH5_DBG_TCR` writer"] +pub type W = crate::W; +#[doc = "Field `CH5_DBG_TCR` reader - "] +pub type CH5_DBG_TCR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn ch5_dbg_tcr(&self) -> CH5_DBG_TCR_R { + CH5_DBG_TCR_R::new(self.bits) } } +impl W {} #[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer -You can [`read`](crate::generic::Reg::read) this register and get [`ch5_dbg_tcr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`ch5_dbg_tcr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch5_dbg_tcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CH5_DBG_TCR_SPEC; impl crate::RegisterSpec for CH5_DBG_TCR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`ch5_dbg_tcr::R`](R) reader structure"] impl crate::Readable for CH5_DBG_TCR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch5_dbg_tcr::W`](W) writer structure"] +impl crate::Writable for CH5_DBG_TCR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets CH5_DBG_TCR to value 0"] impl crate::Resettable for CH5_DBG_TCR_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/dma/ch6_dbg_tcr.rs b/src/dma/ch6_dbg_tcr.rs index a522ebdcf..3af57a7d3 100644 --- a/src/dma/ch6_dbg_tcr.rs +++ b/src/dma/ch6_dbg_tcr.rs @@ -1,24 +1,32 @@ #[doc = "Register `CH6_DBG_TCR` reader"] pub type R = crate::R; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) - } -} -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +#[doc = "Register `CH6_DBG_TCR` writer"] +pub type W = crate::W; +#[doc = "Field `CH6_DBG_TCR` reader - "] +pub type CH6_DBG_TCR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn ch6_dbg_tcr(&self) -> CH6_DBG_TCR_R { + CH6_DBG_TCR_R::new(self.bits) } } +impl W {} #[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer -You can [`read`](crate::generic::Reg::read) this register and get [`ch6_dbg_tcr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`ch6_dbg_tcr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch6_dbg_tcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CH6_DBG_TCR_SPEC; impl crate::RegisterSpec for CH6_DBG_TCR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`ch6_dbg_tcr::R`](R) reader structure"] impl crate::Readable for CH6_DBG_TCR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch6_dbg_tcr::W`](W) writer structure"] +impl crate::Writable for CH6_DBG_TCR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets CH6_DBG_TCR to value 0"] impl crate::Resettable for CH6_DBG_TCR_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/dma/ch7_dbg_tcr.rs b/src/dma/ch7_dbg_tcr.rs index e85acab52..5754eec03 100644 --- a/src/dma/ch7_dbg_tcr.rs +++ b/src/dma/ch7_dbg_tcr.rs @@ -1,24 +1,32 @@ #[doc = "Register `CH7_DBG_TCR` reader"] pub type R = crate::R; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) - } -} -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +#[doc = "Register `CH7_DBG_TCR` writer"] +pub type W = crate::W; +#[doc = "Field `CH7_DBG_TCR` reader - "] +pub type CH7_DBG_TCR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn ch7_dbg_tcr(&self) -> CH7_DBG_TCR_R { + CH7_DBG_TCR_R::new(self.bits) } } +impl W {} #[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer -You can [`read`](crate::generic::Reg::read) this register and get [`ch7_dbg_tcr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`ch7_dbg_tcr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch7_dbg_tcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CH7_DBG_TCR_SPEC; impl crate::RegisterSpec for CH7_DBG_TCR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`ch7_dbg_tcr::R`](R) reader structure"] impl crate::Readable for CH7_DBG_TCR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch7_dbg_tcr::W`](W) writer structure"] +impl crate::Writable for CH7_DBG_TCR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets CH7_DBG_TCR to value 0"] impl crate::Resettable for CH7_DBG_TCR_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/dma/ch8_dbg_tcr.rs b/src/dma/ch8_dbg_tcr.rs index 74ee9a4c4..af6e49d4e 100644 --- a/src/dma/ch8_dbg_tcr.rs +++ b/src/dma/ch8_dbg_tcr.rs @@ -1,24 +1,32 @@ #[doc = "Register `CH8_DBG_TCR` reader"] pub type R = crate::R; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) - } -} -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +#[doc = "Register `CH8_DBG_TCR` writer"] +pub type W = crate::W; +#[doc = "Field `CH8_DBG_TCR` reader - "] +pub type CH8_DBG_TCR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn ch8_dbg_tcr(&self) -> CH8_DBG_TCR_R { + CH8_DBG_TCR_R::new(self.bits) } } +impl W {} #[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer -You can [`read`](crate::generic::Reg::read) this register and get [`ch8_dbg_tcr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`ch8_dbg_tcr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch8_dbg_tcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CH8_DBG_TCR_SPEC; impl crate::RegisterSpec for CH8_DBG_TCR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`ch8_dbg_tcr::R`](R) reader structure"] impl crate::Readable for CH8_DBG_TCR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch8_dbg_tcr::W`](W) writer structure"] +impl crate::Writable for CH8_DBG_TCR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets CH8_DBG_TCR to value 0"] impl crate::Resettable for CH8_DBG_TCR_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/dma/ch9_dbg_tcr.rs b/src/dma/ch9_dbg_tcr.rs index 02a6dd942..d55c8ab83 100644 --- a/src/dma/ch9_dbg_tcr.rs +++ b/src/dma/ch9_dbg_tcr.rs @@ -1,24 +1,32 @@ #[doc = "Register `CH9_DBG_TCR` reader"] pub type R = crate::R; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) - } -} -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +#[doc = "Register `CH9_DBG_TCR` writer"] +pub type W = crate::W; +#[doc = "Field `CH9_DBG_TCR` reader - "] +pub type CH9_DBG_TCR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn ch9_dbg_tcr(&self) -> CH9_DBG_TCR_R { + CH9_DBG_TCR_R::new(self.bits) } } +impl W {} #[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer -You can [`read`](crate::generic::Reg::read) this register and get [`ch9_dbg_tcr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`ch9_dbg_tcr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch9_dbg_tcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CH9_DBG_TCR_SPEC; impl crate::RegisterSpec for CH9_DBG_TCR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`ch9_dbg_tcr::R`](R) reader structure"] impl crate::Readable for CH9_DBG_TCR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch9_dbg_tcr::W`](W) writer structure"] +impl crate::Writable for CH9_DBG_TCR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets CH9_DBG_TCR to value 0"] impl crate::Resettable for CH9_DBG_TCR_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/dma/chan_abort.rs b/src/dma/chan_abort.rs index 82c47ba6b..92b8634cc 100644 --- a/src/dma/chan_abort.rs +++ b/src/dma/chan_abort.rs @@ -2,27 +2,19 @@ pub type R = crate::R; #[doc = "Register `CHAN_ABORT` writer"] pub type W = crate::W; -#[doc = "Field `CHAN_ABORT` reader - Each bit corresponds to a channel. Writing a 1 aborts whatever transfer sequence is in progress on that channel. The bit will remain high until any in-flight transfers have been flushed through the address and data FIFOs. - - After writing, this register must be polled until it returns all-zero. Until this point, it is unsafe to restart the channel."] +#[doc = "Field `CHAN_ABORT` reader - Each bit corresponds to a channel. Writing a 1 aborts whatever transfer sequence is in progress on that channel. The bit will remain high until any in-flight transfers have been flushed through the address and data FIFOs. After writing, this register must be polled until it returns all-zero. Until this point, it is unsafe to restart the channel."] pub type CHAN_ABORT_R = crate::FieldReader; -#[doc = "Field `CHAN_ABORT` writer - Each bit corresponds to a channel. Writing a 1 aborts whatever transfer sequence is in progress on that channel. The bit will remain high until any in-flight transfers have been flushed through the address and data FIFOs. - - After writing, this register must be polled until it returns all-zero. Until this point, it is unsafe to restart the channel."] +#[doc = "Field `CHAN_ABORT` writer - Each bit corresponds to a channel. Writing a 1 aborts whatever transfer sequence is in progress on that channel. The bit will remain high until any in-flight transfers have been flushed through the address and data FIFOs. After writing, this register must be polled until it returns all-zero. Until this point, it is unsafe to restart the channel."] pub type CHAN_ABORT_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; impl R { - #[doc = "Bits 0:15 - Each bit corresponds to a channel. Writing a 1 aborts whatever transfer sequence is in progress on that channel. The bit will remain high until any in-flight transfers have been flushed through the address and data FIFOs. - - After writing, this register must be polled until it returns all-zero. Until this point, it is unsafe to restart the channel."] + #[doc = "Bits 0:15 - Each bit corresponds to a channel. Writing a 1 aborts whatever transfer sequence is in progress on that channel. The bit will remain high until any in-flight transfers have been flushed through the address and data FIFOs. After writing, this register must be polled until it returns all-zero. Until this point, it is unsafe to restart the channel."] #[inline(always)] pub fn chan_abort(&self) -> CHAN_ABORT_R { CHAN_ABORT_R::new((self.bits & 0xffff) as u16) } } impl W { - #[doc = "Bits 0:15 - Each bit corresponds to a channel. Writing a 1 aborts whatever transfer sequence is in progress on that channel. The bit will remain high until any in-flight transfers have been flushed through the address and data FIFOs. - - After writing, this register must be polled until it returns all-zero. Until this point, it is unsafe to restart the channel."] + #[doc = "Bits 0:15 - Each bit corresponds to a channel. Writing a 1 aborts whatever transfer sequence is in progress on that channel. The bit will remain high until any in-flight transfers have been flushed through the address and data FIFOs. After writing, this register must be polled until it returns all-zero. Until this point, it is unsafe to restart the channel."] #[inline(always)] #[must_use] pub fn chan_abort(&mut self) -> CHAN_ABORT_W { diff --git a/src/dma/fifo_levels.rs b/src/dma/fifo_levels.rs index 19224ce00..02bbb1ec3 100644 --- a/src/dma/fifo_levels.rs +++ b/src/dma/fifo_levels.rs @@ -1,5 +1,7 @@ #[doc = "Register `FIFO_LEVELS` reader"] pub type R = crate::R; +#[doc = "Register `FIFO_LEVELS` writer"] +pub type W = crate::W; #[doc = "Field `TDF_LVL` reader - Current Transfer-Data-FIFO fill level"] pub type TDF_LVL_R = crate::FieldReader; #[doc = "Field `WAF_LVL` reader - Current Write-Address-FIFO fill level"] @@ -23,15 +25,22 @@ impl R { RAF_LVL_R::new(((self.bits >> 16) & 0xff) as u8) } } +impl W {} #[doc = "Debug RAF, WAF, TDF levels -You can [`read`](crate::generic::Reg::read) this register and get [`fifo_levels::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`fifo_levels::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo_levels::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FIFO_LEVELS_SPEC; impl crate::RegisterSpec for FIFO_LEVELS_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`fifo_levels::R`](R) reader structure"] impl crate::Readable for FIFO_LEVELS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fifo_levels::W`](W) writer structure"] +impl crate::Writable for FIFO_LEVELS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets FIFO_LEVELS to value 0"] impl crate::Resettable for FIFO_LEVELS_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/dma/intr.rs b/src/dma/intr.rs index c84d7c909..c1821d619 100644 --- a/src/dma/intr.rs +++ b/src/dma/intr.rs @@ -2,43 +2,19 @@ pub type R = crate::R; #[doc = "Register `INTR` writer"] pub type W = crate::W; -#[doc = "Field `INTR` reader - Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR, INTS0 or INTS1. - - Channel interrupts can be routed to either of two system-level IRQs based on INTE0 and INTE1. - - This can be used vector different channel interrupts to different ISRs: this might be done to allow NVIC IRQ preemption for more time-critical channels, or to spread IRQ load across different cores. - - It is also valid to ignore this behaviour and just use INTE0/INTS0/IRQ 0."] +#[doc = "Field `INTR` reader - Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR, INTS0 or INTS1. Channel interrupts can be routed to either of two system-level IRQs based on INTE0 and INTE1. This can be used vector different channel interrupts to different ISRs: this might be done to allow NVIC IRQ preemption for more time-critical channels, or to spread IRQ load across different cores. It is also valid to ignore this behaviour and just use INTE0/INTS0/IRQ 0."] pub type INTR_R = crate::FieldReader; -#[doc = "Field `INTR` writer - Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR, INTS0 or INTS1. - - Channel interrupts can be routed to either of two system-level IRQs based on INTE0 and INTE1. - - This can be used vector different channel interrupts to different ISRs: this might be done to allow NVIC IRQ preemption for more time-critical channels, or to spread IRQ load across different cores. - - It is also valid to ignore this behaviour and just use INTE0/INTS0/IRQ 0."] +#[doc = "Field `INTR` writer - Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR, INTS0 or INTS1. Channel interrupts can be routed to either of two system-level IRQs based on INTE0 and INTE1. This can be used vector different channel interrupts to different ISRs: this might be done to allow NVIC IRQ preemption for more time-critical channels, or to spread IRQ load across different cores. It is also valid to ignore this behaviour and just use INTE0/INTS0/IRQ 0."] pub type INTR_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; impl R { - #[doc = "Bits 0:15 - Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR, INTS0 or INTS1. - - Channel interrupts can be routed to either of two system-level IRQs based on INTE0 and INTE1. - - This can be used vector different channel interrupts to different ISRs: this might be done to allow NVIC IRQ preemption for more time-critical channels, or to spread IRQ load across different cores. - - It is also valid to ignore this behaviour and just use INTE0/INTS0/IRQ 0."] + #[doc = "Bits 0:15 - Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR, INTS0 or INTS1. Channel interrupts can be routed to either of two system-level IRQs based on INTE0 and INTE1. This can be used vector different channel interrupts to different ISRs: this might be done to allow NVIC IRQ preemption for more time-critical channels, or to spread IRQ load across different cores. It is also valid to ignore this behaviour and just use INTE0/INTS0/IRQ 0."] #[inline(always)] pub fn intr(&self) -> INTR_R { INTR_R::new((self.bits & 0xffff) as u16) } } impl W { - #[doc = "Bits 0:15 - Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR, INTS0 or INTS1. - - Channel interrupts can be routed to either of two system-level IRQs based on INTE0 and INTE1. - - This can be used vector different channel interrupts to different ISRs: this might be done to allow NVIC IRQ preemption for more time-critical channels, or to spread IRQ load across different cores. - - It is also valid to ignore this behaviour and just use INTE0/INTS0/IRQ 0."] + #[doc = "Bits 0:15 - Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR, INTS0 or INTS1. Channel interrupts can be routed to either of two system-level IRQs based on INTE0 and INTE1. This can be used vector different channel interrupts to different ISRs: this might be done to allow NVIC IRQ preemption for more time-critical channels, or to spread IRQ load across different cores. It is also valid to ignore this behaviour and just use INTE0/INTS0/IRQ 0."] #[inline(always)] #[must_use] pub fn intr(&mut self) -> INTR_W { diff --git a/src/dma/intr1.rs b/src/dma/intr1.rs new file mode 100644 index 000000000..35759db8d --- /dev/null +++ b/src/dma/intr1.rs @@ -0,0 +1,42 @@ +#[doc = "Register `INTR1` reader"] +pub type R = crate::R; +#[doc = "Register `INTR1` writer"] +pub type W = crate::W; +#[doc = "Field `INTR1` reader - Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR, INTS0 or INTS1. Channel interrupts can be routed to either of two system-level IRQs based on INTE0 and INTE1. This can be used vector different channel interrupts to different ISRs: this might be done to allow NVIC IRQ preemption for more time-critical channels, or to spread IRQ load across different cores. It is also valid to ignore this behaviour and just use INTE0/INTS0/IRQ 0."] +pub type INTR1_R = crate::FieldReader; +#[doc = "Field `INTR1` writer - Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR, INTS0 or INTS1. Channel interrupts can be routed to either of two system-level IRQs based on INTE0 and INTE1. This can be used vector different channel interrupts to different ISRs: this might be done to allow NVIC IRQ preemption for more time-critical channels, or to spread IRQ load across different cores. It is also valid to ignore this behaviour and just use INTE0/INTS0/IRQ 0."] +pub type INTR1_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR, INTS0 or INTS1. Channel interrupts can be routed to either of two system-level IRQs based on INTE0 and INTE1. This can be used vector different channel interrupts to different ISRs: this might be done to allow NVIC IRQ preemption for more time-critical channels, or to spread IRQ load across different cores. It is also valid to ignore this behaviour and just use INTE0/INTS0/IRQ 0."] + #[inline(always)] + pub fn intr1(&self) -> INTR1_R { + INTR1_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR, INTS0 or INTS1. Channel interrupts can be routed to either of two system-level IRQs based on INTE0 and INTE1. This can be used vector different channel interrupts to different ISRs: this might be done to allow NVIC IRQ preemption for more time-critical channels, or to spread IRQ load across different cores. It is also valid to ignore this behaviour and just use INTE0/INTS0/IRQ 0."] + #[inline(always)] + #[must_use] + pub fn intr1(&mut self) -> INTR1_W { + INTR1_W::new(self, 0) + } +} +#[doc = "Interrupt Status (raw) + +You can [`read`](crate::generic::Reg::read) this register and get [`intr1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTR1_SPEC; +impl crate::RegisterSpec for INTR1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`intr1::R`](R) reader structure"] +impl crate::Readable for INTR1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`intr1::W`](W) writer structure"] +impl crate::Writable for INTR1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0xffff; +} +#[doc = "`reset()` method sets INTR1 to value 0"] +impl crate::Resettable for INTR1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/ints0.rs b/src/dma/ints0.rs index 994a68e80..dc6bb8079 100644 --- a/src/dma/ints0.rs +++ b/src/dma/ints0.rs @@ -2,23 +2,19 @@ pub type R = crate::R; #[doc = "Register `INTS0` writer"] pub type W = crate::W; -#[doc = "Field `INTS0` reader - Indicates active channel interrupt requests which are currently causing IRQ 0 to be asserted. - Channel interrupts can be cleared by writing a bit mask here."] +#[doc = "Field `INTS0` reader - Indicates active channel interrupt requests which are currently causing IRQ 0 to be asserted. Channel interrupts can be cleared by writing a bit mask here."] pub type INTS0_R = crate::FieldReader; -#[doc = "Field `INTS0` writer - Indicates active channel interrupt requests which are currently causing IRQ 0 to be asserted. - Channel interrupts can be cleared by writing a bit mask here."] +#[doc = "Field `INTS0` writer - Indicates active channel interrupt requests which are currently causing IRQ 0 to be asserted. Channel interrupts can be cleared by writing a bit mask here."] pub type INTS0_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; impl R { - #[doc = "Bits 0:15 - Indicates active channel interrupt requests which are currently causing IRQ 0 to be asserted. - Channel interrupts can be cleared by writing a bit mask here."] + #[doc = "Bits 0:15 - Indicates active channel interrupt requests which are currently causing IRQ 0 to be asserted. Channel interrupts can be cleared by writing a bit mask here."] #[inline(always)] pub fn ints0(&self) -> INTS0_R { INTS0_R::new((self.bits & 0xffff) as u16) } } impl W { - #[doc = "Bits 0:15 - Indicates active channel interrupt requests which are currently causing IRQ 0 to be asserted. - Channel interrupts can be cleared by writing a bit mask here."] + #[doc = "Bits 0:15 - Indicates active channel interrupt requests which are currently causing IRQ 0 to be asserted. Channel interrupts can be cleared by writing a bit mask here."] #[inline(always)] #[must_use] pub fn ints0(&mut self) -> INTS0_W { diff --git a/src/dma/ints1.rs b/src/dma/ints1.rs index 78beebea6..f00d5a0b0 100644 --- a/src/dma/ints1.rs +++ b/src/dma/ints1.rs @@ -2,23 +2,19 @@ pub type R = crate::R; #[doc = "Register `INTS1` writer"] pub type W = crate::W; -#[doc = "Field `INTS1` reader - Indicates active channel interrupt requests which are currently causing IRQ 1 to be asserted. - Channel interrupts can be cleared by writing a bit mask here."] +#[doc = "Field `INTS1` reader - Indicates active channel interrupt requests which are currently causing IRQ 1 to be asserted. Channel interrupts can be cleared by writing a bit mask here."] pub type INTS1_R = crate::FieldReader; -#[doc = "Field `INTS1` writer - Indicates active channel interrupt requests which are currently causing IRQ 1 to be asserted. - Channel interrupts can be cleared by writing a bit mask here."] +#[doc = "Field `INTS1` writer - Indicates active channel interrupt requests which are currently causing IRQ 1 to be asserted. Channel interrupts can be cleared by writing a bit mask here."] pub type INTS1_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; impl R { - #[doc = "Bits 0:15 - Indicates active channel interrupt requests which are currently causing IRQ 1 to be asserted. - Channel interrupts can be cleared by writing a bit mask here."] + #[doc = "Bits 0:15 - Indicates active channel interrupt requests which are currently causing IRQ 1 to be asserted. Channel interrupts can be cleared by writing a bit mask here."] #[inline(always)] pub fn ints1(&self) -> INTS1_R { INTS1_R::new((self.bits & 0xffff) as u16) } } impl W { - #[doc = "Bits 0:15 - Indicates active channel interrupt requests which are currently causing IRQ 1 to be asserted. - Channel interrupts can be cleared by writing a bit mask here."] + #[doc = "Bits 0:15 - Indicates active channel interrupt requests which are currently causing IRQ 1 to be asserted. Channel interrupts can be cleared by writing a bit mask here."] #[inline(always)] #[must_use] pub fn ints1(&mut self) -> INTS1_W { diff --git a/src/dma/multi_chan_trigger.rs b/src/dma/multi_chan_trigger.rs index 0eb8b0e67..83e2a38e9 100644 --- a/src/dma/multi_chan_trigger.rs +++ b/src/dma/multi_chan_trigger.rs @@ -2,17 +2,8 @@ pub type R = crate::R; #[doc = "Register `MULTI_CHAN_TRIGGER` writer"] pub type W = crate::W; -#[doc = "Field `MULTI_CHAN_TRIGGER` reader - Each bit in this register corresponds to a DMA channel. Writing a 1 to the relevant bit is the same as writing to that channel's trigger register; the channel will start if it is currently enabled and not already busy."] -pub type MULTI_CHAN_TRIGGER_R = crate::FieldReader; #[doc = "Field `MULTI_CHAN_TRIGGER` writer - Each bit in this register corresponds to a DMA channel. Writing a 1 to the relevant bit is the same as writing to that channel's trigger register; the channel will start if it is currently enabled and not already busy."] pub type MULTI_CHAN_TRIGGER_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -impl R { - #[doc = "Bits 0:15 - Each bit in this register corresponds to a DMA channel. Writing a 1 to the relevant bit is the same as writing to that channel's trigger register; the channel will start if it is currently enabled and not already busy."] - #[inline(always)] - pub fn multi_chan_trigger(&self) -> MULTI_CHAN_TRIGGER_R { - MULTI_CHAN_TRIGGER_R::new((self.bits & 0xffff) as u16) - } -} impl W { #[doc = "Bits 0:15 - Each bit in this register corresponds to a DMA channel. Writing a 1 to the relevant bit is the same as writing to that channel's trigger register; the channel will start if it is currently enabled and not already busy."] #[inline(always)] diff --git a/src/dma/n_channels.rs b/src/dma/n_channels.rs index ae6c2bc5f..71a7e0fcf 100644 --- a/src/dma/n_channels.rs +++ b/src/dma/n_channels.rs @@ -1,5 +1,7 @@ #[doc = "Register `N_CHANNELS` reader"] pub type R = crate::R; +#[doc = "Register `N_CHANNELS` writer"] +pub type W = crate::W; #[doc = "Field `N_CHANNELS` reader - "] pub type N_CHANNELS_R = crate::FieldReader; impl R { @@ -9,15 +11,22 @@ impl R { N_CHANNELS_R::new((self.bits & 0x1f) as u8) } } +impl W {} #[doc = "The number of channels this DMA instance is equipped with. This DMA supports up to 16 hardware channels, but can be configured with as few as one, to minimise silicon area. -You can [`read`](crate::generic::Reg::read) this register and get [`n_channels::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`n_channels::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`n_channels::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct N_CHANNELS_SPEC; impl crate::RegisterSpec for N_CHANNELS_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`n_channels::R`](R) reader structure"] impl crate::Readable for N_CHANNELS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`n_channels::W`](W) writer structure"] +impl crate::Writable for N_CHANNELS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets N_CHANNELS to value 0"] impl crate::Resettable for N_CHANNELS_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/dma/sniff_ctrl.rs b/src/dma/sniff_ctrl.rs index 1e4432c05..75ad30de3 100644 --- a/src/dma/sniff_ctrl.rs +++ b/src/dma/sniff_ctrl.rs @@ -123,13 +123,9 @@ where self.variant(CALC_A::SUM) } } -#[doc = "Field `BSWAP` reader - Locally perform a byte reverse on the sniffed data, before feeding into checksum. - - Note that the sniff hardware is downstream of the DMA channel byteswap performed in the read master: if channel CTRL_BSWAP and SNIFF_CTRL_BSWAP are both enabled, their effects cancel from the sniffer's point of view."] +#[doc = "Field `BSWAP` reader - Locally perform a byte reverse on the sniffed data, before feeding into checksum. Note that the sniff hardware is downstream of the DMA channel byteswap performed in the read master: if channel CTRL_BSWAP and SNIFF_CTRL_BSWAP are both enabled, their effects cancel from the sniffer's point of view."] pub type BSWAP_R = crate::BitReader; -#[doc = "Field `BSWAP` writer - Locally perform a byte reverse on the sniffed data, before feeding into checksum. - - Note that the sniff hardware is downstream of the DMA channel byteswap performed in the read master: if channel CTRL_BSWAP and SNIFF_CTRL_BSWAP are both enabled, their effects cancel from the sniffer's point of view."] +#[doc = "Field `BSWAP` writer - Locally perform a byte reverse on the sniffed data, before feeding into checksum. Note that the sniff hardware is downstream of the DMA channel byteswap performed in the read master: if channel CTRL_BSWAP and SNIFF_CTRL_BSWAP are both enabled, their effects cancel from the sniffer's point of view."] pub type BSWAP_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `OUT_REV` reader - If set, the result appears bit-reversed when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus."] pub type OUT_REV_R = crate::BitReader; @@ -155,9 +151,7 @@ impl R { pub fn calc(&self) -> CALC_R { CALC_R::new(((self.bits >> 5) & 0x0f) as u8) } - #[doc = "Bit 9 - Locally perform a byte reverse on the sniffed data, before feeding into checksum. - - Note that the sniff hardware is downstream of the DMA channel byteswap performed in the read master: if channel CTRL_BSWAP and SNIFF_CTRL_BSWAP are both enabled, their effects cancel from the sniffer's point of view."] + #[doc = "Bit 9 - Locally perform a byte reverse on the sniffed data, before feeding into checksum. Note that the sniff hardware is downstream of the DMA channel byteswap performed in the read master: if channel CTRL_BSWAP and SNIFF_CTRL_BSWAP are both enabled, their effects cancel from the sniffer's point of view."] #[inline(always)] pub fn bswap(&self) -> BSWAP_R { BSWAP_R::new(((self.bits >> 9) & 1) != 0) @@ -192,9 +186,7 @@ impl W { pub fn calc(&mut self) -> CALC_W { CALC_W::new(self, 5) } - #[doc = "Bit 9 - Locally perform a byte reverse on the sniffed data, before feeding into checksum. - - Note that the sniff hardware is downstream of the DMA channel byteswap performed in the read master: if channel CTRL_BSWAP and SNIFF_CTRL_BSWAP are both enabled, their effects cancel from the sniffer's point of view."] + #[doc = "Bit 9 - Locally perform a byte reverse on the sniffed data, before feeding into checksum. Note that the sniff hardware is downstream of the DMA channel byteswap performed in the read master: if channel CTRL_BSWAP and SNIFF_CTRL_BSWAP are both enabled, their effects cancel from the sniffer's point of view."] #[inline(always)] #[must_use] pub fn bswap(&mut self) -> BSWAP_W { diff --git a/src/dma/sniff_data.rs b/src/dma/sniff_data.rs index 298f49b3a..47cf7cfa0 100644 --- a/src/dma/sniff_data.rs +++ b/src/dma/sniff_data.rs @@ -2,19 +2,26 @@ pub type R = crate::R; #[doc = "Register `SNIFF_DATA` writer"] pub type W = crate::W; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) +#[doc = "Field `SNIFF_DATA` reader - Write an initial seed value here before starting a DMA transfer on the channel indicated by SNIFF_CTRL_DMACH. The hardware will update this register each time it observes a read from the indicated channel. Once the channel completes, the final result can be read from this register."] +pub type SNIFF_DATA_R = crate::FieldReader; +#[doc = "Field `SNIFF_DATA` writer - Write an initial seed value here before starting a DMA transfer on the channel indicated by SNIFF_CTRL_DMACH. The hardware will update this register each time it observes a read from the indicated channel. Once the channel completes, the final result can be read from this register."] +pub type SNIFF_DATA_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Write an initial seed value here before starting a DMA transfer on the channel indicated by SNIFF_CTRL_DMACH. The hardware will update this register each time it observes a read from the indicated channel. Once the channel completes, the final result can be read from this register."] + #[inline(always)] + pub fn sniff_data(&self) -> SNIFF_DATA_R { + SNIFF_DATA_R::new(self.bits) } } -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +impl W { + #[doc = "Bits 0:31 - Write an initial seed value here before starting a DMA transfer on the channel indicated by SNIFF_CTRL_DMACH. The hardware will update this register each time it observes a read from the indicated channel. Once the channel completes, the final result can be read from this register."] + #[inline(always)] + #[must_use] + pub fn sniff_data(&mut self) -> SNIFF_DATA_W { + SNIFF_DATA_W::new(self, 0) } } -impl W {} #[doc = "Data accumulator for sniff hardware - Write an initial seed value here before starting a DMA transfer on the channel indicated by SNIFF_CTRL_DMACH. The hardware will update this register each time it observes a read from the indicated channel. Once the channel completes, the final result can be read from this register. You can [`read`](crate::generic::Reg::read) this register and get [`sniff_data::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sniff_data::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SNIFF_DATA_SPEC; diff --git a/src/dma/timer0.rs b/src/dma/timer0.rs index b0c0d1395..57ae950a8 100644 --- a/src/dma/timer0.rs +++ b/src/dma/timer0.rs @@ -36,8 +36,7 @@ impl W { X_W::new(self, 16) } } -#[doc = "Pacing (X/Y) Fractional Timer - The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. +#[doc = "Pacing (X/Y) Fractional Timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. You can [`read`](crate::generic::Reg::read) this register and get [`timer0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timer0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TIMER0_SPEC; diff --git a/src/dma/timer1.rs b/src/dma/timer1.rs index ddf44a745..061918190 100644 --- a/src/dma/timer1.rs +++ b/src/dma/timer1.rs @@ -36,8 +36,7 @@ impl W { X_W::new(self, 16) } } -#[doc = "Pacing (X/Y) Fractional Timer - The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. +#[doc = "Pacing (X/Y) Fractional Timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. You can [`read`](crate::generic::Reg::read) this register and get [`timer1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timer1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TIMER1_SPEC; diff --git a/src/dma/timer2.rs b/src/dma/timer2.rs index b23b748cb..187b290e6 100644 --- a/src/dma/timer2.rs +++ b/src/dma/timer2.rs @@ -36,8 +36,7 @@ impl W { X_W::new(self, 16) } } -#[doc = "Pacing (X/Y) Fractional Timer - The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. +#[doc = "Pacing (X/Y) Fractional Timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. You can [`read`](crate::generic::Reg::read) this register and get [`timer2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timer2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TIMER2_SPEC; diff --git a/src/dma/timer3.rs b/src/dma/timer3.rs index 0041ca097..75a306db8 100644 --- a/src/dma/timer3.rs +++ b/src/dma/timer3.rs @@ -36,8 +36,7 @@ impl W { X_W::new(self, 16) } } -#[doc = "Pacing (X/Y) Fractional Timer - The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. +#[doc = "Pacing (X/Y) Fractional Timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. You can [`read`](crate::generic::Reg::read) this register and get [`timer3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timer3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TIMER3_SPEC; diff --git a/src/i2c0.rs b/src/i2c0.rs index 5e09fdf84..4c942273d 100644 --- a/src/i2c0.rs +++ b/src/i2c0.rs @@ -50,19 +50,13 @@ pub struct RegisterBlock { } impl RegisterBlock { #[doc = "0x00 - I2C Control Register. This register can be written only when the DW_apb_i2c is disabled, which corresponds to the IC_ENABLE\\[0\\] -register being set to 0. Writes at other times have no effect. - - Read/Write Access: - bit 10 is read only. - bit 11 is read only - bit 16 is read only - bit 17 is read only - bits 18 and 19 are read only."] +register being set to 0. Writes at other times have no effect. Read/Write Access: - bit 10 is read only. - bit 11 is read only - bit 16 is read only - bit 17 is read only - bits 18 and 19 are read only."] #[inline(always)] pub const fn ic_con(&self) -> &IC_CON { &self.ic_con } - #[doc = "0x04 - I2C Target Address Register - - This register is 12 bits wide, and bits 31:12 are reserved. This register can be written to only when IC_ENABLE\\[0\\] -is set to 0. - - Note: If the software or application is aware that the DW_apb_i2c is not using the TAR address for the pending commands in the Tx FIFO, then it is possible to update the TAR address even while the Tx FIFO has entries (IC_STATUS\\[2\\]= 0). - It is not necessary to perform any write to this register if DW_apb_i2c is enabled as an I2C slave only."] + #[doc = "0x04 - I2C Target Address Register This register is 12 bits wide, and bits 31:12 are reserved. This register can be written to only when IC_ENABLE\\[0\\] +is set to 0. Note: If the software or application is aware that the DW_apb_i2c is not using the TAR address for the pending commands in the Tx FIFO, then it is possible to update the TAR address even while the Tx FIFO has entries (IC_STATUS\\[2\\]= 0). - It is not necessary to perform any write to this register if DW_apb_i2c is enabled as an I2C slave only."] #[inline(always)] pub const fn ic_tar(&self) -> &IC_TAR { &self.ic_tar @@ -72,11 +66,7 @@ is set to 0. pub const fn ic_sar(&self) -> &IC_SAR { &self.ic_sar } - #[doc = "0x10 - I2C Rx/Tx Data Buffer and Command Register; this is the register the CPU writes to when filling the TX FIFO and the CPU reads from when retrieving bytes from RX FIFO. - - The size of the register changes as follows: - - Write: - 11 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=1 - 9 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=0 Read: - 12 bits when IC_FIRST_DATA_BYTE_STATUS = 1 - 8 bits when IC_FIRST_DATA_BYTE_STATUS = 0 Note: In order for the DW_apb_i2c to continue acknowledging reads, a read command should be written for every byte that is to be received; otherwise the DW_apb_i2c will stop acknowledging."] + #[doc = "0x10 - I2C Rx/Tx Data Buffer and Command Register; this is the register the CPU writes to when filling the TX FIFO and the CPU reads from when retrieving bytes from RX FIFO. The size of the register changes as follows: Write: - 11 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=1 - 9 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=0 Read: - 12 bits when IC_FIRST_DATA_BYTE_STATUS = 1 - 8 bits when IC_FIRST_DATA_BYTE_STATUS = 0 Note: In order for the DW_apb_i2c to continue acknowledging reads, a read command should be written for every byte that is to be received; otherwise the DW_apb_i2c will stop acknowledging."] #[inline(always)] pub const fn ic_data_cmd(&self) -> &IC_DATA_CMD { &self.ic_data_cmd @@ -101,23 +91,17 @@ is set to 0. pub const fn ic_fs_scl_lcnt(&self) -> &IC_FS_SCL_LCNT { &self.ic_fs_scl_lcnt } - #[doc = "0x2c - I2C Interrupt Status Register - - Each bit in this register has a corresponding mask bit in the IC_INTR_MASK register. These bits are cleared by reading the matching interrupt clear register. The unmasked raw versions of these bits are available in the IC_RAW_INTR_STAT register."] + #[doc = "0x2c - I2C Interrupt Status Register Each bit in this register has a corresponding mask bit in the IC_INTR_MASK register. These bits are cleared by reading the matching interrupt clear register. The unmasked raw versions of these bits are available in the IC_RAW_INTR_STAT register."] #[inline(always)] pub const fn ic_intr_stat(&self) -> &IC_INTR_STAT { &self.ic_intr_stat } - #[doc = "0x30 - I2C Interrupt Mask Register. - - These bits mask their corresponding interrupt status bits. This register is active low; a value of 0 masks the interrupt, whereas a value of 1 unmasks the interrupt."] + #[doc = "0x30 - I2C Interrupt Mask Register. These bits mask their corresponding interrupt status bits. This register is active low; a value of 0 masks the interrupt, whereas a value of 1 unmasks the interrupt."] #[inline(always)] pub const fn ic_intr_mask(&self) -> &IC_INTR_MASK { &self.ic_intr_mask } - #[doc = "0x34 - I2C Raw Interrupt Status Register - - Unlike the IC_INTR_STAT register, these bits are not masked so they always show the true status of the DW_apb_i2c."] + #[doc = "0x34 - I2C Raw Interrupt Status Register Unlike the IC_INTR_STAT register, these bits are not masked so they always show the true status of the DW_apb_i2c."] #[inline(always)] pub const fn ic_raw_intr_stat(&self) -> &IC_RAW_INTR_STAT { &self.ic_raw_intr_stat @@ -192,11 +176,7 @@ is set to 0. pub const fn ic_enable(&self) -> &IC_ENABLE { &self.ic_enable } - #[doc = "0x70 - I2C Status Register - - This is a read-only register used to indicate the current transfer status and FIFO status. The status register may be read at any time. None of the bits in this register request an interrupt. - - When the I2C is disabled by writing 0 in bit 0 of the IC_ENABLE register: - Bits 1 and 2 are set to 1 - Bits 3 and 10 are set to 0 When the master or slave state machines goes to idle and ic_en=0: - Bits 5 and 6 are set to 0"] + #[doc = "0x70 - I2C Status Register This is a read-only register used to indicate the current transfer status and FIFO status. The status register may be read at any time. None of the bits in this register request an interrupt. When the I2C is disabled by writing 0 in bit 0 of the IC_ENABLE register: - Bits 1 and 2 are set to 1 - Bits 3 and 10 are set to 0 When the master or slave state machines goes to idle and ic_en=0: - Bits 5 and 6 are set to 0"] #[inline(always)] pub const fn ic_status(&self) -> &IC_STATUS { &self.ic_status @@ -211,37 +191,19 @@ is set to 0. pub const fn ic_rxflr(&self) -> &IC_RXFLR { &self.ic_rxflr } - #[doc = "0x7c - I2C SDA Hold Time Length Register - - The bits \\[15:0\\] -of this register are used to control the hold time of SDA during transmit in both slave and master mode (after SCL goes from HIGH to LOW). - - The bits \\[23:16\\] -of this register are used to extend the SDA transition (if any) whenever SCL is HIGH in the receiver in either master or slave mode. - - Writes to this register succeed only when IC_ENABLE\\[0\\]=0. - - The values in this register are in units of ic_clk period. The value programmed in IC_SDA_TX_HOLD must be greater than the minimum hold time in each mode (one cycle in master mode, seven cycles in slave mode) for the value to be implemented. - - The programmed SDA hold time during transmit (IC_SDA_TX_HOLD) cannot exceed at any time the duration of the low part of scl. Therefore the programmed value cannot be larger than N_SCL_LOW-2, where N_SCL_LOW is the duration of the low part of the scl period measured in ic_clk cycles."] + #[doc = "0x7c - I2C SDA Hold Time Length Register The bits \\[15:0\\] +of this register are used to control the hold time of SDA during transmit in both slave and master mode (after SCL goes from HIGH to LOW). The bits \\[23:16\\] +of this register are used to extend the SDA transition (if any) whenever SCL is HIGH in the receiver in either master or slave mode. Writes to this register succeed only when IC_ENABLE\\[0\\]=0. The values in this register are in units of ic_clk period. The value programmed in IC_SDA_TX_HOLD must be greater than the minimum hold time in each mode (one cycle in master mode, seven cycles in slave mode) for the value to be implemented. The programmed SDA hold time during transmit (IC_SDA_TX_HOLD) cannot exceed at any time the duration of the low part of scl. Therefore the programmed value cannot be larger than N_SCL_LOW-2, where N_SCL_LOW is the duration of the low part of the scl period measured in ic_clk cycles."] #[inline(always)] pub const fn ic_sda_hold(&self) -> &IC_SDA_HOLD { &self.ic_sda_hold } - #[doc = "0x80 - I2C Transmit Abort Source Register - - This register has 32 bits that indicate the source of the TX_ABRT bit. Except for Bit 9, this register is cleared whenever the IC_CLR_TX_ABRT register or the IC_CLR_INTR register is read. To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; RESTART must be enabled (IC_CON\\[5\\]=1), the SPECIAL bit must be cleared (IC_TAR\\[11\\]), or the GC_OR_START bit must be cleared (IC_TAR\\[10\\]). - - Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, Bit 9 clears for one cycle and is then re-asserted."] + #[doc = "0x80 - I2C Transmit Abort Source Register This register has 32 bits that indicate the source of the TX_ABRT bit. Except for Bit 9, this register is cleared whenever the IC_CLR_TX_ABRT register or the IC_CLR_INTR register is read. To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; RESTART must be enabled (IC_CON\\[5\\]=1), the SPECIAL bit must be cleared (IC_TAR\\[11\\]), or the GC_OR_START bit must be cleared (IC_TAR\\[10\\]). Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, Bit 9 clears for one cycle and is then re-asserted."] #[inline(always)] pub const fn ic_tx_abrt_source(&self) -> &IC_TX_ABRT_SOURCE { &self.ic_tx_abrt_source } - #[doc = "0x84 - Generate Slave Data NACK Register - - The register is used to generate a NACK for the data part of a transfer when DW_apb_i2c is acting as a slave-receiver. This register only exists when the IC_SLV_DATA_NACK_ONLY parameter is set to 1. When this parameter disabled, this register does not exist and writing to the register's address has no effect. - - A write can occur on this register if both of the following conditions are met: - DW_apb_i2c is disabled (IC_ENABLE\\[0\\] + #[doc = "0x84 - Generate Slave Data NACK Register The register is used to generate a NACK for the data part of a transfer when DW_apb_i2c is acting as a slave-receiver. This register only exists when the IC_SLV_DATA_NACK_ONLY parameter is set to 1. When this parameter disabled, this register does not exist and writing to the register's address has no effect. A write can occur on this register if both of the following conditions are met: - DW_apb_i2c is disabled (IC_ENABLE\\[0\\] = 0) - Slave part is inactive (IC_STATUS\\[6\\] = 0) Note: The IC_STATUS\\[6\\] is a register read-back location for the internal slv_activity signal; the user should poll this before writing the ic_slv_data_nack_only bit."] @@ -249,9 +211,7 @@ is a register read-back location for the internal slv_activity signal; the user pub const fn ic_slv_data_nack_only(&self) -> &IC_SLV_DATA_NACK_ONLY { &self.ic_slv_data_nack_only } - #[doc = "0x88 - DMA Control Register - - The register is used to enable the DMA Controller interface operation. There is a separate bit for transmit and receive. This can be programmed regardless of the state of IC_ENABLE."] + #[doc = "0x88 - DMA Control Register The register is used to enable the DMA Controller interface operation. There is a separate bit for transmit and receive. This can be programmed regardless of the state of IC_ENABLE."] #[inline(always)] pub const fn ic_dma_cr(&self) -> &IC_DMA_CR { &self.ic_dma_cr @@ -266,47 +226,27 @@ is a register read-back location for the internal slv_activity signal; the user pub const fn ic_dma_rdlr(&self) -> &IC_DMA_RDLR { &self.ic_dma_rdlr } - #[doc = "0x94 - I2C SDA Setup Register - - This register controls the amount of time delay (in terms of number of ic_clk clock periods) introduced in the rising edge of SCL - relative to SDA changing - when DW_apb_i2c services a read request in a slave-transmitter operation. The relevant I2C requirement is tSU:DAT (note 4) as detailed in the I2C Bus Specification. This register must be programmed with a value equal to or greater than 2. - - Writes to this register succeed only when IC_ENABLE\\[0\\] -= 0. - - Note: The length of setup time is calculated using \\[(IC_SDA_SETUP - 1) * (ic_clk_period)\\], so if the user requires 10 ic_clk periods of setup time, they should program a value of 11. The IC_SDA_SETUP register is only used by the DW_apb_i2c when operating as a slave transmitter."] + #[doc = "0x94 - I2C SDA Setup Register This register controls the amount of time delay (in terms of number of ic_clk clock periods) introduced in the rising edge of SCL - relative to SDA changing - when DW_apb_i2c services a read request in a slave-transmitter operation. The relevant I2C requirement is tSU:DAT (note 4) as detailed in the I2C Bus Specification. This register must be programmed with a value equal to or greater than 2. Writes to this register succeed only when IC_ENABLE\\[0\\] += 0. Note: The length of setup time is calculated using \\[(IC_SDA_SETUP - 1) * (ic_clk_period)\\], so if the user requires 10 ic_clk periods of setup time, they should program a value of 11. The IC_SDA_SETUP register is only used by the DW_apb_i2c when operating as a slave transmitter."] #[inline(always)] pub const fn ic_sda_setup(&self) -> &IC_SDA_SETUP { &self.ic_sda_setup } - #[doc = "0x98 - I2C ACK General Call Register - - The register controls whether DW_apb_i2c responds with a ACK or NACK when it receives an I2C General Call address. - - This register is applicable only when the DW_apb_i2c is in slave mode."] + #[doc = "0x98 - I2C ACK General Call Register The register controls whether DW_apb_i2c responds with a ACK or NACK when it receives an I2C General Call address. This register is applicable only when the DW_apb_i2c is in slave mode."] #[inline(always)] pub const fn ic_ack_general_call(&self) -> &IC_ACK_GENERAL_CALL { &self.ic_ack_general_call } - #[doc = "0x9c - I2C Enable Status Register - - The register is used to report the DW_apb_i2c hardware status when the IC_ENABLE\\[0\\] -register is set from 1 to 0; that is, when DW_apb_i2c is disabled. - - If IC_ENABLE\\[0\\] -has been set to 1, bits 2:1 are forced to 0, and bit 0 is forced to 1. - - If IC_ENABLE\\[0\\] -has been set to 0, bits 2:1 is only be valid as soon as bit 0 is read as '0'. - - Note: When IC_ENABLE\\[0\\] + #[doc = "0x9c - I2C Enable Status Register The register is used to report the DW_apb_i2c hardware status when the IC_ENABLE\\[0\\] +register is set from 1 to 0; that is, when DW_apb_i2c is disabled. If IC_ENABLE\\[0\\] +has been set to 1, bits 2:1 are forced to 0, and bit 0 is forced to 1. If IC_ENABLE\\[0\\] +has been set to 0, bits 2:1 is only be valid as soon as bit 0 is read as '0'. Note: When IC_ENABLE\\[0\\] has been set to 0, a delay occurs for bit 0 to be read as 0 because disabling the DW_apb_i2c depends on I2C bus activities."] #[inline(always)] pub const fn ic_enable_status(&self) -> &IC_ENABLE_STATUS { &self.ic_enable_status } - #[doc = "0xa0 - I2C SS, FS or FM+ spike suppression limit - - This register is used to store the duration, measured in ic_clk cycles, of the longest spike that is filtered out by the spike suppression logic when the component is operating in SS, FS or FM+ modes. The relevant I2C requirement is tSP (table 4) as detailed in the I2C Bus Specification. This register must be programmed with a minimum value of 1."] + #[doc = "0xa0 - I2C SS, FS or FM+ spike suppression limit This register is used to store the duration, measured in ic_clk cycles, of the longest spike that is filtered out by the spike suppression logic when the component is operating in SS, FS or FM+ modes. The relevant I2C requirement is tSP (table 4) as detailed in the I2C Bus Specification. This register must be programmed with a minimum value of 1."] #[inline(always)] pub const fn ic_fs_spklen(&self) -> &IC_FS_SPKLEN { &self.ic_fs_spklen @@ -316,9 +256,7 @@ has been set to 0, a delay occurs for bit 0 to be read as 0 because disabling th pub const fn ic_clr_restart_det(&self) -> &IC_CLR_RESTART_DET { &self.ic_clr_restart_det } - #[doc = "0xf4 - Component Parameter Register 1 - - Note This register is not implemented and therefore reads as 0. If it was implemented it would be a constant read-only register that contains encoded information about the component's parameter settings. Fields shown below are the settings for those parameters"] + #[doc = "0xf4 - Component Parameter Register 1 Note This register is not implemented and therefore reads as 0. If it was implemented it would be a constant read-only register that contains encoded information about the component's parameter settings. Fields shown below are the settings for those parameters"] #[inline(always)] pub const fn ic_comp_param_1(&self) -> &IC_COMP_PARAM_1 { &self.ic_comp_param_1 @@ -335,9 +273,7 @@ has been set to 0, a delay occurs for bit 0 to be read as 0 because disabling th } } #[doc = "IC_CON (rw) register accessor: I2C Control Register. This register can be written only when the DW_apb_i2c is disabled, which corresponds to the IC_ENABLE\\[0\\] -register being set to 0. Writes at other times have no effect. - - Read/Write Access: - bit 10 is read only. - bit 11 is read only - bit 16 is read only - bit 17 is read only - bits 18 and 19 are read only. +register being set to 0. Writes at other times have no effect. Read/Write Access: - bit 10 is read only. - bit 11 is read only - bit 16 is read only - bit 17 is read only - bits 18 and 19 are read only. You can [`read`](crate::generic::Reg::read) this register and get [`ic_con::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_con::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). @@ -345,28 +281,18 @@ For information about available fields see [`mod@ic_con`] module"] pub type IC_CON = crate::Reg; #[doc = "I2C Control Register. This register can be written only when the DW_apb_i2c is disabled, which corresponds to the IC_ENABLE\\[0\\] -register being set to 0. Writes at other times have no effect. - - Read/Write Access: - bit 10 is read only. - bit 11 is read only - bit 16 is read only - bit 17 is read only - bits 18 and 19 are read only."] +register being set to 0. Writes at other times have no effect. Read/Write Access: - bit 10 is read only. - bit 11 is read only - bit 16 is read only - bit 17 is read only - bits 18 and 19 are read only."] pub mod ic_con; -#[doc = "IC_TAR (rw) register accessor: I2C Target Address Register - - This register is 12 bits wide, and bits 31:12 are reserved. This register can be written to only when IC_ENABLE\\[0\\] -is set to 0. - - Note: If the software or application is aware that the DW_apb_i2c is not using the TAR address for the pending commands in the Tx FIFO, then it is possible to update the TAR address even while the Tx FIFO has entries (IC_STATUS\\[2\\]= 0). - It is not necessary to perform any write to this register if DW_apb_i2c is enabled as an I2C slave only. +#[doc = "IC_TAR (rw) register accessor: I2C Target Address Register This register is 12 bits wide, and bits 31:12 are reserved. This register can be written to only when IC_ENABLE\\[0\\] +is set to 0. Note: If the software or application is aware that the DW_apb_i2c is not using the TAR address for the pending commands in the Tx FIFO, then it is possible to update the TAR address even while the Tx FIFO has entries (IC_STATUS\\[2\\]= 0). - It is not necessary to perform any write to this register if DW_apb_i2c is enabled as an I2C slave only. You can [`read`](crate::generic::Reg::read) this register and get [`ic_tar::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_tar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@ic_tar`] module"] pub type IC_TAR = crate::Reg; -#[doc = "I2C Target Address Register - - This register is 12 bits wide, and bits 31:12 are reserved. This register can be written to only when IC_ENABLE\\[0\\] -is set to 0. - - Note: If the software or application is aware that the DW_apb_i2c is not using the TAR address for the pending commands in the Tx FIFO, then it is possible to update the TAR address even while the Tx FIFO has entries (IC_STATUS\\[2\\]= 0). - It is not necessary to perform any write to this register if DW_apb_i2c is enabled as an I2C slave only."] +#[doc = "I2C Target Address Register This register is 12 bits wide, and bits 31:12 are reserved. This register can be written to only when IC_ENABLE\\[0\\] +is set to 0. Note: If the software or application is aware that the DW_apb_i2c is not using the TAR address for the pending commands in the Tx FIFO, then it is possible to update the TAR address even while the Tx FIFO has entries (IC_STATUS\\[2\\]= 0). - It is not necessary to perform any write to this register if DW_apb_i2c is enabled as an I2C slave only."] pub mod ic_tar; #[doc = "IC_SAR (rw) register accessor: I2C Slave Address Register @@ -377,22 +303,14 @@ module"] pub type IC_SAR = crate::Reg; #[doc = "I2C Slave Address Register"] pub mod ic_sar; -#[doc = "IC_DATA_CMD (rw) register accessor: I2C Rx/Tx Data Buffer and Command Register; this is the register the CPU writes to when filling the TX FIFO and the CPU reads from when retrieving bytes from RX FIFO. - - The size of the register changes as follows: - - Write: - 11 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=1 - 9 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=0 Read: - 12 bits when IC_FIRST_DATA_BYTE_STATUS = 1 - 8 bits when IC_FIRST_DATA_BYTE_STATUS = 0 Note: In order for the DW_apb_i2c to continue acknowledging reads, a read command should be written for every byte that is to be received; otherwise the DW_apb_i2c will stop acknowledging. +#[doc = "IC_DATA_CMD (rw) register accessor: I2C Rx/Tx Data Buffer and Command Register; this is the register the CPU writes to when filling the TX FIFO and the CPU reads from when retrieving bytes from RX FIFO. The size of the register changes as follows: Write: - 11 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=1 - 9 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=0 Read: - 12 bits when IC_FIRST_DATA_BYTE_STATUS = 1 - 8 bits when IC_FIRST_DATA_BYTE_STATUS = 0 Note: In order for the DW_apb_i2c to continue acknowledging reads, a read command should be written for every byte that is to be received; otherwise the DW_apb_i2c will stop acknowledging. You can [`read`](crate::generic::Reg::read) this register and get [`ic_data_cmd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_data_cmd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@ic_data_cmd`] module"] pub type IC_DATA_CMD = crate::Reg; -#[doc = "I2C Rx/Tx Data Buffer and Command Register; this is the register the CPU writes to when filling the TX FIFO and the CPU reads from when retrieving bytes from RX FIFO. - - The size of the register changes as follows: - - Write: - 11 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=1 - 9 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=0 Read: - 12 bits when IC_FIRST_DATA_BYTE_STATUS = 1 - 8 bits when IC_FIRST_DATA_BYTE_STATUS = 0 Note: In order for the DW_apb_i2c to continue acknowledging reads, a read command should be written for every byte that is to be received; otherwise the DW_apb_i2c will stop acknowledging."] +#[doc = "I2C Rx/Tx Data Buffer and Command Register; this is the register the CPU writes to when filling the TX FIFO and the CPU reads from when retrieving bytes from RX FIFO. The size of the register changes as follows: Write: - 11 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=1 - 9 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=0 Read: - 12 bits when IC_FIRST_DATA_BYTE_STATUS = 1 - 8 bits when IC_FIRST_DATA_BYTE_STATUS = 0 Note: In order for the DW_apb_i2c to continue acknowledging reads, a read command should be written for every byte that is to be received; otherwise the DW_apb_i2c will stop acknowledging."] pub mod ic_data_cmd; #[doc = "IC_SS_SCL_HCNT (rw) register accessor: Standard Speed I2C Clock SCL High Count Register @@ -430,44 +348,32 @@ module"] pub type IC_FS_SCL_LCNT = crate::Reg; #[doc = "Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register"] pub mod ic_fs_scl_lcnt; -#[doc = "IC_INTR_STAT (r) register accessor: I2C Interrupt Status Register - - Each bit in this register has a corresponding mask bit in the IC_INTR_MASK register. These bits are cleared by reading the matching interrupt clear register. The unmasked raw versions of these bits are available in the IC_RAW_INTR_STAT register. +#[doc = "IC_INTR_STAT (rw) register accessor: I2C Interrupt Status Register Each bit in this register has a corresponding mask bit in the IC_INTR_MASK register. These bits are cleared by reading the matching interrupt clear register. The unmasked raw versions of these bits are available in the IC_RAW_INTR_STAT register. -You can [`read`](crate::generic::Reg::read) this register and get [`ic_intr_stat::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`ic_intr_stat::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_intr_stat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@ic_intr_stat`] module"] pub type IC_INTR_STAT = crate::Reg; -#[doc = "I2C Interrupt Status Register - - Each bit in this register has a corresponding mask bit in the IC_INTR_MASK register. These bits are cleared by reading the matching interrupt clear register. The unmasked raw versions of these bits are available in the IC_RAW_INTR_STAT register."] +#[doc = "I2C Interrupt Status Register Each bit in this register has a corresponding mask bit in the IC_INTR_MASK register. These bits are cleared by reading the matching interrupt clear register. The unmasked raw versions of these bits are available in the IC_RAW_INTR_STAT register."] pub mod ic_intr_stat; -#[doc = "IC_INTR_MASK (rw) register accessor: I2C Interrupt Mask Register. - - These bits mask their corresponding interrupt status bits. This register is active low; a value of 0 masks the interrupt, whereas a value of 1 unmasks the interrupt. +#[doc = "IC_INTR_MASK (rw) register accessor: I2C Interrupt Mask Register. These bits mask their corresponding interrupt status bits. This register is active low; a value of 0 masks the interrupt, whereas a value of 1 unmasks the interrupt. You can [`read`](crate::generic::Reg::read) this register and get [`ic_intr_mask::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_intr_mask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@ic_intr_mask`] module"] pub type IC_INTR_MASK = crate::Reg; -#[doc = "I2C Interrupt Mask Register. - - These bits mask their corresponding interrupt status bits. This register is active low; a value of 0 masks the interrupt, whereas a value of 1 unmasks the interrupt."] +#[doc = "I2C Interrupt Mask Register. These bits mask their corresponding interrupt status bits. This register is active low; a value of 0 masks the interrupt, whereas a value of 1 unmasks the interrupt."] pub mod ic_intr_mask; -#[doc = "IC_RAW_INTR_STAT (r) register accessor: I2C Raw Interrupt Status Register +#[doc = "IC_RAW_INTR_STAT (rw) register accessor: I2C Raw Interrupt Status Register Unlike the IC_INTR_STAT register, these bits are not masked so they always show the true status of the DW_apb_i2c. - Unlike the IC_INTR_STAT register, these bits are not masked so they always show the true status of the DW_apb_i2c. - -You can [`read`](crate::generic::Reg::read) this register and get [`ic_raw_intr_stat::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`ic_raw_intr_stat::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_raw_intr_stat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@ic_raw_intr_stat`] module"] pub type IC_RAW_INTR_STAT = crate::Reg; -#[doc = "I2C Raw Interrupt Status Register - - Unlike the IC_INTR_STAT register, these bits are not masked so they always show the true status of the DW_apb_i2c."] +#[doc = "I2C Raw Interrupt Status Register Unlike the IC_INTR_STAT register, these bits are not masked so they always show the true status of the DW_apb_i2c."] pub mod ic_raw_intr_stat; #[doc = "IC_RX_TL (rw) register accessor: I2C Receive FIFO Threshold Register @@ -487,99 +393,99 @@ module"] pub type IC_TX_TL = crate::Reg; #[doc = "I2C Transmit FIFO Threshold Register"] pub mod ic_tx_tl; -#[doc = "IC_CLR_INTR (r) register accessor: Clear Combined and Individual Interrupt Register +#[doc = "IC_CLR_INTR (rw) register accessor: Clear Combined and Individual Interrupt Register -You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_intr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_intr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_clr_intr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@ic_clr_intr`] module"] pub type IC_CLR_INTR = crate::Reg; #[doc = "Clear Combined and Individual Interrupt Register"] pub mod ic_clr_intr; -#[doc = "IC_CLR_RX_UNDER (r) register accessor: Clear RX_UNDER Interrupt Register +#[doc = "IC_CLR_RX_UNDER (rw) register accessor: Clear RX_UNDER Interrupt Register -You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_rx_under::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_rx_under::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_clr_rx_under::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@ic_clr_rx_under`] module"] pub type IC_CLR_RX_UNDER = crate::Reg; #[doc = "Clear RX_UNDER Interrupt Register"] pub mod ic_clr_rx_under; -#[doc = "IC_CLR_RX_OVER (r) register accessor: Clear RX_OVER Interrupt Register +#[doc = "IC_CLR_RX_OVER (rw) register accessor: Clear RX_OVER Interrupt Register -You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_rx_over::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_rx_over::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_clr_rx_over::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@ic_clr_rx_over`] module"] pub type IC_CLR_RX_OVER = crate::Reg; #[doc = "Clear RX_OVER Interrupt Register"] pub mod ic_clr_rx_over; -#[doc = "IC_CLR_TX_OVER (r) register accessor: Clear TX_OVER Interrupt Register +#[doc = "IC_CLR_TX_OVER (rw) register accessor: Clear TX_OVER Interrupt Register -You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_tx_over::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_tx_over::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_clr_tx_over::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@ic_clr_tx_over`] module"] pub type IC_CLR_TX_OVER = crate::Reg; #[doc = "Clear TX_OVER Interrupt Register"] pub mod ic_clr_tx_over; -#[doc = "IC_CLR_RD_REQ (r) register accessor: Clear RD_REQ Interrupt Register +#[doc = "IC_CLR_RD_REQ (rw) register accessor: Clear RD_REQ Interrupt Register -You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_rd_req::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_rd_req::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_clr_rd_req::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@ic_clr_rd_req`] module"] pub type IC_CLR_RD_REQ = crate::Reg; #[doc = "Clear RD_REQ Interrupt Register"] pub mod ic_clr_rd_req; -#[doc = "IC_CLR_TX_ABRT (r) register accessor: Clear TX_ABRT Interrupt Register +#[doc = "IC_CLR_TX_ABRT (rw) register accessor: Clear TX_ABRT Interrupt Register -You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_tx_abrt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_tx_abrt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_clr_tx_abrt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@ic_clr_tx_abrt`] module"] pub type IC_CLR_TX_ABRT = crate::Reg; #[doc = "Clear TX_ABRT Interrupt Register"] pub mod ic_clr_tx_abrt; -#[doc = "IC_CLR_RX_DONE (r) register accessor: Clear RX_DONE Interrupt Register +#[doc = "IC_CLR_RX_DONE (rw) register accessor: Clear RX_DONE Interrupt Register -You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_rx_done::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_rx_done::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_clr_rx_done::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@ic_clr_rx_done`] module"] pub type IC_CLR_RX_DONE = crate::Reg; #[doc = "Clear RX_DONE Interrupt Register"] pub mod ic_clr_rx_done; -#[doc = "IC_CLR_ACTIVITY (r) register accessor: Clear ACTIVITY Interrupt Register +#[doc = "IC_CLR_ACTIVITY (rw) register accessor: Clear ACTIVITY Interrupt Register -You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_activity::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_activity::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_clr_activity::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@ic_clr_activity`] module"] pub type IC_CLR_ACTIVITY = crate::Reg; #[doc = "Clear ACTIVITY Interrupt Register"] pub mod ic_clr_activity; -#[doc = "IC_CLR_STOP_DET (r) register accessor: Clear STOP_DET Interrupt Register +#[doc = "IC_CLR_STOP_DET (rw) register accessor: Clear STOP_DET Interrupt Register -You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_stop_det::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_stop_det::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_clr_stop_det::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@ic_clr_stop_det`] module"] pub type IC_CLR_STOP_DET = crate::Reg; #[doc = "Clear STOP_DET Interrupt Register"] pub mod ic_clr_stop_det; -#[doc = "IC_CLR_START_DET (r) register accessor: Clear START_DET Interrupt Register +#[doc = "IC_CLR_START_DET (rw) register accessor: Clear START_DET Interrupt Register -You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_start_det::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_start_det::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_clr_start_det::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@ic_clr_start_det`] module"] pub type IC_CLR_START_DET = crate::Reg; #[doc = "Clear START_DET Interrupt Register"] pub mod ic_clr_start_det; -#[doc = "IC_CLR_GEN_CALL (r) register accessor: Clear GEN_CALL Interrupt Register +#[doc = "IC_CLR_GEN_CALL (rw) register accessor: Clear GEN_CALL Interrupt Register -You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_gen_call::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_gen_call::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_clr_gen_call::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@ic_clr_gen_call`] module"] @@ -595,96 +501,56 @@ module"] pub type IC_ENABLE = crate::Reg; #[doc = "I2C Enable Register"] pub mod ic_enable; -#[doc = "IC_STATUS (r) register accessor: I2C Status Register +#[doc = "IC_STATUS (rw) register accessor: I2C Status Register This is a read-only register used to indicate the current transfer status and FIFO status. The status register may be read at any time. None of the bits in this register request an interrupt. When the I2C is disabled by writing 0 in bit 0 of the IC_ENABLE register: - Bits 1 and 2 are set to 1 - Bits 3 and 10 are set to 0 When the master or slave state machines goes to idle and ic_en=0: - Bits 5 and 6 are set to 0 - This is a read-only register used to indicate the current transfer status and FIFO status. The status register may be read at any time. None of the bits in this register request an interrupt. - - When the I2C is disabled by writing 0 in bit 0 of the IC_ENABLE register: - Bits 1 and 2 are set to 1 - Bits 3 and 10 are set to 0 When the master or slave state machines goes to idle and ic_en=0: - Bits 5 and 6 are set to 0 - -You can [`read`](crate::generic::Reg::read) this register and get [`ic_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`ic_status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@ic_status`] module"] pub type IC_STATUS = crate::Reg; -#[doc = "I2C Status Register - - This is a read-only register used to indicate the current transfer status and FIFO status. The status register may be read at any time. None of the bits in this register request an interrupt. - - When the I2C is disabled by writing 0 in bit 0 of the IC_ENABLE register: - Bits 1 and 2 are set to 1 - Bits 3 and 10 are set to 0 When the master or slave state machines goes to idle and ic_en=0: - Bits 5 and 6 are set to 0"] +#[doc = "I2C Status Register This is a read-only register used to indicate the current transfer status and FIFO status. The status register may be read at any time. None of the bits in this register request an interrupt. When the I2C is disabled by writing 0 in bit 0 of the IC_ENABLE register: - Bits 1 and 2 are set to 1 - Bits 3 and 10 are set to 0 When the master or slave state machines goes to idle and ic_en=0: - Bits 5 and 6 are set to 0"] pub mod ic_status; -#[doc = "IC_TXFLR (r) register accessor: I2C Transmit FIFO Level Register This register contains the number of valid data entries in the transmit FIFO buffer. It is cleared whenever: - The I2C is disabled - There is a transmit abort - that is, TX_ABRT bit is set in the IC_RAW_INTR_STAT register - The slave bulk transmit mode is aborted The register increments whenever data is placed into the transmit FIFO and decrements when data is taken from the transmit FIFO. +#[doc = "IC_TXFLR (rw) register accessor: I2C Transmit FIFO Level Register This register contains the number of valid data entries in the transmit FIFO buffer. It is cleared whenever: - The I2C is disabled - There is a transmit abort - that is, TX_ABRT bit is set in the IC_RAW_INTR_STAT register - The slave bulk transmit mode is aborted The register increments whenever data is placed into the transmit FIFO and decrements when data is taken from the transmit FIFO. -You can [`read`](crate::generic::Reg::read) this register and get [`ic_txflr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`ic_txflr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_txflr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@ic_txflr`] module"] pub type IC_TXFLR = crate::Reg; #[doc = "I2C Transmit FIFO Level Register This register contains the number of valid data entries in the transmit FIFO buffer. It is cleared whenever: - The I2C is disabled - There is a transmit abort - that is, TX_ABRT bit is set in the IC_RAW_INTR_STAT register - The slave bulk transmit mode is aborted The register increments whenever data is placed into the transmit FIFO and decrements when data is taken from the transmit FIFO."] pub mod ic_txflr; -#[doc = "IC_RXFLR (r) register accessor: I2C Receive FIFO Level Register This register contains the number of valid data entries in the receive FIFO buffer. It is cleared whenever: - The I2C is disabled - Whenever there is a transmit abort caused by any of the events tracked in IC_TX_ABRT_SOURCE The register increments whenever data is placed into the receive FIFO and decrements when data is taken from the receive FIFO. +#[doc = "IC_RXFLR (rw) register accessor: I2C Receive FIFO Level Register This register contains the number of valid data entries in the receive FIFO buffer. It is cleared whenever: - The I2C is disabled - Whenever there is a transmit abort caused by any of the events tracked in IC_TX_ABRT_SOURCE The register increments whenever data is placed into the receive FIFO and decrements when data is taken from the receive FIFO. -You can [`read`](crate::generic::Reg::read) this register and get [`ic_rxflr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`ic_rxflr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_rxflr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@ic_rxflr`] module"] pub type IC_RXFLR = crate::Reg; #[doc = "I2C Receive FIFO Level Register This register contains the number of valid data entries in the receive FIFO buffer. It is cleared whenever: - The I2C is disabled - Whenever there is a transmit abort caused by any of the events tracked in IC_TX_ABRT_SOURCE The register increments whenever data is placed into the receive FIFO and decrements when data is taken from the receive FIFO."] pub mod ic_rxflr; -#[doc = "IC_SDA_HOLD (rw) register accessor: I2C SDA Hold Time Length Register - - The bits \\[15:0\\] -of this register are used to control the hold time of SDA during transmit in both slave and master mode (after SCL goes from HIGH to LOW). - - The bits \\[23:16\\] -of this register are used to extend the SDA transition (if any) whenever SCL is HIGH in the receiver in either master or slave mode. - - Writes to this register succeed only when IC_ENABLE\\[0\\]=0. - - The values in this register are in units of ic_clk period. The value programmed in IC_SDA_TX_HOLD must be greater than the minimum hold time in each mode (one cycle in master mode, seven cycles in slave mode) for the value to be implemented. - - The programmed SDA hold time during transmit (IC_SDA_TX_HOLD) cannot exceed at any time the duration of the low part of scl. Therefore the programmed value cannot be larger than N_SCL_LOW-2, where N_SCL_LOW is the duration of the low part of the scl period measured in ic_clk cycles. +#[doc = "IC_SDA_HOLD (rw) register accessor: I2C SDA Hold Time Length Register The bits \\[15:0\\] +of this register are used to control the hold time of SDA during transmit in both slave and master mode (after SCL goes from HIGH to LOW). The bits \\[23:16\\] +of this register are used to extend the SDA transition (if any) whenever SCL is HIGH in the receiver in either master or slave mode. Writes to this register succeed only when IC_ENABLE\\[0\\]=0. The values in this register are in units of ic_clk period. The value programmed in IC_SDA_TX_HOLD must be greater than the minimum hold time in each mode (one cycle in master mode, seven cycles in slave mode) for the value to be implemented. The programmed SDA hold time during transmit (IC_SDA_TX_HOLD) cannot exceed at any time the duration of the low part of scl. Therefore the programmed value cannot be larger than N_SCL_LOW-2, where N_SCL_LOW is the duration of the low part of the scl period measured in ic_clk cycles. You can [`read`](crate::generic::Reg::read) this register and get [`ic_sda_hold::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_sda_hold::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@ic_sda_hold`] module"] pub type IC_SDA_HOLD = crate::Reg; -#[doc = "I2C SDA Hold Time Length Register - - The bits \\[15:0\\] -of this register are used to control the hold time of SDA during transmit in both slave and master mode (after SCL goes from HIGH to LOW). - - The bits \\[23:16\\] -of this register are used to extend the SDA transition (if any) whenever SCL is HIGH in the receiver in either master or slave mode. - - Writes to this register succeed only when IC_ENABLE\\[0\\]=0. - - The values in this register are in units of ic_clk period. The value programmed in IC_SDA_TX_HOLD must be greater than the minimum hold time in each mode (one cycle in master mode, seven cycles in slave mode) for the value to be implemented. - - The programmed SDA hold time during transmit (IC_SDA_TX_HOLD) cannot exceed at any time the duration of the low part of scl. Therefore the programmed value cannot be larger than N_SCL_LOW-2, where N_SCL_LOW is the duration of the low part of the scl period measured in ic_clk cycles."] +#[doc = "I2C SDA Hold Time Length Register The bits \\[15:0\\] +of this register are used to control the hold time of SDA during transmit in both slave and master mode (after SCL goes from HIGH to LOW). The bits \\[23:16\\] +of this register are used to extend the SDA transition (if any) whenever SCL is HIGH in the receiver in either master or slave mode. Writes to this register succeed only when IC_ENABLE\\[0\\]=0. The values in this register are in units of ic_clk period. The value programmed in IC_SDA_TX_HOLD must be greater than the minimum hold time in each mode (one cycle in master mode, seven cycles in slave mode) for the value to be implemented. The programmed SDA hold time during transmit (IC_SDA_TX_HOLD) cannot exceed at any time the duration of the low part of scl. Therefore the programmed value cannot be larger than N_SCL_LOW-2, where N_SCL_LOW is the duration of the low part of the scl period measured in ic_clk cycles."] pub mod ic_sda_hold; -#[doc = "IC_TX_ABRT_SOURCE (r) register accessor: I2C Transmit Abort Source Register - - This register has 32 bits that indicate the source of the TX_ABRT bit. Except for Bit 9, this register is cleared whenever the IC_CLR_TX_ABRT register or the IC_CLR_INTR register is read. To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; RESTART must be enabled (IC_CON\\[5\\]=1), the SPECIAL bit must be cleared (IC_TAR\\[11\\]), or the GC_OR_START bit must be cleared (IC_TAR\\[10\\]). +#[doc = "IC_TX_ABRT_SOURCE (rw) register accessor: I2C Transmit Abort Source Register This register has 32 bits that indicate the source of the TX_ABRT bit. Except for Bit 9, this register is cleared whenever the IC_CLR_TX_ABRT register or the IC_CLR_INTR register is read. To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; RESTART must be enabled (IC_CON\\[5\\]=1), the SPECIAL bit must be cleared (IC_TAR\\[11\\]), or the GC_OR_START bit must be cleared (IC_TAR\\[10\\]). Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, Bit 9 clears for one cycle and is then re-asserted. - Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, Bit 9 clears for one cycle and is then re-asserted. - -You can [`read`](crate::generic::Reg::read) this register and get [`ic_tx_abrt_source::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`ic_tx_abrt_source::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_tx_abrt_source::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@ic_tx_abrt_source`] module"] pub type IC_TX_ABRT_SOURCE = crate::Reg; -#[doc = "I2C Transmit Abort Source Register - - This register has 32 bits that indicate the source of the TX_ABRT bit. Except for Bit 9, this register is cleared whenever the IC_CLR_TX_ABRT register or the IC_CLR_INTR register is read. To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; RESTART must be enabled (IC_CON\\[5\\]=1), the SPECIAL bit must be cleared (IC_TAR\\[11\\]), or the GC_OR_START bit must be cleared (IC_TAR\\[10\\]). - - Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, Bit 9 clears for one cycle and is then re-asserted."] +#[doc = "I2C Transmit Abort Source Register This register has 32 bits that indicate the source of the TX_ABRT bit. Except for Bit 9, this register is cleared whenever the IC_CLR_TX_ABRT register or the IC_CLR_INTR register is read. To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; RESTART must be enabled (IC_CON\\[5\\]=1), the SPECIAL bit must be cleared (IC_TAR\\[11\\]), or the GC_OR_START bit must be cleared (IC_TAR\\[10\\]). Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, Bit 9 clears for one cycle and is then re-asserted."] pub mod ic_tx_abrt_source; -#[doc = "IC_SLV_DATA_NACK_ONLY (rw) register accessor: Generate Slave Data NACK Register - - The register is used to generate a NACK for the data part of a transfer when DW_apb_i2c is acting as a slave-receiver. This register only exists when the IC_SLV_DATA_NACK_ONLY parameter is set to 1. When this parameter disabled, this register does not exist and writing to the register's address has no effect. - - A write can occur on this register if both of the following conditions are met: - DW_apb_i2c is disabled (IC_ENABLE\\[0\\] +#[doc = "IC_SLV_DATA_NACK_ONLY (rw) register accessor: Generate Slave Data NACK Register The register is used to generate a NACK for the data part of a transfer when DW_apb_i2c is acting as a slave-receiver. This register only exists when the IC_SLV_DATA_NACK_ONLY parameter is set to 1. When this parameter disabled, this register does not exist and writing to the register's address has no effect. A write can occur on this register if both of the following conditions are met: - DW_apb_i2c is disabled (IC_ENABLE\\[0\\] = 0) - Slave part is inactive (IC_STATUS\\[6\\] = 0) Note: The IC_STATUS\\[6\\] is a register read-back location for the internal slv_activity signal; the user should poll this before writing the ic_slv_data_nack_only bit. @@ -694,27 +560,19 @@ You can [`read`](crate::generic::Reg::read) this register and get [`ic_slv_data_ For information about available fields see [`mod@ic_slv_data_nack_only`] module"] pub type IC_SLV_DATA_NACK_ONLY = crate::Reg; -#[doc = "Generate Slave Data NACK Register - - The register is used to generate a NACK for the data part of a transfer when DW_apb_i2c is acting as a slave-receiver. This register only exists when the IC_SLV_DATA_NACK_ONLY parameter is set to 1. When this parameter disabled, this register does not exist and writing to the register's address has no effect. - - A write can occur on this register if both of the following conditions are met: - DW_apb_i2c is disabled (IC_ENABLE\\[0\\] +#[doc = "Generate Slave Data NACK Register The register is used to generate a NACK for the data part of a transfer when DW_apb_i2c is acting as a slave-receiver. This register only exists when the IC_SLV_DATA_NACK_ONLY parameter is set to 1. When this parameter disabled, this register does not exist and writing to the register's address has no effect. A write can occur on this register if both of the following conditions are met: - DW_apb_i2c is disabled (IC_ENABLE\\[0\\] = 0) - Slave part is inactive (IC_STATUS\\[6\\] = 0) Note: The IC_STATUS\\[6\\] is a register read-back location for the internal slv_activity signal; the user should poll this before writing the ic_slv_data_nack_only bit."] pub mod ic_slv_data_nack_only; -#[doc = "IC_DMA_CR (rw) register accessor: DMA Control Register - - The register is used to enable the DMA Controller interface operation. There is a separate bit for transmit and receive. This can be programmed regardless of the state of IC_ENABLE. +#[doc = "IC_DMA_CR (rw) register accessor: DMA Control Register The register is used to enable the DMA Controller interface operation. There is a separate bit for transmit and receive. This can be programmed regardless of the state of IC_ENABLE. You can [`read`](crate::generic::Reg::read) this register and get [`ic_dma_cr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_dma_cr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@ic_dma_cr`] module"] pub type IC_DMA_CR = crate::Reg; -#[doc = "DMA Control Register - - The register is used to enable the DMA Controller interface operation. There is a separate bit for transmit and receive. This can be programmed regardless of the state of IC_ENABLE."] +#[doc = "DMA Control Register The register is used to enable the DMA Controller interface operation. There is a separate bit for transmit and receive. This can be programmed regardless of the state of IC_ENABLE."] pub mod ic_dma_cr; #[doc = "IC_DMA_TDLR (rw) register accessor: DMA Transmit Data Level Register @@ -734,126 +592,82 @@ module"] pub type IC_DMA_RDLR = crate::Reg; #[doc = "I2C Receive Data Level Register"] pub mod ic_dma_rdlr; -#[doc = "IC_SDA_SETUP (rw) register accessor: I2C SDA Setup Register - - This register controls the amount of time delay (in terms of number of ic_clk clock periods) introduced in the rising edge of SCL - relative to SDA changing - when DW_apb_i2c services a read request in a slave-transmitter operation. The relevant I2C requirement is tSU:DAT (note 4) as detailed in the I2C Bus Specification. This register must be programmed with a value equal to or greater than 2. - - Writes to this register succeed only when IC_ENABLE\\[0\\] -= 0. - - Note: The length of setup time is calculated using \\[(IC_SDA_SETUP - 1) * (ic_clk_period)\\], so if the user requires 10 ic_clk periods of setup time, they should program a value of 11. The IC_SDA_SETUP register is only used by the DW_apb_i2c when operating as a slave transmitter. +#[doc = "IC_SDA_SETUP (rw) register accessor: I2C SDA Setup Register This register controls the amount of time delay (in terms of number of ic_clk clock periods) introduced in the rising edge of SCL - relative to SDA changing - when DW_apb_i2c services a read request in a slave-transmitter operation. The relevant I2C requirement is tSU:DAT (note 4) as detailed in the I2C Bus Specification. This register must be programmed with a value equal to or greater than 2. Writes to this register succeed only when IC_ENABLE\\[0\\] += 0. Note: The length of setup time is calculated using \\[(IC_SDA_SETUP - 1) * (ic_clk_period)\\], so if the user requires 10 ic_clk periods of setup time, they should program a value of 11. The IC_SDA_SETUP register is only used by the DW_apb_i2c when operating as a slave transmitter. You can [`read`](crate::generic::Reg::read) this register and get [`ic_sda_setup::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_sda_setup::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@ic_sda_setup`] module"] pub type IC_SDA_SETUP = crate::Reg; -#[doc = "I2C SDA Setup Register - - This register controls the amount of time delay (in terms of number of ic_clk clock periods) introduced in the rising edge of SCL - relative to SDA changing - when DW_apb_i2c services a read request in a slave-transmitter operation. The relevant I2C requirement is tSU:DAT (note 4) as detailed in the I2C Bus Specification. This register must be programmed with a value equal to or greater than 2. - - Writes to this register succeed only when IC_ENABLE\\[0\\] -= 0. - - Note: The length of setup time is calculated using \\[(IC_SDA_SETUP - 1) * (ic_clk_period)\\], so if the user requires 10 ic_clk periods of setup time, they should program a value of 11. The IC_SDA_SETUP register is only used by the DW_apb_i2c when operating as a slave transmitter."] +#[doc = "I2C SDA Setup Register This register controls the amount of time delay (in terms of number of ic_clk clock periods) introduced in the rising edge of SCL - relative to SDA changing - when DW_apb_i2c services a read request in a slave-transmitter operation. The relevant I2C requirement is tSU:DAT (note 4) as detailed in the I2C Bus Specification. This register must be programmed with a value equal to or greater than 2. Writes to this register succeed only when IC_ENABLE\\[0\\] += 0. Note: The length of setup time is calculated using \\[(IC_SDA_SETUP - 1) * (ic_clk_period)\\], so if the user requires 10 ic_clk periods of setup time, they should program a value of 11. The IC_SDA_SETUP register is only used by the DW_apb_i2c when operating as a slave transmitter."] pub mod ic_sda_setup; -#[doc = "IC_ACK_GENERAL_CALL (rw) register accessor: I2C ACK General Call Register - - The register controls whether DW_apb_i2c responds with a ACK or NACK when it receives an I2C General Call address. - - This register is applicable only when the DW_apb_i2c is in slave mode. +#[doc = "IC_ACK_GENERAL_CALL (rw) register accessor: I2C ACK General Call Register The register controls whether DW_apb_i2c responds with a ACK or NACK when it receives an I2C General Call address. This register is applicable only when the DW_apb_i2c is in slave mode. You can [`read`](crate::generic::Reg::read) this register and get [`ic_ack_general_call::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_ack_general_call::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@ic_ack_general_call`] module"] pub type IC_ACK_GENERAL_CALL = crate::Reg; -#[doc = "I2C ACK General Call Register - - The register controls whether DW_apb_i2c responds with a ACK or NACK when it receives an I2C General Call address. - - This register is applicable only when the DW_apb_i2c is in slave mode."] +#[doc = "I2C ACK General Call Register The register controls whether DW_apb_i2c responds with a ACK or NACK when it receives an I2C General Call address. This register is applicable only when the DW_apb_i2c is in slave mode."] pub mod ic_ack_general_call; -#[doc = "IC_ENABLE_STATUS (r) register accessor: I2C Enable Status Register - - The register is used to report the DW_apb_i2c hardware status when the IC_ENABLE\\[0\\] -register is set from 1 to 0; that is, when DW_apb_i2c is disabled. - - If IC_ENABLE\\[0\\] -has been set to 1, bits 2:1 are forced to 0, and bit 0 is forced to 1. - - If IC_ENABLE\\[0\\] -has been set to 0, bits 2:1 is only be valid as soon as bit 0 is read as '0'. - - Note: When IC_ENABLE\\[0\\] +#[doc = "IC_ENABLE_STATUS (rw) register accessor: I2C Enable Status Register The register is used to report the DW_apb_i2c hardware status when the IC_ENABLE\\[0\\] +register is set from 1 to 0; that is, when DW_apb_i2c is disabled. If IC_ENABLE\\[0\\] +has been set to 1, bits 2:1 are forced to 0, and bit 0 is forced to 1. If IC_ENABLE\\[0\\] +has been set to 0, bits 2:1 is only be valid as soon as bit 0 is read as '0'. Note: When IC_ENABLE\\[0\\] has been set to 0, a delay occurs for bit 0 to be read as 0 because disabling the DW_apb_i2c depends on I2C bus activities. -You can [`read`](crate::generic::Reg::read) this register and get [`ic_enable_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`ic_enable_status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_enable_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@ic_enable_status`] module"] pub type IC_ENABLE_STATUS = crate::Reg; -#[doc = "I2C Enable Status Register - - The register is used to report the DW_apb_i2c hardware status when the IC_ENABLE\\[0\\] -register is set from 1 to 0; that is, when DW_apb_i2c is disabled. - - If IC_ENABLE\\[0\\] -has been set to 1, bits 2:1 are forced to 0, and bit 0 is forced to 1. - - If IC_ENABLE\\[0\\] -has been set to 0, bits 2:1 is only be valid as soon as bit 0 is read as '0'. - - Note: When IC_ENABLE\\[0\\] +#[doc = "I2C Enable Status Register The register is used to report the DW_apb_i2c hardware status when the IC_ENABLE\\[0\\] +register is set from 1 to 0; that is, when DW_apb_i2c is disabled. If IC_ENABLE\\[0\\] +has been set to 1, bits 2:1 are forced to 0, and bit 0 is forced to 1. If IC_ENABLE\\[0\\] +has been set to 0, bits 2:1 is only be valid as soon as bit 0 is read as '0'. Note: When IC_ENABLE\\[0\\] has been set to 0, a delay occurs for bit 0 to be read as 0 because disabling the DW_apb_i2c depends on I2C bus activities."] pub mod ic_enable_status; -#[doc = "IC_FS_SPKLEN (rw) register accessor: I2C SS, FS or FM+ spike suppression limit - - This register is used to store the duration, measured in ic_clk cycles, of the longest spike that is filtered out by the spike suppression logic when the component is operating in SS, FS or FM+ modes. The relevant I2C requirement is tSP (table 4) as detailed in the I2C Bus Specification. This register must be programmed with a minimum value of 1. +#[doc = "IC_FS_SPKLEN (rw) register accessor: I2C SS, FS or FM+ spike suppression limit This register is used to store the duration, measured in ic_clk cycles, of the longest spike that is filtered out by the spike suppression logic when the component is operating in SS, FS or FM+ modes. The relevant I2C requirement is tSP (table 4) as detailed in the I2C Bus Specification. This register must be programmed with a minimum value of 1. You can [`read`](crate::generic::Reg::read) this register and get [`ic_fs_spklen::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_fs_spklen::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@ic_fs_spklen`] module"] pub type IC_FS_SPKLEN = crate::Reg; -#[doc = "I2C SS, FS or FM+ spike suppression limit - - This register is used to store the duration, measured in ic_clk cycles, of the longest spike that is filtered out by the spike suppression logic when the component is operating in SS, FS or FM+ modes. The relevant I2C requirement is tSP (table 4) as detailed in the I2C Bus Specification. This register must be programmed with a minimum value of 1."] +#[doc = "I2C SS, FS or FM+ spike suppression limit This register is used to store the duration, measured in ic_clk cycles, of the longest spike that is filtered out by the spike suppression logic when the component is operating in SS, FS or FM+ modes. The relevant I2C requirement is tSP (table 4) as detailed in the I2C Bus Specification. This register must be programmed with a minimum value of 1."] pub mod ic_fs_spklen; -#[doc = "IC_CLR_RESTART_DET (r) register accessor: Clear RESTART_DET Interrupt Register +#[doc = "IC_CLR_RESTART_DET (rw) register accessor: Clear RESTART_DET Interrupt Register -You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_restart_det::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_restart_det::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_clr_restart_det::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@ic_clr_restart_det`] module"] pub type IC_CLR_RESTART_DET = crate::Reg; #[doc = "Clear RESTART_DET Interrupt Register"] pub mod ic_clr_restart_det; -#[doc = "IC_COMP_PARAM_1 (r) register accessor: Component Parameter Register 1 +#[doc = "IC_COMP_PARAM_1 (rw) register accessor: Component Parameter Register 1 Note This register is not implemented and therefore reads as 0. If it was implemented it would be a constant read-only register that contains encoded information about the component's parameter settings. Fields shown below are the settings for those parameters - Note This register is not implemented and therefore reads as 0. If it was implemented it would be a constant read-only register that contains encoded information about the component's parameter settings. Fields shown below are the settings for those parameters - -You can [`read`](crate::generic::Reg::read) this register and get [`ic_comp_param_1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`ic_comp_param_1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_comp_param_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@ic_comp_param_1`] module"] pub type IC_COMP_PARAM_1 = crate::Reg; -#[doc = "Component Parameter Register 1 - - Note This register is not implemented and therefore reads as 0. If it was implemented it would be a constant read-only register that contains encoded information about the component's parameter settings. Fields shown below are the settings for those parameters"] +#[doc = "Component Parameter Register 1 Note This register is not implemented and therefore reads as 0. If it was implemented it would be a constant read-only register that contains encoded information about the component's parameter settings. Fields shown below are the settings for those parameters"] pub mod ic_comp_param_1; -#[doc = "IC_COMP_VERSION (r) register accessor: I2C Component Version Register +#[doc = "IC_COMP_VERSION (rw) register accessor: I2C Component Version Register -You can [`read`](crate::generic::Reg::read) this register and get [`ic_comp_version::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`ic_comp_version::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_comp_version::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@ic_comp_version`] module"] pub type IC_COMP_VERSION = crate::Reg; #[doc = "I2C Component Version Register"] pub mod ic_comp_version; -#[doc = "IC_COMP_TYPE (r) register accessor: I2C Component Type Register +#[doc = "IC_COMP_TYPE (rw) register accessor: I2C Component Type Register -You can [`read`](crate::generic::Reg::read) this register and get [`ic_comp_type::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`ic_comp_type::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_comp_type::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@ic_comp_type`] module"] diff --git a/src/i2c0/ic_ack_general_call.rs b/src/i2c0/ic_ack_general_call.rs index d012db2fe..608dd984e 100644 --- a/src/i2c0/ic_ack_general_call.rs +++ b/src/i2c0/ic_ack_general_call.rs @@ -72,11 +72,7 @@ impl W { ACK_GEN_CALL_W::new(self, 0) } } -#[doc = "I2C ACK General Call Register - - The register controls whether DW_apb_i2c responds with a ACK or NACK when it receives an I2C General Call address. - - This register is applicable only when the DW_apb_i2c is in slave mode. +#[doc = "I2C ACK General Call Register The register controls whether DW_apb_i2c responds with a ACK or NACK when it receives an I2C General Call address. This register is applicable only when the DW_apb_i2c is in slave mode. You can [`read`](crate::generic::Reg::read) this register and get [`ic_ack_general_call::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_ack_general_call::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IC_ACK_GENERAL_CALL_SPEC; diff --git a/src/i2c0/ic_clr_activity.rs b/src/i2c0/ic_clr_activity.rs index aa363a7e3..243b26501 100644 --- a/src/i2c0/ic_clr_activity.rs +++ b/src/i2c0/ic_clr_activity.rs @@ -1,27 +1,32 @@ #[doc = "Register `IC_CLR_ACTIVITY` reader"] pub type R = crate::R; -#[doc = "Field `CLR_ACTIVITY` reader - Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore. If the I2C module is still active on the bus, the ACTIVITY interrupt bit continues to be set. It is automatically cleared by hardware if the module is disabled and if there is no further activity on the bus. The value read from this register to get status of the ACTIVITY interrupt (bit 8) of the IC_RAW_INTR_STAT register. - - Reset value: 0x0"] +#[doc = "Register `IC_CLR_ACTIVITY` writer"] +pub type W = crate::W; +#[doc = "Field `CLR_ACTIVITY` reader - Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore. If the I2C module is still active on the bus, the ACTIVITY interrupt bit continues to be set. It is automatically cleared by hardware if the module is disabled and if there is no further activity on the bus. The value read from this register to get status of the ACTIVITY interrupt (bit 8) of the IC_RAW_INTR_STAT register. Reset value: 0x0"] pub type CLR_ACTIVITY_R = crate::BitReader; impl R { - #[doc = "Bit 0 - Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore. If the I2C module is still active on the bus, the ACTIVITY interrupt bit continues to be set. It is automatically cleared by hardware if the module is disabled and if there is no further activity on the bus. The value read from this register to get status of the ACTIVITY interrupt (bit 8) of the IC_RAW_INTR_STAT register. - - Reset value: 0x0"] + #[doc = "Bit 0 - Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore. If the I2C module is still active on the bus, the ACTIVITY interrupt bit continues to be set. It is automatically cleared by hardware if the module is disabled and if there is no further activity on the bus. The value read from this register to get status of the ACTIVITY interrupt (bit 8) of the IC_RAW_INTR_STAT register. Reset value: 0x0"] #[inline(always)] pub fn clr_activity(&self) -> CLR_ACTIVITY_R { CLR_ACTIVITY_R::new((self.bits & 1) != 0) } } +impl W {} #[doc = "Clear ACTIVITY Interrupt Register -You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_activity::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_activity::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_clr_activity::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IC_CLR_ACTIVITY_SPEC; impl crate::RegisterSpec for IC_CLR_ACTIVITY_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`ic_clr_activity::R`](R) reader structure"] impl crate::Readable for IC_CLR_ACTIVITY_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ic_clr_activity::W`](W) writer structure"] +impl crate::Writable for IC_CLR_ACTIVITY_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets IC_CLR_ACTIVITY to value 0"] impl crate::Resettable for IC_CLR_ACTIVITY_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/i2c0/ic_clr_gen_call.rs b/src/i2c0/ic_clr_gen_call.rs index fffd7c810..6edd25a71 100644 --- a/src/i2c0/ic_clr_gen_call.rs +++ b/src/i2c0/ic_clr_gen_call.rs @@ -1,27 +1,32 @@ #[doc = "Register `IC_CLR_GEN_CALL` reader"] pub type R = crate::R; -#[doc = "Field `CLR_GEN_CALL` reader - Read this register to clear the GEN_CALL interrupt (bit 11) of IC_RAW_INTR_STAT register. - - Reset value: 0x0"] +#[doc = "Register `IC_CLR_GEN_CALL` writer"] +pub type W = crate::W; +#[doc = "Field `CLR_GEN_CALL` reader - Read this register to clear the GEN_CALL interrupt (bit 11) of IC_RAW_INTR_STAT register. Reset value: 0x0"] pub type CLR_GEN_CALL_R = crate::BitReader; impl R { - #[doc = "Bit 0 - Read this register to clear the GEN_CALL interrupt (bit 11) of IC_RAW_INTR_STAT register. - - Reset value: 0x0"] + #[doc = "Bit 0 - Read this register to clear the GEN_CALL interrupt (bit 11) of IC_RAW_INTR_STAT register. Reset value: 0x0"] #[inline(always)] pub fn clr_gen_call(&self) -> CLR_GEN_CALL_R { CLR_GEN_CALL_R::new((self.bits & 1) != 0) } } +impl W {} #[doc = "Clear GEN_CALL Interrupt Register -You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_gen_call::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_gen_call::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_clr_gen_call::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IC_CLR_GEN_CALL_SPEC; impl crate::RegisterSpec for IC_CLR_GEN_CALL_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`ic_clr_gen_call::R`](R) reader structure"] impl crate::Readable for IC_CLR_GEN_CALL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ic_clr_gen_call::W`](W) writer structure"] +impl crate::Writable for IC_CLR_GEN_CALL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets IC_CLR_GEN_CALL to value 0"] impl crate::Resettable for IC_CLR_GEN_CALL_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/i2c0/ic_clr_intr.rs b/src/i2c0/ic_clr_intr.rs index 0f5eb9146..2b88653d7 100644 --- a/src/i2c0/ic_clr_intr.rs +++ b/src/i2c0/ic_clr_intr.rs @@ -1,27 +1,32 @@ #[doc = "Register `IC_CLR_INTR` reader"] pub type R = crate::R; -#[doc = "Field `CLR_INTR` reader - Read this register to clear the combined interrupt, all individual interrupts, and the IC_TX_ABRT_SOURCE register. This bit does not clear hardware clearable interrupts but software clearable interrupts. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE. - - Reset value: 0x0"] +#[doc = "Register `IC_CLR_INTR` writer"] +pub type W = crate::W; +#[doc = "Field `CLR_INTR` reader - Read this register to clear the combined interrupt, all individual interrupts, and the IC_TX_ABRT_SOURCE register. This bit does not clear hardware clearable interrupts but software clearable interrupts. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE. Reset value: 0x0"] pub type CLR_INTR_R = crate::BitReader; impl R { - #[doc = "Bit 0 - Read this register to clear the combined interrupt, all individual interrupts, and the IC_TX_ABRT_SOURCE register. This bit does not clear hardware clearable interrupts but software clearable interrupts. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE. - - Reset value: 0x0"] + #[doc = "Bit 0 - Read this register to clear the combined interrupt, all individual interrupts, and the IC_TX_ABRT_SOURCE register. This bit does not clear hardware clearable interrupts but software clearable interrupts. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE. Reset value: 0x0"] #[inline(always)] pub fn clr_intr(&self) -> CLR_INTR_R { CLR_INTR_R::new((self.bits & 1) != 0) } } +impl W {} #[doc = "Clear Combined and Individual Interrupt Register -You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_intr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_intr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_clr_intr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IC_CLR_INTR_SPEC; impl crate::RegisterSpec for IC_CLR_INTR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`ic_clr_intr::R`](R) reader structure"] impl crate::Readable for IC_CLR_INTR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ic_clr_intr::W`](W) writer structure"] +impl crate::Writable for IC_CLR_INTR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets IC_CLR_INTR to value 0"] impl crate::Resettable for IC_CLR_INTR_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/i2c0/ic_clr_rd_req.rs b/src/i2c0/ic_clr_rd_req.rs index 41a234ccd..d11fafb56 100644 --- a/src/i2c0/ic_clr_rd_req.rs +++ b/src/i2c0/ic_clr_rd_req.rs @@ -1,27 +1,32 @@ #[doc = "Register `IC_CLR_RD_REQ` reader"] pub type R = crate::R; -#[doc = "Field `CLR_RD_REQ` reader - Read this register to clear the RD_REQ interrupt (bit 5) of the IC_RAW_INTR_STAT register. - - Reset value: 0x0"] +#[doc = "Register `IC_CLR_RD_REQ` writer"] +pub type W = crate::W; +#[doc = "Field `CLR_RD_REQ` reader - Read this register to clear the RD_REQ interrupt (bit 5) of the IC_RAW_INTR_STAT register. Reset value: 0x0"] pub type CLR_RD_REQ_R = crate::BitReader; impl R { - #[doc = "Bit 0 - Read this register to clear the RD_REQ interrupt (bit 5) of the IC_RAW_INTR_STAT register. - - Reset value: 0x0"] + #[doc = "Bit 0 - Read this register to clear the RD_REQ interrupt (bit 5) of the IC_RAW_INTR_STAT register. Reset value: 0x0"] #[inline(always)] pub fn clr_rd_req(&self) -> CLR_RD_REQ_R { CLR_RD_REQ_R::new((self.bits & 1) != 0) } } +impl W {} #[doc = "Clear RD_REQ Interrupt Register -You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_rd_req::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_rd_req::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_clr_rd_req::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IC_CLR_RD_REQ_SPEC; impl crate::RegisterSpec for IC_CLR_RD_REQ_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`ic_clr_rd_req::R`](R) reader structure"] impl crate::Readable for IC_CLR_RD_REQ_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ic_clr_rd_req::W`](W) writer structure"] +impl crate::Writable for IC_CLR_RD_REQ_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets IC_CLR_RD_REQ to value 0"] impl crate::Resettable for IC_CLR_RD_REQ_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/i2c0/ic_clr_restart_det.rs b/src/i2c0/ic_clr_restart_det.rs index bc047b617..bee5a008e 100644 --- a/src/i2c0/ic_clr_restart_det.rs +++ b/src/i2c0/ic_clr_restart_det.rs @@ -1,27 +1,32 @@ #[doc = "Register `IC_CLR_RESTART_DET` reader"] pub type R = crate::R; -#[doc = "Field `CLR_RESTART_DET` reader - Read this register to clear the RESTART_DET interrupt (bit 12) of IC_RAW_INTR_STAT register. - - Reset value: 0x0"] +#[doc = "Register `IC_CLR_RESTART_DET` writer"] +pub type W = crate::W; +#[doc = "Field `CLR_RESTART_DET` reader - Read this register to clear the RESTART_DET interrupt (bit 12) of IC_RAW_INTR_STAT register. Reset value: 0x0"] pub type CLR_RESTART_DET_R = crate::BitReader; impl R { - #[doc = "Bit 0 - Read this register to clear the RESTART_DET interrupt (bit 12) of IC_RAW_INTR_STAT register. - - Reset value: 0x0"] + #[doc = "Bit 0 - Read this register to clear the RESTART_DET interrupt (bit 12) of IC_RAW_INTR_STAT register. Reset value: 0x0"] #[inline(always)] pub fn clr_restart_det(&self) -> CLR_RESTART_DET_R { CLR_RESTART_DET_R::new((self.bits & 1) != 0) } } +impl W {} #[doc = "Clear RESTART_DET Interrupt Register -You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_restart_det::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_restart_det::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_clr_restart_det::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IC_CLR_RESTART_DET_SPEC; impl crate::RegisterSpec for IC_CLR_RESTART_DET_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`ic_clr_restart_det::R`](R) reader structure"] impl crate::Readable for IC_CLR_RESTART_DET_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ic_clr_restart_det::W`](W) writer structure"] +impl crate::Writable for IC_CLR_RESTART_DET_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets IC_CLR_RESTART_DET to value 0"] impl crate::Resettable for IC_CLR_RESTART_DET_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/i2c0/ic_clr_rx_done.rs b/src/i2c0/ic_clr_rx_done.rs index c1e30fc5f..965c2c1d0 100644 --- a/src/i2c0/ic_clr_rx_done.rs +++ b/src/i2c0/ic_clr_rx_done.rs @@ -1,27 +1,32 @@ #[doc = "Register `IC_CLR_RX_DONE` reader"] pub type R = crate::R; -#[doc = "Field `CLR_RX_DONE` reader - Read this register to clear the RX_DONE interrupt (bit 7) of the IC_RAW_INTR_STAT register. - - Reset value: 0x0"] +#[doc = "Register `IC_CLR_RX_DONE` writer"] +pub type W = crate::W; +#[doc = "Field `CLR_RX_DONE` reader - Read this register to clear the RX_DONE interrupt (bit 7) of the IC_RAW_INTR_STAT register. Reset value: 0x0"] pub type CLR_RX_DONE_R = crate::BitReader; impl R { - #[doc = "Bit 0 - Read this register to clear the RX_DONE interrupt (bit 7) of the IC_RAW_INTR_STAT register. - - Reset value: 0x0"] + #[doc = "Bit 0 - Read this register to clear the RX_DONE interrupt (bit 7) of the IC_RAW_INTR_STAT register. Reset value: 0x0"] #[inline(always)] pub fn clr_rx_done(&self) -> CLR_RX_DONE_R { CLR_RX_DONE_R::new((self.bits & 1) != 0) } } +impl W {} #[doc = "Clear RX_DONE Interrupt Register -You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_rx_done::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_rx_done::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_clr_rx_done::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IC_CLR_RX_DONE_SPEC; impl crate::RegisterSpec for IC_CLR_RX_DONE_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`ic_clr_rx_done::R`](R) reader structure"] impl crate::Readable for IC_CLR_RX_DONE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ic_clr_rx_done::W`](W) writer structure"] +impl crate::Writable for IC_CLR_RX_DONE_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets IC_CLR_RX_DONE to value 0"] impl crate::Resettable for IC_CLR_RX_DONE_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/i2c0/ic_clr_rx_over.rs b/src/i2c0/ic_clr_rx_over.rs index e971de22d..5e0c2b363 100644 --- a/src/i2c0/ic_clr_rx_over.rs +++ b/src/i2c0/ic_clr_rx_over.rs @@ -1,27 +1,32 @@ #[doc = "Register `IC_CLR_RX_OVER` reader"] pub type R = crate::R; -#[doc = "Field `CLR_RX_OVER` reader - Read this register to clear the RX_OVER interrupt (bit 1) of the IC_RAW_INTR_STAT register. - - Reset value: 0x0"] +#[doc = "Register `IC_CLR_RX_OVER` writer"] +pub type W = crate::W; +#[doc = "Field `CLR_RX_OVER` reader - Read this register to clear the RX_OVER interrupt (bit 1) of the IC_RAW_INTR_STAT register. Reset value: 0x0"] pub type CLR_RX_OVER_R = crate::BitReader; impl R { - #[doc = "Bit 0 - Read this register to clear the RX_OVER interrupt (bit 1) of the IC_RAW_INTR_STAT register. - - Reset value: 0x0"] + #[doc = "Bit 0 - Read this register to clear the RX_OVER interrupt (bit 1) of the IC_RAW_INTR_STAT register. Reset value: 0x0"] #[inline(always)] pub fn clr_rx_over(&self) -> CLR_RX_OVER_R { CLR_RX_OVER_R::new((self.bits & 1) != 0) } } +impl W {} #[doc = "Clear RX_OVER Interrupt Register -You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_rx_over::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_rx_over::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_clr_rx_over::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IC_CLR_RX_OVER_SPEC; impl crate::RegisterSpec for IC_CLR_RX_OVER_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`ic_clr_rx_over::R`](R) reader structure"] impl crate::Readable for IC_CLR_RX_OVER_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ic_clr_rx_over::W`](W) writer structure"] +impl crate::Writable for IC_CLR_RX_OVER_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets IC_CLR_RX_OVER to value 0"] impl crate::Resettable for IC_CLR_RX_OVER_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/i2c0/ic_clr_rx_under.rs b/src/i2c0/ic_clr_rx_under.rs index 1b213b86e..39480622b 100644 --- a/src/i2c0/ic_clr_rx_under.rs +++ b/src/i2c0/ic_clr_rx_under.rs @@ -1,27 +1,32 @@ #[doc = "Register `IC_CLR_RX_UNDER` reader"] pub type R = crate::R; -#[doc = "Field `CLR_RX_UNDER` reader - Read this register to clear the RX_UNDER interrupt (bit 0) of the IC_RAW_INTR_STAT register. - - Reset value: 0x0"] +#[doc = "Register `IC_CLR_RX_UNDER` writer"] +pub type W = crate::W; +#[doc = "Field `CLR_RX_UNDER` reader - Read this register to clear the RX_UNDER interrupt (bit 0) of the IC_RAW_INTR_STAT register. Reset value: 0x0"] pub type CLR_RX_UNDER_R = crate::BitReader; impl R { - #[doc = "Bit 0 - Read this register to clear the RX_UNDER interrupt (bit 0) of the IC_RAW_INTR_STAT register. - - Reset value: 0x0"] + #[doc = "Bit 0 - Read this register to clear the RX_UNDER interrupt (bit 0) of the IC_RAW_INTR_STAT register. Reset value: 0x0"] #[inline(always)] pub fn clr_rx_under(&self) -> CLR_RX_UNDER_R { CLR_RX_UNDER_R::new((self.bits & 1) != 0) } } +impl W {} #[doc = "Clear RX_UNDER Interrupt Register -You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_rx_under::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_rx_under::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_clr_rx_under::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IC_CLR_RX_UNDER_SPEC; impl crate::RegisterSpec for IC_CLR_RX_UNDER_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`ic_clr_rx_under::R`](R) reader structure"] impl crate::Readable for IC_CLR_RX_UNDER_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ic_clr_rx_under::W`](W) writer structure"] +impl crate::Writable for IC_CLR_RX_UNDER_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets IC_CLR_RX_UNDER to value 0"] impl crate::Resettable for IC_CLR_RX_UNDER_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/i2c0/ic_clr_start_det.rs b/src/i2c0/ic_clr_start_det.rs index 6b023c604..b948f512d 100644 --- a/src/i2c0/ic_clr_start_det.rs +++ b/src/i2c0/ic_clr_start_det.rs @@ -1,27 +1,32 @@ #[doc = "Register `IC_CLR_START_DET` reader"] pub type R = crate::R; -#[doc = "Field `CLR_START_DET` reader - Read this register to clear the START_DET interrupt (bit 10) of the IC_RAW_INTR_STAT register. - - Reset value: 0x0"] +#[doc = "Register `IC_CLR_START_DET` writer"] +pub type W = crate::W; +#[doc = "Field `CLR_START_DET` reader - Read this register to clear the START_DET interrupt (bit 10) of the IC_RAW_INTR_STAT register. Reset value: 0x0"] pub type CLR_START_DET_R = crate::BitReader; impl R { - #[doc = "Bit 0 - Read this register to clear the START_DET interrupt (bit 10) of the IC_RAW_INTR_STAT register. - - Reset value: 0x0"] + #[doc = "Bit 0 - Read this register to clear the START_DET interrupt (bit 10) of the IC_RAW_INTR_STAT register. Reset value: 0x0"] #[inline(always)] pub fn clr_start_det(&self) -> CLR_START_DET_R { CLR_START_DET_R::new((self.bits & 1) != 0) } } +impl W {} #[doc = "Clear START_DET Interrupt Register -You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_start_det::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_start_det::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_clr_start_det::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IC_CLR_START_DET_SPEC; impl crate::RegisterSpec for IC_CLR_START_DET_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`ic_clr_start_det::R`](R) reader structure"] impl crate::Readable for IC_CLR_START_DET_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ic_clr_start_det::W`](W) writer structure"] +impl crate::Writable for IC_CLR_START_DET_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets IC_CLR_START_DET to value 0"] impl crate::Resettable for IC_CLR_START_DET_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/i2c0/ic_clr_stop_det.rs b/src/i2c0/ic_clr_stop_det.rs index 21e987281..8bf136b80 100644 --- a/src/i2c0/ic_clr_stop_det.rs +++ b/src/i2c0/ic_clr_stop_det.rs @@ -1,27 +1,32 @@ #[doc = "Register `IC_CLR_STOP_DET` reader"] pub type R = crate::R; -#[doc = "Field `CLR_STOP_DET` reader - Read this register to clear the STOP_DET interrupt (bit 9) of the IC_RAW_INTR_STAT register. - - Reset value: 0x0"] +#[doc = "Register `IC_CLR_STOP_DET` writer"] +pub type W = crate::W; +#[doc = "Field `CLR_STOP_DET` reader - Read this register to clear the STOP_DET interrupt (bit 9) of the IC_RAW_INTR_STAT register. Reset value: 0x0"] pub type CLR_STOP_DET_R = crate::BitReader; impl R { - #[doc = "Bit 0 - Read this register to clear the STOP_DET interrupt (bit 9) of the IC_RAW_INTR_STAT register. - - Reset value: 0x0"] + #[doc = "Bit 0 - Read this register to clear the STOP_DET interrupt (bit 9) of the IC_RAW_INTR_STAT register. Reset value: 0x0"] #[inline(always)] pub fn clr_stop_det(&self) -> CLR_STOP_DET_R { CLR_STOP_DET_R::new((self.bits & 1) != 0) } } +impl W {} #[doc = "Clear STOP_DET Interrupt Register -You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_stop_det::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_stop_det::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_clr_stop_det::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IC_CLR_STOP_DET_SPEC; impl crate::RegisterSpec for IC_CLR_STOP_DET_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`ic_clr_stop_det::R`](R) reader structure"] impl crate::Readable for IC_CLR_STOP_DET_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ic_clr_stop_det::W`](W) writer structure"] +impl crate::Writable for IC_CLR_STOP_DET_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets IC_CLR_STOP_DET to value 0"] impl crate::Resettable for IC_CLR_STOP_DET_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/i2c0/ic_clr_tx_abrt.rs b/src/i2c0/ic_clr_tx_abrt.rs index 5e607c9d6..e6c6ba1d4 100644 --- a/src/i2c0/ic_clr_tx_abrt.rs +++ b/src/i2c0/ic_clr_tx_abrt.rs @@ -1,27 +1,32 @@ #[doc = "Register `IC_CLR_TX_ABRT` reader"] pub type R = crate::R; -#[doc = "Field `CLR_TX_ABRT` reader - Read this register to clear the TX_ABRT interrupt (bit 6) of the IC_RAW_INTR_STAT register, and the IC_TX_ABRT_SOURCE register. This also releases the TX FIFO from the flushed/reset state, allowing more writes to the TX FIFO. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE. - - Reset value: 0x0"] +#[doc = "Register `IC_CLR_TX_ABRT` writer"] +pub type W = crate::W; +#[doc = "Field `CLR_TX_ABRT` reader - Read this register to clear the TX_ABRT interrupt (bit 6) of the IC_RAW_INTR_STAT register, and the IC_TX_ABRT_SOURCE register. This also releases the TX FIFO from the flushed/reset state, allowing more writes to the TX FIFO. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE. Reset value: 0x0"] pub type CLR_TX_ABRT_R = crate::BitReader; impl R { - #[doc = "Bit 0 - Read this register to clear the TX_ABRT interrupt (bit 6) of the IC_RAW_INTR_STAT register, and the IC_TX_ABRT_SOURCE register. This also releases the TX FIFO from the flushed/reset state, allowing more writes to the TX FIFO. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE. - - Reset value: 0x0"] + #[doc = "Bit 0 - Read this register to clear the TX_ABRT interrupt (bit 6) of the IC_RAW_INTR_STAT register, and the IC_TX_ABRT_SOURCE register. This also releases the TX FIFO from the flushed/reset state, allowing more writes to the TX FIFO. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE. Reset value: 0x0"] #[inline(always)] pub fn clr_tx_abrt(&self) -> CLR_TX_ABRT_R { CLR_TX_ABRT_R::new((self.bits & 1) != 0) } } +impl W {} #[doc = "Clear TX_ABRT Interrupt Register -You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_tx_abrt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_tx_abrt::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_clr_tx_abrt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IC_CLR_TX_ABRT_SPEC; impl crate::RegisterSpec for IC_CLR_TX_ABRT_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`ic_clr_tx_abrt::R`](R) reader structure"] impl crate::Readable for IC_CLR_TX_ABRT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ic_clr_tx_abrt::W`](W) writer structure"] +impl crate::Writable for IC_CLR_TX_ABRT_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets IC_CLR_TX_ABRT to value 0"] impl crate::Resettable for IC_CLR_TX_ABRT_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/i2c0/ic_clr_tx_over.rs b/src/i2c0/ic_clr_tx_over.rs index 47d8502ce..8fec4b347 100644 --- a/src/i2c0/ic_clr_tx_over.rs +++ b/src/i2c0/ic_clr_tx_over.rs @@ -1,27 +1,32 @@ #[doc = "Register `IC_CLR_TX_OVER` reader"] pub type R = crate::R; -#[doc = "Field `CLR_TX_OVER` reader - Read this register to clear the TX_OVER interrupt (bit 3) of the IC_RAW_INTR_STAT register. - - Reset value: 0x0"] +#[doc = "Register `IC_CLR_TX_OVER` writer"] +pub type W = crate::W; +#[doc = "Field `CLR_TX_OVER` reader - Read this register to clear the TX_OVER interrupt (bit 3) of the IC_RAW_INTR_STAT register. Reset value: 0x0"] pub type CLR_TX_OVER_R = crate::BitReader; impl R { - #[doc = "Bit 0 - Read this register to clear the TX_OVER interrupt (bit 3) of the IC_RAW_INTR_STAT register. - - Reset value: 0x0"] + #[doc = "Bit 0 - Read this register to clear the TX_OVER interrupt (bit 3) of the IC_RAW_INTR_STAT register. Reset value: 0x0"] #[inline(always)] pub fn clr_tx_over(&self) -> CLR_TX_OVER_R { CLR_TX_OVER_R::new((self.bits & 1) != 0) } } +impl W {} #[doc = "Clear TX_OVER Interrupt Register -You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_tx_over::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`ic_clr_tx_over::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_clr_tx_over::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IC_CLR_TX_OVER_SPEC; impl crate::RegisterSpec for IC_CLR_TX_OVER_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`ic_clr_tx_over::R`](R) reader structure"] impl crate::Readable for IC_CLR_TX_OVER_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ic_clr_tx_over::W`](W) writer structure"] +impl crate::Writable for IC_CLR_TX_OVER_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets IC_CLR_TX_OVER to value 0"] impl crate::Resettable for IC_CLR_TX_OVER_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/i2c0/ic_comp_param_1.rs b/src/i2c0/ic_comp_param_1.rs index d059487c3..36d1a8f23 100644 --- a/src/i2c0/ic_comp_param_1.rs +++ b/src/i2c0/ic_comp_param_1.rs @@ -1,5 +1,7 @@ #[doc = "Register `IC_COMP_PARAM_1` reader"] pub type R = crate::R; +#[doc = "Register `IC_COMP_PARAM_1` writer"] +pub type W = crate::W; #[doc = "Field `APB_DATA_WIDTH` reader - APB data bus width is 32 bits"] pub type APB_DATA_WIDTH_R = crate::FieldReader; #[doc = "Field `MAX_SPEED_MODE` reader - MAX SPEED MODE = FAST MODE"] @@ -58,17 +60,22 @@ impl R { TX_BUFFER_DEPTH_R::new(((self.bits >> 16) & 0xff) as u8) } } -#[doc = "Component Parameter Register 1 +impl W {} +#[doc = "Component Parameter Register 1 Note This register is not implemented and therefore reads as 0. If it was implemented it would be a constant read-only register that contains encoded information about the component's parameter settings. Fields shown below are the settings for those parameters - Note This register is not implemented and therefore reads as 0. If it was implemented it would be a constant read-only register that contains encoded information about the component's parameter settings. Fields shown below are the settings for those parameters - -You can [`read`](crate::generic::Reg::read) this register and get [`ic_comp_param_1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`ic_comp_param_1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_comp_param_1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IC_COMP_PARAM_1_SPEC; impl crate::RegisterSpec for IC_COMP_PARAM_1_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`ic_comp_param_1::R`](R) reader structure"] impl crate::Readable for IC_COMP_PARAM_1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ic_comp_param_1::W`](W) writer structure"] +impl crate::Writable for IC_COMP_PARAM_1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets IC_COMP_PARAM_1 to value 0"] impl crate::Resettable for IC_COMP_PARAM_1_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/i2c0/ic_comp_type.rs b/src/i2c0/ic_comp_type.rs index 00fa9e0e4..1deb9616d 100644 --- a/src/i2c0/ic_comp_type.rs +++ b/src/i2c0/ic_comp_type.rs @@ -1,5 +1,7 @@ #[doc = "Register `IC_COMP_TYPE` reader"] pub type R = crate::R; +#[doc = "Register `IC_COMP_TYPE` writer"] +pub type W = crate::W; #[doc = "Field `IC_COMP_TYPE` reader - Designware Component Type number = 0x44_57_01_40. This assigned unique hex value is constant and is derived from the two ASCII letters 'DW' followed by a 16-bit unsigned number."] pub type IC_COMP_TYPE_R = crate::FieldReader; impl R { @@ -9,15 +11,22 @@ impl R { IC_COMP_TYPE_R::new(self.bits) } } +impl W {} #[doc = "I2C Component Type Register -You can [`read`](crate::generic::Reg::read) this register and get [`ic_comp_type::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`ic_comp_type::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_comp_type::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IC_COMP_TYPE_SPEC; impl crate::RegisterSpec for IC_COMP_TYPE_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`ic_comp_type::R`](R) reader structure"] impl crate::Readable for IC_COMP_TYPE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ic_comp_type::W`](W) writer structure"] +impl crate::Writable for IC_COMP_TYPE_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets IC_COMP_TYPE to value 0x4457_0140"] impl crate::Resettable for IC_COMP_TYPE_SPEC { const RESET_VALUE: u32 = 0x4457_0140; diff --git a/src/i2c0/ic_comp_version.rs b/src/i2c0/ic_comp_version.rs index 488ce877e..795595e2d 100644 --- a/src/i2c0/ic_comp_version.rs +++ b/src/i2c0/ic_comp_version.rs @@ -1,5 +1,7 @@ #[doc = "Register `IC_COMP_VERSION` reader"] pub type R = crate::R; +#[doc = "Register `IC_COMP_VERSION` writer"] +pub type W = crate::W; #[doc = "Field `IC_COMP_VERSION` reader - "] pub type IC_COMP_VERSION_R = crate::FieldReader; impl R { @@ -9,15 +11,22 @@ impl R { IC_COMP_VERSION_R::new(self.bits) } } +impl W {} #[doc = "I2C Component Version Register -You can [`read`](crate::generic::Reg::read) this register and get [`ic_comp_version::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`ic_comp_version::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_comp_version::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IC_COMP_VERSION_SPEC; impl crate::RegisterSpec for IC_COMP_VERSION_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`ic_comp_version::R`](R) reader structure"] impl crate::Readable for IC_COMP_VERSION_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ic_comp_version::W`](W) writer structure"] +impl crate::Writable for IC_COMP_VERSION_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets IC_COMP_VERSION to value 0x3230_312a"] impl crate::Resettable for IC_COMP_VERSION_SPEC { const RESET_VALUE: u32 = 0x3230_312a; diff --git a/src/i2c0/ic_con.rs b/src/i2c0/ic_con.rs index a210ffffa..fe2f77ab5 100644 --- a/src/i2c0/ic_con.rs +++ b/src/i2c0/ic_con.rs @@ -2,9 +2,7 @@ pub type R = crate::R; #[doc = "Register `IC_CON` writer"] pub type W = crate::W; -#[doc = "This bit controls whether the DW_apb_i2c master is enabled. - - NOTE: Software should ensure that if this bit is written with '1' then bit 6 should also be written with a '1'. +#[doc = "This bit controls whether the DW_apb_i2c master is enabled. NOTE: Software should ensure that if this bit is written with '1' then bit 6 should also be written with a '1'. Value on reset: 1"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -20,9 +18,7 @@ impl From for bool { variant as u8 != 0 } } -#[doc = "Field `MASTER_MODE` reader - This bit controls whether the DW_apb_i2c master is enabled. - - NOTE: Software should ensure that if this bit is written with '1' then bit 6 should also be written with a '1'."] +#[doc = "Field `MASTER_MODE` reader - This bit controls whether the DW_apb_i2c master is enabled. NOTE: Software should ensure that if this bit is written with '1' then bit 6 should also be written with a '1'."] pub type MASTER_MODE_R = crate::BitReader; impl MASTER_MODE_R { #[doc = "Get enumerated values variant"] @@ -44,9 +40,7 @@ impl MASTER_MODE_R { *self == MASTER_MODE_A::ENABLED } } -#[doc = "Field `MASTER_MODE` writer - This bit controls whether the DW_apb_i2c master is enabled. - - NOTE: Software should ensure that if this bit is written with '1' then bit 6 should also be written with a '1'."] +#[doc = "Field `MASTER_MODE` writer - This bit controls whether the DW_apb_i2c master is enabled. NOTE: Software should ensure that if this bit is written with '1' then bit 6 should also be written with a '1'."] pub type MASTER_MODE_W<'a, REG> = crate::BitWriter<'a, REG, MASTER_MODE_A>; impl<'a, REG> MASTER_MODE_W<'a, REG> where @@ -63,17 +57,7 @@ where self.variant(MASTER_MODE_A::ENABLED) } } -#[doc = "These bits control at which speed the DW_apb_i2c operates; its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode also, as it is used to capture correct value of spike filter as per the speed mode. - - This register should be programmed only with a value in the range of 1 to IC_MAX_SPEED_MODE; otherwise, hardware updates this register with the value of IC_MAX_SPEED_MODE. - - 1: standard mode (100 kbit/s) - - 2: fast mode (<=400 kbit/s) or fast mode plus (<=1000Kbit/s) - - 3: high speed mode (3.4 Mbit/s) - - Note: This field is not applicable when IC_ULTRA_FAST_MODE=1 +#[doc = "These bits control at which speed the DW_apb_i2c operates; its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode also, as it is used to capture correct value of spike filter as per the speed mode. This register should be programmed only with a value in the range of 1 to IC_MAX_SPEED_MODE; otherwise, hardware updates this register with the value of IC_MAX_SPEED_MODE. 1: standard mode (100 kbit/s) 2: fast mode (<=400 kbit/s) or fast mode plus (<=1000Kbit/s) 3: high speed mode (3.4 Mbit/s) Note: This field is not applicable when IC_ULTRA_FAST_MODE=1 Value on reset: 2"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -95,17 +79,7 @@ impl From for u8 { impl crate::FieldSpec for SPEED_A { type Ux = u8; } -#[doc = "Field `SPEED` reader - These bits control at which speed the DW_apb_i2c operates; its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode also, as it is used to capture correct value of spike filter as per the speed mode. - - This register should be programmed only with a value in the range of 1 to IC_MAX_SPEED_MODE; otherwise, hardware updates this register with the value of IC_MAX_SPEED_MODE. - - 1: standard mode (100 kbit/s) - - 2: fast mode (<=400 kbit/s) or fast mode plus (<=1000Kbit/s) - - 3: high speed mode (3.4 Mbit/s) - - Note: This field is not applicable when IC_ULTRA_FAST_MODE=1"] +#[doc = "Field `SPEED` reader - These bits control at which speed the DW_apb_i2c operates; its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode also, as it is used to capture correct value of spike filter as per the speed mode. This register should be programmed only with a value in the range of 1 to IC_MAX_SPEED_MODE; otherwise, hardware updates this register with the value of IC_MAX_SPEED_MODE. 1: standard mode (100 kbit/s) 2: fast mode (<=400 kbit/s) or fast mode plus (<=1000Kbit/s) 3: high speed mode (3.4 Mbit/s) Note: This field is not applicable when IC_ULTRA_FAST_MODE=1"] pub type SPEED_R = crate::FieldReader; impl SPEED_R { #[doc = "Get enumerated values variant"] @@ -134,17 +108,7 @@ impl SPEED_R { *self == SPEED_A::HIGH } } -#[doc = "Field `SPEED` writer - These bits control at which speed the DW_apb_i2c operates; its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode also, as it is used to capture correct value of spike filter as per the speed mode. - - This register should be programmed only with a value in the range of 1 to IC_MAX_SPEED_MODE; otherwise, hardware updates this register with the value of IC_MAX_SPEED_MODE. - - 1: standard mode (100 kbit/s) - - 2: fast mode (<=400 kbit/s) or fast mode plus (<=1000Kbit/s) - - 3: high speed mode (3.4 Mbit/s) - - Note: This field is not applicable when IC_ULTRA_FAST_MODE=1"] +#[doc = "Field `SPEED` writer - These bits control at which speed the DW_apb_i2c operates; its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode also, as it is used to capture correct value of spike filter as per the speed mode. This register should be programmed only with a value in the range of 1 to IC_MAX_SPEED_MODE; otherwise, hardware updates this register with the value of IC_MAX_SPEED_MODE. 1: standard mode (100 kbit/s) 2: fast mode (<=400 kbit/s) or fast mode plus (<=1000Kbit/s) 3: high speed mode (3.4 Mbit/s) Note: This field is not applicable when IC_ULTRA_FAST_MODE=1"] pub type SPEED_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SPEED_A>; impl<'a, REG> SPEED_W<'a, REG> where @@ -277,9 +241,7 @@ where self.variant(IC_10BITADDR_MASTER_A::ADDR_10BITS) } } -#[doc = "Determines whether RESTART conditions may be sent when acting as a master. Some older slaves do not support handling RESTART conditions; however, RESTART conditions are used in several DW_apb_i2c operations. When RESTART is disabled, the master is prohibited from performing the following functions: - Sending a START BYTE - Performing any high-speed mode operation - High-speed mode operation - Performing direction changes in combined format mode - Performing a read operation with a 10-bit address By replacing RESTART condition followed by a STOP and a subsequent START condition, split operations are broken down into multiple DW_apb_i2c transfers. If the above operations are performed, it will result in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. - - Reset value: ENABLED +#[doc = "Determines whether RESTART conditions may be sent when acting as a master. Some older slaves do not support handling RESTART conditions; however, RESTART conditions are used in several DW_apb_i2c operations. When RESTART is disabled, the master is prohibited from performing the following functions: - Sending a START BYTE - Performing any high-speed mode operation - High-speed mode operation - Performing direction changes in combined format mode - Performing a read operation with a 10-bit address By replacing RESTART condition followed by a STOP and a subsequent START condition, split operations are broken down into multiple DW_apb_i2c transfers. If the above operations are performed, it will result in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. Reset value: ENABLED Value on reset: 1"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -295,9 +257,7 @@ impl From for bool { variant as u8 != 0 } } -#[doc = "Field `IC_RESTART_EN` reader - Determines whether RESTART conditions may be sent when acting as a master. Some older slaves do not support handling RESTART conditions; however, RESTART conditions are used in several DW_apb_i2c operations. When RESTART is disabled, the master is prohibited from performing the following functions: - Sending a START BYTE - Performing any high-speed mode operation - High-speed mode operation - Performing direction changes in combined format mode - Performing a read operation with a 10-bit address By replacing RESTART condition followed by a STOP and a subsequent START condition, split operations are broken down into multiple DW_apb_i2c transfers. If the above operations are performed, it will result in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. - - Reset value: ENABLED"] +#[doc = "Field `IC_RESTART_EN` reader - Determines whether RESTART conditions may be sent when acting as a master. Some older slaves do not support handling RESTART conditions; however, RESTART conditions are used in several DW_apb_i2c operations. When RESTART is disabled, the master is prohibited from performing the following functions: - Sending a START BYTE - Performing any high-speed mode operation - High-speed mode operation - Performing direction changes in combined format mode - Performing a read operation with a 10-bit address By replacing RESTART condition followed by a STOP and a subsequent START condition, split operations are broken down into multiple DW_apb_i2c transfers. If the above operations are performed, it will result in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. Reset value: ENABLED"] pub type IC_RESTART_EN_R = crate::BitReader; impl IC_RESTART_EN_R { #[doc = "Get enumerated values variant"] @@ -319,9 +279,7 @@ impl IC_RESTART_EN_R { *self == IC_RESTART_EN_A::ENABLED } } -#[doc = "Field `IC_RESTART_EN` writer - Determines whether RESTART conditions may be sent when acting as a master. Some older slaves do not support handling RESTART conditions; however, RESTART conditions are used in several DW_apb_i2c operations. When RESTART is disabled, the master is prohibited from performing the following functions: - Sending a START BYTE - Performing any high-speed mode operation - High-speed mode operation - Performing direction changes in combined format mode - Performing a read operation with a 10-bit address By replacing RESTART condition followed by a STOP and a subsequent START condition, split operations are broken down into multiple DW_apb_i2c transfers. If the above operations are performed, it will result in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. - - Reset value: ENABLED"] +#[doc = "Field `IC_RESTART_EN` writer - Determines whether RESTART conditions may be sent when acting as a master. Some older slaves do not support handling RESTART conditions; however, RESTART conditions are used in several DW_apb_i2c operations. When RESTART is disabled, the master is prohibited from performing the following functions: - Sending a START BYTE - Performing any high-speed mode operation - High-speed mode operation - Performing direction changes in combined format mode - Performing a read operation with a 10-bit address By replacing RESTART condition followed by a STOP and a subsequent START condition, split operations are broken down into multiple DW_apb_i2c transfers. If the above operations are performed, it will result in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. Reset value: ENABLED"] pub type IC_RESTART_EN_W<'a, REG> = crate::BitWriter<'a, REG, IC_RESTART_EN_A>; impl<'a, REG> IC_RESTART_EN_W<'a, REG> where @@ -338,11 +296,7 @@ where self.variant(IC_RESTART_EN_A::ENABLED) } } -#[doc = "This bit controls whether I2C has its slave disabled, which means once the presetn signal is applied, then this bit is set and the slave is disabled. - - If this bit is set (slave is disabled), DW_apb_i2c functions only as a master and does not perform any action that requires a slave. - - NOTE: Software should ensure that if this bit is written with 0, then bit 0 should also be written with a 0. +#[doc = "This bit controls whether I2C has its slave disabled, which means once the presetn signal is applied, then this bit is set and the slave is disabled. If this bit is set (slave is disabled), DW_apb_i2c functions only as a master and does not perform any action that requires a slave. NOTE: Software should ensure that if this bit is written with 0, then bit 0 should also be written with a 0. Value on reset: 1"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -358,11 +312,7 @@ impl From for bool { variant as u8 != 0 } } -#[doc = "Field `IC_SLAVE_DISABLE` reader - This bit controls whether I2C has its slave disabled, which means once the presetn signal is applied, then this bit is set and the slave is disabled. - - If this bit is set (slave is disabled), DW_apb_i2c functions only as a master and does not perform any action that requires a slave. - - NOTE: Software should ensure that if this bit is written with 0, then bit 0 should also be written with a 0."] +#[doc = "Field `IC_SLAVE_DISABLE` reader - This bit controls whether I2C has its slave disabled, which means once the presetn signal is applied, then this bit is set and the slave is disabled. If this bit is set (slave is disabled), DW_apb_i2c functions only as a master and does not perform any action that requires a slave. NOTE: Software should ensure that if this bit is written with 0, then bit 0 should also be written with a 0."] pub type IC_SLAVE_DISABLE_R = crate::BitReader; impl IC_SLAVE_DISABLE_R { #[doc = "Get enumerated values variant"] @@ -384,11 +334,7 @@ impl IC_SLAVE_DISABLE_R { *self == IC_SLAVE_DISABLE_A::SLAVE_DISABLED } } -#[doc = "Field `IC_SLAVE_DISABLE` writer - This bit controls whether I2C has its slave disabled, which means once the presetn signal is applied, then this bit is set and the slave is disabled. - - If this bit is set (slave is disabled), DW_apb_i2c functions only as a master and does not perform any action that requires a slave. - - NOTE: Software should ensure that if this bit is written with 0, then bit 0 should also be written with a 0."] +#[doc = "Field `IC_SLAVE_DISABLE` writer - This bit controls whether I2C has its slave disabled, which means once the presetn signal is applied, then this bit is set and the slave is disabled. If this bit is set (slave is disabled), DW_apb_i2c functions only as a master and does not perform any action that requires a slave. NOTE: Software should ensure that if this bit is written with 0, then bit 0 should also be written with a 0."] pub type IC_SLAVE_DISABLE_W<'a, REG> = crate::BitWriter<'a, REG, IC_SLAVE_DISABLE_A>; impl<'a, REG> IC_SLAVE_DISABLE_W<'a, REG> where @@ -405,9 +351,7 @@ where self.variant(IC_SLAVE_DISABLE_A::SLAVE_DISABLED) } } -#[doc = "In slave mode: - 1'b1: issues the STOP_DET interrupt only when it is addressed. - 1'b0: issues the STOP_DET irrespective of whether it's addressed or not. Reset value: 0x0 - - NOTE: During a general call address, this slave does not issue the STOP_DET interrupt if STOP_DET_IF_ADDRESSED = 1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR). +#[doc = "In slave mode: - 1'b1: issues the STOP_DET interrupt only when it is addressed. - 1'b0: issues the STOP_DET irrespective of whether it's addressed or not. Reset value: 0x0 NOTE: During a general call address, this slave does not issue the STOP_DET interrupt if STOP_DET_IF_ADDRESSED = 1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR). Value on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -423,9 +367,7 @@ impl From for bool { variant as u8 != 0 } } -#[doc = "Field `STOP_DET_IFADDRESSED` reader - In slave mode: - 1'b1: issues the STOP_DET interrupt only when it is addressed. - 1'b0: issues the STOP_DET irrespective of whether it's addressed or not. Reset value: 0x0 - - NOTE: During a general call address, this slave does not issue the STOP_DET interrupt if STOP_DET_IF_ADDRESSED = 1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR)."] +#[doc = "Field `STOP_DET_IFADDRESSED` reader - In slave mode: - 1'b1: issues the STOP_DET interrupt only when it is addressed. - 1'b0: issues the STOP_DET irrespective of whether it's addressed or not. Reset value: 0x0 NOTE: During a general call address, this slave does not issue the STOP_DET interrupt if STOP_DET_IF_ADDRESSED = 1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR)."] pub type STOP_DET_IFADDRESSED_R = crate::BitReader; impl STOP_DET_IFADDRESSED_R { #[doc = "Get enumerated values variant"] @@ -447,9 +389,7 @@ impl STOP_DET_IFADDRESSED_R { *self == STOP_DET_IFADDRESSED_A::ENABLED } } -#[doc = "Field `STOP_DET_IFADDRESSED` writer - In slave mode: - 1'b1: issues the STOP_DET interrupt only when it is addressed. - 1'b0: issues the STOP_DET irrespective of whether it's addressed or not. Reset value: 0x0 - - NOTE: During a general call address, this slave does not issue the STOP_DET interrupt if STOP_DET_IF_ADDRESSED = 1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR)."] +#[doc = "Field `STOP_DET_IFADDRESSED` writer - In slave mode: - 1'b1: issues the STOP_DET interrupt only when it is addressed. - 1'b0: issues the STOP_DET irrespective of whether it's addressed or not. Reset value: 0x0 NOTE: During a general call address, this slave does not issue the STOP_DET interrupt if STOP_DET_IF_ADDRESSED = 1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR)."] pub type STOP_DET_IFADDRESSED_W<'a, REG> = crate::BitWriter<'a, REG, STOP_DET_IFADDRESSED_A>; impl<'a, REG> STOP_DET_IFADDRESSED_W<'a, REG> where @@ -466,9 +406,7 @@ where self.variant(STOP_DET_IFADDRESSED_A::ENABLED) } } -#[doc = "This bit controls the generation of the TX_EMPTY interrupt, as described in the IC_RAW_INTR_STAT register. - - Reset value: 0x0. +#[doc = "This bit controls the generation of the TX_EMPTY interrupt, as described in the IC_RAW_INTR_STAT register. Reset value: 0x0. Value on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -484,9 +422,7 @@ impl From for bool { variant as u8 != 0 } } -#[doc = "Field `TX_EMPTY_CTRL` reader - This bit controls the generation of the TX_EMPTY interrupt, as described in the IC_RAW_INTR_STAT register. - - Reset value: 0x0."] +#[doc = "Field `TX_EMPTY_CTRL` reader - This bit controls the generation of the TX_EMPTY interrupt, as described in the IC_RAW_INTR_STAT register. Reset value: 0x0."] pub type TX_EMPTY_CTRL_R = crate::BitReader; impl TX_EMPTY_CTRL_R { #[doc = "Get enumerated values variant"] @@ -508,9 +444,7 @@ impl TX_EMPTY_CTRL_R { *self == TX_EMPTY_CTRL_A::ENABLED } } -#[doc = "Field `TX_EMPTY_CTRL` writer - This bit controls the generation of the TX_EMPTY interrupt, as described in the IC_RAW_INTR_STAT register. - - Reset value: 0x0."] +#[doc = "Field `TX_EMPTY_CTRL` writer - This bit controls the generation of the TX_EMPTY interrupt, as described in the IC_RAW_INTR_STAT register. Reset value: 0x0."] pub type TX_EMPTY_CTRL_W<'a, REG> = crate::BitWriter<'a, REG, TX_EMPTY_CTRL_A>; impl<'a, REG> TX_EMPTY_CTRL_W<'a, REG> where @@ -527,9 +461,7 @@ where self.variant(TX_EMPTY_CTRL_A::ENABLED) } } -#[doc = "This bit controls whether DW_apb_i2c should hold the bus when the Rx FIFO is physically full to its RX_BUFFER_DEPTH, as described in the IC_RX_FULL_HLD_BUS_EN parameter. - - Reset value: 0x0. +#[doc = "This bit controls whether DW_apb_i2c should hold the bus when the Rx FIFO is physically full to its RX_BUFFER_DEPTH, as described in the IC_RX_FULL_HLD_BUS_EN parameter. Reset value: 0x0. Value on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -545,9 +477,7 @@ impl From for bool { variant as u8 != 0 } } -#[doc = "Field `RX_FIFO_FULL_HLD_CTRL` reader - This bit controls whether DW_apb_i2c should hold the bus when the Rx FIFO is physically full to its RX_BUFFER_DEPTH, as described in the IC_RX_FULL_HLD_BUS_EN parameter. - - Reset value: 0x0."] +#[doc = "Field `RX_FIFO_FULL_HLD_CTRL` reader - This bit controls whether DW_apb_i2c should hold the bus when the Rx FIFO is physically full to its RX_BUFFER_DEPTH, as described in the IC_RX_FULL_HLD_BUS_EN parameter. Reset value: 0x0."] pub type RX_FIFO_FULL_HLD_CTRL_R = crate::BitReader; impl RX_FIFO_FULL_HLD_CTRL_R { #[doc = "Get enumerated values variant"] @@ -569,9 +499,7 @@ impl RX_FIFO_FULL_HLD_CTRL_R { *self == RX_FIFO_FULL_HLD_CTRL_A::ENABLED } } -#[doc = "Field `RX_FIFO_FULL_HLD_CTRL` writer - This bit controls whether DW_apb_i2c should hold the bus when the Rx FIFO is physically full to its RX_BUFFER_DEPTH, as described in the IC_RX_FULL_HLD_BUS_EN parameter. - - Reset value: 0x0."] +#[doc = "Field `RX_FIFO_FULL_HLD_CTRL` writer - This bit controls whether DW_apb_i2c should hold the bus when the Rx FIFO is physically full to its RX_BUFFER_DEPTH, as described in the IC_RX_FULL_HLD_BUS_EN parameter. Reset value: 0x0."] pub type RX_FIFO_FULL_HLD_CTRL_W<'a, REG> = crate::BitWriter<'a, REG, RX_FIFO_FULL_HLD_CTRL_A>; impl<'a, REG> RX_FIFO_FULL_HLD_CTRL_W<'a, REG> where @@ -591,24 +519,12 @@ where #[doc = "Field `STOP_DET_IF_MASTER_ACTIVE` reader - Master issues the STOP_DET interrupt irrespective of whether master is active or not"] pub type STOP_DET_IF_MASTER_ACTIVE_R = crate::BitReader; impl R { - #[doc = "Bit 0 - This bit controls whether the DW_apb_i2c master is enabled. - - NOTE: Software should ensure that if this bit is written with '1' then bit 6 should also be written with a '1'."] + #[doc = "Bit 0 - This bit controls whether the DW_apb_i2c master is enabled. NOTE: Software should ensure that if this bit is written with '1' then bit 6 should also be written with a '1'."] #[inline(always)] pub fn master_mode(&self) -> MASTER_MODE_R { MASTER_MODE_R::new((self.bits & 1) != 0) } - #[doc = "Bits 1:2 - These bits control at which speed the DW_apb_i2c operates; its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode also, as it is used to capture correct value of spike filter as per the speed mode. - - This register should be programmed only with a value in the range of 1 to IC_MAX_SPEED_MODE; otherwise, hardware updates this register with the value of IC_MAX_SPEED_MODE. - - 1: standard mode (100 kbit/s) - - 2: fast mode (<=400 kbit/s) or fast mode plus (<=1000Kbit/s) - - 3: high speed mode (3.4 Mbit/s) - - Note: This field is not applicable when IC_ULTRA_FAST_MODE=1"] + #[doc = "Bits 1:2 - These bits control at which speed the DW_apb_i2c operates; its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode also, as it is used to capture correct value of spike filter as per the speed mode. This register should be programmed only with a value in the range of 1 to IC_MAX_SPEED_MODE; otherwise, hardware updates this register with the value of IC_MAX_SPEED_MODE. 1: standard mode (100 kbit/s) 2: fast mode (<=400 kbit/s) or fast mode plus (<=1000Kbit/s) 3: high speed mode (3.4 Mbit/s) Note: This field is not applicable when IC_ULTRA_FAST_MODE=1"] #[inline(always)] pub fn speed(&self) -> SPEED_R { SPEED_R::new(((self.bits >> 1) & 3) as u8) @@ -623,39 +539,27 @@ impl R { pub fn ic_10bitaddr_master(&self) -> IC_10BITADDR_MASTER_R { IC_10BITADDR_MASTER_R::new(((self.bits >> 4) & 1) != 0) } - #[doc = "Bit 5 - Determines whether RESTART conditions may be sent when acting as a master. Some older slaves do not support handling RESTART conditions; however, RESTART conditions are used in several DW_apb_i2c operations. When RESTART is disabled, the master is prohibited from performing the following functions: - Sending a START BYTE - Performing any high-speed mode operation - High-speed mode operation - Performing direction changes in combined format mode - Performing a read operation with a 10-bit address By replacing RESTART condition followed by a STOP and a subsequent START condition, split operations are broken down into multiple DW_apb_i2c transfers. If the above operations are performed, it will result in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. - - Reset value: ENABLED"] + #[doc = "Bit 5 - Determines whether RESTART conditions may be sent when acting as a master. Some older slaves do not support handling RESTART conditions; however, RESTART conditions are used in several DW_apb_i2c operations. When RESTART is disabled, the master is prohibited from performing the following functions: - Sending a START BYTE - Performing any high-speed mode operation - High-speed mode operation - Performing direction changes in combined format mode - Performing a read operation with a 10-bit address By replacing RESTART condition followed by a STOP and a subsequent START condition, split operations are broken down into multiple DW_apb_i2c transfers. If the above operations are performed, it will result in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. Reset value: ENABLED"] #[inline(always)] pub fn ic_restart_en(&self) -> IC_RESTART_EN_R { IC_RESTART_EN_R::new(((self.bits >> 5) & 1) != 0) } - #[doc = "Bit 6 - This bit controls whether I2C has its slave disabled, which means once the presetn signal is applied, then this bit is set and the slave is disabled. - - If this bit is set (slave is disabled), DW_apb_i2c functions only as a master and does not perform any action that requires a slave. - - NOTE: Software should ensure that if this bit is written with 0, then bit 0 should also be written with a 0."] + #[doc = "Bit 6 - This bit controls whether I2C has its slave disabled, which means once the presetn signal is applied, then this bit is set and the slave is disabled. If this bit is set (slave is disabled), DW_apb_i2c functions only as a master and does not perform any action that requires a slave. NOTE: Software should ensure that if this bit is written with 0, then bit 0 should also be written with a 0."] #[inline(always)] pub fn ic_slave_disable(&self) -> IC_SLAVE_DISABLE_R { IC_SLAVE_DISABLE_R::new(((self.bits >> 6) & 1) != 0) } - #[doc = "Bit 7 - In slave mode: - 1'b1: issues the STOP_DET interrupt only when it is addressed. - 1'b0: issues the STOP_DET irrespective of whether it's addressed or not. Reset value: 0x0 - - NOTE: During a general call address, this slave does not issue the STOP_DET interrupt if STOP_DET_IF_ADDRESSED = 1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR)."] + #[doc = "Bit 7 - In slave mode: - 1'b1: issues the STOP_DET interrupt only when it is addressed. - 1'b0: issues the STOP_DET irrespective of whether it's addressed or not. Reset value: 0x0 NOTE: During a general call address, this slave does not issue the STOP_DET interrupt if STOP_DET_IF_ADDRESSED = 1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR)."] #[inline(always)] pub fn stop_det_ifaddressed(&self) -> STOP_DET_IFADDRESSED_R { STOP_DET_IFADDRESSED_R::new(((self.bits >> 7) & 1) != 0) } - #[doc = "Bit 8 - This bit controls the generation of the TX_EMPTY interrupt, as described in the IC_RAW_INTR_STAT register. - - Reset value: 0x0."] + #[doc = "Bit 8 - This bit controls the generation of the TX_EMPTY interrupt, as described in the IC_RAW_INTR_STAT register. Reset value: 0x0."] #[inline(always)] pub fn tx_empty_ctrl(&self) -> TX_EMPTY_CTRL_R { TX_EMPTY_CTRL_R::new(((self.bits >> 8) & 1) != 0) } - #[doc = "Bit 9 - This bit controls whether DW_apb_i2c should hold the bus when the Rx FIFO is physically full to its RX_BUFFER_DEPTH, as described in the IC_RX_FULL_HLD_BUS_EN parameter. - - Reset value: 0x0."] + #[doc = "Bit 9 - This bit controls whether DW_apb_i2c should hold the bus when the Rx FIFO is physically full to its RX_BUFFER_DEPTH, as described in the IC_RX_FULL_HLD_BUS_EN parameter. Reset value: 0x0."] #[inline(always)] pub fn rx_fifo_full_hld_ctrl(&self) -> RX_FIFO_FULL_HLD_CTRL_R { RX_FIFO_FULL_HLD_CTRL_R::new(((self.bits >> 9) & 1) != 0) @@ -667,25 +571,13 @@ impl R { } } impl W { - #[doc = "Bit 0 - This bit controls whether the DW_apb_i2c master is enabled. - - NOTE: Software should ensure that if this bit is written with '1' then bit 6 should also be written with a '1'."] + #[doc = "Bit 0 - This bit controls whether the DW_apb_i2c master is enabled. NOTE: Software should ensure that if this bit is written with '1' then bit 6 should also be written with a '1'."] #[inline(always)] #[must_use] pub fn master_mode(&mut self) -> MASTER_MODE_W { MASTER_MODE_W::new(self, 0) } - #[doc = "Bits 1:2 - These bits control at which speed the DW_apb_i2c operates; its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode also, as it is used to capture correct value of spike filter as per the speed mode. - - This register should be programmed only with a value in the range of 1 to IC_MAX_SPEED_MODE; otherwise, hardware updates this register with the value of IC_MAX_SPEED_MODE. - - 1: standard mode (100 kbit/s) - - 2: fast mode (<=400 kbit/s) or fast mode plus (<=1000Kbit/s) - - 3: high speed mode (3.4 Mbit/s) - - Note: This field is not applicable when IC_ULTRA_FAST_MODE=1"] + #[doc = "Bits 1:2 - These bits control at which speed the DW_apb_i2c operates; its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode also, as it is used to capture correct value of spike filter as per the speed mode. This register should be programmed only with a value in the range of 1 to IC_MAX_SPEED_MODE; otherwise, hardware updates this register with the value of IC_MAX_SPEED_MODE. 1: standard mode (100 kbit/s) 2: fast mode (<=400 kbit/s) or fast mode plus (<=1000Kbit/s) 3: high speed mode (3.4 Mbit/s) Note: This field is not applicable when IC_ULTRA_FAST_MODE=1"] #[inline(always)] #[must_use] pub fn speed(&mut self) -> SPEED_W { @@ -703,43 +595,31 @@ impl W { pub fn ic_10bitaddr_master(&mut self) -> IC_10BITADDR_MASTER_W { IC_10BITADDR_MASTER_W::new(self, 4) } - #[doc = "Bit 5 - Determines whether RESTART conditions may be sent when acting as a master. Some older slaves do not support handling RESTART conditions; however, RESTART conditions are used in several DW_apb_i2c operations. When RESTART is disabled, the master is prohibited from performing the following functions: - Sending a START BYTE - Performing any high-speed mode operation - High-speed mode operation - Performing direction changes in combined format mode - Performing a read operation with a 10-bit address By replacing RESTART condition followed by a STOP and a subsequent START condition, split operations are broken down into multiple DW_apb_i2c transfers. If the above operations are performed, it will result in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. - - Reset value: ENABLED"] + #[doc = "Bit 5 - Determines whether RESTART conditions may be sent when acting as a master. Some older slaves do not support handling RESTART conditions; however, RESTART conditions are used in several DW_apb_i2c operations. When RESTART is disabled, the master is prohibited from performing the following functions: - Sending a START BYTE - Performing any high-speed mode operation - High-speed mode operation - Performing direction changes in combined format mode - Performing a read operation with a 10-bit address By replacing RESTART condition followed by a STOP and a subsequent START condition, split operations are broken down into multiple DW_apb_i2c transfers. If the above operations are performed, it will result in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. Reset value: ENABLED"] #[inline(always)] #[must_use] pub fn ic_restart_en(&mut self) -> IC_RESTART_EN_W { IC_RESTART_EN_W::new(self, 5) } - #[doc = "Bit 6 - This bit controls whether I2C has its slave disabled, which means once the presetn signal is applied, then this bit is set and the slave is disabled. - - If this bit is set (slave is disabled), DW_apb_i2c functions only as a master and does not perform any action that requires a slave. - - NOTE: Software should ensure that if this bit is written with 0, then bit 0 should also be written with a 0."] + #[doc = "Bit 6 - This bit controls whether I2C has its slave disabled, which means once the presetn signal is applied, then this bit is set and the slave is disabled. If this bit is set (slave is disabled), DW_apb_i2c functions only as a master and does not perform any action that requires a slave. NOTE: Software should ensure that if this bit is written with 0, then bit 0 should also be written with a 0."] #[inline(always)] #[must_use] pub fn ic_slave_disable(&mut self) -> IC_SLAVE_DISABLE_W { IC_SLAVE_DISABLE_W::new(self, 6) } - #[doc = "Bit 7 - In slave mode: - 1'b1: issues the STOP_DET interrupt only when it is addressed. - 1'b0: issues the STOP_DET irrespective of whether it's addressed or not. Reset value: 0x0 - - NOTE: During a general call address, this slave does not issue the STOP_DET interrupt if STOP_DET_IF_ADDRESSED = 1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR)."] + #[doc = "Bit 7 - In slave mode: - 1'b1: issues the STOP_DET interrupt only when it is addressed. - 1'b0: issues the STOP_DET irrespective of whether it's addressed or not. Reset value: 0x0 NOTE: During a general call address, this slave does not issue the STOP_DET interrupt if STOP_DET_IF_ADDRESSED = 1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR)."] #[inline(always)] #[must_use] pub fn stop_det_ifaddressed(&mut self) -> STOP_DET_IFADDRESSED_W { STOP_DET_IFADDRESSED_W::new(self, 7) } - #[doc = "Bit 8 - This bit controls the generation of the TX_EMPTY interrupt, as described in the IC_RAW_INTR_STAT register. - - Reset value: 0x0."] + #[doc = "Bit 8 - This bit controls the generation of the TX_EMPTY interrupt, as described in the IC_RAW_INTR_STAT register. Reset value: 0x0."] #[inline(always)] #[must_use] pub fn tx_empty_ctrl(&mut self) -> TX_EMPTY_CTRL_W { TX_EMPTY_CTRL_W::new(self, 8) } - #[doc = "Bit 9 - This bit controls whether DW_apb_i2c should hold the bus when the Rx FIFO is physically full to its RX_BUFFER_DEPTH, as described in the IC_RX_FULL_HLD_BUS_EN parameter. - - Reset value: 0x0."] + #[doc = "Bit 9 - This bit controls whether DW_apb_i2c should hold the bus when the Rx FIFO is physically full to its RX_BUFFER_DEPTH, as described in the IC_RX_FULL_HLD_BUS_EN parameter. Reset value: 0x0."] #[inline(always)] #[must_use] pub fn rx_fifo_full_hld_ctrl(&mut self) -> RX_FIFO_FULL_HLD_CTRL_W { @@ -747,9 +627,7 @@ impl W { } } #[doc = "I2C Control Register. This register can be written only when the DW_apb_i2c is disabled, which corresponds to the IC_ENABLE\\[0\\] -register being set to 0. Writes at other times have no effect. - - Read/Write Access: - bit 10 is read only. - bit 11 is read only - bit 16 is read only - bit 17 is read only - bits 18 and 19 are read only. +register being set to 0. Writes at other times have no effect. Read/Write Access: - bit 10 is read only. - bit 11 is read only - bit 16 is read only - bit 17 is read only - bits 18 and 19 are read only. You can [`read`](crate::generic::Reg::read) this register and get [`ic_con::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_con::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IC_CON_SPEC; diff --git a/src/i2c0/ic_data_cmd.rs b/src/i2c0/ic_data_cmd.rs index a0cd32bcb..7f34665d1 100644 --- a/src/i2c0/ic_data_cmd.rs +++ b/src/i2c0/ic_data_cmd.rs @@ -2,21 +2,11 @@ pub type R = crate::R; #[doc = "Register `IC_DATA_CMD` writer"] pub type W = crate::W; -#[doc = "Field `DAT` reader - This register contains the data to be transmitted or received on the I2C bus. If you are writing to this register and want to perform a read, bits 7:0 (DAT) are ignored by the DW_apb_i2c. However, when you read this register, these bits return the value of data received on the DW_apb_i2c interface. - - Reset value: 0x0"] +#[doc = "Field `DAT` reader - This register contains the data to be transmitted or received on the I2C bus. If you are writing to this register and want to perform a read, bits 7:0 (DAT) are ignored by the DW_apb_i2c. However, when you read this register, these bits return the value of data received on the DW_apb_i2c interface. Reset value: 0x0"] pub type DAT_R = crate::FieldReader; -#[doc = "Field `DAT` writer - This register contains the data to be transmitted or received on the I2C bus. If you are writing to this register and want to perform a read, bits 7:0 (DAT) are ignored by the DW_apb_i2c. However, when you read this register, these bits return the value of data received on the DW_apb_i2c interface. - - Reset value: 0x0"] +#[doc = "Field `DAT` writer - This register contains the data to be transmitted or received on the I2C bus. If you are writing to this register and want to perform a read, bits 7:0 (DAT) are ignored by the DW_apb_i2c. However, when you read this register, these bits return the value of data received on the DW_apb_i2c interface. Reset value: 0x0"] pub type DAT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "This bit controls whether a read or a write is performed. This bit does not control the direction when the DW_apb_i2con acts as a slave. It controls only the direction when it acts as a master. - - When a command is entered in the TX FIFO, this bit distinguishes the write and read commands. In slave-receiver mode, this bit is a 'don't care' because writes to this register are not required. In slave-transmitter mode, a '0' indicates that the data in IC_DATA_CMD is to be transmitted. - - When programming this bit, you should remember the following: attempting to perform a read operation after a General Call command has been sent results in a TX_ABRT interrupt (bit 6 of the IC_RAW_INTR_STAT register), unless bit 11 (SPECIAL) in the IC_TAR register has been cleared. If a '1' is written to this bit after receiving a RD_REQ interrupt, then a TX_ABRT interrupt occurs. - - Reset value: 0x0 +#[doc = "This bit controls whether a read or a write is performed. This bit does not control the direction when the DW_apb_i2con acts as a slave. It controls only the direction when it acts as a master. When a command is entered in the TX FIFO, this bit distinguishes the write and read commands. In slave-receiver mode, this bit is a 'don't care' because writes to this register are not required. In slave-transmitter mode, a '0' indicates that the data in IC_DATA_CMD is to be transmitted. When programming this bit, you should remember the following: attempting to perform a read operation after a General Call command has been sent results in a TX_ABRT interrupt (bit 6 of the IC_RAW_INTR_STAT register), unless bit 11 (SPECIAL) in the IC_TAR register has been cleared. If a '1' is written to this bit after receiving a RD_REQ interrupt, then a TX_ABRT interrupt occurs. Reset value: 0x0 Value on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -32,41 +22,7 @@ impl From for bool { variant as u8 != 0 } } -#[doc = "Field `CMD` reader - This bit controls whether a read or a write is performed. This bit does not control the direction when the DW_apb_i2con acts as a slave. It controls only the direction when it acts as a master. - - When a command is entered in the TX FIFO, this bit distinguishes the write and read commands. In slave-receiver mode, this bit is a 'don't care' because writes to this register are not required. In slave-transmitter mode, a '0' indicates that the data in IC_DATA_CMD is to be transmitted. - - When programming this bit, you should remember the following: attempting to perform a read operation after a General Call command has been sent results in a TX_ABRT interrupt (bit 6 of the IC_RAW_INTR_STAT register), unless bit 11 (SPECIAL) in the IC_TAR register has been cleared. If a '1' is written to this bit after receiving a RD_REQ interrupt, then a TX_ABRT interrupt occurs. - - Reset value: 0x0"] -pub type CMD_R = crate::BitReader; -impl CMD_R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> CMD_A { - match self.bits { - false => CMD_A::WRITE, - true => CMD_A::READ, - } - } - #[doc = "Master Write Command"] - #[inline(always)] - pub fn is_write(&self) -> bool { - *self == CMD_A::WRITE - } - #[doc = "Master Read Command"] - #[inline(always)] - pub fn is_read(&self) -> bool { - *self == CMD_A::READ - } -} -#[doc = "Field `CMD` writer - This bit controls whether a read or a write is performed. This bit does not control the direction when the DW_apb_i2con acts as a slave. It controls only the direction when it acts as a master. - - When a command is entered in the TX FIFO, this bit distinguishes the write and read commands. In slave-receiver mode, this bit is a 'don't care' because writes to this register are not required. In slave-transmitter mode, a '0' indicates that the data in IC_DATA_CMD is to be transmitted. - - When programming this bit, you should remember the following: attempting to perform a read operation after a General Call command has been sent results in a TX_ABRT interrupt (bit 6 of the IC_RAW_INTR_STAT register), unless bit 11 (SPECIAL) in the IC_TAR register has been cleared. If a '1' is written to this bit after receiving a RD_REQ interrupt, then a TX_ABRT interrupt occurs. - - Reset value: 0x0"] +#[doc = "Field `CMD` writer - This bit controls whether a read or a write is performed. This bit does not control the direction when the DW_apb_i2con acts as a slave. It controls only the direction when it acts as a master. When a command is entered in the TX FIFO, this bit distinguishes the write and read commands. In slave-receiver mode, this bit is a 'don't care' because writes to this register are not required. In slave-transmitter mode, a '0' indicates that the data in IC_DATA_CMD is to be transmitted. When programming this bit, you should remember the following: attempting to perform a read operation after a General Call command has been sent results in a TX_ABRT interrupt (bit 6 of the IC_RAW_INTR_STAT register), unless bit 11 (SPECIAL) in the IC_TAR register has been cleared. If a '1' is written to this bit after receiving a RD_REQ interrupt, then a TX_ABRT interrupt occurs. Reset value: 0x0"] pub type CMD_W<'a, REG> = crate::BitWriter<'a, REG, CMD_A>; impl<'a, REG> CMD_W<'a, REG> where @@ -83,9 +39,7 @@ where self.variant(CMD_A::READ) } } -#[doc = "This bit controls whether a STOP is issued after the byte is sent or received. - - - 1 - STOP is issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master immediately tries to start a new transfer by issuing a START and arbitrating for the bus. - 0 - STOP is not issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master continues the current transfer by sending/receiving data bytes according to the value of the CMD bit. If the Tx FIFO is empty, the master holds the SCL line low and stalls the bus until a new command is available in the Tx FIFO. Reset value: 0x0 +#[doc = "This bit controls whether a STOP is issued after the byte is sent or received. - 1 - STOP is issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master immediately tries to start a new transfer by issuing a START and arbitrating for the bus. - 0 - STOP is not issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master continues the current transfer by sending/receiving data bytes according to the value of the CMD bit. If the Tx FIFO is empty, the master holds the SCL line low and stalls the bus until a new command is available in the Tx FIFO. Reset value: 0x0 Value on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -101,33 +55,7 @@ impl From for bool { variant as u8 != 0 } } -#[doc = "Field `STOP` reader - This bit controls whether a STOP is issued after the byte is sent or received. - - - 1 - STOP is issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master immediately tries to start a new transfer by issuing a START and arbitrating for the bus. - 0 - STOP is not issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master continues the current transfer by sending/receiving data bytes according to the value of the CMD bit. If the Tx FIFO is empty, the master holds the SCL line low and stalls the bus until a new command is available in the Tx FIFO. Reset value: 0x0"] -pub type STOP_R = crate::BitReader; -impl STOP_R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> STOP_A { - match self.bits { - false => STOP_A::DISABLE, - true => STOP_A::ENABLE, - } - } - #[doc = "Don't Issue STOP after this command"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == STOP_A::DISABLE - } - #[doc = "Issue STOP after this command"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == STOP_A::ENABLE - } -} -#[doc = "Field `STOP` writer - This bit controls whether a STOP is issued after the byte is sent or received. - - - 1 - STOP is issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master immediately tries to start a new transfer by issuing a START and arbitrating for the bus. - 0 - STOP is not issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master continues the current transfer by sending/receiving data bytes according to the value of the CMD bit. If the Tx FIFO is empty, the master holds the SCL line low and stalls the bus until a new command is available in the Tx FIFO. Reset value: 0x0"] +#[doc = "Field `STOP` writer - This bit controls whether a STOP is issued after the byte is sent or received. - 1 - STOP is issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master immediately tries to start a new transfer by issuing a START and arbitrating for the bus. - 0 - STOP is not issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master continues the current transfer by sending/receiving data bytes according to the value of the CMD bit. If the Tx FIFO is empty, the master holds the SCL line low and stalls the bus until a new command is available in the Tx FIFO. Reset value: 0x0"] pub type STOP_W<'a, REG> = crate::BitWriter<'a, REG, STOP_A>; impl<'a, REG> STOP_W<'a, REG> where @@ -144,13 +72,7 @@ where self.variant(STOP_A::ENABLE) } } -#[doc = "This bit controls whether a RESTART is issued before the byte is sent or received. - - 1 - If IC_RESTART_EN is 1, a RESTART is issued before the data is sent/received (according to the value of CMD), regardless of whether or not the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead. - - 0 - If IC_RESTART_EN is 1, a RESTART is issued only if the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead. - - Reset value: 0x0 +#[doc = "This bit controls whether a RESTART is issued before the byte is sent or received. 1 - If IC_RESTART_EN is 1, a RESTART is issued before the data is sent/received (according to the value of CMD), regardless of whether or not the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead. 0 - If IC_RESTART_EN is 1, a RESTART is issued only if the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead. Reset value: 0x0 Value on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -166,41 +88,7 @@ impl From for bool { variant as u8 != 0 } } -#[doc = "Field `RESTART` reader - This bit controls whether a RESTART is issued before the byte is sent or received. - - 1 - If IC_RESTART_EN is 1, a RESTART is issued before the data is sent/received (according to the value of CMD), regardless of whether or not the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead. - - 0 - If IC_RESTART_EN is 1, a RESTART is issued only if the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead. - - Reset value: 0x0"] -pub type RESTART_R = crate::BitReader; -impl RESTART_R { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> RESTART_A { - match self.bits { - false => RESTART_A::DISABLE, - true => RESTART_A::ENABLE, - } - } - #[doc = "Don't Issue RESTART before this command"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == RESTART_A::DISABLE - } - #[doc = "Issue RESTART before this command"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == RESTART_A::ENABLE - } -} -#[doc = "Field `RESTART` writer - This bit controls whether a RESTART is issued before the byte is sent or received. - - 1 - If IC_RESTART_EN is 1, a RESTART is issued before the data is sent/received (according to the value of CMD), regardless of whether or not the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead. - - 0 - If IC_RESTART_EN is 1, a RESTART is issued only if the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead. - - Reset value: 0x0"] +#[doc = "Field `RESTART` writer - This bit controls whether a RESTART is issued before the byte is sent or received. 1 - If IC_RESTART_EN is 1, a RESTART is issued before the data is sent/received (according to the value of CMD), regardless of whether or not the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead. 0 - If IC_RESTART_EN is 1, a RESTART is issued only if the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead. Reset value: 0x0"] pub type RESTART_W<'a, REG> = crate::BitWriter<'a, REG, RESTART_A>; impl<'a, REG> RESTART_W<'a, REG> where @@ -217,19 +105,9 @@ where self.variant(RESTART_A::ENABLE) } } -#[doc = "Indicates the first data byte received after the address phase for receive transfer in Master receiver or Slave receiver mode. - - Reset value : 0x0 - - NOTE: In case of APB_DATA_WIDTH=8, - - 1. The user has to perform two APB Reads to IC_DATA_CMD in order to get status on 11 bit. - - 2. In order to read the 11 bit, the user has to perform the first data byte read \\[7:0\\] +#[doc = "Indicates the first data byte received after the address phase for receive transfer in Master receiver or Slave receiver mode. Reset value : 0x0 NOTE: In case of APB_DATA_WIDTH=8, 1. The user has to perform two APB Reads to IC_DATA_CMD in order to get status on 11 bit. 2. In order to read the 11 bit, the user has to perform the first data byte read \\[7:0\\] (offset 0x10) and then perform the second read \\[15:8\\] -(offset 0x11) in order to know the status of 11 bit (whether the data received in previous read is a first data byte or not). - - 3. The 11th bit is an optional read field, user can ignore 2nd byte read \\[15:8\\] +(offset 0x11) in order to know the status of 11 bit (whether the data received in previous read is a first data byte or not). 3. The 11th bit is an optional read field, user can ignore 2nd byte read \\[15:8\\] (offset 0x11) if not interested in FIRST_DATA_BYTE status. Value on reset: 0"] @@ -246,19 +124,9 @@ impl From for bool { variant as u8 != 0 } } -#[doc = "Field `FIRST_DATA_BYTE` reader - Indicates the first data byte received after the address phase for receive transfer in Master receiver or Slave receiver mode. - - Reset value : 0x0 - - NOTE: In case of APB_DATA_WIDTH=8, - - 1. The user has to perform two APB Reads to IC_DATA_CMD in order to get status on 11 bit. - - 2. In order to read the 11 bit, the user has to perform the first data byte read \\[7:0\\] +#[doc = "Field `FIRST_DATA_BYTE` reader - Indicates the first data byte received after the address phase for receive transfer in Master receiver or Slave receiver mode. Reset value : 0x0 NOTE: In case of APB_DATA_WIDTH=8, 1. The user has to perform two APB Reads to IC_DATA_CMD in order to get status on 11 bit. 2. In order to read the 11 bit, the user has to perform the first data byte read \\[7:0\\] (offset 0x10) and then perform the second read \\[15:8\\] -(offset 0x11) in order to know the status of 11 bit (whether the data received in previous read is a first data byte or not). - - 3. The 11th bit is an optional read field, user can ignore 2nd byte read \\[15:8\\] +(offset 0x11) in order to know the status of 11 bit (whether the data received in previous read is a first data byte or not). 3. The 11th bit is an optional read field, user can ignore 2nd byte read \\[15:8\\] (offset 0x11) if not interested in FIRST_DATA_BYTE status."] pub type FIRST_DATA_BYTE_R = crate::BitReader; impl FIRST_DATA_BYTE_R { @@ -282,55 +150,14 @@ impl FIRST_DATA_BYTE_R { } } impl R { - #[doc = "Bits 0:7 - This register contains the data to be transmitted or received on the I2C bus. If you are writing to this register and want to perform a read, bits 7:0 (DAT) are ignored by the DW_apb_i2c. However, when you read this register, these bits return the value of data received on the DW_apb_i2c interface. - - Reset value: 0x0"] + #[doc = "Bits 0:7 - This register contains the data to be transmitted or received on the I2C bus. If you are writing to this register and want to perform a read, bits 7:0 (DAT) are ignored by the DW_apb_i2c. However, when you read this register, these bits return the value of data received on the DW_apb_i2c interface. Reset value: 0x0"] #[inline(always)] pub fn dat(&self) -> DAT_R { DAT_R::new((self.bits & 0xff) as u8) } - #[doc = "Bit 8 - This bit controls whether a read or a write is performed. This bit does not control the direction when the DW_apb_i2con acts as a slave. It controls only the direction when it acts as a master. - - When a command is entered in the TX FIFO, this bit distinguishes the write and read commands. In slave-receiver mode, this bit is a 'don't care' because writes to this register are not required. In slave-transmitter mode, a '0' indicates that the data in IC_DATA_CMD is to be transmitted. - - When programming this bit, you should remember the following: attempting to perform a read operation after a General Call command has been sent results in a TX_ABRT interrupt (bit 6 of the IC_RAW_INTR_STAT register), unless bit 11 (SPECIAL) in the IC_TAR register has been cleared. If a '1' is written to this bit after receiving a RD_REQ interrupt, then a TX_ABRT interrupt occurs. - - Reset value: 0x0"] - #[inline(always)] - pub fn cmd(&self) -> CMD_R { - CMD_R::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - This bit controls whether a STOP is issued after the byte is sent or received. - - - 1 - STOP is issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master immediately tries to start a new transfer by issuing a START and arbitrating for the bus. - 0 - STOP is not issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master continues the current transfer by sending/receiving data bytes according to the value of the CMD bit. If the Tx FIFO is empty, the master holds the SCL line low and stalls the bus until a new command is available in the Tx FIFO. Reset value: 0x0"] - #[inline(always)] - pub fn stop(&self) -> STOP_R { - STOP_R::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10 - This bit controls whether a RESTART is issued before the byte is sent or received. - - 1 - If IC_RESTART_EN is 1, a RESTART is issued before the data is sent/received (according to the value of CMD), regardless of whether or not the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead. - - 0 - If IC_RESTART_EN is 1, a RESTART is issued only if the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead. - - Reset value: 0x0"] - #[inline(always)] - pub fn restart(&self) -> RESTART_R { - RESTART_R::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 11 - Indicates the first data byte received after the address phase for receive transfer in Master receiver or Slave receiver mode. - - Reset value : 0x0 - - NOTE: In case of APB_DATA_WIDTH=8, - - 1. The user has to perform two APB Reads to IC_DATA_CMD in order to get status on 11 bit. - - 2. In order to read the 11 bit, the user has to perform the first data byte read \\[7:0\\] + #[doc = "Bit 11 - Indicates the first data byte received after the address phase for receive transfer in Master receiver or Slave receiver mode. Reset value : 0x0 NOTE: In case of APB_DATA_WIDTH=8, 1. The user has to perform two APB Reads to IC_DATA_CMD in order to get status on 11 bit. 2. In order to read the 11 bit, the user has to perform the first data byte read \\[7:0\\] (offset 0x10) and then perform the second read \\[15:8\\] -(offset 0x11) in order to know the status of 11 bit (whether the data received in previous read is a first data byte or not). - - 3. The 11th bit is an optional read field, user can ignore 2nd byte read \\[15:8\\] +(offset 0x11) in order to know the status of 11 bit (whether the data received in previous read is a first data byte or not). 3. The 11th bit is an optional read field, user can ignore 2nd byte read \\[15:8\\] (offset 0x11) if not interested in FIRST_DATA_BYTE status."] #[inline(always)] pub fn first_data_byte(&self) -> FIRST_DATA_BYTE_R { @@ -338,52 +165,32 @@ impl R { } } impl W { - #[doc = "Bits 0:7 - This register contains the data to be transmitted or received on the I2C bus. If you are writing to this register and want to perform a read, bits 7:0 (DAT) are ignored by the DW_apb_i2c. However, when you read this register, these bits return the value of data received on the DW_apb_i2c interface. - - Reset value: 0x0"] + #[doc = "Bits 0:7 - This register contains the data to be transmitted or received on the I2C bus. If you are writing to this register and want to perform a read, bits 7:0 (DAT) are ignored by the DW_apb_i2c. However, when you read this register, these bits return the value of data received on the DW_apb_i2c interface. Reset value: 0x0"] #[inline(always)] #[must_use] pub fn dat(&mut self) -> DAT_W { DAT_W::new(self, 0) } - #[doc = "Bit 8 - This bit controls whether a read or a write is performed. This bit does not control the direction when the DW_apb_i2con acts as a slave. It controls only the direction when it acts as a master. - - When a command is entered in the TX FIFO, this bit distinguishes the write and read commands. In slave-receiver mode, this bit is a 'don't care' because writes to this register are not required. In slave-transmitter mode, a '0' indicates that the data in IC_DATA_CMD is to be transmitted. - - When programming this bit, you should remember the following: attempting to perform a read operation after a General Call command has been sent results in a TX_ABRT interrupt (bit 6 of the IC_RAW_INTR_STAT register), unless bit 11 (SPECIAL) in the IC_TAR register has been cleared. If a '1' is written to this bit after receiving a RD_REQ interrupt, then a TX_ABRT interrupt occurs. - - Reset value: 0x0"] + #[doc = "Bit 8 - This bit controls whether a read or a write is performed. This bit does not control the direction when the DW_apb_i2con acts as a slave. It controls only the direction when it acts as a master. When a command is entered in the TX FIFO, this bit distinguishes the write and read commands. In slave-receiver mode, this bit is a 'don't care' because writes to this register are not required. In slave-transmitter mode, a '0' indicates that the data in IC_DATA_CMD is to be transmitted. When programming this bit, you should remember the following: attempting to perform a read operation after a General Call command has been sent results in a TX_ABRT interrupt (bit 6 of the IC_RAW_INTR_STAT register), unless bit 11 (SPECIAL) in the IC_TAR register has been cleared. If a '1' is written to this bit after receiving a RD_REQ interrupt, then a TX_ABRT interrupt occurs. Reset value: 0x0"] #[inline(always)] #[must_use] pub fn cmd(&mut self) -> CMD_W { CMD_W::new(self, 8) } - #[doc = "Bit 9 - This bit controls whether a STOP is issued after the byte is sent or received. - - - 1 - STOP is issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master immediately tries to start a new transfer by issuing a START and arbitrating for the bus. - 0 - STOP is not issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master continues the current transfer by sending/receiving data bytes according to the value of the CMD bit. If the Tx FIFO is empty, the master holds the SCL line low and stalls the bus until a new command is available in the Tx FIFO. Reset value: 0x0"] + #[doc = "Bit 9 - This bit controls whether a STOP is issued after the byte is sent or received. - 1 - STOP is issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master immediately tries to start a new transfer by issuing a START and arbitrating for the bus. - 0 - STOP is not issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master continues the current transfer by sending/receiving data bytes according to the value of the CMD bit. If the Tx FIFO is empty, the master holds the SCL line low and stalls the bus until a new command is available in the Tx FIFO. Reset value: 0x0"] #[inline(always)] #[must_use] pub fn stop(&mut self) -> STOP_W { STOP_W::new(self, 9) } - #[doc = "Bit 10 - This bit controls whether a RESTART is issued before the byte is sent or received. - - 1 - If IC_RESTART_EN is 1, a RESTART is issued before the data is sent/received (according to the value of CMD), regardless of whether or not the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead. - - 0 - If IC_RESTART_EN is 1, a RESTART is issued only if the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead. - - Reset value: 0x0"] + #[doc = "Bit 10 - This bit controls whether a RESTART is issued before the byte is sent or received. 1 - If IC_RESTART_EN is 1, a RESTART is issued before the data is sent/received (according to the value of CMD), regardless of whether or not the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead. 0 - If IC_RESTART_EN is 1, a RESTART is issued only if the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead. Reset value: 0x0"] #[inline(always)] #[must_use] pub fn restart(&mut self) -> RESTART_W { RESTART_W::new(self, 10) } } -#[doc = "I2C Rx/Tx Data Buffer and Command Register; this is the register the CPU writes to when filling the TX FIFO and the CPU reads from when retrieving bytes from RX FIFO. - - The size of the register changes as follows: - - Write: - 11 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=1 - 9 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=0 Read: - 12 bits when IC_FIRST_DATA_BYTE_STATUS = 1 - 8 bits when IC_FIRST_DATA_BYTE_STATUS = 0 Note: In order for the DW_apb_i2c to continue acknowledging reads, a read command should be written for every byte that is to be received; otherwise the DW_apb_i2c will stop acknowledging. +#[doc = "I2C Rx/Tx Data Buffer and Command Register; this is the register the CPU writes to when filling the TX FIFO and the CPU reads from when retrieving bytes from RX FIFO. The size of the register changes as follows: Write: - 11 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=1 - 9 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=0 Read: - 12 bits when IC_FIRST_DATA_BYTE_STATUS = 1 - 8 bits when IC_FIRST_DATA_BYTE_STATUS = 0 Note: In order for the DW_apb_i2c to continue acknowledging reads, a read command should be written for every byte that is to be received; otherwise the DW_apb_i2c will stop acknowledging. You can [`read`](crate::generic::Reg::read) this register and get [`ic_data_cmd::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_data_cmd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IC_DATA_CMD_SPEC; diff --git a/src/i2c0/ic_dma_cr.rs b/src/i2c0/ic_dma_cr.rs index 73ace2dd3..47f755256 100644 --- a/src/i2c0/ic_dma_cr.rs +++ b/src/i2c0/ic_dma_cr.rs @@ -138,9 +138,7 @@ impl W { TDMAE_W::new(self, 1) } } -#[doc = "DMA Control Register - - The register is used to enable the DMA Controller interface operation. There is a separate bit for transmit and receive. This can be programmed regardless of the state of IC_ENABLE. +#[doc = "DMA Control Register The register is used to enable the DMA Controller interface operation. There is a separate bit for transmit and receive. This can be programmed regardless of the state of IC_ENABLE. You can [`read`](crate::generic::Reg::read) this register and get [`ic_dma_cr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_dma_cr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IC_DMA_CR_SPEC; diff --git a/src/i2c0/ic_dma_rdlr.rs b/src/i2c0/ic_dma_rdlr.rs index 0acb62409..72db23050 100644 --- a/src/i2c0/ic_dma_rdlr.rs +++ b/src/i2c0/ic_dma_rdlr.rs @@ -2,27 +2,19 @@ pub type R = crate::R; #[doc = "Register `IC_DMA_RDLR` writer"] pub type W = crate::W; -#[doc = "Field `DMARDL` reader - Receive Data Level. This bit field controls the level at which a DMA request is made by the receive logic. The watermark level = DMARDL+1; that is, dma_rx_req is generated when the number of valid data entries in the receive FIFO is equal to or more than this field value + 1, and RDMAE =1. For instance, when DMARDL is 0, then dma_rx_req is asserted when 1 or more data entries are present in the receive FIFO. - - Reset value: 0x0"] +#[doc = "Field `DMARDL` reader - Receive Data Level. This bit field controls the level at which a DMA request is made by the receive logic. The watermark level = DMARDL+1; that is, dma_rx_req is generated when the number of valid data entries in the receive FIFO is equal to or more than this field value + 1, and RDMAE =1. For instance, when DMARDL is 0, then dma_rx_req is asserted when 1 or more data entries are present in the receive FIFO. Reset value: 0x0"] pub type DMARDL_R = crate::FieldReader; -#[doc = "Field `DMARDL` writer - Receive Data Level. This bit field controls the level at which a DMA request is made by the receive logic. The watermark level = DMARDL+1; that is, dma_rx_req is generated when the number of valid data entries in the receive FIFO is equal to or more than this field value + 1, and RDMAE =1. For instance, when DMARDL is 0, then dma_rx_req is asserted when 1 or more data entries are present in the receive FIFO. - - Reset value: 0x0"] +#[doc = "Field `DMARDL` writer - Receive Data Level. This bit field controls the level at which a DMA request is made by the receive logic. The watermark level = DMARDL+1; that is, dma_rx_req is generated when the number of valid data entries in the receive FIFO is equal to or more than this field value + 1, and RDMAE =1. For instance, when DMARDL is 0, then dma_rx_req is asserted when 1 or more data entries are present in the receive FIFO. Reset value: 0x0"] pub type DMARDL_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; impl R { - #[doc = "Bits 0:3 - Receive Data Level. This bit field controls the level at which a DMA request is made by the receive logic. The watermark level = DMARDL+1; that is, dma_rx_req is generated when the number of valid data entries in the receive FIFO is equal to or more than this field value + 1, and RDMAE =1. For instance, when DMARDL is 0, then dma_rx_req is asserted when 1 or more data entries are present in the receive FIFO. - - Reset value: 0x0"] + #[doc = "Bits 0:3 - Receive Data Level. This bit field controls the level at which a DMA request is made by the receive logic. The watermark level = DMARDL+1; that is, dma_rx_req is generated when the number of valid data entries in the receive FIFO is equal to or more than this field value + 1, and RDMAE =1. For instance, when DMARDL is 0, then dma_rx_req is asserted when 1 or more data entries are present in the receive FIFO. Reset value: 0x0"] #[inline(always)] pub fn dmardl(&self) -> DMARDL_R { DMARDL_R::new((self.bits & 0x0f) as u8) } } impl W { - #[doc = "Bits 0:3 - Receive Data Level. This bit field controls the level at which a DMA request is made by the receive logic. The watermark level = DMARDL+1; that is, dma_rx_req is generated when the number of valid data entries in the receive FIFO is equal to or more than this field value + 1, and RDMAE =1. For instance, when DMARDL is 0, then dma_rx_req is asserted when 1 or more data entries are present in the receive FIFO. - - Reset value: 0x0"] + #[doc = "Bits 0:3 - Receive Data Level. This bit field controls the level at which a DMA request is made by the receive logic. The watermark level = DMARDL+1; that is, dma_rx_req is generated when the number of valid data entries in the receive FIFO is equal to or more than this field value + 1, and RDMAE =1. For instance, when DMARDL is 0, then dma_rx_req is asserted when 1 or more data entries are present in the receive FIFO. Reset value: 0x0"] #[inline(always)] #[must_use] pub fn dmardl(&mut self) -> DMARDL_W { diff --git a/src/i2c0/ic_dma_tdlr.rs b/src/i2c0/ic_dma_tdlr.rs index 9afd98445..8c782eae9 100644 --- a/src/i2c0/ic_dma_tdlr.rs +++ b/src/i2c0/ic_dma_tdlr.rs @@ -2,27 +2,19 @@ pub type R = crate::R; #[doc = "Register `IC_DMA_TDLR` writer"] pub type W = crate::W; -#[doc = "Field `DMATDL` reader - Transmit Data Level. This bit field controls the level at which a DMA request is made by the transmit logic. It is equal to the watermark level; that is, the dma_tx_req signal is generated when the number of valid data entries in the transmit FIFO is equal to or below this field value, and TDMAE = 1. - - Reset value: 0x0"] +#[doc = "Field `DMATDL` reader - Transmit Data Level. This bit field controls the level at which a DMA request is made by the transmit logic. It is equal to the watermark level; that is, the dma_tx_req signal is generated when the number of valid data entries in the transmit FIFO is equal to or below this field value, and TDMAE = 1. Reset value: 0x0"] pub type DMATDL_R = crate::FieldReader; -#[doc = "Field `DMATDL` writer - Transmit Data Level. This bit field controls the level at which a DMA request is made by the transmit logic. It is equal to the watermark level; that is, the dma_tx_req signal is generated when the number of valid data entries in the transmit FIFO is equal to or below this field value, and TDMAE = 1. - - Reset value: 0x0"] +#[doc = "Field `DMATDL` writer - Transmit Data Level. This bit field controls the level at which a DMA request is made by the transmit logic. It is equal to the watermark level; that is, the dma_tx_req signal is generated when the number of valid data entries in the transmit FIFO is equal to or below this field value, and TDMAE = 1. Reset value: 0x0"] pub type DMATDL_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; impl R { - #[doc = "Bits 0:3 - Transmit Data Level. This bit field controls the level at which a DMA request is made by the transmit logic. It is equal to the watermark level; that is, the dma_tx_req signal is generated when the number of valid data entries in the transmit FIFO is equal to or below this field value, and TDMAE = 1. - - Reset value: 0x0"] + #[doc = "Bits 0:3 - Transmit Data Level. This bit field controls the level at which a DMA request is made by the transmit logic. It is equal to the watermark level; that is, the dma_tx_req signal is generated when the number of valid data entries in the transmit FIFO is equal to or below this field value, and TDMAE = 1. Reset value: 0x0"] #[inline(always)] pub fn dmatdl(&self) -> DMATDL_R { DMATDL_R::new((self.bits & 0x0f) as u8) } } impl W { - #[doc = "Bits 0:3 - Transmit Data Level. This bit field controls the level at which a DMA request is made by the transmit logic. It is equal to the watermark level; that is, the dma_tx_req signal is generated when the number of valid data entries in the transmit FIFO is equal to or below this field value, and TDMAE = 1. - - Reset value: 0x0"] + #[doc = "Bits 0:3 - Transmit Data Level. This bit field controls the level at which a DMA request is made by the transmit logic. It is equal to the watermark level; that is, the dma_tx_req signal is generated when the number of valid data entries in the transmit FIFO is equal to or below this field value, and TDMAE = 1. Reset value: 0x0"] #[inline(always)] #[must_use] pub fn dmatdl(&mut self) -> DMATDL_W { diff --git a/src/i2c0/ic_enable.rs b/src/i2c0/ic_enable.rs index 960e02f5c..76a228314 100644 --- a/src/i2c0/ic_enable.rs +++ b/src/i2c0/ic_enable.rs @@ -2,13 +2,7 @@ pub type R = crate::R; #[doc = "Register `IC_ENABLE` writer"] pub type W = crate::W; -#[doc = "Controls whether the DW_apb_i2c is enabled. - 0: Disables DW_apb_i2c (TX and RX FIFOs are held in an erased state) - 1: Enables DW_apb_i2c Software can disable DW_apb_i2c while it is active. However, it is important that care be taken to ensure that DW_apb_i2c is disabled properly. A recommended procedure is described in 'Disabling DW_apb_i2c'. - - When DW_apb_i2c is disabled, the following occurs: - The TX FIFO and RX FIFO get flushed. - Status bits in the IC_INTR_STAT register are still active until DW_apb_i2c goes into IDLE state. If the module is transmitting, it stops as well as deletes the contents of the transmit buffer after the current transfer is complete. If the module is receiving, the DW_apb_i2c stops the current transfer at the end of the current byte and does not acknowledge the transfer. - - In systems with asynchronous pclk and ic_clk when IC_CLK_TYPE parameter set to asynchronous (1), there is a two ic_clk delay when enabling or disabling the DW_apb_i2c. For a detailed description on how to disable DW_apb_i2c, refer to 'Disabling DW_apb_i2c' - - Reset value: 0x0 +#[doc = "Controls whether the DW_apb_i2c is enabled. - 0: Disables DW_apb_i2c (TX and RX FIFOs are held in an erased state) - 1: Enables DW_apb_i2c Software can disable DW_apb_i2c while it is active. However, it is important that care be taken to ensure that DW_apb_i2c is disabled properly. A recommended procedure is described in 'Disabling DW_apb_i2c'. When DW_apb_i2c is disabled, the following occurs: - The TX FIFO and RX FIFO get flushed. - Status bits in the IC_INTR_STAT register are still active until DW_apb_i2c goes into IDLE state. If the module is transmitting, it stops as well as deletes the contents of the transmit buffer after the current transfer is complete. If the module is receiving, the DW_apb_i2c stops the current transfer at the end of the current byte and does not acknowledge the transfer. In systems with asynchronous pclk and ic_clk when IC_CLK_TYPE parameter set to asynchronous (1), there is a two ic_clk delay when enabling or disabling the DW_apb_i2c. For a detailed description on how to disable DW_apb_i2c, refer to 'Disabling DW_apb_i2c' Reset value: 0x0 Value on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -24,13 +18,7 @@ impl From for bool { variant as u8 != 0 } } -#[doc = "Field `ENABLE` reader - Controls whether the DW_apb_i2c is enabled. - 0: Disables DW_apb_i2c (TX and RX FIFOs are held in an erased state) - 1: Enables DW_apb_i2c Software can disable DW_apb_i2c while it is active. However, it is important that care be taken to ensure that DW_apb_i2c is disabled properly. A recommended procedure is described in 'Disabling DW_apb_i2c'. - - When DW_apb_i2c is disabled, the following occurs: - The TX FIFO and RX FIFO get flushed. - Status bits in the IC_INTR_STAT register are still active until DW_apb_i2c goes into IDLE state. If the module is transmitting, it stops as well as deletes the contents of the transmit buffer after the current transfer is complete. If the module is receiving, the DW_apb_i2c stops the current transfer at the end of the current byte and does not acknowledge the transfer. - - In systems with asynchronous pclk and ic_clk when IC_CLK_TYPE parameter set to asynchronous (1), there is a two ic_clk delay when enabling or disabling the DW_apb_i2c. For a detailed description on how to disable DW_apb_i2c, refer to 'Disabling DW_apb_i2c' - - Reset value: 0x0"] +#[doc = "Field `ENABLE` reader - Controls whether the DW_apb_i2c is enabled. - 0: Disables DW_apb_i2c (TX and RX FIFOs are held in an erased state) - 1: Enables DW_apb_i2c Software can disable DW_apb_i2c while it is active. However, it is important that care be taken to ensure that DW_apb_i2c is disabled properly. A recommended procedure is described in 'Disabling DW_apb_i2c'. When DW_apb_i2c is disabled, the following occurs: - The TX FIFO and RX FIFO get flushed. - Status bits in the IC_INTR_STAT register are still active until DW_apb_i2c goes into IDLE state. If the module is transmitting, it stops as well as deletes the contents of the transmit buffer after the current transfer is complete. If the module is receiving, the DW_apb_i2c stops the current transfer at the end of the current byte and does not acknowledge the transfer. In systems with asynchronous pclk and ic_clk when IC_CLK_TYPE parameter set to asynchronous (1), there is a two ic_clk delay when enabling or disabling the DW_apb_i2c. For a detailed description on how to disable DW_apb_i2c, refer to 'Disabling DW_apb_i2c' Reset value: 0x0"] pub type ENABLE_R = crate::BitReader; impl ENABLE_R { #[doc = "Get enumerated values variant"] @@ -52,13 +40,7 @@ impl ENABLE_R { *self == ENABLE_A::ENABLED } } -#[doc = "Field `ENABLE` writer - Controls whether the DW_apb_i2c is enabled. - 0: Disables DW_apb_i2c (TX and RX FIFOs are held in an erased state) - 1: Enables DW_apb_i2c Software can disable DW_apb_i2c while it is active. However, it is important that care be taken to ensure that DW_apb_i2c is disabled properly. A recommended procedure is described in 'Disabling DW_apb_i2c'. - - When DW_apb_i2c is disabled, the following occurs: - The TX FIFO and RX FIFO get flushed. - Status bits in the IC_INTR_STAT register are still active until DW_apb_i2c goes into IDLE state. If the module is transmitting, it stops as well as deletes the contents of the transmit buffer after the current transfer is complete. If the module is receiving, the DW_apb_i2c stops the current transfer at the end of the current byte and does not acknowledge the transfer. - - In systems with asynchronous pclk and ic_clk when IC_CLK_TYPE parameter set to asynchronous (1), there is a two ic_clk delay when enabling or disabling the DW_apb_i2c. For a detailed description on how to disable DW_apb_i2c, refer to 'Disabling DW_apb_i2c' - - Reset value: 0x0"] +#[doc = "Field `ENABLE` writer - Controls whether the DW_apb_i2c is enabled. - 0: Disables DW_apb_i2c (TX and RX FIFOs are held in an erased state) - 1: Enables DW_apb_i2c Software can disable DW_apb_i2c while it is active. However, it is important that care be taken to ensure that DW_apb_i2c is disabled properly. A recommended procedure is described in 'Disabling DW_apb_i2c'. When DW_apb_i2c is disabled, the following occurs: - The TX FIFO and RX FIFO get flushed. - Status bits in the IC_INTR_STAT register are still active until DW_apb_i2c goes into IDLE state. If the module is transmitting, it stops as well as deletes the contents of the transmit buffer after the current transfer is complete. If the module is receiving, the DW_apb_i2c stops the current transfer at the end of the current byte and does not acknowledge the transfer. In systems with asynchronous pclk and ic_clk when IC_CLK_TYPE parameter set to asynchronous (1), there is a two ic_clk delay when enabling or disabling the DW_apb_i2c. For a detailed description on how to disable DW_apb_i2c, refer to 'Disabling DW_apb_i2c' Reset value: 0x0"] pub type ENABLE_W<'a, REG> = crate::BitWriter<'a, REG, ENABLE_A>; impl<'a, REG> ENABLE_W<'a, REG> where @@ -75,11 +57,7 @@ where self.variant(ENABLE_A::ENABLED) } } -#[doc = "When set, the controller initiates the transfer abort. - 0: ABORT not initiated or ABORT done - 1: ABORT operation in progress The software can abort the I2C transfer in master mode by setting this bit. The software can set this bit only when ENABLE is already set; otherwise, the controller ignores any write to ABORT bit. The software cannot clear the ABORT bit once set. In response to an ABORT, the controller issues a STOP and flushes the Tx FIFO after completing the current transfer, then sets the TX_ABORT interrupt after the abort operation. The ABORT bit is cleared automatically after the abort operation. - - For a detailed description on how to abort I2C transfers, refer to 'Aborting I2C Transfers'. - - Reset value: 0x0 +#[doc = "When set, the controller initiates the transfer abort. - 0: ABORT not initiated or ABORT done - 1: ABORT operation in progress The software can abort the I2C transfer in master mode by setting this bit. The software can set this bit only when ENABLE is already set; otherwise, the controller ignores any write to ABORT bit. The software cannot clear the ABORT bit once set. In response to an ABORT, the controller issues a STOP and flushes the Tx FIFO after completing the current transfer, then sets the TX_ABORT interrupt after the abort operation. The ABORT bit is cleared automatically after the abort operation. For a detailed description on how to abort I2C transfers, refer to 'Aborting I2C Transfers'. Reset value: 0x0 Value on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -95,11 +73,7 @@ impl From for bool { variant as u8 != 0 } } -#[doc = "Field `ABORT` reader - When set, the controller initiates the transfer abort. - 0: ABORT not initiated or ABORT done - 1: ABORT operation in progress The software can abort the I2C transfer in master mode by setting this bit. The software can set this bit only when ENABLE is already set; otherwise, the controller ignores any write to ABORT bit. The software cannot clear the ABORT bit once set. In response to an ABORT, the controller issues a STOP and flushes the Tx FIFO after completing the current transfer, then sets the TX_ABORT interrupt after the abort operation. The ABORT bit is cleared automatically after the abort operation. - - For a detailed description on how to abort I2C transfers, refer to 'Aborting I2C Transfers'. - - Reset value: 0x0"] +#[doc = "Field `ABORT` reader - When set, the controller initiates the transfer abort. - 0: ABORT not initiated or ABORT done - 1: ABORT operation in progress The software can abort the I2C transfer in master mode by setting this bit. The software can set this bit only when ENABLE is already set; otherwise, the controller ignores any write to ABORT bit. The software cannot clear the ABORT bit once set. In response to an ABORT, the controller issues a STOP and flushes the Tx FIFO after completing the current transfer, then sets the TX_ABORT interrupt after the abort operation. The ABORT bit is cleared automatically after the abort operation. For a detailed description on how to abort I2C transfers, refer to 'Aborting I2C Transfers'. Reset value: 0x0"] pub type ABORT_R = crate::BitReader; impl ABORT_R { #[doc = "Get enumerated values variant"] @@ -121,11 +95,7 @@ impl ABORT_R { *self == ABORT_A::ENABLED } } -#[doc = "Field `ABORT` writer - When set, the controller initiates the transfer abort. - 0: ABORT not initiated or ABORT done - 1: ABORT operation in progress The software can abort the I2C transfer in master mode by setting this bit. The software can set this bit only when ENABLE is already set; otherwise, the controller ignores any write to ABORT bit. The software cannot clear the ABORT bit once set. In response to an ABORT, the controller issues a STOP and flushes the Tx FIFO after completing the current transfer, then sets the TX_ABORT interrupt after the abort operation. The ABORT bit is cleared automatically after the abort operation. - - For a detailed description on how to abort I2C transfers, refer to 'Aborting I2C Transfers'. - - Reset value: 0x0"] +#[doc = "Field `ABORT` writer - When set, the controller initiates the transfer abort. - 0: ABORT not initiated or ABORT done - 1: ABORT operation in progress The software can abort the I2C transfer in master mode by setting this bit. The software can set this bit only when ENABLE is already set; otherwise, the controller ignores any write to ABORT bit. The software cannot clear the ABORT bit once set. In response to an ABORT, the controller issues a STOP and flushes the Tx FIFO after completing the current transfer, then sets the TX_ABORT interrupt after the abort operation. The ABORT bit is cleared automatically after the abort operation. For a detailed description on how to abort I2C transfers, refer to 'Aborting I2C Transfers'. Reset value: 0x0"] pub type ABORT_W<'a, REG> = crate::BitWriter<'a, REG, ABORT_A>; impl<'a, REG> ABORT_W<'a, REG> where @@ -201,22 +171,12 @@ where } } impl R { - #[doc = "Bit 0 - Controls whether the DW_apb_i2c is enabled. - 0: Disables DW_apb_i2c (TX and RX FIFOs are held in an erased state) - 1: Enables DW_apb_i2c Software can disable DW_apb_i2c while it is active. However, it is important that care be taken to ensure that DW_apb_i2c is disabled properly. A recommended procedure is described in 'Disabling DW_apb_i2c'. - - When DW_apb_i2c is disabled, the following occurs: - The TX FIFO and RX FIFO get flushed. - Status bits in the IC_INTR_STAT register are still active until DW_apb_i2c goes into IDLE state. If the module is transmitting, it stops as well as deletes the contents of the transmit buffer after the current transfer is complete. If the module is receiving, the DW_apb_i2c stops the current transfer at the end of the current byte and does not acknowledge the transfer. - - In systems with asynchronous pclk and ic_clk when IC_CLK_TYPE parameter set to asynchronous (1), there is a two ic_clk delay when enabling or disabling the DW_apb_i2c. For a detailed description on how to disable DW_apb_i2c, refer to 'Disabling DW_apb_i2c' - - Reset value: 0x0"] + #[doc = "Bit 0 - Controls whether the DW_apb_i2c is enabled. - 0: Disables DW_apb_i2c (TX and RX FIFOs are held in an erased state) - 1: Enables DW_apb_i2c Software can disable DW_apb_i2c while it is active. However, it is important that care be taken to ensure that DW_apb_i2c is disabled properly. A recommended procedure is described in 'Disabling DW_apb_i2c'. When DW_apb_i2c is disabled, the following occurs: - The TX FIFO and RX FIFO get flushed. - Status bits in the IC_INTR_STAT register are still active until DW_apb_i2c goes into IDLE state. If the module is transmitting, it stops as well as deletes the contents of the transmit buffer after the current transfer is complete. If the module is receiving, the DW_apb_i2c stops the current transfer at the end of the current byte and does not acknowledge the transfer. In systems with asynchronous pclk and ic_clk when IC_CLK_TYPE parameter set to asynchronous (1), there is a two ic_clk delay when enabling or disabling the DW_apb_i2c. For a detailed description on how to disable DW_apb_i2c, refer to 'Disabling DW_apb_i2c' Reset value: 0x0"] #[inline(always)] pub fn enable(&self) -> ENABLE_R { ENABLE_R::new((self.bits & 1) != 0) } - #[doc = "Bit 1 - When set, the controller initiates the transfer abort. - 0: ABORT not initiated or ABORT done - 1: ABORT operation in progress The software can abort the I2C transfer in master mode by setting this bit. The software can set this bit only when ENABLE is already set; otherwise, the controller ignores any write to ABORT bit. The software cannot clear the ABORT bit once set. In response to an ABORT, the controller issues a STOP and flushes the Tx FIFO after completing the current transfer, then sets the TX_ABORT interrupt after the abort operation. The ABORT bit is cleared automatically after the abort operation. - - For a detailed description on how to abort I2C transfers, refer to 'Aborting I2C Transfers'. - - Reset value: 0x0"] + #[doc = "Bit 1 - When set, the controller initiates the transfer abort. - 0: ABORT not initiated or ABORT done - 1: ABORT operation in progress The software can abort the I2C transfer in master mode by setting this bit. The software can set this bit only when ENABLE is already set; otherwise, the controller ignores any write to ABORT bit. The software cannot clear the ABORT bit once set. In response to an ABORT, the controller issues a STOP and flushes the Tx FIFO after completing the current transfer, then sets the TX_ABORT interrupt after the abort operation. The ABORT bit is cleared automatically after the abort operation. For a detailed description on how to abort I2C transfers, refer to 'Aborting I2C Transfers'. Reset value: 0x0"] #[inline(always)] pub fn abort(&self) -> ABORT_R { ABORT_R::new(((self.bits >> 1) & 1) != 0) @@ -229,23 +189,13 @@ impl R { } } impl W { - #[doc = "Bit 0 - Controls whether the DW_apb_i2c is enabled. - 0: Disables DW_apb_i2c (TX and RX FIFOs are held in an erased state) - 1: Enables DW_apb_i2c Software can disable DW_apb_i2c while it is active. However, it is important that care be taken to ensure that DW_apb_i2c is disabled properly. A recommended procedure is described in 'Disabling DW_apb_i2c'. - - When DW_apb_i2c is disabled, the following occurs: - The TX FIFO and RX FIFO get flushed. - Status bits in the IC_INTR_STAT register are still active until DW_apb_i2c goes into IDLE state. If the module is transmitting, it stops as well as deletes the contents of the transmit buffer after the current transfer is complete. If the module is receiving, the DW_apb_i2c stops the current transfer at the end of the current byte and does not acknowledge the transfer. - - In systems with asynchronous pclk and ic_clk when IC_CLK_TYPE parameter set to asynchronous (1), there is a two ic_clk delay when enabling or disabling the DW_apb_i2c. For a detailed description on how to disable DW_apb_i2c, refer to 'Disabling DW_apb_i2c' - - Reset value: 0x0"] + #[doc = "Bit 0 - Controls whether the DW_apb_i2c is enabled. - 0: Disables DW_apb_i2c (TX and RX FIFOs are held in an erased state) - 1: Enables DW_apb_i2c Software can disable DW_apb_i2c while it is active. However, it is important that care be taken to ensure that DW_apb_i2c is disabled properly. A recommended procedure is described in 'Disabling DW_apb_i2c'. When DW_apb_i2c is disabled, the following occurs: - The TX FIFO and RX FIFO get flushed. - Status bits in the IC_INTR_STAT register are still active until DW_apb_i2c goes into IDLE state. If the module is transmitting, it stops as well as deletes the contents of the transmit buffer after the current transfer is complete. If the module is receiving, the DW_apb_i2c stops the current transfer at the end of the current byte and does not acknowledge the transfer. In systems with asynchronous pclk and ic_clk when IC_CLK_TYPE parameter set to asynchronous (1), there is a two ic_clk delay when enabling or disabling the DW_apb_i2c. For a detailed description on how to disable DW_apb_i2c, refer to 'Disabling DW_apb_i2c' Reset value: 0x0"] #[inline(always)] #[must_use] pub fn enable(&mut self) -> ENABLE_W { ENABLE_W::new(self, 0) } - #[doc = "Bit 1 - When set, the controller initiates the transfer abort. - 0: ABORT not initiated or ABORT done - 1: ABORT operation in progress The software can abort the I2C transfer in master mode by setting this bit. The software can set this bit only when ENABLE is already set; otherwise, the controller ignores any write to ABORT bit. The software cannot clear the ABORT bit once set. In response to an ABORT, the controller issues a STOP and flushes the Tx FIFO after completing the current transfer, then sets the TX_ABORT interrupt after the abort operation. The ABORT bit is cleared automatically after the abort operation. - - For a detailed description on how to abort I2C transfers, refer to 'Aborting I2C Transfers'. - - Reset value: 0x0"] + #[doc = "Bit 1 - When set, the controller initiates the transfer abort. - 0: ABORT not initiated or ABORT done - 1: ABORT operation in progress The software can abort the I2C transfer in master mode by setting this bit. The software can set this bit only when ENABLE is already set; otherwise, the controller ignores any write to ABORT bit. The software cannot clear the ABORT bit once set. In response to an ABORT, the controller issues a STOP and flushes the Tx FIFO after completing the current transfer, then sets the TX_ABORT interrupt after the abort operation. The ABORT bit is cleared automatically after the abort operation. For a detailed description on how to abort I2C transfers, refer to 'Aborting I2C Transfers'. Reset value: 0x0"] #[inline(always)] #[must_use] pub fn abort(&mut self) -> ABORT_W { diff --git a/src/i2c0/ic_enable_status.rs b/src/i2c0/ic_enable_status.rs index b431554b3..dd695301c 100644 --- a/src/i2c0/ic_enable_status.rs +++ b/src/i2c0/ic_enable_status.rs @@ -1,8 +1,8 @@ #[doc = "Register `IC_ENABLE_STATUS` reader"] pub type R = crate::R; -#[doc = "ic_en Status. This bit always reflects the value driven on the output port ic_en. - When read as 1, DW_apb_i2c is deemed to be in an enabled state. - When read as 0, DW_apb_i2c is deemed completely inactive. Note: The CPU can safely read this bit anytime. When this bit is read as 0, the CPU can safely read SLV_RX_DATA_LOST (bit 2) and SLV_DISABLED_WHILE_BUSY (bit 1). - - Reset value: 0x0 +#[doc = "Register `IC_ENABLE_STATUS` writer"] +pub type W = crate::W; +#[doc = "ic_en Status. This bit always reflects the value driven on the output port ic_en. - When read as 1, DW_apb_i2c is deemed to be in an enabled state. - When read as 0, DW_apb_i2c is deemed completely inactive. Note: The CPU can safely read this bit anytime. When this bit is read as 0, the CPU can safely read SLV_RX_DATA_LOST (bit 2) and SLV_DISABLED_WHILE_BUSY (bit 1). Reset value: 0x0 Value on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -18,9 +18,7 @@ impl From for bool { variant as u8 != 0 } } -#[doc = "Field `IC_EN` reader - ic_en Status. This bit always reflects the value driven on the output port ic_en. - When read as 1, DW_apb_i2c is deemed to be in an enabled state. - When read as 0, DW_apb_i2c is deemed completely inactive. Note: The CPU can safely read this bit anytime. When this bit is read as 0, the CPU can safely read SLV_RX_DATA_LOST (bit 2) and SLV_DISABLED_WHILE_BUSY (bit 1). - - Reset value: 0x0"] +#[doc = "Field `IC_EN` reader - ic_en Status. This bit always reflects the value driven on the output port ic_en. - When read as 1, DW_apb_i2c is deemed to be in an enabled state. - When read as 0, DW_apb_i2c is deemed completely inactive. Note: The CPU can safely read this bit anytime. When this bit is read as 0, the CPU can safely read SLV_RX_DATA_LOST (bit 2) and SLV_DISABLED_WHILE_BUSY (bit 1). Reset value: 0x0"] pub type IC_EN_R = crate::BitReader; impl IC_EN_R { #[doc = "Get enumerated values variant"] @@ -42,24 +40,8 @@ impl IC_EN_R { *self == IC_EN_A::ENABLED } } -#[doc = "Slave Disabled While Busy (Transmit, Receive). This bit indicates if a potential or active Slave operation has been aborted due to the setting bit 0 of the IC_ENABLE register from 1 to 0. This bit is set when the CPU writes a 0 to the IC_ENABLE register while: - - (a) DW_apb_i2c is receiving the address byte of the Slave-Transmitter operation from a remote master; - - OR, - - (b) address and data bytes of the Slave-Receiver operation from a remote master. - - When read as 1, DW_apb_i2c is deemed to have forced a NACK during any part of an I2C transfer, irrespective of whether the I2C address matches the slave address set in DW_apb_i2c (IC_SAR register) OR if the transfer is completed before IC_ENABLE is set to 0 but has not taken effect. - - Note: If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE\\[0\\] -has been set to 0, then this bit will also be set to 1. - - When read as 0, DW_apb_i2c is deemed to have been disabled when there is master activity, or when the I2C bus is idle. - - Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0. - - Reset value: 0x0 +#[doc = "Slave Disabled While Busy (Transmit, Receive). This bit indicates if a potential or active Slave operation has been aborted due to the setting bit 0 of the IC_ENABLE register from 1 to 0. This bit is set when the CPU writes a 0 to the IC_ENABLE register while: (a) DW_apb_i2c is receiving the address byte of the Slave-Transmitter operation from a remote master; OR, (b) address and data bytes of the Slave-Receiver operation from a remote master. When read as 1, DW_apb_i2c is deemed to have forced a NACK during any part of an I2C transfer, irrespective of whether the I2C address matches the slave address set in DW_apb_i2c (IC_SAR register) OR if the transfer is completed before IC_ENABLE is set to 0 but has not taken effect. Note: If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE\\[0\\] +has been set to 0, then this bit will also be set to 1. When read as 0, DW_apb_i2c is deemed to have been disabled when there is master activity, or when the I2C bus is idle. Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0. Reset value: 0x0 Value on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -75,24 +57,8 @@ impl From for bool { variant as u8 != 0 } } -#[doc = "Field `SLV_DISABLED_WHILE_BUSY` reader - Slave Disabled While Busy (Transmit, Receive). This bit indicates if a potential or active Slave operation has been aborted due to the setting bit 0 of the IC_ENABLE register from 1 to 0. This bit is set when the CPU writes a 0 to the IC_ENABLE register while: - - (a) DW_apb_i2c is receiving the address byte of the Slave-Transmitter operation from a remote master; - - OR, - - (b) address and data bytes of the Slave-Receiver operation from a remote master. - - When read as 1, DW_apb_i2c is deemed to have forced a NACK during any part of an I2C transfer, irrespective of whether the I2C address matches the slave address set in DW_apb_i2c (IC_SAR register) OR if the transfer is completed before IC_ENABLE is set to 0 but has not taken effect. - - Note: If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE\\[0\\] -has been set to 0, then this bit will also be set to 1. - - When read as 0, DW_apb_i2c is deemed to have been disabled when there is master activity, or when the I2C bus is idle. - - Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0. - - Reset value: 0x0"] +#[doc = "Field `SLV_DISABLED_WHILE_BUSY` reader - Slave Disabled While Busy (Transmit, Receive). This bit indicates if a potential or active Slave operation has been aborted due to the setting bit 0 of the IC_ENABLE register from 1 to 0. This bit is set when the CPU writes a 0 to the IC_ENABLE register while: (a) DW_apb_i2c is receiving the address byte of the Slave-Transmitter operation from a remote master; OR, (b) address and data bytes of the Slave-Receiver operation from a remote master. When read as 1, DW_apb_i2c is deemed to have forced a NACK during any part of an I2C transfer, irrespective of whether the I2C address matches the slave address set in DW_apb_i2c (IC_SAR register) OR if the transfer is completed before IC_ENABLE is set to 0 but has not taken effect. Note: If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE\\[0\\] +has been set to 0, then this bit will also be set to 1. When read as 0, DW_apb_i2c is deemed to have been disabled when there is master activity, or when the I2C bus is idle. Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0. Reset value: 0x0"] pub type SLV_DISABLED_WHILE_BUSY_R = crate::BitReader; impl SLV_DISABLED_WHILE_BUSY_R { #[doc = "Get enumerated values variant"] @@ -114,16 +80,8 @@ impl SLV_DISABLED_WHILE_BUSY_R { *self == SLV_DISABLED_WHILE_BUSY_A::ACTIVE } } -#[doc = "Slave Received Data Lost. This bit indicates if a Slave-Receiver operation has been aborted with at least one data byte received from an I2C transfer due to the setting bit 0 of IC_ENABLE from 1 to 0. When read as 1, DW_apb_i2c is deemed to have been actively engaged in an aborted I2C transfer (with matching address) and the data phase of the I2C transfer has been entered, even though a data byte has been responded with a NACK. - - Note: If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE\\[0\\] -has been set to 0, then this bit is also set to 1. - - When read as 0, DW_apb_i2c is deemed to have been disabled without being actively involved in the data phase of a Slave-Receiver transfer. - - Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0. - - Reset value: 0x0 +#[doc = "Slave Received Data Lost. This bit indicates if a Slave-Receiver operation has been aborted with at least one data byte received from an I2C transfer due to the setting bit 0 of IC_ENABLE from 1 to 0. When read as 1, DW_apb_i2c is deemed to have been actively engaged in an aborted I2C transfer (with matching address) and the data phase of the I2C transfer has been entered, even though a data byte has been responded with a NACK. Note: If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE\\[0\\] +has been set to 0, then this bit is also set to 1. When read as 0, DW_apb_i2c is deemed to have been disabled without being actively involved in the data phase of a Slave-Receiver transfer. Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0. Reset value: 0x0 Value on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -139,16 +97,8 @@ impl From for bool { variant as u8 != 0 } } -#[doc = "Field `SLV_RX_DATA_LOST` reader - Slave Received Data Lost. This bit indicates if a Slave-Receiver operation has been aborted with at least one data byte received from an I2C transfer due to the setting bit 0 of IC_ENABLE from 1 to 0. When read as 1, DW_apb_i2c is deemed to have been actively engaged in an aborted I2C transfer (with matching address) and the data phase of the I2C transfer has been entered, even though a data byte has been responded with a NACK. - - Note: If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE\\[0\\] -has been set to 0, then this bit is also set to 1. - - When read as 0, DW_apb_i2c is deemed to have been disabled without being actively involved in the data phase of a Slave-Receiver transfer. - - Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0. - - Reset value: 0x0"] +#[doc = "Field `SLV_RX_DATA_LOST` reader - Slave Received Data Lost. This bit indicates if a Slave-Receiver operation has been aborted with at least one data byte received from an I2C transfer due to the setting bit 0 of IC_ENABLE from 1 to 0. When read as 1, DW_apb_i2c is deemed to have been actively engaged in an aborted I2C transfer (with matching address) and the data phase of the I2C transfer has been entered, even though a data byte has been responded with a NACK. Note: If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE\\[0\\] +has been set to 0, then this bit is also set to 1. When read as 0, DW_apb_i2c is deemed to have been disabled without being actively involved in the data phase of a Slave-Receiver transfer. Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0. Reset value: 0x0"] pub type SLV_RX_DATA_LOST_R = crate::BitReader; impl SLV_RX_DATA_LOST_R { #[doc = "Get enumerated values variant"] @@ -171,71 +121,44 @@ impl SLV_RX_DATA_LOST_R { } } impl R { - #[doc = "Bit 0 - ic_en Status. This bit always reflects the value driven on the output port ic_en. - When read as 1, DW_apb_i2c is deemed to be in an enabled state. - When read as 0, DW_apb_i2c is deemed completely inactive. Note: The CPU can safely read this bit anytime. When this bit is read as 0, the CPU can safely read SLV_RX_DATA_LOST (bit 2) and SLV_DISABLED_WHILE_BUSY (bit 1). - - Reset value: 0x0"] + #[doc = "Bit 0 - ic_en Status. This bit always reflects the value driven on the output port ic_en. - When read as 1, DW_apb_i2c is deemed to be in an enabled state. - When read as 0, DW_apb_i2c is deemed completely inactive. Note: The CPU can safely read this bit anytime. When this bit is read as 0, the CPU can safely read SLV_RX_DATA_LOST (bit 2) and SLV_DISABLED_WHILE_BUSY (bit 1). Reset value: 0x0"] #[inline(always)] pub fn ic_en(&self) -> IC_EN_R { IC_EN_R::new((self.bits & 1) != 0) } - #[doc = "Bit 1 - Slave Disabled While Busy (Transmit, Receive). This bit indicates if a potential or active Slave operation has been aborted due to the setting bit 0 of the IC_ENABLE register from 1 to 0. This bit is set when the CPU writes a 0 to the IC_ENABLE register while: - - (a) DW_apb_i2c is receiving the address byte of the Slave-Transmitter operation from a remote master; - - OR, - - (b) address and data bytes of the Slave-Receiver operation from a remote master. - - When read as 1, DW_apb_i2c is deemed to have forced a NACK during any part of an I2C transfer, irrespective of whether the I2C address matches the slave address set in DW_apb_i2c (IC_SAR register) OR if the transfer is completed before IC_ENABLE is set to 0 but has not taken effect. - - Note: If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE\\[0\\] -has been set to 0, then this bit will also be set to 1. - - When read as 0, DW_apb_i2c is deemed to have been disabled when there is master activity, or when the I2C bus is idle. - - Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0. - - Reset value: 0x0"] + #[doc = "Bit 1 - Slave Disabled While Busy (Transmit, Receive). This bit indicates if a potential or active Slave operation has been aborted due to the setting bit 0 of the IC_ENABLE register from 1 to 0. This bit is set when the CPU writes a 0 to the IC_ENABLE register while: (a) DW_apb_i2c is receiving the address byte of the Slave-Transmitter operation from a remote master; OR, (b) address and data bytes of the Slave-Receiver operation from a remote master. When read as 1, DW_apb_i2c is deemed to have forced a NACK during any part of an I2C transfer, irrespective of whether the I2C address matches the slave address set in DW_apb_i2c (IC_SAR register) OR if the transfer is completed before IC_ENABLE is set to 0 but has not taken effect. Note: If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE\\[0\\] +has been set to 0, then this bit will also be set to 1. When read as 0, DW_apb_i2c is deemed to have been disabled when there is master activity, or when the I2C bus is idle. Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0. Reset value: 0x0"] #[inline(always)] pub fn slv_disabled_while_busy(&self) -> SLV_DISABLED_WHILE_BUSY_R { SLV_DISABLED_WHILE_BUSY_R::new(((self.bits >> 1) & 1) != 0) } - #[doc = "Bit 2 - Slave Received Data Lost. This bit indicates if a Slave-Receiver operation has been aborted with at least one data byte received from an I2C transfer due to the setting bit 0 of IC_ENABLE from 1 to 0. When read as 1, DW_apb_i2c is deemed to have been actively engaged in an aborted I2C transfer (with matching address) and the data phase of the I2C transfer has been entered, even though a data byte has been responded with a NACK. - - Note: If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE\\[0\\] -has been set to 0, then this bit is also set to 1. - - When read as 0, DW_apb_i2c is deemed to have been disabled without being actively involved in the data phase of a Slave-Receiver transfer. - - Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0. - - Reset value: 0x0"] + #[doc = "Bit 2 - Slave Received Data Lost. This bit indicates if a Slave-Receiver operation has been aborted with at least one data byte received from an I2C transfer due to the setting bit 0 of IC_ENABLE from 1 to 0. When read as 1, DW_apb_i2c is deemed to have been actively engaged in an aborted I2C transfer (with matching address) and the data phase of the I2C transfer has been entered, even though a data byte has been responded with a NACK. Note: If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE\\[0\\] +has been set to 0, then this bit is also set to 1. When read as 0, DW_apb_i2c is deemed to have been disabled without being actively involved in the data phase of a Slave-Receiver transfer. Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0. Reset value: 0x0"] #[inline(always)] pub fn slv_rx_data_lost(&self) -> SLV_RX_DATA_LOST_R { SLV_RX_DATA_LOST_R::new(((self.bits >> 2) & 1) != 0) } } -#[doc = "I2C Enable Status Register - - The register is used to report the DW_apb_i2c hardware status when the IC_ENABLE\\[0\\] -register is set from 1 to 0; that is, when DW_apb_i2c is disabled. - - If IC_ENABLE\\[0\\] -has been set to 1, bits 2:1 are forced to 0, and bit 0 is forced to 1. - - If IC_ENABLE\\[0\\] -has been set to 0, bits 2:1 is only be valid as soon as bit 0 is read as '0'. - - Note: When IC_ENABLE\\[0\\] +impl W {} +#[doc = "I2C Enable Status Register The register is used to report the DW_apb_i2c hardware status when the IC_ENABLE\\[0\\] +register is set from 1 to 0; that is, when DW_apb_i2c is disabled. If IC_ENABLE\\[0\\] +has been set to 1, bits 2:1 are forced to 0, and bit 0 is forced to 1. If IC_ENABLE\\[0\\] +has been set to 0, bits 2:1 is only be valid as soon as bit 0 is read as '0'. Note: When IC_ENABLE\\[0\\] has been set to 0, a delay occurs for bit 0 to be read as 0 because disabling the DW_apb_i2c depends on I2C bus activities. -You can [`read`](crate::generic::Reg::read) this register and get [`ic_enable_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`ic_enable_status::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_enable_status::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IC_ENABLE_STATUS_SPEC; impl crate::RegisterSpec for IC_ENABLE_STATUS_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`ic_enable_status::R`](R) reader structure"] impl crate::Readable for IC_ENABLE_STATUS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ic_enable_status::W`](W) writer structure"] +impl crate::Writable for IC_ENABLE_STATUS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets IC_ENABLE_STATUS to value 0"] impl crate::Resettable for IC_ENABLE_STATUS_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/i2c0/ic_fs_scl_hcnt.rs b/src/i2c0/ic_fs_scl_hcnt.rs index 85d134b2d..01f94f203 100644 --- a/src/i2c0/ic_fs_scl_hcnt.rs +++ b/src/i2c0/ic_fs_scl_hcnt.rs @@ -2,39 +2,23 @@ pub type R = crate::R; #[doc = "Register `IC_FS_SCL_HCNT` writer"] pub type W = crate::W; -#[doc = "Field `IC_FS_SCL_HCNT` reader - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for fast mode or fast mode plus. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'. - - This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE\\[0\\] -register being set to 0. Writes at other times have no effect. - - The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH == 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed."] +#[doc = "Field `IC_FS_SCL_HCNT` reader - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for fast mode or fast mode plus. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'. This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE\\[0\\] +register being set to 0. Writes at other times have no effect. The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH == 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed."] pub type IC_FS_SCL_HCNT_R = crate::FieldReader; -#[doc = "Field `IC_FS_SCL_HCNT` writer - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for fast mode or fast mode plus. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'. - - This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE\\[0\\] -register being set to 0. Writes at other times have no effect. - - The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH == 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed."] +#[doc = "Field `IC_FS_SCL_HCNT` writer - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for fast mode or fast mode plus. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'. This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE\\[0\\] +register being set to 0. Writes at other times have no effect. The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH == 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed."] pub type IC_FS_SCL_HCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; impl R { - #[doc = "Bits 0:15 - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for fast mode or fast mode plus. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'. - - This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE\\[0\\] -register being set to 0. Writes at other times have no effect. - - The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH == 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed."] + #[doc = "Bits 0:15 - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for fast mode or fast mode plus. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'. This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE\\[0\\] +register being set to 0. Writes at other times have no effect. The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH == 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed."] #[inline(always)] pub fn ic_fs_scl_hcnt(&self) -> IC_FS_SCL_HCNT_R { IC_FS_SCL_HCNT_R::new((self.bits & 0xffff) as u16) } } impl W { - #[doc = "Bits 0:15 - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for fast mode or fast mode plus. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'. - - This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE\\[0\\] -register being set to 0. Writes at other times have no effect. - - The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH == 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed."] + #[doc = "Bits 0:15 - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for fast mode or fast mode plus. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'. This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE\\[0\\] +register being set to 0. Writes at other times have no effect. The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH == 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed."] #[inline(always)] #[must_use] pub fn ic_fs_scl_hcnt(&mut self) -> IC_FS_SCL_HCNT_W { diff --git a/src/i2c0/ic_fs_scl_lcnt.rs b/src/i2c0/ic_fs_scl_lcnt.rs index 046f1eb3a..086bf1b4e 100644 --- a/src/i2c0/ic_fs_scl_lcnt.rs +++ b/src/i2c0/ic_fs_scl_lcnt.rs @@ -2,47 +2,23 @@ pub type R = crate::R; #[doc = "Register `IC_FS_SCL_LCNT` writer"] pub type W = crate::W; -#[doc = "Field `IC_FS_SCL_LCNT` reader - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for fast speed. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'. - - This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard. - - This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE\\[0\\] -register being set to 0. Writes at other times have no effect. - - The minimum valid value is 8; hardware prevents values less than this being written, and if attempted results in 8 being set. For designs with APB_DATA_WIDTH = 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. If the value is less than 8 then the count value gets changed to 8."] +#[doc = "Field `IC_FS_SCL_LCNT` reader - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for fast speed. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'. This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE\\[0\\] +register being set to 0. Writes at other times have no effect. The minimum valid value is 8; hardware prevents values less than this being written, and if attempted results in 8 being set. For designs with APB_DATA_WIDTH = 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. If the value is less than 8 then the count value gets changed to 8."] pub type IC_FS_SCL_LCNT_R = crate::FieldReader; -#[doc = "Field `IC_FS_SCL_LCNT` writer - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for fast speed. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'. - - This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard. - - This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE\\[0\\] -register being set to 0. Writes at other times have no effect. - - The minimum valid value is 8; hardware prevents values less than this being written, and if attempted results in 8 being set. For designs with APB_DATA_WIDTH = 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. If the value is less than 8 then the count value gets changed to 8."] +#[doc = "Field `IC_FS_SCL_LCNT` writer - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for fast speed. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'. This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE\\[0\\] +register being set to 0. Writes at other times have no effect. The minimum valid value is 8; hardware prevents values less than this being written, and if attempted results in 8 being set. For designs with APB_DATA_WIDTH = 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. If the value is less than 8 then the count value gets changed to 8."] pub type IC_FS_SCL_LCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; impl R { - #[doc = "Bits 0:15 - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for fast speed. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'. - - This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard. - - This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE\\[0\\] -register being set to 0. Writes at other times have no effect. - - The minimum valid value is 8; hardware prevents values less than this being written, and if attempted results in 8 being set. For designs with APB_DATA_WIDTH = 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. If the value is less than 8 then the count value gets changed to 8."] + #[doc = "Bits 0:15 - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for fast speed. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'. This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE\\[0\\] +register being set to 0. Writes at other times have no effect. The minimum valid value is 8; hardware prevents values less than this being written, and if attempted results in 8 being set. For designs with APB_DATA_WIDTH = 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. If the value is less than 8 then the count value gets changed to 8."] #[inline(always)] pub fn ic_fs_scl_lcnt(&self) -> IC_FS_SCL_LCNT_R { IC_FS_SCL_LCNT_R::new((self.bits & 0xffff) as u16) } } impl W { - #[doc = "Bits 0:15 - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for fast speed. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'. - - This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard. - - This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE\\[0\\] -register being set to 0. Writes at other times have no effect. - - The minimum valid value is 8; hardware prevents values less than this being written, and if attempted results in 8 being set. For designs with APB_DATA_WIDTH = 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. If the value is less than 8 then the count value gets changed to 8."] + #[doc = "Bits 0:15 - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for fast speed. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'. This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE\\[0\\] +register being set to 0. Writes at other times have no effect. The minimum valid value is 8; hardware prevents values less than this being written, and if attempted results in 8 being set. For designs with APB_DATA_WIDTH = 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. If the value is less than 8 then the count value gets changed to 8."] #[inline(always)] #[must_use] pub fn ic_fs_scl_lcnt(&mut self) -> IC_FS_SCL_LCNT_W { diff --git a/src/i2c0/ic_fs_spklen.rs b/src/i2c0/ic_fs_spklen.rs index 59d99b468..1e8fc40f6 100644 --- a/src/i2c0/ic_fs_spklen.rs +++ b/src/i2c0/ic_fs_spklen.rs @@ -25,9 +25,7 @@ register being set to 0. Writes at other times have no effect. The minimum valid IC_FS_SPKLEN_W::new(self, 0) } } -#[doc = "I2C SS, FS or FM+ spike suppression limit - - This register is used to store the duration, measured in ic_clk cycles, of the longest spike that is filtered out by the spike suppression logic when the component is operating in SS, FS or FM+ modes. The relevant I2C requirement is tSP (table 4) as detailed in the I2C Bus Specification. This register must be programmed with a minimum value of 1. +#[doc = "I2C SS, FS or FM+ spike suppression limit This register is used to store the duration, measured in ic_clk cycles, of the longest spike that is filtered out by the spike suppression logic when the component is operating in SS, FS or FM+ modes. The relevant I2C requirement is tSP (table 4) as detailed in the I2C Bus Specification. This register must be programmed with a minimum value of 1. You can [`read`](crate::generic::Reg::read) this register and get [`ic_fs_spklen::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_fs_spklen::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IC_FS_SPKLEN_SPEC; diff --git a/src/i2c0/ic_intr_mask.rs b/src/i2c0/ic_intr_mask.rs index f2512f11c..553bba56b 100644 --- a/src/i2c0/ic_intr_mask.rs +++ b/src/i2c0/ic_intr_mask.rs @@ -2,9 +2,7 @@ pub type R = crate::R; #[doc = "Register `IC_INTR_MASK` writer"] pub type W = crate::W; -#[doc = "This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register. - - Reset value: 0x1 +#[doc = "This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register. Reset value: 0x1 Value on reset: 1"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -20,9 +18,7 @@ impl From for bool { variant as u8 != 0 } } -#[doc = "Field `M_RX_UNDER` reader - This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register. - - Reset value: 0x1"] +#[doc = "Field `M_RX_UNDER` reader - This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register. Reset value: 0x1"] pub type M_RX_UNDER_R = crate::BitReader; impl M_RX_UNDER_R { #[doc = "Get enumerated values variant"] @@ -44,9 +40,7 @@ impl M_RX_UNDER_R { *self == M_RX_UNDER_A::DISABLED } } -#[doc = "Field `M_RX_UNDER` writer - This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register. - - Reset value: 0x1"] +#[doc = "Field `M_RX_UNDER` writer - This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register. Reset value: 0x1"] pub type M_RX_UNDER_W<'a, REG> = crate::BitWriter<'a, REG, M_RX_UNDER_A>; impl<'a, REG> M_RX_UNDER_W<'a, REG> where @@ -63,9 +57,7 @@ where self.variant(M_RX_UNDER_A::DISABLED) } } -#[doc = "This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register. - - Reset value: 0x1 +#[doc = "This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register. Reset value: 0x1 Value on reset: 1"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -81,9 +73,7 @@ impl From for bool { variant as u8 != 0 } } -#[doc = "Field `M_RX_OVER` reader - This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register. - - Reset value: 0x1"] +#[doc = "Field `M_RX_OVER` reader - This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register. Reset value: 0x1"] pub type M_RX_OVER_R = crate::BitReader; impl M_RX_OVER_R { #[doc = "Get enumerated values variant"] @@ -105,9 +95,7 @@ impl M_RX_OVER_R { *self == M_RX_OVER_A::DISABLED } } -#[doc = "Field `M_RX_OVER` writer - This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register. - - Reset value: 0x1"] +#[doc = "Field `M_RX_OVER` writer - This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register. Reset value: 0x1"] pub type M_RX_OVER_W<'a, REG> = crate::BitWriter<'a, REG, M_RX_OVER_A>; impl<'a, REG> M_RX_OVER_W<'a, REG> where @@ -124,9 +112,7 @@ where self.variant(M_RX_OVER_A::DISABLED) } } -#[doc = "This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register. - - Reset value: 0x1 +#[doc = "This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register. Reset value: 0x1 Value on reset: 1"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -142,9 +128,7 @@ impl From for bool { variant as u8 != 0 } } -#[doc = "Field `M_RX_FULL` reader - This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register. - - Reset value: 0x1"] +#[doc = "Field `M_RX_FULL` reader - This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register. Reset value: 0x1"] pub type M_RX_FULL_R = crate::BitReader; impl M_RX_FULL_R { #[doc = "Get enumerated values variant"] @@ -166,9 +150,7 @@ impl M_RX_FULL_R { *self == M_RX_FULL_A::DISABLED } } -#[doc = "Field `M_RX_FULL` writer - This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register. - - Reset value: 0x1"] +#[doc = "Field `M_RX_FULL` writer - This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register. Reset value: 0x1"] pub type M_RX_FULL_W<'a, REG> = crate::BitWriter<'a, REG, M_RX_FULL_A>; impl<'a, REG> M_RX_FULL_W<'a, REG> where @@ -185,9 +167,7 @@ where self.variant(M_RX_FULL_A::DISABLED) } } -#[doc = "This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register. - - Reset value: 0x1 +#[doc = "This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register. Reset value: 0x1 Value on reset: 1"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -203,9 +183,7 @@ impl From for bool { variant as u8 != 0 } } -#[doc = "Field `M_TX_OVER` reader - This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register. - - Reset value: 0x1"] +#[doc = "Field `M_TX_OVER` reader - This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register. Reset value: 0x1"] pub type M_TX_OVER_R = crate::BitReader; impl M_TX_OVER_R { #[doc = "Get enumerated values variant"] @@ -227,9 +205,7 @@ impl M_TX_OVER_R { *self == M_TX_OVER_A::DISABLED } } -#[doc = "Field `M_TX_OVER` writer - This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register. - - Reset value: 0x1"] +#[doc = "Field `M_TX_OVER` writer - This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register. Reset value: 0x1"] pub type M_TX_OVER_W<'a, REG> = crate::BitWriter<'a, REG, M_TX_OVER_A>; impl<'a, REG> M_TX_OVER_W<'a, REG> where @@ -246,9 +222,7 @@ where self.variant(M_TX_OVER_A::DISABLED) } } -#[doc = "This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register. - - Reset value: 0x1 +#[doc = "This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register. Reset value: 0x1 Value on reset: 1"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -264,9 +238,7 @@ impl From for bool { variant as u8 != 0 } } -#[doc = "Field `M_TX_EMPTY` reader - This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register. - - Reset value: 0x1"] +#[doc = "Field `M_TX_EMPTY` reader - This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register. Reset value: 0x1"] pub type M_TX_EMPTY_R = crate::BitReader; impl M_TX_EMPTY_R { #[doc = "Get enumerated values variant"] @@ -288,9 +260,7 @@ impl M_TX_EMPTY_R { *self == M_TX_EMPTY_A::DISABLED } } -#[doc = "Field `M_TX_EMPTY` writer - This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register. - - Reset value: 0x1"] +#[doc = "Field `M_TX_EMPTY` writer - This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register. Reset value: 0x1"] pub type M_TX_EMPTY_W<'a, REG> = crate::BitWriter<'a, REG, M_TX_EMPTY_A>; impl<'a, REG> M_TX_EMPTY_W<'a, REG> where @@ -307,9 +277,7 @@ where self.variant(M_TX_EMPTY_A::DISABLED) } } -#[doc = "This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register. - - Reset value: 0x1 +#[doc = "This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register. Reset value: 0x1 Value on reset: 1"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -325,9 +293,7 @@ impl From for bool { variant as u8 != 0 } } -#[doc = "Field `M_RD_REQ` reader - This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register. - - Reset value: 0x1"] +#[doc = "Field `M_RD_REQ` reader - This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register. Reset value: 0x1"] pub type M_RD_REQ_R = crate::BitReader; impl M_RD_REQ_R { #[doc = "Get enumerated values variant"] @@ -349,9 +315,7 @@ impl M_RD_REQ_R { *self == M_RD_REQ_A::DISABLED } } -#[doc = "Field `M_RD_REQ` writer - This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register. - - Reset value: 0x1"] +#[doc = "Field `M_RD_REQ` writer - This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register. Reset value: 0x1"] pub type M_RD_REQ_W<'a, REG> = crate::BitWriter<'a, REG, M_RD_REQ_A>; impl<'a, REG> M_RD_REQ_W<'a, REG> where @@ -368,9 +332,7 @@ where self.variant(M_RD_REQ_A::DISABLED) } } -#[doc = "This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register. - - Reset value: 0x1 +#[doc = "This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register. Reset value: 0x1 Value on reset: 1"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -386,9 +348,7 @@ impl From for bool { variant as u8 != 0 } } -#[doc = "Field `M_TX_ABRT` reader - This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register. - - Reset value: 0x1"] +#[doc = "Field `M_TX_ABRT` reader - This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register. Reset value: 0x1"] pub type M_TX_ABRT_R = crate::BitReader; impl M_TX_ABRT_R { #[doc = "Get enumerated values variant"] @@ -410,9 +370,7 @@ impl M_TX_ABRT_R { *self == M_TX_ABRT_A::DISABLED } } -#[doc = "Field `M_TX_ABRT` writer - This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register. - - Reset value: 0x1"] +#[doc = "Field `M_TX_ABRT` writer - This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register. Reset value: 0x1"] pub type M_TX_ABRT_W<'a, REG> = crate::BitWriter<'a, REG, M_TX_ABRT_A>; impl<'a, REG> M_TX_ABRT_W<'a, REG> where @@ -429,9 +387,7 @@ where self.variant(M_TX_ABRT_A::DISABLED) } } -#[doc = "This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register. - - Reset value: 0x1 +#[doc = "This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register. Reset value: 0x1 Value on reset: 1"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -447,9 +403,7 @@ impl From for bool { variant as u8 != 0 } } -#[doc = "Field `M_RX_DONE` reader - This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register. - - Reset value: 0x1"] +#[doc = "Field `M_RX_DONE` reader - This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register. Reset value: 0x1"] pub type M_RX_DONE_R = crate::BitReader; impl M_RX_DONE_R { #[doc = "Get enumerated values variant"] @@ -471,9 +425,7 @@ impl M_RX_DONE_R { *self == M_RX_DONE_A::DISABLED } } -#[doc = "Field `M_RX_DONE` writer - This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register. - - Reset value: 0x1"] +#[doc = "Field `M_RX_DONE` writer - This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register. Reset value: 0x1"] pub type M_RX_DONE_W<'a, REG> = crate::BitWriter<'a, REG, M_RX_DONE_A>; impl<'a, REG> M_RX_DONE_W<'a, REG> where @@ -490,9 +442,7 @@ where self.variant(M_RX_DONE_A::DISABLED) } } -#[doc = "This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register. - - Reset value: 0x0 +#[doc = "This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register. Reset value: 0x0 Value on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -508,9 +458,7 @@ impl From for bool { variant as u8 != 0 } } -#[doc = "Field `M_ACTIVITY` reader - This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register. - - Reset value: 0x0"] +#[doc = "Field `M_ACTIVITY` reader - This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register. Reset value: 0x0"] pub type M_ACTIVITY_R = crate::BitReader; impl M_ACTIVITY_R { #[doc = "Get enumerated values variant"] @@ -532,9 +480,7 @@ impl M_ACTIVITY_R { *self == M_ACTIVITY_A::DISABLED } } -#[doc = "Field `M_ACTIVITY` writer - This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register. - - Reset value: 0x0"] +#[doc = "Field `M_ACTIVITY` writer - This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register. Reset value: 0x0"] pub type M_ACTIVITY_W<'a, REG> = crate::BitWriter<'a, REG, M_ACTIVITY_A>; impl<'a, REG> M_ACTIVITY_W<'a, REG> where @@ -551,9 +497,7 @@ where self.variant(M_ACTIVITY_A::DISABLED) } } -#[doc = "This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register. - - Reset value: 0x0 +#[doc = "This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register. Reset value: 0x0 Value on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -569,9 +513,7 @@ impl From for bool { variant as u8 != 0 } } -#[doc = "Field `M_STOP_DET` reader - This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register. - - Reset value: 0x0"] +#[doc = "Field `M_STOP_DET` reader - This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register. Reset value: 0x0"] pub type M_STOP_DET_R = crate::BitReader; impl M_STOP_DET_R { #[doc = "Get enumerated values variant"] @@ -593,9 +535,7 @@ impl M_STOP_DET_R { *self == M_STOP_DET_A::DISABLED } } -#[doc = "Field `M_STOP_DET` writer - This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register. - - Reset value: 0x0"] +#[doc = "Field `M_STOP_DET` writer - This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register. Reset value: 0x0"] pub type M_STOP_DET_W<'a, REG> = crate::BitWriter<'a, REG, M_STOP_DET_A>; impl<'a, REG> M_STOP_DET_W<'a, REG> where @@ -612,9 +552,7 @@ where self.variant(M_STOP_DET_A::DISABLED) } } -#[doc = "This bit masks the R_START_DET interrupt in IC_INTR_STAT register. - - Reset value: 0x0 +#[doc = "This bit masks the R_START_DET interrupt in IC_INTR_STAT register. Reset value: 0x0 Value on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -630,9 +568,7 @@ impl From for bool { variant as u8 != 0 } } -#[doc = "Field `M_START_DET` reader - This bit masks the R_START_DET interrupt in IC_INTR_STAT register. - - Reset value: 0x0"] +#[doc = "Field `M_START_DET` reader - This bit masks the R_START_DET interrupt in IC_INTR_STAT register. Reset value: 0x0"] pub type M_START_DET_R = crate::BitReader; impl M_START_DET_R { #[doc = "Get enumerated values variant"] @@ -654,9 +590,7 @@ impl M_START_DET_R { *self == M_START_DET_A::DISABLED } } -#[doc = "Field `M_START_DET` writer - This bit masks the R_START_DET interrupt in IC_INTR_STAT register. - - Reset value: 0x0"] +#[doc = "Field `M_START_DET` writer - This bit masks the R_START_DET interrupt in IC_INTR_STAT register. Reset value: 0x0"] pub type M_START_DET_W<'a, REG> = crate::BitWriter<'a, REG, M_START_DET_A>; impl<'a, REG> M_START_DET_W<'a, REG> where @@ -673,9 +607,7 @@ where self.variant(M_START_DET_A::DISABLED) } } -#[doc = "This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register. - - Reset value: 0x1 +#[doc = "This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register. Reset value: 0x1 Value on reset: 1"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -691,9 +623,7 @@ impl From for bool { variant as u8 != 0 } } -#[doc = "Field `M_GEN_CALL` reader - This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register. - - Reset value: 0x1"] +#[doc = "Field `M_GEN_CALL` reader - This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register. Reset value: 0x1"] pub type M_GEN_CALL_R = crate::BitReader; impl M_GEN_CALL_R { #[doc = "Get enumerated values variant"] @@ -715,9 +645,7 @@ impl M_GEN_CALL_R { *self == M_GEN_CALL_A::DISABLED } } -#[doc = "Field `M_GEN_CALL` writer - This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register. - - Reset value: 0x1"] +#[doc = "Field `M_GEN_CALL` writer - This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register. Reset value: 0x1"] pub type M_GEN_CALL_W<'a, REG> = crate::BitWriter<'a, REG, M_GEN_CALL_A>; impl<'a, REG> M_GEN_CALL_W<'a, REG> where @@ -734,9 +662,7 @@ where self.variant(M_GEN_CALL_A::DISABLED) } } -#[doc = "This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register. - - Reset value: 0x0 +#[doc = "This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register. Reset value: 0x0 Value on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -752,9 +678,7 @@ impl From for bool { variant as u8 != 0 } } -#[doc = "Field `M_RESTART_DET` reader - This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register. - - Reset value: 0x0"] +#[doc = "Field `M_RESTART_DET` reader - This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register. Reset value: 0x0"] pub type M_RESTART_DET_R = crate::BitReader; impl M_RESTART_DET_R { #[doc = "Get enumerated values variant"] @@ -776,9 +700,7 @@ impl M_RESTART_DET_R { *self == M_RESTART_DET_A::DISABLED } } -#[doc = "Field `M_RESTART_DET` writer - This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register. - - Reset value: 0x0"] +#[doc = "Field `M_RESTART_DET` writer - This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register. Reset value: 0x0"] pub type M_RESTART_DET_W<'a, REG> = crate::BitWriter<'a, REG, M_RESTART_DET_A>; impl<'a, REG> M_RESTART_DET_W<'a, REG> where @@ -796,207 +718,153 @@ where } } impl R { - #[doc = "Bit 0 - This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register. - - Reset value: 0x1"] + #[doc = "Bit 0 - This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register. Reset value: 0x1"] #[inline(always)] pub fn m_rx_under(&self) -> M_RX_UNDER_R { M_RX_UNDER_R::new((self.bits & 1) != 0) } - #[doc = "Bit 1 - This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register. - - Reset value: 0x1"] + #[doc = "Bit 1 - This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register. Reset value: 0x1"] #[inline(always)] pub fn m_rx_over(&self) -> M_RX_OVER_R { M_RX_OVER_R::new(((self.bits >> 1) & 1) != 0) } - #[doc = "Bit 2 - This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register. - - Reset value: 0x1"] + #[doc = "Bit 2 - This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register. Reset value: 0x1"] #[inline(always)] pub fn m_rx_full(&self) -> M_RX_FULL_R { M_RX_FULL_R::new(((self.bits >> 2) & 1) != 0) } - #[doc = "Bit 3 - This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register. - - Reset value: 0x1"] + #[doc = "Bit 3 - This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register. Reset value: 0x1"] #[inline(always)] pub fn m_tx_over(&self) -> M_TX_OVER_R { M_TX_OVER_R::new(((self.bits >> 3) & 1) != 0) } - #[doc = "Bit 4 - This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register. - - Reset value: 0x1"] + #[doc = "Bit 4 - This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register. Reset value: 0x1"] #[inline(always)] pub fn m_tx_empty(&self) -> M_TX_EMPTY_R { M_TX_EMPTY_R::new(((self.bits >> 4) & 1) != 0) } - #[doc = "Bit 5 - This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register. - - Reset value: 0x1"] + #[doc = "Bit 5 - This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register. Reset value: 0x1"] #[inline(always)] pub fn m_rd_req(&self) -> M_RD_REQ_R { M_RD_REQ_R::new(((self.bits >> 5) & 1) != 0) } - #[doc = "Bit 6 - This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register. - - Reset value: 0x1"] + #[doc = "Bit 6 - This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register. Reset value: 0x1"] #[inline(always)] pub fn m_tx_abrt(&self) -> M_TX_ABRT_R { M_TX_ABRT_R::new(((self.bits >> 6) & 1) != 0) } - #[doc = "Bit 7 - This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register. - - Reset value: 0x1"] + #[doc = "Bit 7 - This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register. Reset value: 0x1"] #[inline(always)] pub fn m_rx_done(&self) -> M_RX_DONE_R { M_RX_DONE_R::new(((self.bits >> 7) & 1) != 0) } - #[doc = "Bit 8 - This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register. - - Reset value: 0x0"] + #[doc = "Bit 8 - This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register. Reset value: 0x0"] #[inline(always)] pub fn m_activity(&self) -> M_ACTIVITY_R { M_ACTIVITY_R::new(((self.bits >> 8) & 1) != 0) } - #[doc = "Bit 9 - This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register. - - Reset value: 0x0"] + #[doc = "Bit 9 - This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register. Reset value: 0x0"] #[inline(always)] pub fn m_stop_det(&self) -> M_STOP_DET_R { M_STOP_DET_R::new(((self.bits >> 9) & 1) != 0) } - #[doc = "Bit 10 - This bit masks the R_START_DET interrupt in IC_INTR_STAT register. - - Reset value: 0x0"] + #[doc = "Bit 10 - This bit masks the R_START_DET interrupt in IC_INTR_STAT register. Reset value: 0x0"] #[inline(always)] pub fn m_start_det(&self) -> M_START_DET_R { M_START_DET_R::new(((self.bits >> 10) & 1) != 0) } - #[doc = "Bit 11 - This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register. - - Reset value: 0x1"] + #[doc = "Bit 11 - This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register. Reset value: 0x1"] #[inline(always)] pub fn m_gen_call(&self) -> M_GEN_CALL_R { M_GEN_CALL_R::new(((self.bits >> 11) & 1) != 0) } - #[doc = "Bit 12 - This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register. - - Reset value: 0x0"] + #[doc = "Bit 12 - This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register. Reset value: 0x0"] #[inline(always)] pub fn m_restart_det(&self) -> M_RESTART_DET_R { M_RESTART_DET_R::new(((self.bits >> 12) & 1) != 0) } } impl W { - #[doc = "Bit 0 - This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register. - - Reset value: 0x1"] + #[doc = "Bit 0 - This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register. Reset value: 0x1"] #[inline(always)] #[must_use] pub fn m_rx_under(&mut self) -> M_RX_UNDER_W { M_RX_UNDER_W::new(self, 0) } - #[doc = "Bit 1 - This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register. - - Reset value: 0x1"] + #[doc = "Bit 1 - This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register. Reset value: 0x1"] #[inline(always)] #[must_use] pub fn m_rx_over(&mut self) -> M_RX_OVER_W { M_RX_OVER_W::new(self, 1) } - #[doc = "Bit 2 - This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register. - - Reset value: 0x1"] + #[doc = "Bit 2 - This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register. Reset value: 0x1"] #[inline(always)] #[must_use] pub fn m_rx_full(&mut self) -> M_RX_FULL_W { M_RX_FULL_W::new(self, 2) } - #[doc = "Bit 3 - This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register. - - Reset value: 0x1"] + #[doc = "Bit 3 - This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register. Reset value: 0x1"] #[inline(always)] #[must_use] pub fn m_tx_over(&mut self) -> M_TX_OVER_W { M_TX_OVER_W::new(self, 3) } - #[doc = "Bit 4 - This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register. - - Reset value: 0x1"] + #[doc = "Bit 4 - This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register. Reset value: 0x1"] #[inline(always)] #[must_use] pub fn m_tx_empty(&mut self) -> M_TX_EMPTY_W { M_TX_EMPTY_W::new(self, 4) } - #[doc = "Bit 5 - This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register. - - Reset value: 0x1"] + #[doc = "Bit 5 - This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register. Reset value: 0x1"] #[inline(always)] #[must_use] pub fn m_rd_req(&mut self) -> M_RD_REQ_W { M_RD_REQ_W::new(self, 5) } - #[doc = "Bit 6 - This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register. - - Reset value: 0x1"] + #[doc = "Bit 6 - This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register. Reset value: 0x1"] #[inline(always)] #[must_use] pub fn m_tx_abrt(&mut self) -> M_TX_ABRT_W { M_TX_ABRT_W::new(self, 6) } - #[doc = "Bit 7 - This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register. - - Reset value: 0x1"] + #[doc = "Bit 7 - This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register. Reset value: 0x1"] #[inline(always)] #[must_use] pub fn m_rx_done(&mut self) -> M_RX_DONE_W { M_RX_DONE_W::new(self, 7) } - #[doc = "Bit 8 - This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register. - - Reset value: 0x0"] + #[doc = "Bit 8 - This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register. Reset value: 0x0"] #[inline(always)] #[must_use] pub fn m_activity(&mut self) -> M_ACTIVITY_W { M_ACTIVITY_W::new(self, 8) } - #[doc = "Bit 9 - This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register. - - Reset value: 0x0"] + #[doc = "Bit 9 - This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register. Reset value: 0x0"] #[inline(always)] #[must_use] pub fn m_stop_det(&mut self) -> M_STOP_DET_W { M_STOP_DET_W::new(self, 9) } - #[doc = "Bit 10 - This bit masks the R_START_DET interrupt in IC_INTR_STAT register. - - Reset value: 0x0"] + #[doc = "Bit 10 - This bit masks the R_START_DET interrupt in IC_INTR_STAT register. Reset value: 0x0"] #[inline(always)] #[must_use] pub fn m_start_det(&mut self) -> M_START_DET_W { M_START_DET_W::new(self, 10) } - #[doc = "Bit 11 - This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register. - - Reset value: 0x1"] + #[doc = "Bit 11 - This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register. Reset value: 0x1"] #[inline(always)] #[must_use] pub fn m_gen_call(&mut self) -> M_GEN_CALL_W { M_GEN_CALL_W::new(self, 11) } - #[doc = "Bit 12 - This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register. - - Reset value: 0x0"] + #[doc = "Bit 12 - This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register. Reset value: 0x0"] #[inline(always)] #[must_use] pub fn m_restart_det(&mut self) -> M_RESTART_DET_W { M_RESTART_DET_W::new(self, 12) } } -#[doc = "I2C Interrupt Mask Register. - - These bits mask their corresponding interrupt status bits. This register is active low; a value of 0 masks the interrupt, whereas a value of 1 unmasks the interrupt. +#[doc = "I2C Interrupt Mask Register. These bits mask their corresponding interrupt status bits. This register is active low; a value of 0 masks the interrupt, whereas a value of 1 unmasks the interrupt. You can [`read`](crate::generic::Reg::read) this register and get [`ic_intr_mask::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_intr_mask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IC_INTR_MASK_SPEC; diff --git a/src/i2c0/ic_intr_stat.rs b/src/i2c0/ic_intr_stat.rs index c8aea206a..463c112de 100644 --- a/src/i2c0/ic_intr_stat.rs +++ b/src/i2c0/ic_intr_stat.rs @@ -1,8 +1,8 @@ #[doc = "Register `IC_INTR_STAT` reader"] pub type R = crate::R; -#[doc = "See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER bit. - - Reset value: 0x0 +#[doc = "Register `IC_INTR_STAT` writer"] +pub type W = crate::W; +#[doc = "See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER bit. Reset value: 0x0 Value on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -18,9 +18,7 @@ impl From for bool { variant as u8 != 0 } } -#[doc = "Field `R_RX_UNDER` reader - See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER bit. - - Reset value: 0x0"] +#[doc = "Field `R_RX_UNDER` reader - See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER bit. Reset value: 0x0"] pub type R_RX_UNDER_R = crate::BitReader; impl R_RX_UNDER_R { #[doc = "Get enumerated values variant"] @@ -42,9 +40,7 @@ impl R_RX_UNDER_R { *self == R_RX_UNDER_A::ACTIVE } } -#[doc = "See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER bit. - - Reset value: 0x0 +#[doc = "See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER bit. Reset value: 0x0 Value on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -60,9 +56,7 @@ impl From for bool { variant as u8 != 0 } } -#[doc = "Field `R_RX_OVER` reader - See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER bit. - - Reset value: 0x0"] +#[doc = "Field `R_RX_OVER` reader - See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER bit. Reset value: 0x0"] pub type R_RX_OVER_R = crate::BitReader; impl R_RX_OVER_R { #[doc = "Get enumerated values variant"] @@ -84,9 +78,7 @@ impl R_RX_OVER_R { *self == R_RX_OVER_A::ACTIVE } } -#[doc = "See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL bit. - - Reset value: 0x0 +#[doc = "See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL bit. Reset value: 0x0 Value on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -102,9 +94,7 @@ impl From for bool { variant as u8 != 0 } } -#[doc = "Field `R_RX_FULL` reader - See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL bit. - - Reset value: 0x0"] +#[doc = "Field `R_RX_FULL` reader - See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL bit. Reset value: 0x0"] pub type R_RX_FULL_R = crate::BitReader; impl R_RX_FULL_R { #[doc = "Get enumerated values variant"] @@ -126,9 +116,7 @@ impl R_RX_FULL_R { *self == R_RX_FULL_A::ACTIVE } } -#[doc = "See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER bit. - - Reset value: 0x0 +#[doc = "See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER bit. Reset value: 0x0 Value on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -144,9 +132,7 @@ impl From for bool { variant as u8 != 0 } } -#[doc = "Field `R_TX_OVER` reader - See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER bit. - - Reset value: 0x0"] +#[doc = "Field `R_TX_OVER` reader - See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER bit. Reset value: 0x0"] pub type R_TX_OVER_R = crate::BitReader; impl R_TX_OVER_R { #[doc = "Get enumerated values variant"] @@ -168,9 +154,7 @@ impl R_TX_OVER_R { *self == R_TX_OVER_A::ACTIVE } } -#[doc = "See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY bit. - - Reset value: 0x0 +#[doc = "See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY bit. Reset value: 0x0 Value on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -186,9 +170,7 @@ impl From for bool { variant as u8 != 0 } } -#[doc = "Field `R_TX_EMPTY` reader - See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY bit. - - Reset value: 0x0"] +#[doc = "Field `R_TX_EMPTY` reader - See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY bit. Reset value: 0x0"] pub type R_TX_EMPTY_R = crate::BitReader; impl R_TX_EMPTY_R { #[doc = "Get enumerated values variant"] @@ -210,9 +192,7 @@ impl R_TX_EMPTY_R { *self == R_TX_EMPTY_A::ACTIVE } } -#[doc = "See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ bit. - - Reset value: 0x0 +#[doc = "See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ bit. Reset value: 0x0 Value on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -228,9 +208,7 @@ impl From for bool { variant as u8 != 0 } } -#[doc = "Field `R_RD_REQ` reader - See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ bit. - - Reset value: 0x0"] +#[doc = "Field `R_RD_REQ` reader - See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ bit. Reset value: 0x0"] pub type R_RD_REQ_R = crate::BitReader; impl R_RD_REQ_R { #[doc = "Get enumerated values variant"] @@ -252,9 +230,7 @@ impl R_RD_REQ_R { *self == R_RD_REQ_A::ACTIVE } } -#[doc = "See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT bit. - - Reset value: 0x0 +#[doc = "See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT bit. Reset value: 0x0 Value on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -270,9 +246,7 @@ impl From for bool { variant as u8 != 0 } } -#[doc = "Field `R_TX_ABRT` reader - See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT bit. - - Reset value: 0x0"] +#[doc = "Field `R_TX_ABRT` reader - See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT bit. Reset value: 0x0"] pub type R_TX_ABRT_R = crate::BitReader; impl R_TX_ABRT_R { #[doc = "Get enumerated values variant"] @@ -294,9 +268,7 @@ impl R_TX_ABRT_R { *self == R_TX_ABRT_A::ACTIVE } } -#[doc = "See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE bit. - - Reset value: 0x0 +#[doc = "See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE bit. Reset value: 0x0 Value on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -312,9 +284,7 @@ impl From for bool { variant as u8 != 0 } } -#[doc = "Field `R_RX_DONE` reader - See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE bit. - - Reset value: 0x0"] +#[doc = "Field `R_RX_DONE` reader - See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE bit. Reset value: 0x0"] pub type R_RX_DONE_R = crate::BitReader; impl R_RX_DONE_R { #[doc = "Get enumerated values variant"] @@ -336,9 +306,7 @@ impl R_RX_DONE_R { *self == R_RX_DONE_A::ACTIVE } } -#[doc = "See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY bit. - - Reset value: 0x0 +#[doc = "See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY bit. Reset value: 0x0 Value on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -354,9 +322,7 @@ impl From for bool { variant as u8 != 0 } } -#[doc = "Field `R_ACTIVITY` reader - See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY bit. - - Reset value: 0x0"] +#[doc = "Field `R_ACTIVITY` reader - See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY bit. Reset value: 0x0"] pub type R_ACTIVITY_R = crate::BitReader; impl R_ACTIVITY_R { #[doc = "Get enumerated values variant"] @@ -378,9 +344,7 @@ impl R_ACTIVITY_R { *self == R_ACTIVITY_A::ACTIVE } } -#[doc = "See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET bit. - - Reset value: 0x0 +#[doc = "See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET bit. Reset value: 0x0 Value on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -396,9 +360,7 @@ impl From for bool { variant as u8 != 0 } } -#[doc = "Field `R_STOP_DET` reader - See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET bit. - - Reset value: 0x0"] +#[doc = "Field `R_STOP_DET` reader - See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET bit. Reset value: 0x0"] pub type R_STOP_DET_R = crate::BitReader; impl R_STOP_DET_R { #[doc = "Get enumerated values variant"] @@ -420,9 +382,7 @@ impl R_STOP_DET_R { *self == R_STOP_DET_A::ACTIVE } } -#[doc = "See IC_RAW_INTR_STAT for a detailed description of R_START_DET bit. - - Reset value: 0x0 +#[doc = "See IC_RAW_INTR_STAT for a detailed description of R_START_DET bit. Reset value: 0x0 Value on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -438,9 +398,7 @@ impl From for bool { variant as u8 != 0 } } -#[doc = "Field `R_START_DET` reader - See IC_RAW_INTR_STAT for a detailed description of R_START_DET bit. - - Reset value: 0x0"] +#[doc = "Field `R_START_DET` reader - See IC_RAW_INTR_STAT for a detailed description of R_START_DET bit. Reset value: 0x0"] pub type R_START_DET_R = crate::BitReader; impl R_START_DET_R { #[doc = "Get enumerated values variant"] @@ -462,9 +420,7 @@ impl R_START_DET_R { *self == R_START_DET_A::ACTIVE } } -#[doc = "See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL bit. - - Reset value: 0x0 +#[doc = "See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL bit. Reset value: 0x0 Value on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -480,9 +436,7 @@ impl From for bool { variant as u8 != 0 } } -#[doc = "Field `R_GEN_CALL` reader - See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL bit. - - Reset value: 0x0"] +#[doc = "Field `R_GEN_CALL` reader - See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL bit. Reset value: 0x0"] pub type R_GEN_CALL_R = crate::BitReader; impl R_GEN_CALL_R { #[doc = "Get enumerated values variant"] @@ -504,9 +458,7 @@ impl R_GEN_CALL_R { *self == R_GEN_CALL_A::ACTIVE } } -#[doc = "See IC_RAW_INTR_STAT for a detailed description of R_RESTART_DET bit. - - Reset value: 0x0 +#[doc = "See IC_RAW_INTR_STAT for a detailed description of R_RESTART_DET bit. Reset value: 0x0 Value on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -522,9 +474,7 @@ impl From for bool { variant as u8 != 0 } } -#[doc = "Field `R_RESTART_DET` reader - See IC_RAW_INTR_STAT for a detailed description of R_RESTART_DET bit. - - Reset value: 0x0"] +#[doc = "Field `R_RESTART_DET` reader - See IC_RAW_INTR_STAT for a detailed description of R_RESTART_DET bit. Reset value: 0x0"] pub type R_RESTART_DET_R = crate::BitReader; impl R_RESTART_DET_R { #[doc = "Get enumerated values variant"] @@ -547,109 +497,88 @@ impl R_RESTART_DET_R { } } impl R { - #[doc = "Bit 0 - See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER bit. - - Reset value: 0x0"] + #[doc = "Bit 0 - See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER bit. Reset value: 0x0"] #[inline(always)] pub fn r_rx_under(&self) -> R_RX_UNDER_R { R_RX_UNDER_R::new((self.bits & 1) != 0) } - #[doc = "Bit 1 - See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER bit. - - Reset value: 0x0"] + #[doc = "Bit 1 - See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER bit. Reset value: 0x0"] #[inline(always)] pub fn r_rx_over(&self) -> R_RX_OVER_R { R_RX_OVER_R::new(((self.bits >> 1) & 1) != 0) } - #[doc = "Bit 2 - See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL bit. - - Reset value: 0x0"] + #[doc = "Bit 2 - See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL bit. Reset value: 0x0"] #[inline(always)] pub fn r_rx_full(&self) -> R_RX_FULL_R { R_RX_FULL_R::new(((self.bits >> 2) & 1) != 0) } - #[doc = "Bit 3 - See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER bit. - - Reset value: 0x0"] + #[doc = "Bit 3 - See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER bit. Reset value: 0x0"] #[inline(always)] pub fn r_tx_over(&self) -> R_TX_OVER_R { R_TX_OVER_R::new(((self.bits >> 3) & 1) != 0) } - #[doc = "Bit 4 - See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY bit. - - Reset value: 0x0"] + #[doc = "Bit 4 - See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY bit. Reset value: 0x0"] #[inline(always)] pub fn r_tx_empty(&self) -> R_TX_EMPTY_R { R_TX_EMPTY_R::new(((self.bits >> 4) & 1) != 0) } - #[doc = "Bit 5 - See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ bit. - - Reset value: 0x0"] + #[doc = "Bit 5 - See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ bit. Reset value: 0x0"] #[inline(always)] pub fn r_rd_req(&self) -> R_RD_REQ_R { R_RD_REQ_R::new(((self.bits >> 5) & 1) != 0) } - #[doc = "Bit 6 - See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT bit. - - Reset value: 0x0"] + #[doc = "Bit 6 - See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT bit. Reset value: 0x0"] #[inline(always)] pub fn r_tx_abrt(&self) -> R_TX_ABRT_R { R_TX_ABRT_R::new(((self.bits >> 6) & 1) != 0) } - #[doc = "Bit 7 - See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE bit. - - Reset value: 0x0"] + #[doc = "Bit 7 - See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE bit. Reset value: 0x0"] #[inline(always)] pub fn r_rx_done(&self) -> R_RX_DONE_R { R_RX_DONE_R::new(((self.bits >> 7) & 1) != 0) } - #[doc = "Bit 8 - See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY bit. - - Reset value: 0x0"] + #[doc = "Bit 8 - See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY bit. Reset value: 0x0"] #[inline(always)] pub fn r_activity(&self) -> R_ACTIVITY_R { R_ACTIVITY_R::new(((self.bits >> 8) & 1) != 0) } - #[doc = "Bit 9 - See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET bit. - - Reset value: 0x0"] + #[doc = "Bit 9 - See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET bit. Reset value: 0x0"] #[inline(always)] pub fn r_stop_det(&self) -> R_STOP_DET_R { R_STOP_DET_R::new(((self.bits >> 9) & 1) != 0) } - #[doc = "Bit 10 - See IC_RAW_INTR_STAT for a detailed description of R_START_DET bit. - - Reset value: 0x0"] + #[doc = "Bit 10 - See IC_RAW_INTR_STAT for a detailed description of R_START_DET bit. Reset value: 0x0"] #[inline(always)] pub fn r_start_det(&self) -> R_START_DET_R { R_START_DET_R::new(((self.bits >> 10) & 1) != 0) } - #[doc = "Bit 11 - See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL bit. - - Reset value: 0x0"] + #[doc = "Bit 11 - See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL bit. Reset value: 0x0"] #[inline(always)] pub fn r_gen_call(&self) -> R_GEN_CALL_R { R_GEN_CALL_R::new(((self.bits >> 11) & 1) != 0) } - #[doc = "Bit 12 - See IC_RAW_INTR_STAT for a detailed description of R_RESTART_DET bit. - - Reset value: 0x0"] + #[doc = "Bit 12 - See IC_RAW_INTR_STAT for a detailed description of R_RESTART_DET bit. Reset value: 0x0"] #[inline(always)] pub fn r_restart_det(&self) -> R_RESTART_DET_R { R_RESTART_DET_R::new(((self.bits >> 12) & 1) != 0) } } -#[doc = "I2C Interrupt Status Register +impl W {} +#[doc = "I2C Interrupt Status Register Each bit in this register has a corresponding mask bit in the IC_INTR_MASK register. These bits are cleared by reading the matching interrupt clear register. The unmasked raw versions of these bits are available in the IC_RAW_INTR_STAT register. - Each bit in this register has a corresponding mask bit in the IC_INTR_MASK register. These bits are cleared by reading the matching interrupt clear register. The unmasked raw versions of these bits are available in the IC_RAW_INTR_STAT register. - -You can [`read`](crate::generic::Reg::read) this register and get [`ic_intr_stat::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`ic_intr_stat::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_intr_stat::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IC_INTR_STAT_SPEC; impl crate::RegisterSpec for IC_INTR_STAT_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`ic_intr_stat::R`](R) reader structure"] impl crate::Readable for IC_INTR_STAT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ic_intr_stat::W`](W) writer structure"] +impl crate::Writable for IC_INTR_STAT_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets IC_INTR_STAT to value 0"] impl crate::Resettable for IC_INTR_STAT_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/i2c0/ic_raw_intr_stat.rs b/src/i2c0/ic_raw_intr_stat.rs index 527538c31..a92791ade 100644 --- a/src/i2c0/ic_raw_intr_stat.rs +++ b/src/i2c0/ic_raw_intr_stat.rs @@ -1,8 +1,8 @@ #[doc = "Register `IC_RAW_INTR_STAT` reader"] pub type R = crate::R; -#[doc = "Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register. If the module is disabled (IC_ENABLE\\[0\\]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. - - Reset value: 0x0 +#[doc = "Register `IC_RAW_INTR_STAT` writer"] +pub type W = crate::W; +#[doc = "Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register. If the module is disabled (IC_ENABLE\\[0\\]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. Reset value: 0x0 Value on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -18,9 +18,7 @@ impl From for bool { variant as u8 != 0 } } -#[doc = "Field `RX_UNDER` reader - Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register. If the module is disabled (IC_ENABLE\\[0\\]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. - - Reset value: 0x0"] +#[doc = "Field `RX_UNDER` reader - Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register. If the module is disabled (IC_ENABLE\\[0\\]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. Reset value: 0x0"] pub type RX_UNDER_R = crate::BitReader; impl RX_UNDER_R { #[doc = "Get enumerated values variant"] @@ -42,11 +40,7 @@ impl RX_UNDER_R { *self == RX_UNDER_A::ACTIVE } } -#[doc = "Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an additional byte is received from an external I2C device. The DW_apb_i2c acknowledges this, but any data bytes received after the FIFO is full are lost. If the module is disabled (IC_ENABLE\\[0\\]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. - - Note: If bit 9 of the IC_CON register (RX_FIFO_FULL_HLD_CTRL) is programmed to HIGH, then the RX_OVER interrupt never occurs, because the Rx FIFO never overflows. - - Reset value: 0x0 +#[doc = "Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an additional byte is received from an external I2C device. The DW_apb_i2c acknowledges this, but any data bytes received after the FIFO is full are lost. If the module is disabled (IC_ENABLE\\[0\\]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. Note: If bit 9 of the IC_CON register (RX_FIFO_FULL_HLD_CTRL) is programmed to HIGH, then the RX_OVER interrupt never occurs, because the Rx FIFO never overflows. Reset value: 0x0 Value on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -62,11 +56,7 @@ impl From for bool { variant as u8 != 0 } } -#[doc = "Field `RX_OVER` reader - Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an additional byte is received from an external I2C device. The DW_apb_i2c acknowledges this, but any data bytes received after the FIFO is full are lost. If the module is disabled (IC_ENABLE\\[0\\]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. - - Note: If bit 9 of the IC_CON register (RX_FIFO_FULL_HLD_CTRL) is programmed to HIGH, then the RX_OVER interrupt never occurs, because the Rx FIFO never overflows. - - Reset value: 0x0"] +#[doc = "Field `RX_OVER` reader - Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an additional byte is received from an external I2C device. The DW_apb_i2c acknowledges this, but any data bytes received after the FIFO is full are lost. If the module is disabled (IC_ENABLE\\[0\\]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. Note: If bit 9 of the IC_CON register (RX_FIFO_FULL_HLD_CTRL) is programmed to HIGH, then the RX_OVER interrupt never occurs, because the Rx FIFO never overflows. Reset value: 0x0"] pub type RX_OVER_R = crate::BitReader; impl RX_OVER_R { #[doc = "Get enumerated values variant"] @@ -88,9 +78,7 @@ impl RX_OVER_R { *self == RX_OVER_A::ACTIVE } } -#[doc = "Set when the receive buffer reaches or goes above the RX_TL threshold in the IC_RX_TL register. It is automatically cleared by hardware when buffer level goes below the threshold. If the module is disabled (IC_ENABLE\\[0\\]=0), the RX FIFO is flushed and held in reset; therefore the RX FIFO is not full. So this bit is cleared once the IC_ENABLE bit 0 is programmed with a 0, regardless of the activity that continues. - - Reset value: 0x0 +#[doc = "Set when the receive buffer reaches or goes above the RX_TL threshold in the IC_RX_TL register. It is automatically cleared by hardware when buffer level goes below the threshold. If the module is disabled (IC_ENABLE\\[0\\]=0), the RX FIFO is flushed and held in reset; therefore the RX FIFO is not full. So this bit is cleared once the IC_ENABLE bit 0 is programmed with a 0, regardless of the activity that continues. Reset value: 0x0 Value on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -106,9 +94,7 @@ impl From for bool { variant as u8 != 0 } } -#[doc = "Field `RX_FULL` reader - Set when the receive buffer reaches or goes above the RX_TL threshold in the IC_RX_TL register. It is automatically cleared by hardware when buffer level goes below the threshold. If the module is disabled (IC_ENABLE\\[0\\]=0), the RX FIFO is flushed and held in reset; therefore the RX FIFO is not full. So this bit is cleared once the IC_ENABLE bit 0 is programmed with a 0, regardless of the activity that continues. - - Reset value: 0x0"] +#[doc = "Field `RX_FULL` reader - Set when the receive buffer reaches or goes above the RX_TL threshold in the IC_RX_TL register. It is automatically cleared by hardware when buffer level goes below the threshold. If the module is disabled (IC_ENABLE\\[0\\]=0), the RX FIFO is flushed and held in reset; therefore the RX FIFO is not full. So this bit is cleared once the IC_ENABLE bit 0 is programmed with a 0, regardless of the activity that continues. Reset value: 0x0"] pub type RX_FULL_R = crate::BitReader; impl RX_FULL_R { #[doc = "Get enumerated values variant"] @@ -130,9 +116,7 @@ impl RX_FULL_R { *self == RX_FULL_A::ACTIVE } } -#[doc = "Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register. When the module is disabled, this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. - - Reset value: 0x0 +#[doc = "Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register. When the module is disabled, this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. Reset value: 0x0 Value on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -148,9 +132,7 @@ impl From for bool { variant as u8 != 0 } } -#[doc = "Field `TX_OVER` reader - Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register. When the module is disabled, this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. - - Reset value: 0x0"] +#[doc = "Field `TX_OVER` reader - Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register. When the module is disabled, this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. Reset value: 0x0"] pub type TX_OVER_R = crate::BitReader; impl TX_OVER_R { #[doc = "Get enumerated values variant"] @@ -173,9 +155,7 @@ impl TX_OVER_R { } } #[doc = "The behavior of the TX_EMPTY interrupt status differs based on the TX_EMPTY_CTRL selection in the IC_CON register. - When TX_EMPTY_CTRL = 0: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register. - When TX_EMPTY_CTRL = 1: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register and the transmission of the address/data from the internal shift register for the most recently popped command is completed. It is automatically cleared by hardware when the buffer level goes above the threshold. When IC_ENABLE\\[0\\] -is set to 0, the TX FIFO is flushed and held in reset. There the TX FIFO looks like it has no data within it, so this bit is set to 1, provided there is activity in the master or slave state machines. When there is no longer any activity, then with ic_en=0, this bit is set to 0. - - Reset value: 0x0. +is set to 0, the TX FIFO is flushed and held in reset. There the TX FIFO looks like it has no data within it, so this bit is set to 1, provided there is activity in the master or slave state machines. When there is no longer any activity, then with ic_en=0, this bit is set to 0. Reset value: 0x0. Value on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -192,9 +172,7 @@ impl From for bool { } } #[doc = "Field `TX_EMPTY` reader - The behavior of the TX_EMPTY interrupt status differs based on the TX_EMPTY_CTRL selection in the IC_CON register. - When TX_EMPTY_CTRL = 0: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register. - When TX_EMPTY_CTRL = 1: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register and the transmission of the address/data from the internal shift register for the most recently popped command is completed. It is automatically cleared by hardware when the buffer level goes above the threshold. When IC_ENABLE\\[0\\] -is set to 0, the TX FIFO is flushed and held in reset. There the TX FIFO looks like it has no data within it, so this bit is set to 1, provided there is activity in the master or slave state machines. When there is no longer any activity, then with ic_en=0, this bit is set to 0. - - Reset value: 0x0."] +is set to 0, the TX FIFO is flushed and held in reset. There the TX FIFO looks like it has no data within it, so this bit is set to 1, provided there is activity in the master or slave state machines. When there is no longer any activity, then with ic_en=0, this bit is set to 0. Reset value: 0x0."] pub type TX_EMPTY_R = crate::BitReader; impl TX_EMPTY_R { #[doc = "Get enumerated values variant"] @@ -216,9 +194,7 @@ impl TX_EMPTY_R { *self == TX_EMPTY_A::ACTIVE } } -#[doc = "This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C master is attempting to read data from DW_apb_i2c. The DW_apb_i2c holds the I2C bus in a wait state (SCL=0) until this interrupt is serviced, which means that the slave has been addressed by a remote master that is asking for data to be transferred. The processor must respond to this interrupt and then write the requested data to the IC_DATA_CMD register. This bit is set to 0 just after the processor reads the IC_CLR_RD_REQ register. - - Reset value: 0x0 +#[doc = "This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C master is attempting to read data from DW_apb_i2c. The DW_apb_i2c holds the I2C bus in a wait state (SCL=0) until this interrupt is serviced, which means that the slave has been addressed by a remote master that is asking for data to be transferred. The processor must respond to this interrupt and then write the requested data to the IC_DATA_CMD register. This bit is set to 0 just after the processor reads the IC_CLR_RD_REQ register. Reset value: 0x0 Value on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -234,9 +210,7 @@ impl From for bool { variant as u8 != 0 } } -#[doc = "Field `RD_REQ` reader - This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C master is attempting to read data from DW_apb_i2c. The DW_apb_i2c holds the I2C bus in a wait state (SCL=0) until this interrupt is serviced, which means that the slave has been addressed by a remote master that is asking for data to be transferred. The processor must respond to this interrupt and then write the requested data to the IC_DATA_CMD register. This bit is set to 0 just after the processor reads the IC_CLR_RD_REQ register. - - Reset value: 0x0"] +#[doc = "Field `RD_REQ` reader - This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C master is attempting to read data from DW_apb_i2c. The DW_apb_i2c holds the I2C bus in a wait state (SCL=0) until this interrupt is serviced, which means that the slave has been addressed by a remote master that is asking for data to be transferred. The processor must respond to this interrupt and then write the requested data to the IC_DATA_CMD register. This bit is set to 0 just after the processor reads the IC_CLR_RD_REQ register. Reset value: 0x0"] pub type RD_REQ_R = crate::BitReader; impl RD_REQ_R { #[doc = "Get enumerated values variant"] @@ -258,11 +232,7 @@ impl RD_REQ_R { *self == RD_REQ_A::ACTIVE } } -#[doc = "This bit indicates if DW_apb_i2c, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO. This situation can occur both as an I2C master or an I2C slave, and is referred to as a 'transmit abort'. When this bit is set to 1, the IC_TX_ABRT_SOURCE register indicates the reason why the transmit abort takes places. - - Note: The DW_apb_i2c flushes/resets/empties the TX_FIFO and RX_FIFO whenever there is a transmit abort caused by any of the events tracked by the IC_TX_ABRT_SOURCE register. The FIFOs remains in this flushed state until the register IC_CLR_TX_ABRT is read. Once this read is performed, the Tx FIFO is then ready to accept more data bytes from the APB interface. - - Reset value: 0x0 +#[doc = "This bit indicates if DW_apb_i2c, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO. This situation can occur both as an I2C master or an I2C slave, and is referred to as a 'transmit abort'. When this bit is set to 1, the IC_TX_ABRT_SOURCE register indicates the reason why the transmit abort takes places. Note: The DW_apb_i2c flushes/resets/empties the TX_FIFO and RX_FIFO whenever there is a transmit abort caused by any of the events tracked by the IC_TX_ABRT_SOURCE register. The FIFOs remains in this flushed state until the register IC_CLR_TX_ABRT is read. Once this read is performed, the Tx FIFO is then ready to accept more data bytes from the APB interface. Reset value: 0x0 Value on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -278,11 +248,7 @@ impl From for bool { variant as u8 != 0 } } -#[doc = "Field `TX_ABRT` reader - This bit indicates if DW_apb_i2c, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO. This situation can occur both as an I2C master or an I2C slave, and is referred to as a 'transmit abort'. When this bit is set to 1, the IC_TX_ABRT_SOURCE register indicates the reason why the transmit abort takes places. - - Note: The DW_apb_i2c flushes/resets/empties the TX_FIFO and RX_FIFO whenever there is a transmit abort caused by any of the events tracked by the IC_TX_ABRT_SOURCE register. The FIFOs remains in this flushed state until the register IC_CLR_TX_ABRT is read. Once this read is performed, the Tx FIFO is then ready to accept more data bytes from the APB interface. - - Reset value: 0x0"] +#[doc = "Field `TX_ABRT` reader - This bit indicates if DW_apb_i2c, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO. This situation can occur both as an I2C master or an I2C slave, and is referred to as a 'transmit abort'. When this bit is set to 1, the IC_TX_ABRT_SOURCE register indicates the reason why the transmit abort takes places. Note: The DW_apb_i2c flushes/resets/empties the TX_FIFO and RX_FIFO whenever there is a transmit abort caused by any of the events tracked by the IC_TX_ABRT_SOURCE register. The FIFOs remains in this flushed state until the register IC_CLR_TX_ABRT is read. Once this read is performed, the Tx FIFO is then ready to accept more data bytes from the APB interface. Reset value: 0x0"] pub type TX_ABRT_R = crate::BitReader; impl TX_ABRT_R { #[doc = "Get enumerated values variant"] @@ -304,9 +270,7 @@ impl TX_ABRT_R { *self == TX_ABRT_A::ACTIVE } } -#[doc = "When the DW_apb_i2c is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte. This occurs on the last byte of the transmission, indicating that the transmission is done. - - Reset value: 0x0 +#[doc = "When the DW_apb_i2c is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte. This occurs on the last byte of the transmission, indicating that the transmission is done. Reset value: 0x0 Value on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -322,9 +286,7 @@ impl From for bool { variant as u8 != 0 } } -#[doc = "Field `RX_DONE` reader - When the DW_apb_i2c is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte. This occurs on the last byte of the transmission, indicating that the transmission is done. - - Reset value: 0x0"] +#[doc = "Field `RX_DONE` reader - When the DW_apb_i2c is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte. This occurs on the last byte of the transmission, indicating that the transmission is done. Reset value: 0x0"] pub type RX_DONE_R = crate::BitReader; impl RX_DONE_R { #[doc = "Get enumerated values variant"] @@ -346,9 +308,7 @@ impl RX_DONE_R { *self == RX_DONE_A::ACTIVE } } -#[doc = "This bit captures DW_apb_i2c activity and stays set until it is cleared. There are four ways to clear it: - Disabling the DW_apb_i2c - Reading the IC_CLR_ACTIVITY register - Reading the IC_CLR_INTR register - System reset Once this bit is set, it stays set unless one of the four methods is used to clear it. Even if the DW_apb_i2c module is idle, this bit remains set until cleared, indicating that there was activity on the bus. - - Reset value: 0x0 +#[doc = "This bit captures DW_apb_i2c activity and stays set until it is cleared. There are four ways to clear it: - Disabling the DW_apb_i2c - Reading the IC_CLR_ACTIVITY register - Reading the IC_CLR_INTR register - System reset Once this bit is set, it stays set unless one of the four methods is used to clear it. Even if the DW_apb_i2c module is idle, this bit remains set until cleared, indicating that there was activity on the bus. Reset value: 0x0 Value on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -364,9 +324,7 @@ impl From for bool { variant as u8 != 0 } } -#[doc = "Field `ACTIVITY` reader - This bit captures DW_apb_i2c activity and stays set until it is cleared. There are four ways to clear it: - Disabling the DW_apb_i2c - Reading the IC_CLR_ACTIVITY register - Reading the IC_CLR_INTR register - System reset Once this bit is set, it stays set unless one of the four methods is used to clear it. Even if the DW_apb_i2c module is idle, this bit remains set until cleared, indicating that there was activity on the bus. - - Reset value: 0x0"] +#[doc = "Field `ACTIVITY` reader - This bit captures DW_apb_i2c activity and stays set until it is cleared. There are four ways to clear it: - Disabling the DW_apb_i2c - Reading the IC_CLR_ACTIVITY register - Reading the IC_CLR_INTR register - System reset Once this bit is set, it stays set unless one of the four methods is used to clear it. Even if the DW_apb_i2c module is idle, this bit remains set until cleared, indicating that there was activity on the bus. Reset value: 0x0"] pub type ACTIVITY_R = crate::BitReader; impl ACTIVITY_R { #[doc = "Get enumerated values variant"] @@ -388,9 +346,7 @@ impl ACTIVITY_R { *self == ACTIVITY_A::ACTIVE } } -#[doc = "Indicates whether a STOP condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode. - - In Slave Mode: - If IC_CON\\[7\\]=1'b1 (STOP_DET_IFADDRESSED), the STOP_DET interrupt will be issued only if slave is addressed. Note: During a general call address, this slave does not issue a STOP_DET interrupt if STOP_DET_IF_ADDRESSED=1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR). - If IC_CON\\[7\\]=1'b0 (STOP_DET_IFADDRESSED), the STOP_DET interrupt is issued irrespective of whether it is being addressed. In Master Mode: - If IC_CON\\[10\\]=1'b1 (STOP_DET_IF_MASTER_ACTIVE),the STOP_DET interrupt will be issued only if Master is active. - If IC_CON\\[10\\]=1'b0 (STOP_DET_IFADDRESSED),the STOP_DET interrupt will be issued irrespective of whether master is active or not. Reset value: 0x0 +#[doc = "Indicates whether a STOP condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode. In Slave Mode: - If IC_CON\\[7\\]=1'b1 (STOP_DET_IFADDRESSED), the STOP_DET interrupt will be issued only if slave is addressed. Note: During a general call address, this slave does not issue a STOP_DET interrupt if STOP_DET_IF_ADDRESSED=1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR). - If IC_CON\\[7\\]=1'b0 (STOP_DET_IFADDRESSED), the STOP_DET interrupt is issued irrespective of whether it is being addressed. In Master Mode: - If IC_CON\\[10\\]=1'b1 (STOP_DET_IF_MASTER_ACTIVE),the STOP_DET interrupt will be issued only if Master is active. - If IC_CON\\[10\\]=1'b0 (STOP_DET_IFADDRESSED),the STOP_DET interrupt will be issued irrespective of whether master is active or not. Reset value: 0x0 Value on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -406,9 +362,7 @@ impl From for bool { variant as u8 != 0 } } -#[doc = "Field `STOP_DET` reader - Indicates whether a STOP condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode. - - In Slave Mode: - If IC_CON\\[7\\]=1'b1 (STOP_DET_IFADDRESSED), the STOP_DET interrupt will be issued only if slave is addressed. Note: During a general call address, this slave does not issue a STOP_DET interrupt if STOP_DET_IF_ADDRESSED=1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR). - If IC_CON\\[7\\]=1'b0 (STOP_DET_IFADDRESSED), the STOP_DET interrupt is issued irrespective of whether it is being addressed. In Master Mode: - If IC_CON\\[10\\]=1'b1 (STOP_DET_IF_MASTER_ACTIVE),the STOP_DET interrupt will be issued only if Master is active. - If IC_CON\\[10\\]=1'b0 (STOP_DET_IFADDRESSED),the STOP_DET interrupt will be issued irrespective of whether master is active or not. Reset value: 0x0"] +#[doc = "Field `STOP_DET` reader - Indicates whether a STOP condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode. In Slave Mode: - If IC_CON\\[7\\]=1'b1 (STOP_DET_IFADDRESSED), the STOP_DET interrupt will be issued only if slave is addressed. Note: During a general call address, this slave does not issue a STOP_DET interrupt if STOP_DET_IF_ADDRESSED=1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR). - If IC_CON\\[7\\]=1'b0 (STOP_DET_IFADDRESSED), the STOP_DET interrupt is issued irrespective of whether it is being addressed. In Master Mode: - If IC_CON\\[10\\]=1'b1 (STOP_DET_IF_MASTER_ACTIVE),the STOP_DET interrupt will be issued only if Master is active. - If IC_CON\\[10\\]=1'b0 (STOP_DET_IFADDRESSED),the STOP_DET interrupt will be issued irrespective of whether master is active or not. Reset value: 0x0"] pub type STOP_DET_R = crate::BitReader; impl STOP_DET_R { #[doc = "Get enumerated values variant"] @@ -430,9 +384,7 @@ impl STOP_DET_R { *self == STOP_DET_A::ACTIVE } } -#[doc = "Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode. - - Reset value: 0x0 +#[doc = "Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode. Reset value: 0x0 Value on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -448,9 +400,7 @@ impl From for bool { variant as u8 != 0 } } -#[doc = "Field `START_DET` reader - Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode. - - Reset value: 0x0"] +#[doc = "Field `START_DET` reader - Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode. Reset value: 0x0"] pub type START_DET_R = crate::BitReader; impl START_DET_R { #[doc = "Get enumerated values variant"] @@ -472,9 +422,7 @@ impl START_DET_R { *self == START_DET_A::ACTIVE } } -#[doc = "Set only when a General Call address is received and it is acknowledged. It stays set until it is cleared either by disabling DW_apb_i2c or when the CPU reads bit 0 of the IC_CLR_GEN_CALL register. DW_apb_i2c stores the received data in the Rx buffer. - - Reset value: 0x0 +#[doc = "Set only when a General Call address is received and it is acknowledged. It stays set until it is cleared either by disabling DW_apb_i2c or when the CPU reads bit 0 of the IC_CLR_GEN_CALL register. DW_apb_i2c stores the received data in the Rx buffer. Reset value: 0x0 Value on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -490,9 +438,7 @@ impl From for bool { variant as u8 != 0 } } -#[doc = "Field `GEN_CALL` reader - Set only when a General Call address is received and it is acknowledged. It stays set until it is cleared either by disabling DW_apb_i2c or when the CPU reads bit 0 of the IC_CLR_GEN_CALL register. DW_apb_i2c stores the received data in the Rx buffer. - - Reset value: 0x0"] +#[doc = "Field `GEN_CALL` reader - Set only when a General Call address is received and it is acknowledged. It stays set until it is cleared either by disabling DW_apb_i2c or when the CPU reads bit 0 of the IC_CLR_GEN_CALL register. DW_apb_i2c stores the received data in the Rx buffer. Reset value: 0x0"] pub type GEN_CALL_R = crate::BitReader; impl GEN_CALL_R { #[doc = "Get enumerated values variant"] @@ -514,11 +460,7 @@ impl GEN_CALL_R { *self == GEN_CALL_A::ACTIVE } } -#[doc = "Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in Slave mode and the slave is being addressed. Enabled only when IC_SLV_RESTART_DET_EN=1. - - Note: However, in high-speed mode or during a START BYTE transfer, the RESTART comes before the address field as per the I2C protocol. In this case, the slave is not the addressed slave when the RESTART is issued, therefore DW_apb_i2c does not generate the RESTART_DET interrupt. - - Reset value: 0x0 +#[doc = "Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in Slave mode and the slave is being addressed. Enabled only when IC_SLV_RESTART_DET_EN=1. Note: However, in high-speed mode or during a START BYTE transfer, the RESTART comes before the address field as per the I2C protocol. In this case, the slave is not the addressed slave when the RESTART is issued, therefore DW_apb_i2c does not generate the RESTART_DET interrupt. Reset value: 0x0 Value on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -534,11 +476,7 @@ impl From for bool { variant as u8 != 0 } } -#[doc = "Field `RESTART_DET` reader - Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in Slave mode and the slave is being addressed. Enabled only when IC_SLV_RESTART_DET_EN=1. - - Note: However, in high-speed mode or during a START BYTE transfer, the RESTART comes before the address field as per the I2C protocol. In this case, the slave is not the addressed slave when the RESTART is issued, therefore DW_apb_i2c does not generate the RESTART_DET interrupt. - - Reset value: 0x0"] +#[doc = "Field `RESTART_DET` reader - Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in Slave mode and the slave is being addressed. Enabled only when IC_SLV_RESTART_DET_EN=1. Note: However, in high-speed mode or during a START BYTE transfer, the RESTART comes before the address field as per the I2C protocol. In this case, the slave is not the addressed slave when the RESTART is issued, therefore DW_apb_i2c does not generate the RESTART_DET interrupt. Reset value: 0x0"] pub type RESTART_DET_R = crate::BitReader; impl RESTART_DET_R { #[doc = "Get enumerated values variant"] @@ -561,116 +499,89 @@ impl RESTART_DET_R { } } impl R { - #[doc = "Bit 0 - Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register. If the module is disabled (IC_ENABLE\\[0\\]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. - - Reset value: 0x0"] + #[doc = "Bit 0 - Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register. If the module is disabled (IC_ENABLE\\[0\\]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. Reset value: 0x0"] #[inline(always)] pub fn rx_under(&self) -> RX_UNDER_R { RX_UNDER_R::new((self.bits & 1) != 0) } - #[doc = "Bit 1 - Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an additional byte is received from an external I2C device. The DW_apb_i2c acknowledges this, but any data bytes received after the FIFO is full are lost. If the module is disabled (IC_ENABLE\\[0\\]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. - - Note: If bit 9 of the IC_CON register (RX_FIFO_FULL_HLD_CTRL) is programmed to HIGH, then the RX_OVER interrupt never occurs, because the Rx FIFO never overflows. - - Reset value: 0x0"] + #[doc = "Bit 1 - Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an additional byte is received from an external I2C device. The DW_apb_i2c acknowledges this, but any data bytes received after the FIFO is full are lost. If the module is disabled (IC_ENABLE\\[0\\]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. Note: If bit 9 of the IC_CON register (RX_FIFO_FULL_HLD_CTRL) is programmed to HIGH, then the RX_OVER interrupt never occurs, because the Rx FIFO never overflows. Reset value: 0x0"] #[inline(always)] pub fn rx_over(&self) -> RX_OVER_R { RX_OVER_R::new(((self.bits >> 1) & 1) != 0) } - #[doc = "Bit 2 - Set when the receive buffer reaches or goes above the RX_TL threshold in the IC_RX_TL register. It is automatically cleared by hardware when buffer level goes below the threshold. If the module is disabled (IC_ENABLE\\[0\\]=0), the RX FIFO is flushed and held in reset; therefore the RX FIFO is not full. So this bit is cleared once the IC_ENABLE bit 0 is programmed with a 0, regardless of the activity that continues. - - Reset value: 0x0"] + #[doc = "Bit 2 - Set when the receive buffer reaches or goes above the RX_TL threshold in the IC_RX_TL register. It is automatically cleared by hardware when buffer level goes below the threshold. If the module is disabled (IC_ENABLE\\[0\\]=0), the RX FIFO is flushed and held in reset; therefore the RX FIFO is not full. So this bit is cleared once the IC_ENABLE bit 0 is programmed with a 0, regardless of the activity that continues. Reset value: 0x0"] #[inline(always)] pub fn rx_full(&self) -> RX_FULL_R { RX_FULL_R::new(((self.bits >> 2) & 1) != 0) } - #[doc = "Bit 3 - Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register. When the module is disabled, this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. - - Reset value: 0x0"] + #[doc = "Bit 3 - Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register. When the module is disabled, this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. Reset value: 0x0"] #[inline(always)] pub fn tx_over(&self) -> TX_OVER_R { TX_OVER_R::new(((self.bits >> 3) & 1) != 0) } #[doc = "Bit 4 - The behavior of the TX_EMPTY interrupt status differs based on the TX_EMPTY_CTRL selection in the IC_CON register. - When TX_EMPTY_CTRL = 0: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register. - When TX_EMPTY_CTRL = 1: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register and the transmission of the address/data from the internal shift register for the most recently popped command is completed. It is automatically cleared by hardware when the buffer level goes above the threshold. When IC_ENABLE\\[0\\] -is set to 0, the TX FIFO is flushed and held in reset. There the TX FIFO looks like it has no data within it, so this bit is set to 1, provided there is activity in the master or slave state machines. When there is no longer any activity, then with ic_en=0, this bit is set to 0. - - Reset value: 0x0."] +is set to 0, the TX FIFO is flushed and held in reset. There the TX FIFO looks like it has no data within it, so this bit is set to 1, provided there is activity in the master or slave state machines. When there is no longer any activity, then with ic_en=0, this bit is set to 0. Reset value: 0x0."] #[inline(always)] pub fn tx_empty(&self) -> TX_EMPTY_R { TX_EMPTY_R::new(((self.bits >> 4) & 1) != 0) } - #[doc = "Bit 5 - This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C master is attempting to read data from DW_apb_i2c. The DW_apb_i2c holds the I2C bus in a wait state (SCL=0) until this interrupt is serviced, which means that the slave has been addressed by a remote master that is asking for data to be transferred. The processor must respond to this interrupt and then write the requested data to the IC_DATA_CMD register. This bit is set to 0 just after the processor reads the IC_CLR_RD_REQ register. - - Reset value: 0x0"] + #[doc = "Bit 5 - This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C master is attempting to read data from DW_apb_i2c. The DW_apb_i2c holds the I2C bus in a wait state (SCL=0) until this interrupt is serviced, which means that the slave has been addressed by a remote master that is asking for data to be transferred. The processor must respond to this interrupt and then write the requested data to the IC_DATA_CMD register. This bit is set to 0 just after the processor reads the IC_CLR_RD_REQ register. Reset value: 0x0"] #[inline(always)] pub fn rd_req(&self) -> RD_REQ_R { RD_REQ_R::new(((self.bits >> 5) & 1) != 0) } - #[doc = "Bit 6 - This bit indicates if DW_apb_i2c, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO. This situation can occur both as an I2C master or an I2C slave, and is referred to as a 'transmit abort'. When this bit is set to 1, the IC_TX_ABRT_SOURCE register indicates the reason why the transmit abort takes places. - - Note: The DW_apb_i2c flushes/resets/empties the TX_FIFO and RX_FIFO whenever there is a transmit abort caused by any of the events tracked by the IC_TX_ABRT_SOURCE register. The FIFOs remains in this flushed state until the register IC_CLR_TX_ABRT is read. Once this read is performed, the Tx FIFO is then ready to accept more data bytes from the APB interface. - - Reset value: 0x0"] + #[doc = "Bit 6 - This bit indicates if DW_apb_i2c, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO. This situation can occur both as an I2C master or an I2C slave, and is referred to as a 'transmit abort'. When this bit is set to 1, the IC_TX_ABRT_SOURCE register indicates the reason why the transmit abort takes places. Note: The DW_apb_i2c flushes/resets/empties the TX_FIFO and RX_FIFO whenever there is a transmit abort caused by any of the events tracked by the IC_TX_ABRT_SOURCE register. The FIFOs remains in this flushed state until the register IC_CLR_TX_ABRT is read. Once this read is performed, the Tx FIFO is then ready to accept more data bytes from the APB interface. Reset value: 0x0"] #[inline(always)] pub fn tx_abrt(&self) -> TX_ABRT_R { TX_ABRT_R::new(((self.bits >> 6) & 1) != 0) } - #[doc = "Bit 7 - When the DW_apb_i2c is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte. This occurs on the last byte of the transmission, indicating that the transmission is done. - - Reset value: 0x0"] + #[doc = "Bit 7 - When the DW_apb_i2c is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte. This occurs on the last byte of the transmission, indicating that the transmission is done. Reset value: 0x0"] #[inline(always)] pub fn rx_done(&self) -> RX_DONE_R { RX_DONE_R::new(((self.bits >> 7) & 1) != 0) } - #[doc = "Bit 8 - This bit captures DW_apb_i2c activity and stays set until it is cleared. There are four ways to clear it: - Disabling the DW_apb_i2c - Reading the IC_CLR_ACTIVITY register - Reading the IC_CLR_INTR register - System reset Once this bit is set, it stays set unless one of the four methods is used to clear it. Even if the DW_apb_i2c module is idle, this bit remains set until cleared, indicating that there was activity on the bus. - - Reset value: 0x0"] + #[doc = "Bit 8 - This bit captures DW_apb_i2c activity and stays set until it is cleared. There are four ways to clear it: - Disabling the DW_apb_i2c - Reading the IC_CLR_ACTIVITY register - Reading the IC_CLR_INTR register - System reset Once this bit is set, it stays set unless one of the four methods is used to clear it. Even if the DW_apb_i2c module is idle, this bit remains set until cleared, indicating that there was activity on the bus. Reset value: 0x0"] #[inline(always)] pub fn activity(&self) -> ACTIVITY_R { ACTIVITY_R::new(((self.bits >> 8) & 1) != 0) } - #[doc = "Bit 9 - Indicates whether a STOP condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode. - - In Slave Mode: - If IC_CON\\[7\\]=1'b1 (STOP_DET_IFADDRESSED), the STOP_DET interrupt will be issued only if slave is addressed. Note: During a general call address, this slave does not issue a STOP_DET interrupt if STOP_DET_IF_ADDRESSED=1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR). - If IC_CON\\[7\\]=1'b0 (STOP_DET_IFADDRESSED), the STOP_DET interrupt is issued irrespective of whether it is being addressed. In Master Mode: - If IC_CON\\[10\\]=1'b1 (STOP_DET_IF_MASTER_ACTIVE),the STOP_DET interrupt will be issued only if Master is active. - If IC_CON\\[10\\]=1'b0 (STOP_DET_IFADDRESSED),the STOP_DET interrupt will be issued irrespective of whether master is active or not. Reset value: 0x0"] + #[doc = "Bit 9 - Indicates whether a STOP condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode. In Slave Mode: - If IC_CON\\[7\\]=1'b1 (STOP_DET_IFADDRESSED), the STOP_DET interrupt will be issued only if slave is addressed. Note: During a general call address, this slave does not issue a STOP_DET interrupt if STOP_DET_IF_ADDRESSED=1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR). - If IC_CON\\[7\\]=1'b0 (STOP_DET_IFADDRESSED), the STOP_DET interrupt is issued irrespective of whether it is being addressed. In Master Mode: - If IC_CON\\[10\\]=1'b1 (STOP_DET_IF_MASTER_ACTIVE),the STOP_DET interrupt will be issued only if Master is active. - If IC_CON\\[10\\]=1'b0 (STOP_DET_IFADDRESSED),the STOP_DET interrupt will be issued irrespective of whether master is active or not. Reset value: 0x0"] #[inline(always)] pub fn stop_det(&self) -> STOP_DET_R { STOP_DET_R::new(((self.bits >> 9) & 1) != 0) } - #[doc = "Bit 10 - Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode. - - Reset value: 0x0"] + #[doc = "Bit 10 - Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode. Reset value: 0x0"] #[inline(always)] pub fn start_det(&self) -> START_DET_R { START_DET_R::new(((self.bits >> 10) & 1) != 0) } - #[doc = "Bit 11 - Set only when a General Call address is received and it is acknowledged. It stays set until it is cleared either by disabling DW_apb_i2c or when the CPU reads bit 0 of the IC_CLR_GEN_CALL register. DW_apb_i2c stores the received data in the Rx buffer. - - Reset value: 0x0"] + #[doc = "Bit 11 - Set only when a General Call address is received and it is acknowledged. It stays set until it is cleared either by disabling DW_apb_i2c or when the CPU reads bit 0 of the IC_CLR_GEN_CALL register. DW_apb_i2c stores the received data in the Rx buffer. Reset value: 0x0"] #[inline(always)] pub fn gen_call(&self) -> GEN_CALL_R { GEN_CALL_R::new(((self.bits >> 11) & 1) != 0) } - #[doc = "Bit 12 - Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in Slave mode and the slave is being addressed. Enabled only when IC_SLV_RESTART_DET_EN=1. - - Note: However, in high-speed mode or during a START BYTE transfer, the RESTART comes before the address field as per the I2C protocol. In this case, the slave is not the addressed slave when the RESTART is issued, therefore DW_apb_i2c does not generate the RESTART_DET interrupt. - - Reset value: 0x0"] + #[doc = "Bit 12 - Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in Slave mode and the slave is being addressed. Enabled only when IC_SLV_RESTART_DET_EN=1. Note: However, in high-speed mode or during a START BYTE transfer, the RESTART comes before the address field as per the I2C protocol. In this case, the slave is not the addressed slave when the RESTART is issued, therefore DW_apb_i2c does not generate the RESTART_DET interrupt. Reset value: 0x0"] #[inline(always)] pub fn restart_det(&self) -> RESTART_DET_R { RESTART_DET_R::new(((self.bits >> 12) & 1) != 0) } } -#[doc = "I2C Raw Interrupt Status Register - - Unlike the IC_INTR_STAT register, these bits are not masked so they always show the true status of the DW_apb_i2c. +impl W {} +#[doc = "I2C Raw Interrupt Status Register Unlike the IC_INTR_STAT register, these bits are not masked so they always show the true status of the DW_apb_i2c. -You can [`read`](crate::generic::Reg::read) this register and get [`ic_raw_intr_stat::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`ic_raw_intr_stat::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_raw_intr_stat::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IC_RAW_INTR_STAT_SPEC; impl crate::RegisterSpec for IC_RAW_INTR_STAT_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`ic_raw_intr_stat::R`](R) reader structure"] impl crate::Readable for IC_RAW_INTR_STAT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ic_raw_intr_stat::W`](W) writer structure"] +impl crate::Writable for IC_RAW_INTR_STAT_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets IC_RAW_INTR_STAT to value 0"] impl crate::Resettable for IC_RAW_INTR_STAT_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/i2c0/ic_rx_tl.rs b/src/i2c0/ic_rx_tl.rs index bc573d9c7..2c19cf76c 100644 --- a/src/i2c0/ic_rx_tl.rs +++ b/src/i2c0/ic_rx_tl.rs @@ -2,27 +2,19 @@ pub type R = crate::R; #[doc = "Register `IC_RX_TL` writer"] pub type W = crate::W; -#[doc = "Field `RX_TL` reader - Receive FIFO Threshold Level. - - Controls the level of entries (or above) that triggers the RX_FULL interrupt (bit 2 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that hardware does not allow this value to be set to a value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 1 entry, and a value of 255 sets the threshold for 256 entries."] +#[doc = "Field `RX_TL` reader - Receive FIFO Threshold Level. Controls the level of entries (or above) that triggers the RX_FULL interrupt (bit 2 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that hardware does not allow this value to be set to a value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 1 entry, and a value of 255 sets the threshold for 256 entries."] pub type RX_TL_R = crate::FieldReader; -#[doc = "Field `RX_TL` writer - Receive FIFO Threshold Level. - - Controls the level of entries (or above) that triggers the RX_FULL interrupt (bit 2 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that hardware does not allow this value to be set to a value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 1 entry, and a value of 255 sets the threshold for 256 entries."] +#[doc = "Field `RX_TL` writer - Receive FIFO Threshold Level. Controls the level of entries (or above) that triggers the RX_FULL interrupt (bit 2 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that hardware does not allow this value to be set to a value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 1 entry, and a value of 255 sets the threshold for 256 entries."] pub type RX_TL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { - #[doc = "Bits 0:7 - Receive FIFO Threshold Level. - - Controls the level of entries (or above) that triggers the RX_FULL interrupt (bit 2 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that hardware does not allow this value to be set to a value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 1 entry, and a value of 255 sets the threshold for 256 entries."] + #[doc = "Bits 0:7 - Receive FIFO Threshold Level. Controls the level of entries (or above) that triggers the RX_FULL interrupt (bit 2 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that hardware does not allow this value to be set to a value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 1 entry, and a value of 255 sets the threshold for 256 entries."] #[inline(always)] pub fn rx_tl(&self) -> RX_TL_R { RX_TL_R::new((self.bits & 0xff) as u8) } } impl W { - #[doc = "Bits 0:7 - Receive FIFO Threshold Level. - - Controls the level of entries (or above) that triggers the RX_FULL interrupt (bit 2 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that hardware does not allow this value to be set to a value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 1 entry, and a value of 255 sets the threshold for 256 entries."] + #[doc = "Bits 0:7 - Receive FIFO Threshold Level. Controls the level of entries (or above) that triggers the RX_FULL interrupt (bit 2 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that hardware does not allow this value to be set to a value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 1 entry, and a value of 255 sets the threshold for 256 entries."] #[inline(always)] #[must_use] pub fn rx_tl(&mut self) -> RX_TL_W { diff --git a/src/i2c0/ic_rxflr.rs b/src/i2c0/ic_rxflr.rs index 93f75cb4f..8028ecad1 100644 --- a/src/i2c0/ic_rxflr.rs +++ b/src/i2c0/ic_rxflr.rs @@ -1,27 +1,32 @@ #[doc = "Register `IC_RXFLR` reader"] pub type R = crate::R; -#[doc = "Field `RXFLR` reader - Receive FIFO Level. Contains the number of valid data entries in the receive FIFO. - - Reset value: 0x0"] +#[doc = "Register `IC_RXFLR` writer"] +pub type W = crate::W; +#[doc = "Field `RXFLR` reader - Receive FIFO Level. Contains the number of valid data entries in the receive FIFO. Reset value: 0x0"] pub type RXFLR_R = crate::FieldReader; impl R { - #[doc = "Bits 0:4 - Receive FIFO Level. Contains the number of valid data entries in the receive FIFO. - - Reset value: 0x0"] + #[doc = "Bits 0:4 - Receive FIFO Level. Contains the number of valid data entries in the receive FIFO. Reset value: 0x0"] #[inline(always)] pub fn rxflr(&self) -> RXFLR_R { RXFLR_R::new((self.bits & 0x1f) as u8) } } +impl W {} #[doc = "I2C Receive FIFO Level Register This register contains the number of valid data entries in the receive FIFO buffer. It is cleared whenever: - The I2C is disabled - Whenever there is a transmit abort caused by any of the events tracked in IC_TX_ABRT_SOURCE The register increments whenever data is placed into the receive FIFO and decrements when data is taken from the receive FIFO. -You can [`read`](crate::generic::Reg::read) this register and get [`ic_rxflr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`ic_rxflr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_rxflr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IC_RXFLR_SPEC; impl crate::RegisterSpec for IC_RXFLR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`ic_rxflr::R`](R) reader structure"] impl crate::Readable for IC_RXFLR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ic_rxflr::W`](W) writer structure"] +impl crate::Writable for IC_RXFLR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets IC_RXFLR to value 0"] impl crate::Resettable for IC_RXFLR_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/i2c0/ic_sar.rs b/src/i2c0/ic_sar.rs index ea3e58ee4..fc57002b1 100644 --- a/src/i2c0/ic_sar.rs +++ b/src/i2c0/ic_sar.rs @@ -3,29 +3,17 @@ pub type R = crate::R; #[doc = "Register `IC_SAR` writer"] pub type W = crate::W; #[doc = "Field `IC_SAR` reader - The IC_SAR holds the slave address when the I2C is operating as a slave. For 7-bit addressing, only IC_SAR\\[6:0\\] -is used. - - This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE\\[0\\] -register being set to 0. Writes at other times have no effect. - - Note: The default values cannot be any of the reserved address locations: that is, 0x00 to 0x07, or 0x78 to 0x7f. The correct operation of the device is not guaranteed if you program the IC_SAR or IC_TAR to a reserved value. Refer to <<table_I2C_firstbyte_bit_defs>> for a complete list of these reserved values."] +is used. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE\\[0\\] +register being set to 0. Writes at other times have no effect. Note: The default values cannot be any of the reserved address locations: that is, 0x00 to 0x07, or 0x78 to 0x7f. The correct operation of the device is not guaranteed if you program the IC_SAR or IC_TAR to a reserved value. Refer to <<table_I2C_firstbyte_bit_defs>> for a complete list of these reserved values."] pub type IC_SAR_R = crate::FieldReader; #[doc = "Field `IC_SAR` writer - The IC_SAR holds the slave address when the I2C is operating as a slave. For 7-bit addressing, only IC_SAR\\[6:0\\] -is used. - - This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE\\[0\\] -register being set to 0. Writes at other times have no effect. - - Note: The default values cannot be any of the reserved address locations: that is, 0x00 to 0x07, or 0x78 to 0x7f. The correct operation of the device is not guaranteed if you program the IC_SAR or IC_TAR to a reserved value. Refer to <<table_I2C_firstbyte_bit_defs>> for a complete list of these reserved values."] +is used. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE\\[0\\] +register being set to 0. Writes at other times have no effect. Note: The default values cannot be any of the reserved address locations: that is, 0x00 to 0x07, or 0x78 to 0x7f. The correct operation of the device is not guaranteed if you program the IC_SAR or IC_TAR to a reserved value. Refer to <<table_I2C_firstbyte_bit_defs>> for a complete list of these reserved values."] pub type IC_SAR_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; impl R { #[doc = "Bits 0:9 - The IC_SAR holds the slave address when the I2C is operating as a slave. For 7-bit addressing, only IC_SAR\\[6:0\\] -is used. - - This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE\\[0\\] -register being set to 0. Writes at other times have no effect. - - Note: The default values cannot be any of the reserved address locations: that is, 0x00 to 0x07, or 0x78 to 0x7f. The correct operation of the device is not guaranteed if you program the IC_SAR or IC_TAR to a reserved value. Refer to <<table_I2C_firstbyte_bit_defs>> for a complete list of these reserved values."] +is used. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE\\[0\\] +register being set to 0. Writes at other times have no effect. Note: The default values cannot be any of the reserved address locations: that is, 0x00 to 0x07, or 0x78 to 0x7f. The correct operation of the device is not guaranteed if you program the IC_SAR or IC_TAR to a reserved value. Refer to <<table_I2C_firstbyte_bit_defs>> for a complete list of these reserved values."] #[inline(always)] pub fn ic_sar(&self) -> IC_SAR_R { IC_SAR_R::new((self.bits & 0x03ff) as u16) @@ -33,12 +21,8 @@ register being set to 0. Writes at other times have no effect. } impl W { #[doc = "Bits 0:9 - The IC_SAR holds the slave address when the I2C is operating as a slave. For 7-bit addressing, only IC_SAR\\[6:0\\] -is used. - - This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE\\[0\\] -register being set to 0. Writes at other times have no effect. - - Note: The default values cannot be any of the reserved address locations: that is, 0x00 to 0x07, or 0x78 to 0x7f. The correct operation of the device is not guaranteed if you program the IC_SAR or IC_TAR to a reserved value. Refer to <<table_I2C_firstbyte_bit_defs>> for a complete list of these reserved values."] +is used. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE\\[0\\] +register being set to 0. Writes at other times have no effect. Note: The default values cannot be any of the reserved address locations: that is, 0x00 to 0x07, or 0x78 to 0x7f. The correct operation of the device is not guaranteed if you program the IC_SAR or IC_TAR to a reserved value. Refer to <<table_I2C_firstbyte_bit_defs>> for a complete list of these reserved values."] #[inline(always)] #[must_use] pub fn ic_sar(&mut self) -> IC_SAR_W { diff --git a/src/i2c0/ic_sda_hold.rs b/src/i2c0/ic_sda_hold.rs index 60f8bddc2..f97b86d2d 100644 --- a/src/i2c0/ic_sda_hold.rs +++ b/src/i2c0/ic_sda_hold.rs @@ -2,69 +2,43 @@ pub type R = crate::R; #[doc = "Register `IC_SDA_HOLD` writer"] pub type W = crate::W; -#[doc = "Field `IC_SDA_TX_HOLD` reader - Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a transmitter. - - Reset value: IC_DEFAULT_SDA_HOLD\\[15:0\\]."] +#[doc = "Field `IC_SDA_TX_HOLD` reader - Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a transmitter. Reset value: IC_DEFAULT_SDA_HOLD\\[15:0\\]."] pub type IC_SDA_TX_HOLD_R = crate::FieldReader; -#[doc = "Field `IC_SDA_TX_HOLD` writer - Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a transmitter. - - Reset value: IC_DEFAULT_SDA_HOLD\\[15:0\\]."] +#[doc = "Field `IC_SDA_TX_HOLD` writer - Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a transmitter. Reset value: IC_DEFAULT_SDA_HOLD\\[15:0\\]."] pub type IC_SDA_TX_HOLD_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; -#[doc = "Field `IC_SDA_RX_HOLD` reader - Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a receiver. - - Reset value: IC_DEFAULT_SDA_HOLD\\[23:16\\]."] +#[doc = "Field `IC_SDA_RX_HOLD` reader - Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a receiver. Reset value: IC_DEFAULT_SDA_HOLD\\[23:16\\]."] pub type IC_SDA_RX_HOLD_R = crate::FieldReader; -#[doc = "Field `IC_SDA_RX_HOLD` writer - Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a receiver. - - Reset value: IC_DEFAULT_SDA_HOLD\\[23:16\\]."] +#[doc = "Field `IC_SDA_RX_HOLD` writer - Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a receiver. Reset value: IC_DEFAULT_SDA_HOLD\\[23:16\\]."] pub type IC_SDA_RX_HOLD_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { - #[doc = "Bits 0:15 - Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a transmitter. - - Reset value: IC_DEFAULT_SDA_HOLD\\[15:0\\]."] + #[doc = "Bits 0:15 - Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a transmitter. Reset value: IC_DEFAULT_SDA_HOLD\\[15:0\\]."] #[inline(always)] pub fn ic_sda_tx_hold(&self) -> IC_SDA_TX_HOLD_R { IC_SDA_TX_HOLD_R::new((self.bits & 0xffff) as u16) } - #[doc = "Bits 16:23 - Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a receiver. - - Reset value: IC_DEFAULT_SDA_HOLD\\[23:16\\]."] + #[doc = "Bits 16:23 - Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a receiver. Reset value: IC_DEFAULT_SDA_HOLD\\[23:16\\]."] #[inline(always)] pub fn ic_sda_rx_hold(&self) -> IC_SDA_RX_HOLD_R { IC_SDA_RX_HOLD_R::new(((self.bits >> 16) & 0xff) as u8) } } impl W { - #[doc = "Bits 0:15 - Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a transmitter. - - Reset value: IC_DEFAULT_SDA_HOLD\\[15:0\\]."] + #[doc = "Bits 0:15 - Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a transmitter. Reset value: IC_DEFAULT_SDA_HOLD\\[15:0\\]."] #[inline(always)] #[must_use] pub fn ic_sda_tx_hold(&mut self) -> IC_SDA_TX_HOLD_W { IC_SDA_TX_HOLD_W::new(self, 0) } - #[doc = "Bits 16:23 - Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a receiver. - - Reset value: IC_DEFAULT_SDA_HOLD\\[23:16\\]."] + #[doc = "Bits 16:23 - Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a receiver. Reset value: IC_DEFAULT_SDA_HOLD\\[23:16\\]."] #[inline(always)] #[must_use] pub fn ic_sda_rx_hold(&mut self) -> IC_SDA_RX_HOLD_W { IC_SDA_RX_HOLD_W::new(self, 16) } } -#[doc = "I2C SDA Hold Time Length Register - - The bits \\[15:0\\] -of this register are used to control the hold time of SDA during transmit in both slave and master mode (after SCL goes from HIGH to LOW). - - The bits \\[23:16\\] -of this register are used to extend the SDA transition (if any) whenever SCL is HIGH in the receiver in either master or slave mode. - - Writes to this register succeed only when IC_ENABLE\\[0\\]=0. - - The values in this register are in units of ic_clk period. The value programmed in IC_SDA_TX_HOLD must be greater than the minimum hold time in each mode (one cycle in master mode, seven cycles in slave mode) for the value to be implemented. - - The programmed SDA hold time during transmit (IC_SDA_TX_HOLD) cannot exceed at any time the duration of the low part of scl. Therefore the programmed value cannot be larger than N_SCL_LOW-2, where N_SCL_LOW is the duration of the low part of the scl period measured in ic_clk cycles. +#[doc = "I2C SDA Hold Time Length Register The bits \\[15:0\\] +of this register are used to control the hold time of SDA during transmit in both slave and master mode (after SCL goes from HIGH to LOW). The bits \\[23:16\\] +of this register are used to extend the SDA transition (if any) whenever SCL is HIGH in the receiver in either master or slave mode. Writes to this register succeed only when IC_ENABLE\\[0\\]=0. The values in this register are in units of ic_clk period. The value programmed in IC_SDA_TX_HOLD must be greater than the minimum hold time in each mode (one cycle in master mode, seven cycles in slave mode) for the value to be implemented. The programmed SDA hold time during transmit (IC_SDA_TX_HOLD) cannot exceed at any time the duration of the low part of scl. Therefore the programmed value cannot be larger than N_SCL_LOW-2, where N_SCL_LOW is the duration of the low part of the scl period measured in ic_clk cycles. You can [`read`](crate::generic::Reg::read) this register and get [`ic_sda_hold::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_sda_hold::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IC_SDA_HOLD_SPEC; diff --git a/src/i2c0/ic_sda_setup.rs b/src/i2c0/ic_sda_setup.rs index d6d02c3ba..20fe6d5c4 100644 --- a/src/i2c0/ic_sda_setup.rs +++ b/src/i2c0/ic_sda_setup.rs @@ -21,14 +21,8 @@ impl W { SDA_SETUP_W::new(self, 0) } } -#[doc = "I2C SDA Setup Register - - This register controls the amount of time delay (in terms of number of ic_clk clock periods) introduced in the rising edge of SCL - relative to SDA changing - when DW_apb_i2c services a read request in a slave-transmitter operation. The relevant I2C requirement is tSU:DAT (note 4) as detailed in the I2C Bus Specification. This register must be programmed with a value equal to or greater than 2. - - Writes to this register succeed only when IC_ENABLE\\[0\\] -= 0. - - Note: The length of setup time is calculated using \\[(IC_SDA_SETUP - 1) * (ic_clk_period)\\], so if the user requires 10 ic_clk periods of setup time, they should program a value of 11. The IC_SDA_SETUP register is only used by the DW_apb_i2c when operating as a slave transmitter. +#[doc = "I2C SDA Setup Register This register controls the amount of time delay (in terms of number of ic_clk clock periods) introduced in the rising edge of SCL - relative to SDA changing - when DW_apb_i2c services a read request in a slave-transmitter operation. The relevant I2C requirement is tSU:DAT (note 4) as detailed in the I2C Bus Specification. This register must be programmed with a value equal to or greater than 2. Writes to this register succeed only when IC_ENABLE\\[0\\] += 0. Note: The length of setup time is calculated using \\[(IC_SDA_SETUP - 1) * (ic_clk_period)\\], so if the user requires 10 ic_clk periods of setup time, they should program a value of 11. The IC_SDA_SETUP register is only used by the DW_apb_i2c when operating as a slave transmitter. You can [`read`](crate::generic::Reg::read) this register and get [`ic_sda_setup::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_sda_setup::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IC_SDA_SETUP_SPEC; diff --git a/src/i2c0/ic_slv_data_nack_only.rs b/src/i2c0/ic_slv_data_nack_only.rs index beb7e06bb..71e88021c 100644 --- a/src/i2c0/ic_slv_data_nack_only.rs +++ b/src/i2c0/ic_slv_data_nack_only.rs @@ -2,9 +2,7 @@ pub type R = crate::R; #[doc = "Register `IC_SLV_DATA_NACK_ONLY` writer"] pub type W = crate::W; -#[doc = "Generate NACK. This NACK generation only occurs when DW_apb_i2c is a slave-receiver. If this register is set to a value of 1, it can only generate a NACK after a data byte is received; hence, the data transfer is aborted and the data received is not pushed to the receive buffer. - - When the register is set to a value of 0, it generates NACK/ACK, depending on normal criteria. - 1: generate NACK after data byte received - 0: generate NACK/ACK normally Reset value: 0x0 +#[doc = "Generate NACK. This NACK generation only occurs when DW_apb_i2c is a slave-receiver. If this register is set to a value of 1, it can only generate a NACK after a data byte is received; hence, the data transfer is aborted and the data received is not pushed to the receive buffer. When the register is set to a value of 0, it generates NACK/ACK, depending on normal criteria. - 1: generate NACK after data byte received - 0: generate NACK/ACK normally Reset value: 0x0 Value on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -20,9 +18,7 @@ impl From for bool { variant as u8 != 0 } } -#[doc = "Field `NACK` reader - Generate NACK. This NACK generation only occurs when DW_apb_i2c is a slave-receiver. If this register is set to a value of 1, it can only generate a NACK after a data byte is received; hence, the data transfer is aborted and the data received is not pushed to the receive buffer. - - When the register is set to a value of 0, it generates NACK/ACK, depending on normal criteria. - 1: generate NACK after data byte received - 0: generate NACK/ACK normally Reset value: 0x0"] +#[doc = "Field `NACK` reader - Generate NACK. This NACK generation only occurs when DW_apb_i2c is a slave-receiver. If this register is set to a value of 1, it can only generate a NACK after a data byte is received; hence, the data transfer is aborted and the data received is not pushed to the receive buffer. When the register is set to a value of 0, it generates NACK/ACK, depending on normal criteria. - 1: generate NACK after data byte received - 0: generate NACK/ACK normally Reset value: 0x0"] pub type NACK_R = crate::BitReader; impl NACK_R { #[doc = "Get enumerated values variant"] @@ -44,9 +40,7 @@ impl NACK_R { *self == NACK_A::ENABLED } } -#[doc = "Field `NACK` writer - Generate NACK. This NACK generation only occurs when DW_apb_i2c is a slave-receiver. If this register is set to a value of 1, it can only generate a NACK after a data byte is received; hence, the data transfer is aborted and the data received is not pushed to the receive buffer. - - When the register is set to a value of 0, it generates NACK/ACK, depending on normal criteria. - 1: generate NACK after data byte received - 0: generate NACK/ACK normally Reset value: 0x0"] +#[doc = "Field `NACK` writer - Generate NACK. This NACK generation only occurs when DW_apb_i2c is a slave-receiver. If this register is set to a value of 1, it can only generate a NACK after a data byte is received; hence, the data transfer is aborted and the data received is not pushed to the receive buffer. When the register is set to a value of 0, it generates NACK/ACK, depending on normal criteria. - 1: generate NACK after data byte received - 0: generate NACK/ACK normally Reset value: 0x0"] pub type NACK_W<'a, REG> = crate::BitWriter<'a, REG, NACK_A>; impl<'a, REG> NACK_W<'a, REG> where @@ -64,29 +58,21 @@ where } } impl R { - #[doc = "Bit 0 - Generate NACK. This NACK generation only occurs when DW_apb_i2c is a slave-receiver. If this register is set to a value of 1, it can only generate a NACK after a data byte is received; hence, the data transfer is aborted and the data received is not pushed to the receive buffer. - - When the register is set to a value of 0, it generates NACK/ACK, depending on normal criteria. - 1: generate NACK after data byte received - 0: generate NACK/ACK normally Reset value: 0x0"] + #[doc = "Bit 0 - Generate NACK. This NACK generation only occurs when DW_apb_i2c is a slave-receiver. If this register is set to a value of 1, it can only generate a NACK after a data byte is received; hence, the data transfer is aborted and the data received is not pushed to the receive buffer. When the register is set to a value of 0, it generates NACK/ACK, depending on normal criteria. - 1: generate NACK after data byte received - 0: generate NACK/ACK normally Reset value: 0x0"] #[inline(always)] pub fn nack(&self) -> NACK_R { NACK_R::new((self.bits & 1) != 0) } } impl W { - #[doc = "Bit 0 - Generate NACK. This NACK generation only occurs when DW_apb_i2c is a slave-receiver. If this register is set to a value of 1, it can only generate a NACK after a data byte is received; hence, the data transfer is aborted and the data received is not pushed to the receive buffer. - - When the register is set to a value of 0, it generates NACK/ACK, depending on normal criteria. - 1: generate NACK after data byte received - 0: generate NACK/ACK normally Reset value: 0x0"] + #[doc = "Bit 0 - Generate NACK. This NACK generation only occurs when DW_apb_i2c is a slave-receiver. If this register is set to a value of 1, it can only generate a NACK after a data byte is received; hence, the data transfer is aborted and the data received is not pushed to the receive buffer. When the register is set to a value of 0, it generates NACK/ACK, depending on normal criteria. - 1: generate NACK after data byte received - 0: generate NACK/ACK normally Reset value: 0x0"] #[inline(always)] #[must_use] pub fn nack(&mut self) -> NACK_W { NACK_W::new(self, 0) } } -#[doc = "Generate Slave Data NACK Register - - The register is used to generate a NACK for the data part of a transfer when DW_apb_i2c is acting as a slave-receiver. This register only exists when the IC_SLV_DATA_NACK_ONLY parameter is set to 1. When this parameter disabled, this register does not exist and writing to the register's address has no effect. - - A write can occur on this register if both of the following conditions are met: - DW_apb_i2c is disabled (IC_ENABLE\\[0\\] +#[doc = "Generate Slave Data NACK Register The register is used to generate a NACK for the data part of a transfer when DW_apb_i2c is acting as a slave-receiver. This register only exists when the IC_SLV_DATA_NACK_ONLY parameter is set to 1. When this parameter disabled, this register does not exist and writing to the register's address has no effect. A write can occur on this register if both of the following conditions are met: - DW_apb_i2c is disabled (IC_ENABLE\\[0\\] = 0) - Slave part is inactive (IC_STATUS\\[6\\] = 0) Note: The IC_STATUS\\[6\\] is a register read-back location for the internal slv_activity signal; the user should poll this before writing the ic_slv_data_nack_only bit. diff --git a/src/i2c0/ic_ss_scl_hcnt.rs b/src/i2c0/ic_ss_scl_hcnt.rs index f6272e5c5..13cf99275 100644 --- a/src/i2c0/ic_ss_scl_hcnt.rs +++ b/src/i2c0/ic_ss_scl_hcnt.rs @@ -2,47 +2,23 @@ pub type R = crate::R; #[doc = "Register `IC_SS_SCL_HCNT` writer"] pub type W = crate::W; -#[doc = "Field `IC_SS_SCL_HCNT` reader - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration'. - - This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE\\[0\\] -register being set to 0. Writes at other times have no effect. - - The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. - - NOTE: This register must not be programmed to a value higher than 65525, because DW_apb_i2c uses a 16-bit counter to flag an I2C bus idle condition when this counter reaches a value of IC_SS_SCL_HCNT + 10."] +#[doc = "Field `IC_SS_SCL_HCNT` reader - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration'. This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE\\[0\\] +register being set to 0. Writes at other times have no effect. The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. NOTE: This register must not be programmed to a value higher than 65525, because DW_apb_i2c uses a 16-bit counter to flag an I2C bus idle condition when this counter reaches a value of IC_SS_SCL_HCNT + 10."] pub type IC_SS_SCL_HCNT_R = crate::FieldReader; -#[doc = "Field `IC_SS_SCL_HCNT` writer - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration'. - - This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE\\[0\\] -register being set to 0. Writes at other times have no effect. - - The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. - - NOTE: This register must not be programmed to a value higher than 65525, because DW_apb_i2c uses a 16-bit counter to flag an I2C bus idle condition when this counter reaches a value of IC_SS_SCL_HCNT + 10."] +#[doc = "Field `IC_SS_SCL_HCNT` writer - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration'. This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE\\[0\\] +register being set to 0. Writes at other times have no effect. The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. NOTE: This register must not be programmed to a value higher than 65525, because DW_apb_i2c uses a 16-bit counter to flag an I2C bus idle condition when this counter reaches a value of IC_SS_SCL_HCNT + 10."] pub type IC_SS_SCL_HCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; impl R { - #[doc = "Bits 0:15 - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration'. - - This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE\\[0\\] -register being set to 0. Writes at other times have no effect. - - The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. - - NOTE: This register must not be programmed to a value higher than 65525, because DW_apb_i2c uses a 16-bit counter to flag an I2C bus idle condition when this counter reaches a value of IC_SS_SCL_HCNT + 10."] + #[doc = "Bits 0:15 - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration'. This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE\\[0\\] +register being set to 0. Writes at other times have no effect. The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. NOTE: This register must not be programmed to a value higher than 65525, because DW_apb_i2c uses a 16-bit counter to flag an I2C bus idle condition when this counter reaches a value of IC_SS_SCL_HCNT + 10."] #[inline(always)] pub fn ic_ss_scl_hcnt(&self) -> IC_SS_SCL_HCNT_R { IC_SS_SCL_HCNT_R::new((self.bits & 0xffff) as u16) } } impl W { - #[doc = "Bits 0:15 - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration'. - - This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE\\[0\\] -register being set to 0. Writes at other times have no effect. - - The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. - - NOTE: This register must not be programmed to a value higher than 65525, because DW_apb_i2c uses a 16-bit counter to flag an I2C bus idle condition when this counter reaches a value of IC_SS_SCL_HCNT + 10."] + #[doc = "Bits 0:15 - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration'. This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE\\[0\\] +register being set to 0. Writes at other times have no effect. The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. NOTE: This register must not be programmed to a value higher than 65525, because DW_apb_i2c uses a 16-bit counter to flag an I2C bus idle condition when this counter reaches a value of IC_SS_SCL_HCNT + 10."] #[inline(always)] #[must_use] pub fn ic_ss_scl_hcnt(&mut self) -> IC_SS_SCL_HCNT_W { diff --git a/src/i2c0/ic_ss_scl_lcnt.rs b/src/i2c0/ic_ss_scl_lcnt.rs index 99940d30a..ec27406ad 100644 --- a/src/i2c0/ic_ss_scl_lcnt.rs +++ b/src/i2c0/ic_ss_scl_lcnt.rs @@ -2,39 +2,23 @@ pub type R = crate::R; #[doc = "Register `IC_SS_SCL_LCNT` writer"] pub type W = crate::W; -#[doc = "Field `IC_SS_SCL_LCNT` reader - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration' - - This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE\\[0\\] -register being set to 0. Writes at other times have no effect. - - The minimum valid value is 8; hardware prevents values less than this being written, and if attempted, results in 8 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of DW_apb_i2c. The lower byte must be programmed first, and then the upper byte is programmed."] +#[doc = "Field `IC_SS_SCL_LCNT` reader - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration' This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE\\[0\\] +register being set to 0. Writes at other times have no effect. The minimum valid value is 8; hardware prevents values less than this being written, and if attempted, results in 8 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of DW_apb_i2c. The lower byte must be programmed first, and then the upper byte is programmed."] pub type IC_SS_SCL_LCNT_R = crate::FieldReader; -#[doc = "Field `IC_SS_SCL_LCNT` writer - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration' - - This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE\\[0\\] -register being set to 0. Writes at other times have no effect. - - The minimum valid value is 8; hardware prevents values less than this being written, and if attempted, results in 8 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of DW_apb_i2c. The lower byte must be programmed first, and then the upper byte is programmed."] +#[doc = "Field `IC_SS_SCL_LCNT` writer - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration' This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE\\[0\\] +register being set to 0. Writes at other times have no effect. The minimum valid value is 8; hardware prevents values less than this being written, and if attempted, results in 8 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of DW_apb_i2c. The lower byte must be programmed first, and then the upper byte is programmed."] pub type IC_SS_SCL_LCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; impl R { - #[doc = "Bits 0:15 - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration' - - This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE\\[0\\] -register being set to 0. Writes at other times have no effect. - - The minimum valid value is 8; hardware prevents values less than this being written, and if attempted, results in 8 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of DW_apb_i2c. The lower byte must be programmed first, and then the upper byte is programmed."] + #[doc = "Bits 0:15 - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration' This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE\\[0\\] +register being set to 0. Writes at other times have no effect. The minimum valid value is 8; hardware prevents values less than this being written, and if attempted, results in 8 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of DW_apb_i2c. The lower byte must be programmed first, and then the upper byte is programmed."] #[inline(always)] pub fn ic_ss_scl_lcnt(&self) -> IC_SS_SCL_LCNT_R { IC_SS_SCL_LCNT_R::new((self.bits & 0xffff) as u16) } } impl W { - #[doc = "Bits 0:15 - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration' - - This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE\\[0\\] -register being set to 0. Writes at other times have no effect. - - The minimum valid value is 8; hardware prevents values less than this being written, and if attempted, results in 8 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of DW_apb_i2c. The lower byte must be programmed first, and then the upper byte is programmed."] + #[doc = "Bits 0:15 - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration' This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE\\[0\\] +register being set to 0. Writes at other times have no effect. The minimum valid value is 8; hardware prevents values less than this being written, and if attempted, results in 8 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of DW_apb_i2c. The lower byte must be programmed first, and then the upper byte is programmed."] #[inline(always)] #[must_use] pub fn ic_ss_scl_lcnt(&mut self) -> IC_SS_SCL_LCNT_W { diff --git a/src/i2c0/ic_status.rs b/src/i2c0/ic_status.rs index a449a0b2e..2bdecaf48 100644 --- a/src/i2c0/ic_status.rs +++ b/src/i2c0/ic_status.rs @@ -1,5 +1,7 @@ #[doc = "Register `IC_STATUS` reader"] pub type R = crate::R; +#[doc = "Register `IC_STATUS` writer"] +pub type W = crate::W; #[doc = "I2C Activity Status. Reset value: 0x0 Value on reset: 0"] @@ -190,9 +192,7 @@ impl RFF_R { *self == RFF_A::FULL } } -#[doc = "Master FSM Activity Status. When the Master Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Master FSM is in IDLE state so the Master part of DW_apb_i2c is not Active - 1: Master FSM is not in IDLE state so the Master part of DW_apb_i2c is Active Note: IC_STATUS\\[0\\]-that is, ACTIVITY bit-is the OR of SLV_ACTIVITY and MST_ACTIVITY bits. - - Reset value: 0x0 +#[doc = "Master FSM Activity Status. When the Master Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Master FSM is in IDLE state so the Master part of DW_apb_i2c is not Active - 1: Master FSM is not in IDLE state so the Master part of DW_apb_i2c is Active Note: IC_STATUS\\[0\\]-that is, ACTIVITY bit-is the OR of SLV_ACTIVITY and MST_ACTIVITY bits. Reset value: 0x0 Value on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -208,9 +208,7 @@ impl From for bool { variant as u8 != 0 } } -#[doc = "Field `MST_ACTIVITY` reader - Master FSM Activity Status. When the Master Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Master FSM is in IDLE state so the Master part of DW_apb_i2c is not Active - 1: Master FSM is not in IDLE state so the Master part of DW_apb_i2c is Active Note: IC_STATUS\\[0\\]-that is, ACTIVITY bit-is the OR of SLV_ACTIVITY and MST_ACTIVITY bits. - - Reset value: 0x0"] +#[doc = "Field `MST_ACTIVITY` reader - Master FSM Activity Status. When the Master Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Master FSM is in IDLE state so the Master part of DW_apb_i2c is not Active - 1: Master FSM is not in IDLE state so the Master part of DW_apb_i2c is Active Note: IC_STATUS\\[0\\]-that is, ACTIVITY bit-is the OR of SLV_ACTIVITY and MST_ACTIVITY bits. Reset value: 0x0"] pub type MST_ACTIVITY_R = crate::BitReader; impl MST_ACTIVITY_R { #[doc = "Get enumerated values variant"] @@ -296,9 +294,7 @@ impl R { pub fn rff(&self) -> RFF_R { RFF_R::new(((self.bits >> 4) & 1) != 0) } - #[doc = "Bit 5 - Master FSM Activity Status. When the Master Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Master FSM is in IDLE state so the Master part of DW_apb_i2c is not Active - 1: Master FSM is not in IDLE state so the Master part of DW_apb_i2c is Active Note: IC_STATUS\\[0\\]-that is, ACTIVITY bit-is the OR of SLV_ACTIVITY and MST_ACTIVITY bits. - - Reset value: 0x0"] + #[doc = "Bit 5 - Master FSM Activity Status. When the Master Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Master FSM is in IDLE state so the Master part of DW_apb_i2c is not Active - 1: Master FSM is not in IDLE state so the Master part of DW_apb_i2c is Active Note: IC_STATUS\\[0\\]-that is, ACTIVITY bit-is the OR of SLV_ACTIVITY and MST_ACTIVITY bits. Reset value: 0x0"] #[inline(always)] pub fn mst_activity(&self) -> MST_ACTIVITY_R { MST_ACTIVITY_R::new(((self.bits >> 5) & 1) != 0) @@ -309,19 +305,22 @@ impl R { SLV_ACTIVITY_R::new(((self.bits >> 6) & 1) != 0) } } -#[doc = "I2C Status Register +impl W {} +#[doc = "I2C Status Register This is a read-only register used to indicate the current transfer status and FIFO status. The status register may be read at any time. None of the bits in this register request an interrupt. When the I2C is disabled by writing 0 in bit 0 of the IC_ENABLE register: - Bits 1 and 2 are set to 1 - Bits 3 and 10 are set to 0 When the master or slave state machines goes to idle and ic_en=0: - Bits 5 and 6 are set to 0 - This is a read-only register used to indicate the current transfer status and FIFO status. The status register may be read at any time. None of the bits in this register request an interrupt. - - When the I2C is disabled by writing 0 in bit 0 of the IC_ENABLE register: - Bits 1 and 2 are set to 1 - Bits 3 and 10 are set to 0 When the master or slave state machines goes to idle and ic_en=0: - Bits 5 and 6 are set to 0 - -You can [`read`](crate::generic::Reg::read) this register and get [`ic_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`ic_status::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_status::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IC_STATUS_SPEC; impl crate::RegisterSpec for IC_STATUS_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`ic_status::R`](R) reader structure"] impl crate::Readable for IC_STATUS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ic_status::W`](W) writer structure"] +impl crate::Writable for IC_STATUS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets IC_STATUS to value 0x06"] impl crate::Resettable for IC_STATUS_SPEC { const RESET_VALUE: u32 = 0x06; diff --git a/src/i2c0/ic_tar.rs b/src/i2c0/ic_tar.rs index 4cf0e1e35..821b02c4f 100644 --- a/src/i2c0/ic_tar.rs +++ b/src/i2c0/ic_tar.rs @@ -2,13 +2,9 @@ pub type R = crate::R; #[doc = "Register `IC_TAR` writer"] pub type W = crate::W; -#[doc = "Field `IC_TAR` reader - This is the target address for any master transaction. When transmitting a General Call, these bits are ignored. To generate a START BYTE, the CPU needs to write only once into these bits. - - If the IC_TAR and IC_SAR are the same, loopback exists but the FIFOs are shared between master and slave, so full loopback is not feasible. Only one direction loopback mode is supported (simplex), not duplex. A master cannot transmit to itself; it can transmit to only a slave."] +#[doc = "Field `IC_TAR` reader - This is the target address for any master transaction. When transmitting a General Call, these bits are ignored. To generate a START BYTE, the CPU needs to write only once into these bits. If the IC_TAR and IC_SAR are the same, loopback exists but the FIFOs are shared between master and slave, so full loopback is not feasible. Only one direction loopback mode is supported (simplex), not duplex. A master cannot transmit to itself; it can transmit to only a slave."] pub type IC_TAR_R = crate::FieldReader; -#[doc = "Field `IC_TAR` writer - This is the target address for any master transaction. When transmitting a General Call, these bits are ignored. To generate a START BYTE, the CPU needs to write only once into these bits. - - If the IC_TAR and IC_SAR are the same, loopback exists but the FIFOs are shared between master and slave, so full loopback is not feasible. Only one direction loopback mode is supported (simplex), not duplex. A master cannot transmit to itself; it can transmit to only a slave."] +#[doc = "Field `IC_TAR` writer - This is the target address for any master transaction. When transmitting a General Call, these bits are ignored. To generate a START BYTE, the CPU needs to write only once into these bits. If the IC_TAR and IC_SAR are the same, loopback exists but the FIFOs are shared between master and slave, so full loopback is not feasible. Only one direction loopback mode is supported (simplex), not duplex. A master cannot transmit to itself; it can transmit to only a slave."] pub type IC_TAR_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; #[doc = "If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to 0, then this bit indicates whether a General Call or START byte command is to be performed by the DW_apb_i2c. - 0: General Call Address - after issuing a General Call, only writes may be performed. Attempting to issue a read command results in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. The DW_apb_i2c remains in General Call mode until the SPECIAL bit value (bit 11) is cleared. - 1: START BYTE Reset value: 0x0 @@ -121,9 +117,7 @@ where } } impl R { - #[doc = "Bits 0:9 - This is the target address for any master transaction. When transmitting a General Call, these bits are ignored. To generate a START BYTE, the CPU needs to write only once into these bits. - - If the IC_TAR and IC_SAR are the same, loopback exists but the FIFOs are shared between master and slave, so full loopback is not feasible. Only one direction loopback mode is supported (simplex), not duplex. A master cannot transmit to itself; it can transmit to only a slave."] + #[doc = "Bits 0:9 - This is the target address for any master transaction. When transmitting a General Call, these bits are ignored. To generate a START BYTE, the CPU needs to write only once into these bits. If the IC_TAR and IC_SAR are the same, loopback exists but the FIFOs are shared between master and slave, so full loopback is not feasible. Only one direction loopback mode is supported (simplex), not duplex. A master cannot transmit to itself; it can transmit to only a slave."] #[inline(always)] pub fn ic_tar(&self) -> IC_TAR_R { IC_TAR_R::new((self.bits & 0x03ff) as u16) @@ -140,9 +134,7 @@ impl R { } } impl W { - #[doc = "Bits 0:9 - This is the target address for any master transaction. When transmitting a General Call, these bits are ignored. To generate a START BYTE, the CPU needs to write only once into these bits. - - If the IC_TAR and IC_SAR are the same, loopback exists but the FIFOs are shared between master and slave, so full loopback is not feasible. Only one direction loopback mode is supported (simplex), not duplex. A master cannot transmit to itself; it can transmit to only a slave."] + #[doc = "Bits 0:9 - This is the target address for any master transaction. When transmitting a General Call, these bits are ignored. To generate a START BYTE, the CPU needs to write only once into these bits. If the IC_TAR and IC_SAR are the same, loopback exists but the FIFOs are shared between master and slave, so full loopback is not feasible. Only one direction loopback mode is supported (simplex), not duplex. A master cannot transmit to itself; it can transmit to only a slave."] #[inline(always)] #[must_use] pub fn ic_tar(&mut self) -> IC_TAR_W { @@ -161,12 +153,8 @@ impl W { SPECIAL_W::new(self, 11) } } -#[doc = "I2C Target Address Register - - This register is 12 bits wide, and bits 31:12 are reserved. This register can be written to only when IC_ENABLE\\[0\\] -is set to 0. - - Note: If the software or application is aware that the DW_apb_i2c is not using the TAR address for the pending commands in the Tx FIFO, then it is possible to update the TAR address even while the Tx FIFO has entries (IC_STATUS\\[2\\]= 0). - It is not necessary to perform any write to this register if DW_apb_i2c is enabled as an I2C slave only. +#[doc = "I2C Target Address Register This register is 12 bits wide, and bits 31:12 are reserved. This register can be written to only when IC_ENABLE\\[0\\] +is set to 0. Note: If the software or application is aware that the DW_apb_i2c is not using the TAR address for the pending commands in the Tx FIFO, then it is possible to update the TAR address even while the Tx FIFO has entries (IC_STATUS\\[2\\]= 0). - It is not necessary to perform any write to this register if DW_apb_i2c is enabled as an I2C slave only. You can [`read`](crate::generic::Reg::read) this register and get [`ic_tar::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_tar::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IC_TAR_SPEC; diff --git a/src/i2c0/ic_tx_abrt_source.rs b/src/i2c0/ic_tx_abrt_source.rs index 7fbde9336..a31600666 100644 --- a/src/i2c0/ic_tx_abrt_source.rs +++ b/src/i2c0/ic_tx_abrt_source.rs @@ -1,10 +1,8 @@ #[doc = "Register `IC_TX_ABRT_SOURCE` reader"] pub type R = crate::R; -#[doc = "This field indicates that the Master is in 7-bit addressing mode and the address sent was not acknowledged by any slave. - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Transmitter or Master-Receiver +#[doc = "Register `IC_TX_ABRT_SOURCE` writer"] +pub type W = crate::W; +#[doc = "This field indicates that the Master is in 7-bit addressing mode and the address sent was not acknowledged by any slave. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Master-Receiver Value on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -20,11 +18,7 @@ impl From for bool { variant as u8 != 0 } } -#[doc = "Field `ABRT_7B_ADDR_NOACK` reader - This field indicates that the Master is in 7-bit addressing mode and the address sent was not acknowledged by any slave. - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Transmitter or Master-Receiver"] +#[doc = "Field `ABRT_7B_ADDR_NOACK` reader - This field indicates that the Master is in 7-bit addressing mode and the address sent was not acknowledged by any slave. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Master-Receiver"] pub type ABRT_7B_ADDR_NOACK_R = crate::BitReader; impl ABRT_7B_ADDR_NOACK_R { #[doc = "Get enumerated values variant"] @@ -46,11 +40,7 @@ impl ABRT_7B_ADDR_NOACK_R { *self == ABRT_7B_ADDR_NOACK_A::ACTIVE } } -#[doc = "This field indicates that the Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave. - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Transmitter or Master-Receiver +#[doc = "This field indicates that the Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Master-Receiver Value on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -66,11 +56,7 @@ impl From for bool { variant as u8 != 0 } } -#[doc = "Field `ABRT_10ADDR1_NOACK` reader - This field indicates that the Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave. - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Transmitter or Master-Receiver"] +#[doc = "Field `ABRT_10ADDR1_NOACK` reader - This field indicates that the Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Master-Receiver"] pub type ABRT_10ADDR1_NOACK_R = crate::BitReader; impl ABRT_10ADDR1_NOACK_R { #[doc = "Get enumerated values variant"] @@ -92,11 +78,7 @@ impl ABRT_10ADDR1_NOACK_R { *self == ABRT_10ADDR1_NOACK_A::ACTIVE } } -#[doc = "This field indicates that the Master is in 10-bit address mode and that the second address byte of the 10-bit address was not acknowledged by any slave. - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Transmitter or Master-Receiver +#[doc = "This field indicates that the Master is in 10-bit address mode and that the second address byte of the 10-bit address was not acknowledged by any slave. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Master-Receiver Value on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -112,11 +94,7 @@ impl From for bool { variant as u8 != 0 } } -#[doc = "Field `ABRT_10ADDR2_NOACK` reader - This field indicates that the Master is in 10-bit address mode and that the second address byte of the 10-bit address was not acknowledged by any slave. - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Transmitter or Master-Receiver"] +#[doc = "Field `ABRT_10ADDR2_NOACK` reader - This field indicates that the Master is in 10-bit address mode and that the second address byte of the 10-bit address was not acknowledged by any slave. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Master-Receiver"] pub type ABRT_10ADDR2_NOACK_R = crate::BitReader; impl ABRT_10ADDR2_NOACK_R { #[doc = "Get enumerated values variant"] @@ -138,11 +116,7 @@ impl ABRT_10ADDR2_NOACK_R { *self == ABRT_10ADDR2_NOACK_A::ACTIVE } } -#[doc = "This field indicates the master-mode only bit. When the master receives an acknowledgement for the address, but when it sends data byte(s) following the address, it did not receive an acknowledge from the remote slave(s). - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Transmitter +#[doc = "This field indicates the master-mode only bit. When the master receives an acknowledgement for the address, but when it sends data byte(s) following the address, it did not receive an acknowledge from the remote slave(s). Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter Value on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -158,11 +132,7 @@ impl From for bool { variant as u8 != 0 } } -#[doc = "Field `ABRT_TXDATA_NOACK` reader - This field indicates the master-mode only bit. When the master receives an acknowledgement for the address, but when it sends data byte(s) following the address, it did not receive an acknowledge from the remote slave(s). - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Transmitter"] +#[doc = "Field `ABRT_TXDATA_NOACK` reader - This field indicates the master-mode only bit. When the master receives an acknowledgement for the address, but when it sends data byte(s) following the address, it did not receive an acknowledge from the remote slave(s). Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter"] pub type ABRT_TXDATA_NOACK_R = crate::BitReader; impl ABRT_TXDATA_NOACK_R { #[doc = "Get enumerated values variant"] @@ -184,11 +154,7 @@ impl ABRT_TXDATA_NOACK_R { *self == ABRT_TXDATA_NOACK_A::ABRT_TXDATA_NOACK_GENERATED } } -#[doc = "This field indicates that DW_apb_i2c in master mode has sent a General Call and no slave on the bus acknowledged the General Call. - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Transmitter +#[doc = "This field indicates that DW_apb_i2c in master mode has sent a General Call and no slave on the bus acknowledged the General Call. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter Value on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -204,11 +170,7 @@ impl From for bool { variant as u8 != 0 } } -#[doc = "Field `ABRT_GCALL_NOACK` reader - This field indicates that DW_apb_i2c in master mode has sent a General Call and no slave on the bus acknowledged the General Call. - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Transmitter"] +#[doc = "Field `ABRT_GCALL_NOACK` reader - This field indicates that DW_apb_i2c in master mode has sent a General Call and no slave on the bus acknowledged the General Call. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter"] pub type ABRT_GCALL_NOACK_R = crate::BitReader; impl ABRT_GCALL_NOACK_R { #[doc = "Get enumerated values variant"] @@ -231,11 +193,7 @@ impl ABRT_GCALL_NOACK_R { } } #[doc = "This field indicates that DW_apb_i2c in the master mode has sent a General Call but the user programmed the byte following the General Call to be a read from the bus (IC_DATA_CMD\\[9\\] -is set to 1). - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Transmitter +is set to 1). Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter Value on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -252,11 +210,7 @@ impl From for bool { } } #[doc = "Field `ABRT_GCALL_READ` reader - This field indicates that DW_apb_i2c in the master mode has sent a General Call but the user programmed the byte following the General Call to be a read from the bus (IC_DATA_CMD\\[9\\] -is set to 1). - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Transmitter"] +is set to 1). Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter"] pub type ABRT_GCALL_READ_R = crate::BitReader; impl ABRT_GCALL_READ_R { #[doc = "Get enumerated values variant"] @@ -278,11 +232,7 @@ impl ABRT_GCALL_READ_R { *self == ABRT_GCALL_READ_A::ABRT_GCALL_READ_GENERATED } } -#[doc = "This field indicates that the Master is in High Speed mode and the High Speed Master code was acknowledged (wrong behavior). - - Reset value: 0x0 - - Role of DW_apb_i2c: Master +#[doc = "This field indicates that the Master is in High Speed mode and the High Speed Master code was acknowledged (wrong behavior). Reset value: 0x0 Role of DW_apb_i2c: Master Value on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -298,11 +248,7 @@ impl From for bool { variant as u8 != 0 } } -#[doc = "Field `ABRT_HS_ACKDET` reader - This field indicates that the Master is in High Speed mode and the High Speed Master code was acknowledged (wrong behavior). - - Reset value: 0x0 - - Role of DW_apb_i2c: Master"] +#[doc = "Field `ABRT_HS_ACKDET` reader - This field indicates that the Master is in High Speed mode and the High Speed Master code was acknowledged (wrong behavior). Reset value: 0x0 Role of DW_apb_i2c: Master"] pub type ABRT_HS_ACKDET_R = crate::BitReader; impl ABRT_HS_ACKDET_R { #[doc = "Get enumerated values variant"] @@ -324,11 +270,7 @@ impl ABRT_HS_ACKDET_R { *self == ABRT_HS_ACKDET_A::ABRT_HS_ACK_GENERATED } } -#[doc = "This field indicates that the Master has sent a START Byte and the START Byte was acknowledged (wrong behavior). - - Reset value: 0x0 - - Role of DW_apb_i2c: Master +#[doc = "This field indicates that the Master has sent a START Byte and the START Byte was acknowledged (wrong behavior). Reset value: 0x0 Role of DW_apb_i2c: Master Value on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -344,11 +286,7 @@ impl From for bool { variant as u8 != 0 } } -#[doc = "Field `ABRT_SBYTE_ACKDET` reader - This field indicates that the Master has sent a START Byte and the START Byte was acknowledged (wrong behavior). - - Reset value: 0x0 - - Role of DW_apb_i2c: Master"] +#[doc = "Field `ABRT_SBYTE_ACKDET` reader - This field indicates that the Master has sent a START Byte and the START Byte was acknowledged (wrong behavior). Reset value: 0x0 Role of DW_apb_i2c: Master"] pub type ABRT_SBYTE_ACKDET_R = crate::BitReader; impl ABRT_SBYTE_ACKDET_R { #[doc = "Get enumerated values variant"] @@ -370,11 +308,7 @@ impl ABRT_SBYTE_ACKDET_R { *self == ABRT_SBYTE_ACKDET_A::ABRT_SBYTE_ACKDET_GENERATED } } -#[doc = "This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON\\[5\\]) =0) and the user is trying to use the master to transfer data in High Speed mode. - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Transmitter or Master-Receiver +#[doc = "This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON\\[5\\]) =0) and the user is trying to use the master to transfer data in High Speed mode. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Master-Receiver Value on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -390,11 +324,7 @@ impl From for bool { variant as u8 != 0 } } -#[doc = "Field `ABRT_HS_NORSTRT` reader - This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON\\[5\\]) =0) and the user is trying to use the master to transfer data in High Speed mode. - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Transmitter or Master-Receiver"] +#[doc = "Field `ABRT_HS_NORSTRT` reader - This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON\\[5\\]) =0) and the user is trying to use the master to transfer data in High Speed mode. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Master-Receiver"] pub type ABRT_HS_NORSTRT_R = crate::BitReader; impl ABRT_HS_NORSTRT_R { #[doc = "Get enumerated values variant"] @@ -416,11 +346,7 @@ impl ABRT_HS_NORSTRT_R { *self == ABRT_HS_NORSTRT_A::ABRT_HS_NORSTRT_GENERATED } } -#[doc = "To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; restart must be enabled (IC_CON\\[5\\]=1), the SPECIAL bit must be cleared (IC_TAR\\[11\\]), or the GC_OR_START bit must be cleared (IC_TAR\\[10\\]). Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, bit 9 clears for one cycle and then gets reasserted. When this field is set to 1, the restart is disabled (IC_RESTART_EN bit (IC_CON\\[5\\]) =0) and the user is trying to send a START Byte. - - Reset value: 0x0 - - Role of DW_apb_i2c: Master +#[doc = "To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; restart must be enabled (IC_CON\\[5\\]=1), the SPECIAL bit must be cleared (IC_TAR\\[11\\]), or the GC_OR_START bit must be cleared (IC_TAR\\[10\\]). Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, bit 9 clears for one cycle and then gets reasserted. When this field is set to 1, the restart is disabled (IC_RESTART_EN bit (IC_CON\\[5\\]) =0) and the user is trying to send a START Byte. Reset value: 0x0 Role of DW_apb_i2c: Master Value on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -436,11 +362,7 @@ impl From for bool { variant as u8 != 0 } } -#[doc = "Field `ABRT_SBYTE_NORSTRT` reader - To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; restart must be enabled (IC_CON\\[5\\]=1), the SPECIAL bit must be cleared (IC_TAR\\[11\\]), or the GC_OR_START bit must be cleared (IC_TAR\\[10\\]). Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, bit 9 clears for one cycle and then gets reasserted. When this field is set to 1, the restart is disabled (IC_RESTART_EN bit (IC_CON\\[5\\]) =0) and the user is trying to send a START Byte. - - Reset value: 0x0 - - Role of DW_apb_i2c: Master"] +#[doc = "Field `ABRT_SBYTE_NORSTRT` reader - To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; restart must be enabled (IC_CON\\[5\\]=1), the SPECIAL bit must be cleared (IC_TAR\\[11\\]), or the GC_OR_START bit must be cleared (IC_TAR\\[10\\]). Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, bit 9 clears for one cycle and then gets reasserted. When this field is set to 1, the restart is disabled (IC_RESTART_EN bit (IC_CON\\[5\\]) =0) and the user is trying to send a START Byte. Reset value: 0x0 Role of DW_apb_i2c: Master"] pub type ABRT_SBYTE_NORSTRT_R = crate::BitReader; impl ABRT_SBYTE_NORSTRT_R { #[doc = "Get enumerated values variant"] @@ -462,11 +384,7 @@ impl ABRT_SBYTE_NORSTRT_R { *self == ABRT_SBYTE_NORSTRT_A::ABRT_SBYTE_NORSTRT_GENERATED } } -#[doc = "This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON\\[5\\]) =0) and the master sends a read command in 10-bit addressing mode. - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Receiver +#[doc = "This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON\\[5\\]) =0) and the master sends a read command in 10-bit addressing mode. Reset value: 0x0 Role of DW_apb_i2c: Master-Receiver Value on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -482,11 +400,7 @@ impl From for bool { variant as u8 != 0 } } -#[doc = "Field `ABRT_10B_RD_NORSTRT` reader - This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON\\[5\\]) =0) and the master sends a read command in 10-bit addressing mode. - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Receiver"] +#[doc = "Field `ABRT_10B_RD_NORSTRT` reader - This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON\\[5\\]) =0) and the master sends a read command in 10-bit addressing mode. Reset value: 0x0 Role of DW_apb_i2c: Master-Receiver"] pub type ABRT_10B_RD_NORSTRT_R = crate::BitReader; impl ABRT_10B_RD_NORSTRT_R { #[doc = "Get enumerated values variant"] @@ -508,11 +422,7 @@ impl ABRT_10B_RD_NORSTRT_R { *self == ABRT_10B_RD_NORSTRT_A::ABRT_10B_RD_GENERATED } } -#[doc = "This field indicates that the User tries to initiate a Master operation with the Master mode disabled. - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Transmitter or Master-Receiver +#[doc = "This field indicates that the User tries to initiate a Master operation with the Master mode disabled. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Master-Receiver Value on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -528,11 +438,7 @@ impl From for bool { variant as u8 != 0 } } -#[doc = "Field `ABRT_MASTER_DIS` reader - This field indicates that the User tries to initiate a Master operation with the Master mode disabled. - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Transmitter or Master-Receiver"] +#[doc = "Field `ABRT_MASTER_DIS` reader - This field indicates that the User tries to initiate a Master operation with the Master mode disabled. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Master-Receiver"] pub type ABRT_MASTER_DIS_R = crate::BitReader; impl ABRT_MASTER_DIS_R { #[doc = "Get enumerated values variant"] @@ -555,11 +461,7 @@ impl ABRT_MASTER_DIS_R { } } #[doc = "This field specifies that the Master has lost arbitration, or if IC_TX_ABRT_SOURCE\\[14\\] -is also set, then the slave transmitter has lost arbitration. - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter +is also set, then the slave transmitter has lost arbitration. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter Value on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -576,11 +478,7 @@ impl From for bool { } } #[doc = "Field `ARB_LOST` reader - This field specifies that the Master has lost arbitration, or if IC_TX_ABRT_SOURCE\\[14\\] -is also set, then the slave transmitter has lost arbitration. - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter"] +is also set, then the slave transmitter has lost arbitration. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter"] pub type ARB_LOST_R = crate::BitReader; impl ARB_LOST_R { #[doc = "Get enumerated values variant"] @@ -602,11 +500,7 @@ impl ARB_LOST_R { *self == ARB_LOST_A::ABRT_LOST_GENERATED } } -#[doc = "This field specifies that the Slave has received a read command and some data exists in the TX FIFO, so the slave issues a TX_ABRT interrupt to flush old data in TX FIFO. - - Reset value: 0x0 - - Role of DW_apb_i2c: Slave-Transmitter +#[doc = "This field specifies that the Slave has received a read command and some data exists in the TX FIFO, so the slave issues a TX_ABRT interrupt to flush old data in TX FIFO. Reset value: 0x0 Role of DW_apb_i2c: Slave-Transmitter Value on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -622,11 +516,7 @@ impl From for bool { variant as u8 != 0 } } -#[doc = "Field `ABRT_SLVFLUSH_TXFIFO` reader - This field specifies that the Slave has received a read command and some data exists in the TX FIFO, so the slave issues a TX_ABRT interrupt to flush old data in TX FIFO. - - Reset value: 0x0 - - Role of DW_apb_i2c: Slave-Transmitter"] +#[doc = "Field `ABRT_SLVFLUSH_TXFIFO` reader - This field specifies that the Slave has received a read command and some data exists in the TX FIFO, so the slave issues a TX_ABRT interrupt to flush old data in TX FIFO. Reset value: 0x0 Role of DW_apb_i2c: Slave-Transmitter"] pub type ABRT_SLVFLUSH_TXFIFO_R = crate::BitReader; impl ABRT_SLVFLUSH_TXFIFO_R { #[doc = "Get enumerated values variant"] @@ -649,11 +539,7 @@ impl ABRT_SLVFLUSH_TXFIFO_R { } } #[doc = "This field indicates that a Slave has lost the bus while transmitting data to a remote master. IC_TX_ABRT_SOURCE\\[12\\] -is set at the same time. Note: Even though the slave never 'owns' the bus, something could go wrong on the bus. This is a fail safe check. For instance, during a data transmission at the low-to-high transition of SCL, if what is on the data bus is not what is supposed to be transmitted, then DW_apb_i2c no longer own the bus. - - Reset value: 0x0 - - Role of DW_apb_i2c: Slave-Transmitter +is set at the same time. Note: Even though the slave never 'owns' the bus, something could go wrong on the bus. This is a fail safe check. For instance, during a data transmission at the low-to-high transition of SCL, if what is on the data bus is not what is supposed to be transmitted, then DW_apb_i2c no longer own the bus. Reset value: 0x0 Role of DW_apb_i2c: Slave-Transmitter Value on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -670,11 +556,7 @@ impl From for bool { } } #[doc = "Field `ABRT_SLV_ARBLOST` reader - This field indicates that a Slave has lost the bus while transmitting data to a remote master. IC_TX_ABRT_SOURCE\\[12\\] -is set at the same time. Note: Even though the slave never 'owns' the bus, something could go wrong on the bus. This is a fail safe check. For instance, during a data transmission at the low-to-high transition of SCL, if what is on the data bus is not what is supposed to be transmitted, then DW_apb_i2c no longer own the bus. - - Reset value: 0x0 - - Role of DW_apb_i2c: Slave-Transmitter"] +is set at the same time. Note: Even though the slave never 'owns' the bus, something could go wrong on the bus. This is a fail safe check. For instance, during a data transmission at the low-to-high transition of SCL, if what is on the data bus is not what is supposed to be transmitted, then DW_apb_i2c no longer own the bus. Reset value: 0x0 Role of DW_apb_i2c: Slave-Transmitter"] pub type ABRT_SLV_ARBLOST_R = crate::BitReader; impl ABRT_SLV_ARBLOST_R { #[doc = "Get enumerated values variant"] @@ -696,11 +578,7 @@ impl ABRT_SLV_ARBLOST_R { *self == ABRT_SLV_ARBLOST_A::ABRT_SLV_ARBLOST_GENERATED } } -#[doc = "1: When the processor side responds to a slave mode request for data to be transmitted to a remote master and user writes a 1 in CMD (bit 8) of IC_DATA_CMD register. - - Reset value: 0x0 - - Role of DW_apb_i2c: Slave-Transmitter +#[doc = "1: When the processor side responds to a slave mode request for data to be transmitted to a remote master and user writes a 1 in CMD (bit 8) of IC_DATA_CMD register. Reset value: 0x0 Role of DW_apb_i2c: Slave-Transmitter Value on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -716,11 +594,7 @@ impl From for bool { variant as u8 != 0 } } -#[doc = "Field `ABRT_SLVRD_INTX` reader - 1: When the processor side responds to a slave mode request for data to be transmitted to a remote master and user writes a 1 in CMD (bit 8) of IC_DATA_CMD register. - - Reset value: 0x0 - - Role of DW_apb_i2c: Slave-Transmitter"] +#[doc = "Field `ABRT_SLVRD_INTX` reader - 1: When the processor side responds to a slave mode request for data to be transmitted to a remote master and user writes a 1 in CMD (bit 8) of IC_DATA_CMD register. Reset value: 0x0 Role of DW_apb_i2c: Slave-Transmitter"] pub type ABRT_SLVRD_INTX_R = crate::BitReader; impl ABRT_SLVRD_INTX_R { #[doc = "Get enumerated values variant"] @@ -742,11 +616,7 @@ impl ABRT_SLVRD_INTX_R { *self == ABRT_SLVRD_INTX_A::ABRT_SLVRD_INTX_GENERATED } } -#[doc = "This is a master-mode-only bit. Master has detected the transfer abort (IC_ENABLE\\[1\\]) - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Transmitter +#[doc = "This is a master-mode-only bit. Master has detected the transfer abort (IC_ENABLE\\[1\\]) Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter Value on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -762,11 +632,7 @@ impl From for bool { variant as u8 != 0 } } -#[doc = "Field `ABRT_USER_ABRT` reader - This is a master-mode-only bit. Master has detected the transfer abort (IC_ENABLE\\[1\\]) - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Transmitter"] +#[doc = "Field `ABRT_USER_ABRT` reader - This is a master-mode-only bit. Master has detected the transfer abort (IC_ENABLE\\[1\\]) Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter"] pub type ABRT_USER_ABRT_R = crate::BitReader; impl ABRT_USER_ABRT_R { #[doc = "Get enumerated values variant"] @@ -788,192 +654,119 @@ impl ABRT_USER_ABRT_R { *self == ABRT_USER_ABRT_A::ABRT_USER_ABRT_GENERATED } } -#[doc = "Field `TX_FLUSH_CNT` reader - This field indicates the number of Tx FIFO Data Commands which are flushed due to TX_ABRT interrupt. It is cleared whenever I2C is disabled. - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter"] +#[doc = "Field `TX_FLUSH_CNT` reader - This field indicates the number of Tx FIFO Data Commands which are flushed due to TX_ABRT interrupt. It is cleared whenever I2C is disabled. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter"] pub type TX_FLUSH_CNT_R = crate::FieldReader; impl R { - #[doc = "Bit 0 - This field indicates that the Master is in 7-bit addressing mode and the address sent was not acknowledged by any slave. - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Transmitter or Master-Receiver"] + #[doc = "Bit 0 - This field indicates that the Master is in 7-bit addressing mode and the address sent was not acknowledged by any slave. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Master-Receiver"] #[inline(always)] pub fn abrt_7b_addr_noack(&self) -> ABRT_7B_ADDR_NOACK_R { ABRT_7B_ADDR_NOACK_R::new((self.bits & 1) != 0) } - #[doc = "Bit 1 - This field indicates that the Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave. - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Transmitter or Master-Receiver"] + #[doc = "Bit 1 - This field indicates that the Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Master-Receiver"] #[inline(always)] pub fn abrt_10addr1_noack(&self) -> ABRT_10ADDR1_NOACK_R { ABRT_10ADDR1_NOACK_R::new(((self.bits >> 1) & 1) != 0) } - #[doc = "Bit 2 - This field indicates that the Master is in 10-bit address mode and that the second address byte of the 10-bit address was not acknowledged by any slave. - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Transmitter or Master-Receiver"] + #[doc = "Bit 2 - This field indicates that the Master is in 10-bit address mode and that the second address byte of the 10-bit address was not acknowledged by any slave. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Master-Receiver"] #[inline(always)] pub fn abrt_10addr2_noack(&self) -> ABRT_10ADDR2_NOACK_R { ABRT_10ADDR2_NOACK_R::new(((self.bits >> 2) & 1) != 0) } - #[doc = "Bit 3 - This field indicates the master-mode only bit. When the master receives an acknowledgement for the address, but when it sends data byte(s) following the address, it did not receive an acknowledge from the remote slave(s). - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Transmitter"] + #[doc = "Bit 3 - This field indicates the master-mode only bit. When the master receives an acknowledgement for the address, but when it sends data byte(s) following the address, it did not receive an acknowledge from the remote slave(s). Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter"] #[inline(always)] pub fn abrt_txdata_noack(&self) -> ABRT_TXDATA_NOACK_R { ABRT_TXDATA_NOACK_R::new(((self.bits >> 3) & 1) != 0) } - #[doc = "Bit 4 - This field indicates that DW_apb_i2c in master mode has sent a General Call and no slave on the bus acknowledged the General Call. - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Transmitter"] + #[doc = "Bit 4 - This field indicates that DW_apb_i2c in master mode has sent a General Call and no slave on the bus acknowledged the General Call. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter"] #[inline(always)] pub fn abrt_gcall_noack(&self) -> ABRT_GCALL_NOACK_R { ABRT_GCALL_NOACK_R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 5 - This field indicates that DW_apb_i2c in the master mode has sent a General Call but the user programmed the byte following the General Call to be a read from the bus (IC_DATA_CMD\\[9\\] -is set to 1). - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Transmitter"] +is set to 1). Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter"] #[inline(always)] pub fn abrt_gcall_read(&self) -> ABRT_GCALL_READ_R { ABRT_GCALL_READ_R::new(((self.bits >> 5) & 1) != 0) } - #[doc = "Bit 6 - This field indicates that the Master is in High Speed mode and the High Speed Master code was acknowledged (wrong behavior). - - Reset value: 0x0 - - Role of DW_apb_i2c: Master"] + #[doc = "Bit 6 - This field indicates that the Master is in High Speed mode and the High Speed Master code was acknowledged (wrong behavior). Reset value: 0x0 Role of DW_apb_i2c: Master"] #[inline(always)] pub fn abrt_hs_ackdet(&self) -> ABRT_HS_ACKDET_R { ABRT_HS_ACKDET_R::new(((self.bits >> 6) & 1) != 0) } - #[doc = "Bit 7 - This field indicates that the Master has sent a START Byte and the START Byte was acknowledged (wrong behavior). - - Reset value: 0x0 - - Role of DW_apb_i2c: Master"] + #[doc = "Bit 7 - This field indicates that the Master has sent a START Byte and the START Byte was acknowledged (wrong behavior). Reset value: 0x0 Role of DW_apb_i2c: Master"] #[inline(always)] pub fn abrt_sbyte_ackdet(&self) -> ABRT_SBYTE_ACKDET_R { ABRT_SBYTE_ACKDET_R::new(((self.bits >> 7) & 1) != 0) } - #[doc = "Bit 8 - This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON\\[5\\]) =0) and the user is trying to use the master to transfer data in High Speed mode. - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Transmitter or Master-Receiver"] + #[doc = "Bit 8 - This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON\\[5\\]) =0) and the user is trying to use the master to transfer data in High Speed mode. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Master-Receiver"] #[inline(always)] pub fn abrt_hs_norstrt(&self) -> ABRT_HS_NORSTRT_R { ABRT_HS_NORSTRT_R::new(((self.bits >> 8) & 1) != 0) } - #[doc = "Bit 9 - To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; restart must be enabled (IC_CON\\[5\\]=1), the SPECIAL bit must be cleared (IC_TAR\\[11\\]), or the GC_OR_START bit must be cleared (IC_TAR\\[10\\]). Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, bit 9 clears for one cycle and then gets reasserted. When this field is set to 1, the restart is disabled (IC_RESTART_EN bit (IC_CON\\[5\\]) =0) and the user is trying to send a START Byte. - - Reset value: 0x0 - - Role of DW_apb_i2c: Master"] + #[doc = "Bit 9 - To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; restart must be enabled (IC_CON\\[5\\]=1), the SPECIAL bit must be cleared (IC_TAR\\[11\\]), or the GC_OR_START bit must be cleared (IC_TAR\\[10\\]). Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, bit 9 clears for one cycle and then gets reasserted. When this field is set to 1, the restart is disabled (IC_RESTART_EN bit (IC_CON\\[5\\]) =0) and the user is trying to send a START Byte. Reset value: 0x0 Role of DW_apb_i2c: Master"] #[inline(always)] pub fn abrt_sbyte_norstrt(&self) -> ABRT_SBYTE_NORSTRT_R { ABRT_SBYTE_NORSTRT_R::new(((self.bits >> 9) & 1) != 0) } - #[doc = "Bit 10 - This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON\\[5\\]) =0) and the master sends a read command in 10-bit addressing mode. - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Receiver"] + #[doc = "Bit 10 - This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON\\[5\\]) =0) and the master sends a read command in 10-bit addressing mode. Reset value: 0x0 Role of DW_apb_i2c: Master-Receiver"] #[inline(always)] pub fn abrt_10b_rd_norstrt(&self) -> ABRT_10B_RD_NORSTRT_R { ABRT_10B_RD_NORSTRT_R::new(((self.bits >> 10) & 1) != 0) } - #[doc = "Bit 11 - This field indicates that the User tries to initiate a Master operation with the Master mode disabled. - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Transmitter or Master-Receiver"] + #[doc = "Bit 11 - This field indicates that the User tries to initiate a Master operation with the Master mode disabled. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Master-Receiver"] #[inline(always)] pub fn abrt_master_dis(&self) -> ABRT_MASTER_DIS_R { ABRT_MASTER_DIS_R::new(((self.bits >> 11) & 1) != 0) } #[doc = "Bit 12 - This field specifies that the Master has lost arbitration, or if IC_TX_ABRT_SOURCE\\[14\\] -is also set, then the slave transmitter has lost arbitration. - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter"] +is also set, then the slave transmitter has lost arbitration. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter"] #[inline(always)] pub fn arb_lost(&self) -> ARB_LOST_R { ARB_LOST_R::new(((self.bits >> 12) & 1) != 0) } - #[doc = "Bit 13 - This field specifies that the Slave has received a read command and some data exists in the TX FIFO, so the slave issues a TX_ABRT interrupt to flush old data in TX FIFO. - - Reset value: 0x0 - - Role of DW_apb_i2c: Slave-Transmitter"] + #[doc = "Bit 13 - This field specifies that the Slave has received a read command and some data exists in the TX FIFO, so the slave issues a TX_ABRT interrupt to flush old data in TX FIFO. Reset value: 0x0 Role of DW_apb_i2c: Slave-Transmitter"] #[inline(always)] pub fn abrt_slvflush_txfifo(&self) -> ABRT_SLVFLUSH_TXFIFO_R { ABRT_SLVFLUSH_TXFIFO_R::new(((self.bits >> 13) & 1) != 0) } #[doc = "Bit 14 - This field indicates that a Slave has lost the bus while transmitting data to a remote master. IC_TX_ABRT_SOURCE\\[12\\] -is set at the same time. Note: Even though the slave never 'owns' the bus, something could go wrong on the bus. This is a fail safe check. For instance, during a data transmission at the low-to-high transition of SCL, if what is on the data bus is not what is supposed to be transmitted, then DW_apb_i2c no longer own the bus. - - Reset value: 0x0 - - Role of DW_apb_i2c: Slave-Transmitter"] +is set at the same time. Note: Even though the slave never 'owns' the bus, something could go wrong on the bus. This is a fail safe check. For instance, during a data transmission at the low-to-high transition of SCL, if what is on the data bus is not what is supposed to be transmitted, then DW_apb_i2c no longer own the bus. Reset value: 0x0 Role of DW_apb_i2c: Slave-Transmitter"] #[inline(always)] pub fn abrt_slv_arblost(&self) -> ABRT_SLV_ARBLOST_R { ABRT_SLV_ARBLOST_R::new(((self.bits >> 14) & 1) != 0) } - #[doc = "Bit 15 - 1: When the processor side responds to a slave mode request for data to be transmitted to a remote master and user writes a 1 in CMD (bit 8) of IC_DATA_CMD register. - - Reset value: 0x0 - - Role of DW_apb_i2c: Slave-Transmitter"] + #[doc = "Bit 15 - 1: When the processor side responds to a slave mode request for data to be transmitted to a remote master and user writes a 1 in CMD (bit 8) of IC_DATA_CMD register. Reset value: 0x0 Role of DW_apb_i2c: Slave-Transmitter"] #[inline(always)] pub fn abrt_slvrd_intx(&self) -> ABRT_SLVRD_INTX_R { ABRT_SLVRD_INTX_R::new(((self.bits >> 15) & 1) != 0) } - #[doc = "Bit 16 - This is a master-mode-only bit. Master has detected the transfer abort (IC_ENABLE\\[1\\]) - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Transmitter"] + #[doc = "Bit 16 - This is a master-mode-only bit. Master has detected the transfer abort (IC_ENABLE\\[1\\]) Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter"] #[inline(always)] pub fn abrt_user_abrt(&self) -> ABRT_USER_ABRT_R { ABRT_USER_ABRT_R::new(((self.bits >> 16) & 1) != 0) } - #[doc = "Bits 23:31 - This field indicates the number of Tx FIFO Data Commands which are flushed due to TX_ABRT interrupt. It is cleared whenever I2C is disabled. - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter"] + #[doc = "Bits 23:31 - This field indicates the number of Tx FIFO Data Commands which are flushed due to TX_ABRT interrupt. It is cleared whenever I2C is disabled. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter"] #[inline(always)] pub fn tx_flush_cnt(&self) -> TX_FLUSH_CNT_R { TX_FLUSH_CNT_R::new(((self.bits >> 23) & 0x01ff) as u16) } } -#[doc = "I2C Transmit Abort Source Register +impl W {} +#[doc = "I2C Transmit Abort Source Register This register has 32 bits that indicate the source of the TX_ABRT bit. Except for Bit 9, this register is cleared whenever the IC_CLR_TX_ABRT register or the IC_CLR_INTR register is read. To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; RESTART must be enabled (IC_CON\\[5\\]=1), the SPECIAL bit must be cleared (IC_TAR\\[11\\]), or the GC_OR_START bit must be cleared (IC_TAR\\[10\\]). Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, Bit 9 clears for one cycle and is then re-asserted. - This register has 32 bits that indicate the source of the TX_ABRT bit. Except for Bit 9, this register is cleared whenever the IC_CLR_TX_ABRT register or the IC_CLR_INTR register is read. To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; RESTART must be enabled (IC_CON\\[5\\]=1), the SPECIAL bit must be cleared (IC_TAR\\[11\\]), or the GC_OR_START bit must be cleared (IC_TAR\\[10\\]). - - Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, Bit 9 clears for one cycle and is then re-asserted. - -You can [`read`](crate::generic::Reg::read) this register and get [`ic_tx_abrt_source::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`ic_tx_abrt_source::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_tx_abrt_source::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IC_TX_ABRT_SOURCE_SPEC; impl crate::RegisterSpec for IC_TX_ABRT_SOURCE_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`ic_tx_abrt_source::R`](R) reader structure"] impl crate::Readable for IC_TX_ABRT_SOURCE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ic_tx_abrt_source::W`](W) writer structure"] +impl crate::Writable for IC_TX_ABRT_SOURCE_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets IC_TX_ABRT_SOURCE to value 0"] impl crate::Resettable for IC_TX_ABRT_SOURCE_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/i2c0/ic_tx_tl.rs b/src/i2c0/ic_tx_tl.rs index 32fa42d7e..ed3cf956b 100644 --- a/src/i2c0/ic_tx_tl.rs +++ b/src/i2c0/ic_tx_tl.rs @@ -2,27 +2,19 @@ pub type R = crate::R; #[doc = "Register `IC_TX_TL` writer"] pub type W = crate::W; -#[doc = "Field `TX_TL` reader - Transmit FIFO Threshold Level. - - Controls the level of entries (or below) that trigger the TX_EMPTY interrupt (bit 4 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that it may not be set to value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 0 entries, and a value of 255 sets the threshold for 255 entries."] +#[doc = "Field `TX_TL` reader - Transmit FIFO Threshold Level. Controls the level of entries (or below) that trigger the TX_EMPTY interrupt (bit 4 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that it may not be set to value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 0 entries, and a value of 255 sets the threshold for 255 entries."] pub type TX_TL_R = crate::FieldReader; -#[doc = "Field `TX_TL` writer - Transmit FIFO Threshold Level. - - Controls the level of entries (or below) that trigger the TX_EMPTY interrupt (bit 4 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that it may not be set to value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 0 entries, and a value of 255 sets the threshold for 255 entries."] +#[doc = "Field `TX_TL` writer - Transmit FIFO Threshold Level. Controls the level of entries (or below) that trigger the TX_EMPTY interrupt (bit 4 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that it may not be set to value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 0 entries, and a value of 255 sets the threshold for 255 entries."] pub type TX_TL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { - #[doc = "Bits 0:7 - Transmit FIFO Threshold Level. - - Controls the level of entries (or below) that trigger the TX_EMPTY interrupt (bit 4 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that it may not be set to value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 0 entries, and a value of 255 sets the threshold for 255 entries."] + #[doc = "Bits 0:7 - Transmit FIFO Threshold Level. Controls the level of entries (or below) that trigger the TX_EMPTY interrupt (bit 4 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that it may not be set to value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 0 entries, and a value of 255 sets the threshold for 255 entries."] #[inline(always)] pub fn tx_tl(&self) -> TX_TL_R { TX_TL_R::new((self.bits & 0xff) as u8) } } impl W { - #[doc = "Bits 0:7 - Transmit FIFO Threshold Level. - - Controls the level of entries (or below) that trigger the TX_EMPTY interrupt (bit 4 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that it may not be set to value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 0 entries, and a value of 255 sets the threshold for 255 entries."] + #[doc = "Bits 0:7 - Transmit FIFO Threshold Level. Controls the level of entries (or below) that trigger the TX_EMPTY interrupt (bit 4 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that it may not be set to value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 0 entries, and a value of 255 sets the threshold for 255 entries."] #[inline(always)] #[must_use] pub fn tx_tl(&mut self) -> TX_TL_W { diff --git a/src/i2c0/ic_txflr.rs b/src/i2c0/ic_txflr.rs index 66e5c8cc3..001c90110 100644 --- a/src/i2c0/ic_txflr.rs +++ b/src/i2c0/ic_txflr.rs @@ -1,27 +1,32 @@ #[doc = "Register `IC_TXFLR` reader"] pub type R = crate::R; -#[doc = "Field `TXFLR` reader - Transmit FIFO Level. Contains the number of valid data entries in the transmit FIFO. - - Reset value: 0x0"] +#[doc = "Register `IC_TXFLR` writer"] +pub type W = crate::W; +#[doc = "Field `TXFLR` reader - Transmit FIFO Level. Contains the number of valid data entries in the transmit FIFO. Reset value: 0x0"] pub type TXFLR_R = crate::FieldReader; impl R { - #[doc = "Bits 0:4 - Transmit FIFO Level. Contains the number of valid data entries in the transmit FIFO. - - Reset value: 0x0"] + #[doc = "Bits 0:4 - Transmit FIFO Level. Contains the number of valid data entries in the transmit FIFO. Reset value: 0x0"] #[inline(always)] pub fn txflr(&self) -> TXFLR_R { TXFLR_R::new((self.bits & 0x1f) as u8) } } +impl W {} #[doc = "I2C Transmit FIFO Level Register This register contains the number of valid data entries in the transmit FIFO buffer. It is cleared whenever: - The I2C is disabled - There is a transmit abort - that is, TX_ABRT bit is set in the IC_RAW_INTR_STAT register - The slave bulk transmit mode is aborted The register increments whenever data is placed into the transmit FIFO and decrements when data is taken from the transmit FIFO. -You can [`read`](crate::generic::Reg::read) this register and get [`ic_txflr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`ic_txflr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic_txflr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IC_TXFLR_SPEC; impl crate::RegisterSpec for IC_TXFLR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`ic_txflr::R`](R) reader structure"] impl crate::Readable for IC_TXFLR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ic_txflr::W`](W) writer structure"] +impl crate::Writable for IC_TXFLR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets IC_TXFLR to value 0"] impl crate::Resettable for IC_TXFLR_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/io_bank0.rs b/src/io_bank0.rs index 728289fcf..4fc785342 100644 --- a/src/io_bank0.rs +++ b/src/io_bank0.rs @@ -168,9 +168,9 @@ module"] pub type PROC0_INTF = crate::Reg; #[doc = "Interrupt Force for proc0"] pub mod proc0_intf; -#[doc = "PROC0_INTS (r) register accessor: Interrupt status after masking & forcing for proc0 +#[doc = "PROC0_INTS (rw) register accessor: Interrupt status after masking & forcing for proc0 -You can [`read`](crate::generic::Reg::read) this register and get [`proc0_ints::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`proc0_ints::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`proc0_ints::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@proc0_ints`] module"] @@ -195,9 +195,9 @@ module"] pub type PROC1_INTF = crate::Reg; #[doc = "Interrupt Force for proc1"] pub mod proc1_intf; -#[doc = "PROC1_INTS (r) register accessor: Interrupt status after masking & forcing for proc1 +#[doc = "PROC1_INTS (rw) register accessor: Interrupt status after masking & forcing for proc1 -You can [`read`](crate::generic::Reg::read) this register and get [`proc1_ints::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`proc1_ints::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`proc1_ints::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@proc1_ints`] module"] @@ -222,9 +222,9 @@ module"] pub type DORMANT_WAKE_INTF = crate::Reg; #[doc = "Interrupt Force for dormant_wake"] pub mod dormant_wake_intf; -#[doc = "DORMANT_WAKE_INTS (r) register accessor: Interrupt status after masking & forcing for dormant_wake +#[doc = "DORMANT_WAKE_INTS (rw) register accessor: Interrupt status after masking & forcing for dormant_wake -You can [`read`](crate::generic::Reg::read) this register and get [`dormant_wake_ints::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`dormant_wake_ints::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dormant_wake_ints::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@dormant_wake_ints`] module"] diff --git a/src/io_bank0/dormant_wake_ints.rs b/src/io_bank0/dormant_wake_ints.rs index 7e5165f17..feec51d18 100644 --- a/src/io_bank0/dormant_wake_ints.rs +++ b/src/io_bank0/dormant_wake_ints.rs @@ -1,5 +1,7 @@ #[doc = "Register `DORMANT_WAKE_INTS%s` reader"] pub type R = crate::R; +#[doc = "Register `DORMANT_WAKE_INTS%s` writer"] +pub type W = crate::W; #[doc = "Field `GPIO0_LEVEL_LOW` reader - "] pub type GPIO0_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO0_LEVEL_HIGH` reader - "] @@ -226,15 +228,22 @@ impl R { GPIO7_EDGE_HIGH_R::new(((self.bits >> 31) & 1) != 0) } } +impl W {} #[doc = "Interrupt status after masking & forcing for dormant_wake -You can [`read`](crate::generic::Reg::read) this register and get [`dormant_wake_ints::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`dormant_wake_ints::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dormant_wake_ints::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DORMANT_WAKE_INTS_SPEC; impl crate::RegisterSpec for DORMANT_WAKE_INTS_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`dormant_wake_ints::R`](R) reader structure"] impl crate::Readable for DORMANT_WAKE_INTS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dormant_wake_ints::W`](W) writer structure"] +impl crate::Writable for DORMANT_WAKE_INTS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets DORMANT_WAKE_INTS%s to value 0"] impl crate::Resettable for DORMANT_WAKE_INTS_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/io_bank0/gpio.rs b/src/io_bank0/gpio.rs index 77023bc7d..8c4d69683 100644 --- a/src/io_bank0/gpio.rs +++ b/src/io_bank0/gpio.rs @@ -16,9 +16,9 @@ impl GPIO { &self.gpio_ctrl } } -#[doc = "GPIO_STATUS (r) register accessor: GPIO status +#[doc = "GPIO_STATUS (rw) register accessor: GPIO status -You can [`read`](crate::generic::Reg::read) this register and get [`gpio_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`gpio_status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@gpio_status`] module"] diff --git a/src/io_bank0/gpio/gpio_status.rs b/src/io_bank0/gpio/gpio_status.rs index 801488279..0d9ea0b2b 100644 --- a/src/io_bank0/gpio/gpio_status.rs +++ b/src/io_bank0/gpio/gpio_status.rs @@ -1,5 +1,7 @@ #[doc = "Register `GPIO_STATUS` reader"] pub type R = crate::R; +#[doc = "Register `GPIO_STATUS` writer"] +pub type W = crate::W; #[doc = "Field `OUTFROMPERI` reader - output signal from selected peripheral, before register override is applied"] pub type OUTFROMPERI_R = crate::BitReader; #[doc = "Field `OUTTOPAD` reader - output signal to pad after register override is applied"] @@ -58,15 +60,22 @@ impl R { IRQTOPROC_R::new(((self.bits >> 26) & 1) != 0) } } +impl W {} #[doc = "GPIO status -You can [`read`](crate::generic::Reg::read) this register and get [`gpio_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`gpio_status::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_status::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPIO_STATUS_SPEC; impl crate::RegisterSpec for GPIO_STATUS_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`gpio_status::R`](R) reader structure"] impl crate::Readable for GPIO_STATUS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio_status::W`](W) writer structure"] +impl crate::Writable for GPIO_STATUS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets GPIO_STATUS to value 0"] impl crate::Resettable for GPIO_STATUS_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/io_bank0/proc0_ints.rs b/src/io_bank0/proc0_ints.rs index 730b0f968..6bf14030a 100644 --- a/src/io_bank0/proc0_ints.rs +++ b/src/io_bank0/proc0_ints.rs @@ -1,5 +1,7 @@ #[doc = "Register `PROC0_INTS%s` reader"] pub type R = crate::R; +#[doc = "Register `PROC0_INTS%s` writer"] +pub type W = crate::W; #[doc = "Field `GPIO0_LEVEL_LOW` reader - "] pub type GPIO0_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO0_LEVEL_HIGH` reader - "] @@ -226,15 +228,22 @@ impl R { GPIO7_EDGE_HIGH_R::new(((self.bits >> 31) & 1) != 0) } } +impl W {} #[doc = "Interrupt status after masking & forcing for proc0 -You can [`read`](crate::generic::Reg::read) this register and get [`proc0_ints::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`proc0_ints::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`proc0_ints::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PROC0_INTS_SPEC; impl crate::RegisterSpec for PROC0_INTS_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`proc0_ints::R`](R) reader structure"] impl crate::Readable for PROC0_INTS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`proc0_ints::W`](W) writer structure"] +impl crate::Writable for PROC0_INTS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets PROC0_INTS%s to value 0"] impl crate::Resettable for PROC0_INTS_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/io_bank0/proc1_ints.rs b/src/io_bank0/proc1_ints.rs index 24303f139..b618990f4 100644 --- a/src/io_bank0/proc1_ints.rs +++ b/src/io_bank0/proc1_ints.rs @@ -1,5 +1,7 @@ #[doc = "Register `PROC1_INTS%s` reader"] pub type R = crate::R; +#[doc = "Register `PROC1_INTS%s` writer"] +pub type W = crate::W; #[doc = "Field `GPIO0_LEVEL_LOW` reader - "] pub type GPIO0_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO0_LEVEL_HIGH` reader - "] @@ -226,15 +228,22 @@ impl R { GPIO7_EDGE_HIGH_R::new(((self.bits >> 31) & 1) != 0) } } +impl W {} #[doc = "Interrupt status after masking & forcing for proc1 -You can [`read`](crate::generic::Reg::read) this register and get [`proc1_ints::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`proc1_ints::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`proc1_ints::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PROC1_INTS_SPEC; impl crate::RegisterSpec for PROC1_INTS_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`proc1_ints::R`](R) reader structure"] impl crate::Readable for PROC1_INTS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`proc1_ints::W`](W) writer structure"] +impl crate::Writable for PROC1_INTS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets PROC1_INTS%s to value 0"] impl crate::Resettable for PROC1_INTS_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/io_qspi.rs b/src/io_qspi.rs index aeaf4ad26..cd3245189 100644 --- a/src/io_qspi.rs +++ b/src/io_qspi.rs @@ -138,9 +138,9 @@ module"] pub type PROC0_INTF = crate::Reg; #[doc = "Interrupt Force for proc0"] pub mod proc0_intf; -#[doc = "PROC0_INTS (r) register accessor: Interrupt status after masking & forcing for proc0 +#[doc = "PROC0_INTS (rw) register accessor: Interrupt status after masking & forcing for proc0 -You can [`read`](crate::generic::Reg::read) this register and get [`proc0_ints::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`proc0_ints::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`proc0_ints::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@proc0_ints`] module"] @@ -165,9 +165,9 @@ module"] pub type PROC1_INTF = crate::Reg; #[doc = "Interrupt Force for proc1"] pub mod proc1_intf; -#[doc = "PROC1_INTS (r) register accessor: Interrupt status after masking & forcing for proc1 +#[doc = "PROC1_INTS (rw) register accessor: Interrupt status after masking & forcing for proc1 -You can [`read`](crate::generic::Reg::read) this register and get [`proc1_ints::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`proc1_ints::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`proc1_ints::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@proc1_ints`] module"] @@ -192,9 +192,9 @@ module"] pub type DORMANT_WAKE_INTF = crate::Reg; #[doc = "Interrupt Force for dormant_wake"] pub mod dormant_wake_intf; -#[doc = "DORMANT_WAKE_INTS (r) register accessor: Interrupt status after masking & forcing for dormant_wake +#[doc = "DORMANT_WAKE_INTS (rw) register accessor: Interrupt status after masking & forcing for dormant_wake -You can [`read`](crate::generic::Reg::read) this register and get [`dormant_wake_ints::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`dormant_wake_ints::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dormant_wake_ints::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@dormant_wake_ints`] module"] diff --git a/src/io_qspi/dormant_wake_ints.rs b/src/io_qspi/dormant_wake_ints.rs index 732122cd2..03e4861d2 100644 --- a/src/io_qspi/dormant_wake_ints.rs +++ b/src/io_qspi/dormant_wake_ints.rs @@ -1,5 +1,7 @@ #[doc = "Register `DORMANT_WAKE_INTS` reader"] pub type R = crate::R; +#[doc = "Register `DORMANT_WAKE_INTS` writer"] +pub type W = crate::W; #[doc = "Field `GPIO_QSPI_SCLK_LEVEL_LOW` reader - "] pub type GPIO_QSPI_SCLK_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SCLK_LEVEL_HIGH` reader - "] @@ -170,15 +172,22 @@ impl R { GPIO_QSPI_SD3_EDGE_HIGH_R::new(((self.bits >> 23) & 1) != 0) } } +impl W {} #[doc = "Interrupt status after masking & forcing for dormant_wake -You can [`read`](crate::generic::Reg::read) this register and get [`dormant_wake_ints::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`dormant_wake_ints::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dormant_wake_ints::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DORMANT_WAKE_INTS_SPEC; impl crate::RegisterSpec for DORMANT_WAKE_INTS_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`dormant_wake_ints::R`](R) reader structure"] impl crate::Readable for DORMANT_WAKE_INTS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dormant_wake_ints::W`](W) writer structure"] +impl crate::Writable for DORMANT_WAKE_INTS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets DORMANT_WAKE_INTS to value 0"] impl crate::Resettable for DORMANT_WAKE_INTS_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/io_qspi/gpio_qspi.rs b/src/io_qspi/gpio_qspi.rs index 8b60a9ad1..30885f0e8 100644 --- a/src/io_qspi/gpio_qspi.rs +++ b/src/io_qspi/gpio_qspi.rs @@ -16,9 +16,9 @@ impl GPIO_QSPI { &self.gpio_ctrl } } -#[doc = "GPIO_STATUS (r) register accessor: GPIO status +#[doc = "GPIO_STATUS (rw) register accessor: GPIO status -You can [`read`](crate::generic::Reg::read) this register and get [`gpio_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`gpio_status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@gpio_status`] module"] diff --git a/src/io_qspi/gpio_qspi/gpio_ctrl.rs b/src/io_qspi/gpio_qspi/gpio_ctrl.rs index c91a7f94c..dc3e5cc04 100644 --- a/src/io_qspi/gpio_qspi/gpio_ctrl.rs +++ b/src/io_qspi/gpio_qspi/gpio_ctrl.rs @@ -2,8 +2,7 @@ pub type R = crate::R; #[doc = "Register `GPIO_CTRL` writer"] pub type W = crate::W; -#[doc = "0-31 -> selects pin function according to the gpio table - 31 == NULL +#[doc = "0-31 -> selects pin function according to the gpio table 31 == NULL Value on reset: 31"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -25,8 +24,7 @@ impl From for u8 { impl crate::FieldSpec for FUNCSEL_A { type Ux = u8; } -#[doc = "Field `FUNCSEL` reader - 0-31 -> selects pin function according to the gpio table - 31 == NULL"] +#[doc = "Field `FUNCSEL` reader - 0-31 -> selects pin function according to the gpio table 31 == NULL"] pub type FUNCSEL_R = crate::FieldReader; impl FUNCSEL_R { #[doc = "Get enumerated values variant"] @@ -55,8 +53,7 @@ impl FUNCSEL_R { *self == FUNCSEL_A::NULL } } -#[doc = "Field `FUNCSEL` writer - 0-31 -> selects pin function according to the gpio table - 31 == NULL"] +#[doc = "Field `FUNCSEL` writer - 0-31 -> selects pin function according to the gpio table 31 == NULL"] pub type FUNCSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 5, FUNCSEL_A>; impl<'a, REG> FUNCSEL_W<'a, REG> where @@ -428,8 +425,7 @@ where } } impl R { - #[doc = "Bits 0:4 - 0-31 -> selects pin function according to the gpio table - 31 == NULL"] + #[doc = "Bits 0:4 - 0-31 -> selects pin function according to the gpio table 31 == NULL"] #[inline(always)] pub fn funcsel(&self) -> FUNCSEL_R { FUNCSEL_R::new((self.bits & 0x1f) as u8) @@ -456,8 +452,7 @@ impl R { } } impl W { - #[doc = "Bits 0:4 - 0-31 -> selects pin function according to the gpio table - 31 == NULL"] + #[doc = "Bits 0:4 - 0-31 -> selects pin function according to the gpio table 31 == NULL"] #[inline(always)] #[must_use] pub fn funcsel(&mut self) -> FUNCSEL_W { diff --git a/src/io_qspi/gpio_qspi/gpio_status.rs b/src/io_qspi/gpio_qspi/gpio_status.rs index 801488279..0d9ea0b2b 100644 --- a/src/io_qspi/gpio_qspi/gpio_status.rs +++ b/src/io_qspi/gpio_qspi/gpio_status.rs @@ -1,5 +1,7 @@ #[doc = "Register `GPIO_STATUS` reader"] pub type R = crate::R; +#[doc = "Register `GPIO_STATUS` writer"] +pub type W = crate::W; #[doc = "Field `OUTFROMPERI` reader - output signal from selected peripheral, before register override is applied"] pub type OUTFROMPERI_R = crate::BitReader; #[doc = "Field `OUTTOPAD` reader - output signal to pad after register override is applied"] @@ -58,15 +60,22 @@ impl R { IRQTOPROC_R::new(((self.bits >> 26) & 1) != 0) } } +impl W {} #[doc = "GPIO status -You can [`read`](crate::generic::Reg::read) this register and get [`gpio_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`gpio_status::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_status::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPIO_STATUS_SPEC; impl crate::RegisterSpec for GPIO_STATUS_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`gpio_status::R`](R) reader structure"] impl crate::Readable for GPIO_STATUS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio_status::W`](W) writer structure"] +impl crate::Writable for GPIO_STATUS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets GPIO_STATUS to value 0"] impl crate::Resettable for GPIO_STATUS_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/io_qspi/proc0_ints.rs b/src/io_qspi/proc0_ints.rs index b59526569..50362d2e3 100644 --- a/src/io_qspi/proc0_ints.rs +++ b/src/io_qspi/proc0_ints.rs @@ -1,5 +1,7 @@ #[doc = "Register `PROC0_INTS` reader"] pub type R = crate::R; +#[doc = "Register `PROC0_INTS` writer"] +pub type W = crate::W; #[doc = "Field `GPIO_QSPI_SCLK_LEVEL_LOW` reader - "] pub type GPIO_QSPI_SCLK_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SCLK_LEVEL_HIGH` reader - "] @@ -170,15 +172,22 @@ impl R { GPIO_QSPI_SD3_EDGE_HIGH_R::new(((self.bits >> 23) & 1) != 0) } } +impl W {} #[doc = "Interrupt status after masking & forcing for proc0 -You can [`read`](crate::generic::Reg::read) this register and get [`proc0_ints::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`proc0_ints::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`proc0_ints::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PROC0_INTS_SPEC; impl crate::RegisterSpec for PROC0_INTS_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`proc0_ints::R`](R) reader structure"] impl crate::Readable for PROC0_INTS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`proc0_ints::W`](W) writer structure"] +impl crate::Writable for PROC0_INTS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets PROC0_INTS to value 0"] impl crate::Resettable for PROC0_INTS_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/io_qspi/proc1_ints.rs b/src/io_qspi/proc1_ints.rs index a31d11608..5b79d582e 100644 --- a/src/io_qspi/proc1_ints.rs +++ b/src/io_qspi/proc1_ints.rs @@ -1,5 +1,7 @@ #[doc = "Register `PROC1_INTS` reader"] pub type R = crate::R; +#[doc = "Register `PROC1_INTS` writer"] +pub type W = crate::W; #[doc = "Field `GPIO_QSPI_SCLK_LEVEL_LOW` reader - "] pub type GPIO_QSPI_SCLK_LEVEL_LOW_R = crate::BitReader; #[doc = "Field `GPIO_QSPI_SCLK_LEVEL_HIGH` reader - "] @@ -170,15 +172,22 @@ impl R { GPIO_QSPI_SD3_EDGE_HIGH_R::new(((self.bits >> 23) & 1) != 0) } } +impl W {} #[doc = "Interrupt status after masking & forcing for proc1 -You can [`read`](crate::generic::Reg::read) this register and get [`proc1_ints::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`proc1_ints::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`proc1_ints::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PROC1_INTS_SPEC; impl crate::RegisterSpec for PROC1_INTS_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`proc1_ints::R`](R) reader structure"] impl crate::Readable for PROC1_INTS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`proc1_ints::W`](W) writer structure"] +impl crate::Writable for PROC1_INTS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets PROC1_INTS to value 0"] impl crate::Resettable for PROC1_INTS_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/lib.rs b/src/lib.rs index 094585a0a..4f1127de1 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -219,17 +219,17 @@ unsafe impl cortex_m::interrupt::InterruptNumber for Interrupt { self as u16 } } -#[doc = "QSPI flash execute-in-place block"] -pub struct XIP_CTRL { +#[doc = "RESETS"] +pub struct RESETS { _marker: PhantomData<*const ()>, } -unsafe impl Send for XIP_CTRL {} -impl XIP_CTRL { +unsafe impl Send for RESETS {} +impl RESETS { #[doc = r"Pointer to the register block"] - pub const PTR: *const xip_ctrl::RegisterBlock = 0x1400_0000 as *const _; + pub const PTR: *const resets::RegisterBlock = 0x4000_c000 as *const _; #[doc = r"Return the pointer to the register block"] #[inline(always)] - pub const fn ptr() -> *const xip_ctrl::RegisterBlock { + pub const fn ptr() -> *const resets::RegisterBlock { Self::PTR } #[doc = r" Steal an instance of this peripheral"] @@ -251,56 +251,31 @@ impl XIP_CTRL { } } } -impl Deref for XIP_CTRL { - type Target = xip_ctrl::RegisterBlock; +impl Deref for RESETS { + type Target = resets::RegisterBlock; #[inline(always)] fn deref(&self) -> &Self::Target { unsafe { &*Self::PTR } } } -impl core::fmt::Debug for XIP_CTRL { +impl core::fmt::Debug for RESETS { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("XIP_CTRL").finish() + f.debug_struct("RESETS").finish() } } -#[doc = "QSPI flash execute-in-place block"] -pub mod xip_ctrl; -#[doc = "DW_apb_ssi has the following features: - * APB interface - Allows for easy integration into a DesignWare Synthesizable Components for AMBA 2 implementation. - * APB3 and APB4 protocol support. - * Scalable APB data bus width - Supports APB data bus widths of 8, 16, and 32 bits. - * Serial-master or serial-slave operation - Enables serial communication with serial-master or serial-slave peripheral devices. - * Programmable Dual/Quad/Octal SPI support in Master Mode. - * Dual Data Rate (DDR) and Read Data Strobe (RDS) Support - Enables the DW_apb_ssi master to perform operations with the device in DDR and RDS modes when working in Dual/Quad/Octal mode of operation. - * Data Mask Support - Enables the DW_apb_ssi to selectively update the bytes in the device. This feature is applicable only in enhanced SPI modes. - * eXecute-In-Place (XIP) support - Enables the DW_apb_ssi master to behave as a memory mapped I/O and fetches the data from the device based on the APB read request. This feature is applicable only in enhanced SPI modes. - * DMA Controller Interface - Enables the DW_apb_ssi to interface to a DMA controller over the bus using a handshaking interface for transfer requests. - * Independent masking of interrupts - Master collision, transmit FIFO overflow, transmit FIFO empty, receive FIFO full, receive FIFO underflow, and receive FIFO overflow interrupts can all be masked independently. - * Multi-master contention detection - Informs the processor of multiple serial-master accesses on the serial bus. - * Bypass of meta-stability flip-flops for synchronous clocks - When the APB clock (pclk) and the DW_apb_ssi serial clock (ssi_clk) are synchronous, meta-stable flip-flops are not used when transferring control signals across these clock domains. - * Programmable delay on the sample time of the received serial data bit (rxd); enables programmable control of routing delays resulting in higher serial data-bit rates. - * Programmable features: - - Serial interface operation - Choice of Motorola SPI, Texas Instruments Synchronous Serial Protocol or National Semiconductor Microwire. - - Clock bit-rate - Dynamic control of the serial bit rate of the data transfer; used in only serial-master mode of operation. - - Data Item size (4 to 32 bits) - Item size of each data transfer under the control of the programmer. - * Configured features: - - FIFO depth - 16 words deep. The FIFO width is fixed at 32 bits. - - 1 slave select output. - - Hardware slave-select - Dedicated hardware slave-select line. - - Combined interrupt line - one combined interrupt line from the DW_apb_ssi to the interrupt controller. - - Interrupt polarity - active high interrupt lines. - - Serial clock polarity - low serial-clock polarity directly after reset. - - Serial clock phase - capture on first edge of serial-clock directly after reset."] -pub struct XIP_SSI { +#[doc = "RESETS"] +pub mod resets; +#[doc = "PSM"] +pub struct PSM { _marker: PhantomData<*const ()>, } -unsafe impl Send for XIP_SSI {} -impl XIP_SSI { +unsafe impl Send for PSM {} +impl PSM { #[doc = r"Pointer to the register block"] - pub const PTR: *const xip_ssi::RegisterBlock = 0x1800_0000 as *const _; + pub const PTR: *const psm::RegisterBlock = 0x4001_0000 as *const _; #[doc = r"Return the pointer to the register block"] #[inline(always)] - pub const fn ptr() -> *const xip_ssi::RegisterBlock { + pub const fn ptr() -> *const psm::RegisterBlock { Self::PTR } #[doc = r" Steal an instance of this peripheral"] @@ -322,56 +297,31 @@ impl XIP_SSI { } } } -impl Deref for XIP_SSI { - type Target = xip_ssi::RegisterBlock; +impl Deref for PSM { + type Target = psm::RegisterBlock; #[inline(always)] fn deref(&self) -> &Self::Target { unsafe { &*Self::PTR } } } -impl core::fmt::Debug for XIP_SSI { +impl core::fmt::Debug for PSM { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("XIP_SSI").finish() - } -} -#[doc = "DW_apb_ssi has the following features: - * APB interface - Allows for easy integration into a DesignWare Synthesizable Components for AMBA 2 implementation. - * APB3 and APB4 protocol support. - * Scalable APB data bus width - Supports APB data bus widths of 8, 16, and 32 bits. - * Serial-master or serial-slave operation - Enables serial communication with serial-master or serial-slave peripheral devices. - * Programmable Dual/Quad/Octal SPI support in Master Mode. - * Dual Data Rate (DDR) and Read Data Strobe (RDS) Support - Enables the DW_apb_ssi master to perform operations with the device in DDR and RDS modes when working in Dual/Quad/Octal mode of operation. - * Data Mask Support - Enables the DW_apb_ssi to selectively update the bytes in the device. This feature is applicable only in enhanced SPI modes. - * eXecute-In-Place (XIP) support - Enables the DW_apb_ssi master to behave as a memory mapped I/O and fetches the data from the device based on the APB read request. This feature is applicable only in enhanced SPI modes. - * DMA Controller Interface - Enables the DW_apb_ssi to interface to a DMA controller over the bus using a handshaking interface for transfer requests. - * Independent masking of interrupts - Master collision, transmit FIFO overflow, transmit FIFO empty, receive FIFO full, receive FIFO underflow, and receive FIFO overflow interrupts can all be masked independently. - * Multi-master contention detection - Informs the processor of multiple serial-master accesses on the serial bus. - * Bypass of meta-stability flip-flops for synchronous clocks - When the APB clock (pclk) and the DW_apb_ssi serial clock (ssi_clk) are synchronous, meta-stable flip-flops are not used when transferring control signals across these clock domains. - * Programmable delay on the sample time of the received serial data bit (rxd); enables programmable control of routing delays resulting in higher serial data-bit rates. - * Programmable features: - - Serial interface operation - Choice of Motorola SPI, Texas Instruments Synchronous Serial Protocol or National Semiconductor Microwire. - - Clock bit-rate - Dynamic control of the serial bit rate of the data transfer; used in only serial-master mode of operation. - - Data Item size (4 to 32 bits) - Item size of each data transfer under the control of the programmer. - * Configured features: - - FIFO depth - 16 words deep. The FIFO width is fixed at 32 bits. - - 1 slave select output. - - Hardware slave-select - Dedicated hardware slave-select line. - - Combined interrupt line - one combined interrupt line from the DW_apb_ssi to the interrupt controller. - - Interrupt polarity - active high interrupt lines. - - Serial clock polarity - low serial-clock polarity directly after reset. - - Serial clock phase - capture on first edge of serial-clock directly after reset."] -pub mod xip_ssi; -#[doc = "SYSINFO"] -pub struct SYSINFO { + f.debug_struct("PSM").finish() + } +} +#[doc = "PSM"] +pub mod psm; +#[doc = "CLOCKS"] +pub struct CLOCKS { _marker: PhantomData<*const ()>, } -unsafe impl Send for SYSINFO {} -impl SYSINFO { +unsafe impl Send for CLOCKS {} +impl CLOCKS { #[doc = r"Pointer to the register block"] - pub const PTR: *const sysinfo::RegisterBlock = 0x4000_0000 as *const _; + pub const PTR: *const clocks::RegisterBlock = 0x4000_8000 as *const _; #[doc = r"Return the pointer to the register block"] #[inline(always)] - pub const fn ptr() -> *const sysinfo::RegisterBlock { + pub const fn ptr() -> *const clocks::RegisterBlock { Self::PTR } #[doc = r" Steal an instance of this peripheral"] @@ -393,31 +343,31 @@ impl SYSINFO { } } } -impl Deref for SYSINFO { - type Target = sysinfo::RegisterBlock; +impl Deref for CLOCKS { + type Target = clocks::RegisterBlock; #[inline(always)] fn deref(&self) -> &Self::Target { unsafe { &*Self::PTR } } } -impl core::fmt::Debug for SYSINFO { +impl core::fmt::Debug for CLOCKS { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SYSINFO").finish() + f.debug_struct("CLOCKS").finish() } } -#[doc = "SYSINFO"] -pub mod sysinfo; -#[doc = "Register block for various chip control signals"] -pub struct SYSCFG { +#[doc = "CLOCKS"] +pub mod clocks; +#[doc = "PADS_BANK0"] +pub struct PADS_BANK0 { _marker: PhantomData<*const ()>, } -unsafe impl Send for SYSCFG {} -impl SYSCFG { +unsafe impl Send for PADS_BANK0 {} +impl PADS_BANK0 { #[doc = r"Pointer to the register block"] - pub const PTR: *const syscfg::RegisterBlock = 0x4000_4000 as *const _; + pub const PTR: *const pads_bank0::RegisterBlock = 0x4001_c000 as *const _; #[doc = r"Return the pointer to the register block"] #[inline(always)] - pub const fn ptr() -> *const syscfg::RegisterBlock { + pub const fn ptr() -> *const pads_bank0::RegisterBlock { Self::PTR } #[doc = r" Steal an instance of this peripheral"] @@ -439,31 +389,31 @@ impl SYSCFG { } } } -impl Deref for SYSCFG { - type Target = syscfg::RegisterBlock; +impl Deref for PADS_BANK0 { + type Target = pads_bank0::RegisterBlock; #[inline(always)] fn deref(&self) -> &Self::Target { unsafe { &*Self::PTR } } } -impl core::fmt::Debug for SYSCFG { +impl core::fmt::Debug for PADS_BANK0 { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SYSCFG").finish() + f.debug_struct("PADS_BANK0").finish() } } -#[doc = "Register block for various chip control signals"] -pub mod syscfg; -#[doc = "CLOCKS"] -pub struct CLOCKS { +#[doc = "PADS_BANK0"] +pub mod pads_bank0; +#[doc = "PADS_QSPI"] +pub struct PADS_QSPI { _marker: PhantomData<*const ()>, } -unsafe impl Send for CLOCKS {} -impl CLOCKS { +unsafe impl Send for PADS_QSPI {} +impl PADS_QSPI { #[doc = r"Pointer to the register block"] - pub const PTR: *const clocks::RegisterBlock = 0x4000_8000 as *const _; + pub const PTR: *const pads_qspi::RegisterBlock = 0x4002_0000 as *const _; #[doc = r"Return the pointer to the register block"] #[inline(always)] - pub const fn ptr() -> *const clocks::RegisterBlock { + pub const fn ptr() -> *const pads_qspi::RegisterBlock { Self::PTR } #[doc = r" Steal an instance of this peripheral"] @@ -485,31 +435,31 @@ impl CLOCKS { } } } -impl Deref for CLOCKS { - type Target = clocks::RegisterBlock; +impl Deref for PADS_QSPI { + type Target = pads_qspi::RegisterBlock; #[inline(always)] fn deref(&self) -> &Self::Target { unsafe { &*Self::PTR } } } -impl core::fmt::Debug for CLOCKS { +impl core::fmt::Debug for PADS_QSPI { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("CLOCKS").finish() + f.debug_struct("PADS_QSPI").finish() } } -#[doc = "CLOCKS"] -pub mod clocks; -#[doc = "RESETS"] -pub struct RESETS { +#[doc = "PADS_QSPI"] +pub mod pads_qspi; +#[doc = "IO_QSPI"] +pub struct IO_QSPI { _marker: PhantomData<*const ()>, } -unsafe impl Send for RESETS {} -impl RESETS { +unsafe impl Send for IO_QSPI {} +impl IO_QSPI { #[doc = r"Pointer to the register block"] - pub const PTR: *const resets::RegisterBlock = 0x4000_c000 as *const _; + pub const PTR: *const io_qspi::RegisterBlock = 0x4001_8000 as *const _; #[doc = r"Return the pointer to the register block"] #[inline(always)] - pub const fn ptr() -> *const resets::RegisterBlock { + pub const fn ptr() -> *const io_qspi::RegisterBlock { Self::PTR } #[doc = r" Steal an instance of this peripheral"] @@ -531,31 +481,31 @@ impl RESETS { } } } -impl Deref for RESETS { - type Target = resets::RegisterBlock; +impl Deref for IO_QSPI { + type Target = io_qspi::RegisterBlock; #[inline(always)] fn deref(&self) -> &Self::Target { unsafe { &*Self::PTR } } } -impl core::fmt::Debug for RESETS { +impl core::fmt::Debug for IO_QSPI { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("RESETS").finish() + f.debug_struct("IO_QSPI").finish() } } -#[doc = "RESETS"] -pub mod resets; -#[doc = "PSM"] -pub struct PSM { +#[doc = "IO_QSPI"] +pub mod io_qspi; +#[doc = "IO_BANK0"] +pub struct IO_BANK0 { _marker: PhantomData<*const ()>, } -unsafe impl Send for PSM {} -impl PSM { +unsafe impl Send for IO_BANK0 {} +impl IO_BANK0 { #[doc = r"Pointer to the register block"] - pub const PTR: *const psm::RegisterBlock = 0x4001_0000 as *const _; + pub const PTR: *const io_bank0::RegisterBlock = 0x4001_4000 as *const _; #[doc = r"Return the pointer to the register block"] #[inline(always)] - pub const fn ptr() -> *const psm::RegisterBlock { + pub const fn ptr() -> *const io_bank0::RegisterBlock { Self::PTR } #[doc = r" Steal an instance of this peripheral"] @@ -577,31 +527,31 @@ impl PSM { } } } -impl Deref for PSM { - type Target = psm::RegisterBlock; +impl Deref for IO_BANK0 { + type Target = io_bank0::RegisterBlock; #[inline(always)] fn deref(&self) -> &Self::Target { unsafe { &*Self::PTR } } } -impl core::fmt::Debug for PSM { +impl core::fmt::Debug for IO_BANK0 { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("PSM").finish() + f.debug_struct("IO_BANK0").finish() } } -#[doc = "PSM"] -pub mod psm; #[doc = "IO_BANK0"] -pub struct IO_BANK0 { +pub mod io_bank0; +#[doc = "SYSINFO"] +pub struct SYSINFO { _marker: PhantomData<*const ()>, } -unsafe impl Send for IO_BANK0 {} -impl IO_BANK0 { +unsafe impl Send for SYSINFO {} +impl SYSINFO { #[doc = r"Pointer to the register block"] - pub const PTR: *const io_bank0::RegisterBlock = 0x4001_4000 as *const _; + pub const PTR: *const sysinfo::RegisterBlock = 0x4000_0000 as *const _; #[doc = r"Return the pointer to the register block"] #[inline(always)] - pub const fn ptr() -> *const io_bank0::RegisterBlock { + pub const fn ptr() -> *const sysinfo::RegisterBlock { Self::PTR } #[doc = r" Steal an instance of this peripheral"] @@ -623,31 +573,31 @@ impl IO_BANK0 { } } } -impl Deref for IO_BANK0 { - type Target = io_bank0::RegisterBlock; +impl Deref for SYSINFO { + type Target = sysinfo::RegisterBlock; #[inline(always)] fn deref(&self) -> &Self::Target { unsafe { &*Self::PTR } } } -impl core::fmt::Debug for IO_BANK0 { +impl core::fmt::Debug for SYSINFO { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("IO_BANK0").finish() + f.debug_struct("SYSINFO").finish() } } -#[doc = "IO_BANK0"] -pub mod io_bank0; -#[doc = "IO_QSPI"] -pub struct IO_QSPI { +#[doc = "SYSINFO"] +pub mod sysinfo; +#[doc = "PPB"] +pub struct PPB { _marker: PhantomData<*const ()>, } -unsafe impl Send for IO_QSPI {} -impl IO_QSPI { +unsafe impl Send for PPB {} +impl PPB { #[doc = r"Pointer to the register block"] - pub const PTR: *const io_qspi::RegisterBlock = 0x4001_8000 as *const _; + pub const PTR: *const ppb::RegisterBlock = 0xe000_0000 as *const _; #[doc = r"Return the pointer to the register block"] #[inline(always)] - pub const fn ptr() -> *const io_qspi::RegisterBlock { + pub const fn ptr() -> *const ppb::RegisterBlock { Self::PTR } #[doc = r" Steal an instance of this peripheral"] @@ -669,31 +619,31 @@ impl IO_QSPI { } } } -impl Deref for IO_QSPI { - type Target = io_qspi::RegisterBlock; +impl Deref for PPB { + type Target = ppb::RegisterBlock; #[inline(always)] fn deref(&self) -> &Self::Target { unsafe { &*Self::PTR } } } -impl core::fmt::Debug for IO_QSPI { +impl core::fmt::Debug for PPB { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("IO_QSPI").finish() + f.debug_struct("PPB").finish() } } -#[doc = "IO_QSPI"] -pub mod io_qspi; -#[doc = "PADS_BANK0"] -pub struct PADS_BANK0 { +#[doc = "PPB"] +pub mod ppb; +#[doc = "DW_apb_ssi has the following features: * APB interface – Allows for easy integration into a DesignWare Synthesizable Components for AMBA 2 implementation. * APB3 and APB4 protocol support. * Scalable APB data bus width – Supports APB data bus widths of 8, 16, and 32 bits. * Serial-master or serial-slave operation – Enables serial communication with serial-master or serial-slave peripheral devices. * Programmable Dual/Quad/Octal SPI support in Master Mode. * Dual Data Rate (DDR) and Read Data Strobe (RDS) Support - Enables the DW_apb_ssi master to perform operations with the device in DDR and RDS modes when working in Dual/Quad/Octal mode of operation. * Data Mask Support - Enables the DW_apb_ssi to selectively update the bytes in the device. This feature is applicable only in enhanced SPI modes. * eXecute-In-Place (XIP) support - Enables the DW_apb_ssi master to behave as a memory mapped I/O and fetches the data from the device based on the APB read request. This feature is applicable only in enhanced SPI modes. * DMA Controller Interface – Enables the DW_apb_ssi to interface to a DMA controller over the bus using a handshaking interface for transfer requests. * Independent masking of interrupts – Master collision, transmit FIFO overflow, transmit FIFO empty, receive FIFO full, receive FIFO underflow, and receive FIFO overflow interrupts can all be masked independently. * Multi-master contention detection – Informs the processor of multiple serial-master accesses on the serial bus. * Bypass of meta-stability flip-flops for synchronous clocks – When the APB clock (pclk) and the DW_apb_ssi serial clock (ssi_clk) are synchronous, meta-stable flip-flops are not used when transferring control signals across these clock domains. * Programmable delay on the sample time of the received serial data bit (rxd); enables programmable control of routing delays resulting in higher serial data-bit rates. * Programmable features: - Serial interface operation – Choice of Motorola SPI, Texas Instruments Synchronous Serial Protocol or National Semiconductor Microwire. - Clock bit-rate – Dynamic control of the serial bit rate of the data transfer; used in only serial-master mode of operation. - Data Item size (4 to 32 bits) – Item size of each data transfer under the control of the programmer. * Configured features: - FIFO depth – 16 words deep. The FIFO width is fixed at 32 bits. - 1 slave select output. - Hardware slave-select – Dedicated hardware slave-select line. - Combined interrupt line - one combined interrupt line from the DW_apb_ssi to the interrupt controller. - Interrupt polarity – active high interrupt lines. - Serial clock polarity – low serial-clock polarity directly after reset. - Serial clock phase – capture on first edge of serial-clock directly after reset."] +pub struct SSI { _marker: PhantomData<*const ()>, } -unsafe impl Send for PADS_BANK0 {} -impl PADS_BANK0 { +unsafe impl Send for SSI {} +impl SSI { #[doc = r"Pointer to the register block"] - pub const PTR: *const pads_bank0::RegisterBlock = 0x4001_c000 as *const _; + pub const PTR: *const ssi::RegisterBlock = 0x1800_0000 as *const _; #[doc = r"Return the pointer to the register block"] #[inline(always)] - pub const fn ptr() -> *const pads_bank0::RegisterBlock { + pub const fn ptr() -> *const ssi::RegisterBlock { Self::PTR } #[doc = r" Steal an instance of this peripheral"] @@ -715,31 +665,31 @@ impl PADS_BANK0 { } } } -impl Deref for PADS_BANK0 { - type Target = pads_bank0::RegisterBlock; +impl Deref for SSI { + type Target = ssi::RegisterBlock; #[inline(always)] fn deref(&self) -> &Self::Target { unsafe { &*Self::PTR } } } -impl core::fmt::Debug for PADS_BANK0 { +impl core::fmt::Debug for SSI { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("PADS_BANK0").finish() + f.debug_struct("SSI").finish() } } -#[doc = "PADS_BANK0"] -pub mod pads_bank0; -#[doc = "PADS_QSPI"] -pub struct PADS_QSPI { +#[doc = "DW_apb_ssi has the following features: * APB interface – Allows for easy integration into a DesignWare Synthesizable Components for AMBA 2 implementation. * APB3 and APB4 protocol support. * Scalable APB data bus width – Supports APB data bus widths of 8, 16, and 32 bits. * Serial-master or serial-slave operation – Enables serial communication with serial-master or serial-slave peripheral devices. * Programmable Dual/Quad/Octal SPI support in Master Mode. * Dual Data Rate (DDR) and Read Data Strobe (RDS) Support - Enables the DW_apb_ssi master to perform operations with the device in DDR and RDS modes when working in Dual/Quad/Octal mode of operation. * Data Mask Support - Enables the DW_apb_ssi to selectively update the bytes in the device. This feature is applicable only in enhanced SPI modes. * eXecute-In-Place (XIP) support - Enables the DW_apb_ssi master to behave as a memory mapped I/O and fetches the data from the device based on the APB read request. This feature is applicable only in enhanced SPI modes. * DMA Controller Interface – Enables the DW_apb_ssi to interface to a DMA controller over the bus using a handshaking interface for transfer requests. * Independent masking of interrupts – Master collision, transmit FIFO overflow, transmit FIFO empty, receive FIFO full, receive FIFO underflow, and receive FIFO overflow interrupts can all be masked independently. * Multi-master contention detection – Informs the processor of multiple serial-master accesses on the serial bus. * Bypass of meta-stability flip-flops for synchronous clocks – When the APB clock (pclk) and the DW_apb_ssi serial clock (ssi_clk) are synchronous, meta-stable flip-flops are not used when transferring control signals across these clock domains. * Programmable delay on the sample time of the received serial data bit (rxd); enables programmable control of routing delays resulting in higher serial data-bit rates. * Programmable features: - Serial interface operation – Choice of Motorola SPI, Texas Instruments Synchronous Serial Protocol or National Semiconductor Microwire. - Clock bit-rate – Dynamic control of the serial bit rate of the data transfer; used in only serial-master mode of operation. - Data Item size (4 to 32 bits) – Item size of each data transfer under the control of the programmer. * Configured features: - FIFO depth – 16 words deep. The FIFO width is fixed at 32 bits. - 1 slave select output. - Hardware slave-select – Dedicated hardware slave-select line. - Combined interrupt line - one combined interrupt line from the DW_apb_ssi to the interrupt controller. - Interrupt polarity – active high interrupt lines. - Serial clock polarity – low serial-clock polarity directly after reset. - Serial clock phase – capture on first edge of serial-clock directly after reset."] +pub mod ssi; +#[doc = "QSPI flash execute-in-place block"] +pub struct XIP_CTRL { _marker: PhantomData<*const ()>, } -unsafe impl Send for PADS_QSPI {} -impl PADS_QSPI { +unsafe impl Send for XIP_CTRL {} +impl XIP_CTRL { #[doc = r"Pointer to the register block"] - pub const PTR: *const pads_qspi::RegisterBlock = 0x4002_0000 as *const _; + pub const PTR: *const xip_ctrl::RegisterBlock = 0x1400_0000 as *const _; #[doc = r"Return the pointer to the register block"] #[inline(always)] - pub const fn ptr() -> *const pads_qspi::RegisterBlock { + pub const fn ptr() -> *const xip_ctrl::RegisterBlock { Self::PTR } #[doc = r" Steal an instance of this peripheral"] @@ -761,31 +711,31 @@ impl PADS_QSPI { } } } -impl Deref for PADS_QSPI { - type Target = pads_qspi::RegisterBlock; +impl Deref for XIP_CTRL { + type Target = xip_ctrl::RegisterBlock; #[inline(always)] fn deref(&self) -> &Self::Target { unsafe { &*Self::PTR } } } -impl core::fmt::Debug for PADS_QSPI { +impl core::fmt::Debug for XIP_CTRL { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("PADS_QSPI").finish() + f.debug_struct("XIP_CTRL").finish() } } -#[doc = "PADS_QSPI"] -pub mod pads_qspi; -#[doc = "Controls the crystal oscillator"] -pub struct XOSC { +#[doc = "QSPI flash execute-in-place block"] +pub mod xip_ctrl; +#[doc = "Register block for various chip control signals"] +pub struct SYSCFG { _marker: PhantomData<*const ()>, } -unsafe impl Send for XOSC {} -impl XOSC { +unsafe impl Send for SYSCFG {} +impl SYSCFG { #[doc = r"Pointer to the register block"] - pub const PTR: *const xosc::RegisterBlock = 0x4002_4000 as *const _; + pub const PTR: *const syscfg::RegisterBlock = 0x4000_4000 as *const _; #[doc = r"Return the pointer to the register block"] #[inline(always)] - pub const fn ptr() -> *const xosc::RegisterBlock { + pub const fn ptr() -> *const syscfg::RegisterBlock { Self::PTR } #[doc = r" Steal an instance of this peripheral"] @@ -807,31 +757,31 @@ impl XOSC { } } } -impl Deref for XOSC { - type Target = xosc::RegisterBlock; +impl Deref for SYSCFG { + type Target = syscfg::RegisterBlock; #[inline(always)] fn deref(&self) -> &Self::Target { unsafe { &*Self::PTR } } } -impl core::fmt::Debug for XOSC { +impl core::fmt::Debug for SYSCFG { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("XOSC").finish() + f.debug_struct("SYSCFG").finish() } } +#[doc = "Register block for various chip control signals"] +pub mod syscfg; #[doc = "Controls the crystal oscillator"] -pub mod xosc; -#[doc = "PLL_SYS"] -pub struct PLL_SYS { +pub struct XOSC { _marker: PhantomData<*const ()>, } -unsafe impl Send for PLL_SYS {} -impl PLL_SYS { +unsafe impl Send for XOSC {} +impl XOSC { #[doc = r"Pointer to the register block"] - pub const PTR: *const pll_sys::RegisterBlock = 0x4002_8000 as *const _; + pub const PTR: *const xosc::RegisterBlock = 0x4002_4000 as *const _; #[doc = r"Return the pointer to the register block"] #[inline(always)] - pub const fn ptr() -> *const pll_sys::RegisterBlock { + pub const fn ptr() -> *const xosc::RegisterBlock { Self::PTR } #[doc = r" Steal an instance of this peripheral"] @@ -853,28 +803,28 @@ impl PLL_SYS { } } } -impl Deref for PLL_SYS { - type Target = pll_sys::RegisterBlock; +impl Deref for XOSC { + type Target = xosc::RegisterBlock; #[inline(always)] fn deref(&self) -> &Self::Target { unsafe { &*Self::PTR } } } -impl core::fmt::Debug for PLL_SYS { +impl core::fmt::Debug for XOSC { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("PLL_SYS").finish() + f.debug_struct("XOSC").finish() } } +#[doc = "Controls the crystal oscillator"] +pub mod xosc; #[doc = "PLL_SYS"] -pub mod pll_sys; -#[doc = "PLL_USB"] -pub struct PLL_USB { +pub struct PLL_SYS { _marker: PhantomData<*const ()>, } -unsafe impl Send for PLL_USB {} -impl PLL_USB { +unsafe impl Send for PLL_SYS {} +impl PLL_SYS { #[doc = r"Pointer to the register block"] - pub const PTR: *const pll_sys::RegisterBlock = 0x4002_c000 as *const _; + pub const PTR: *const pll_sys::RegisterBlock = 0x4002_8000 as *const _; #[doc = r"Return the pointer to the register block"] #[inline(always)] pub const fn ptr() -> *const pll_sys::RegisterBlock { @@ -899,31 +849,31 @@ impl PLL_USB { } } } -impl Deref for PLL_USB { +impl Deref for PLL_SYS { type Target = pll_sys::RegisterBlock; #[inline(always)] fn deref(&self) -> &Self::Target { unsafe { &*Self::PTR } } } -impl core::fmt::Debug for PLL_USB { +impl core::fmt::Debug for PLL_SYS { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("PLL_USB").finish() + f.debug_struct("PLL_SYS").finish() } } +#[doc = "PLL_SYS"] +pub mod pll_sys; #[doc = "PLL_USB"] -pub use self::pll_sys as pll_usb; -#[doc = "Register block for busfabric control signals and performance counters"] -pub struct BUSCTRL { +pub struct PLL_USB { _marker: PhantomData<*const ()>, } -unsafe impl Send for BUSCTRL {} -impl BUSCTRL { +unsafe impl Send for PLL_USB {} +impl PLL_USB { #[doc = r"Pointer to the register block"] - pub const PTR: *const busctrl::RegisterBlock = 0x4003_0000 as *const _; + pub const PTR: *const pll_sys::RegisterBlock = 0x4002_c000 as *const _; #[doc = r"Return the pointer to the register block"] #[inline(always)] - pub const fn ptr() -> *const busctrl::RegisterBlock { + pub const fn ptr() -> *const pll_sys::RegisterBlock { Self::PTR } #[doc = r" Steal an instance of this peripheral"] @@ -945,20 +895,20 @@ impl BUSCTRL { } } } -impl Deref for BUSCTRL { - type Target = busctrl::RegisterBlock; +impl Deref for PLL_USB { + type Target = pll_sys::RegisterBlock; #[inline(always)] fn deref(&self) -> &Self::Target { unsafe { &*Self::PTR } } } -impl core::fmt::Debug for BUSCTRL { +impl core::fmt::Debug for PLL_USB { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("BUSCTRL").finish() + f.debug_struct("PLL_USB").finish() } } -#[doc = "Register block for busfabric control signals and performance counters"] -pub mod busctrl; +#[doc = "PLL_USB"] +pub use self::pll_sys as pll_usb; #[doc = "UART0"] pub struct UART0 { _marker: PhantomData<*const ()>, @@ -1051,17 +1001,17 @@ impl core::fmt::Debug for UART1 { } #[doc = "UART1"] pub use self::uart0 as uart1; -#[doc = "SPI0"] -pub struct SPI0 { +#[doc = "ROSC"] +pub struct ROSC { _marker: PhantomData<*const ()>, } -unsafe impl Send for SPI0 {} -impl SPI0 { +unsafe impl Send for ROSC {} +impl ROSC { #[doc = r"Pointer to the register block"] - pub const PTR: *const spi0::RegisterBlock = 0x4003_c000 as *const _; + pub const PTR: *const rosc::RegisterBlock = 0x4006_0000 as *const _; #[doc = r"Return the pointer to the register block"] #[inline(always)] - pub const fn ptr() -> *const spi0::RegisterBlock { + pub const fn ptr() -> *const rosc::RegisterBlock { Self::PTR } #[doc = r" Steal an instance of this peripheral"] @@ -1083,31 +1033,31 @@ impl SPI0 { } } } -impl Deref for SPI0 { - type Target = spi0::RegisterBlock; +impl Deref for ROSC { + type Target = rosc::RegisterBlock; #[inline(always)] fn deref(&self) -> &Self::Target { unsafe { &*Self::PTR } } } -impl core::fmt::Debug for SPI0 { +impl core::fmt::Debug for ROSC { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SPI0").finish() + f.debug_struct("ROSC").finish() } } -#[doc = "SPI0"] -pub mod spi0; -#[doc = "SPI1"] -pub struct SPI1 { +#[doc = "ROSC"] +pub mod rosc; +#[doc = "WATCHDOG"] +pub struct WATCHDOG { _marker: PhantomData<*const ()>, } -unsafe impl Send for SPI1 {} -impl SPI1 { +unsafe impl Send for WATCHDOG {} +impl WATCHDOG { #[doc = r"Pointer to the register block"] - pub const PTR: *const spi0::RegisterBlock = 0x4004_0000 as *const _; + pub const PTR: *const watchdog::RegisterBlock = 0x4005_8000 as *const _; #[doc = r"Return the pointer to the register block"] #[inline(always)] - pub const fn ptr() -> *const spi0::RegisterBlock { + pub const fn ptr() -> *const watchdog::RegisterBlock { Self::PTR } #[doc = r" Steal an instance of this peripheral"] @@ -1129,102 +1079,31 @@ impl SPI1 { } } } -impl Deref for SPI1 { - type Target = spi0::RegisterBlock; +impl Deref for WATCHDOG { + type Target = watchdog::RegisterBlock; #[inline(always)] fn deref(&self) -> &Self::Target { unsafe { &*Self::PTR } } } -impl core::fmt::Debug for SPI1 { +impl core::fmt::Debug for WATCHDOG { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SPI1").finish() + f.debug_struct("WATCHDOG").finish() } } -#[doc = "SPI1"] -pub use self::spi0 as spi1; -#[doc = "DW_apb_i2c address block - - List of configuration constants for the Synopsys I2C hardware (you may see references to these in I2C register header; these are *fixed* values, set at hardware design time): - - IC_ULTRA_FAST_MODE ................ 0x0 - IC_UFM_TBUF_CNT_DEFAULT ........... 0x8 - IC_UFM_SCL_LOW_COUNT .............. 0x0008 - IC_UFM_SCL_HIGH_COUNT ............. 0x0006 - IC_TX_TL .......................... 0x0 - IC_TX_CMD_BLOCK ................... 0x1 - IC_HAS_DMA ........................ 0x1 - IC_HAS_ASYNC_FIFO ................. 0x0 - IC_SMBUS_ARP ...................... 0x0 - IC_FIRST_DATA_BYTE_STATUS ......... 0x1 - IC_INTR_IO ........................ 0x1 - IC_MASTER_MODE .................... 0x1 - IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1 - IC_INTR_POL ....................... 0x1 - IC_OPTIONAL_SAR ................... 0x0 - IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055 - IC_DEFAULT_SLAVE_ADDR ............. 0x055 - IC_DEFAULT_HS_SPKLEN .............. 0x1 - IC_FS_SCL_HIGH_COUNT .............. 0x0006 - IC_HS_SCL_LOW_COUNT ............... 0x0008 - IC_DEVICE_ID_VALUE ................ 0x0 - IC_10BITADDR_MASTER ............... 0x0 - IC_CLK_FREQ_OPTIMIZATION .......... 0x0 - IC_DEFAULT_FS_SPKLEN .............. 0x7 - IC_ADD_ENCODED_PARAMS ............. 0x0 - IC_DEFAULT_SDA_HOLD ............... 0x000001 - IC_DEFAULT_SDA_SETUP .............. 0x64 - IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0 - IC_CLOCK_PERIOD ................... 100 - IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1 - IC_RESTART_EN ..................... 0x1 - IC_TX_CMD_BLOCK_DEFAULT ........... 0x0 - IC_BUS_CLEAR_FEATURE .............. 0x0 - IC_CAP_LOADING .................... 100 - IC_FS_SCL_LOW_COUNT ............... 0x000d - APB_DATA_WIDTH .................... 32 - IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff - IC_SLV_DATA_NACK_ONLY ............. 0x1 - IC_10BITADDR_SLAVE ................ 0x0 - IC_CLK_TYPE ....................... 0x0 - IC_SMBUS_UDID_MSB ................. 0x0 - IC_SMBUS_SUSPEND_ALERT ............ 0x0 - IC_HS_SCL_HIGH_COUNT .............. 0x0006 - IC_SLV_RESTART_DET_EN ............. 0x1 - IC_SMBUS .......................... 0x0 - IC_OPTIONAL_SAR_DEFAULT ........... 0x0 - IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0 - IC_USE_COUNTS ..................... 0x0 - IC_RX_BUFFER_DEPTH ................ 16 - IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff - IC_RX_FULL_HLD_BUS_EN ............. 0x1 - IC_SLAVE_DISABLE .................. 0x1 - IC_RX_TL .......................... 0x0 - IC_DEVICE_ID ...................... 0x0 - IC_HC_COUNT_VALUES ................ 0x0 - I2C_DYNAMIC_TAR_UPDATE ............ 0 - IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff - IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff - IC_HS_MASTER_CODE ................. 0x1 - IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff - IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff - IC_SS_SCL_HIGH_COUNT .............. 0x0028 - IC_SS_SCL_LOW_COUNT ............... 0x002f - IC_MAX_SPEED_MODE ................. 0x2 - IC_STAT_FOR_CLK_STRETCH ........... 0x0 - IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0 - IC_DEFAULT_UFM_SPKLEN ............. 0x1 - IC_TX_BUFFER_DEPTH ................ 16"] -pub struct I2C0 { +#[doc = "WATCHDOG"] +pub mod watchdog; +#[doc = "DMA with separate read and write masters"] +pub struct DMA { _marker: PhantomData<*const ()>, } -unsafe impl Send for I2C0 {} -impl I2C0 { +unsafe impl Send for DMA {} +impl DMA { #[doc = r"Pointer to the register block"] - pub const PTR: *const i2c0::RegisterBlock = 0x4004_4000 as *const _; + pub const PTR: *const dma::RegisterBlock = 0x5000_0000 as *const _; #[doc = r"Return the pointer to the register block"] #[inline(always)] - pub const fn ptr() -> *const i2c0::RegisterBlock { + pub const fn ptr() -> *const dma::RegisterBlock { Self::PTR } #[doc = r" Steal an instance of this peripheral"] @@ -1246,173 +1125,31 @@ impl I2C0 { } } } -impl Deref for I2C0 { - type Target = i2c0::RegisterBlock; +impl Deref for DMA { + type Target = dma::RegisterBlock; #[inline(always)] fn deref(&self) -> &Self::Target { unsafe { &*Self::PTR } } } -impl core::fmt::Debug for I2C0 { +impl core::fmt::Debug for DMA { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("I2C0").finish() + f.debug_struct("DMA").finish() } } -#[doc = "DW_apb_i2c address block - - List of configuration constants for the Synopsys I2C hardware (you may see references to these in I2C register header; these are *fixed* values, set at hardware design time): - - IC_ULTRA_FAST_MODE ................ 0x0 - IC_UFM_TBUF_CNT_DEFAULT ........... 0x8 - IC_UFM_SCL_LOW_COUNT .............. 0x0008 - IC_UFM_SCL_HIGH_COUNT ............. 0x0006 - IC_TX_TL .......................... 0x0 - IC_TX_CMD_BLOCK ................... 0x1 - IC_HAS_DMA ........................ 0x1 - IC_HAS_ASYNC_FIFO ................. 0x0 - IC_SMBUS_ARP ...................... 0x0 - IC_FIRST_DATA_BYTE_STATUS ......... 0x1 - IC_INTR_IO ........................ 0x1 - IC_MASTER_MODE .................... 0x1 - IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1 - IC_INTR_POL ....................... 0x1 - IC_OPTIONAL_SAR ................... 0x0 - IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055 - IC_DEFAULT_SLAVE_ADDR ............. 0x055 - IC_DEFAULT_HS_SPKLEN .............. 0x1 - IC_FS_SCL_HIGH_COUNT .............. 0x0006 - IC_HS_SCL_LOW_COUNT ............... 0x0008 - IC_DEVICE_ID_VALUE ................ 0x0 - IC_10BITADDR_MASTER ............... 0x0 - IC_CLK_FREQ_OPTIMIZATION .......... 0x0 - IC_DEFAULT_FS_SPKLEN .............. 0x7 - IC_ADD_ENCODED_PARAMS ............. 0x0 - IC_DEFAULT_SDA_HOLD ............... 0x000001 - IC_DEFAULT_SDA_SETUP .............. 0x64 - IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0 - IC_CLOCK_PERIOD ................... 100 - IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1 - IC_RESTART_EN ..................... 0x1 - IC_TX_CMD_BLOCK_DEFAULT ........... 0x0 - IC_BUS_CLEAR_FEATURE .............. 0x0 - IC_CAP_LOADING .................... 100 - IC_FS_SCL_LOW_COUNT ............... 0x000d - APB_DATA_WIDTH .................... 32 - IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff - IC_SLV_DATA_NACK_ONLY ............. 0x1 - IC_10BITADDR_SLAVE ................ 0x0 - IC_CLK_TYPE ....................... 0x0 - IC_SMBUS_UDID_MSB ................. 0x0 - IC_SMBUS_SUSPEND_ALERT ............ 0x0 - IC_HS_SCL_HIGH_COUNT .............. 0x0006 - IC_SLV_RESTART_DET_EN ............. 0x1 - IC_SMBUS .......................... 0x0 - IC_OPTIONAL_SAR_DEFAULT ........... 0x0 - IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0 - IC_USE_COUNTS ..................... 0x0 - IC_RX_BUFFER_DEPTH ................ 16 - IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff - IC_RX_FULL_HLD_BUS_EN ............. 0x1 - IC_SLAVE_DISABLE .................. 0x1 - IC_RX_TL .......................... 0x0 - IC_DEVICE_ID ...................... 0x0 - IC_HC_COUNT_VALUES ................ 0x0 - I2C_DYNAMIC_TAR_UPDATE ............ 0 - IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff - IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff - IC_HS_MASTER_CODE ................. 0x1 - IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff - IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff - IC_SS_SCL_HIGH_COUNT .............. 0x0028 - IC_SS_SCL_LOW_COUNT ............... 0x002f - IC_MAX_SPEED_MODE ................. 0x2 - IC_STAT_FOR_CLK_STRETCH ........... 0x0 - IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0 - IC_DEFAULT_UFM_SPKLEN ............. 0x1 - IC_TX_BUFFER_DEPTH ................ 16"] -pub mod i2c0; -#[doc = "DW_apb_i2c address block - - List of configuration constants for the Synopsys I2C hardware (you may see references to these in I2C register header; these are *fixed* values, set at hardware design time): - - IC_ULTRA_FAST_MODE ................ 0x0 - IC_UFM_TBUF_CNT_DEFAULT ........... 0x8 - IC_UFM_SCL_LOW_COUNT .............. 0x0008 - IC_UFM_SCL_HIGH_COUNT ............. 0x0006 - IC_TX_TL .......................... 0x0 - IC_TX_CMD_BLOCK ................... 0x1 - IC_HAS_DMA ........................ 0x1 - IC_HAS_ASYNC_FIFO ................. 0x0 - IC_SMBUS_ARP ...................... 0x0 - IC_FIRST_DATA_BYTE_STATUS ......... 0x1 - IC_INTR_IO ........................ 0x1 - IC_MASTER_MODE .................... 0x1 - IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1 - IC_INTR_POL ....................... 0x1 - IC_OPTIONAL_SAR ................... 0x0 - IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055 - IC_DEFAULT_SLAVE_ADDR ............. 0x055 - IC_DEFAULT_HS_SPKLEN .............. 0x1 - IC_FS_SCL_HIGH_COUNT .............. 0x0006 - IC_HS_SCL_LOW_COUNT ............... 0x0008 - IC_DEVICE_ID_VALUE ................ 0x0 - IC_10BITADDR_MASTER ............... 0x0 - IC_CLK_FREQ_OPTIMIZATION .......... 0x0 - IC_DEFAULT_FS_SPKLEN .............. 0x7 - IC_ADD_ENCODED_PARAMS ............. 0x0 - IC_DEFAULT_SDA_HOLD ............... 0x000001 - IC_DEFAULT_SDA_SETUP .............. 0x64 - IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0 - IC_CLOCK_PERIOD ................... 100 - IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1 - IC_RESTART_EN ..................... 0x1 - IC_TX_CMD_BLOCK_DEFAULT ........... 0x0 - IC_BUS_CLEAR_FEATURE .............. 0x0 - IC_CAP_LOADING .................... 100 - IC_FS_SCL_LOW_COUNT ............... 0x000d - APB_DATA_WIDTH .................... 32 - IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff - IC_SLV_DATA_NACK_ONLY ............. 0x1 - IC_10BITADDR_SLAVE ................ 0x0 - IC_CLK_TYPE ....................... 0x0 - IC_SMBUS_UDID_MSB ................. 0x0 - IC_SMBUS_SUSPEND_ALERT ............ 0x0 - IC_HS_SCL_HIGH_COUNT .............. 0x0006 - IC_SLV_RESTART_DET_EN ............. 0x1 - IC_SMBUS .......................... 0x0 - IC_OPTIONAL_SAR_DEFAULT ........... 0x0 - IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0 - IC_USE_COUNTS ..................... 0x0 - IC_RX_BUFFER_DEPTH ................ 16 - IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff - IC_RX_FULL_HLD_BUS_EN ............. 0x1 - IC_SLAVE_DISABLE .................. 0x1 - IC_RX_TL .......................... 0x0 - IC_DEVICE_ID ...................... 0x0 - IC_HC_COUNT_VALUES ................ 0x0 - I2C_DYNAMIC_TAR_UPDATE ............ 0 - IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff - IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff - IC_HS_MASTER_CODE ................. 0x1 - IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff - IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff - IC_SS_SCL_HIGH_COUNT .............. 0x0028 - IC_SS_SCL_LOW_COUNT ............... 0x002f - IC_MAX_SPEED_MODE ................. 0x2 - IC_STAT_FOR_CLK_STRETCH ........... 0x0 - IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0 - IC_DEFAULT_UFM_SPKLEN ............. 0x1 - IC_TX_BUFFER_DEPTH ................ 16"] -pub struct I2C1 { +#[doc = "DMA with separate read and write masters"] +pub mod dma; +#[doc = "Controls time and alarms time is a 64 bit value indicating the time in usec since power-on timeh is the top 32 bits of time & timel is the bottom 32 bits to change time write to timelw before timehw to read time read from timelr before timehr An alarm is set by setting alarm_enable and writing to the corresponding alarm register When an alarm is pending, the corresponding alarm_running signal will be high An alarm can be cancelled before it has finished by clearing the alarm_enable When an alarm fires, the corresponding alarm_irq is set and alarm_running is cleared To clear the interrupt write a 1 to the corresponding alarm_irq"] +pub struct TIMER { _marker: PhantomData<*const ()>, } -unsafe impl Send for I2C1 {} -impl I2C1 { +unsafe impl Send for TIMER {} +impl TIMER { #[doc = r"Pointer to the register block"] - pub const PTR: *const i2c0::RegisterBlock = 0x4004_8000 as *const _; + pub const PTR: *const timer::RegisterBlock = 0x4005_4000 as *const _; #[doc = r"Return the pointer to the register block"] #[inline(always)] - pub const fn ptr() -> *const i2c0::RegisterBlock { + pub const fn ptr() -> *const timer::RegisterBlock { Self::PTR } #[doc = r" Steal an instance of this peripheral"] @@ -1434,102 +1171,31 @@ impl I2C1 { } } } -impl Deref for I2C1 { - type Target = i2c0::RegisterBlock; +impl Deref for TIMER { + type Target = timer::RegisterBlock; #[inline(always)] fn deref(&self) -> &Self::Target { unsafe { &*Self::PTR } } } -impl core::fmt::Debug for I2C1 { +impl core::fmt::Debug for TIMER { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("I2C1").finish() + f.debug_struct("TIMER").finish() } } -#[doc = "DW_apb_i2c address block - - List of configuration constants for the Synopsys I2C hardware (you may see references to these in I2C register header; these are *fixed* values, set at hardware design time): - - IC_ULTRA_FAST_MODE ................ 0x0 - IC_UFM_TBUF_CNT_DEFAULT ........... 0x8 - IC_UFM_SCL_LOW_COUNT .............. 0x0008 - IC_UFM_SCL_HIGH_COUNT ............. 0x0006 - IC_TX_TL .......................... 0x0 - IC_TX_CMD_BLOCK ................... 0x1 - IC_HAS_DMA ........................ 0x1 - IC_HAS_ASYNC_FIFO ................. 0x0 - IC_SMBUS_ARP ...................... 0x0 - IC_FIRST_DATA_BYTE_STATUS ......... 0x1 - IC_INTR_IO ........................ 0x1 - IC_MASTER_MODE .................... 0x1 - IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1 - IC_INTR_POL ....................... 0x1 - IC_OPTIONAL_SAR ................... 0x0 - IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055 - IC_DEFAULT_SLAVE_ADDR ............. 0x055 - IC_DEFAULT_HS_SPKLEN .............. 0x1 - IC_FS_SCL_HIGH_COUNT .............. 0x0006 - IC_HS_SCL_LOW_COUNT ............... 0x0008 - IC_DEVICE_ID_VALUE ................ 0x0 - IC_10BITADDR_MASTER ............... 0x0 - IC_CLK_FREQ_OPTIMIZATION .......... 0x0 - IC_DEFAULT_FS_SPKLEN .............. 0x7 - IC_ADD_ENCODED_PARAMS ............. 0x0 - IC_DEFAULT_SDA_HOLD ............... 0x000001 - IC_DEFAULT_SDA_SETUP .............. 0x64 - IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0 - IC_CLOCK_PERIOD ................... 100 - IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1 - IC_RESTART_EN ..................... 0x1 - IC_TX_CMD_BLOCK_DEFAULT ........... 0x0 - IC_BUS_CLEAR_FEATURE .............. 0x0 - IC_CAP_LOADING .................... 100 - IC_FS_SCL_LOW_COUNT ............... 0x000d - APB_DATA_WIDTH .................... 32 - IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff - IC_SLV_DATA_NACK_ONLY ............. 0x1 - IC_10BITADDR_SLAVE ................ 0x0 - IC_CLK_TYPE ....................... 0x0 - IC_SMBUS_UDID_MSB ................. 0x0 - IC_SMBUS_SUSPEND_ALERT ............ 0x0 - IC_HS_SCL_HIGH_COUNT .............. 0x0006 - IC_SLV_RESTART_DET_EN ............. 0x1 - IC_SMBUS .......................... 0x0 - IC_OPTIONAL_SAR_DEFAULT ........... 0x0 - IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0 - IC_USE_COUNTS ..................... 0x0 - IC_RX_BUFFER_DEPTH ................ 16 - IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff - IC_RX_FULL_HLD_BUS_EN ............. 0x1 - IC_SLAVE_DISABLE .................. 0x1 - IC_RX_TL .......................... 0x0 - IC_DEVICE_ID ...................... 0x0 - IC_HC_COUNT_VALUES ................ 0x0 - I2C_DYNAMIC_TAR_UPDATE ............ 0 - IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff - IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff - IC_HS_MASTER_CODE ................. 0x1 - IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff - IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff - IC_SS_SCL_HIGH_COUNT .............. 0x0028 - IC_SS_SCL_LOW_COUNT ............... 0x002f - IC_MAX_SPEED_MODE ................. 0x2 - IC_STAT_FOR_CLK_STRETCH ........... 0x0 - IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0 - IC_DEFAULT_UFM_SPKLEN ............. 0x1 - IC_TX_BUFFER_DEPTH ................ 16"] -pub use self::i2c0 as i2c1; -#[doc = "Control and data interface to SAR ADC"] -pub struct ADC { +#[doc = "Controls time and alarms time is a 64 bit value indicating the time in usec since power-on timeh is the top 32 bits of time & timel is the bottom 32 bits to change time write to timelw before timehw to read time read from timelr before timehr An alarm is set by setting alarm_enable and writing to the corresponding alarm register When an alarm is pending, the corresponding alarm_running signal will be high An alarm can be cancelled before it has finished by clearing the alarm_enable When an alarm fires, the corresponding alarm_irq is set and alarm_running is cleared To clear the interrupt write a 1 to the corresponding alarm_irq"] +pub mod timer; +#[doc = "Simple PWM"] +pub struct PWM { _marker: PhantomData<*const ()>, } -unsafe impl Send for ADC {} -impl ADC { +unsafe impl Send for PWM {} +impl PWM { #[doc = r"Pointer to the register block"] - pub const PTR: *const adc::RegisterBlock = 0x4004_c000 as *const _; + pub const PTR: *const pwm::RegisterBlock = 0x4005_0000 as *const _; #[doc = r"Return the pointer to the register block"] #[inline(always)] - pub const fn ptr() -> *const adc::RegisterBlock { + pub const fn ptr() -> *const pwm::RegisterBlock { Self::PTR } #[doc = r" Steal an instance of this peripheral"] @@ -1551,31 +1217,31 @@ impl ADC { } } } -impl Deref for ADC { - type Target = adc::RegisterBlock; +impl Deref for PWM { + type Target = pwm::RegisterBlock; #[inline(always)] fn deref(&self) -> &Self::Target { unsafe { &*Self::PTR } } } -impl core::fmt::Debug for ADC { +impl core::fmt::Debug for PWM { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("ADC").finish() + f.debug_struct("PWM").finish() } } -#[doc = "Control and data interface to SAR ADC"] -pub mod adc; #[doc = "Simple PWM"] -pub struct PWM { +pub mod pwm; +#[doc = "Control and data interface to SAR ADC"] +pub struct ADC { _marker: PhantomData<*const ()>, } -unsafe impl Send for PWM {} -impl PWM { +unsafe impl Send for ADC {} +impl ADC { #[doc = r"Pointer to the register block"] - pub const PTR: *const pwm::RegisterBlock = 0x4005_0000 as *const _; + pub const PTR: *const adc::RegisterBlock = 0x4004_c000 as *const _; #[doc = r"Return the pointer to the register block"] #[inline(always)] - pub const fn ptr() -> *const pwm::RegisterBlock { + pub const fn ptr() -> *const adc::RegisterBlock { Self::PTR } #[doc = r" Steal an instance of this peripheral"] @@ -1597,40 +1263,31 @@ impl PWM { } } } -impl Deref for PWM { - type Target = pwm::RegisterBlock; +impl Deref for ADC { + type Target = adc::RegisterBlock; #[inline(always)] fn deref(&self) -> &Self::Target { unsafe { &*Self::PTR } } } -impl core::fmt::Debug for PWM { +impl core::fmt::Debug for ADC { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("PWM").finish() + f.debug_struct("ADC").finish() } } -#[doc = "Simple PWM"] -pub mod pwm; -#[doc = "Controls time and alarms - time is a 64 bit value indicating the time in usec since power-on - timeh is the top 32 bits of time & timel is the bottom 32 bits - to change time write to timelw before timehw - to read time read from timelr before timehr - An alarm is set by setting alarm_enable and writing to the corresponding alarm register - When an alarm is pending, the corresponding alarm_running signal will be high - An alarm can be cancelled before it has finished by clearing the alarm_enable - When an alarm fires, the corresponding alarm_irq is set and alarm_running is cleared - To clear the interrupt write a 1 to the corresponding alarm_irq"] -pub struct TIMER { +#[doc = "Control and data interface to SAR ADC"] +pub mod adc; +#[doc = "DW_apb_i2c address block List of configuration constants for the Synopsys I2C hardware (you may see references to these in I2C register header; these are *fixed* values, set at hardware design time): IC_ULTRA_FAST_MODE ................ 0x0 IC_UFM_TBUF_CNT_DEFAULT ........... 0x8 IC_UFM_SCL_LOW_COUNT .............. 0x0008 IC_UFM_SCL_HIGH_COUNT ............. 0x0006 IC_TX_TL .......................... 0x0 IC_TX_CMD_BLOCK ................... 0x1 IC_HAS_DMA ........................ 0x1 IC_HAS_ASYNC_FIFO ................. 0x0 IC_SMBUS_ARP ...................... 0x0 IC_FIRST_DATA_BYTE_STATUS ......... 0x1 IC_INTR_IO ........................ 0x1 IC_MASTER_MODE .................... 0x1 IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1 IC_INTR_POL ....................... 0x1 IC_OPTIONAL_SAR ................... 0x0 IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055 IC_DEFAULT_SLAVE_ADDR ............. 0x055 IC_DEFAULT_HS_SPKLEN .............. 0x1 IC_FS_SCL_HIGH_COUNT .............. 0x0006 IC_HS_SCL_LOW_COUNT ............... 0x0008 IC_DEVICE_ID_VALUE ................ 0x0 IC_10BITADDR_MASTER ............... 0x0 IC_CLK_FREQ_OPTIMIZATION .......... 0x0 IC_DEFAULT_FS_SPKLEN .............. 0x7 IC_ADD_ENCODED_PARAMS ............. 0x0 IC_DEFAULT_SDA_HOLD ............... 0x000001 IC_DEFAULT_SDA_SETUP .............. 0x64 IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0 IC_CLOCK_PERIOD ................... 100 IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1 IC_RESTART_EN ..................... 0x1 IC_TX_CMD_BLOCK_DEFAULT ........... 0x0 IC_BUS_CLEAR_FEATURE .............. 0x0 IC_CAP_LOADING .................... 100 IC_FS_SCL_LOW_COUNT ............... 0x000d APB_DATA_WIDTH .................... 32 IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff IC_SLV_DATA_NACK_ONLY ............. 0x1 IC_10BITADDR_SLAVE ................ 0x0 IC_CLK_TYPE ....................... 0x0 IC_SMBUS_UDID_MSB ................. 0x0 IC_SMBUS_SUSPEND_ALERT ............ 0x0 IC_HS_SCL_HIGH_COUNT .............. 0x0006 IC_SLV_RESTART_DET_EN ............. 0x1 IC_SMBUS .......................... 0x0 IC_OPTIONAL_SAR_DEFAULT ........... 0x0 IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0 IC_USE_COUNTS ..................... 0x0 IC_RX_BUFFER_DEPTH ................ 16 IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff IC_RX_FULL_HLD_BUS_EN ............. 0x1 IC_SLAVE_DISABLE .................. 0x1 IC_RX_TL .......................... 0x0 IC_DEVICE_ID ...................... 0x0 IC_HC_COUNT_VALUES ................ 0x0 I2C_DYNAMIC_TAR_UPDATE ............ 0 IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff IC_HS_MASTER_CODE ................. 0x1 IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff IC_SS_SCL_HIGH_COUNT .............. 0x0028 IC_SS_SCL_LOW_COUNT ............... 0x002f IC_MAX_SPEED_MODE ................. 0x2 IC_STAT_FOR_CLK_STRETCH ........... 0x0 IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0 IC_DEFAULT_UFM_SPKLEN ............. 0x1 IC_TX_BUFFER_DEPTH ................ 16"] +pub struct I2C0 { _marker: PhantomData<*const ()>, } -unsafe impl Send for TIMER {} -impl TIMER { +unsafe impl Send for I2C0 {} +impl I2C0 { #[doc = r"Pointer to the register block"] - pub const PTR: *const timer::RegisterBlock = 0x4005_4000 as *const _; + pub const PTR: *const i2c0::RegisterBlock = 0x4004_4000 as *const _; #[doc = r"Return the pointer to the register block"] #[inline(always)] - pub const fn ptr() -> *const timer::RegisterBlock { + pub const fn ptr() -> *const i2c0::RegisterBlock { Self::PTR } #[doc = r" Steal an instance of this peripheral"] @@ -1652,40 +1309,31 @@ impl TIMER { } } } -impl Deref for TIMER { - type Target = timer::RegisterBlock; +impl Deref for I2C0 { + type Target = i2c0::RegisterBlock; #[inline(always)] fn deref(&self) -> &Self::Target { unsafe { &*Self::PTR } } } -impl core::fmt::Debug for TIMER { +impl core::fmt::Debug for I2C0 { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("TIMER").finish() + f.debug_struct("I2C0").finish() } } -#[doc = "Controls time and alarms - time is a 64 bit value indicating the time in usec since power-on - timeh is the top 32 bits of time & timel is the bottom 32 bits - to change time write to timelw before timehw - to read time read from timelr before timehr - An alarm is set by setting alarm_enable and writing to the corresponding alarm register - When an alarm is pending, the corresponding alarm_running signal will be high - An alarm can be cancelled before it has finished by clearing the alarm_enable - When an alarm fires, the corresponding alarm_irq is set and alarm_running is cleared - To clear the interrupt write a 1 to the corresponding alarm_irq"] -pub mod timer; -#[doc = "WATCHDOG"] -pub struct WATCHDOG { +#[doc = "DW_apb_i2c address block List of configuration constants for the Synopsys I2C hardware (you may see references to these in I2C register header; these are *fixed* values, set at hardware design time): IC_ULTRA_FAST_MODE ................ 0x0 IC_UFM_TBUF_CNT_DEFAULT ........... 0x8 IC_UFM_SCL_LOW_COUNT .............. 0x0008 IC_UFM_SCL_HIGH_COUNT ............. 0x0006 IC_TX_TL .......................... 0x0 IC_TX_CMD_BLOCK ................... 0x1 IC_HAS_DMA ........................ 0x1 IC_HAS_ASYNC_FIFO ................. 0x0 IC_SMBUS_ARP ...................... 0x0 IC_FIRST_DATA_BYTE_STATUS ......... 0x1 IC_INTR_IO ........................ 0x1 IC_MASTER_MODE .................... 0x1 IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1 IC_INTR_POL ....................... 0x1 IC_OPTIONAL_SAR ................... 0x0 IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055 IC_DEFAULT_SLAVE_ADDR ............. 0x055 IC_DEFAULT_HS_SPKLEN .............. 0x1 IC_FS_SCL_HIGH_COUNT .............. 0x0006 IC_HS_SCL_LOW_COUNT ............... 0x0008 IC_DEVICE_ID_VALUE ................ 0x0 IC_10BITADDR_MASTER ............... 0x0 IC_CLK_FREQ_OPTIMIZATION .......... 0x0 IC_DEFAULT_FS_SPKLEN .............. 0x7 IC_ADD_ENCODED_PARAMS ............. 0x0 IC_DEFAULT_SDA_HOLD ............... 0x000001 IC_DEFAULT_SDA_SETUP .............. 0x64 IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0 IC_CLOCK_PERIOD ................... 100 IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1 IC_RESTART_EN ..................... 0x1 IC_TX_CMD_BLOCK_DEFAULT ........... 0x0 IC_BUS_CLEAR_FEATURE .............. 0x0 IC_CAP_LOADING .................... 100 IC_FS_SCL_LOW_COUNT ............... 0x000d APB_DATA_WIDTH .................... 32 IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff IC_SLV_DATA_NACK_ONLY ............. 0x1 IC_10BITADDR_SLAVE ................ 0x0 IC_CLK_TYPE ....................... 0x0 IC_SMBUS_UDID_MSB ................. 0x0 IC_SMBUS_SUSPEND_ALERT ............ 0x0 IC_HS_SCL_HIGH_COUNT .............. 0x0006 IC_SLV_RESTART_DET_EN ............. 0x1 IC_SMBUS .......................... 0x0 IC_OPTIONAL_SAR_DEFAULT ........... 0x0 IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0 IC_USE_COUNTS ..................... 0x0 IC_RX_BUFFER_DEPTH ................ 16 IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff IC_RX_FULL_HLD_BUS_EN ............. 0x1 IC_SLAVE_DISABLE .................. 0x1 IC_RX_TL .......................... 0x0 IC_DEVICE_ID ...................... 0x0 IC_HC_COUNT_VALUES ................ 0x0 I2C_DYNAMIC_TAR_UPDATE ............ 0 IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff IC_HS_MASTER_CODE ................. 0x1 IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff IC_SS_SCL_HIGH_COUNT .............. 0x0028 IC_SS_SCL_LOW_COUNT ............... 0x002f IC_MAX_SPEED_MODE ................. 0x2 IC_STAT_FOR_CLK_STRETCH ........... 0x0 IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0 IC_DEFAULT_UFM_SPKLEN ............. 0x1 IC_TX_BUFFER_DEPTH ................ 16"] +pub mod i2c0; +#[doc = "DW_apb_i2c address block List of configuration constants for the Synopsys I2C hardware (you may see references to these in I2C register header; these are *fixed* values, set at hardware design time): IC_ULTRA_FAST_MODE ................ 0x0 IC_UFM_TBUF_CNT_DEFAULT ........... 0x8 IC_UFM_SCL_LOW_COUNT .............. 0x0008 IC_UFM_SCL_HIGH_COUNT ............. 0x0006 IC_TX_TL .......................... 0x0 IC_TX_CMD_BLOCK ................... 0x1 IC_HAS_DMA ........................ 0x1 IC_HAS_ASYNC_FIFO ................. 0x0 IC_SMBUS_ARP ...................... 0x0 IC_FIRST_DATA_BYTE_STATUS ......... 0x1 IC_INTR_IO ........................ 0x1 IC_MASTER_MODE .................... 0x1 IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1 IC_INTR_POL ....................... 0x1 IC_OPTIONAL_SAR ................... 0x0 IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055 IC_DEFAULT_SLAVE_ADDR ............. 0x055 IC_DEFAULT_HS_SPKLEN .............. 0x1 IC_FS_SCL_HIGH_COUNT .............. 0x0006 IC_HS_SCL_LOW_COUNT ............... 0x0008 IC_DEVICE_ID_VALUE ................ 0x0 IC_10BITADDR_MASTER ............... 0x0 IC_CLK_FREQ_OPTIMIZATION .......... 0x0 IC_DEFAULT_FS_SPKLEN .............. 0x7 IC_ADD_ENCODED_PARAMS ............. 0x0 IC_DEFAULT_SDA_HOLD ............... 0x000001 IC_DEFAULT_SDA_SETUP .............. 0x64 IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0 IC_CLOCK_PERIOD ................... 100 IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1 IC_RESTART_EN ..................... 0x1 IC_TX_CMD_BLOCK_DEFAULT ........... 0x0 IC_BUS_CLEAR_FEATURE .............. 0x0 IC_CAP_LOADING .................... 100 IC_FS_SCL_LOW_COUNT ............... 0x000d APB_DATA_WIDTH .................... 32 IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff IC_SLV_DATA_NACK_ONLY ............. 0x1 IC_10BITADDR_SLAVE ................ 0x0 IC_CLK_TYPE ....................... 0x0 IC_SMBUS_UDID_MSB ................. 0x0 IC_SMBUS_SUSPEND_ALERT ............ 0x0 IC_HS_SCL_HIGH_COUNT .............. 0x0006 IC_SLV_RESTART_DET_EN ............. 0x1 IC_SMBUS .......................... 0x0 IC_OPTIONAL_SAR_DEFAULT ........... 0x0 IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0 IC_USE_COUNTS ..................... 0x0 IC_RX_BUFFER_DEPTH ................ 16 IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff IC_RX_FULL_HLD_BUS_EN ............. 0x1 IC_SLAVE_DISABLE .................. 0x1 IC_RX_TL .......................... 0x0 IC_DEVICE_ID ...................... 0x0 IC_HC_COUNT_VALUES ................ 0x0 I2C_DYNAMIC_TAR_UPDATE ............ 0 IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff IC_HS_MASTER_CODE ................. 0x1 IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff IC_SS_SCL_HIGH_COUNT .............. 0x0028 IC_SS_SCL_LOW_COUNT ............... 0x002f IC_MAX_SPEED_MODE ................. 0x2 IC_STAT_FOR_CLK_STRETCH ........... 0x0 IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0 IC_DEFAULT_UFM_SPKLEN ............. 0x1 IC_TX_BUFFER_DEPTH ................ 16"] +pub struct I2C1 { _marker: PhantomData<*const ()>, } -unsafe impl Send for WATCHDOG {} -impl WATCHDOG { +unsafe impl Send for I2C1 {} +impl I2C1 { #[doc = r"Pointer to the register block"] - pub const PTR: *const watchdog::RegisterBlock = 0x4005_8000 as *const _; + pub const PTR: *const i2c0::RegisterBlock = 0x4004_8000 as *const _; #[doc = r"Return the pointer to the register block"] #[inline(always)] - pub const fn ptr() -> *const watchdog::RegisterBlock { + pub const fn ptr() -> *const i2c0::RegisterBlock { Self::PTR } #[doc = r" Steal an instance of this peripheral"] @@ -1707,31 +1355,31 @@ impl WATCHDOG { } } } -impl Deref for WATCHDOG { - type Target = watchdog::RegisterBlock; +impl Deref for I2C1 { + type Target = i2c0::RegisterBlock; #[inline(always)] fn deref(&self) -> &Self::Target { unsafe { &*Self::PTR } } } -impl core::fmt::Debug for WATCHDOG { +impl core::fmt::Debug for I2C1 { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("WATCHDOG").finish() + f.debug_struct("I2C1").finish() } } -#[doc = "WATCHDOG"] -pub mod watchdog; -#[doc = "Register block to control RTC"] -pub struct RTC { +#[doc = "DW_apb_i2c address block List of configuration constants for the Synopsys I2C hardware (you may see references to these in I2C register header; these are *fixed* values, set at hardware design time): IC_ULTRA_FAST_MODE ................ 0x0 IC_UFM_TBUF_CNT_DEFAULT ........... 0x8 IC_UFM_SCL_LOW_COUNT .............. 0x0008 IC_UFM_SCL_HIGH_COUNT ............. 0x0006 IC_TX_TL .......................... 0x0 IC_TX_CMD_BLOCK ................... 0x1 IC_HAS_DMA ........................ 0x1 IC_HAS_ASYNC_FIFO ................. 0x0 IC_SMBUS_ARP ...................... 0x0 IC_FIRST_DATA_BYTE_STATUS ......... 0x1 IC_INTR_IO ........................ 0x1 IC_MASTER_MODE .................... 0x1 IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1 IC_INTR_POL ....................... 0x1 IC_OPTIONAL_SAR ................... 0x0 IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055 IC_DEFAULT_SLAVE_ADDR ............. 0x055 IC_DEFAULT_HS_SPKLEN .............. 0x1 IC_FS_SCL_HIGH_COUNT .............. 0x0006 IC_HS_SCL_LOW_COUNT ............... 0x0008 IC_DEVICE_ID_VALUE ................ 0x0 IC_10BITADDR_MASTER ............... 0x0 IC_CLK_FREQ_OPTIMIZATION .......... 0x0 IC_DEFAULT_FS_SPKLEN .............. 0x7 IC_ADD_ENCODED_PARAMS ............. 0x0 IC_DEFAULT_SDA_HOLD ............... 0x000001 IC_DEFAULT_SDA_SETUP .............. 0x64 IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0 IC_CLOCK_PERIOD ................... 100 IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1 IC_RESTART_EN ..................... 0x1 IC_TX_CMD_BLOCK_DEFAULT ........... 0x0 IC_BUS_CLEAR_FEATURE .............. 0x0 IC_CAP_LOADING .................... 100 IC_FS_SCL_LOW_COUNT ............... 0x000d APB_DATA_WIDTH .................... 32 IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff IC_SLV_DATA_NACK_ONLY ............. 0x1 IC_10BITADDR_SLAVE ................ 0x0 IC_CLK_TYPE ....................... 0x0 IC_SMBUS_UDID_MSB ................. 0x0 IC_SMBUS_SUSPEND_ALERT ............ 0x0 IC_HS_SCL_HIGH_COUNT .............. 0x0006 IC_SLV_RESTART_DET_EN ............. 0x1 IC_SMBUS .......................... 0x0 IC_OPTIONAL_SAR_DEFAULT ........... 0x0 IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0 IC_USE_COUNTS ..................... 0x0 IC_RX_BUFFER_DEPTH ................ 16 IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff IC_RX_FULL_HLD_BUS_EN ............. 0x1 IC_SLAVE_DISABLE .................. 0x1 IC_RX_TL .......................... 0x0 IC_DEVICE_ID ...................... 0x0 IC_HC_COUNT_VALUES ................ 0x0 I2C_DYNAMIC_TAR_UPDATE ............ 0 IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff IC_HS_MASTER_CODE ................. 0x1 IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff IC_SS_SCL_HIGH_COUNT .............. 0x0028 IC_SS_SCL_LOW_COUNT ............... 0x002f IC_MAX_SPEED_MODE ................. 0x2 IC_STAT_FOR_CLK_STRETCH ........... 0x0 IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0 IC_DEFAULT_UFM_SPKLEN ............. 0x1 IC_TX_BUFFER_DEPTH ................ 16"] +pub use self::i2c0 as i2c1; +#[doc = "SPI0"] +pub struct SPI0 { _marker: PhantomData<*const ()>, } -unsafe impl Send for RTC {} -impl RTC { +unsafe impl Send for SPI0 {} +impl SPI0 { #[doc = r"Pointer to the register block"] - pub const PTR: *const rtc::RegisterBlock = 0x4005_c000 as *const _; + pub const PTR: *const spi0::RegisterBlock = 0x4003_c000 as *const _; #[doc = r"Return the pointer to the register block"] #[inline(always)] - pub const fn ptr() -> *const rtc::RegisterBlock { + pub const fn ptr() -> *const spi0::RegisterBlock { Self::PTR } #[doc = r" Steal an instance of this peripheral"] @@ -1753,31 +1401,31 @@ impl RTC { } } } -impl Deref for RTC { - type Target = rtc::RegisterBlock; +impl Deref for SPI0 { + type Target = spi0::RegisterBlock; #[inline(always)] fn deref(&self) -> &Self::Target { unsafe { &*Self::PTR } } } -impl core::fmt::Debug for RTC { +impl core::fmt::Debug for SPI0 { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("RTC").finish() + f.debug_struct("SPI0").finish() } } -#[doc = "Register block to control RTC"] -pub mod rtc; -#[doc = "ROSC"] -pub struct ROSC { +#[doc = "SPI0"] +pub mod spi0; +#[doc = "SPI1"] +pub struct SPI1 { _marker: PhantomData<*const ()>, } -unsafe impl Send for ROSC {} -impl ROSC { +unsafe impl Send for SPI1 {} +impl SPI1 { #[doc = r"Pointer to the register block"] - pub const PTR: *const rosc::RegisterBlock = 0x4006_0000 as *const _; + pub const PTR: *const spi0::RegisterBlock = 0x4004_0000 as *const _; #[doc = r"Return the pointer to the register block"] #[inline(always)] - pub const fn ptr() -> *const rosc::RegisterBlock { + pub const fn ptr() -> *const spi0::RegisterBlock { Self::PTR } #[doc = r" Steal an instance of this peripheral"] @@ -1799,31 +1447,31 @@ impl ROSC { } } } -impl Deref for ROSC { - type Target = rosc::RegisterBlock; +impl Deref for SPI1 { + type Target = spi0::RegisterBlock; #[inline(always)] fn deref(&self) -> &Self::Target { unsafe { &*Self::PTR } } } -impl core::fmt::Debug for ROSC { +impl core::fmt::Debug for SPI1 { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("ROSC").finish() + f.debug_struct("SPI1").finish() } } -#[doc = "ROSC"] -pub mod rosc; -#[doc = "control and status for on-chip voltage regulator and chip level reset subsystem"] -pub struct VREG_AND_CHIP_RESET { +#[doc = "SPI1"] +pub use self::spi0 as spi1; +#[doc = "Programmable IO block"] +pub struct PIO0 { _marker: PhantomData<*const ()>, } -unsafe impl Send for VREG_AND_CHIP_RESET {} -impl VREG_AND_CHIP_RESET { +unsafe impl Send for PIO0 {} +impl PIO0 { #[doc = r"Pointer to the register block"] - pub const PTR: *const vreg_and_chip_reset::RegisterBlock = 0x4006_4000 as *const _; + pub const PTR: *const pio0::RegisterBlock = 0x5020_0000 as *const _; #[doc = r"Return the pointer to the register block"] #[inline(always)] - pub const fn ptr() -> *const vreg_and_chip_reset::RegisterBlock { + pub const fn ptr() -> *const pio0::RegisterBlock { Self::PTR } #[doc = r" Steal an instance of this peripheral"] @@ -1845,31 +1493,31 @@ impl VREG_AND_CHIP_RESET { } } } -impl Deref for VREG_AND_CHIP_RESET { - type Target = vreg_and_chip_reset::RegisterBlock; +impl Deref for PIO0 { + type Target = pio0::RegisterBlock; #[inline(always)] fn deref(&self) -> &Self::Target { unsafe { &*Self::PTR } } } -impl core::fmt::Debug for VREG_AND_CHIP_RESET { +impl core::fmt::Debug for PIO0 { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("VREG_AND_CHIP_RESET").finish() + f.debug_struct("PIO0").finish() } } -#[doc = "control and status for on-chip voltage regulator and chip level reset subsystem"] -pub mod vreg_and_chip_reset; -#[doc = "Testbench manager. Allows the programmer to know what platform their software is running on."] -pub struct TBMAN { +#[doc = "Programmable IO block"] +pub mod pio0; +#[doc = "Programmable IO block"] +pub struct PIO1 { _marker: PhantomData<*const ()>, } -unsafe impl Send for TBMAN {} -impl TBMAN { +unsafe impl Send for PIO1 {} +impl PIO1 { #[doc = r"Pointer to the register block"] - pub const PTR: *const tbman::RegisterBlock = 0x4006_c000 as *const _; + pub const PTR: *const pio0::RegisterBlock = 0x5030_0000 as *const _; #[doc = r"Return the pointer to the register block"] #[inline(always)] - pub const fn ptr() -> *const tbman::RegisterBlock { + pub const fn ptr() -> *const pio0::RegisterBlock { Self::PTR } #[doc = r" Steal an instance of this peripheral"] @@ -1891,31 +1539,31 @@ impl TBMAN { } } } -impl Deref for TBMAN { - type Target = tbman::RegisterBlock; +impl Deref for PIO1 { + type Target = pio0::RegisterBlock; #[inline(always)] fn deref(&self) -> &Self::Target { unsafe { &*Self::PTR } } } -impl core::fmt::Debug for TBMAN { +impl core::fmt::Debug for PIO1 { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("TBMAN").finish() + f.debug_struct("PIO1").finish() } } -#[doc = "Testbench manager. Allows the programmer to know what platform their software is running on."] -pub mod tbman; -#[doc = "DMA with separate read and write masters"] -pub struct DMA { +#[doc = "Programmable IO block"] +pub use self::pio0 as pio1; +#[doc = "Register block for busfabric control signals and performance counters"] +pub struct BUSCTRL { _marker: PhantomData<*const ()>, } -unsafe impl Send for DMA {} -impl DMA { +unsafe impl Send for BUSCTRL {} +impl BUSCTRL { #[doc = r"Pointer to the register block"] - pub const PTR: *const dma::RegisterBlock = 0x5000_0000 as *const _; + pub const PTR: *const busctrl::RegisterBlock = 0x4003_0000 as *const _; #[doc = r"Return the pointer to the register block"] #[inline(always)] - pub const fn ptr() -> *const dma::RegisterBlock { + pub const fn ptr() -> *const busctrl::RegisterBlock { Self::PTR } #[doc = r" Steal an instance of this peripheral"] @@ -1937,31 +1585,31 @@ impl DMA { } } } -impl Deref for DMA { - type Target = dma::RegisterBlock; +impl Deref for BUSCTRL { + type Target = busctrl::RegisterBlock; #[inline(always)] fn deref(&self) -> &Self::Target { unsafe { &*Self::PTR } } } -impl core::fmt::Debug for DMA { +impl core::fmt::Debug for BUSCTRL { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("DMA").finish() + f.debug_struct("BUSCTRL").finish() } } -#[doc = "DMA with separate read and write masters"] -pub mod dma; -#[doc = "DPRAM layout for USB device."] -pub struct USBCTRL_DPRAM { +#[doc = "Register block for busfabric control signals and performance counters"] +pub mod busctrl; +#[doc = "Single-cycle IO block Provides core-local and inter-core hardware for the two processors, with single-cycle access."] +pub struct SIO { _marker: PhantomData<*const ()>, } -unsafe impl Send for USBCTRL_DPRAM {} -impl USBCTRL_DPRAM { +unsafe impl Send for SIO {} +impl SIO { #[doc = r"Pointer to the register block"] - pub const PTR: *const usbctrl_dpram::RegisterBlock = 0x5010_0000 as *const _; + pub const PTR: *const sio::RegisterBlock = 0xd000_0000 as *const _; #[doc = r"Return the pointer to the register block"] #[inline(always)] - pub const fn ptr() -> *const usbctrl_dpram::RegisterBlock { + pub const fn ptr() -> *const sio::RegisterBlock { Self::PTR } #[doc = r" Steal an instance of this peripheral"] @@ -1983,20 +1631,20 @@ impl USBCTRL_DPRAM { } } } -impl Deref for USBCTRL_DPRAM { - type Target = usbctrl_dpram::RegisterBlock; +impl Deref for SIO { + type Target = sio::RegisterBlock; #[inline(always)] fn deref(&self) -> &Self::Target { unsafe { &*Self::PTR } } } -impl core::fmt::Debug for USBCTRL_DPRAM { +impl core::fmt::Debug for SIO { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("USBCTRL_DPRAM").finish() + f.debug_struct("SIO").finish() } } -#[doc = "DPRAM layout for USB device."] -pub mod usbctrl_dpram; +#[doc = "Single-cycle IO block Provides core-local and inter-core hardware for the two processors, with single-cycle access."] +pub mod sio; #[doc = "USB FS/LS controller device registers"] pub struct USBCTRL_REGS { _marker: PhantomData<*const ()>, @@ -2043,17 +1691,17 @@ impl core::fmt::Debug for USBCTRL_REGS { } #[doc = "USB FS/LS controller device registers"] pub mod usbctrl_regs; -#[doc = "Programmable IO block"] -pub struct PIO0 { +#[doc = "DPRAM layout for USB device."] +pub struct USBCTRL_DPRAM { _marker: PhantomData<*const ()>, } -unsafe impl Send for PIO0 {} -impl PIO0 { +unsafe impl Send for USBCTRL_DPRAM {} +impl USBCTRL_DPRAM { #[doc = r"Pointer to the register block"] - pub const PTR: *const pio0::RegisterBlock = 0x5020_0000 as *const _; + pub const PTR: *const usbctrl_dpram::RegisterBlock = 0x5010_0000 as *const _; #[doc = r"Return the pointer to the register block"] #[inline(always)] - pub const fn ptr() -> *const pio0::RegisterBlock { + pub const fn ptr() -> *const usbctrl_dpram::RegisterBlock { Self::PTR } #[doc = r" Steal an instance of this peripheral"] @@ -2075,31 +1723,31 @@ impl PIO0 { } } } -impl Deref for PIO0 { - type Target = pio0::RegisterBlock; +impl Deref for USBCTRL_DPRAM { + type Target = usbctrl_dpram::RegisterBlock; #[inline(always)] fn deref(&self) -> &Self::Target { unsafe { &*Self::PTR } } } -impl core::fmt::Debug for PIO0 { +impl core::fmt::Debug for USBCTRL_DPRAM { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("PIO0").finish() + f.debug_struct("USBCTRL_DPRAM").finish() } } -#[doc = "Programmable IO block"] -pub mod pio0; -#[doc = "Programmable IO block"] -pub struct PIO1 { +#[doc = "DPRAM layout for USB device."] +pub mod usbctrl_dpram; +#[doc = "Testbench manager. Allows the programmer to know what platform their software is running on."] +pub struct TBMAN { _marker: PhantomData<*const ()>, } -unsafe impl Send for PIO1 {} -impl PIO1 { +unsafe impl Send for TBMAN {} +impl TBMAN { #[doc = r"Pointer to the register block"] - pub const PTR: *const pio0::RegisterBlock = 0x5030_0000 as *const _; + pub const PTR: *const tbman::RegisterBlock = 0x4006_c000 as *const _; #[doc = r"Return the pointer to the register block"] #[inline(always)] - pub const fn ptr() -> *const pio0::RegisterBlock { + pub const fn ptr() -> *const tbman::RegisterBlock { Self::PTR } #[doc = r" Steal an instance of this peripheral"] @@ -2121,32 +1769,31 @@ impl PIO1 { } } } -impl Deref for PIO1 { - type Target = pio0::RegisterBlock; +impl Deref for TBMAN { + type Target = tbman::RegisterBlock; #[inline(always)] fn deref(&self) -> &Self::Target { unsafe { &*Self::PTR } } } -impl core::fmt::Debug for PIO1 { +impl core::fmt::Debug for TBMAN { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("PIO1").finish() + f.debug_struct("TBMAN").finish() } } -#[doc = "Programmable IO block"] -pub use self::pio0 as pio1; -#[doc = "Single-cycle IO block - Provides core-local and inter-core hardware for the two processors, with single-cycle access."] -pub struct SIO { +#[doc = "Testbench manager. Allows the programmer to know what platform their software is running on."] +pub mod tbman; +#[doc = "control and status for on-chip voltage regulator and chip level reset subsystem"] +pub struct VREG_AND_CHIP_RESET { _marker: PhantomData<*const ()>, } -unsafe impl Send for SIO {} -impl SIO { +unsafe impl Send for VREG_AND_CHIP_RESET {} +impl VREG_AND_CHIP_RESET { #[doc = r"Pointer to the register block"] - pub const PTR: *const sio::RegisterBlock = 0xd000_0000 as *const _; + pub const PTR: *const vreg_and_chip_reset::RegisterBlock = 0x4006_4000 as *const _; #[doc = r"Return the pointer to the register block"] #[inline(always)] - pub const fn ptr() -> *const sio::RegisterBlock { + pub const fn ptr() -> *const vreg_and_chip_reset::RegisterBlock { Self::PTR } #[doc = r" Steal an instance of this peripheral"] @@ -2168,32 +1815,31 @@ impl SIO { } } } -impl Deref for SIO { - type Target = sio::RegisterBlock; +impl Deref for VREG_AND_CHIP_RESET { + type Target = vreg_and_chip_reset::RegisterBlock; #[inline(always)] fn deref(&self) -> &Self::Target { unsafe { &*Self::PTR } } } -impl core::fmt::Debug for SIO { +impl core::fmt::Debug for VREG_AND_CHIP_RESET { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SIO").finish() + f.debug_struct("VREG_AND_CHIP_RESET").finish() } } -#[doc = "Single-cycle IO block - Provides core-local and inter-core hardware for the two processors, with single-cycle access."] -pub mod sio; -#[doc = "PPB"] -pub struct PPB { +#[doc = "control and status for on-chip voltage regulator and chip level reset subsystem"] +pub mod vreg_and_chip_reset; +#[doc = "Register block to control RTC"] +pub struct RTC { _marker: PhantomData<*const ()>, } -unsafe impl Send for PPB {} -impl PPB { +unsafe impl Send for RTC {} +impl RTC { #[doc = r"Pointer to the register block"] - pub const PTR: *const ppb::RegisterBlock = 0xe000_0000 as *const _; + pub const PTR: *const rtc::RegisterBlock = 0x4005_c000 as *const _; #[doc = r"Return the pointer to the register block"] #[inline(always)] - pub const fn ptr() -> *const ppb::RegisterBlock { + pub const fn ptr() -> *const rtc::RegisterBlock { Self::PTR } #[doc = r" Steal an instance of this peripheral"] @@ -2215,20 +1861,20 @@ impl PPB { } } } -impl Deref for PPB { - type Target = ppb::RegisterBlock; +impl Deref for RTC { + type Target = rtc::RegisterBlock; #[inline(always)] fn deref(&self) -> &Self::Target { unsafe { &*Self::PTR } } } -impl core::fmt::Debug for PPB { +impl core::fmt::Debug for RTC { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("PPB").finish() + f.debug_struct("RTC").finish() } } -#[doc = "PPB"] -pub mod ppb; +#[doc = "Register block to control RTC"] +pub mod rtc; #[no_mangle] static mut DEVICE_PERIPHERALS: bool = false; #[doc = r" All the peripherals."] @@ -2280,6 +1926,8 @@ pub struct Peripherals { pub SPI0: SPI0, #[doc = "SPI1"] pub SPI1: SPI1, + #[doc = "SSI"] + pub SSI: SSI, #[doc = "SYSCFG"] pub SYSCFG: SYSCFG, #[doc = "SYSINFO"] @@ -2302,8 +1950,6 @@ pub struct Peripherals { pub WATCHDOG: WATCHDOG, #[doc = "XIP_CTRL"] pub XIP_CTRL: XIP_CTRL, - #[doc = "XIP_SSI"] - pub XIP_SSI: XIP_SSI, #[doc = "XOSC"] pub XOSC: XOSC, } @@ -2328,37 +1974,40 @@ impl Peripherals { pub unsafe fn steal() -> Self { DEVICE_PERIPHERALS = true; Peripherals { - XIP_CTRL: XIP_CTRL { + RESETS: RESETS { _marker: PhantomData, }, - XIP_SSI: XIP_SSI { + PSM: PSM { _marker: PhantomData, }, - SYSINFO: SYSINFO { + CLOCKS: CLOCKS { _marker: PhantomData, }, - SYSCFG: SYSCFG { + PADS_BANK0: PADS_BANK0 { _marker: PhantomData, }, - CLOCKS: CLOCKS { + PADS_QSPI: PADS_QSPI { _marker: PhantomData, }, - RESETS: RESETS { + IO_QSPI: IO_QSPI { _marker: PhantomData, }, - PSM: PSM { + IO_BANK0: IO_BANK0 { _marker: PhantomData, }, - IO_BANK0: IO_BANK0 { + SYSINFO: SYSINFO { _marker: PhantomData, }, - IO_QSPI: IO_QSPI { + PPB: PPB { _marker: PhantomData, }, - PADS_BANK0: PADS_BANK0 { + SSI: SSI { _marker: PhantomData, }, - PADS_QSPI: PADS_QSPI { + XIP_CTRL: XIP_CTRL { + _marker: PhantomData, + }, + SYSCFG: SYSCFG { _marker: PhantomData, }, XOSC: XOSC { @@ -2370,70 +2019,67 @@ impl Peripherals { PLL_USB: PLL_USB { _marker: PhantomData, }, - BUSCTRL: BUSCTRL { - _marker: PhantomData, - }, UART0: UART0 { _marker: PhantomData, }, UART1: UART1 { _marker: PhantomData, }, - SPI0: SPI0 { + ROSC: ROSC { _marker: PhantomData, }, - SPI1: SPI1 { + WATCHDOG: WATCHDOG { _marker: PhantomData, }, - I2C0: I2C0 { + DMA: DMA { _marker: PhantomData, }, - I2C1: I2C1 { + TIMER: TIMER { _marker: PhantomData, }, - ADC: ADC { + PWM: PWM { _marker: PhantomData, }, - PWM: PWM { + ADC: ADC { _marker: PhantomData, }, - TIMER: TIMER { + I2C0: I2C0 { _marker: PhantomData, }, - WATCHDOG: WATCHDOG { + I2C1: I2C1 { _marker: PhantomData, }, - RTC: RTC { + SPI0: SPI0 { _marker: PhantomData, }, - ROSC: ROSC { + SPI1: SPI1 { _marker: PhantomData, }, - VREG_AND_CHIP_RESET: VREG_AND_CHIP_RESET { + PIO0: PIO0 { _marker: PhantomData, }, - TBMAN: TBMAN { + PIO1: PIO1 { _marker: PhantomData, }, - DMA: DMA { + BUSCTRL: BUSCTRL { _marker: PhantomData, }, - USBCTRL_DPRAM: USBCTRL_DPRAM { + SIO: SIO { _marker: PhantomData, }, USBCTRL_REGS: USBCTRL_REGS { _marker: PhantomData, }, - PIO0: PIO0 { + USBCTRL_DPRAM: USBCTRL_DPRAM { _marker: PhantomData, }, - PIO1: PIO1 { + TBMAN: TBMAN { _marker: PhantomData, }, - SIO: SIO { + VREG_AND_CHIP_RESET: VREG_AND_CHIP_RESET { _marker: PhantomData, }, - PPB: PPB { + RTC: RTC { _marker: PhantomData, }, } diff --git a/src/pio0.rs b/src/pio0.rs index d13478492..b0eb49dea 100644 --- a/src/pio0.rs +++ b/src/pio0.rs @@ -61,9 +61,7 @@ impl RegisterBlock { pub fn rxf_iter(&self) -> impl Iterator { self.rxf.iter() } - #[doc = "0x30 - State machine IRQ flags register. Write 1 to clear. There are 8 state machine IRQ flags, which can be set, cleared, and waited on by the state machines. There's no fixed association between flags and state machines -- any state machine can use any flag. - - Any of the 8 flags can be used for timing synchronisation between state machines, using IRQ and WAIT instructions. The lower four of these flags are also routed out to system-level interrupt requests, alongside FIFO status interrupts -- see e.g. IRQ0_INTE."] + #[doc = "0x30 - State machine IRQ flags register. Write 1 to clear. There are 8 state machine IRQ flags, which can be set, cleared, and waited on by the state machines. There's no fixed association between flags and state machines -- any state machine can use any flag. Any of the 8 flags can be used for timing synchronisation between state machines, using IRQ and WAIT instructions. The lower four of these flags are also routed out to system-level interrupt requests, alongside FIFO status interrupts -- see e.g. IRQ0_INTE."] #[inline(always)] pub const fn irq(&self) -> &IRQ { &self.irq @@ -73,10 +71,7 @@ impl RegisterBlock { pub const fn irq_force(&self) -> &IRQ_FORCE { &self.irq_force } - #[doc = "0x38 - There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic from metastabilities. This increases input delay, and for fast synchronous IO (e.g. SPI) these synchronizers may need to be bypassed. Each bit in this register corresponds to one GPIO. - 0 -> input is synchronized (default) - 1 -> synchronizer is bypassed - If in doubt, leave this register as all zeroes."] + #[doc = "0x38 - There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic from metastabilities. This increases input delay, and for fast synchronous IO (e.g. SPI) these synchronizers may need to be bypassed. Each bit in this register corresponds to one GPIO. 0 -> input is synchronized (default) 1 -> synchronizer is bypassed If in doubt, leave this register as all zeroes."] #[inline(always)] pub const fn input_sync_bypass(&self) -> &INPUT_SYNC_BYPASS { &self.input_sync_bypass @@ -91,8 +86,7 @@ impl RegisterBlock { pub const fn dbg_padoe(&self) -> &DBG_PADOE { &self.dbg_padoe } - #[doc = "0x44 - The PIO hardware has some free parameters that may vary between chip products. - These should be provided in the chip datasheet, but are also exposed here."] + #[doc = "0x44 - The PIO hardware has some free parameters that may vary between chip products. These should be provided in the chip datasheet, but are also exposed here."] #[inline(always)] pub const fn dbg_cfginfo(&self) -> &DBG_CFGINFO { &self.dbg_cfginfo @@ -145,9 +139,9 @@ module"] pub type CTRL = crate::Reg; #[doc = "PIO control register"] pub mod ctrl; -#[doc = "FSTAT (r) register accessor: FIFO status register +#[doc = "FSTAT (rw) register accessor: FIFO status register -You can [`read`](crate::generic::Reg::read) this register and get [`fstat::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`fstat::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fstat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@fstat`] module"] @@ -163,102 +157,90 @@ module"] pub type FDEBUG = crate::Reg; #[doc = "FIFO debug register"] pub mod fdebug; -#[doc = "FLEVEL (r) register accessor: FIFO levels +#[doc = "FLEVEL (rw) register accessor: FIFO levels -You can [`read`](crate::generic::Reg::read) this register and get [`flevel::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`flevel::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`flevel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@flevel`] module"] pub type FLEVEL = crate::Reg; #[doc = "FIFO levels"] pub mod flevel; -#[doc = "TXF (w) register accessor: Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO. +#[doc = "TXF (rw) register accessor: Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO. -You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txf::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`txf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@txf`] module"] pub type TXF = crate::Reg; #[doc = "Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO."] pub mod txf; -#[doc = "RXF (r) register accessor: Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined. +#[doc = "RXF (rw) register accessor: Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined. -You can [`read`](crate::generic::Reg::read) this register and get [`rxf::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`rxf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@rxf`] module"] pub type RXF = crate::Reg; #[doc = "Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined."] pub mod rxf; -#[doc = "IRQ (rw) register accessor: State machine IRQ flags register. Write 1 to clear. There are 8 state machine IRQ flags, which can be set, cleared, and waited on by the state machines. There's no fixed association between flags and state machines -- any state machine can use any flag. - - Any of the 8 flags can be used for timing synchronisation between state machines, using IRQ and WAIT instructions. The lower four of these flags are also routed out to system-level interrupt requests, alongside FIFO status interrupts -- see e.g. IRQ0_INTE. +#[doc = "IRQ (rw) register accessor: State machine IRQ flags register. Write 1 to clear. There are 8 state machine IRQ flags, which can be set, cleared, and waited on by the state machines. There's no fixed association between flags and state machines -- any state machine can use any flag. Any of the 8 flags can be used for timing synchronisation between state machines, using IRQ and WAIT instructions. The lower four of these flags are also routed out to system-level interrupt requests, alongside FIFO status interrupts -- see e.g. IRQ0_INTE. You can [`read`](crate::generic::Reg::read) this register and get [`irq::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@irq`] module"] pub type IRQ = crate::Reg; -#[doc = "State machine IRQ flags register. Write 1 to clear. There are 8 state machine IRQ flags, which can be set, cleared, and waited on by the state machines. There's no fixed association between flags and state machines -- any state machine can use any flag. - - Any of the 8 flags can be used for timing synchronisation between state machines, using IRQ and WAIT instructions. The lower four of these flags are also routed out to system-level interrupt requests, alongside FIFO status interrupts -- see e.g. IRQ0_INTE."] +#[doc = "State machine IRQ flags register. Write 1 to clear. There are 8 state machine IRQ flags, which can be set, cleared, and waited on by the state machines. There's no fixed association between flags and state machines -- any state machine can use any flag. Any of the 8 flags can be used for timing synchronisation between state machines, using IRQ and WAIT instructions. The lower four of these flags are also routed out to system-level interrupt requests, alongside FIFO status interrupts -- see e.g. IRQ0_INTE."] pub mod irq; -#[doc = "IRQ_FORCE (w) register accessor: Writing a 1 to each of these bits will forcibly assert the corresponding IRQ. Note this is different to the INTF register: writing here affects PIO internal state. INTF just asserts the processor-facing IRQ signal for testing ISRs, and is not visible to the state machines. +#[doc = "IRQ_FORCE (rw) register accessor: Writing a 1 to each of these bits will forcibly assert the corresponding IRQ. Note this is different to the INTF register: writing here affects PIO internal state. INTF just asserts the processor-facing IRQ signal for testing ISRs, and is not visible to the state machines. -You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_force::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`irq_force::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_force::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@irq_force`] module"] pub type IRQ_FORCE = crate::Reg; #[doc = "Writing a 1 to each of these bits will forcibly assert the corresponding IRQ. Note this is different to the INTF register: writing here affects PIO internal state. INTF just asserts the processor-facing IRQ signal for testing ISRs, and is not visible to the state machines."] pub mod irq_force; -#[doc = "INPUT_SYNC_BYPASS (rw) register accessor: There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic from metastabilities. This increases input delay, and for fast synchronous IO (e.g. SPI) these synchronizers may need to be bypassed. Each bit in this register corresponds to one GPIO. - 0 -> input is synchronized (default) - 1 -> synchronizer is bypassed - If in doubt, leave this register as all zeroes. +#[doc = "INPUT_SYNC_BYPASS (rw) register accessor: There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic from metastabilities. This increases input delay, and for fast synchronous IO (e.g. SPI) these synchronizers may need to be bypassed. Each bit in this register corresponds to one GPIO. 0 -> input is synchronized (default) 1 -> synchronizer is bypassed If in doubt, leave this register as all zeroes. You can [`read`](crate::generic::Reg::read) this register and get [`input_sync_bypass::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`input_sync_bypass::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@input_sync_bypass`] module"] pub type INPUT_SYNC_BYPASS = crate::Reg; -#[doc = "There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic from metastabilities. This increases input delay, and for fast synchronous IO (e.g. SPI) these synchronizers may need to be bypassed. Each bit in this register corresponds to one GPIO. - 0 -> input is synchronized (default) - 1 -> synchronizer is bypassed - If in doubt, leave this register as all zeroes."] +#[doc = "There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic from metastabilities. This increases input delay, and for fast synchronous IO (e.g. SPI) these synchronizers may need to be bypassed. Each bit in this register corresponds to one GPIO. 0 -> input is synchronized (default) 1 -> synchronizer is bypassed If in doubt, leave this register as all zeroes."] pub mod input_sync_bypass; -#[doc = "DBG_PADOUT (r) register accessor: Read to sample the pad output values PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0. +#[doc = "DBG_PADOUT (rw) register accessor: Read to sample the pad output values PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0. -You can [`read`](crate::generic::Reg::read) this register and get [`dbg_padout::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`dbg_padout::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dbg_padout::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@dbg_padout`] module"] pub type DBG_PADOUT = crate::Reg; #[doc = "Read to sample the pad output values PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0."] pub mod dbg_padout; -#[doc = "DBG_PADOE (r) register accessor: Read to sample the pad output enables (direction) PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0. +#[doc = "DBG_PADOE (rw) register accessor: Read to sample the pad output enables (direction) PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0. -You can [`read`](crate::generic::Reg::read) this register and get [`dbg_padoe::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`dbg_padoe::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dbg_padoe::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@dbg_padoe`] module"] pub type DBG_PADOE = crate::Reg; #[doc = "Read to sample the pad output enables (direction) PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0."] pub mod dbg_padoe; -#[doc = "DBG_CFGINFO (r) register accessor: The PIO hardware has some free parameters that may vary between chip products. - These should be provided in the chip datasheet, but are also exposed here. +#[doc = "DBG_CFGINFO (rw) register accessor: The PIO hardware has some free parameters that may vary between chip products. These should be provided in the chip datasheet, but are also exposed here. -You can [`read`](crate::generic::Reg::read) this register and get [`dbg_cfginfo::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`dbg_cfginfo::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dbg_cfginfo::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@dbg_cfginfo`] module"] pub type DBG_CFGINFO = crate::Reg; -#[doc = "The PIO hardware has some free parameters that may vary between chip products. - These should be provided in the chip datasheet, but are also exposed here."] +#[doc = "The PIO hardware has some free parameters that may vary between chip products. These should be provided in the chip datasheet, but are also exposed here."] pub mod dbg_cfginfo; -#[doc = "INSTR_MEM (w) register accessor: Write-only access to instruction memory location %s +#[doc = "INSTR_MEM (rw) register accessor: Write-only access to instruction memory location %s -You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`instr_mem::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`instr_mem::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`instr_mem::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@instr_mem`] module"] @@ -270,9 +252,9 @@ pub use self::sm::SM; #[doc = r"Cluster"] #[doc = "Cluster SM%s, containing SM*_CLKDIV, SM*_EXECCTRL, SM*_SHIFTCTRL, SM*_ADDR, SM*_INSTR, SM*_PINCTRL"] pub mod sm; -#[doc = "INTR (r) register accessor: Raw Interrupts +#[doc = "INTR (rw) register accessor: Raw Interrupts -You can [`read`](crate::generic::Reg::read) this register and get [`intr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`intr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@intr`] module"] diff --git a/src/pio0/ctrl.rs b/src/pio0/ctrl.rs index a3638640d..7bee6a350 100644 --- a/src/pio0/ctrl.rs +++ b/src/pio0/ctrl.rs @@ -6,29 +6,9 @@ pub type W = crate::W; pub type SM_ENABLE_R = crate::FieldReader; #[doc = "Field `SM_ENABLE` writer - Enable/disable each of the four state machines by writing 1/0 to each of these four bits. When disabled, a state machine will cease executing instructions, except those written directly to SMx_INSTR by the system. Multiple bits can be set/cleared at once to run/halt multiple state machines simultaneously."] pub type SM_ENABLE_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `SM_RESTART` reader - Write 1 to instantly clear internal SM state which may be otherwise difficult to access and will affect future execution. - - Specifically, the following are cleared: input and output shift counters; the contents of the input shift register; the delay counter; the waiting-on-IRQ state; any stalled instruction written to SMx_INSTR or run by OUT/MOV EXEC; any pin write left asserted due to OUT_STICKY. - - The program counter, the contents of the output shift register and the X/Y scratch registers are not affected."] -pub type SM_RESTART_R = crate::FieldReader; -#[doc = "Field `SM_RESTART` writer - Write 1 to instantly clear internal SM state which may be otherwise difficult to access and will affect future execution. - - Specifically, the following are cleared: input and output shift counters; the contents of the input shift register; the delay counter; the waiting-on-IRQ state; any stalled instruction written to SMx_INSTR or run by OUT/MOV EXEC; any pin write left asserted due to OUT_STICKY. - - The program counter, the contents of the output shift register and the X/Y scratch registers are not affected."] +#[doc = "Field `SM_RESTART` writer - Write 1 to instantly clear internal SM state which may be otherwise difficult to access and will affect future execution. Specifically, the following are cleared: input and output shift counters; the contents of the input shift register; the delay counter; the waiting-on-IRQ state; any stalled instruction written to SMx_INSTR or run by OUT/MOV EXEC; any pin write left asserted due to OUT_STICKY. The program counter, the contents of the output shift register and the X/Y scratch registers are not affected."] pub type SM_RESTART_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `CLKDIV_RESTART` reader - Restart a state machine's clock divider from an initial phase of 0. Clock dividers are free-running, so once started, their output (including fractional jitter) is completely determined by the integer/fractional divisor configured in SMx_CLKDIV. This means that, if multiple clock dividers with the same divisor are restarted simultaneously, by writing multiple 1 bits to this field, the execution clocks of those state machines will run in precise lockstep. - - Note that setting/clearing SM_ENABLE does not stop the clock divider from running, so once multiple state machines' clocks are synchronised, it is safe to disable/reenable a state machine, whilst keeping the clock dividers in sync. - - Note also that CLKDIV_RESTART can be written to whilst the state machine is running, and this is useful to resynchronise clock dividers after the divisors (SMx_CLKDIV) have been changed on-the-fly."] -pub type CLKDIV_RESTART_R = crate::FieldReader; -#[doc = "Field `CLKDIV_RESTART` writer - Restart a state machine's clock divider from an initial phase of 0. Clock dividers are free-running, so once started, their output (including fractional jitter) is completely determined by the integer/fractional divisor configured in SMx_CLKDIV. This means that, if multiple clock dividers with the same divisor are restarted simultaneously, by writing multiple 1 bits to this field, the execution clocks of those state machines will run in precise lockstep. - - Note that setting/clearing SM_ENABLE does not stop the clock divider from running, so once multiple state machines' clocks are synchronised, it is safe to disable/reenable a state machine, whilst keeping the clock dividers in sync. - - Note also that CLKDIV_RESTART can be written to whilst the state machine is running, and this is useful to resynchronise clock dividers after the divisors (SMx_CLKDIV) have been changed on-the-fly."] +#[doc = "Field `CLKDIV_RESTART` writer - Restart a state machine's clock divider from an initial phase of 0. Clock dividers are free-running, so once started, their output (including fractional jitter) is completely determined by the integer/fractional divisor configured in SMx_CLKDIV. This means that, if multiple clock dividers with the same divisor are restarted simultaneously, by writing multiple 1 bits to this field, the execution clocks of those state machines will run in precise lockstep. Note that setting/clearing SM_ENABLE does not stop the clock divider from running, so once multiple state machines' clocks are synchronised, it is safe to disable/reenable a state machine, whilst keeping the clock dividers in sync. Note also that CLKDIV_RESTART can be written to whilst the state machine is running, and this is useful to resynchronise clock dividers after the divisors (SMx_CLKDIV) have been changed on-the-fly."] pub type CLKDIV_RESTART_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; impl R { #[doc = "Bits 0:3 - Enable/disable each of the four state machines by writing 1/0 to each of these four bits. When disabled, a state machine will cease executing instructions, except those written directly to SMx_INSTR by the system. Multiple bits can be set/cleared at once to run/halt multiple state machines simultaneously."] @@ -36,24 +16,6 @@ impl R { pub fn sm_enable(&self) -> SM_ENABLE_R { SM_ENABLE_R::new((self.bits & 0x0f) as u8) } - #[doc = "Bits 4:7 - Write 1 to instantly clear internal SM state which may be otherwise difficult to access and will affect future execution. - - Specifically, the following are cleared: input and output shift counters; the contents of the input shift register; the delay counter; the waiting-on-IRQ state; any stalled instruction written to SMx_INSTR or run by OUT/MOV EXEC; any pin write left asserted due to OUT_STICKY. - - The program counter, the contents of the output shift register and the X/Y scratch registers are not affected."] - #[inline(always)] - pub fn sm_restart(&self) -> SM_RESTART_R { - SM_RESTART_R::new(((self.bits >> 4) & 0x0f) as u8) - } - #[doc = "Bits 8:11 - Restart a state machine's clock divider from an initial phase of 0. Clock dividers are free-running, so once started, their output (including fractional jitter) is completely determined by the integer/fractional divisor configured in SMx_CLKDIV. This means that, if multiple clock dividers with the same divisor are restarted simultaneously, by writing multiple 1 bits to this field, the execution clocks of those state machines will run in precise lockstep. - - Note that setting/clearing SM_ENABLE does not stop the clock divider from running, so once multiple state machines' clocks are synchronised, it is safe to disable/reenable a state machine, whilst keeping the clock dividers in sync. - - Note also that CLKDIV_RESTART can be written to whilst the state machine is running, and this is useful to resynchronise clock dividers after the divisors (SMx_CLKDIV) have been changed on-the-fly."] - #[inline(always)] - pub fn clkdiv_restart(&self) -> CLKDIV_RESTART_R { - CLKDIV_RESTART_R::new(((self.bits >> 8) & 0x0f) as u8) - } } impl W { #[doc = "Bits 0:3 - Enable/disable each of the four state machines by writing 1/0 to each of these four bits. When disabled, a state machine will cease executing instructions, except those written directly to SMx_INSTR by the system. Multiple bits can be set/cleared at once to run/halt multiple state machines simultaneously."] @@ -62,21 +24,13 @@ impl W { pub fn sm_enable(&mut self) -> SM_ENABLE_W { SM_ENABLE_W::new(self, 0) } - #[doc = "Bits 4:7 - Write 1 to instantly clear internal SM state which may be otherwise difficult to access and will affect future execution. - - Specifically, the following are cleared: input and output shift counters; the contents of the input shift register; the delay counter; the waiting-on-IRQ state; any stalled instruction written to SMx_INSTR or run by OUT/MOV EXEC; any pin write left asserted due to OUT_STICKY. - - The program counter, the contents of the output shift register and the X/Y scratch registers are not affected."] + #[doc = "Bits 4:7 - Write 1 to instantly clear internal SM state which may be otherwise difficult to access and will affect future execution. Specifically, the following are cleared: input and output shift counters; the contents of the input shift register; the delay counter; the waiting-on-IRQ state; any stalled instruction written to SMx_INSTR or run by OUT/MOV EXEC; any pin write left asserted due to OUT_STICKY. The program counter, the contents of the output shift register and the X/Y scratch registers are not affected."] #[inline(always)] #[must_use] pub fn sm_restart(&mut self) -> SM_RESTART_W { SM_RESTART_W::new(self, 4) } - #[doc = "Bits 8:11 - Restart a state machine's clock divider from an initial phase of 0. Clock dividers are free-running, so once started, their output (including fractional jitter) is completely determined by the integer/fractional divisor configured in SMx_CLKDIV. This means that, if multiple clock dividers with the same divisor are restarted simultaneously, by writing multiple 1 bits to this field, the execution clocks of those state machines will run in precise lockstep. - - Note that setting/clearing SM_ENABLE does not stop the clock divider from running, so once multiple state machines' clocks are synchronised, it is safe to disable/reenable a state machine, whilst keeping the clock dividers in sync. - - Note also that CLKDIV_RESTART can be written to whilst the state machine is running, and this is useful to resynchronise clock dividers after the divisors (SMx_CLKDIV) have been changed on-the-fly."] + #[doc = "Bits 8:11 - Restart a state machine's clock divider from an initial phase of 0. Clock dividers are free-running, so once started, their output (including fractional jitter) is completely determined by the integer/fractional divisor configured in SMx_CLKDIV. This means that, if multiple clock dividers with the same divisor are restarted simultaneously, by writing multiple 1 bits to this field, the execution clocks of those state machines will run in precise lockstep. Note that setting/clearing SM_ENABLE does not stop the clock divider from running, so once multiple state machines' clocks are synchronised, it is safe to disable/reenable a state machine, whilst keeping the clock dividers in sync. Note also that CLKDIV_RESTART can be written to whilst the state machine is running, and this is useful to resynchronise clock dividers after the divisors (SMx_CLKDIV) have been changed on-the-fly."] #[inline(always)] #[must_use] pub fn clkdiv_restart(&mut self) -> CLKDIV_RESTART_W { diff --git a/src/pio0/dbg_cfginfo.rs b/src/pio0/dbg_cfginfo.rs index cb8479c69..656a05b47 100644 --- a/src/pio0/dbg_cfginfo.rs +++ b/src/pio0/dbg_cfginfo.rs @@ -1,17 +1,15 @@ #[doc = "Register `DBG_CFGINFO` reader"] pub type R = crate::R; -#[doc = "Field `FIFO_DEPTH` reader - The depth of the state machine TX/RX FIFOs, measured in words. - Joining fifos via SHIFTCTRL_FJOIN gives one FIFO with double - this depth."] +#[doc = "Register `DBG_CFGINFO` writer"] +pub type W = crate::W; +#[doc = "Field `FIFO_DEPTH` reader - The depth of the state machine TX/RX FIFOs, measured in words. Joining fifos via SHIFTCTRL_FJOIN gives one FIFO with double this depth."] pub type FIFO_DEPTH_R = crate::FieldReader; #[doc = "Field `SM_COUNT` reader - The number of state machines this PIO instance is equipped with."] pub type SM_COUNT_R = crate::FieldReader; #[doc = "Field `IMEM_SIZE` reader - The size of the instruction memory, measured in units of one instruction"] pub type IMEM_SIZE_R = crate::FieldReader; impl R { - #[doc = "Bits 0:5 - The depth of the state machine TX/RX FIFOs, measured in words. - Joining fifos via SHIFTCTRL_FJOIN gives one FIFO with double - this depth."] + #[doc = "Bits 0:5 - The depth of the state machine TX/RX FIFOs, measured in words. Joining fifos via SHIFTCTRL_FJOIN gives one FIFO with double this depth."] #[inline(always)] pub fn fifo_depth(&self) -> FIFO_DEPTH_R { FIFO_DEPTH_R::new((self.bits & 0x3f) as u8) @@ -27,16 +25,22 @@ impl R { IMEM_SIZE_R::new(((self.bits >> 16) & 0x3f) as u8) } } -#[doc = "The PIO hardware has some free parameters that may vary between chip products. - These should be provided in the chip datasheet, but are also exposed here. +impl W {} +#[doc = "The PIO hardware has some free parameters that may vary between chip products. These should be provided in the chip datasheet, but are also exposed here. -You can [`read`](crate::generic::Reg::read) this register and get [`dbg_cfginfo::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`dbg_cfginfo::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dbg_cfginfo::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DBG_CFGINFO_SPEC; impl crate::RegisterSpec for DBG_CFGINFO_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`dbg_cfginfo::R`](R) reader structure"] impl crate::Readable for DBG_CFGINFO_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dbg_cfginfo::W`](W) writer structure"] +impl crate::Writable for DBG_CFGINFO_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets DBG_CFGINFO to value 0"] impl crate::Resettable for DBG_CFGINFO_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/pio0/dbg_padoe.rs b/src/pio0/dbg_padoe.rs index 259791d8c..1fec97fe6 100644 --- a/src/pio0/dbg_padoe.rs +++ b/src/pio0/dbg_padoe.rs @@ -1,24 +1,32 @@ #[doc = "Register `DBG_PADOE` reader"] pub type R = crate::R; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) - } -} -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +#[doc = "Register `DBG_PADOE` writer"] +pub type W = crate::W; +#[doc = "Field `DBG_PADOE` reader - "] +pub type DBG_PADOE_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn dbg_padoe(&self) -> DBG_PADOE_R { + DBG_PADOE_R::new(self.bits) } } +impl W {} #[doc = "Read to sample the pad output enables (direction) PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0. -You can [`read`](crate::generic::Reg::read) this register and get [`dbg_padoe::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`dbg_padoe::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dbg_padoe::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DBG_PADOE_SPEC; impl crate::RegisterSpec for DBG_PADOE_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`dbg_padoe::R`](R) reader structure"] impl crate::Readable for DBG_PADOE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dbg_padoe::W`](W) writer structure"] +impl crate::Writable for DBG_PADOE_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets DBG_PADOE to value 0"] impl crate::Resettable for DBG_PADOE_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/pio0/dbg_padout.rs b/src/pio0/dbg_padout.rs index 793c02697..23fe95358 100644 --- a/src/pio0/dbg_padout.rs +++ b/src/pio0/dbg_padout.rs @@ -1,24 +1,32 @@ #[doc = "Register `DBG_PADOUT` reader"] pub type R = crate::R; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) - } -} -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +#[doc = "Register `DBG_PADOUT` writer"] +pub type W = crate::W; +#[doc = "Field `DBG_PADOUT` reader - "] +pub type DBG_PADOUT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn dbg_padout(&self) -> DBG_PADOUT_R { + DBG_PADOUT_R::new(self.bits) } } +impl W {} #[doc = "Read to sample the pad output values PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0. -You can [`read`](crate::generic::Reg::read) this register and get [`dbg_padout::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`dbg_padout::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dbg_padout::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DBG_PADOUT_SPEC; impl crate::RegisterSpec for DBG_PADOUT_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`dbg_padout::R`](R) reader structure"] impl crate::Readable for DBG_PADOUT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dbg_padout::W`](W) writer structure"] +impl crate::Writable for DBG_PADOUT_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets DBG_PADOUT to value 0"] impl crate::Resettable for DBG_PADOUT_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/pio0/flevel.rs b/src/pio0/flevel.rs index baf39f5ec..42c9e3232 100644 --- a/src/pio0/flevel.rs +++ b/src/pio0/flevel.rs @@ -1,5 +1,7 @@ #[doc = "Register `FLEVEL` reader"] pub type R = crate::R; +#[doc = "Register `FLEVEL` writer"] +pub type W = crate::W; #[doc = "Field `TX0` reader - "] pub type TX0_R = crate::FieldReader; #[doc = "Field `RX0` reader - "] @@ -58,15 +60,22 @@ impl R { RX3_R::new(((self.bits >> 28) & 0x0f) as u8) } } +impl W {} #[doc = "FIFO levels -You can [`read`](crate::generic::Reg::read) this register and get [`flevel::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`flevel::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`flevel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FLEVEL_SPEC; impl crate::RegisterSpec for FLEVEL_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`flevel::R`](R) reader structure"] impl crate::Readable for FLEVEL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`flevel::W`](W) writer structure"] +impl crate::Writable for FLEVEL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets FLEVEL to value 0"] impl crate::Resettable for FLEVEL_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/pio0/fstat.rs b/src/pio0/fstat.rs index 8c22f835a..d96a99e71 100644 --- a/src/pio0/fstat.rs +++ b/src/pio0/fstat.rs @@ -1,5 +1,7 @@ #[doc = "Register `FSTAT` reader"] pub type R = crate::R; +#[doc = "Register `FSTAT` writer"] +pub type W = crate::W; #[doc = "Field `RXFULL` reader - State machine RX FIFO is full"] pub type RXFULL_R = crate::FieldReader; #[doc = "Field `RXEMPTY` reader - State machine RX FIFO is empty"] @@ -30,15 +32,22 @@ impl R { TXEMPTY_R::new(((self.bits >> 24) & 0x0f) as u8) } } +impl W {} #[doc = "FIFO status register -You can [`read`](crate::generic::Reg::read) this register and get [`fstat::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`fstat::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fstat::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FSTAT_SPEC; impl crate::RegisterSpec for FSTAT_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`fstat::R`](R) reader structure"] impl crate::Readable for FSTAT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fstat::W`](W) writer structure"] +impl crate::Writable for FSTAT_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets FSTAT to value 0x0f00_0f00"] impl crate::Resettable for FSTAT_SPEC { const RESET_VALUE: u32 = 0x0f00_0f00; diff --git a/src/pio0/input_sync_bypass.rs b/src/pio0/input_sync_bypass.rs index 0b355db58..a0813f26d 100644 --- a/src/pio0/input_sync_bypass.rs +++ b/src/pio0/input_sync_bypass.rs @@ -2,21 +2,26 @@ pub type R = crate::R; #[doc = "Register `INPUT_SYNC_BYPASS` writer"] pub type W = crate::W; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) +#[doc = "Field `INPUT_SYNC_BYPASS` reader - "] +pub type INPUT_SYNC_BYPASS_R = crate::FieldReader; +#[doc = "Field `INPUT_SYNC_BYPASS` writer - "] +pub type INPUT_SYNC_BYPASS_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn input_sync_bypass(&self) -> INPUT_SYNC_BYPASS_R { + INPUT_SYNC_BYPASS_R::new(self.bits) } } -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn input_sync_bypass(&mut self) -> INPUT_SYNC_BYPASS_W { + INPUT_SYNC_BYPASS_W::new(self, 0) } } -impl W {} -#[doc = "There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic from metastabilities. This increases input delay, and for fast synchronous IO (e.g. SPI) these synchronizers may need to be bypassed. Each bit in this register corresponds to one GPIO. - 0 -> input is synchronized (default) - 1 -> synchronizer is bypassed - If in doubt, leave this register as all zeroes. +#[doc = "There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic from metastabilities. This increases input delay, and for fast synchronous IO (e.g. SPI) these synchronizers may need to be bypassed. Each bit in this register corresponds to one GPIO. 0 -> input is synchronized (default) 1 -> synchronizer is bypassed If in doubt, leave this register as all zeroes. You can [`read`](crate::generic::Reg::read) this register and get [`input_sync_bypass::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`input_sync_bypass::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INPUT_SYNC_BYPASS_SPEC; diff --git a/src/pio0/instr_mem.rs b/src/pio0/instr_mem.rs index 1b69c4ef9..c206f396a 100644 --- a/src/pio0/instr_mem.rs +++ b/src/pio0/instr_mem.rs @@ -1,3 +1,5 @@ +#[doc = "Register `INSTR_MEM%s` reader"] +pub type R = crate::R; #[doc = "Register `INSTR_MEM%s` writer"] pub type W = crate::W; #[doc = "Field `INSTR_MEM0` writer - "] @@ -12,11 +14,13 @@ impl W { } #[doc = "Write-only access to instruction memory location %s -You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`instr_mem::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`instr_mem::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`instr_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INSTR_MEM_SPEC; impl crate::RegisterSpec for INSTR_MEM_SPEC { type Ux = u32; } +#[doc = "`read()` method returns [`instr_mem::R`](R) reader structure"] +impl crate::Readable for INSTR_MEM_SPEC {} #[doc = "`write(|w| ..)` method takes [`instr_mem::W`](W) writer structure"] impl crate::Writable for INSTR_MEM_SPEC { type Safety = crate::Unsafe; diff --git a/src/pio0/intr.rs b/src/pio0/intr.rs index 49bb86e21..06c2d33a8 100644 --- a/src/pio0/intr.rs +++ b/src/pio0/intr.rs @@ -1,5 +1,7 @@ #[doc = "Register `INTR` reader"] pub type R = crate::R; +#[doc = "Register `INTR` writer"] +pub type W = crate::W; #[doc = "Field `SM0_RXNEMPTY` reader - "] pub type SM0_RXNEMPTY_R = crate::BitReader; #[doc = "Field `SM1_RXNEMPTY` reader - "] @@ -86,15 +88,22 @@ impl R { SM3_R::new(((self.bits >> 11) & 1) != 0) } } +impl W {} #[doc = "Raw Interrupts -You can [`read`](crate::generic::Reg::read) this register and get [`intr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`intr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTR_SPEC; impl crate::RegisterSpec for INTR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`intr::R`](R) reader structure"] impl crate::Readable for INTR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`intr::W`](W) writer structure"] +impl crate::Writable for INTR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets INTR to value 0"] impl crate::Resettable for INTR_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/pio0/irq.rs b/src/pio0/irq.rs index 587f8f05e..ed2858906 100644 --- a/src/pio0/irq.rs +++ b/src/pio0/irq.rs @@ -21,9 +21,7 @@ impl W { IRQ_W::new(self, 0) } } -#[doc = "State machine IRQ flags register. Write 1 to clear. There are 8 state machine IRQ flags, which can be set, cleared, and waited on by the state machines. There's no fixed association between flags and state machines -- any state machine can use any flag. - - Any of the 8 flags can be used for timing synchronisation between state machines, using IRQ and WAIT instructions. The lower four of these flags are also routed out to system-level interrupt requests, alongside FIFO status interrupts -- see e.g. IRQ0_INTE. +#[doc = "State machine IRQ flags register. Write 1 to clear. There are 8 state machine IRQ flags, which can be set, cleared, and waited on by the state machines. There's no fixed association between flags and state machines -- any state machine can use any flag. Any of the 8 flags can be used for timing synchronisation between state machines, using IRQ and WAIT instructions. The lower four of these flags are also routed out to system-level interrupt requests, alongside FIFO status interrupts -- see e.g. IRQ0_INTE. You can [`read`](crate::generic::Reg::read) this register and get [`irq::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IRQ_SPEC; diff --git a/src/pio0/irq_force.rs b/src/pio0/irq_force.rs index 46e8b95fd..26b326287 100644 --- a/src/pio0/irq_force.rs +++ b/src/pio0/irq_force.rs @@ -1,3 +1,5 @@ +#[doc = "Register `IRQ_FORCE` reader"] +pub type R = crate::R; #[doc = "Register `IRQ_FORCE` writer"] pub type W = crate::W; #[doc = "Field `IRQ_FORCE` writer - "] @@ -12,11 +14,13 @@ impl W { } #[doc = "Writing a 1 to each of these bits will forcibly assert the corresponding IRQ. Note this is different to the INTF register: writing here affects PIO internal state. INTF just asserts the processor-facing IRQ signal for testing ISRs, and is not visible to the state machines. -You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_force::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`irq_force::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_force::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IRQ_FORCE_SPEC; impl crate::RegisterSpec for IRQ_FORCE_SPEC { type Ux = u32; } +#[doc = "`read()` method returns [`irq_force::R`](R) reader structure"] +impl crate::Readable for IRQ_FORCE_SPEC {} #[doc = "`write(|w| ..)` method takes [`irq_force::W`](W) writer structure"] impl crate::Writable for IRQ_FORCE_SPEC { type Safety = crate::Unsafe; diff --git a/src/pio0/rxf.rs b/src/pio0/rxf.rs index 30cbc12b6..5d300ccf5 100644 --- a/src/pio0/rxf.rs +++ b/src/pio0/rxf.rs @@ -1,24 +1,34 @@ #[doc = "Register `RXF%s` reader"] pub type R = crate::R; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) - } -} -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +#[doc = "Register `RXF%s` writer"] +pub type W = crate::W; +#[doc = "Field `RXF0` reader - + +The field is **modified** in some way after a read operation."] +pub type RXF0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn rxf0(&self) -> RXF0_R { + RXF0_R::new(self.bits) } } +impl W {} #[doc = "Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined. -You can [`read`](crate::generic::Reg::read) this register and get [`rxf::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`rxf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RXF_SPEC; impl crate::RegisterSpec for RXF_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`rxf::R`](R) reader structure"] impl crate::Readable for RXF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rxf::W`](W) writer structure"] +impl crate::Writable for RXF_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets RXF%s to value 0"] impl crate::Resettable for RXF_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/pio0/sm.rs b/src/pio0/sm.rs index 05686cd36..3ddddff33 100644 --- a/src/pio0/sm.rs +++ b/src/pio0/sm.rs @@ -9,8 +9,7 @@ pub struct SM { sm_pinctrl: SM_PINCTRL, } impl SM { - #[doc = "0x00 - Clock divisor register for state machine 0 - Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)"] + #[doc = "0x00 - Clock divisor register for state machine 0 Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)"] #[inline(always)] pub const fn sm_clkdiv(&self) -> &SM_CLKDIV { &self.sm_clkdiv @@ -30,8 +29,7 @@ impl SM { pub const fn sm_addr(&self) -> &SM_ADDR { &self.sm_addr } - #[doc = "0x10 - Read to see the instruction currently addressed by state machine 0's program counter - Write to execute an instruction immediately (including jumps) and then resume execution."] + #[doc = "0x10 - Read to see the instruction currently addressed by state machine 0's program counter Write to execute an instruction immediately (including jumps) and then resume execution."] #[inline(always)] pub const fn sm_instr(&self) -> &SM_INSTR { &self.sm_instr @@ -42,16 +40,14 @@ impl SM { &self.sm_pinctrl } } -#[doc = "SM_CLKDIV (rw) register accessor: Clock divisor register for state machine 0 - Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) +#[doc = "SM_CLKDIV (rw) register accessor: Clock divisor register for state machine 0 Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) You can [`read`](crate::generic::Reg::read) this register and get [`sm_clkdiv::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sm_clkdiv::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@sm_clkdiv`] module"] pub type SM_CLKDIV = crate::Reg; -#[doc = "Clock divisor register for state machine 0 - Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)"] +#[doc = "Clock divisor register for state machine 0 Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)"] pub mod sm_clkdiv; #[doc = "SM_EXECCTRL (rw) register accessor: Execution/behavioural settings for state machine 0 @@ -71,25 +67,23 @@ module"] pub type SM_SHIFTCTRL = crate::Reg; #[doc = "Control behaviour of the input/output shift registers for state machine 0"] pub mod sm_shiftctrl; -#[doc = "SM_ADDR (r) register accessor: Current instruction address of state machine 0 +#[doc = "SM_ADDR (rw) register accessor: Current instruction address of state machine 0 -You can [`read`](crate::generic::Reg::read) this register and get [`sm_addr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`sm_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sm_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@sm_addr`] module"] pub type SM_ADDR = crate::Reg; #[doc = "Current instruction address of state machine 0"] pub mod sm_addr; -#[doc = "SM_INSTR (rw) register accessor: Read to see the instruction currently addressed by state machine 0's program counter - Write to execute an instruction immediately (including jumps) and then resume execution. +#[doc = "SM_INSTR (rw) register accessor: Read to see the instruction currently addressed by state machine 0's program counter Write to execute an instruction immediately (including jumps) and then resume execution. You can [`read`](crate::generic::Reg::read) this register and get [`sm_instr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sm_instr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@sm_instr`] module"] pub type SM_INSTR = crate::Reg; -#[doc = "Read to see the instruction currently addressed by state machine 0's program counter - Write to execute an instruction immediately (including jumps) and then resume execution."] +#[doc = "Read to see the instruction currently addressed by state machine 0's program counter Write to execute an instruction immediately (including jumps) and then resume execution."] pub mod sm_instr; #[doc = "SM_PINCTRL (rw) register accessor: State machine pin control diff --git a/src/pio0/sm/sm_addr.rs b/src/pio0/sm/sm_addr.rs index 56a6ac71d..a3d199542 100644 --- a/src/pio0/sm/sm_addr.rs +++ b/src/pio0/sm/sm_addr.rs @@ -1,5 +1,7 @@ #[doc = "Register `SM_ADDR` reader"] pub type R = crate::R; +#[doc = "Register `SM_ADDR` writer"] +pub type W = crate::W; #[doc = "Field `SM0_ADDR` reader - "] pub type SM0_ADDR_R = crate::FieldReader; impl R { @@ -9,15 +11,22 @@ impl R { SM0_ADDR_R::new((self.bits & 0x1f) as u8) } } +impl W {} #[doc = "Current instruction address of state machine 0 -You can [`read`](crate::generic::Reg::read) this register and get [`sm_addr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`sm_addr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sm_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SM_ADDR_SPEC; impl crate::RegisterSpec for SM_ADDR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`sm_addr::R`](R) reader structure"] impl crate::Readable for SM_ADDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sm_addr::W`](W) writer structure"] +impl crate::Writable for SM_ADDR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets SM_ADDR to value 0"] impl crate::Resettable for SM_ADDR_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/pio0/sm/sm_clkdiv.rs b/src/pio0/sm/sm_clkdiv.rs index e65fbf594..581ae5932 100644 --- a/src/pio0/sm/sm_clkdiv.rs +++ b/src/pio0/sm/sm_clkdiv.rs @@ -6,11 +6,9 @@ pub type W = crate::W; pub type FRAC_R = crate::FieldReader; #[doc = "Field `FRAC` writer - Fractional part of clock divisor"] pub type FRAC_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `INT` reader - Effective frequency is sysclk/(int + frac/256). - Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0."] +#[doc = "Field `INT` reader - Effective frequency is sysclk/(int + frac/256). Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0."] pub type INT_R = crate::FieldReader; -#[doc = "Field `INT` writer - Effective frequency is sysclk/(int + frac/256). - Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0."] +#[doc = "Field `INT` writer - Effective frequency is sysclk/(int + frac/256). Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0."] pub type INT_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; impl R { #[doc = "Bits 8:15 - Fractional part of clock divisor"] @@ -18,8 +16,7 @@ impl R { pub fn frac(&self) -> FRAC_R { FRAC_R::new(((self.bits >> 8) & 0xff) as u8) } - #[doc = "Bits 16:31 - Effective frequency is sysclk/(int + frac/256). - Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0."] + #[doc = "Bits 16:31 - Effective frequency is sysclk/(int + frac/256). Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0."] #[inline(always)] pub fn int(&self) -> INT_R { INT_R::new(((self.bits >> 16) & 0xffff) as u16) @@ -32,16 +29,14 @@ impl W { pub fn frac(&mut self) -> FRAC_W { FRAC_W::new(self, 8) } - #[doc = "Bits 16:31 - Effective frequency is sysclk/(int + frac/256). - Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0."] + #[doc = "Bits 16:31 - Effective frequency is sysclk/(int + frac/256). Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0."] #[inline(always)] #[must_use] pub fn int(&mut self) -> INT_W { INT_W::new(self, 16) } } -#[doc = "Clock divisor register for state machine 0 - Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) +#[doc = "Clock divisor register for state machine 0 Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) You can [`read`](crate::generic::Reg::read) this register and get [`sm_clkdiv::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sm_clkdiv::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SM_CLKDIV_SPEC; diff --git a/src/pio0/sm/sm_execctrl.rs b/src/pio0/sm/sm_execctrl.rs index 419ecc091..5569b487d 100644 --- a/src/pio0/sm/sm_execctrl.rs +++ b/src/pio0/sm/sm_execctrl.rs @@ -65,25 +65,17 @@ where pub type WRAP_BOTTOM_R = crate::FieldReader; #[doc = "Field `WRAP_BOTTOM` writer - After reaching wrap_top, execution is wrapped to this address."] pub type WRAP_BOTTOM_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; -#[doc = "Field `WRAP_TOP` reader - After reaching this address, execution is wrapped to wrap_bottom. - If the instruction is a jump, and the jump condition is true, the jump takes priority."] +#[doc = "Field `WRAP_TOP` reader - After reaching this address, execution is wrapped to wrap_bottom. If the instruction is a jump, and the jump condition is true, the jump takes priority."] pub type WRAP_TOP_R = crate::FieldReader; -#[doc = "Field `WRAP_TOP` writer - After reaching this address, execution is wrapped to wrap_bottom. - If the instruction is a jump, and the jump condition is true, the jump takes priority."] +#[doc = "Field `WRAP_TOP` writer - After reaching this address, execution is wrapped to wrap_bottom. If the instruction is a jump, and the jump condition is true, the jump takes priority."] pub type WRAP_TOP_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; #[doc = "Field `OUT_STICKY` reader - Continuously assert the most recent OUT/SET to the pins"] pub type OUT_STICKY_R = crate::BitReader; #[doc = "Field `OUT_STICKY` writer - Continuously assert the most recent OUT/SET to the pins"] pub type OUT_STICKY_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `INLINE_OUT_EN` reader - If 1, use a bit of OUT data as an auxiliary write enable - When used in conjunction with OUT_STICKY, writes with an enable of 0 will - deassert the latest pin write. This can create useful masking/override behaviour - due to the priority ordering of state machine pin writes (SM0 < SM1 < ...)"] +#[doc = "Field `INLINE_OUT_EN` reader - If 1, use a bit of OUT data as an auxiliary write enable When used in conjunction with OUT_STICKY, writes with an enable of 0 will deassert the latest pin write. This can create useful masking/override behaviour due to the priority ordering of state machine pin writes (SM0 < SM1 < ...)"] pub type INLINE_OUT_EN_R = crate::BitReader; -#[doc = "Field `INLINE_OUT_EN` writer - If 1, use a bit of OUT data as an auxiliary write enable - When used in conjunction with OUT_STICKY, writes with an enable of 0 will - deassert the latest pin write. This can create useful masking/override behaviour - due to the priority ordering of state machine pin writes (SM0 < SM1 < ...)"] +#[doc = "Field `INLINE_OUT_EN` writer - If 1, use a bit of OUT data as an auxiliary write enable When used in conjunction with OUT_STICKY, writes with an enable of 0 will deassert the latest pin write. This can create useful masking/override behaviour due to the priority ordering of state machine pin writes (SM0 < SM1 < ...)"] pub type INLINE_OUT_EN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `OUT_EN_SEL` reader - Which data bit to use for inline OUT enable"] pub type OUT_EN_SEL_R = crate::FieldReader; @@ -119,8 +111,7 @@ impl R { pub fn wrap_bottom(&self) -> WRAP_BOTTOM_R { WRAP_BOTTOM_R::new(((self.bits >> 7) & 0x1f) as u8) } - #[doc = "Bits 12:16 - After reaching this address, execution is wrapped to wrap_bottom. - If the instruction is a jump, and the jump condition is true, the jump takes priority."] + #[doc = "Bits 12:16 - After reaching this address, execution is wrapped to wrap_bottom. If the instruction is a jump, and the jump condition is true, the jump takes priority."] #[inline(always)] pub fn wrap_top(&self) -> WRAP_TOP_R { WRAP_TOP_R::new(((self.bits >> 12) & 0x1f) as u8) @@ -130,10 +121,7 @@ impl R { pub fn out_sticky(&self) -> OUT_STICKY_R { OUT_STICKY_R::new(((self.bits >> 17) & 1) != 0) } - #[doc = "Bit 18 - If 1, use a bit of OUT data as an auxiliary write enable - When used in conjunction with OUT_STICKY, writes with an enable of 0 will - deassert the latest pin write. This can create useful masking/override behaviour - due to the priority ordering of state machine pin writes (SM0 < SM1 < ...)"] + #[doc = "Bit 18 - If 1, use a bit of OUT data as an auxiliary write enable When used in conjunction with OUT_STICKY, writes with an enable of 0 will deassert the latest pin write. This can create useful masking/override behaviour due to the priority ordering of state machine pin writes (SM0 < SM1 < ...)"] #[inline(always)] pub fn inline_out_en(&self) -> INLINE_OUT_EN_R { INLINE_OUT_EN_R::new(((self.bits >> 18) & 1) != 0) @@ -183,8 +171,7 @@ impl W { pub fn wrap_bottom(&mut self) -> WRAP_BOTTOM_W { WRAP_BOTTOM_W::new(self, 7) } - #[doc = "Bits 12:16 - After reaching this address, execution is wrapped to wrap_bottom. - If the instruction is a jump, and the jump condition is true, the jump takes priority."] + #[doc = "Bits 12:16 - After reaching this address, execution is wrapped to wrap_bottom. If the instruction is a jump, and the jump condition is true, the jump takes priority."] #[inline(always)] #[must_use] pub fn wrap_top(&mut self) -> WRAP_TOP_W { @@ -196,10 +183,7 @@ impl W { pub fn out_sticky(&mut self) -> OUT_STICKY_W { OUT_STICKY_W::new(self, 17) } - #[doc = "Bit 18 - If 1, use a bit of OUT data as an auxiliary write enable - When used in conjunction with OUT_STICKY, writes with an enable of 0 will - deassert the latest pin write. This can create useful masking/override behaviour - due to the priority ordering of state machine pin writes (SM0 < SM1 < ...)"] + #[doc = "Bit 18 - If 1, use a bit of OUT data as an auxiliary write enable When used in conjunction with OUT_STICKY, writes with an enable of 0 will deassert the latest pin write. This can create useful masking/override behaviour due to the priority ordering of state machine pin writes (SM0 < SM1 < ...)"] #[inline(always)] #[must_use] pub fn inline_out_en(&mut self) -> INLINE_OUT_EN_W { diff --git a/src/pio0/sm/sm_instr.rs b/src/pio0/sm/sm_instr.rs index 795552995..3d1495d20 100644 --- a/src/pio0/sm/sm_instr.rs +++ b/src/pio0/sm/sm_instr.rs @@ -21,8 +21,7 @@ impl W { SM0_INSTR_W::new(self, 0) } } -#[doc = "Read to see the instruction currently addressed by state machine 0's program counter - Write to execute an instruction immediately (including jumps) and then resume execution. +#[doc = "Read to see the instruction currently addressed by state machine 0's program counter Write to execute an instruction immediately (including jumps) and then resume execution. You can [`read`](crate::generic::Reg::read) this register and get [`sm_instr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sm_instr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SM_INSTR_SPEC; diff --git a/src/pio0/sm/sm_shiftctrl.rs b/src/pio0/sm/sm_shiftctrl.rs index bcb7872b2..a78aa3c29 100644 --- a/src/pio0/sm/sm_shiftctrl.rs +++ b/src/pio0/sm/sm_shiftctrl.rs @@ -18,33 +18,21 @@ pub type IN_SHIFTDIR_W<'a, REG> = crate::BitWriter<'a, REG>; pub type OUT_SHIFTDIR_R = crate::BitReader; #[doc = "Field `OUT_SHIFTDIR` writer - 1 = shift out of output shift register to right. 0 = to left."] pub type OUT_SHIFTDIR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `PUSH_THRESH` reader - Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place. - Write 0 for value of 32."] +#[doc = "Field `PUSH_THRESH` reader - Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place. Write 0 for value of 32."] pub type PUSH_THRESH_R = crate::FieldReader; -#[doc = "Field `PUSH_THRESH` writer - Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place. - Write 0 for value of 32."] +#[doc = "Field `PUSH_THRESH` writer - Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place. Write 0 for value of 32."] pub type PUSH_THRESH_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; -#[doc = "Field `PULL_THRESH` reader - Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place. - Write 0 for value of 32."] +#[doc = "Field `PULL_THRESH` reader - Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place. Write 0 for value of 32."] pub type PULL_THRESH_R = crate::FieldReader; -#[doc = "Field `PULL_THRESH` writer - Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place. - Write 0 for value of 32."] +#[doc = "Field `PULL_THRESH` writer - Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place. Write 0 for value of 32."] pub type PULL_THRESH_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; -#[doc = "Field `FJOIN_TX` reader - When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep. - RX FIFO is disabled as a result (always reads as both full and empty). - FIFOs are flushed when this bit is changed."] +#[doc = "Field `FJOIN_TX` reader - When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep. RX FIFO is disabled as a result (always reads as both full and empty). FIFOs are flushed when this bit is changed."] pub type FJOIN_TX_R = crate::BitReader; -#[doc = "Field `FJOIN_TX` writer - When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep. - RX FIFO is disabled as a result (always reads as both full and empty). - FIFOs are flushed when this bit is changed."] +#[doc = "Field `FJOIN_TX` writer - When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep. RX FIFO is disabled as a result (always reads as both full and empty). FIFOs are flushed when this bit is changed."] pub type FJOIN_TX_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `FJOIN_RX` reader - When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep. - TX FIFO is disabled as a result (always reads as both full and empty). - FIFOs are flushed when this bit is changed."] +#[doc = "Field `FJOIN_RX` reader - When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep. TX FIFO is disabled as a result (always reads as both full and empty). FIFOs are flushed when this bit is changed."] pub type FJOIN_RX_R = crate::BitReader; -#[doc = "Field `FJOIN_RX` writer - When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep. - TX FIFO is disabled as a result (always reads as both full and empty). - FIFOs are flushed when this bit is changed."] +#[doc = "Field `FJOIN_RX` writer - When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep. TX FIFO is disabled as a result (always reads as both full and empty). FIFOs are flushed when this bit is changed."] pub type FJOIN_RX_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 16 - Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH."] @@ -67,28 +55,22 @@ impl R { pub fn out_shiftdir(&self) -> OUT_SHIFTDIR_R { OUT_SHIFTDIR_R::new(((self.bits >> 19) & 1) != 0) } - #[doc = "Bits 20:24 - Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place. - Write 0 for value of 32."] + #[doc = "Bits 20:24 - Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place. Write 0 for value of 32."] #[inline(always)] pub fn push_thresh(&self) -> PUSH_THRESH_R { PUSH_THRESH_R::new(((self.bits >> 20) & 0x1f) as u8) } - #[doc = "Bits 25:29 - Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place. - Write 0 for value of 32."] + #[doc = "Bits 25:29 - Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place. Write 0 for value of 32."] #[inline(always)] pub fn pull_thresh(&self) -> PULL_THRESH_R { PULL_THRESH_R::new(((self.bits >> 25) & 0x1f) as u8) } - #[doc = "Bit 30 - When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep. - RX FIFO is disabled as a result (always reads as both full and empty). - FIFOs are flushed when this bit is changed."] + #[doc = "Bit 30 - When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep. RX FIFO is disabled as a result (always reads as both full and empty). FIFOs are flushed when this bit is changed."] #[inline(always)] pub fn fjoin_tx(&self) -> FJOIN_TX_R { FJOIN_TX_R::new(((self.bits >> 30) & 1) != 0) } - #[doc = "Bit 31 - When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep. - TX FIFO is disabled as a result (always reads as both full and empty). - FIFOs are flushed when this bit is changed."] + #[doc = "Bit 31 - When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep. TX FIFO is disabled as a result (always reads as both full and empty). FIFOs are flushed when this bit is changed."] #[inline(always)] pub fn fjoin_rx(&self) -> FJOIN_RX_R { FJOIN_RX_R::new(((self.bits >> 31) & 1) != 0) @@ -119,31 +101,25 @@ impl W { pub fn out_shiftdir(&mut self) -> OUT_SHIFTDIR_W { OUT_SHIFTDIR_W::new(self, 19) } - #[doc = "Bits 20:24 - Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place. - Write 0 for value of 32."] + #[doc = "Bits 20:24 - Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place. Write 0 for value of 32."] #[inline(always)] #[must_use] pub fn push_thresh(&mut self) -> PUSH_THRESH_W { PUSH_THRESH_W::new(self, 20) } - #[doc = "Bits 25:29 - Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place. - Write 0 for value of 32."] + #[doc = "Bits 25:29 - Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place. Write 0 for value of 32."] #[inline(always)] #[must_use] pub fn pull_thresh(&mut self) -> PULL_THRESH_W { PULL_THRESH_W::new(self, 25) } - #[doc = "Bit 30 - When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep. - RX FIFO is disabled as a result (always reads as both full and empty). - FIFOs are flushed when this bit is changed."] + #[doc = "Bit 30 - When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep. RX FIFO is disabled as a result (always reads as both full and empty). FIFOs are flushed when this bit is changed."] #[inline(always)] #[must_use] pub fn fjoin_tx(&mut self) -> FJOIN_TX_W { FJOIN_TX_W::new(self, 30) } - #[doc = "Bit 31 - When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep. - TX FIFO is disabled as a result (always reads as both full and empty). - FIFOs are flushed when this bit is changed."] + #[doc = "Bit 31 - When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep. TX FIFO is disabled as a result (always reads as both full and empty). FIFOs are flushed when this bit is changed."] #[inline(always)] #[must_use] pub fn fjoin_rx(&mut self) -> FJOIN_RX_W { diff --git a/src/pio0/sm_irq.rs b/src/pio0/sm_irq.rs index b059f6698..1308fab93 100644 --- a/src/pio0/sm_irq.rs +++ b/src/pio0/sm_irq.rs @@ -40,9 +40,9 @@ module"] pub type IRQ_INTF = crate::Reg; #[doc = "Interrupt Force for irq0"] pub mod irq_intf; -#[doc = "IRQ_INTS (r) register accessor: Interrupt status after masking & forcing for irq0 +#[doc = "IRQ_INTS (rw) register accessor: Interrupt status after masking & forcing for irq0 -You can [`read`](crate::generic::Reg::read) this register and get [`irq_ints::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`irq_ints::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_ints::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@irq_ints`] module"] diff --git a/src/pio0/sm_irq/irq_ints.rs b/src/pio0/sm_irq/irq_ints.rs index a4cdd2a7b..1c8662325 100644 --- a/src/pio0/sm_irq/irq_ints.rs +++ b/src/pio0/sm_irq/irq_ints.rs @@ -1,5 +1,7 @@ #[doc = "Register `IRQ_INTS` reader"] pub type R = crate::R; +#[doc = "Register `IRQ_INTS` writer"] +pub type W = crate::W; #[doc = "Field `SM0_RXNEMPTY` reader - "] pub type SM0_RXNEMPTY_R = crate::BitReader; #[doc = "Field `SM1_RXNEMPTY` reader - "] @@ -86,15 +88,22 @@ impl R { SM3_R::new(((self.bits >> 11) & 1) != 0) } } +impl W {} #[doc = "Interrupt status after masking & forcing for irq0 -You can [`read`](crate::generic::Reg::read) this register and get [`irq_ints::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`irq_ints::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_ints::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IRQ_INTS_SPEC; impl crate::RegisterSpec for IRQ_INTS_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`irq_ints::R`](R) reader structure"] impl crate::Readable for IRQ_INTS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`irq_ints::W`](W) writer structure"] +impl crate::Writable for IRQ_INTS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets IRQ_INTS to value 0"] impl crate::Resettable for IRQ_INTS_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/pio0/txf.rs b/src/pio0/txf.rs index 45803a49c..5c29e05d4 100644 --- a/src/pio0/txf.rs +++ b/src/pio0/txf.rs @@ -1,18 +1,26 @@ +#[doc = "Register `TXF%s` reader"] +pub type R = crate::R; #[doc = "Register `TXF%s` writer"] pub type W = crate::W; -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - write!(f, "(not readable)") +#[doc = "Field `TXF0` writer - "] +pub type TXF0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn txf0(&mut self) -> TXF0_W { + TXF0_W::new(self, 0) } } -impl W {} #[doc = "Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO. -You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txf::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`txf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TXF_SPEC; impl crate::RegisterSpec for TXF_SPEC { type Ux = u32; } +#[doc = "`read()` method returns [`txf::R`](R) reader structure"] +impl crate::Readable for TXF_SPEC {} #[doc = "`write(|w| ..)` method takes [`txf::W`](W) writer structure"] impl crate::Writable for TXF_SPEC { type Safety = crate::Unsafe; diff --git a/src/pll_sys.rs b/src/pll_sys.rs index e0c16b1ec..b329f65bc 100644 --- a/src/pll_sys.rs +++ b/src/pll_sys.rs @@ -7,11 +7,7 @@ pub struct RegisterBlock { prim: PRIM, } impl RegisterBlock { - #[doc = "0x00 - Control and Status - GENERAL CONSTRAINTS: - Reference clock frequency min=5MHz, max=800MHz - Feedback divider min=16, max=320 - VCO frequency min=750MHz, max=1600MHz"] + #[doc = "0x00 - Control and Status GENERAL CONSTRAINTS: Reference clock frequency min=5MHz, max=800MHz Feedback divider min=16, max=320 VCO frequency min=750MHz, max=1600MHz"] #[inline(always)] pub const fn cs(&self) -> &CS { &self.cs @@ -21,36 +17,25 @@ impl RegisterBlock { pub const fn pwr(&self) -> &PWR { &self.pwr } - #[doc = "0x08 - Feedback divisor - (note: this PLL does not support fractional division)"] + #[doc = "0x08 - Feedback divisor (note: this PLL does not support fractional division)"] #[inline(always)] pub const fn fbdiv_int(&self) -> &FBDIV_INT { &self.fbdiv_int } - #[doc = "0x0c - Controls the PLL post dividers for the primary output - (note: this PLL does not have a secondary output) - the primary output is driven from VCO divided by postdiv1*postdiv2"] + #[doc = "0x0c - Controls the PLL post dividers for the primary output (note: this PLL does not have a secondary output) the primary output is driven from VCO divided by postdiv1*postdiv2"] #[inline(always)] pub const fn prim(&self) -> &PRIM { &self.prim } } -#[doc = "CS (rw) register accessor: Control and Status - GENERAL CONSTRAINTS: - Reference clock frequency min=5MHz, max=800MHz - Feedback divider min=16, max=320 - VCO frequency min=750MHz, max=1600MHz +#[doc = "CS (rw) register accessor: Control and Status GENERAL CONSTRAINTS: Reference clock frequency min=5MHz, max=800MHz Feedback divider min=16, max=320 VCO frequency min=750MHz, max=1600MHz You can [`read`](crate::generic::Reg::read) this register and get [`cs::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cs::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@cs`] module"] pub type CS = crate::Reg; -#[doc = "Control and Status - GENERAL CONSTRAINTS: - Reference clock frequency min=5MHz, max=800MHz - Feedback divider min=16, max=320 - VCO frequency min=750MHz, max=1600MHz"] +#[doc = "Control and Status GENERAL CONSTRAINTS: Reference clock frequency min=5MHz, max=800MHz Feedback divider min=16, max=320 VCO frequency min=750MHz, max=1600MHz"] pub mod cs; #[doc = "PWR (rw) register accessor: Controls the PLL power modes. @@ -61,27 +46,21 @@ module"] pub type PWR = crate::Reg; #[doc = "Controls the PLL power modes."] pub mod pwr; -#[doc = "FBDIV_INT (rw) register accessor: Feedback divisor - (note: this PLL does not support fractional division) +#[doc = "FBDIV_INT (rw) register accessor: Feedback divisor (note: this PLL does not support fractional division) You can [`read`](crate::generic::Reg::read) this register and get [`fbdiv_int::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fbdiv_int::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@fbdiv_int`] module"] pub type FBDIV_INT = crate::Reg; -#[doc = "Feedback divisor - (note: this PLL does not support fractional division)"] +#[doc = "Feedback divisor (note: this PLL does not support fractional division)"] pub mod fbdiv_int; -#[doc = "PRIM (rw) register accessor: Controls the PLL post dividers for the primary output - (note: this PLL does not have a secondary output) - the primary output is driven from VCO divided by postdiv1*postdiv2 +#[doc = "PRIM (rw) register accessor: Controls the PLL post dividers for the primary output (note: this PLL does not have a secondary output) the primary output is driven from VCO divided by postdiv1*postdiv2 You can [`read`](crate::generic::Reg::read) this register and get [`prim::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`prim::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@prim`] module"] pub type PRIM = crate::Reg; -#[doc = "Controls the PLL post dividers for the primary output - (note: this PLL does not have a secondary output) - the primary output is driven from VCO divided by postdiv1*postdiv2"] +#[doc = "Controls the PLL post dividers for the primary output (note: this PLL does not have a secondary output) the primary output is driven from VCO divided by postdiv1*postdiv2"] pub mod prim; diff --git a/src/pll_sys/cs.rs b/src/pll_sys/cs.rs index a24311e4a..7b341741f 100644 --- a/src/pll_sys/cs.rs +++ b/src/pll_sys/cs.rs @@ -2,13 +2,9 @@ pub type R = crate::R; #[doc = "Register `CS` writer"] pub type W = crate::W; -#[doc = "Field `REFDIV` reader - Divides the PLL input reference clock. - Behaviour is undefined for div=0. - PLL output will be unpredictable during refdiv changes, wait for lock=1 before using it."] +#[doc = "Field `REFDIV` reader - Divides the PLL input reference clock. Behaviour is undefined for div=0. PLL output will be unpredictable during refdiv changes, wait for lock=1 before using it."] pub type REFDIV_R = crate::FieldReader; -#[doc = "Field `REFDIV` writer - Divides the PLL input reference clock. - Behaviour is undefined for div=0. - PLL output will be unpredictable during refdiv changes, wait for lock=1 before using it."] +#[doc = "Field `REFDIV` writer - Divides the PLL input reference clock. Behaviour is undefined for div=0. PLL output will be unpredictable during refdiv changes, wait for lock=1 before using it."] pub type REFDIV_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; #[doc = "Field `BYPASS` reader - Passes the reference clock to the output instead of the divided VCO. The VCO continues to run so the user can switch between the reference clock and the divided VCO but the output will glitch when doing so."] pub type BYPASS_R = crate::BitReader; @@ -17,9 +13,7 @@ pub type BYPASS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `LOCK` reader - PLL is locked"] pub type LOCK_R = crate::BitReader; impl R { - #[doc = "Bits 0:5 - Divides the PLL input reference clock. - Behaviour is undefined for div=0. - PLL output will be unpredictable during refdiv changes, wait for lock=1 before using it."] + #[doc = "Bits 0:5 - Divides the PLL input reference clock. Behaviour is undefined for div=0. PLL output will be unpredictable during refdiv changes, wait for lock=1 before using it."] #[inline(always)] pub fn refdiv(&self) -> REFDIV_R { REFDIV_R::new((self.bits & 0x3f) as u8) @@ -36,9 +30,7 @@ impl R { } } impl W { - #[doc = "Bits 0:5 - Divides the PLL input reference clock. - Behaviour is undefined for div=0. - PLL output will be unpredictable during refdiv changes, wait for lock=1 before using it."] + #[doc = "Bits 0:5 - Divides the PLL input reference clock. Behaviour is undefined for div=0. PLL output will be unpredictable during refdiv changes, wait for lock=1 before using it."] #[inline(always)] #[must_use] pub fn refdiv(&mut self) -> REFDIV_W { @@ -51,11 +43,7 @@ impl W { BYPASS_W::new(self, 8) } } -#[doc = "Control and Status - GENERAL CONSTRAINTS: - Reference clock frequency min=5MHz, max=800MHz - Feedback divider min=16, max=320 - VCO frequency min=750MHz, max=1600MHz +#[doc = "Control and Status GENERAL CONSTRAINTS: Reference clock frequency min=5MHz, max=800MHz Feedback divider min=16, max=320 VCO frequency min=750MHz, max=1600MHz You can [`read`](crate::generic::Reg::read) this register and get [`cs::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cs::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CS_SPEC; diff --git a/src/pll_sys/fbdiv_int.rs b/src/pll_sys/fbdiv_int.rs index 8295a2c89..7a13d70c6 100644 --- a/src/pll_sys/fbdiv_int.rs +++ b/src/pll_sys/fbdiv_int.rs @@ -21,8 +21,7 @@ impl W { FBDIV_INT_W::new(self, 0) } } -#[doc = "Feedback divisor - (note: this PLL does not support fractional division) +#[doc = "Feedback divisor (note: this PLL does not support fractional division) You can [`read`](crate::generic::Reg::read) this register and get [`fbdiv_int::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fbdiv_int::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FBDIV_INT_SPEC; diff --git a/src/pll_sys/prim.rs b/src/pll_sys/prim.rs index 893d1d041..ec9d8a1f4 100644 --- a/src/pll_sys/prim.rs +++ b/src/pll_sys/prim.rs @@ -36,9 +36,7 @@ impl W { POSTDIV1_W::new(self, 16) } } -#[doc = "Controls the PLL post dividers for the primary output - (note: this PLL does not have a secondary output) - the primary output is driven from VCO divided by postdiv1*postdiv2 +#[doc = "Controls the PLL post dividers for the primary output (note: this PLL does not have a secondary output) the primary output is driven from VCO divided by postdiv1*postdiv2 You can [`read`](crate::generic::Reg::read) this register and get [`prim::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`prim::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PRIM_SPEC; diff --git a/src/pll_sys/pwr.rs b/src/pll_sys/pwr.rs index de28e0723..51b19ad57 100644 --- a/src/pll_sys/pwr.rs +++ b/src/pll_sys/pwr.rs @@ -2,80 +2,64 @@ pub type R = crate::R; #[doc = "Register `PWR` writer"] pub type W = crate::W; -#[doc = "Field `PD` reader - PLL powerdown - To save power set high when PLL output not required."] +#[doc = "Field `PD` reader - PLL powerdown To save power set high when PLL output not required."] pub type PD_R = crate::BitReader; -#[doc = "Field `PD` writer - PLL powerdown - To save power set high when PLL output not required."] +#[doc = "Field `PD` writer - PLL powerdown To save power set high when PLL output not required."] pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `DSMPD` reader - PLL DSM powerdown - Nothing is achieved by setting this low."] +#[doc = "Field `DSMPD` reader - PLL DSM powerdown Nothing is achieved by setting this low."] pub type DSMPD_R = crate::BitReader; -#[doc = "Field `DSMPD` writer - PLL DSM powerdown - Nothing is achieved by setting this low."] +#[doc = "Field `DSMPD` writer - PLL DSM powerdown Nothing is achieved by setting this low."] pub type DSMPD_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `POSTDIVPD` reader - PLL post divider powerdown - To save power set high when PLL output not required or bypass=1."] +#[doc = "Field `POSTDIVPD` reader - PLL post divider powerdown To save power set high when PLL output not required or bypass=1."] pub type POSTDIVPD_R = crate::BitReader; -#[doc = "Field `POSTDIVPD` writer - PLL post divider powerdown - To save power set high when PLL output not required or bypass=1."] +#[doc = "Field `POSTDIVPD` writer - PLL post divider powerdown To save power set high when PLL output not required or bypass=1."] pub type POSTDIVPD_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `VCOPD` reader - PLL VCO powerdown - To save power set high when PLL output not required or bypass=1."] +#[doc = "Field `VCOPD` reader - PLL VCO powerdown To save power set high when PLL output not required or bypass=1."] pub type VCOPD_R = crate::BitReader; -#[doc = "Field `VCOPD` writer - PLL VCO powerdown - To save power set high when PLL output not required or bypass=1."] +#[doc = "Field `VCOPD` writer - PLL VCO powerdown To save power set high when PLL output not required or bypass=1."] pub type VCOPD_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { - #[doc = "Bit 0 - PLL powerdown - To save power set high when PLL output not required."] + #[doc = "Bit 0 - PLL powerdown To save power set high when PLL output not required."] #[inline(always)] pub fn pd(&self) -> PD_R { PD_R::new((self.bits & 1) != 0) } - #[doc = "Bit 2 - PLL DSM powerdown - Nothing is achieved by setting this low."] + #[doc = "Bit 2 - PLL DSM powerdown Nothing is achieved by setting this low."] #[inline(always)] pub fn dsmpd(&self) -> DSMPD_R { DSMPD_R::new(((self.bits >> 2) & 1) != 0) } - #[doc = "Bit 3 - PLL post divider powerdown - To save power set high when PLL output not required or bypass=1."] + #[doc = "Bit 3 - PLL post divider powerdown To save power set high when PLL output not required or bypass=1."] #[inline(always)] pub fn postdivpd(&self) -> POSTDIVPD_R { POSTDIVPD_R::new(((self.bits >> 3) & 1) != 0) } - #[doc = "Bit 5 - PLL VCO powerdown - To save power set high when PLL output not required or bypass=1."] + #[doc = "Bit 5 - PLL VCO powerdown To save power set high when PLL output not required or bypass=1."] #[inline(always)] pub fn vcopd(&self) -> VCOPD_R { VCOPD_R::new(((self.bits >> 5) & 1) != 0) } } impl W { - #[doc = "Bit 0 - PLL powerdown - To save power set high when PLL output not required."] + #[doc = "Bit 0 - PLL powerdown To save power set high when PLL output not required."] #[inline(always)] #[must_use] pub fn pd(&mut self) -> PD_W { PD_W::new(self, 0) } - #[doc = "Bit 2 - PLL DSM powerdown - Nothing is achieved by setting this low."] + #[doc = "Bit 2 - PLL DSM powerdown Nothing is achieved by setting this low."] #[inline(always)] #[must_use] pub fn dsmpd(&mut self) -> DSMPD_W { DSMPD_W::new(self, 2) } - #[doc = "Bit 3 - PLL post divider powerdown - To save power set high when PLL output not required or bypass=1."] + #[doc = "Bit 3 - PLL post divider powerdown To save power set high when PLL output not required or bypass=1."] #[inline(always)] #[must_use] pub fn postdivpd(&mut self) -> POSTDIVPD_W { POSTDIVPD_W::new(self, 3) } - #[doc = "Bit 5 - PLL VCO powerdown - To save power set high when PLL output not required or bypass=1."] + #[doc = "Bit 5 - PLL VCO powerdown To save power set high when PLL output not required or bypass=1."] #[inline(always)] #[must_use] pub fn vcopd(&mut self) -> VCOPD_W { diff --git a/src/ppb.rs b/src/ppb.rs index e8dee8f35..99a035463 100644 --- a/src/ppb.rs +++ b/src/ppb.rs @@ -47,8 +47,7 @@ impl RegisterBlock { pub const fn syst_csr(&self) -> &SYST_CSR { &self.syst_csr } - #[doc = "0xe014 - Use the SysTick Reload Value Register to specify the start value to load into the current value register when the counter reaches 0. It can be any value between 0 and 0x00FFFFFF. A start value of 0 is possible, but has no effect because the SysTick interrupt and COUNTFLAG are activated when counting from 1 to 0. The reset value of this register is UNKNOWN. - To generate a multi-shot timer with a period of N processor clock cycles, use a RELOAD value of N-1. For example, if the SysTick interrupt is required every 100 clock pulses, set RELOAD to 99."] + #[doc = "0xe014 - Use the SysTick Reload Value Register to specify the start value to load into the current value register when the counter reaches 0. It can be any value between 0 and 0x00FFFFFF. A start value of 0 is possible, but has no effect because the SysTick interrupt and COUNTFLAG are activated when counting from 1 to 0. The reset value of this register is UNKNOWN. To generate a multi-shot timer with a period of N processor clock cycles, use a RELOAD value of N-1. For example, if the SysTick interrupt is required every 100 clock pulses, set RELOAD to 99."] #[inline(always)] pub const fn syst_rvr(&self) -> &SYST_RVR { &self.syst_rvr @@ -63,8 +62,7 @@ impl RegisterBlock { pub const fn syst_calib(&self) -> &SYST_CALIB { &self.syst_calib } - #[doc = "0xe100 - Use the Interrupt Set-Enable Register to enable interrupts and determine which interrupts are currently enabled. - If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC never activates the interrupt, regardless of its priority."] + #[doc = "0xe100 - Use the Interrupt Set-Enable Register to enable interrupts and determine which interrupts are currently enabled. If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC never activates the interrupt, regardless of its priority."] #[inline(always)] pub const fn nvic_iser(&self) -> &NVIC_ISER { &self.nvic_iser @@ -84,9 +82,7 @@ impl RegisterBlock { pub const fn nvic_icpr(&self) -> &NVIC_ICPR { &self.nvic_icpr } - #[doc = "0xe400 - Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. - Note: Writing 1 to an NVIC_ICPR bit does not affect the active state of the corresponding interrupt. - These registers are only word-accessible"] + #[doc = "0xe400 - Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. Note: Writing 1 to an NVIC_ICPR bit does not affect the active state of the corresponding interrupt. These registers are only word-accessible"] #[inline(always)] pub const fn nvic_ipr0(&self) -> &NVIC_IPR0 { &self.nvic_ipr0 @@ -206,16 +202,14 @@ module"] pub type SYST_CSR = crate::Reg; #[doc = "Use the SysTick Control and Status Register to enable the SysTick features."] pub mod syst_csr; -#[doc = "SYST_RVR (rw) register accessor: Use the SysTick Reload Value Register to specify the start value to load into the current value register when the counter reaches 0. It can be any value between 0 and 0x00FFFFFF. A start value of 0 is possible, but has no effect because the SysTick interrupt and COUNTFLAG are activated when counting from 1 to 0. The reset value of this register is UNKNOWN. - To generate a multi-shot timer with a period of N processor clock cycles, use a RELOAD value of N-1. For example, if the SysTick interrupt is required every 100 clock pulses, set RELOAD to 99. +#[doc = "SYST_RVR (rw) register accessor: Use the SysTick Reload Value Register to specify the start value to load into the current value register when the counter reaches 0. It can be any value between 0 and 0x00FFFFFF. A start value of 0 is possible, but has no effect because the SysTick interrupt and COUNTFLAG are activated when counting from 1 to 0. The reset value of this register is UNKNOWN. To generate a multi-shot timer with a period of N processor clock cycles, use a RELOAD value of N-1. For example, if the SysTick interrupt is required every 100 clock pulses, set RELOAD to 99. You can [`read`](crate::generic::Reg::read) this register and get [`syst_rvr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`syst_rvr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@syst_rvr`] module"] pub type SYST_RVR = crate::Reg; -#[doc = "Use the SysTick Reload Value Register to specify the start value to load into the current value register when the counter reaches 0. It can be any value between 0 and 0x00FFFFFF. A start value of 0 is possible, but has no effect because the SysTick interrupt and COUNTFLAG are activated when counting from 1 to 0. The reset value of this register is UNKNOWN. - To generate a multi-shot timer with a period of N processor clock cycles, use a RELOAD value of N-1. For example, if the SysTick interrupt is required every 100 clock pulses, set RELOAD to 99."] +#[doc = "Use the SysTick Reload Value Register to specify the start value to load into the current value register when the counter reaches 0. It can be any value between 0 and 0x00FFFFFF. A start value of 0 is possible, but has no effect because the SysTick interrupt and COUNTFLAG are activated when counting from 1 to 0. The reset value of this register is UNKNOWN. To generate a multi-shot timer with a period of N processor clock cycles, use a RELOAD value of N-1. For example, if the SysTick interrupt is required every 100 clock pulses, set RELOAD to 99."] pub mod syst_rvr; #[doc = "SYST_CVR (rw) register accessor: Use the SysTick Current Value Register to find the current value in the register. The reset value of this register is UNKNOWN. @@ -226,25 +220,23 @@ module"] pub type SYST_CVR = crate::Reg; #[doc = "Use the SysTick Current Value Register to find the current value in the register. The reset value of this register is UNKNOWN."] pub mod syst_cvr; -#[doc = "SYST_CALIB (r) register accessor: Use the SysTick Calibration Value Register to enable software to scale to any required speed using divide and multiply. +#[doc = "SYST_CALIB (rw) register accessor: Use the SysTick Calibration Value Register to enable software to scale to any required speed using divide and multiply. -You can [`read`](crate::generic::Reg::read) this register and get [`syst_calib::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`syst_calib::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`syst_calib::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@syst_calib`] module"] pub type SYST_CALIB = crate::Reg; #[doc = "Use the SysTick Calibration Value Register to enable software to scale to any required speed using divide and multiply."] pub mod syst_calib; -#[doc = "NVIC_ISER (rw) register accessor: Use the Interrupt Set-Enable Register to enable interrupts and determine which interrupts are currently enabled. - If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC never activates the interrupt, regardless of its priority. +#[doc = "NVIC_ISER (rw) register accessor: Use the Interrupt Set-Enable Register to enable interrupts and determine which interrupts are currently enabled. If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC never activates the interrupt, regardless of its priority. You can [`read`](crate::generic::Reg::read) this register and get [`nvic_iser::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nvic_iser::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@nvic_iser`] module"] pub type NVIC_ISER = crate::Reg; -#[doc = "Use the Interrupt Set-Enable Register to enable interrupts and determine which interrupts are currently enabled. - If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC never activates the interrupt, regardless of its priority."] +#[doc = "Use the Interrupt Set-Enable Register to enable interrupts and determine which interrupts are currently enabled. If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC never activates the interrupt, regardless of its priority."] pub mod nvic_iser; #[doc = "NVIC_ICER (rw) register accessor: Use the Interrupt Clear-Enable Registers to disable interrupts and determine which interrupts are currently enabled. @@ -273,18 +265,14 @@ module"] pub type NVIC_ICPR = crate::Reg; #[doc = "Use the Interrupt Clear-Pending Register to clear pending interrupts and determine which interrupts are currently pending."] pub mod nvic_icpr; -#[doc = "NVIC_IPR0 (rw) register accessor: Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. - Note: Writing 1 to an NVIC_ICPR bit does not affect the active state of the corresponding interrupt. - These registers are only word-accessible +#[doc = "NVIC_IPR0 (rw) register accessor: Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. Note: Writing 1 to an NVIC_ICPR bit does not affect the active state of the corresponding interrupt. These registers are only word-accessible You can [`read`](crate::generic::Reg::read) this register and get [`nvic_ipr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nvic_ipr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@nvic_ipr0`] module"] pub type NVIC_IPR0 = crate::Reg; -#[doc = "Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. - Note: Writing 1 to an NVIC_ICPR bit does not affect the active state of the corresponding interrupt. - These registers are only word-accessible"] +#[doc = "Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. Note: Writing 1 to an NVIC_ICPR bit does not affect the active state of the corresponding interrupt. These registers are only word-accessible"] pub mod nvic_ipr0; #[doc = "NVIC_IPR1 (rw) register accessor: Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. @@ -349,9 +337,9 @@ module"] pub type NVIC_IPR7 = crate::Reg; #[doc = "Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest."] pub mod nvic_ipr7; -#[doc = "CPUID (r) register accessor: Read the CPU ID Base Register to determine: the ID number of the processor core, the version number of the processor core, the implementation details of the processor core. +#[doc = "CPUID (rw) register accessor: Read the CPU ID Base Register to determine: the ID number of the processor core, the version number of the processor core, the implementation details of the processor core. -You can [`read`](crate::generic::Reg::read) this register and get [`cpuid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`cpuid::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cpuid::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@cpuid`] module"] @@ -394,9 +382,9 @@ module"] pub type SCR = crate::Reg; #[doc = "System Control Register. Use the System Control Register for power-management functions: signal to the system when the processor can enter a low power state, control how the processor enters and exits low power states."] pub mod scr; -#[doc = "CCR (r) register accessor: The Configuration and Control Register permanently enables stack alignment and causes unaligned accesses to result in a Hard Fault. +#[doc = "CCR (rw) register accessor: The Configuration and Control Register permanently enables stack alignment and causes unaligned accesses to result in a Hard Fault. -You can [`read`](crate::generic::Reg::read) this register and get [`ccr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`ccr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@ccr`] module"] @@ -430,9 +418,9 @@ module"] pub type SHCSR = crate::Reg; #[doc = "Use the System Handler Control and State Register to determine or clear the pending status of SVCall."] pub mod shcsr; -#[doc = "MPU_TYPE (r) register accessor: Read the MPU Type Register to determine if the processor implements an MPU, and how many regions the MPU supports. +#[doc = "MPU_TYPE (rw) register accessor: Read the MPU Type Register to determine if the processor implements an MPU, and how many regions the MPU supports. -You can [`read`](crate::generic::Reg::read) this register and get [`mpu_type::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`mpu_type::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mpu_type::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@mpu_type`] module"] diff --git a/src/ppb/aircr.rs b/src/ppb/aircr.rs index 6421fe7b0..d89e9b384 100644 --- a/src/ppb/aircr.rs +++ b/src/ppb/aircr.rs @@ -10,16 +10,11 @@ pub type VECTCLRACTIVE_W<'a, REG> = crate::BitWriter<'a, REG>; pub type SYSRESETREQ_R = crate::BitReader; #[doc = "Field `SYSRESETREQ` writer - Writing 1 to this bit causes the SYSRESETREQ signal to the outer system to be asserted to request a reset. The intention is to force a large system reset of all major components except for debug. The C_HALT bit in the DHCSR is cleared as a result of the system reset requested. The debugger does not lose contact with the device."] pub type SYSRESETREQ_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `ENDIANESS` reader - Data endianness implemented: - 0 = Little-endian."] +#[doc = "Field `ENDIANESS` reader - Data endianness implemented: 0 = Little-endian."] pub type ENDIANESS_R = crate::BitReader; -#[doc = "Field `VECTKEY` reader - Register key: - Reads as Unknown - On writes, write 0x05FA to VECTKEY, otherwise the write is ignored."] +#[doc = "Field `VECTKEY` reader - Register key: Reads as Unknown On writes, write 0x05FA to VECTKEY, otherwise the write is ignored."] pub type VECTKEY_R = crate::FieldReader; -#[doc = "Field `VECTKEY` writer - Register key: - Reads as Unknown - On writes, write 0x05FA to VECTKEY, otherwise the write is ignored."] +#[doc = "Field `VECTKEY` writer - Register key: Reads as Unknown On writes, write 0x05FA to VECTKEY, otherwise the write is ignored."] pub type VECTKEY_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; impl R { #[doc = "Bit 1 - Clears all active state information for fixed and configurable exceptions. This bit: is self-clearing, can only be set by the DAP when the core is halted. When set: clears all active exception status of the processor, forces a return to Thread mode, forces an IPSR of 0. A debugger must re-initialize the stack."] @@ -32,15 +27,12 @@ impl R { pub fn sysresetreq(&self) -> SYSRESETREQ_R { SYSRESETREQ_R::new(((self.bits >> 2) & 1) != 0) } - #[doc = "Bit 15 - Data endianness implemented: - 0 = Little-endian."] + #[doc = "Bit 15 - Data endianness implemented: 0 = Little-endian."] #[inline(always)] pub fn endianess(&self) -> ENDIANESS_R { ENDIANESS_R::new(((self.bits >> 15) & 1) != 0) } - #[doc = "Bits 16:31 - Register key: - Reads as Unknown - On writes, write 0x05FA to VECTKEY, otherwise the write is ignored."] + #[doc = "Bits 16:31 - Register key: Reads as Unknown On writes, write 0x05FA to VECTKEY, otherwise the write is ignored."] #[inline(always)] pub fn vectkey(&self) -> VECTKEY_R { VECTKEY_R::new(((self.bits >> 16) & 0xffff) as u16) @@ -59,9 +51,7 @@ impl W { pub fn sysresetreq(&mut self) -> SYSRESETREQ_W { SYSRESETREQ_W::new(self, 2) } - #[doc = "Bits 16:31 - Register key: - Reads as Unknown - On writes, write 0x05FA to VECTKEY, otherwise the write is ignored."] + #[doc = "Bits 16:31 - Register key: Reads as Unknown On writes, write 0x05FA to VECTKEY, otherwise the write is ignored."] #[inline(always)] #[must_use] pub fn vectkey(&mut self) -> VECTKEY_W { diff --git a/src/ppb/ccr.rs b/src/ppb/ccr.rs index cc9c77813..663c03af9 100644 --- a/src/ppb/ccr.rs +++ b/src/ppb/ccr.rs @@ -1,5 +1,7 @@ #[doc = "Register `CCR` reader"] pub type R = crate::R; +#[doc = "Register `CCR` writer"] +pub type W = crate::W; #[doc = "Field `UNALIGN_TRP` reader - Always reads as one, indicates that all unaligned accesses generate a HardFault."] pub type UNALIGN_TRP_R = crate::BitReader; #[doc = "Field `STKALIGN` reader - Always reads as one, indicates 8-byte stack alignment on exception entry. On exception entry, the processor uses bit\\[9\\] @@ -18,15 +20,22 @@ of the stacked PSR to indicate the stack alignment. On return from the exception STKALIGN_R::new(((self.bits >> 9) & 1) != 0) } } +impl W {} #[doc = "The Configuration and Control Register permanently enables stack alignment and causes unaligned accesses to result in a Hard Fault. -You can [`read`](crate::generic::Reg::read) this register and get [`ccr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`ccr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CCR_SPEC; impl crate::RegisterSpec for CCR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`ccr::R`](R) reader structure"] impl crate::Readable for CCR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ccr::W`](W) writer structure"] +impl crate::Writable for CCR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets CCR to value 0"] impl crate::Resettable for CCR_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/ppb/cpuid.rs b/src/ppb/cpuid.rs index 639381b05..4af5b19ea 100644 --- a/src/ppb/cpuid.rs +++ b/src/ppb/cpuid.rs @@ -1,21 +1,19 @@ #[doc = "Register `CPUID` reader"] pub type R = crate::R; -#[doc = "Field `REVISION` reader - Minor revision number m in the rnpm revision status: - 0x1 = Patch 1."] +#[doc = "Register `CPUID` writer"] +pub type W = crate::W; +#[doc = "Field `REVISION` reader - Minor revision number m in the rnpm revision status: 0x1 = Patch 1."] pub type REVISION_R = crate::FieldReader; #[doc = "Field `PARTNO` reader - Number of processor within family: 0xC60 = Cortex-M0+"] pub type PARTNO_R = crate::FieldReader; -#[doc = "Field `ARCHITECTURE` reader - Constant that defines the architecture of the processor: - 0xC = ARMv6-M architecture."] +#[doc = "Field `ARCHITECTURE` reader - Constant that defines the architecture of the processor: 0xC = ARMv6-M architecture."] pub type ARCHITECTURE_R = crate::FieldReader; -#[doc = "Field `VARIANT` reader - Major revision number n in the rnpm revision status: - 0x0 = Revision 0."] +#[doc = "Field `VARIANT` reader - Major revision number n in the rnpm revision status: 0x0 = Revision 0."] pub type VARIANT_R = crate::FieldReader; #[doc = "Field `IMPLEMENTER` reader - Implementor code: 0x41 = ARM"] pub type IMPLEMENTER_R = crate::FieldReader; impl R { - #[doc = "Bits 0:3 - Minor revision number m in the rnpm revision status: - 0x1 = Patch 1."] + #[doc = "Bits 0:3 - Minor revision number m in the rnpm revision status: 0x1 = Patch 1."] #[inline(always)] pub fn revision(&self) -> REVISION_R { REVISION_R::new((self.bits & 0x0f) as u8) @@ -25,14 +23,12 @@ impl R { pub fn partno(&self) -> PARTNO_R { PARTNO_R::new(((self.bits >> 4) & 0x0fff) as u16) } - #[doc = "Bits 16:19 - Constant that defines the architecture of the processor: - 0xC = ARMv6-M architecture."] + #[doc = "Bits 16:19 - Constant that defines the architecture of the processor: 0xC = ARMv6-M architecture."] #[inline(always)] pub fn architecture(&self) -> ARCHITECTURE_R { ARCHITECTURE_R::new(((self.bits >> 16) & 0x0f) as u8) } - #[doc = "Bits 20:23 - Major revision number n in the rnpm revision status: - 0x0 = Revision 0."] + #[doc = "Bits 20:23 - Major revision number n in the rnpm revision status: 0x0 = Revision 0."] #[inline(always)] pub fn variant(&self) -> VARIANT_R { VARIANT_R::new(((self.bits >> 20) & 0x0f) as u8) @@ -43,15 +39,22 @@ impl R { IMPLEMENTER_R::new(((self.bits >> 24) & 0xff) as u8) } } +impl W {} #[doc = "Read the CPU ID Base Register to determine: the ID number of the processor core, the version number of the processor core, the implementation details of the processor core. -You can [`read`](crate::generic::Reg::read) this register and get [`cpuid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`cpuid::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cpuid::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CPUID_SPEC; impl crate::RegisterSpec for CPUID_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`cpuid::R`](R) reader structure"] impl crate::Readable for CPUID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cpuid::W`](W) writer structure"] +impl crate::Writable for CPUID_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets CPUID to value 0x410c_c601"] impl crate::Resettable for CPUID_SPEC { const RESET_VALUE: u32 = 0x410c_c601; diff --git a/src/ppb/icsr.rs b/src/ppb/icsr.rs index 962b96baa..e661300d5 100644 --- a/src/ppb/icsr.rs +++ b/src/ppb/icsr.rs @@ -10,87 +10,25 @@ pub type VECTPENDING_R = crate::FieldReader; pub type ISRPENDING_R = crate::BitReader; #[doc = "Field `ISRPREEMPT` reader - The system can only access this bit when the core is halted. It indicates that a pending interrupt is to be taken in the next running cycle. If C_MASKINTS is clear in the Debug Halting Control and Status Register, the interrupt is serviced."] pub type ISRPREEMPT_R = crate::BitReader; -#[doc = "Field `PENDSTCLR` reader - SysTick exception clear-pending bit. - Write: - 0 = No effect. - 1 = Removes the pending state from the SysTick exception. - This bit is WO. On a register read its value is Unknown."] +#[doc = "Field `PENDSTCLR` reader - SysTick exception clear-pending bit. Write: 0 = No effect. 1 = Removes the pending state from the SysTick exception. This bit is WO. On a register read its value is Unknown."] pub type PENDSTCLR_R = crate::BitReader; -#[doc = "Field `PENDSTCLR` writer - SysTick exception clear-pending bit. - Write: - 0 = No effect. - 1 = Removes the pending state from the SysTick exception. - This bit is WO. On a register read its value is Unknown."] +#[doc = "Field `PENDSTCLR` writer - SysTick exception clear-pending bit. Write: 0 = No effect. 1 = Removes the pending state from the SysTick exception. This bit is WO. On a register read its value is Unknown."] pub type PENDSTCLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `PENDSTSET` reader - SysTick exception set-pending bit. - Write: - 0 = No effect. - 1 = Changes SysTick exception state to pending. - Read: - 0 = SysTick exception is not pending. - 1 = SysTick exception is pending."] +#[doc = "Field `PENDSTSET` reader - SysTick exception set-pending bit. Write: 0 = No effect. 1 = Changes SysTick exception state to pending. Read: 0 = SysTick exception is not pending. 1 = SysTick exception is pending."] pub type PENDSTSET_R = crate::BitReader; -#[doc = "Field `PENDSTSET` writer - SysTick exception set-pending bit. - Write: - 0 = No effect. - 1 = Changes SysTick exception state to pending. - Read: - 0 = SysTick exception is not pending. - 1 = SysTick exception is pending."] +#[doc = "Field `PENDSTSET` writer - SysTick exception set-pending bit. Write: 0 = No effect. 1 = Changes SysTick exception state to pending. Read: 0 = SysTick exception is not pending. 1 = SysTick exception is pending."] pub type PENDSTSET_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `PENDSVCLR` reader - PendSV clear-pending bit. - Write: - 0 = No effect. - 1 = Removes the pending state from the PendSV exception."] +#[doc = "Field `PENDSVCLR` reader - PendSV clear-pending bit. Write: 0 = No effect. 1 = Removes the pending state from the PendSV exception."] pub type PENDSVCLR_R = crate::BitReader; -#[doc = "Field `PENDSVCLR` writer - PendSV clear-pending bit. - Write: - 0 = No effect. - 1 = Removes the pending state from the PendSV exception."] +#[doc = "Field `PENDSVCLR` writer - PendSV clear-pending bit. Write: 0 = No effect. 1 = Removes the pending state from the PendSV exception."] pub type PENDSVCLR_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `PENDSVSET` reader - PendSV set-pending bit. - Write: - 0 = No effect. - 1 = Changes PendSV exception state to pending. - Read: - 0 = PendSV exception is not pending. - 1 = PendSV exception is pending. - Writing 1 to this bit is the only way to set the PendSV exception state to pending."] +#[doc = "Field `PENDSVSET` reader - PendSV set-pending bit. Write: 0 = No effect. 1 = Changes PendSV exception state to pending. Read: 0 = PendSV exception is not pending. 1 = PendSV exception is pending. Writing 1 to this bit is the only way to set the PendSV exception state to pending."] pub type PENDSVSET_R = crate::BitReader; -#[doc = "Field `PENDSVSET` writer - PendSV set-pending bit. - Write: - 0 = No effect. - 1 = Changes PendSV exception state to pending. - Read: - 0 = PendSV exception is not pending. - 1 = PendSV exception is pending. - Writing 1 to this bit is the only way to set the PendSV exception state to pending."] +#[doc = "Field `PENDSVSET` writer - PendSV set-pending bit. Write: 0 = No effect. 1 = Changes PendSV exception state to pending. Read: 0 = PendSV exception is not pending. 1 = PendSV exception is pending. Writing 1 to this bit is the only way to set the PendSV exception state to pending."] pub type PENDSVSET_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `NMIPENDSET` reader - Setting this bit will activate an NMI. Since NMI is the highest priority exception, it will activate as soon as it is registered. - NMI set-pending bit. - Write: - 0 = No effect. - 1 = Changes NMI exception state to pending. - Read: - 0 = NMI exception is not pending. - 1 = NMI exception is pending. - Because NMI is the highest-priority exception, normally the processor enters the NMI - exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears - this bit to 0. This means a read of this bit by the NMI exception handler returns 1 only if the - NMI signal is reasserted while the processor is executing that handler."] +#[doc = "Field `NMIPENDSET` reader - Setting this bit will activate an NMI. Since NMI is the highest priority exception, it will activate as soon as it is registered. NMI set-pending bit. Write: 0 = No effect. 1 = Changes NMI exception state to pending. Read: 0 = NMI exception is not pending. 1 = NMI exception is pending. Because NMI is the highest-priority exception, normally the processor enters the NMI exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears this bit to 0. This means a read of this bit by the NMI exception handler returns 1 only if the NMI signal is reasserted while the processor is executing that handler."] pub type NMIPENDSET_R = crate::BitReader; -#[doc = "Field `NMIPENDSET` writer - Setting this bit will activate an NMI. Since NMI is the highest priority exception, it will activate as soon as it is registered. - NMI set-pending bit. - Write: - 0 = No effect. - 1 = Changes NMI exception state to pending. - Read: - 0 = NMI exception is not pending. - 1 = NMI exception is pending. - Because NMI is the highest-priority exception, normally the processor enters the NMI - exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears - this bit to 0. This means a read of this bit by the NMI exception handler returns 1 only if the - NMI signal is reasserted while the processor is executing that handler."] +#[doc = "Field `NMIPENDSET` writer - Setting this bit will activate an NMI. Since NMI is the highest priority exception, it will activate as soon as it is registered. NMI set-pending bit. Write: 0 = No effect. 1 = Changes NMI exception state to pending. Read: 0 = NMI exception is not pending. 1 = NMI exception is pending. Because NMI is the highest-priority exception, normally the processor enters the NMI exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears this bit to 0. This means a read of this bit by the NMI exception handler returns 1 only if the NMI signal is reasserted while the processor is executing that handler."] pub type NMIPENDSET_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bits 0:8 - Active exception number field. Reset clears the VECTACTIVE field."] @@ -113,120 +51,58 @@ impl R { pub fn isrpreempt(&self) -> ISRPREEMPT_R { ISRPREEMPT_R::new(((self.bits >> 23) & 1) != 0) } - #[doc = "Bit 25 - SysTick exception clear-pending bit. - Write: - 0 = No effect. - 1 = Removes the pending state from the SysTick exception. - This bit is WO. On a register read its value is Unknown."] + #[doc = "Bit 25 - SysTick exception clear-pending bit. Write: 0 = No effect. 1 = Removes the pending state from the SysTick exception. This bit is WO. On a register read its value is Unknown."] #[inline(always)] pub fn pendstclr(&self) -> PENDSTCLR_R { PENDSTCLR_R::new(((self.bits >> 25) & 1) != 0) } - #[doc = "Bit 26 - SysTick exception set-pending bit. - Write: - 0 = No effect. - 1 = Changes SysTick exception state to pending. - Read: - 0 = SysTick exception is not pending. - 1 = SysTick exception is pending."] + #[doc = "Bit 26 - SysTick exception set-pending bit. Write: 0 = No effect. 1 = Changes SysTick exception state to pending. Read: 0 = SysTick exception is not pending. 1 = SysTick exception is pending."] #[inline(always)] pub fn pendstset(&self) -> PENDSTSET_R { PENDSTSET_R::new(((self.bits >> 26) & 1) != 0) } - #[doc = "Bit 27 - PendSV clear-pending bit. - Write: - 0 = No effect. - 1 = Removes the pending state from the PendSV exception."] + #[doc = "Bit 27 - PendSV clear-pending bit. Write: 0 = No effect. 1 = Removes the pending state from the PendSV exception."] #[inline(always)] pub fn pendsvclr(&self) -> PENDSVCLR_R { PENDSVCLR_R::new(((self.bits >> 27) & 1) != 0) } - #[doc = "Bit 28 - PendSV set-pending bit. - Write: - 0 = No effect. - 1 = Changes PendSV exception state to pending. - Read: - 0 = PendSV exception is not pending. - 1 = PendSV exception is pending. - Writing 1 to this bit is the only way to set the PendSV exception state to pending."] + #[doc = "Bit 28 - PendSV set-pending bit. Write: 0 = No effect. 1 = Changes PendSV exception state to pending. Read: 0 = PendSV exception is not pending. 1 = PendSV exception is pending. Writing 1 to this bit is the only way to set the PendSV exception state to pending."] #[inline(always)] pub fn pendsvset(&self) -> PENDSVSET_R { PENDSVSET_R::new(((self.bits >> 28) & 1) != 0) } - #[doc = "Bit 31 - Setting this bit will activate an NMI. Since NMI is the highest priority exception, it will activate as soon as it is registered. - NMI set-pending bit. - Write: - 0 = No effect. - 1 = Changes NMI exception state to pending. - Read: - 0 = NMI exception is not pending. - 1 = NMI exception is pending. - Because NMI is the highest-priority exception, normally the processor enters the NMI - exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears - this bit to 0. This means a read of this bit by the NMI exception handler returns 1 only if the - NMI signal is reasserted while the processor is executing that handler."] + #[doc = "Bit 31 - Setting this bit will activate an NMI. Since NMI is the highest priority exception, it will activate as soon as it is registered. NMI set-pending bit. Write: 0 = No effect. 1 = Changes NMI exception state to pending. Read: 0 = NMI exception is not pending. 1 = NMI exception is pending. Because NMI is the highest-priority exception, normally the processor enters the NMI exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears this bit to 0. This means a read of this bit by the NMI exception handler returns 1 only if the NMI signal is reasserted while the processor is executing that handler."] #[inline(always)] pub fn nmipendset(&self) -> NMIPENDSET_R { NMIPENDSET_R::new(((self.bits >> 31) & 1) != 0) } } impl W { - #[doc = "Bit 25 - SysTick exception clear-pending bit. - Write: - 0 = No effect. - 1 = Removes the pending state from the SysTick exception. - This bit is WO. On a register read its value is Unknown."] + #[doc = "Bit 25 - SysTick exception clear-pending bit. Write: 0 = No effect. 1 = Removes the pending state from the SysTick exception. This bit is WO. On a register read its value is Unknown."] #[inline(always)] #[must_use] pub fn pendstclr(&mut self) -> PENDSTCLR_W { PENDSTCLR_W::new(self, 25) } - #[doc = "Bit 26 - SysTick exception set-pending bit. - Write: - 0 = No effect. - 1 = Changes SysTick exception state to pending. - Read: - 0 = SysTick exception is not pending. - 1 = SysTick exception is pending."] + #[doc = "Bit 26 - SysTick exception set-pending bit. Write: 0 = No effect. 1 = Changes SysTick exception state to pending. Read: 0 = SysTick exception is not pending. 1 = SysTick exception is pending."] #[inline(always)] #[must_use] pub fn pendstset(&mut self) -> PENDSTSET_W { PENDSTSET_W::new(self, 26) } - #[doc = "Bit 27 - PendSV clear-pending bit. - Write: - 0 = No effect. - 1 = Removes the pending state from the PendSV exception."] + #[doc = "Bit 27 - PendSV clear-pending bit. Write: 0 = No effect. 1 = Removes the pending state from the PendSV exception."] #[inline(always)] #[must_use] pub fn pendsvclr(&mut self) -> PENDSVCLR_W { PENDSVCLR_W::new(self, 27) } - #[doc = "Bit 28 - PendSV set-pending bit. - Write: - 0 = No effect. - 1 = Changes PendSV exception state to pending. - Read: - 0 = PendSV exception is not pending. - 1 = PendSV exception is pending. - Writing 1 to this bit is the only way to set the PendSV exception state to pending."] + #[doc = "Bit 28 - PendSV set-pending bit. Write: 0 = No effect. 1 = Changes PendSV exception state to pending. Read: 0 = PendSV exception is not pending. 1 = PendSV exception is pending. Writing 1 to this bit is the only way to set the PendSV exception state to pending."] #[inline(always)] #[must_use] pub fn pendsvset(&mut self) -> PENDSVSET_W { PENDSVSET_W::new(self, 28) } - #[doc = "Bit 31 - Setting this bit will activate an NMI. Since NMI is the highest priority exception, it will activate as soon as it is registered. - NMI set-pending bit. - Write: - 0 = No effect. - 1 = Changes NMI exception state to pending. - Read: - 0 = NMI exception is not pending. - 1 = NMI exception is pending. - Because NMI is the highest-priority exception, normally the processor enters the NMI - exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears - this bit to 0. This means a read of this bit by the NMI exception handler returns 1 only if the - NMI signal is reasserted while the processor is executing that handler."] + #[doc = "Bit 31 - Setting this bit will activate an NMI. Since NMI is the highest priority exception, it will activate as soon as it is registered. NMI set-pending bit. Write: 0 = No effect. 1 = Changes NMI exception state to pending. Read: 0 = NMI exception is not pending. 1 = NMI exception is pending. Because NMI is the highest-priority exception, normally the processor enters the NMI exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears this bit to 0. This means a read of this bit by the NMI exception handler returns 1 only if the NMI signal is reasserted while the processor is executing that handler."] #[inline(always)] #[must_use] pub fn nmipendset(&mut self) -> NMIPENDSET_W { diff --git a/src/ppb/mpu_ctrl.rs b/src/ppb/mpu_ctrl.rs index cf7f7d414..f37c3178f 100644 --- a/src/ppb/mpu_ctrl.rs +++ b/src/ppb/mpu_ctrl.rs @@ -2,85 +2,49 @@ pub type R = crate::R; #[doc = "Register `MPU_CTRL` writer"] pub type W = crate::W; -#[doc = "Field `ENABLE` reader - Enables the MPU. If the MPU is disabled, privileged and unprivileged accesses use the default memory map. - 0 = MPU disabled. - 1 = MPU enabled."] +#[doc = "Field `ENABLE` reader - Enables the MPU. If the MPU is disabled, privileged and unprivileged accesses use the default memory map. 0 = MPU disabled. 1 = MPU enabled."] pub type ENABLE_R = crate::BitReader; -#[doc = "Field `ENABLE` writer - Enables the MPU. If the MPU is disabled, privileged and unprivileged accesses use the default memory map. - 0 = MPU disabled. - 1 = MPU enabled."] +#[doc = "Field `ENABLE` writer - Enables the MPU. If the MPU is disabled, privileged and unprivileged accesses use the default memory map. 0 = MPU disabled. 1 = MPU enabled."] pub type ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `HFNMIENA` reader - Controls the use of the MPU for HardFaults and NMIs. Setting this bit when ENABLE is clear results in UNPREDICTABLE behaviour. - When the MPU is enabled: - 0 = MPU is disabled during HardFault and NMI handlers, regardless of the value of the ENABLE bit. - 1 = the MPU is enabled during HardFault and NMI handlers."] +#[doc = "Field `HFNMIENA` reader - Controls the use of the MPU for HardFaults and NMIs. Setting this bit when ENABLE is clear results in UNPREDICTABLE behaviour. When the MPU is enabled: 0 = MPU is disabled during HardFault and NMI handlers, regardless of the value of the ENABLE bit. 1 = the MPU is enabled during HardFault and NMI handlers."] pub type HFNMIENA_R = crate::BitReader; -#[doc = "Field `HFNMIENA` writer - Controls the use of the MPU for HardFaults and NMIs. Setting this bit when ENABLE is clear results in UNPREDICTABLE behaviour. - When the MPU is enabled: - 0 = MPU is disabled during HardFault and NMI handlers, regardless of the value of the ENABLE bit. - 1 = the MPU is enabled during HardFault and NMI handlers."] +#[doc = "Field `HFNMIENA` writer - Controls the use of the MPU for HardFaults and NMIs. Setting this bit when ENABLE is clear results in UNPREDICTABLE behaviour. When the MPU is enabled: 0 = MPU is disabled during HardFault and NMI handlers, regardless of the value of the ENABLE bit. 1 = the MPU is enabled during HardFault and NMI handlers."] pub type HFNMIENA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `PRIVDEFENA` reader - Controls whether the default memory map is enabled as a background region for privileged accesses. This bit is ignored when ENABLE is clear. - 0 = If the MPU is enabled, disables use of the default memory map. Any memory access to a location not - covered by any enabled region causes a fault. - 1 = If the MPU is enabled, enables use of the default memory map as a background region for privileged software accesses. - When enabled, the background region acts as if it is region number -1. Any region that is defined and enabled has priority over this default map."] +#[doc = "Field `PRIVDEFENA` reader - Controls whether the default memory map is enabled as a background region for privileged accesses. This bit is ignored when ENABLE is clear. 0 = If the MPU is enabled, disables use of the default memory map. Any memory access to a location not covered by any enabled region causes a fault. 1 = If the MPU is enabled, enables use of the default memory map as a background region for privileged software accesses. When enabled, the background region acts as if it is region number -1. Any region that is defined and enabled has priority over this default map."] pub type PRIVDEFENA_R = crate::BitReader; -#[doc = "Field `PRIVDEFENA` writer - Controls whether the default memory map is enabled as a background region for privileged accesses. This bit is ignored when ENABLE is clear. - 0 = If the MPU is enabled, disables use of the default memory map. Any memory access to a location not - covered by any enabled region causes a fault. - 1 = If the MPU is enabled, enables use of the default memory map as a background region for privileged software accesses. - When enabled, the background region acts as if it is region number -1. Any region that is defined and enabled has priority over this default map."] +#[doc = "Field `PRIVDEFENA` writer - Controls whether the default memory map is enabled as a background region for privileged accesses. This bit is ignored when ENABLE is clear. 0 = If the MPU is enabled, disables use of the default memory map. Any memory access to a location not covered by any enabled region causes a fault. 1 = If the MPU is enabled, enables use of the default memory map as a background region for privileged software accesses. When enabled, the background region acts as if it is region number -1. Any region that is defined and enabled has priority over this default map."] pub type PRIVDEFENA_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { - #[doc = "Bit 0 - Enables the MPU. If the MPU is disabled, privileged and unprivileged accesses use the default memory map. - 0 = MPU disabled. - 1 = MPU enabled."] + #[doc = "Bit 0 - Enables the MPU. If the MPU is disabled, privileged and unprivileged accesses use the default memory map. 0 = MPU disabled. 1 = MPU enabled."] #[inline(always)] pub fn enable(&self) -> ENABLE_R { ENABLE_R::new((self.bits & 1) != 0) } - #[doc = "Bit 1 - Controls the use of the MPU for HardFaults and NMIs. Setting this bit when ENABLE is clear results in UNPREDICTABLE behaviour. - When the MPU is enabled: - 0 = MPU is disabled during HardFault and NMI handlers, regardless of the value of the ENABLE bit. - 1 = the MPU is enabled during HardFault and NMI handlers."] + #[doc = "Bit 1 - Controls the use of the MPU for HardFaults and NMIs. Setting this bit when ENABLE is clear results in UNPREDICTABLE behaviour. When the MPU is enabled: 0 = MPU is disabled during HardFault and NMI handlers, regardless of the value of the ENABLE bit. 1 = the MPU is enabled during HardFault and NMI handlers."] #[inline(always)] pub fn hfnmiena(&self) -> HFNMIENA_R { HFNMIENA_R::new(((self.bits >> 1) & 1) != 0) } - #[doc = "Bit 2 - Controls whether the default memory map is enabled as a background region for privileged accesses. This bit is ignored when ENABLE is clear. - 0 = If the MPU is enabled, disables use of the default memory map. Any memory access to a location not - covered by any enabled region causes a fault. - 1 = If the MPU is enabled, enables use of the default memory map as a background region for privileged software accesses. - When enabled, the background region acts as if it is region number -1. Any region that is defined and enabled has priority over this default map."] + #[doc = "Bit 2 - Controls whether the default memory map is enabled as a background region for privileged accesses. This bit is ignored when ENABLE is clear. 0 = If the MPU is enabled, disables use of the default memory map. Any memory access to a location not covered by any enabled region causes a fault. 1 = If the MPU is enabled, enables use of the default memory map as a background region for privileged software accesses. When enabled, the background region acts as if it is region number -1. Any region that is defined and enabled has priority over this default map."] #[inline(always)] pub fn privdefena(&self) -> PRIVDEFENA_R { PRIVDEFENA_R::new(((self.bits >> 2) & 1) != 0) } } impl W { - #[doc = "Bit 0 - Enables the MPU. If the MPU is disabled, privileged and unprivileged accesses use the default memory map. - 0 = MPU disabled. - 1 = MPU enabled."] + #[doc = "Bit 0 - Enables the MPU. If the MPU is disabled, privileged and unprivileged accesses use the default memory map. 0 = MPU disabled. 1 = MPU enabled."] #[inline(always)] #[must_use] pub fn enable(&mut self) -> ENABLE_W { ENABLE_W::new(self, 0) } - #[doc = "Bit 1 - Controls the use of the MPU for HardFaults and NMIs. Setting this bit when ENABLE is clear results in UNPREDICTABLE behaviour. - When the MPU is enabled: - 0 = MPU is disabled during HardFault and NMI handlers, regardless of the value of the ENABLE bit. - 1 = the MPU is enabled during HardFault and NMI handlers."] + #[doc = "Bit 1 - Controls the use of the MPU for HardFaults and NMIs. Setting this bit when ENABLE is clear results in UNPREDICTABLE behaviour. When the MPU is enabled: 0 = MPU is disabled during HardFault and NMI handlers, regardless of the value of the ENABLE bit. 1 = the MPU is enabled during HardFault and NMI handlers."] #[inline(always)] #[must_use] pub fn hfnmiena(&mut self) -> HFNMIENA_W { HFNMIENA_W::new(self, 1) } - #[doc = "Bit 2 - Controls whether the default memory map is enabled as a background region for privileged accesses. This bit is ignored when ENABLE is clear. - 0 = If the MPU is enabled, disables use of the default memory map. Any memory access to a location not - covered by any enabled region causes a fault. - 1 = If the MPU is enabled, enables use of the default memory map as a background region for privileged software accesses. - When enabled, the background region acts as if it is region number -1. Any region that is defined and enabled has priority over this default map."] + #[doc = "Bit 2 - Controls whether the default memory map is enabled as a background region for privileged accesses. This bit is ignored when ENABLE is clear. 0 = If the MPU is enabled, disables use of the default memory map. Any memory access to a location not covered by any enabled region causes a fault. 1 = If the MPU is enabled, enables use of the default memory map as a background region for privileged software accesses. When enabled, the background region acts as if it is region number -1. Any region that is defined and enabled has priority over this default map."] #[inline(always)] #[must_use] pub fn privdefena(&mut self) -> PRIVDEFENA_W { diff --git a/src/ppb/mpu_rasr.rs b/src/ppb/mpu_rasr.rs index 0147611b6..1f1db1ff8 100644 --- a/src/ppb/mpu_rasr.rs +++ b/src/ppb/mpu_rasr.rs @@ -14,23 +14,9 @@ pub type SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; pub type SRD_R = crate::FieldReader; #[doc = "Field `SRD` writer - Subregion Disable. For regions of 256 bytes or larger, each bit of this field controls whether one of the eight equal subregions is enabled."] pub type SRD_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `ATTRS` reader - The MPU Region Attribute field. Use to define the region attribute control. - 28 = XN: Instruction access disable bit: - 0 = Instruction fetches enabled. - 1 = Instruction fetches disabled. - 26:24 = AP: Access permission field - 18 = S: Shareable bit - 17 = C: Cacheable bit - 16 = B: Bufferable bit"] +#[doc = "Field `ATTRS` reader - The MPU Region Attribute field. Use to define the region attribute control. 28 = XN: Instruction access disable bit: 0 = Instruction fetches enabled. 1 = Instruction fetches disabled. 26:24 = AP: Access permission field 18 = S: Shareable bit 17 = C: Cacheable bit 16 = B: Bufferable bit"] pub type ATTRS_R = crate::FieldReader; -#[doc = "Field `ATTRS` writer - The MPU Region Attribute field. Use to define the region attribute control. - 28 = XN: Instruction access disable bit: - 0 = Instruction fetches enabled. - 1 = Instruction fetches disabled. - 26:24 = AP: Access permission field - 18 = S: Shareable bit - 17 = C: Cacheable bit - 16 = B: Bufferable bit"] +#[doc = "Field `ATTRS` writer - The MPU Region Attribute field. Use to define the region attribute control. 28 = XN: Instruction access disable bit: 0 = Instruction fetches enabled. 1 = Instruction fetches disabled. 26:24 = AP: Access permission field 18 = S: Shareable bit 17 = C: Cacheable bit 16 = B: Bufferable bit"] pub type ATTRS_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; impl R { #[doc = "Bit 0 - Enables the region."] @@ -48,14 +34,7 @@ impl R { pub fn srd(&self) -> SRD_R { SRD_R::new(((self.bits >> 8) & 0xff) as u8) } - #[doc = "Bits 16:31 - The MPU Region Attribute field. Use to define the region attribute control. - 28 = XN: Instruction access disable bit: - 0 = Instruction fetches enabled. - 1 = Instruction fetches disabled. - 26:24 = AP: Access permission field - 18 = S: Shareable bit - 17 = C: Cacheable bit - 16 = B: Bufferable bit"] + #[doc = "Bits 16:31 - The MPU Region Attribute field. Use to define the region attribute control. 28 = XN: Instruction access disable bit: 0 = Instruction fetches enabled. 1 = Instruction fetches disabled. 26:24 = AP: Access permission field 18 = S: Shareable bit 17 = C: Cacheable bit 16 = B: Bufferable bit"] #[inline(always)] pub fn attrs(&self) -> ATTRS_R { ATTRS_R::new(((self.bits >> 16) & 0xffff) as u16) @@ -80,14 +59,7 @@ impl W { pub fn srd(&mut self) -> SRD_W { SRD_W::new(self, 8) } - #[doc = "Bits 16:31 - The MPU Region Attribute field. Use to define the region attribute control. - 28 = XN: Instruction access disable bit: - 0 = Instruction fetches enabled. - 1 = Instruction fetches disabled. - 26:24 = AP: Access permission field - 18 = S: Shareable bit - 17 = C: Cacheable bit - 16 = B: Bufferable bit"] + #[doc = "Bits 16:31 - The MPU Region Attribute field. Use to define the region attribute control. 28 = XN: Instruction access disable bit: 0 = Instruction fetches enabled. 1 = Instruction fetches disabled. 26:24 = AP: Access permission field 18 = S: Shareable bit 17 = C: Cacheable bit 16 = B: Bufferable bit"] #[inline(always)] #[must_use] pub fn attrs(&mut self) -> ATTRS_W { diff --git a/src/ppb/mpu_rbar.rs b/src/ppb/mpu_rbar.rs index b59f5b3ac..af7d9f2d6 100644 --- a/src/ppb/mpu_rbar.rs +++ b/src/ppb/mpu_rbar.rs @@ -8,25 +8,9 @@ pub type REGION_R = crate::FieldReader; #[doc = "Field `REGION` writer - On writes, specifies the number of the region whose base address to update provided VALID is set written as 1. On reads, returns bits \\[3:0\\] of MPU_RNR."] pub type REGION_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `VALID` reader - On writes, indicates whether the write must update the base address of the region identified by the REGION field, updating the MPU_RNR to indicate this new region. - Write: - 0 = MPU_RNR not changed, and the processor: - Updates the base address for the region specified in the MPU_RNR. - Ignores the value of the REGION field. - 1 = The processor: - Updates the value of the MPU_RNR to the value of the REGION field. - Updates the base address for the region specified in the REGION field. - Always reads as zero."] +#[doc = "Field `VALID` reader - On writes, indicates whether the write must update the base address of the region identified by the REGION field, updating the MPU_RNR to indicate this new region. Write: 0 = MPU_RNR not changed, and the processor: Updates the base address for the region specified in the MPU_RNR. Ignores the value of the REGION field. 1 = The processor: Updates the value of the MPU_RNR to the value of the REGION field. Updates the base address for the region specified in the REGION field. Always reads as zero."] pub type VALID_R = crate::BitReader; -#[doc = "Field `VALID` writer - On writes, indicates whether the write must update the base address of the region identified by the REGION field, updating the MPU_RNR to indicate this new region. - Write: - 0 = MPU_RNR not changed, and the processor: - Updates the base address for the region specified in the MPU_RNR. - Ignores the value of the REGION field. - 1 = The processor: - Updates the value of the MPU_RNR to the value of the REGION field. - Updates the base address for the region specified in the REGION field. - Always reads as zero."] +#[doc = "Field `VALID` writer - On writes, indicates whether the write must update the base address of the region identified by the REGION field, updating the MPU_RNR to indicate this new region. Write: 0 = MPU_RNR not changed, and the processor: Updates the base address for the region specified in the MPU_RNR. Ignores the value of the REGION field. 1 = The processor: Updates the value of the MPU_RNR to the value of the REGION field. Updates the base address for the region specified in the REGION field. Always reads as zero."] pub type VALID_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ADDR` reader - Base address of the region."] pub type ADDR_R = crate::FieldReader; @@ -39,15 +23,7 @@ of MPU_RNR."] pub fn region(&self) -> REGION_R { REGION_R::new((self.bits & 0x0f) as u8) } - #[doc = "Bit 4 - On writes, indicates whether the write must update the base address of the region identified by the REGION field, updating the MPU_RNR to indicate this new region. - Write: - 0 = MPU_RNR not changed, and the processor: - Updates the base address for the region specified in the MPU_RNR. - Ignores the value of the REGION field. - 1 = The processor: - Updates the value of the MPU_RNR to the value of the REGION field. - Updates the base address for the region specified in the REGION field. - Always reads as zero."] + #[doc = "Bit 4 - On writes, indicates whether the write must update the base address of the region identified by the REGION field, updating the MPU_RNR to indicate this new region. Write: 0 = MPU_RNR not changed, and the processor: Updates the base address for the region specified in the MPU_RNR. Ignores the value of the REGION field. 1 = The processor: Updates the value of the MPU_RNR to the value of the REGION field. Updates the base address for the region specified in the REGION field. Always reads as zero."] #[inline(always)] pub fn valid(&self) -> VALID_R { VALID_R::new(((self.bits >> 4) & 1) != 0) @@ -66,15 +42,7 @@ of MPU_RNR."] pub fn region(&mut self) -> REGION_W { REGION_W::new(self, 0) } - #[doc = "Bit 4 - On writes, indicates whether the write must update the base address of the region identified by the REGION field, updating the MPU_RNR to indicate this new region. - Write: - 0 = MPU_RNR not changed, and the processor: - Updates the base address for the region specified in the MPU_RNR. - Ignores the value of the REGION field. - 1 = The processor: - Updates the value of the MPU_RNR to the value of the REGION field. - Updates the base address for the region specified in the REGION field. - Always reads as zero."] + #[doc = "Bit 4 - On writes, indicates whether the write must update the base address of the region identified by the REGION field, updating the MPU_RNR to indicate this new region. Write: 0 = MPU_RNR not changed, and the processor: Updates the base address for the region specified in the MPU_RNR. Ignores the value of the REGION field. 1 = The processor: Updates the value of the MPU_RNR to the value of the REGION field. Updates the base address for the region specified in the REGION field. Always reads as zero."] #[inline(always)] #[must_use] pub fn valid(&mut self) -> VALID_W { diff --git a/src/ppb/mpu_rnr.rs b/src/ppb/mpu_rnr.rs index d1e57574f..56c41e353 100644 --- a/src/ppb/mpu_rnr.rs +++ b/src/ppb/mpu_rnr.rs @@ -2,23 +2,19 @@ pub type R = crate::R; #[doc = "Register `MPU_RNR` writer"] pub type W = crate::W; -#[doc = "Field `REGION` reader - Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers. - The MPU supports 8 memory regions, so the permitted values of this field are 0-7."] +#[doc = "Field `REGION` reader - Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers. The MPU supports 8 memory regions, so the permitted values of this field are 0-7."] pub type REGION_R = crate::FieldReader; -#[doc = "Field `REGION` writer - Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers. - The MPU supports 8 memory regions, so the permitted values of this field are 0-7."] +#[doc = "Field `REGION` writer - Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers. The MPU supports 8 memory regions, so the permitted values of this field are 0-7."] pub type REGION_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; impl R { - #[doc = "Bits 0:3 - Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers. - The MPU supports 8 memory regions, so the permitted values of this field are 0-7."] + #[doc = "Bits 0:3 - Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers. The MPU supports 8 memory regions, so the permitted values of this field are 0-7."] #[inline(always)] pub fn region(&self) -> REGION_R { REGION_R::new((self.bits & 0x0f) as u8) } } impl W { - #[doc = "Bits 0:3 - Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers. - The MPU supports 8 memory regions, so the permitted values of this field are 0-7."] + #[doc = "Bits 0:3 - Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers. The MPU supports 8 memory regions, so the permitted values of this field are 0-7."] #[inline(always)] #[must_use] pub fn region(&mut self) -> REGION_W { diff --git a/src/ppb/mpu_type.rs b/src/ppb/mpu_type.rs index ff303fbca..f1e90c096 100644 --- a/src/ppb/mpu_type.rs +++ b/src/ppb/mpu_type.rs @@ -1,5 +1,7 @@ #[doc = "Register `MPU_TYPE` reader"] pub type R = crate::R; +#[doc = "Register `MPU_TYPE` writer"] +pub type W = crate::W; #[doc = "Field `SEPARATE` reader - Indicates support for separate instruction and data address maps. Reads as 0 as ARMv6-M only supports a unified MPU."] pub type SEPARATE_R = crate::BitReader; #[doc = "Field `DREGION` reader - Number of regions supported by the MPU."] @@ -23,15 +25,22 @@ impl R { IREGION_R::new(((self.bits >> 16) & 0xff) as u8) } } +impl W {} #[doc = "Read the MPU Type Register to determine if the processor implements an MPU, and how many regions the MPU supports. -You can [`read`](crate::generic::Reg::read) this register and get [`mpu_type::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`mpu_type::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mpu_type::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MPU_TYPE_SPEC; impl crate::RegisterSpec for MPU_TYPE_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`mpu_type::R`](R) reader structure"] impl crate::Readable for MPU_TYPE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mpu_type::W`](W) writer structure"] +impl crate::Writable for MPU_TYPE_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets MPU_TYPE to value 0x0800"] impl crate::Resettable for MPU_TYPE_SPEC { const RESET_VALUE: u32 = 0x0800; diff --git a/src/ppb/nvic_icer.rs b/src/ppb/nvic_icer.rs index 492c9a4f2..845836163 100644 --- a/src/ppb/nvic_icer.rs +++ b/src/ppb/nvic_icer.rs @@ -2,43 +2,19 @@ pub type R = crate::R; #[doc = "Register `NVIC_ICER` writer"] pub type W = crate::W; -#[doc = "Field `CLRENA` reader - Interrupt clear-enable bits. - Write: - 0 = No effect. - 1 = Disable interrupt. - Read: - 0 = Interrupt disabled. - 1 = Interrupt enabled."] +#[doc = "Field `CLRENA` reader - Interrupt clear-enable bits. Write: 0 = No effect. 1 = Disable interrupt. Read: 0 = Interrupt disabled. 1 = Interrupt enabled."] pub type CLRENA_R = crate::FieldReader; -#[doc = "Field `CLRENA` writer - Interrupt clear-enable bits. - Write: - 0 = No effect. - 1 = Disable interrupt. - Read: - 0 = Interrupt disabled. - 1 = Interrupt enabled."] +#[doc = "Field `CLRENA` writer - Interrupt clear-enable bits. Write: 0 = No effect. 1 = Disable interrupt. Read: 0 = Interrupt disabled. 1 = Interrupt enabled."] pub type CLRENA_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { - #[doc = "Bits 0:31 - Interrupt clear-enable bits. - Write: - 0 = No effect. - 1 = Disable interrupt. - Read: - 0 = Interrupt disabled. - 1 = Interrupt enabled."] + #[doc = "Bits 0:31 - Interrupt clear-enable bits. Write: 0 = No effect. 1 = Disable interrupt. Read: 0 = Interrupt disabled. 1 = Interrupt enabled."] #[inline(always)] pub fn clrena(&self) -> CLRENA_R { CLRENA_R::new(self.bits) } } impl W { - #[doc = "Bits 0:31 - Interrupt clear-enable bits. - Write: - 0 = No effect. - 1 = Disable interrupt. - Read: - 0 = Interrupt disabled. - 1 = Interrupt enabled."] + #[doc = "Bits 0:31 - Interrupt clear-enable bits. Write: 0 = No effect. 1 = Disable interrupt. Read: 0 = Interrupt disabled. 1 = Interrupt enabled."] #[inline(always)] #[must_use] pub fn clrena(&mut self) -> CLRENA_W { diff --git a/src/ppb/nvic_icpr.rs b/src/ppb/nvic_icpr.rs index d1266559f..383fe1a9b 100644 --- a/src/ppb/nvic_icpr.rs +++ b/src/ppb/nvic_icpr.rs @@ -2,43 +2,19 @@ pub type R = crate::R; #[doc = "Register `NVIC_ICPR` writer"] pub type W = crate::W; -#[doc = "Field `CLRPEND` reader - Interrupt clear-pending bits. - Write: - 0 = No effect. - 1 = Removes pending state and interrupt. - Read: - 0 = Interrupt is not pending. - 1 = Interrupt is pending."] +#[doc = "Field `CLRPEND` reader - Interrupt clear-pending bits. Write: 0 = No effect. 1 = Removes pending state and interrupt. Read: 0 = Interrupt is not pending. 1 = Interrupt is pending."] pub type CLRPEND_R = crate::FieldReader; -#[doc = "Field `CLRPEND` writer - Interrupt clear-pending bits. - Write: - 0 = No effect. - 1 = Removes pending state and interrupt. - Read: - 0 = Interrupt is not pending. - 1 = Interrupt is pending."] +#[doc = "Field `CLRPEND` writer - Interrupt clear-pending bits. Write: 0 = No effect. 1 = Removes pending state and interrupt. Read: 0 = Interrupt is not pending. 1 = Interrupt is pending."] pub type CLRPEND_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { - #[doc = "Bits 0:31 - Interrupt clear-pending bits. - Write: - 0 = No effect. - 1 = Removes pending state and interrupt. - Read: - 0 = Interrupt is not pending. - 1 = Interrupt is pending."] + #[doc = "Bits 0:31 - Interrupt clear-pending bits. Write: 0 = No effect. 1 = Removes pending state and interrupt. Read: 0 = Interrupt is not pending. 1 = Interrupt is pending."] #[inline(always)] pub fn clrpend(&self) -> CLRPEND_R { CLRPEND_R::new(self.bits) } } impl W { - #[doc = "Bits 0:31 - Interrupt clear-pending bits. - Write: - 0 = No effect. - 1 = Removes pending state and interrupt. - Read: - 0 = Interrupt is not pending. - 1 = Interrupt is pending."] + #[doc = "Bits 0:31 - Interrupt clear-pending bits. Write: 0 = No effect. 1 = Removes pending state and interrupt. Read: 0 = Interrupt is not pending. 1 = Interrupt is pending."] #[inline(always)] #[must_use] pub fn clrpend(&mut self) -> CLRPEND_W { diff --git a/src/ppb/nvic_ipr0.rs b/src/ppb/nvic_ipr0.rs index 829f9209c..7432535ad 100644 --- a/src/ppb/nvic_ipr0.rs +++ b/src/ppb/nvic_ipr0.rs @@ -66,9 +66,7 @@ impl W { IP_3_W::new(self, 30) } } -#[doc = "Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. - Note: Writing 1 to an NVIC_ICPR bit does not affect the active state of the corresponding interrupt. - These registers are only word-accessible +#[doc = "Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. Note: Writing 1 to an NVIC_ICPR bit does not affect the active state of the corresponding interrupt. These registers are only word-accessible You can [`read`](crate::generic::Reg::read) this register and get [`nvic_ipr0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nvic_ipr0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct NVIC_IPR0_SPEC; diff --git a/src/ppb/nvic_iser.rs b/src/ppb/nvic_iser.rs index 314c4d7f3..fa308c05f 100644 --- a/src/ppb/nvic_iser.rs +++ b/src/ppb/nvic_iser.rs @@ -2,51 +2,26 @@ pub type R = crate::R; #[doc = "Register `NVIC_ISER` writer"] pub type W = crate::W; -#[doc = "Field `SETENA` reader - Interrupt set-enable bits. - Write: - 0 = No effect. - 1 = Enable interrupt. - Read: - 0 = Interrupt disabled. - 1 = Interrupt enabled."] +#[doc = "Field `SETENA` reader - Interrupt set-enable bits. Write: 0 = No effect. 1 = Enable interrupt. Read: 0 = Interrupt disabled. 1 = Interrupt enabled."] pub type SETENA_R = crate::FieldReader; -#[doc = "Field `SETENA` writer - Interrupt set-enable bits. - Write: - 0 = No effect. - 1 = Enable interrupt. - Read: - 0 = Interrupt disabled. - 1 = Interrupt enabled."] +#[doc = "Field `SETENA` writer - Interrupt set-enable bits. Write: 0 = No effect. 1 = Enable interrupt. Read: 0 = Interrupt disabled. 1 = Interrupt enabled."] pub type SETENA_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { - #[doc = "Bits 0:31 - Interrupt set-enable bits. - Write: - 0 = No effect. - 1 = Enable interrupt. - Read: - 0 = Interrupt disabled. - 1 = Interrupt enabled."] + #[doc = "Bits 0:31 - Interrupt set-enable bits. Write: 0 = No effect. 1 = Enable interrupt. Read: 0 = Interrupt disabled. 1 = Interrupt enabled."] #[inline(always)] pub fn setena(&self) -> SETENA_R { SETENA_R::new(self.bits) } } impl W { - #[doc = "Bits 0:31 - Interrupt set-enable bits. - Write: - 0 = No effect. - 1 = Enable interrupt. - Read: - 0 = Interrupt disabled. - 1 = Interrupt enabled."] + #[doc = "Bits 0:31 - Interrupt set-enable bits. Write: 0 = No effect. 1 = Enable interrupt. Read: 0 = Interrupt disabled. 1 = Interrupt enabled."] #[inline(always)] #[must_use] pub fn setena(&mut self) -> SETENA_W { SETENA_W::new(self, 0) } } -#[doc = "Use the Interrupt Set-Enable Register to enable interrupts and determine which interrupts are currently enabled. - If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC never activates the interrupt, regardless of its priority. +#[doc = "Use the Interrupt Set-Enable Register to enable interrupts and determine which interrupts are currently enabled. If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC never activates the interrupt, regardless of its priority. You can [`read`](crate::generic::Reg::read) this register and get [`nvic_iser::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nvic_iser::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct NVIC_ISER_SPEC; diff --git a/src/ppb/nvic_ispr.rs b/src/ppb/nvic_ispr.rs index e3462d616..1d6b8c57f 100644 --- a/src/ppb/nvic_ispr.rs +++ b/src/ppb/nvic_ispr.rs @@ -2,55 +2,19 @@ pub type R = crate::R; #[doc = "Register `NVIC_ISPR` writer"] pub type W = crate::W; -#[doc = "Field `SETPEND` reader - Interrupt set-pending bits. - Write: - 0 = No effect. - 1 = Changes interrupt state to pending. - Read: - 0 = Interrupt is not pending. - 1 = Interrupt is pending. - Note: Writing 1 to the NVIC_ISPR bit corresponding to: - An interrupt that is pending has no effect. - A disabled interrupt sets the state of that interrupt to pending."] +#[doc = "Field `SETPEND` reader - Interrupt set-pending bits. Write: 0 = No effect. 1 = Changes interrupt state to pending. Read: 0 = Interrupt is not pending. 1 = Interrupt is pending. Note: Writing 1 to the NVIC_ISPR bit corresponding to: An interrupt that is pending has no effect. A disabled interrupt sets the state of that interrupt to pending."] pub type SETPEND_R = crate::FieldReader; -#[doc = "Field `SETPEND` writer - Interrupt set-pending bits. - Write: - 0 = No effect. - 1 = Changes interrupt state to pending. - Read: - 0 = Interrupt is not pending. - 1 = Interrupt is pending. - Note: Writing 1 to the NVIC_ISPR bit corresponding to: - An interrupt that is pending has no effect. - A disabled interrupt sets the state of that interrupt to pending."] +#[doc = "Field `SETPEND` writer - Interrupt set-pending bits. Write: 0 = No effect. 1 = Changes interrupt state to pending. Read: 0 = Interrupt is not pending. 1 = Interrupt is pending. Note: Writing 1 to the NVIC_ISPR bit corresponding to: An interrupt that is pending has no effect. A disabled interrupt sets the state of that interrupt to pending."] pub type SETPEND_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; impl R { - #[doc = "Bits 0:31 - Interrupt set-pending bits. - Write: - 0 = No effect. - 1 = Changes interrupt state to pending. - Read: - 0 = Interrupt is not pending. - 1 = Interrupt is pending. - Note: Writing 1 to the NVIC_ISPR bit corresponding to: - An interrupt that is pending has no effect. - A disabled interrupt sets the state of that interrupt to pending."] + #[doc = "Bits 0:31 - Interrupt set-pending bits. Write: 0 = No effect. 1 = Changes interrupt state to pending. Read: 0 = Interrupt is not pending. 1 = Interrupt is pending. Note: Writing 1 to the NVIC_ISPR bit corresponding to: An interrupt that is pending has no effect. A disabled interrupt sets the state of that interrupt to pending."] #[inline(always)] pub fn setpend(&self) -> SETPEND_R { SETPEND_R::new(self.bits) } } impl W { - #[doc = "Bits 0:31 - Interrupt set-pending bits. - Write: - 0 = No effect. - 1 = Changes interrupt state to pending. - Read: - 0 = Interrupt is not pending. - 1 = Interrupt is pending. - Note: Writing 1 to the NVIC_ISPR bit corresponding to: - An interrupt that is pending has no effect. - A disabled interrupt sets the state of that interrupt to pending."] + #[doc = "Bits 0:31 - Interrupt set-pending bits. Write: 0 = No effect. 1 = Changes interrupt state to pending. Read: 0 = Interrupt is not pending. 1 = Interrupt is pending. Note: Writing 1 to the NVIC_ISPR bit corresponding to: An interrupt that is pending has no effect. A disabled interrupt sets the state of that interrupt to pending."] #[inline(always)] #[must_use] pub fn setpend(&mut self) -> SETPEND_W { diff --git a/src/ppb/scr.rs b/src/ppb/scr.rs index e21e417a4..700e2ea2f 100644 --- a/src/ppb/scr.rs +++ b/src/ppb/scr.rs @@ -2,89 +2,49 @@ pub type R = crate::R; #[doc = "Register `SCR` writer"] pub type W = crate::W; -#[doc = "Field `SLEEPONEXIT` reader - Indicates sleep-on-exit when returning from Handler mode to Thread mode: - 0 = Do not sleep when returning to Thread mode. - 1 = Enter sleep, or deep sleep, on return from an ISR to Thread mode. - Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application."] +#[doc = "Field `SLEEPONEXIT` reader - Indicates sleep-on-exit when returning from Handler mode to Thread mode: 0 = Do not sleep when returning to Thread mode. 1 = Enter sleep, or deep sleep, on return from an ISR to Thread mode. Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application."] pub type SLEEPONEXIT_R = crate::BitReader; -#[doc = "Field `SLEEPONEXIT` writer - Indicates sleep-on-exit when returning from Handler mode to Thread mode: - 0 = Do not sleep when returning to Thread mode. - 1 = Enter sleep, or deep sleep, on return from an ISR to Thread mode. - Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application."] +#[doc = "Field `SLEEPONEXIT` writer - Indicates sleep-on-exit when returning from Handler mode to Thread mode: 0 = Do not sleep when returning to Thread mode. 1 = Enter sleep, or deep sleep, on return from an ISR to Thread mode. Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application."] pub type SLEEPONEXIT_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SLEEPDEEP` reader - Controls whether the processor uses sleep or deep sleep as its low power mode: - 0 = Sleep. - 1 = Deep sleep."] +#[doc = "Field `SLEEPDEEP` reader - Controls whether the processor uses sleep or deep sleep as its low power mode: 0 = Sleep. 1 = Deep sleep."] pub type SLEEPDEEP_R = crate::BitReader; -#[doc = "Field `SLEEPDEEP` writer - Controls whether the processor uses sleep or deep sleep as its low power mode: - 0 = Sleep. - 1 = Deep sleep."] +#[doc = "Field `SLEEPDEEP` writer - Controls whether the processor uses sleep or deep sleep as its low power mode: 0 = Sleep. 1 = Deep sleep."] pub type SLEEPDEEP_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `SEVONPEND` reader - Send Event on Pending bit: - 0 = Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded. - 1 = Enabled events and all interrupts, including disabled interrupts, can wakeup the processor. - When an event or interrupt becomes pending, the event signal wakes up the processor from WFE. If the - processor is not waiting for an event, the event is registered and affects the next WFE. - The processor also wakes up on execution of an SEV instruction or an external event."] +#[doc = "Field `SEVONPEND` reader - Send Event on Pending bit: 0 = Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded. 1 = Enabled events and all interrupts, including disabled interrupts, can wakeup the processor. When an event or interrupt becomes pending, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE. The processor also wakes up on execution of an SEV instruction or an external event."] pub type SEVONPEND_R = crate::BitReader; -#[doc = "Field `SEVONPEND` writer - Send Event on Pending bit: - 0 = Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded. - 1 = Enabled events and all interrupts, including disabled interrupts, can wakeup the processor. - When an event or interrupt becomes pending, the event signal wakes up the processor from WFE. If the - processor is not waiting for an event, the event is registered and affects the next WFE. - The processor also wakes up on execution of an SEV instruction or an external event."] +#[doc = "Field `SEVONPEND` writer - Send Event on Pending bit: 0 = Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded. 1 = Enabled events and all interrupts, including disabled interrupts, can wakeup the processor. When an event or interrupt becomes pending, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE. The processor also wakes up on execution of an SEV instruction or an external event."] pub type SEVONPEND_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { - #[doc = "Bit 1 - Indicates sleep-on-exit when returning from Handler mode to Thread mode: - 0 = Do not sleep when returning to Thread mode. - 1 = Enter sleep, or deep sleep, on return from an ISR to Thread mode. - Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application."] + #[doc = "Bit 1 - Indicates sleep-on-exit when returning from Handler mode to Thread mode: 0 = Do not sleep when returning to Thread mode. 1 = Enter sleep, or deep sleep, on return from an ISR to Thread mode. Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application."] #[inline(always)] pub fn sleeponexit(&self) -> SLEEPONEXIT_R { SLEEPONEXIT_R::new(((self.bits >> 1) & 1) != 0) } - #[doc = "Bit 2 - Controls whether the processor uses sleep or deep sleep as its low power mode: - 0 = Sleep. - 1 = Deep sleep."] + #[doc = "Bit 2 - Controls whether the processor uses sleep or deep sleep as its low power mode: 0 = Sleep. 1 = Deep sleep."] #[inline(always)] pub fn sleepdeep(&self) -> SLEEPDEEP_R { SLEEPDEEP_R::new(((self.bits >> 2) & 1) != 0) } - #[doc = "Bit 4 - Send Event on Pending bit: - 0 = Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded. - 1 = Enabled events and all interrupts, including disabled interrupts, can wakeup the processor. - When an event or interrupt becomes pending, the event signal wakes up the processor from WFE. If the - processor is not waiting for an event, the event is registered and affects the next WFE. - The processor also wakes up on execution of an SEV instruction or an external event."] + #[doc = "Bit 4 - Send Event on Pending bit: 0 = Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded. 1 = Enabled events and all interrupts, including disabled interrupts, can wakeup the processor. When an event or interrupt becomes pending, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE. The processor also wakes up on execution of an SEV instruction or an external event."] #[inline(always)] pub fn sevonpend(&self) -> SEVONPEND_R { SEVONPEND_R::new(((self.bits >> 4) & 1) != 0) } } impl W { - #[doc = "Bit 1 - Indicates sleep-on-exit when returning from Handler mode to Thread mode: - 0 = Do not sleep when returning to Thread mode. - 1 = Enter sleep, or deep sleep, on return from an ISR to Thread mode. - Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application."] + #[doc = "Bit 1 - Indicates sleep-on-exit when returning from Handler mode to Thread mode: 0 = Do not sleep when returning to Thread mode. 1 = Enter sleep, or deep sleep, on return from an ISR to Thread mode. Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application."] #[inline(always)] #[must_use] pub fn sleeponexit(&mut self) -> SLEEPONEXIT_W { SLEEPONEXIT_W::new(self, 1) } - #[doc = "Bit 2 - Controls whether the processor uses sleep or deep sleep as its low power mode: - 0 = Sleep. - 1 = Deep sleep."] + #[doc = "Bit 2 - Controls whether the processor uses sleep or deep sleep as its low power mode: 0 = Sleep. 1 = Deep sleep."] #[inline(always)] #[must_use] pub fn sleepdeep(&mut self) -> SLEEPDEEP_W { SLEEPDEEP_W::new(self, 2) } - #[doc = "Bit 4 - Send Event on Pending bit: - 0 = Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded. - 1 = Enabled events and all interrupts, including disabled interrupts, can wakeup the processor. - When an event or interrupt becomes pending, the event signal wakes up the processor from WFE. If the - processor is not waiting for an event, the event is registered and affects the next WFE. - The processor also wakes up on execution of an SEV instruction or an external event."] + #[doc = "Bit 4 - Send Event on Pending bit: 0 = Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded. 1 = Enabled events and all interrupts, including disabled interrupts, can wakeup the processor. When an event or interrupt becomes pending, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE. The processor also wakes up on execution of an SEV instruction or an external event."] #[inline(always)] #[must_use] pub fn sevonpend(&mut self) -> SEVONPEND_W { diff --git a/src/ppb/syst_calib.rs b/src/ppb/syst_calib.rs index b8dee019d..c1e6694be 100644 --- a/src/ppb/syst_calib.rs +++ b/src/ppb/syst_calib.rs @@ -1,5 +1,7 @@ #[doc = "Register `SYST_CALIB` reader"] pub type R = crate::R; +#[doc = "Register `SYST_CALIB` writer"] +pub type W = crate::W; #[doc = "Field `TENMS` reader - An optional Reload value to be used for 10ms (100Hz) timing, subject to system clock skew errors. If the value reads as 0, the calibration value is not known."] pub type TENMS_R = crate::FieldReader; #[doc = "Field `SKEW` reader - If reads as 1, the calibration value for 10ms is inexact (due to clock frequency)."] @@ -23,15 +25,22 @@ impl R { NOREF_R::new(((self.bits >> 31) & 1) != 0) } } +impl W {} #[doc = "Use the SysTick Calibration Value Register to enable software to scale to any required speed using divide and multiply. -You can [`read`](crate::generic::Reg::read) this register and get [`syst_calib::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`syst_calib::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`syst_calib::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SYST_CALIB_SPEC; impl crate::RegisterSpec for SYST_CALIB_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`syst_calib::R`](R) reader structure"] impl crate::Readable for SYST_CALIB_SPEC {} +#[doc = "`write(|w| ..)` method takes [`syst_calib::W`](W) writer structure"] +impl crate::Writable for SYST_CALIB_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets SYST_CALIB to value 0"] impl crate::Resettable for SYST_CALIB_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/ppb/syst_csr.rs b/src/ppb/syst_csr.rs index 40c993501..982f710c0 100644 --- a/src/ppb/syst_csr.rs +++ b/src/ppb/syst_csr.rs @@ -2,53 +2,32 @@ pub type R = crate::R; #[doc = "Register `SYST_CSR` writer"] pub type W = crate::W; -#[doc = "Field `ENABLE` reader - Enable SysTick counter: - 0 = Counter disabled. - 1 = Counter enabled."] +#[doc = "Field `ENABLE` reader - Enable SysTick counter: 0 = Counter disabled. 1 = Counter enabled."] pub type ENABLE_R = crate::BitReader; -#[doc = "Field `ENABLE` writer - Enable SysTick counter: - 0 = Counter disabled. - 1 = Counter enabled."] +#[doc = "Field `ENABLE` writer - Enable SysTick counter: 0 = Counter disabled. 1 = Counter enabled."] pub type ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `TICKINT` reader - Enables SysTick exception request: - 0 = Counting down to zero does not assert the SysTick exception request. - 1 = Counting down to zero to asserts the SysTick exception request."] +#[doc = "Field `TICKINT` reader - Enables SysTick exception request: 0 = Counting down to zero does not assert the SysTick exception request. 1 = Counting down to zero to asserts the SysTick exception request."] pub type TICKINT_R = crate::BitReader; -#[doc = "Field `TICKINT` writer - Enables SysTick exception request: - 0 = Counting down to zero does not assert the SysTick exception request. - 1 = Counting down to zero to asserts the SysTick exception request."] +#[doc = "Field `TICKINT` writer - Enables SysTick exception request: 0 = Counting down to zero does not assert the SysTick exception request. 1 = Counting down to zero to asserts the SysTick exception request."] pub type TICKINT_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CLKSOURCE` reader - SysTick clock source. Always reads as one if SYST_CALIB reports NOREF. - Selects the SysTick timer clock source: - 0 = External reference clock. - 1 = Processor clock."] +#[doc = "Field `CLKSOURCE` reader - SysTick clock source. Always reads as one if SYST_CALIB reports NOREF. Selects the SysTick timer clock source: 0 = External reference clock. 1 = Processor clock."] pub type CLKSOURCE_R = crate::BitReader; -#[doc = "Field `CLKSOURCE` writer - SysTick clock source. Always reads as one if SYST_CALIB reports NOREF. - Selects the SysTick timer clock source: - 0 = External reference clock. - 1 = Processor clock."] +#[doc = "Field `CLKSOURCE` writer - SysTick clock source. Always reads as one if SYST_CALIB reports NOREF. Selects the SysTick timer clock source: 0 = External reference clock. 1 = Processor clock."] pub type CLKSOURCE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `COUNTFLAG` reader - Returns 1 if timer counted to 0 since last time this was read. Clears on read by application or debugger."] pub type COUNTFLAG_R = crate::BitReader; impl R { - #[doc = "Bit 0 - Enable SysTick counter: - 0 = Counter disabled. - 1 = Counter enabled."] + #[doc = "Bit 0 - Enable SysTick counter: 0 = Counter disabled. 1 = Counter enabled."] #[inline(always)] pub fn enable(&self) -> ENABLE_R { ENABLE_R::new((self.bits & 1) != 0) } - #[doc = "Bit 1 - Enables SysTick exception request: - 0 = Counting down to zero does not assert the SysTick exception request. - 1 = Counting down to zero to asserts the SysTick exception request."] + #[doc = "Bit 1 - Enables SysTick exception request: 0 = Counting down to zero does not assert the SysTick exception request. 1 = Counting down to zero to asserts the SysTick exception request."] #[inline(always)] pub fn tickint(&self) -> TICKINT_R { TICKINT_R::new(((self.bits >> 1) & 1) != 0) } - #[doc = "Bit 2 - SysTick clock source. Always reads as one if SYST_CALIB reports NOREF. - Selects the SysTick timer clock source: - 0 = External reference clock. - 1 = Processor clock."] + #[doc = "Bit 2 - SysTick clock source. Always reads as one if SYST_CALIB reports NOREF. Selects the SysTick timer clock source: 0 = External reference clock. 1 = Processor clock."] #[inline(always)] pub fn clksource(&self) -> CLKSOURCE_R { CLKSOURCE_R::new(((self.bits >> 2) & 1) != 0) @@ -60,26 +39,19 @@ impl R { } } impl W { - #[doc = "Bit 0 - Enable SysTick counter: - 0 = Counter disabled. - 1 = Counter enabled."] + #[doc = "Bit 0 - Enable SysTick counter: 0 = Counter disabled. 1 = Counter enabled."] #[inline(always)] #[must_use] pub fn enable(&mut self) -> ENABLE_W { ENABLE_W::new(self, 0) } - #[doc = "Bit 1 - Enables SysTick exception request: - 0 = Counting down to zero does not assert the SysTick exception request. - 1 = Counting down to zero to asserts the SysTick exception request."] + #[doc = "Bit 1 - Enables SysTick exception request: 0 = Counting down to zero does not assert the SysTick exception request. 1 = Counting down to zero to asserts the SysTick exception request."] #[inline(always)] #[must_use] pub fn tickint(&mut self) -> TICKINT_W { TICKINT_W::new(self, 1) } - #[doc = "Bit 2 - SysTick clock source. Always reads as one if SYST_CALIB reports NOREF. - Selects the SysTick timer clock source: - 0 = External reference clock. - 1 = Processor clock."] + #[doc = "Bit 2 - SysTick clock source. Always reads as one if SYST_CALIB reports NOREF. Selects the SysTick timer clock source: 0 = External reference clock. 1 = Processor clock."] #[inline(always)] #[must_use] pub fn clksource(&mut self) -> CLKSOURCE_W { diff --git a/src/ppb/syst_rvr.rs b/src/ppb/syst_rvr.rs index 4e8f0451e..016b6728e 100644 --- a/src/ppb/syst_rvr.rs +++ b/src/ppb/syst_rvr.rs @@ -21,8 +21,7 @@ impl W { RELOAD_W::new(self, 0) } } -#[doc = "Use the SysTick Reload Value Register to specify the start value to load into the current value register when the counter reaches 0. It can be any value between 0 and 0x00FFFFFF. A start value of 0 is possible, but has no effect because the SysTick interrupt and COUNTFLAG are activated when counting from 1 to 0. The reset value of this register is UNKNOWN. - To generate a multi-shot timer with a period of N processor clock cycles, use a RELOAD value of N-1. For example, if the SysTick interrupt is required every 100 clock pulses, set RELOAD to 99. +#[doc = "Use the SysTick Reload Value Register to specify the start value to load into the current value register when the counter reaches 0. It can be any value between 0 and 0x00FFFFFF. A start value of 0 is possible, but has no effect because the SysTick interrupt and COUNTFLAG are activated when counting from 1 to 0. The reset value of this register is UNKNOWN. To generate a multi-shot timer with a period of N processor clock cycles, use a RELOAD value of N-1. For example, if the SysTick interrupt is required every 100 clock pulses, set RELOAD to 99. You can [`read`](crate::generic::Reg::read) this register and get [`syst_rvr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`syst_rvr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SYST_RVR_SPEC; diff --git a/src/psm.rs b/src/psm.rs index c31b8c163..846f2318a 100644 --- a/src/psm.rs +++ b/src/psm.rs @@ -55,9 +55,9 @@ module"] pub type WDSEL = crate::Reg; #[doc = "Set to 1 if this peripheral should be reset when the watchdog fires."] pub mod wdsel; -#[doc = "DONE (r) register accessor: Indicates the peripheral's registers are ready to access. +#[doc = "DONE (rw) register accessor: Indicates the peripheral's registers are ready to access. -You can [`read`](crate::generic::Reg::read) this register and get [`done::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`done::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`done::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@done`] module"] diff --git a/src/psm/done.rs b/src/psm/done.rs index f8a86abc5..719efb67f 100644 --- a/src/psm/done.rs +++ b/src/psm/done.rs @@ -1,38 +1,40 @@ #[doc = "Register `DONE` reader"] pub type R = crate::R; -#[doc = "Field `rosc` reader - "] +#[doc = "Register `DONE` writer"] +pub type W = crate::W; +#[doc = "Field `ROSC` reader - "] pub type ROSC_R = crate::BitReader; -#[doc = "Field `xosc` reader - "] +#[doc = "Field `XOSC` reader - "] pub type XOSC_R = crate::BitReader; -#[doc = "Field `clocks` reader - "] +#[doc = "Field `CLOCKS` reader - "] pub type CLOCKS_R = crate::BitReader; -#[doc = "Field `resets` reader - "] +#[doc = "Field `RESETS` reader - "] pub type RESETS_R = crate::BitReader; -#[doc = "Field `busfabric` reader - "] +#[doc = "Field `BUSFABRIC` reader - "] pub type BUSFABRIC_R = crate::BitReader; -#[doc = "Field `rom` reader - "] +#[doc = "Field `ROM` reader - "] pub type ROM_R = crate::BitReader; -#[doc = "Field `sram0` reader - "] +#[doc = "Field `SRAM0` reader - "] pub type SRAM0_R = crate::BitReader; -#[doc = "Field `sram1` reader - "] +#[doc = "Field `SRAM1` reader - "] pub type SRAM1_R = crate::BitReader; -#[doc = "Field `sram2` reader - "] +#[doc = "Field `SRAM2` reader - "] pub type SRAM2_R = crate::BitReader; -#[doc = "Field `sram3` reader - "] +#[doc = "Field `SRAM3` reader - "] pub type SRAM3_R = crate::BitReader; -#[doc = "Field `sram4` reader - "] +#[doc = "Field `SRAM4` reader - "] pub type SRAM4_R = crate::BitReader; -#[doc = "Field `sram5` reader - "] +#[doc = "Field `SRAM5` reader - "] pub type SRAM5_R = crate::BitReader; -#[doc = "Field `xip` reader - "] +#[doc = "Field `XIP` reader - "] pub type XIP_R = crate::BitReader; -#[doc = "Field `vreg_and_chip_reset` reader - "] +#[doc = "Field `VREG_AND_CHIP_RESET` reader - "] pub type VREG_AND_CHIP_RESET_R = crate::BitReader; -#[doc = "Field `sio` reader - "] +#[doc = "Field `SIO` reader - "] pub type SIO_R = crate::BitReader; -#[doc = "Field `proc0` reader - "] +#[doc = "Field `PROC0` reader - "] pub type PROC0_R = crate::BitReader; -#[doc = "Field `proc1` reader - "] +#[doc = "Field `PROC1` reader - "] pub type PROC1_R = crate::BitReader; impl R { #[doc = "Bit 0"] @@ -121,15 +123,22 @@ impl R { PROC1_R::new(((self.bits >> 16) & 1) != 0) } } +impl W {} #[doc = "Indicates the peripheral's registers are ready to access. -You can [`read`](crate::generic::Reg::read) this register and get [`done::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`done::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`done::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DONE_SPEC; impl crate::RegisterSpec for DONE_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`done::R`](R) reader structure"] impl crate::Readable for DONE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`done::W`](W) writer structure"] +impl crate::Writable for DONE_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets DONE to value 0"] impl crate::Resettable for DONE_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/psm/frce_off.rs b/src/psm/frce_off.rs index 762808564..5507a3eaf 100644 --- a/src/psm/frce_off.rs +++ b/src/psm/frce_off.rs @@ -2,73 +2,73 @@ pub type R = crate::R; #[doc = "Register `FRCE_OFF` writer"] pub type W = crate::W; -#[doc = "Field `rosc` reader - "] +#[doc = "Field `ROSC` reader - "] pub type ROSC_R = crate::BitReader; -#[doc = "Field `rosc` writer - "] +#[doc = "Field `ROSC` writer - "] pub type ROSC_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `xosc` reader - "] +#[doc = "Field `XOSC` reader - "] pub type XOSC_R = crate::BitReader; -#[doc = "Field `xosc` writer - "] +#[doc = "Field `XOSC` writer - "] pub type XOSC_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clocks` reader - "] +#[doc = "Field `CLOCKS` reader - "] pub type CLOCKS_R = crate::BitReader; -#[doc = "Field `clocks` writer - "] +#[doc = "Field `CLOCKS` writer - "] pub type CLOCKS_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `resets` reader - "] +#[doc = "Field `RESETS` reader - "] pub type RESETS_R = crate::BitReader; -#[doc = "Field `resets` writer - "] +#[doc = "Field `RESETS` writer - "] pub type RESETS_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `busfabric` reader - "] +#[doc = "Field `BUSFABRIC` reader - "] pub type BUSFABRIC_R = crate::BitReader; -#[doc = "Field `busfabric` writer - "] +#[doc = "Field `BUSFABRIC` writer - "] pub type BUSFABRIC_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `rom` reader - "] +#[doc = "Field `ROM` reader - "] pub type ROM_R = crate::BitReader; -#[doc = "Field `rom` writer - "] +#[doc = "Field `ROM` writer - "] pub type ROM_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `sram0` reader - "] +#[doc = "Field `SRAM0` reader - "] pub type SRAM0_R = crate::BitReader; -#[doc = "Field `sram0` writer - "] +#[doc = "Field `SRAM0` writer - "] pub type SRAM0_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `sram1` reader - "] +#[doc = "Field `SRAM1` reader - "] pub type SRAM1_R = crate::BitReader; -#[doc = "Field `sram1` writer - "] +#[doc = "Field `SRAM1` writer - "] pub type SRAM1_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `sram2` reader - "] +#[doc = "Field `SRAM2` reader - "] pub type SRAM2_R = crate::BitReader; -#[doc = "Field `sram2` writer - "] +#[doc = "Field `SRAM2` writer - "] pub type SRAM2_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `sram3` reader - "] +#[doc = "Field `SRAM3` reader - "] pub type SRAM3_R = crate::BitReader; -#[doc = "Field `sram3` writer - "] +#[doc = "Field `SRAM3` writer - "] pub type SRAM3_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `sram4` reader - "] +#[doc = "Field `SRAM4` reader - "] pub type SRAM4_R = crate::BitReader; -#[doc = "Field `sram4` writer - "] +#[doc = "Field `SRAM4` writer - "] pub type SRAM4_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `sram5` reader - "] +#[doc = "Field `SRAM5` reader - "] pub type SRAM5_R = crate::BitReader; -#[doc = "Field `sram5` writer - "] +#[doc = "Field `SRAM5` writer - "] pub type SRAM5_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `xip` reader - "] +#[doc = "Field `XIP` reader - "] pub type XIP_R = crate::BitReader; -#[doc = "Field `xip` writer - "] +#[doc = "Field `XIP` writer - "] pub type XIP_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `vreg_and_chip_reset` reader - "] +#[doc = "Field `VREG_AND_CHIP_RESET` reader - "] pub type VREG_AND_CHIP_RESET_R = crate::BitReader; -#[doc = "Field `vreg_and_chip_reset` writer - "] +#[doc = "Field `VREG_AND_CHIP_RESET` writer - "] pub type VREG_AND_CHIP_RESET_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `sio` reader - "] +#[doc = "Field `SIO` reader - "] pub type SIO_R = crate::BitReader; -#[doc = "Field `sio` writer - "] +#[doc = "Field `SIO` writer - "] pub type SIO_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `proc0` reader - "] +#[doc = "Field `PROC0` reader - "] pub type PROC0_R = crate::BitReader; -#[doc = "Field `proc0` writer - "] +#[doc = "Field `PROC0` writer - "] pub type PROC0_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `proc1` reader - "] +#[doc = "Field `PROC1` reader - "] pub type PROC1_R = crate::BitReader; -#[doc = "Field `proc1` writer - "] +#[doc = "Field `PROC1` writer - "] pub type PROC1_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0"] diff --git a/src/psm/frce_on.rs b/src/psm/frce_on.rs index b13ba24ae..98ed27f9e 100644 --- a/src/psm/frce_on.rs +++ b/src/psm/frce_on.rs @@ -2,73 +2,73 @@ pub type R = crate::R; #[doc = "Register `FRCE_ON` writer"] pub type W = crate::W; -#[doc = "Field `rosc` reader - "] +#[doc = "Field `ROSC` reader - "] pub type ROSC_R = crate::BitReader; -#[doc = "Field `rosc` writer - "] +#[doc = "Field `ROSC` writer - "] pub type ROSC_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `xosc` reader - "] +#[doc = "Field `XOSC` reader - "] pub type XOSC_R = crate::BitReader; -#[doc = "Field `xosc` writer - "] +#[doc = "Field `XOSC` writer - "] pub type XOSC_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clocks` reader - "] +#[doc = "Field `CLOCKS` reader - "] pub type CLOCKS_R = crate::BitReader; -#[doc = "Field `clocks` writer - "] +#[doc = "Field `CLOCKS` writer - "] pub type CLOCKS_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `resets` reader - "] +#[doc = "Field `RESETS` reader - "] pub type RESETS_R = crate::BitReader; -#[doc = "Field `resets` writer - "] +#[doc = "Field `RESETS` writer - "] pub type RESETS_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `busfabric` reader - "] +#[doc = "Field `BUSFABRIC` reader - "] pub type BUSFABRIC_R = crate::BitReader; -#[doc = "Field `busfabric` writer - "] +#[doc = "Field `BUSFABRIC` writer - "] pub type BUSFABRIC_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `rom` reader - "] +#[doc = "Field `ROM` reader - "] pub type ROM_R = crate::BitReader; -#[doc = "Field `rom` writer - "] +#[doc = "Field `ROM` writer - "] pub type ROM_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `sram0` reader - "] +#[doc = "Field `SRAM0` reader - "] pub type SRAM0_R = crate::BitReader; -#[doc = "Field `sram0` writer - "] +#[doc = "Field `SRAM0` writer - "] pub type SRAM0_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `sram1` reader - "] +#[doc = "Field `SRAM1` reader - "] pub type SRAM1_R = crate::BitReader; -#[doc = "Field `sram1` writer - "] +#[doc = "Field `SRAM1` writer - "] pub type SRAM1_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `sram2` reader - "] +#[doc = "Field `SRAM2` reader - "] pub type SRAM2_R = crate::BitReader; -#[doc = "Field `sram2` writer - "] +#[doc = "Field `SRAM2` writer - "] pub type SRAM2_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `sram3` reader - "] +#[doc = "Field `SRAM3` reader - "] pub type SRAM3_R = crate::BitReader; -#[doc = "Field `sram3` writer - "] +#[doc = "Field `SRAM3` writer - "] pub type SRAM3_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `sram4` reader - "] +#[doc = "Field `SRAM4` reader - "] pub type SRAM4_R = crate::BitReader; -#[doc = "Field `sram4` writer - "] +#[doc = "Field `SRAM4` writer - "] pub type SRAM4_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `sram5` reader - "] +#[doc = "Field `SRAM5` reader - "] pub type SRAM5_R = crate::BitReader; -#[doc = "Field `sram5` writer - "] +#[doc = "Field `SRAM5` writer - "] pub type SRAM5_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `xip` reader - "] +#[doc = "Field `XIP` reader - "] pub type XIP_R = crate::BitReader; -#[doc = "Field `xip` writer - "] +#[doc = "Field `XIP` writer - "] pub type XIP_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `vreg_and_chip_reset` reader - "] +#[doc = "Field `VREG_AND_CHIP_RESET` reader - "] pub type VREG_AND_CHIP_RESET_R = crate::BitReader; -#[doc = "Field `vreg_and_chip_reset` writer - "] +#[doc = "Field `VREG_AND_CHIP_RESET` writer - "] pub type VREG_AND_CHIP_RESET_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `sio` reader - "] +#[doc = "Field `SIO` reader - "] pub type SIO_R = crate::BitReader; -#[doc = "Field `sio` writer - "] +#[doc = "Field `SIO` writer - "] pub type SIO_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `proc0` reader - "] +#[doc = "Field `PROC0` reader - "] pub type PROC0_R = crate::BitReader; -#[doc = "Field `proc0` writer - "] +#[doc = "Field `PROC0` writer - "] pub type PROC0_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `proc1` reader - "] +#[doc = "Field `PROC1` reader - "] pub type PROC1_R = crate::BitReader; -#[doc = "Field `proc1` writer - "] +#[doc = "Field `PROC1` writer - "] pub type PROC1_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0"] diff --git a/src/psm/wdsel.rs b/src/psm/wdsel.rs index 9a5c5d30a..770f13df7 100644 --- a/src/psm/wdsel.rs +++ b/src/psm/wdsel.rs @@ -2,73 +2,73 @@ pub type R = crate::R; #[doc = "Register `WDSEL` writer"] pub type W = crate::W; -#[doc = "Field `rosc` reader - "] +#[doc = "Field `ROSC` reader - "] pub type ROSC_R = crate::BitReader; -#[doc = "Field `rosc` writer - "] +#[doc = "Field `ROSC` writer - "] pub type ROSC_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `xosc` reader - "] +#[doc = "Field `XOSC` reader - "] pub type XOSC_R = crate::BitReader; -#[doc = "Field `xosc` writer - "] +#[doc = "Field `XOSC` writer - "] pub type XOSC_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `clocks` reader - "] +#[doc = "Field `CLOCKS` reader - "] pub type CLOCKS_R = crate::BitReader; -#[doc = "Field `clocks` writer - "] +#[doc = "Field `CLOCKS` writer - "] pub type CLOCKS_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `resets` reader - "] +#[doc = "Field `RESETS` reader - "] pub type RESETS_R = crate::BitReader; -#[doc = "Field `resets` writer - "] +#[doc = "Field `RESETS` writer - "] pub type RESETS_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `busfabric` reader - "] +#[doc = "Field `BUSFABRIC` reader - "] pub type BUSFABRIC_R = crate::BitReader; -#[doc = "Field `busfabric` writer - "] +#[doc = "Field `BUSFABRIC` writer - "] pub type BUSFABRIC_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `rom` reader - "] +#[doc = "Field `ROM` reader - "] pub type ROM_R = crate::BitReader; -#[doc = "Field `rom` writer - "] +#[doc = "Field `ROM` writer - "] pub type ROM_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `sram0` reader - "] +#[doc = "Field `SRAM0` reader - "] pub type SRAM0_R = crate::BitReader; -#[doc = "Field `sram0` writer - "] +#[doc = "Field `SRAM0` writer - "] pub type SRAM0_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `sram1` reader - "] +#[doc = "Field `SRAM1` reader - "] pub type SRAM1_R = crate::BitReader; -#[doc = "Field `sram1` writer - "] +#[doc = "Field `SRAM1` writer - "] pub type SRAM1_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `sram2` reader - "] +#[doc = "Field `SRAM2` reader - "] pub type SRAM2_R = crate::BitReader; -#[doc = "Field `sram2` writer - "] +#[doc = "Field `SRAM2` writer - "] pub type SRAM2_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `sram3` reader - "] +#[doc = "Field `SRAM3` reader - "] pub type SRAM3_R = crate::BitReader; -#[doc = "Field `sram3` writer - "] +#[doc = "Field `SRAM3` writer - "] pub type SRAM3_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `sram4` reader - "] +#[doc = "Field `SRAM4` reader - "] pub type SRAM4_R = crate::BitReader; -#[doc = "Field `sram4` writer - "] +#[doc = "Field `SRAM4` writer - "] pub type SRAM4_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `sram5` reader - "] +#[doc = "Field `SRAM5` reader - "] pub type SRAM5_R = crate::BitReader; -#[doc = "Field `sram5` writer - "] +#[doc = "Field `SRAM5` writer - "] pub type SRAM5_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `xip` reader - "] +#[doc = "Field `XIP` reader - "] pub type XIP_R = crate::BitReader; -#[doc = "Field `xip` writer - "] +#[doc = "Field `XIP` writer - "] pub type XIP_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `vreg_and_chip_reset` reader - "] +#[doc = "Field `VREG_AND_CHIP_RESET` reader - "] pub type VREG_AND_CHIP_RESET_R = crate::BitReader; -#[doc = "Field `vreg_and_chip_reset` writer - "] +#[doc = "Field `VREG_AND_CHIP_RESET` writer - "] pub type VREG_AND_CHIP_RESET_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `sio` reader - "] +#[doc = "Field `SIO` reader - "] pub type SIO_R = crate::BitReader; -#[doc = "Field `sio` writer - "] +#[doc = "Field `SIO` writer - "] pub type SIO_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `proc0` reader - "] +#[doc = "Field `PROC0` reader - "] pub type PROC0_R = crate::BitReader; -#[doc = "Field `proc0` writer - "] +#[doc = "Field `PROC0` writer - "] pub type PROC0_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `proc1` reader - "] +#[doc = "Field `PROC1` reader - "] pub type PROC1_R = crate::BitReader; -#[doc = "Field `proc1` writer - "] +#[doc = "Field `PROC1` writer - "] pub type PROC1_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0"] diff --git a/src/pwm.rs b/src/pwm.rs index cfe10ce1c..14e7c05c8 100644 --- a/src/pwm.rs +++ b/src/pwm.rs @@ -20,11 +20,7 @@ impl RegisterBlock { pub fn ch_iter(&self) -> impl Iterator { self.ch.iter() } - #[doc = "0xa0 - This register aliases the CSR_EN bits for all channels. - Writing to this register allows multiple channels to be enabled - or disabled simultaneously, so they can run in perfect sync. - For each channel, there is only one physical EN register bit, - which can be accessed through here or CHx_CSR."] + #[doc = "0xa0 - This register aliases the CSR_EN bits for all channels. Writing to this register allows multiple channels to be enabled or disabled simultaneously, so they can run in perfect sync. For each channel, there is only one physical EN register bit, which can be accessed through here or CHx_CSR."] #[inline(always)] pub const fn en(&self) -> &EN { &self.en @@ -55,22 +51,14 @@ pub use self::ch::CH; #[doc = r"Cluster"] #[doc = "Cluster CH%s, containing CH*_CC, CH*_CSR, CH*_CTR, CH*_DIV, CH*_TOP"] pub mod ch; -#[doc = "EN (rw) register accessor: This register aliases the CSR_EN bits for all channels. - Writing to this register allows multiple channels to be enabled - or disabled simultaneously, so they can run in perfect sync. - For each channel, there is only one physical EN register bit, - which can be accessed through here or CHx_CSR. +#[doc = "EN (rw) register accessor: This register aliases the CSR_EN bits for all channels. Writing to this register allows multiple channels to be enabled or disabled simultaneously, so they can run in perfect sync. For each channel, there is only one physical EN register bit, which can be accessed through here or CHx_CSR. You can [`read`](crate::generic::Reg::read) this register and get [`en::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`en::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@en`] module"] pub type EN = crate::Reg; -#[doc = "This register aliases the CSR_EN bits for all channels. - Writing to this register allows multiple channels to be enabled - or disabled simultaneously, so they can run in perfect sync. - For each channel, there is only one physical EN register bit, - which can be accessed through here or CHx_CSR."] +#[doc = "This register aliases the CSR_EN bits for all channels. Writing to this register allows multiple channels to be enabled or disabled simultaneously, so they can run in perfect sync. For each channel, there is only one physical EN register bit, which can be accessed through here or CHx_CSR."] pub mod en; #[doc = "INTR (rw) register accessor: Raw Interrupts @@ -99,9 +87,9 @@ module"] pub type INTF = crate::Reg; #[doc = "Interrupt Force"] pub mod intf; -#[doc = "INTS (r) register accessor: Interrupt status after masking & forcing +#[doc = "INTS (rw) register accessor: Interrupt status after masking & forcing -You can [`read`](crate::generic::Reg::read) this register and get [`ints::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`ints::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ints::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@ints`] module"] diff --git a/src/pwm/ch.rs b/src/pwm/ch.rs index e5b3a229b..4c815c9a9 100644 --- a/src/pwm/ch.rs +++ b/src/pwm/ch.rs @@ -13,9 +13,7 @@ impl CH { pub const fn csr(&self) -> &CSR { &self.csr } - #[doc = "0x04 - INT and FRAC form a fixed-point fractional number. - Counting rate is system clock frequency divided by this number. - Fractional division uses simple 1st-order sigma-delta."] + #[doc = "0x04 - INT and FRAC form a fixed-point fractional number. Counting rate is system clock frequency divided by this number. Fractional division uses simple 1st-order sigma-delta."] #[inline(always)] pub const fn div(&self) -> &DIV { &self.div @@ -63,18 +61,14 @@ module"] pub type CTR = crate::Reg; #[doc = "Direct access to the PWM counter"] pub mod ctr; -#[doc = "DIV (rw) register accessor: INT and FRAC form a fixed-point fractional number. - Counting rate is system clock frequency divided by this number. - Fractional division uses simple 1st-order sigma-delta. +#[doc = "DIV (rw) register accessor: INT and FRAC form a fixed-point fractional number. Counting rate is system clock frequency divided by this number. Fractional division uses simple 1st-order sigma-delta. You can [`read`](crate::generic::Reg::read) this register and get [`div::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`div::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@div`] module"] pub type DIV = crate::Reg; -#[doc = "INT and FRAC form a fixed-point fractional number. - Counting rate is system clock frequency divided by this number. - Fractional division uses simple 1st-order sigma-delta."] +#[doc = "INT and FRAC form a fixed-point fractional number. Counting rate is system clock frequency divided by this number. Fractional division uses simple 1st-order sigma-delta."] pub mod div; #[doc = "TOP (rw) register accessor: Counter wrap value diff --git a/src/pwm/ch/csr.rs b/src/pwm/ch/csr.rs index 991645642..103ef3f40 100644 --- a/src/pwm/ch/csr.rs +++ b/src/pwm/ch/csr.rs @@ -105,19 +105,9 @@ where self.variant(DIVMODE_A::FALL) } } -#[doc = "Field `PH_RET` reader - Retard the phase of the counter by 1 count, while it is running. - Self-clearing. Write a 1, and poll until low. Counter must be running."] -pub type PH_RET_R = crate::BitReader; -#[doc = "Field `PH_RET` writer - Retard the phase of the counter by 1 count, while it is running. - Self-clearing. Write a 1, and poll until low. Counter must be running."] +#[doc = "Field `PH_RET` writer - Retard the phase of the counter by 1 count, while it is running. Self-clearing. Write a 1, and poll until low. Counter must be running."] pub type PH_RET_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `PH_ADV` reader - Advance the phase of the counter by 1 count, while it is running. - Self-clearing. Write a 1, and poll until low. Counter must be running - at less than full speed (div_int + div_frac / 16 > 1)"] -pub type PH_ADV_R = crate::BitReader; -#[doc = "Field `PH_ADV` writer - Advance the phase of the counter by 1 count, while it is running. - Self-clearing. Write a 1, and poll until low. Counter must be running - at less than full speed (div_int + div_frac / 16 > 1)"] +#[doc = "Field `PH_ADV` writer - Advance the phase of the counter by 1 count, while it is running. Self-clearing. Write a 1, and poll until low. Counter must be running at less than full speed (div_int + div_frac / 16 > 1)"] pub type PH_ADV_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Enable the PWM channel."] @@ -145,19 +135,6 @@ impl R { pub fn divmode(&self) -> DIVMODE_R { DIVMODE_R::new(((self.bits >> 4) & 3) as u8) } - #[doc = "Bit 6 - Retard the phase of the counter by 1 count, while it is running. - Self-clearing. Write a 1, and poll until low. Counter must be running."] - #[inline(always)] - pub fn ph_ret(&self) -> PH_RET_R { - PH_RET_R::new(((self.bits >> 6) & 1) != 0) - } - #[doc = "Bit 7 - Advance the phase of the counter by 1 count, while it is running. - Self-clearing. Write a 1, and poll until low. Counter must be running - at less than full speed (div_int + div_frac / 16 > 1)"] - #[inline(always)] - pub fn ph_adv(&self) -> PH_ADV_R { - PH_ADV_R::new(((self.bits >> 7) & 1) != 0) - } } impl W { #[doc = "Bit 0 - Enable the PWM channel."] @@ -190,16 +167,13 @@ impl W { pub fn divmode(&mut self) -> DIVMODE_W { DIVMODE_W::new(self, 4) } - #[doc = "Bit 6 - Retard the phase of the counter by 1 count, while it is running. - Self-clearing. Write a 1, and poll until low. Counter must be running."] + #[doc = "Bit 6 - Retard the phase of the counter by 1 count, while it is running. Self-clearing. Write a 1, and poll until low. Counter must be running."] #[inline(always)] #[must_use] pub fn ph_ret(&mut self) -> PH_RET_W { PH_RET_W::new(self, 6) } - #[doc = "Bit 7 - Advance the phase of the counter by 1 count, while it is running. - Self-clearing. Write a 1, and poll until low. Counter must be running - at less than full speed (div_int + div_frac / 16 > 1)"] + #[doc = "Bit 7 - Advance the phase of the counter by 1 count, while it is running. Self-clearing. Write a 1, and poll until low. Counter must be running at less than full speed (div_int + div_frac / 16 > 1)"] #[inline(always)] #[must_use] pub fn ph_adv(&mut self) -> PH_ADV_W { diff --git a/src/pwm/ch/div.rs b/src/pwm/ch/div.rs index 6c0ea55e2..4d6a32d02 100644 --- a/src/pwm/ch/div.rs +++ b/src/pwm/ch/div.rs @@ -36,9 +36,7 @@ impl W { INT_W::new(self, 4) } } -#[doc = "INT and FRAC form a fixed-point fractional number. - Counting rate is system clock frequency divided by this number. - Fractional division uses simple 1st-order sigma-delta. +#[doc = "INT and FRAC form a fixed-point fractional number. Counting rate is system clock frequency divided by this number. Fractional division uses simple 1st-order sigma-delta. You can [`read`](crate::generic::Reg::read) this register and get [`div::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`div::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DIV_SPEC; diff --git a/src/pwm/en.rs b/src/pwm/en.rs index 1e28b4742..fc840faea 100644 --- a/src/pwm/en.rs +++ b/src/pwm/en.rs @@ -126,11 +126,7 @@ impl W { CH7_W::new(self, 7) } } -#[doc = "This register aliases the CSR_EN bits for all channels. - Writing to this register allows multiple channels to be enabled - or disabled simultaneously, so they can run in perfect sync. - For each channel, there is only one physical EN register bit, - which can be accessed through here or CHx_CSR. +#[doc = "This register aliases the CSR_EN bits for all channels. Writing to this register allows multiple channels to be enabled or disabled simultaneously, so they can run in perfect sync. For each channel, there is only one physical EN register bit, which can be accessed through here or CHx_CSR. You can [`read`](crate::generic::Reg::read) this register and get [`en::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`en::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct EN_SPEC; diff --git a/src/pwm/ints.rs b/src/pwm/ints.rs index ee47535e3..d3a03ec29 100644 --- a/src/pwm/ints.rs +++ b/src/pwm/ints.rs @@ -1,5 +1,7 @@ #[doc = "Register `INTS` reader"] pub type R = crate::R; +#[doc = "Register `INTS` writer"] +pub type W = crate::W; #[doc = "Field `CH0` reader - "] pub type CH0_R = crate::BitReader; #[doc = "Field `CH1` reader - "] @@ -58,15 +60,22 @@ impl R { CH7_R::new(((self.bits >> 7) & 1) != 0) } } +impl W {} #[doc = "Interrupt status after masking & forcing -You can [`read`](crate::generic::Reg::read) this register and get [`ints::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`ints::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ints::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTS_SPEC; impl crate::RegisterSpec for INTS_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`ints::R`](R) reader structure"] impl crate::Readable for INTS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ints::W`](W) writer structure"] +impl crate::Writable for INTS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets INTS to value 0"] impl crate::Resettable for INTS_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/resets.rs b/src/resets.rs index 01d9db6d4..98e562739 100644 --- a/src/resets.rs +++ b/src/resets.rs @@ -40,9 +40,9 @@ module"] pub type WDSEL = crate::Reg; #[doc = "Watchdog select. If a bit is set then the watchdog will reset this peripheral when the watchdog fires."] pub mod wdsel; -#[doc = "RESET_DONE (r) register accessor: Reset done. If a bit is set then a reset done signal has been returned by the peripheral. This indicates that the peripheral's registers are ready to be accessed. +#[doc = "RESET_DONE (rw) register accessor: Reset done. If a bit is set then a reset done signal has been returned by the peripheral. This indicates that the peripheral's registers are ready to be accessed. -You can [`read`](crate::generic::Reg::read) this register and get [`reset_done::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`reset_done::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`reset_done::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@reset_done`] module"] diff --git a/src/resets/reset.rs b/src/resets/reset.rs index 7920fb593..43bf0d422 100644 --- a/src/resets/reset.rs +++ b/src/resets/reset.rs @@ -2,105 +2,105 @@ pub type R = crate::R; #[doc = "Register `RESET` writer"] pub type W = crate::W; -#[doc = "Field `adc` reader - "] +#[doc = "Field `ADC` reader - "] pub type ADC_R = crate::BitReader; -#[doc = "Field `adc` writer - "] +#[doc = "Field `ADC` writer - "] pub type ADC_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `busctrl` reader - "] +#[doc = "Field `BUSCTRL` reader - "] pub type BUSCTRL_R = crate::BitReader; -#[doc = "Field `busctrl` writer - "] +#[doc = "Field `BUSCTRL` writer - "] pub type BUSCTRL_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `dma` reader - "] +#[doc = "Field `DMA` reader - "] pub type DMA_R = crate::BitReader; -#[doc = "Field `dma` writer - "] +#[doc = "Field `DMA` writer - "] pub type DMA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `i2c0` reader - "] +#[doc = "Field `I2C0` reader - "] pub type I2C0_R = crate::BitReader; -#[doc = "Field `i2c0` writer - "] +#[doc = "Field `I2C0` writer - "] pub type I2C0_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `i2c1` reader - "] +#[doc = "Field `I2C1` reader - "] pub type I2C1_R = crate::BitReader; -#[doc = "Field `i2c1` writer - "] +#[doc = "Field `I2C1` writer - "] pub type I2C1_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `io_bank0` reader - "] +#[doc = "Field `IO_BANK0` reader - "] pub type IO_BANK0_R = crate::BitReader; -#[doc = "Field `io_bank0` writer - "] +#[doc = "Field `IO_BANK0` writer - "] pub type IO_BANK0_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `io_qspi` reader - "] +#[doc = "Field `IO_QSPI` reader - "] pub type IO_QSPI_R = crate::BitReader; -#[doc = "Field `io_qspi` writer - "] +#[doc = "Field `IO_QSPI` writer - "] pub type IO_QSPI_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `jtag` reader - "] +#[doc = "Field `JTAG` reader - "] pub type JTAG_R = crate::BitReader; -#[doc = "Field `jtag` writer - "] +#[doc = "Field `JTAG` writer - "] pub type JTAG_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `pads_bank0` reader - "] +#[doc = "Field `PADS_BANK0` reader - "] pub type PADS_BANK0_R = crate::BitReader; -#[doc = "Field `pads_bank0` writer - "] +#[doc = "Field `PADS_BANK0` writer - "] pub type PADS_BANK0_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `pads_qspi` reader - "] +#[doc = "Field `PADS_QSPI` reader - "] pub type PADS_QSPI_R = crate::BitReader; -#[doc = "Field `pads_qspi` writer - "] +#[doc = "Field `PADS_QSPI` writer - "] pub type PADS_QSPI_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `pio0` reader - "] +#[doc = "Field `PIO0` reader - "] pub type PIO0_R = crate::BitReader; -#[doc = "Field `pio0` writer - "] +#[doc = "Field `PIO0` writer - "] pub type PIO0_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `pio1` reader - "] +#[doc = "Field `PIO1` reader - "] pub type PIO1_R = crate::BitReader; -#[doc = "Field `pio1` writer - "] +#[doc = "Field `PIO1` writer - "] pub type PIO1_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `pll_sys` reader - "] +#[doc = "Field `PLL_SYS` reader - "] pub type PLL_SYS_R = crate::BitReader; -#[doc = "Field `pll_sys` writer - "] +#[doc = "Field `PLL_SYS` writer - "] pub type PLL_SYS_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `pll_usb` reader - "] +#[doc = "Field `PLL_USB` reader - "] pub type PLL_USB_R = crate::BitReader; -#[doc = "Field `pll_usb` writer - "] +#[doc = "Field `PLL_USB` writer - "] pub type PLL_USB_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `pwm` reader - "] +#[doc = "Field `PWM` reader - "] pub type PWM_R = crate::BitReader; -#[doc = "Field `pwm` writer - "] +#[doc = "Field `PWM` writer - "] pub type PWM_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `rtc` reader - "] +#[doc = "Field `RTC` reader - "] pub type RTC_R = crate::BitReader; -#[doc = "Field `rtc` writer - "] +#[doc = "Field `RTC` writer - "] pub type RTC_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi0` reader - "] +#[doc = "Field `SPI0` reader - "] pub type SPI0_R = crate::BitReader; -#[doc = "Field `spi0` writer - "] +#[doc = "Field `SPI0` writer - "] pub type SPI0_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi1` reader - "] +#[doc = "Field `SPI1` reader - "] pub type SPI1_R = crate::BitReader; -#[doc = "Field `spi1` writer - "] +#[doc = "Field `SPI1` writer - "] pub type SPI1_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `syscfg` reader - "] +#[doc = "Field `SYSCFG` reader - "] pub type SYSCFG_R = crate::BitReader; -#[doc = "Field `syscfg` writer - "] +#[doc = "Field `SYSCFG` writer - "] pub type SYSCFG_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `sysinfo` reader - "] +#[doc = "Field `SYSINFO` reader - "] pub type SYSINFO_R = crate::BitReader; -#[doc = "Field `sysinfo` writer - "] +#[doc = "Field `SYSINFO` writer - "] pub type SYSINFO_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `tbman` reader - "] +#[doc = "Field `TBMAN` reader - "] pub type TBMAN_R = crate::BitReader; -#[doc = "Field `tbman` writer - "] +#[doc = "Field `TBMAN` writer - "] pub type TBMAN_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `timer` reader - "] +#[doc = "Field `TIMER` reader - "] pub type TIMER_R = crate::BitReader; -#[doc = "Field `timer` writer - "] +#[doc = "Field `TIMER` writer - "] pub type TIMER_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `uart0` reader - "] +#[doc = "Field `UART0` reader - "] pub type UART0_R = crate::BitReader; -#[doc = "Field `uart0` writer - "] +#[doc = "Field `UART0` writer - "] pub type UART0_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `uart1` reader - "] +#[doc = "Field `UART1` reader - "] pub type UART1_R = crate::BitReader; -#[doc = "Field `uart1` writer - "] +#[doc = "Field `UART1` writer - "] pub type UART1_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `usbctrl` reader - "] +#[doc = "Field `USBCTRL` reader - "] pub type USBCTRL_R = crate::BitReader; -#[doc = "Field `usbctrl` writer - "] +#[doc = "Field `USBCTRL` writer - "] pub type USBCTRL_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0"] diff --git a/src/resets/reset_done.rs b/src/resets/reset_done.rs index 0d9d16f76..41922f87f 100644 --- a/src/resets/reset_done.rs +++ b/src/resets/reset_done.rs @@ -1,54 +1,56 @@ #[doc = "Register `RESET_DONE` reader"] pub type R = crate::R; -#[doc = "Field `adc` reader - "] +#[doc = "Register `RESET_DONE` writer"] +pub type W = crate::W; +#[doc = "Field `ADC` reader - "] pub type ADC_R = crate::BitReader; -#[doc = "Field `busctrl` reader - "] +#[doc = "Field `BUSCTRL` reader - "] pub type BUSCTRL_R = crate::BitReader; -#[doc = "Field `dma` reader - "] +#[doc = "Field `DMA` reader - "] pub type DMA_R = crate::BitReader; -#[doc = "Field `i2c0` reader - "] +#[doc = "Field `I2C0` reader - "] pub type I2C0_R = crate::BitReader; -#[doc = "Field `i2c1` reader - "] +#[doc = "Field `I2C1` reader - "] pub type I2C1_R = crate::BitReader; -#[doc = "Field `io_bank0` reader - "] +#[doc = "Field `IO_BANK0` reader - "] pub type IO_BANK0_R = crate::BitReader; -#[doc = "Field `io_qspi` reader - "] +#[doc = "Field `IO_QSPI` reader - "] pub type IO_QSPI_R = crate::BitReader; -#[doc = "Field `jtag` reader - "] +#[doc = "Field `JTAG` reader - "] pub type JTAG_R = crate::BitReader; -#[doc = "Field `pads_bank0` reader - "] +#[doc = "Field `PADS_BANK0` reader - "] pub type PADS_BANK0_R = crate::BitReader; -#[doc = "Field `pads_qspi` reader - "] +#[doc = "Field `PADS_QSPI` reader - "] pub type PADS_QSPI_R = crate::BitReader; -#[doc = "Field `pio0` reader - "] +#[doc = "Field `PIO0` reader - "] pub type PIO0_R = crate::BitReader; -#[doc = "Field `pio1` reader - "] +#[doc = "Field `PIO1` reader - "] pub type PIO1_R = crate::BitReader; -#[doc = "Field `pll_sys` reader - "] +#[doc = "Field `PLL_SYS` reader - "] pub type PLL_SYS_R = crate::BitReader; -#[doc = "Field `pll_usb` reader - "] +#[doc = "Field `PLL_USB` reader - "] pub type PLL_USB_R = crate::BitReader; -#[doc = "Field `pwm` reader - "] +#[doc = "Field `PWM` reader - "] pub type PWM_R = crate::BitReader; -#[doc = "Field `rtc` reader - "] +#[doc = "Field `RTC` reader - "] pub type RTC_R = crate::BitReader; -#[doc = "Field `spi0` reader - "] +#[doc = "Field `SPI0` reader - "] pub type SPI0_R = crate::BitReader; -#[doc = "Field `spi1` reader - "] +#[doc = "Field `SPI1` reader - "] pub type SPI1_R = crate::BitReader; -#[doc = "Field `syscfg` reader - "] +#[doc = "Field `SYSCFG` reader - "] pub type SYSCFG_R = crate::BitReader; -#[doc = "Field `sysinfo` reader - "] +#[doc = "Field `SYSINFO` reader - "] pub type SYSINFO_R = crate::BitReader; -#[doc = "Field `tbman` reader - "] +#[doc = "Field `TBMAN` reader - "] pub type TBMAN_R = crate::BitReader; -#[doc = "Field `timer` reader - "] +#[doc = "Field `TIMER` reader - "] pub type TIMER_R = crate::BitReader; -#[doc = "Field `uart0` reader - "] +#[doc = "Field `UART0` reader - "] pub type UART0_R = crate::BitReader; -#[doc = "Field `uart1` reader - "] +#[doc = "Field `UART1` reader - "] pub type UART1_R = crate::BitReader; -#[doc = "Field `usbctrl` reader - "] +#[doc = "Field `USBCTRL` reader - "] pub type USBCTRL_R = crate::BitReader; impl R { #[doc = "Bit 0"] @@ -177,15 +179,22 @@ impl R { USBCTRL_R::new(((self.bits >> 24) & 1) != 0) } } +impl W {} #[doc = "Reset done. If a bit is set then a reset done signal has been returned by the peripheral. This indicates that the peripheral's registers are ready to be accessed. -You can [`read`](crate::generic::Reg::read) this register and get [`reset_done::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`reset_done::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`reset_done::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RESET_DONE_SPEC; impl crate::RegisterSpec for RESET_DONE_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`reset_done::R`](R) reader structure"] impl crate::Readable for RESET_DONE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`reset_done::W`](W) writer structure"] +impl crate::Writable for RESET_DONE_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets RESET_DONE to value 0"] impl crate::Resettable for RESET_DONE_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/resets/wdsel.rs b/src/resets/wdsel.rs index 325379277..94a79a115 100644 --- a/src/resets/wdsel.rs +++ b/src/resets/wdsel.rs @@ -2,105 +2,105 @@ pub type R = crate::R; #[doc = "Register `WDSEL` writer"] pub type W = crate::W; -#[doc = "Field `adc` reader - "] +#[doc = "Field `ADC` reader - "] pub type ADC_R = crate::BitReader; -#[doc = "Field `adc` writer - "] +#[doc = "Field `ADC` writer - "] pub type ADC_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `busctrl` reader - "] +#[doc = "Field `BUSCTRL` reader - "] pub type BUSCTRL_R = crate::BitReader; -#[doc = "Field `busctrl` writer - "] +#[doc = "Field `BUSCTRL` writer - "] pub type BUSCTRL_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `dma` reader - "] +#[doc = "Field `DMA` reader - "] pub type DMA_R = crate::BitReader; -#[doc = "Field `dma` writer - "] +#[doc = "Field `DMA` writer - "] pub type DMA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `i2c0` reader - "] +#[doc = "Field `I2C0` reader - "] pub type I2C0_R = crate::BitReader; -#[doc = "Field `i2c0` writer - "] +#[doc = "Field `I2C0` writer - "] pub type I2C0_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `i2c1` reader - "] +#[doc = "Field `I2C1` reader - "] pub type I2C1_R = crate::BitReader; -#[doc = "Field `i2c1` writer - "] +#[doc = "Field `I2C1` writer - "] pub type I2C1_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `io_bank0` reader - "] +#[doc = "Field `IO_BANK0` reader - "] pub type IO_BANK0_R = crate::BitReader; -#[doc = "Field `io_bank0` writer - "] +#[doc = "Field `IO_BANK0` writer - "] pub type IO_BANK0_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `io_qspi` reader - "] +#[doc = "Field `IO_QSPI` reader - "] pub type IO_QSPI_R = crate::BitReader; -#[doc = "Field `io_qspi` writer - "] +#[doc = "Field `IO_QSPI` writer - "] pub type IO_QSPI_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `jtag` reader - "] +#[doc = "Field `JTAG` reader - "] pub type JTAG_R = crate::BitReader; -#[doc = "Field `jtag` writer - "] +#[doc = "Field `JTAG` writer - "] pub type JTAG_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `pads_bank0` reader - "] +#[doc = "Field `PADS_BANK0` reader - "] pub type PADS_BANK0_R = crate::BitReader; -#[doc = "Field `pads_bank0` writer - "] +#[doc = "Field `PADS_BANK0` writer - "] pub type PADS_BANK0_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `pads_qspi` reader - "] +#[doc = "Field `PADS_QSPI` reader - "] pub type PADS_QSPI_R = crate::BitReader; -#[doc = "Field `pads_qspi` writer - "] +#[doc = "Field `PADS_QSPI` writer - "] pub type PADS_QSPI_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `pio0` reader - "] +#[doc = "Field `PIO0` reader - "] pub type PIO0_R = crate::BitReader; -#[doc = "Field `pio0` writer - "] +#[doc = "Field `PIO0` writer - "] pub type PIO0_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `pio1` reader - "] +#[doc = "Field `PIO1` reader - "] pub type PIO1_R = crate::BitReader; -#[doc = "Field `pio1` writer - "] +#[doc = "Field `PIO1` writer - "] pub type PIO1_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `pll_sys` reader - "] +#[doc = "Field `PLL_SYS` reader - "] pub type PLL_SYS_R = crate::BitReader; -#[doc = "Field `pll_sys` writer - "] +#[doc = "Field `PLL_SYS` writer - "] pub type PLL_SYS_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `pll_usb` reader - "] +#[doc = "Field `PLL_USB` reader - "] pub type PLL_USB_R = crate::BitReader; -#[doc = "Field `pll_usb` writer - "] +#[doc = "Field `PLL_USB` writer - "] pub type PLL_USB_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `pwm` reader - "] +#[doc = "Field `PWM` reader - "] pub type PWM_R = crate::BitReader; -#[doc = "Field `pwm` writer - "] +#[doc = "Field `PWM` writer - "] pub type PWM_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `rtc` reader - "] +#[doc = "Field `RTC` reader - "] pub type RTC_R = crate::BitReader; -#[doc = "Field `rtc` writer - "] +#[doc = "Field `RTC` writer - "] pub type RTC_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi0` reader - "] +#[doc = "Field `SPI0` reader - "] pub type SPI0_R = crate::BitReader; -#[doc = "Field `spi0` writer - "] +#[doc = "Field `SPI0` writer - "] pub type SPI0_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `spi1` reader - "] +#[doc = "Field `SPI1` reader - "] pub type SPI1_R = crate::BitReader; -#[doc = "Field `spi1` writer - "] +#[doc = "Field `SPI1` writer - "] pub type SPI1_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `syscfg` reader - "] +#[doc = "Field `SYSCFG` reader - "] pub type SYSCFG_R = crate::BitReader; -#[doc = "Field `syscfg` writer - "] +#[doc = "Field `SYSCFG` writer - "] pub type SYSCFG_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `sysinfo` reader - "] +#[doc = "Field `SYSINFO` reader - "] pub type SYSINFO_R = crate::BitReader; -#[doc = "Field `sysinfo` writer - "] +#[doc = "Field `SYSINFO` writer - "] pub type SYSINFO_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `tbman` reader - "] +#[doc = "Field `TBMAN` reader - "] pub type TBMAN_R = crate::BitReader; -#[doc = "Field `tbman` writer - "] +#[doc = "Field `TBMAN` writer - "] pub type TBMAN_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `timer` reader - "] +#[doc = "Field `TIMER` reader - "] pub type TIMER_R = crate::BitReader; -#[doc = "Field `timer` writer - "] +#[doc = "Field `TIMER` writer - "] pub type TIMER_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `uart0` reader - "] +#[doc = "Field `UART0` reader - "] pub type UART0_R = crate::BitReader; -#[doc = "Field `uart0` writer - "] +#[doc = "Field `UART0` writer - "] pub type UART0_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `uart1` reader - "] +#[doc = "Field `UART1` reader - "] pub type UART1_R = crate::BitReader; -#[doc = "Field `uart1` writer - "] +#[doc = "Field `UART1` writer - "] pub type UART1_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `usbctrl` reader - "] +#[doc = "Field `USBCTRL` reader - "] pub type USBCTRL_R = crate::BitReader; -#[doc = "Field `usbctrl` writer - "] +#[doc = "Field `USBCTRL` writer - "] pub type USBCTRL_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0"] diff --git a/src/rosc.rs b/src/rosc.rs index 35c81fc3e..379d1fba0 100644 --- a/src/rosc.rs +++ b/src/rosc.rs @@ -16,13 +16,7 @@ impl RegisterBlock { pub const fn ctrl(&self) -> &CTRL { &self.ctrl } - #[doc = "0x04 - The FREQA & FREQB registers control the frequency by controlling the drive strength of each stage - The drive strength has 4 levels determined by the number of bits set - Increasing the number of bits set increases the drive strength and increases the oscillation frequency - 0 bits set is the default drive strength - 1 bit set doubles the drive strength - 2 bits set triples drive strength - 3 bits set quadruples drive strength"] + #[doc = "0x04 - The FREQA & FREQB registers control the frequency by controlling the drive strength of each stage The drive strength has 4 levels determined by the number of bits set Increasing the number of bits set increases the drive strength and increases the oscillation frequency 0 bits set is the default drive strength 1 bit set doubles the drive strength 2 bits set triples drive strength 3 bits set quadruples drive strength"] #[inline(always)] pub const fn freqa(&self) -> &FREQA { &self.freqa @@ -32,11 +26,7 @@ impl RegisterBlock { pub const fn freqb(&self) -> &FREQB { &self.freqb } - #[doc = "0x0c - Ring Oscillator pause control - This is used to save power by pausing the ROSC - On power-up this field is initialised to WAKE - An invalid write will also select WAKE - Warning: setup the irq before selecting dormant mode"] + #[doc = "0x0c - Ring Oscillator pause control"] #[inline(always)] pub const fn dormant(&self) -> &DORMANT { &self.dormant @@ -71,26 +61,14 @@ module"] pub type CTRL = crate::Reg; #[doc = "Ring Oscillator control"] pub mod ctrl; -#[doc = "FREQA (rw) register accessor: The FREQA & FREQB registers control the frequency by controlling the drive strength of each stage - The drive strength has 4 levels determined by the number of bits set - Increasing the number of bits set increases the drive strength and increases the oscillation frequency - 0 bits set is the default drive strength - 1 bit set doubles the drive strength - 2 bits set triples drive strength - 3 bits set quadruples drive strength +#[doc = "FREQA (rw) register accessor: The FREQA & FREQB registers control the frequency by controlling the drive strength of each stage The drive strength has 4 levels determined by the number of bits set Increasing the number of bits set increases the drive strength and increases the oscillation frequency 0 bits set is the default drive strength 1 bit set doubles the drive strength 2 bits set triples drive strength 3 bits set quadruples drive strength You can [`read`](crate::generic::Reg::read) this register and get [`freqa::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`freqa::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@freqa`] module"] pub type FREQA = crate::Reg; -#[doc = "The FREQA & FREQB registers control the frequency by controlling the drive strength of each stage - The drive strength has 4 levels determined by the number of bits set - Increasing the number of bits set increases the drive strength and increases the oscillation frequency - 0 bits set is the default drive strength - 1 bit set doubles the drive strength - 2 bits set triples drive strength - 3 bits set quadruples drive strength"] +#[doc = "The FREQA & FREQB registers control the frequency by controlling the drive strength of each stage The drive strength has 4 levels determined by the number of bits set Increasing the number of bits set increases the drive strength and increases the oscillation frequency 0 bits set is the default drive strength 1 bit set doubles the drive strength 2 bits set triples drive strength 3 bits set quadruples drive strength"] pub mod freqa; #[doc = "FREQB (rw) register accessor: For a detailed description see freqa register @@ -102,21 +80,13 @@ pub type FREQB = crate::Reg; #[doc = "For a detailed description see freqa register"] pub mod freqb; #[doc = "DORMANT (rw) register accessor: Ring Oscillator pause control - This is used to save power by pausing the ROSC - On power-up this field is initialised to WAKE - An invalid write will also select WAKE - Warning: setup the irq before selecting dormant mode You can [`read`](crate::generic::Reg::read) this register and get [`dormant::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dormant::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@dormant`] module"] pub type DORMANT = crate::Reg; -#[doc = "Ring Oscillator pause control - This is used to save power by pausing the ROSC - On power-up this field is initialised to WAKE - An invalid write will also select WAKE - Warning: setup the irq before selecting dormant mode"] +#[doc = "Ring Oscillator pause control"] pub mod dormant; #[doc = "DIV (rw) register accessor: Controls the output divider @@ -136,18 +106,18 @@ module"] pub type PHASE = crate::Reg; #[doc = "Controls the phase shifted output"] pub mod phase; -#[doc = "RANDOMBIT (r) register accessor: This just reads the state of the oscillator output so randomness is compromised if the ring oscillator is stopped or run at a harmonic of the bus frequency +#[doc = "RANDOMBIT (rw) register accessor: This just reads the state of the oscillator output so randomness is compromised if the ring oscillator is stopped or run at a harmonic of the bus frequency -You can [`read`](crate::generic::Reg::read) this register and get [`randombit::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`randombit::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`randombit::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@randombit`] module"] pub type RANDOMBIT = crate::Reg; #[doc = "This just reads the state of the oscillator output so randomness is compromised if the ring oscillator is stopped or run at a harmonic of the bus frequency"] pub mod randombit; -#[doc = "STATUS (r) register accessor: Ring Oscillator Status +#[doc = "STATUS (rw) register accessor: Ring Oscillator Status -You can [`read`](crate::generic::Reg::read) this register and get [`status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@status`] module"] diff --git a/src/rosc/ctrl.rs b/src/rosc/ctrl.rs index 66bbef5e0..1d67a4bb9 100644 --- a/src/rosc/ctrl.rs +++ b/src/rosc/ctrl.rs @@ -2,14 +2,7 @@ pub type R = crate::R; #[doc = "Register `CTRL` writer"] pub type W = crate::W; -#[doc = "Controls the number of delay stages in the ROSC ring - LOW uses stages 0 to 7 - MEDIUM uses stages 0 to 5 - HIGH uses stages 0 to 3 - TOOHIGH uses stages 0 to 1 and should not be used because its frequency exceeds design specifications - The clock output will not glitch when changing the range up one step at a time - The clock output will glitch when changing the range down - Note: the values here are gray coded which is why HIGH comes before TOOHIGH +#[doc = "Controls the number of delay stages in the ROSC ring LOW uses stages 0 to 7 MEDIUM uses stages 2 to 7 HIGH uses stages 4 to 7 TOOHIGH uses stages 6 to 7 and should not be used because its frequency exceeds design specifications The clock output will not glitch when changing the range up one step at a time The clock output will glitch when changing the range down Note: the values here are gray coded which is why HIGH comes before TOOHIGH Value on reset: 2720"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -33,14 +26,7 @@ impl From for u16 { impl crate::FieldSpec for FREQ_RANGE_A { type Ux = u16; } -#[doc = "Field `FREQ_RANGE` reader - Controls the number of delay stages in the ROSC ring - LOW uses stages 0 to 7 - MEDIUM uses stages 0 to 5 - HIGH uses stages 0 to 3 - TOOHIGH uses stages 0 to 1 and should not be used because its frequency exceeds design specifications - The clock output will not glitch when changing the range up one step at a time - The clock output will glitch when changing the range down - Note: the values here are gray coded which is why HIGH comes before TOOHIGH"] +#[doc = "Field `FREQ_RANGE` reader - Controls the number of delay stages in the ROSC ring LOW uses stages 0 to 7 MEDIUM uses stages 2 to 7 HIGH uses stages 4 to 7 TOOHIGH uses stages 6 to 7 and should not be used because its frequency exceeds design specifications The clock output will not glitch when changing the range up one step at a time The clock output will glitch when changing the range down Note: the values here are gray coded which is why HIGH comes before TOOHIGH"] pub type FREQ_RANGE_R = crate::FieldReader; impl FREQ_RANGE_R { #[doc = "Get enumerated values variant"] @@ -75,14 +61,7 @@ impl FREQ_RANGE_R { *self == FREQ_RANGE_A::TOOHIGH } } -#[doc = "Field `FREQ_RANGE` writer - Controls the number of delay stages in the ROSC ring - LOW uses stages 0 to 7 - MEDIUM uses stages 0 to 5 - HIGH uses stages 0 to 3 - TOOHIGH uses stages 0 to 1 and should not be used because its frequency exceeds design specifications - The clock output will not glitch when changing the range up one step at a time - The clock output will glitch when changing the range down - Note: the values here are gray coded which is why HIGH comes before TOOHIGH"] +#[doc = "Field `FREQ_RANGE` writer - Controls the number of delay stages in the ROSC ring LOW uses stages 0 to 7 MEDIUM uses stages 2 to 7 HIGH uses stages 4 to 7 TOOHIGH uses stages 6 to 7 and should not be used because its frequency exceeds design specifications The clock output will not glitch when changing the range up one step at a time The clock output will glitch when changing the range down Note: the values here are gray coded which is why HIGH comes before TOOHIGH"] pub type FREQ_RANGE_W<'a, REG> = crate::FieldWriter<'a, REG, 12, FREQ_RANGE_A>; impl<'a, REG> FREQ_RANGE_W<'a, REG> where @@ -110,9 +89,7 @@ where self.variant(FREQ_RANGE_A::TOOHIGH) } } -#[doc = "On power-up this field is initialised to ENABLE - The system clock must be switched to another source before setting this field to DISABLE otherwise the chip will lock up - The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator. +#[doc = "On power-up this field is initialised to ENABLE The system clock must be switched to another source before setting this field to DISABLE otherwise the chip will lock up The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator. Value on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -132,9 +109,7 @@ impl From for u16 { impl crate::FieldSpec for ENABLE_A { type Ux = u16; } -#[doc = "Field `ENABLE` reader - On power-up this field is initialised to ENABLE - The system clock must be switched to another source before setting this field to DISABLE otherwise the chip will lock up - The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator."] +#[doc = "Field `ENABLE` reader - On power-up this field is initialised to ENABLE The system clock must be switched to another source before setting this field to DISABLE otherwise the chip will lock up The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator."] pub type ENABLE_R = crate::FieldReader; impl ENABLE_R { #[doc = "Get enumerated values variant"] @@ -157,9 +132,7 @@ impl ENABLE_R { *self == ENABLE_A::ENABLE } } -#[doc = "Field `ENABLE` writer - On power-up this field is initialised to ENABLE - The system clock must be switched to another source before setting this field to DISABLE otherwise the chip will lock up - The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator."] +#[doc = "Field `ENABLE` writer - On power-up this field is initialised to ENABLE The system clock must be switched to another source before setting this field to DISABLE otherwise the chip will lock up The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator."] pub type ENABLE_W<'a, REG> = crate::FieldWriter<'a, REG, 12, ENABLE_A>; impl<'a, REG> ENABLE_W<'a, REG> where @@ -178,43 +151,25 @@ where } } impl R { - #[doc = "Bits 0:11 - Controls the number of delay stages in the ROSC ring - LOW uses stages 0 to 7 - MEDIUM uses stages 0 to 5 - HIGH uses stages 0 to 3 - TOOHIGH uses stages 0 to 1 and should not be used because its frequency exceeds design specifications - The clock output will not glitch when changing the range up one step at a time - The clock output will glitch when changing the range down - Note: the values here are gray coded which is why HIGH comes before TOOHIGH"] + #[doc = "Bits 0:11 - Controls the number of delay stages in the ROSC ring LOW uses stages 0 to 7 MEDIUM uses stages 2 to 7 HIGH uses stages 4 to 7 TOOHIGH uses stages 6 to 7 and should not be used because its frequency exceeds design specifications The clock output will not glitch when changing the range up one step at a time The clock output will glitch when changing the range down Note: the values here are gray coded which is why HIGH comes before TOOHIGH"] #[inline(always)] pub fn freq_range(&self) -> FREQ_RANGE_R { FREQ_RANGE_R::new((self.bits & 0x0fff) as u16) } - #[doc = "Bits 12:23 - On power-up this field is initialised to ENABLE - The system clock must be switched to another source before setting this field to DISABLE otherwise the chip will lock up - The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator."] + #[doc = "Bits 12:23 - On power-up this field is initialised to ENABLE The system clock must be switched to another source before setting this field to DISABLE otherwise the chip will lock up The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator."] #[inline(always)] pub fn enable(&self) -> ENABLE_R { ENABLE_R::new(((self.bits >> 12) & 0x0fff) as u16) } } impl W { - #[doc = "Bits 0:11 - Controls the number of delay stages in the ROSC ring - LOW uses stages 0 to 7 - MEDIUM uses stages 0 to 5 - HIGH uses stages 0 to 3 - TOOHIGH uses stages 0 to 1 and should not be used because its frequency exceeds design specifications - The clock output will not glitch when changing the range up one step at a time - The clock output will glitch when changing the range down - Note: the values here are gray coded which is why HIGH comes before TOOHIGH"] + #[doc = "Bits 0:11 - Controls the number of delay stages in the ROSC ring LOW uses stages 0 to 7 MEDIUM uses stages 2 to 7 HIGH uses stages 4 to 7 TOOHIGH uses stages 6 to 7 and should not be used because its frequency exceeds design specifications The clock output will not glitch when changing the range up one step at a time The clock output will glitch when changing the range down Note: the values here are gray coded which is why HIGH comes before TOOHIGH"] #[inline(always)] #[must_use] pub fn freq_range(&mut self) -> FREQ_RANGE_W { FREQ_RANGE_W::new(self, 0) } - #[doc = "Bits 12:23 - On power-up this field is initialised to ENABLE - The system clock must be switched to another source before setting this field to DISABLE otherwise the chip will lock up - The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator."] + #[doc = "Bits 12:23 - On power-up this field is initialised to ENABLE The system clock must be switched to another source before setting this field to DISABLE otherwise the chip will lock up The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator."] #[inline(always)] #[must_use] pub fn enable(&mut self) -> ENABLE_W { diff --git a/src/rosc/div.rs b/src/rosc/div.rs index d79cf2155..dd63451e3 100644 --- a/src/rosc/div.rs +++ b/src/rosc/div.rs @@ -2,11 +2,7 @@ pub type R = crate::R; #[doc = "Register `DIV` writer"] pub type W = crate::W; -#[doc = "set to 0xaa0 + div where - div = 0 divides by 32 - div = 1-31 divides by div - any other value sets div=31 - this register resets to div=16 +#[doc = "set to 0xaa0 + div where div = 0 divides by 32 div = 1-31 divides by div any other value sets div=31 this register resets to div=16 Value on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -24,11 +20,7 @@ impl From for u16 { impl crate::FieldSpec for DIV_A { type Ux = u16; } -#[doc = "Field `DIV` reader - set to 0xaa0 + div where - div = 0 divides by 32 - div = 1-31 divides by div - any other value sets div=31 - this register resets to div=16"] +#[doc = "Field `DIV` reader - set to 0xaa0 + div where div = 0 divides by 32 div = 1-31 divides by div any other value sets div=31 this register resets to div=16"] pub type DIV_R = crate::FieldReader; impl DIV_R { #[doc = "Get enumerated values variant"] @@ -45,11 +37,7 @@ impl DIV_R { *self == DIV_A::PASS } } -#[doc = "Field `DIV` writer - set to 0xaa0 + div where - div = 0 divides by 32 - div = 1-31 divides by div - any other value sets div=31 - this register resets to div=16"] +#[doc = "Field `DIV` writer - set to 0xaa0 + div where div = 0 divides by 32 div = 1-31 divides by div any other value sets div=31 this register resets to div=16"] pub type DIV_W<'a, REG> = crate::FieldWriter<'a, REG, 12, DIV_A>; impl<'a, REG> DIV_W<'a, REG> where @@ -63,22 +51,14 @@ where } } impl R { - #[doc = "Bits 0:11 - set to 0xaa0 + div where - div = 0 divides by 32 - div = 1-31 divides by div - any other value sets div=31 - this register resets to div=16"] + #[doc = "Bits 0:11 - set to 0xaa0 + div where div = 0 divides by 32 div = 1-31 divides by div any other value sets div=31 this register resets to div=16"] #[inline(always)] pub fn div(&self) -> DIV_R { DIV_R::new((self.bits & 0x0fff) as u16) } } impl W { - #[doc = "Bits 0:11 - set to 0xaa0 + div where - div = 0 divides by 32 - div = 1-31 divides by div - any other value sets div=31 - this register resets to div=16"] + #[doc = "Bits 0:11 - set to 0xaa0 + div where div = 0 divides by 32 div = 1-31 divides by div any other value sets div=31 this register resets to div=16"] #[inline(always)] #[must_use] pub fn div(&mut self) -> DIV_W { diff --git a/src/rosc/dormant.rs b/src/rosc/dormant.rs index 1697d4d00..1d5c9b3af 100644 --- a/src/rosc/dormant.rs +++ b/src/rosc/dormant.rs @@ -2,22 +2,83 @@ pub type R = crate::R; #[doc = "Register `DORMANT` writer"] pub type W = crate::W; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) +#[doc = "This is used to save power by pausing the ROSC On power-up this field is initialised to WAKE An invalid write will also select WAKE Warning: setup the irq before selecting dormant mode + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u32)] +pub enum DORMANT_A { + #[doc = "1668246881: `1100011011011110110110101100001`"] + DORMANT = 1668246881, + #[doc = "2002873189: `1110111011000010110101101100101`"] + WAKE = 2002873189, +} +impl From for u32 { + #[inline(always)] + fn from(variant: DORMANT_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for DORMANT_A { + type Ux = u32; +} +#[doc = "Field `DORMANT` reader - This is used to save power by pausing the ROSC On power-up this field is initialised to WAKE An invalid write will also select WAKE Warning: setup the irq before selecting dormant mode"] +pub type DORMANT_R = crate::FieldReader; +impl DORMANT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1668246881 => Some(DORMANT_A::DORMANT), + 2002873189 => Some(DORMANT_A::WAKE), + _ => None, + } + } + #[doc = "`1100011011011110110110101100001`"] + #[inline(always)] + pub fn is_dormant(&self) -> bool { + *self == DORMANT_A::DORMANT + } + #[doc = "`1110111011000010110101101100101`"] + #[inline(always)] + pub fn is_wake(&self) -> bool { + *self == DORMANT_A::WAKE + } +} +#[doc = "Field `DORMANT` writer - This is used to save power by pausing the ROSC On power-up this field is initialised to WAKE An invalid write will also select WAKE Warning: setup the irq before selecting dormant mode"] +pub type DORMANT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, DORMANT_A>; +impl<'a, REG> DORMANT_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`1100011011011110110110101100001`"] + #[inline(always)] + pub fn dormant(self) -> &'a mut crate::W { + self.variant(DORMANT_A::DORMANT) + } + #[doc = "`1110111011000010110101101100101`"] + #[inline(always)] + pub fn wake(self) -> &'a mut crate::W { + self.variant(DORMANT_A::WAKE) + } +} +impl R { + #[doc = "Bits 0:31 - This is used to save power by pausing the ROSC On power-up this field is initialised to WAKE An invalid write will also select WAKE Warning: setup the irq before selecting dormant mode"] + #[inline(always)] + pub fn dormant(&self) -> DORMANT_R { + DORMANT_R::new(self.bits) } } -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +impl W { + #[doc = "Bits 0:31 - This is used to save power by pausing the ROSC On power-up this field is initialised to WAKE An invalid write will also select WAKE Warning: setup the irq before selecting dormant mode"] + #[inline(always)] + #[must_use] + pub fn dormant(&mut self) -> DORMANT_W { + DORMANT_W::new(self, 0) } } -impl W {} #[doc = "Ring Oscillator pause control - This is used to save power by pausing the ROSC - On power-up this field is initialised to WAKE - An invalid write will also select WAKE - Warning: setup the irq before selecting dormant mode You can [`read`](crate::generic::Reg::read) this register and get [`dormant::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dormant::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DORMANT_SPEC; diff --git a/src/rosc/freqa.rs b/src/rosc/freqa.rs index d7c9b6476..a231da175 100644 --- a/src/rosc/freqa.rs +++ b/src/rosc/freqa.rs @@ -18,8 +18,7 @@ pub type DS2_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; pub type DS3_R = crate::FieldReader; #[doc = "Field `DS3` writer - Stage 3 drive strength"] pub type DS3_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; -#[doc = "Set to 0x9696 to apply the settings - Any other value in this field will set all drive strengths to 0 +#[doc = "Set to 0x9696 to apply the settings Any other value in this field will set all drive strengths to 0 Value on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -37,8 +36,7 @@ impl From for u16 { impl crate::FieldSpec for PASSWD_A { type Ux = u16; } -#[doc = "Field `PASSWD` reader - Set to 0x9696 to apply the settings - Any other value in this field will set all drive strengths to 0"] +#[doc = "Field `PASSWD` reader - Set to 0x9696 to apply the settings Any other value in this field will set all drive strengths to 0"] pub type PASSWD_R = crate::FieldReader; impl PASSWD_R { #[doc = "Get enumerated values variant"] @@ -55,8 +53,7 @@ impl PASSWD_R { *self == PASSWD_A::PASS } } -#[doc = "Field `PASSWD` writer - Set to 0x9696 to apply the settings - Any other value in this field will set all drive strengths to 0"] +#[doc = "Field `PASSWD` writer - Set to 0x9696 to apply the settings Any other value in this field will set all drive strengths to 0"] pub type PASSWD_W<'a, REG> = crate::FieldWriter<'a, REG, 16, PASSWD_A>; impl<'a, REG> PASSWD_W<'a, REG> where @@ -90,8 +87,7 @@ impl R { pub fn ds3(&self) -> DS3_R { DS3_R::new(((self.bits >> 12) & 7) as u8) } - #[doc = "Bits 16:31 - Set to 0x9696 to apply the settings - Any other value in this field will set all drive strengths to 0"] + #[doc = "Bits 16:31 - Set to 0x9696 to apply the settings Any other value in this field will set all drive strengths to 0"] #[inline(always)] pub fn passwd(&self) -> PASSWD_R { PASSWD_R::new(((self.bits >> 16) & 0xffff) as u16) @@ -122,21 +118,14 @@ impl W { pub fn ds3(&mut self) -> DS3_W { DS3_W::new(self, 12) } - #[doc = "Bits 16:31 - Set to 0x9696 to apply the settings - Any other value in this field will set all drive strengths to 0"] + #[doc = "Bits 16:31 - Set to 0x9696 to apply the settings Any other value in this field will set all drive strengths to 0"] #[inline(always)] #[must_use] pub fn passwd(&mut self) -> PASSWD_W { PASSWD_W::new(self, 16) } } -#[doc = "The FREQA & FREQB registers control the frequency by controlling the drive strength of each stage - The drive strength has 4 levels determined by the number of bits set - Increasing the number of bits set increases the drive strength and increases the oscillation frequency - 0 bits set is the default drive strength - 1 bit set doubles the drive strength - 2 bits set triples drive strength - 3 bits set quadruples drive strength +#[doc = "The FREQA & FREQB registers control the frequency by controlling the drive strength of each stage The drive strength has 4 levels determined by the number of bits set Increasing the number of bits set increases the drive strength and increases the oscillation frequency 0 bits set is the default drive strength 1 bit set doubles the drive strength 2 bits set triples drive strength 3 bits set quadruples drive strength You can [`read`](crate::generic::Reg::read) this register and get [`freqa::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`freqa::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FREQA_SPEC; diff --git a/src/rosc/freqb.rs b/src/rosc/freqb.rs index c87b40ad0..afd2eb4a4 100644 --- a/src/rosc/freqb.rs +++ b/src/rosc/freqb.rs @@ -18,8 +18,7 @@ pub type DS6_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; pub type DS7_R = crate::FieldReader; #[doc = "Field `DS7` writer - Stage 7 drive strength"] pub type DS7_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; -#[doc = "Set to 0x9696 to apply the settings - Any other value in this field will set all drive strengths to 0 +#[doc = "Set to 0x9696 to apply the settings Any other value in this field will set all drive strengths to 0 Value on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -37,8 +36,7 @@ impl From for u16 { impl crate::FieldSpec for PASSWD_A { type Ux = u16; } -#[doc = "Field `PASSWD` reader - Set to 0x9696 to apply the settings - Any other value in this field will set all drive strengths to 0"] +#[doc = "Field `PASSWD` reader - Set to 0x9696 to apply the settings Any other value in this field will set all drive strengths to 0"] pub type PASSWD_R = crate::FieldReader; impl PASSWD_R { #[doc = "Get enumerated values variant"] @@ -55,8 +53,7 @@ impl PASSWD_R { *self == PASSWD_A::PASS } } -#[doc = "Field `PASSWD` writer - Set to 0x9696 to apply the settings - Any other value in this field will set all drive strengths to 0"] +#[doc = "Field `PASSWD` writer - Set to 0x9696 to apply the settings Any other value in this field will set all drive strengths to 0"] pub type PASSWD_W<'a, REG> = crate::FieldWriter<'a, REG, 16, PASSWD_A>; impl<'a, REG> PASSWD_W<'a, REG> where @@ -90,8 +87,7 @@ impl R { pub fn ds7(&self) -> DS7_R { DS7_R::new(((self.bits >> 12) & 7) as u8) } - #[doc = "Bits 16:31 - Set to 0x9696 to apply the settings - Any other value in this field will set all drive strengths to 0"] + #[doc = "Bits 16:31 - Set to 0x9696 to apply the settings Any other value in this field will set all drive strengths to 0"] #[inline(always)] pub fn passwd(&self) -> PASSWD_R { PASSWD_R::new(((self.bits >> 16) & 0xffff) as u16) @@ -122,8 +118,7 @@ impl W { pub fn ds7(&mut self) -> DS7_W { DS7_W::new(self, 12) } - #[doc = "Bits 16:31 - Set to 0x9696 to apply the settings - Any other value in this field will set all drive strengths to 0"] + #[doc = "Bits 16:31 - Set to 0x9696 to apply the settings Any other value in this field will set all drive strengths to 0"] #[inline(always)] #[must_use] pub fn passwd(&mut self) -> PASSWD_W { diff --git a/src/rosc/phase.rs b/src/rosc/phase.rs index 7275ec351..0847f61cf 100644 --- a/src/rosc/phase.rs +++ b/src/rosc/phase.rs @@ -2,84 +2,64 @@ pub type R = crate::R; #[doc = "Register `PHASE` writer"] pub type W = crate::W; -#[doc = "Field `SHIFT` reader - phase shift the phase-shifted output by SHIFT input clocks - this can be changed on-the-fly - must be set to 0 before setting div=1"] +#[doc = "Field `SHIFT` reader - phase shift the phase-shifted output by SHIFT input clocks this can be changed on-the-fly must be set to 0 before setting div=1"] pub type SHIFT_R = crate::FieldReader; -#[doc = "Field `SHIFT` writer - phase shift the phase-shifted output by SHIFT input clocks - this can be changed on-the-fly - must be set to 0 before setting div=1"] +#[doc = "Field `SHIFT` writer - phase shift the phase-shifted output by SHIFT input clocks this can be changed on-the-fly must be set to 0 before setting div=1"] pub type SHIFT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `FLIP` reader - invert the phase-shifted output - this is ignored when div=1"] +#[doc = "Field `FLIP` reader - invert the phase-shifted output this is ignored when div=1"] pub type FLIP_R = crate::BitReader; -#[doc = "Field `FLIP` writer - invert the phase-shifted output - this is ignored when div=1"] +#[doc = "Field `FLIP` writer - invert the phase-shifted output this is ignored when div=1"] pub type FLIP_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `ENABLE` reader - enable the phase-shifted output - this can be changed on-the-fly"] +#[doc = "Field `ENABLE` reader - enable the phase-shifted output this can be changed on-the-fly"] pub type ENABLE_R = crate::BitReader; -#[doc = "Field `ENABLE` writer - enable the phase-shifted output - this can be changed on-the-fly"] +#[doc = "Field `ENABLE` writer - enable the phase-shifted output this can be changed on-the-fly"] pub type ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `PASSWD` reader - set to 0xaa - any other value enables the output with shift=0"] +#[doc = "Field `PASSWD` reader - set to 0xaa any other value enables the output with shift=0"] pub type PASSWD_R = crate::FieldReader; -#[doc = "Field `PASSWD` writer - set to 0xaa - any other value enables the output with shift=0"] +#[doc = "Field `PASSWD` writer - set to 0xaa any other value enables the output with shift=0"] pub type PASSWD_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; impl R { - #[doc = "Bits 0:1 - phase shift the phase-shifted output by SHIFT input clocks - this can be changed on-the-fly - must be set to 0 before setting div=1"] + #[doc = "Bits 0:1 - phase shift the phase-shifted output by SHIFT input clocks this can be changed on-the-fly must be set to 0 before setting div=1"] #[inline(always)] pub fn shift(&self) -> SHIFT_R { SHIFT_R::new((self.bits & 3) as u8) } - #[doc = "Bit 2 - invert the phase-shifted output - this is ignored when div=1"] + #[doc = "Bit 2 - invert the phase-shifted output this is ignored when div=1"] #[inline(always)] pub fn flip(&self) -> FLIP_R { FLIP_R::new(((self.bits >> 2) & 1) != 0) } - #[doc = "Bit 3 - enable the phase-shifted output - this can be changed on-the-fly"] + #[doc = "Bit 3 - enable the phase-shifted output this can be changed on-the-fly"] #[inline(always)] pub fn enable(&self) -> ENABLE_R { ENABLE_R::new(((self.bits >> 3) & 1) != 0) } - #[doc = "Bits 4:11 - set to 0xaa - any other value enables the output with shift=0"] + #[doc = "Bits 4:11 - set to 0xaa any other value enables the output with shift=0"] #[inline(always)] pub fn passwd(&self) -> PASSWD_R { PASSWD_R::new(((self.bits >> 4) & 0xff) as u8) } } impl W { - #[doc = "Bits 0:1 - phase shift the phase-shifted output by SHIFT input clocks - this can be changed on-the-fly - must be set to 0 before setting div=1"] + #[doc = "Bits 0:1 - phase shift the phase-shifted output by SHIFT input clocks this can be changed on-the-fly must be set to 0 before setting div=1"] #[inline(always)] #[must_use] pub fn shift(&mut self) -> SHIFT_W { SHIFT_W::new(self, 0) } - #[doc = "Bit 2 - invert the phase-shifted output - this is ignored when div=1"] + #[doc = "Bit 2 - invert the phase-shifted output this is ignored when div=1"] #[inline(always)] #[must_use] pub fn flip(&mut self) -> FLIP_W { FLIP_W::new(self, 2) } - #[doc = "Bit 3 - enable the phase-shifted output - this can be changed on-the-fly"] + #[doc = "Bit 3 - enable the phase-shifted output this can be changed on-the-fly"] #[inline(always)] #[must_use] pub fn enable(&mut self) -> ENABLE_W { ENABLE_W::new(self, 3) } - #[doc = "Bits 4:11 - set to 0xaa - any other value enables the output with shift=0"] + #[doc = "Bits 4:11 - set to 0xaa any other value enables the output with shift=0"] #[inline(always)] #[must_use] pub fn passwd(&mut self) -> PASSWD_W { diff --git a/src/rosc/randombit.rs b/src/rosc/randombit.rs index 1dde53a26..f5eae6224 100644 --- a/src/rosc/randombit.rs +++ b/src/rosc/randombit.rs @@ -1,5 +1,7 @@ #[doc = "Register `RANDOMBIT` reader"] pub type R = crate::R; +#[doc = "Register `RANDOMBIT` writer"] +pub type W = crate::W; #[doc = "Field `RANDOMBIT` reader - "] pub type RANDOMBIT_R = crate::BitReader; impl R { @@ -9,15 +11,22 @@ impl R { RANDOMBIT_R::new((self.bits & 1) != 0) } } +impl W {} #[doc = "This just reads the state of the oscillator output so randomness is compromised if the ring oscillator is stopped or run at a harmonic of the bus frequency -You can [`read`](crate::generic::Reg::read) this register and get [`randombit::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`randombit::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`randombit::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RANDOMBIT_SPEC; impl crate::RegisterSpec for RANDOMBIT_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`randombit::R`](R) reader structure"] impl crate::Readable for RANDOMBIT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`randombit::W`](W) writer structure"] +impl crate::Writable for RANDOMBIT_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets RANDOMBIT to value 0x01"] impl crate::Resettable for RANDOMBIT_SPEC { const RESET_VALUE: u32 = 0x01; diff --git a/src/rosc/status.rs b/src/rosc/status.rs index 43f66c678..197adf1be 100644 --- a/src/rosc/status.rs +++ b/src/rosc/status.rs @@ -1,5 +1,7 @@ #[doc = "Register `STATUS` reader"] pub type R = crate::R; +#[doc = "Register `STATUS` writer"] +pub type W = crate::W; #[doc = "Field `ENABLED` reader - Oscillator is enabled but not necessarily running and stable this resets to 0 but transitions to 1 during chip startup"] pub type ENABLED_R = crate::BitReader; #[doc = "Field `DIV_RUNNING` reader - post-divider is running this resets to 0 but transitions to 1 during chip startup"] @@ -23,15 +25,22 @@ impl R { STABLE_R::new(((self.bits >> 31) & 1) != 0) } } +impl W {} #[doc = "Ring Oscillator Status -You can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct STATUS_SPEC; impl crate::RegisterSpec for STATUS_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`status::R`](R) reader structure"] impl crate::Readable for STATUS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`status::W`](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets STATUS to value 0"] impl crate::Resettable for STATUS_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/rtc.rs b/src/rtc.rs index 3cac0834b..86b8aca2e 100644 --- a/src/rtc.rs +++ b/src/rtc.rs @@ -50,8 +50,7 @@ impl RegisterBlock { pub const fn rtc_1(&self) -> &RTC_1 { &self.rtc_1 } - #[doc = "0x1c - RTC register 0 - Read this before RTC 1!"] + #[doc = "0x1c - RTC register 0 Read this before RTC 1!"] #[inline(always)] pub const fn rtc_0(&self) -> &RTC_0 { &self.rtc_0 @@ -131,29 +130,27 @@ module"] pub type IRQ_SETUP_1 = crate::Reg; #[doc = "Interrupt setup register 1"] pub mod irq_setup_1; -#[doc = "RTC_1 (r) register accessor: RTC register 1. +#[doc = "RTC_1 (rw) register accessor: RTC register 1. -You can [`read`](crate::generic::Reg::read) this register and get [`rtc_1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`rtc_1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rtc_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@rtc_1`] module"] pub type RTC_1 = crate::Reg; #[doc = "RTC register 1."] pub mod rtc_1; -#[doc = "RTC_0 (r) register accessor: RTC register 0 - Read this before RTC 1! +#[doc = "RTC_0 (rw) register accessor: RTC register 0 Read this before RTC 1! -You can [`read`](crate::generic::Reg::read) this register and get [`rtc_0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`rtc_0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rtc_0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@rtc_0`] module"] pub type RTC_0 = crate::Reg; -#[doc = "RTC register 0 - Read this before RTC 1!"] +#[doc = "RTC register 0 Read this before RTC 1!"] pub mod rtc_0; -#[doc = "INTR (r) register accessor: Raw Interrupts +#[doc = "INTR (rw) register accessor: Raw Interrupts -You can [`read`](crate::generic::Reg::read) this register and get [`intr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`intr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@intr`] module"] @@ -178,9 +175,9 @@ module"] pub type INTF = crate::Reg; #[doc = "Interrupt Force"] pub mod intf; -#[doc = "INTS (r) register accessor: Interrupt status after masking & forcing +#[doc = "INTS (rw) register accessor: Interrupt status after masking & forcing -You can [`read`](crate::generic::Reg::read) this register and get [`ints::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`ints::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ints::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@ints`] module"] diff --git a/src/rtc/ctrl.rs b/src/rtc/ctrl.rs index c4a46dc86..c9bd34f85 100644 --- a/src/rtc/ctrl.rs +++ b/src/rtc/ctrl.rs @@ -8,15 +8,11 @@ pub type RTC_ENABLE_R = crate::BitReader; pub type RTC_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `RTC_ACTIVE` reader - RTC enabled (running)"] pub type RTC_ACTIVE_R = crate::BitReader; -#[doc = "Field `LOAD` reader - Load RTC"] -pub type LOAD_R = crate::BitReader; #[doc = "Field `LOAD` writer - Load RTC"] pub type LOAD_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `FORCE_NOTLEAPYEAR` reader - If set, leapyear is forced off. - Useful for years divisible by 100 but not by 400"] +#[doc = "Field `FORCE_NOTLEAPYEAR` reader - If set, leapyear is forced off. Useful for years divisible by 100 but not by 400"] pub type FORCE_NOTLEAPYEAR_R = crate::BitReader; -#[doc = "Field `FORCE_NOTLEAPYEAR` writer - If set, leapyear is forced off. - Useful for years divisible by 100 but not by 400"] +#[doc = "Field `FORCE_NOTLEAPYEAR` writer - If set, leapyear is forced off. Useful for years divisible by 100 but not by 400"] pub type FORCE_NOTLEAPYEAR_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - Enable RTC"] @@ -29,13 +25,7 @@ impl R { pub fn rtc_active(&self) -> RTC_ACTIVE_R { RTC_ACTIVE_R::new(((self.bits >> 1) & 1) != 0) } - #[doc = "Bit 4 - Load RTC"] - #[inline(always)] - pub fn load(&self) -> LOAD_R { - LOAD_R::new(((self.bits >> 4) & 1) != 0) - } - #[doc = "Bit 8 - If set, leapyear is forced off. - Useful for years divisible by 100 but not by 400"] + #[doc = "Bit 8 - If set, leapyear is forced off. Useful for years divisible by 100 but not by 400"] #[inline(always)] pub fn force_notleapyear(&self) -> FORCE_NOTLEAPYEAR_R { FORCE_NOTLEAPYEAR_R::new(((self.bits >> 8) & 1) != 0) @@ -54,8 +44,7 @@ impl W { pub fn load(&mut self) -> LOAD_W { LOAD_W::new(self, 4) } - #[doc = "Bit 8 - If set, leapyear is forced off. - Useful for years divisible by 100 but not by 400"] + #[doc = "Bit 8 - If set, leapyear is forced off. Useful for years divisible by 100 but not by 400"] #[inline(always)] #[must_use] pub fn force_notleapyear(&mut self) -> FORCE_NOTLEAPYEAR_W { diff --git a/src/rtc/intr.rs b/src/rtc/intr.rs index a07f8b7cb..8a2750d21 100644 --- a/src/rtc/intr.rs +++ b/src/rtc/intr.rs @@ -1,5 +1,7 @@ #[doc = "Register `INTR` reader"] pub type R = crate::R; +#[doc = "Register `INTR` writer"] +pub type W = crate::W; #[doc = "Field `RTC` reader - "] pub type RTC_R = crate::BitReader; impl R { @@ -9,15 +11,22 @@ impl R { RTC_R::new((self.bits & 1) != 0) } } +impl W {} #[doc = "Raw Interrupts -You can [`read`](crate::generic::Reg::read) this register and get [`intr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`intr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTR_SPEC; impl crate::RegisterSpec for INTR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`intr::R`](R) reader structure"] impl crate::Readable for INTR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`intr::W`](W) writer structure"] +impl crate::Writable for INTR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets INTR to value 0"] impl crate::Resettable for INTR_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/rtc/ints.rs b/src/rtc/ints.rs index 3918c0e92..f1c309386 100644 --- a/src/rtc/ints.rs +++ b/src/rtc/ints.rs @@ -1,5 +1,7 @@ #[doc = "Register `INTS` reader"] pub type R = crate::R; +#[doc = "Register `INTS` writer"] +pub type W = crate::W; #[doc = "Field `RTC` reader - "] pub type RTC_R = crate::BitReader; impl R { @@ -9,15 +11,22 @@ impl R { RTC_R::new((self.bits & 1) != 0) } } +impl W {} #[doc = "Interrupt status after masking & forcing -You can [`read`](crate::generic::Reg::read) this register and get [`ints::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`ints::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ints::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTS_SPEC; impl crate::RegisterSpec for INTS_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`ints::R`](R) reader structure"] impl crate::Readable for INTS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ints::W`](W) writer structure"] +impl crate::Writable for INTS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets INTS to value 0"] impl crate::Resettable for INTS_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/rtc/rtc_0.rs b/src/rtc/rtc_0.rs index 19581fee7..23d47674f 100644 --- a/src/rtc/rtc_0.rs +++ b/src/rtc/rtc_0.rs @@ -1,12 +1,22 @@ #[doc = "Register `RTC_0` reader"] pub type R = crate::R; -#[doc = "Field `SEC` reader - Seconds"] +#[doc = "Register `RTC_0` writer"] +pub type W = crate::W; +#[doc = "Field `SEC` reader - Seconds + +The field is **modified** in some way after a read operation."] pub type SEC_R = crate::FieldReader; -#[doc = "Field `MIN` reader - Minutes"] +#[doc = "Field `MIN` reader - Minutes + +The field is **modified** in some way after a read operation."] pub type MIN_R = crate::FieldReader; -#[doc = "Field `HOUR` reader - Hours"] +#[doc = "Field `HOUR` reader - Hours + +The field is **modified** in some way after a read operation."] pub type HOUR_R = crate::FieldReader; -#[doc = "Field `DOTW` reader - Day of the week"] +#[doc = "Field `DOTW` reader - Day of the week + +The field is **modified** in some way after a read operation."] pub type DOTW_R = crate::FieldReader; impl R { #[doc = "Bits 0:5 - Seconds"] @@ -30,16 +40,22 @@ impl R { DOTW_R::new(((self.bits >> 24) & 7) as u8) } } -#[doc = "RTC register 0 - Read this before RTC 1! +impl W {} +#[doc = "RTC register 0 Read this before RTC 1! -You can [`read`](crate::generic::Reg::read) this register and get [`rtc_0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`rtc_0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rtc_0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RTC_0_SPEC; impl crate::RegisterSpec for RTC_0_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`rtc_0::R`](R) reader structure"] impl crate::Readable for RTC_0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rtc_0::W`](W) writer structure"] +impl crate::Writable for RTC_0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets RTC_0 to value 0"] impl crate::Resettable for RTC_0_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/rtc/rtc_1.rs b/src/rtc/rtc_1.rs index 78794efc6..3060b6760 100644 --- a/src/rtc/rtc_1.rs +++ b/src/rtc/rtc_1.rs @@ -1,5 +1,7 @@ #[doc = "Register `RTC_1` reader"] pub type R = crate::R; +#[doc = "Register `RTC_1` writer"] +pub type W = crate::W; #[doc = "Field `DAY` reader - Day of the month (1..31)"] pub type DAY_R = crate::FieldReader; #[doc = "Field `MONTH` reader - Month (1..12)"] @@ -23,15 +25,22 @@ impl R { YEAR_R::new(((self.bits >> 12) & 0x0fff) as u16) } } +impl W {} #[doc = "RTC register 1. -You can [`read`](crate::generic::Reg::read) this register and get [`rtc_1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`rtc_1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rtc_1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RTC_1_SPEC; impl crate::RegisterSpec for RTC_1_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`rtc_1::R`](R) reader structure"] impl crate::Readable for RTC_1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rtc_1::W`](W) writer structure"] +impl crate::Writable for RTC_1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets RTC_1 to value 0"] impl crate::Resettable for RTC_1_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/sio.rs b/src/sio.rs index 2b5353da9..a02aa2b33 100644 --- a/src/sio.rs +++ b/src/sio.rs @@ -68,8 +68,7 @@ pub struct RegisterBlock { spinlock: [SPINLOCK; 32], } impl RegisterBlock { - #[doc = "0x00 - Processor core identifier - Value is 0 when read from processor core 0, and 1 when read from processor core 1."] + #[doc = "0x00 - Processor core identifier"] #[inline(always)] pub const fn cpuid(&self) -> &CPUID { &self.cpuid @@ -164,11 +163,7 @@ impl RegisterBlock { pub const fn gpio_hi_oe_xor(&self) -> &GPIO_HI_OE_XOR { &self.gpio_hi_oe_xor } - #[doc = "0x50 - Status register for inter-core FIFOs (mailboxes). - There is one FIFO in the core 0 -> core 1 direction, and one core 1 -> core 0. Both are 32 bits wide and 8 words deep. - Core 0 can see the read side of the 1->0 FIFO (RX), and the write side of 0->1 FIFO (TX). - Core 1 can see the read side of the 0->1 FIFO (RX), and the write side of 1->0 FIFO (TX). - The SIO IRQ for each core is the logical OR of the VLD, WOF and ROE fields of its FIFO_ST register."] + #[doc = "0x50 - Status register for inter-core FIFOs (mailboxes). There is one FIFO in the core 0 -> core 1 direction, and one core 1 -> core 0. Both are 32 bits wide and 8 words deep. Core 0 can see the read side of the 1->0 FIFO (RX), and the write side of 0->1 FIFO (TX). Core 1 can see the read side of the 0->1 FIFO (RX), and the write side of 1->0 FIFO (TX). The SIO IRQ for each core is the logical OR of the VLD, WOF and ROE fields of its FIFO_ST register."] #[inline(always)] pub const fn fifo_st(&self) -> &FIFO_ST { &self.fifo_st @@ -183,59 +178,37 @@ impl RegisterBlock { pub const fn fifo_rd(&self) -> &FIFO_RD { &self.fifo_rd } - #[doc = "0x5c - Spinlock state - A bitmap containing the state of all 32 spinlocks (1=locked). - Mainly intended for debugging."] + #[doc = "0x5c - Spinlock state A bitmap containing the state of all 32 spinlocks (1=locked). Mainly intended for debugging."] #[inline(always)] pub const fn spinlock_st(&self) -> &SPINLOCK_ST { &self.spinlock_st } - #[doc = "0x60 - Divider unsigned dividend - Write to the DIVIDEND operand of the divider, i.e. the p in `p / q`. - Any operand write starts a new calculation. The results appear in QUOTIENT, REMAINDER. - UDIVIDEND/SDIVIDEND are aliases of the same internal register. The U alias starts an - unsigned calculation, and the S alias starts a signed calculation."] + #[doc = "0x60 - Divider unsigned dividend Write to the DIVIDEND operand of the divider, i.e. the p in `p / q`. Any operand write starts a new calculation. The results appear in QUOTIENT, REMAINDER. UDIVIDEND/SDIVIDEND are aliases of the same internal register. The U alias starts an unsigned calculation, and the S alias starts a signed calculation."] #[inline(always)] pub const fn div_udividend(&self) -> &DIV_UDIVIDEND { &self.div_udividend } - #[doc = "0x64 - Divider unsigned divisor - Write to the DIVISOR operand of the divider, i.e. the q in `p / q`. - Any operand write starts a new calculation. The results appear in QUOTIENT, REMAINDER. - UDIVISOR/SDIVISOR are aliases of the same internal register. The U alias starts an - unsigned calculation, and the S alias starts a signed calculation."] + #[doc = "0x64 - Divider unsigned divisor Write to the DIVISOR operand of the divider, i.e. the q in `p / q`. Any operand write starts a new calculation. The results appear in QUOTIENT, REMAINDER. UDIVISOR/SDIVISOR are aliases of the same internal register. The U alias starts an unsigned calculation, and the S alias starts a signed calculation."] #[inline(always)] pub const fn div_udivisor(&self) -> &DIV_UDIVISOR { &self.div_udivisor } - #[doc = "0x68 - Divider signed dividend - The same as UDIVIDEND, but starts a signed calculation, rather than unsigned."] + #[doc = "0x68 - Divider signed dividend The same as UDIVIDEND, but starts a signed calculation, rather than unsigned."] #[inline(always)] pub const fn div_sdividend(&self) -> &DIV_SDIVIDEND { &self.div_sdividend } - #[doc = "0x6c - Divider signed divisor - The same as UDIVISOR, but starts a signed calculation, rather than unsigned."] + #[doc = "0x6c - Divider signed divisor The same as UDIVISOR, but starts a signed calculation, rather than unsigned."] #[inline(always)] pub const fn div_sdivisor(&self) -> &DIV_SDIVISOR { &self.div_sdivisor } - #[doc = "0x70 - Divider result quotient - The result of `DIVIDEND / DIVISOR` (division). Contents undefined while CSR_READY is low. - For signed calculations, QUOTIENT is negative when the signs of DIVIDEND and DIVISOR differ. - This register can be written to directly, for context save/restore purposes. This halts any - in-progress calculation and sets the CSR_READY and CSR_DIRTY flags. - Reading from QUOTIENT clears the CSR_DIRTY flag, so should read results in the order - REMAINDER, QUOTIENT if CSR_DIRTY is used."] + #[doc = "0x70 - Divider result quotient The result of `DIVIDEND / DIVISOR` (division). Contents undefined while CSR_READY is low. For signed calculations, QUOTIENT is negative when the signs of DIVIDEND and DIVISOR differ. This register can be written to directly, for context save/restore purposes. This halts any in-progress calculation and sets the CSR_READY and CSR_DIRTY flags. Reading from QUOTIENT clears the CSR_DIRTY flag, so should read results in the order REMAINDER, QUOTIENT if CSR_DIRTY is used."] #[inline(always)] pub const fn div_quotient(&self) -> &DIV_QUOTIENT { &self.div_quotient } - #[doc = "0x74 - Divider result remainder - The result of `DIVIDEND % DIVISOR` (modulo). Contents undefined while CSR_READY is low. - For signed calculations, REMAINDER is negative only when DIVIDEND is negative. - This register can be written to directly, for context save/restore purposes. This halts any - in-progress calculation and sets the CSR_READY and CSR_DIRTY flags."] + #[doc = "0x74 - Divider result remainder The result of `DIVIDEND % DIVISOR` (modulo). Contents undefined while CSR_READY is low. For signed calculations, REMAINDER is negative only when DIVIDEND is negative. This register can be written to directly, for context save/restore purposes. This halts any in-progress calculation and sets the CSR_READY and CSR_DIRTY flags."] #[inline(always)] pub const fn div_remainder(&self) -> &DIV_REMAINDER { &self.div_remainder @@ -310,20 +283,17 @@ impl RegisterBlock { pub const fn interp0_ctrl_lane1(&self) -> &INTERP0_CTRL_LANE1 { &self.interp0_ctrl_lane1 } - #[doc = "0xb4 - Values written here are atomically added to ACCUM0 - Reading yields lane 0's raw shift and mask value (BASE0 not added)."] + #[doc = "0xb4 - Values written here are atomically added to ACCUM0 Reading yields lane 0's raw shift and mask value (BASE0 not added)."] #[inline(always)] pub const fn interp0_accum0_add(&self) -> &INTERP0_ACCUM0_ADD { &self.interp0_accum0_add } - #[doc = "0xb8 - Values written here are atomically added to ACCUM1 - Reading yields lane 1's raw shift and mask value (BASE1 not added)."] + #[doc = "0xb8 - Values written here are atomically added to ACCUM1 Reading yields lane 1's raw shift and mask value (BASE1 not added)."] #[inline(always)] pub const fn interp0_accum1_add(&self) -> &INTERP0_ACCUM1_ADD { &self.interp0_accum1_add } - #[doc = "0xbc - On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously. - Each half is sign-extended to 32 bits if that lane's SIGNED flag is set."] + #[doc = "0xbc - On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously. Each half is sign-extended to 32 bits if that lane's SIGNED flag is set."] #[inline(always)] pub const fn interp0_base_1and0(&self) -> &INTERP0_BASE_1AND0 { &self.interp0_base_1and0 @@ -393,71 +363,54 @@ impl RegisterBlock { pub const fn interp1_ctrl_lane1(&self) -> &INTERP1_CTRL_LANE1 { &self.interp1_ctrl_lane1 } - #[doc = "0xf4 - Values written here are atomically added to ACCUM0 - Reading yields lane 0's raw shift and mask value (BASE0 not added)."] + #[doc = "0xf4 - Values written here are atomically added to ACCUM0 Reading yields lane 0's raw shift and mask value (BASE0 not added)."] #[inline(always)] pub const fn interp1_accum0_add(&self) -> &INTERP1_ACCUM0_ADD { &self.interp1_accum0_add } - #[doc = "0xf8 - Values written here are atomically added to ACCUM1 - Reading yields lane 1's raw shift and mask value (BASE1 not added)."] + #[doc = "0xf8 - Values written here are atomically added to ACCUM1 Reading yields lane 1's raw shift and mask value (BASE1 not added)."] #[inline(always)] pub const fn interp1_accum1_add(&self) -> &INTERP1_ACCUM1_ADD { &self.interp1_accum1_add } - #[doc = "0xfc - On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously. - Each half is sign-extended to 32 bits if that lane's SIGNED flag is set."] + #[doc = "0xfc - On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously. Each half is sign-extended to 32 bits if that lane's SIGNED flag is set."] #[inline(always)] pub const fn interp1_base_1and0(&self) -> &INTERP1_BASE_1AND0 { &self.interp1_base_1and0 } - #[doc = "0x100..0x180 - Reading from a spinlock address will: - - Return 0 if lock is already locked - - Otherwise return nonzero, and simultaneously claim the lock - - Writing (any value) releases the lock. - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. - The value returned on success is 0x1 << lock number."] + #[doc = "0x100..0x180 - Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number."] #[inline(always)] pub const fn spinlock(&self, n: usize) -> &SPINLOCK { &self.spinlock[n] } #[doc = "Iterator for array of:"] - #[doc = "0x100..0x180 - Reading from a spinlock address will: - - Return 0 if lock is already locked - - Otherwise return nonzero, and simultaneously claim the lock - - Writing (any value) releases the lock. - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. - The value returned on success is 0x1 << lock number."] + #[doc = "0x100..0x180 - Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number."] #[inline(always)] pub fn spinlock_iter(&self) -> impl Iterator { self.spinlock.iter() } } -#[doc = "CPUID (r) register accessor: Processor core identifier - Value is 0 when read from processor core 0, and 1 when read from processor core 1. +#[doc = "CPUID (rw) register accessor: Processor core identifier -You can [`read`](crate::generic::Reg::read) this register and get [`cpuid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`cpuid::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cpuid::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@cpuid`] module"] pub type CPUID = crate::Reg; -#[doc = "Processor core identifier - Value is 0 when read from processor core 0, and 1 when read from processor core 1."] +#[doc = "Processor core identifier"] pub mod cpuid; -#[doc = "GPIO_IN (r) register accessor: Input value for GPIO pins +#[doc = "GPIO_IN (rw) register accessor: Input value for GPIO pins -You can [`read`](crate::generic::Reg::read) this register and get [`gpio_in::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`gpio_in::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_in::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@gpio_in`] module"] pub type GPIO_IN = crate::Reg; #[doc = "Input value for GPIO pins"] pub mod gpio_in; -#[doc = "GPIO_HI_IN (r) register accessor: Input value for QSPI pins +#[doc = "GPIO_HI_IN (rw) register accessor: Input value for QSPI pins -You can [`read`](crate::generic::Reg::read) this register and get [`gpio_hi_in::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`gpio_hi_in::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_hi_in::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@gpio_hi_in`] module"] @@ -473,27 +426,27 @@ module"] pub type GPIO_OUT = crate::Reg; #[doc = "GPIO output value"] pub mod gpio_out; -#[doc = "GPIO_OUT_SET (w) register accessor: GPIO output value set +#[doc = "GPIO_OUT_SET (rw) register accessor: GPIO output value set -You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_out_set::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`gpio_out_set::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_out_set::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@gpio_out_set`] module"] pub type GPIO_OUT_SET = crate::Reg; #[doc = "GPIO output value set"] pub mod gpio_out_set; -#[doc = "GPIO_OUT_CLR (w) register accessor: GPIO output value clear +#[doc = "GPIO_OUT_CLR (rw) register accessor: GPIO output value clear -You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_out_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`gpio_out_clr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_out_clr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@gpio_out_clr`] module"] pub type GPIO_OUT_CLR = crate::Reg; #[doc = "GPIO output value clear"] pub mod gpio_out_clr; -#[doc = "GPIO_OUT_XOR (w) register accessor: GPIO output value XOR +#[doc = "GPIO_OUT_XOR (rw) register accessor: GPIO output value XOR -You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_out_xor::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`gpio_out_xor::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_out_xor::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@gpio_out_xor`] module"] @@ -509,27 +462,27 @@ module"] pub type GPIO_OE = crate::Reg; #[doc = "GPIO output enable"] pub mod gpio_oe; -#[doc = "GPIO_OE_SET (w) register accessor: GPIO output enable set +#[doc = "GPIO_OE_SET (rw) register accessor: GPIO output enable set -You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_oe_set::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`gpio_oe_set::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_oe_set::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@gpio_oe_set`] module"] pub type GPIO_OE_SET = crate::Reg; #[doc = "GPIO output enable set"] pub mod gpio_oe_set; -#[doc = "GPIO_OE_CLR (w) register accessor: GPIO output enable clear +#[doc = "GPIO_OE_CLR (rw) register accessor: GPIO output enable clear -You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_oe_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`gpio_oe_clr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_oe_clr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@gpio_oe_clr`] module"] pub type GPIO_OE_CLR = crate::Reg; #[doc = "GPIO output enable clear"] pub mod gpio_oe_clr; -#[doc = "GPIO_OE_XOR (w) register accessor: GPIO output enable XOR +#[doc = "GPIO_OE_XOR (rw) register accessor: GPIO output enable XOR -You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_oe_xor::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`gpio_oe_xor::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_oe_xor::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@gpio_oe_xor`] module"] @@ -545,27 +498,27 @@ module"] pub type GPIO_HI_OUT = crate::Reg; #[doc = "QSPI output value"] pub mod gpio_hi_out; -#[doc = "GPIO_HI_OUT_SET (w) register accessor: QSPI output value set +#[doc = "GPIO_HI_OUT_SET (rw) register accessor: QSPI output value set -You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_hi_out_set::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`gpio_hi_out_set::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_hi_out_set::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@gpio_hi_out_set`] module"] pub type GPIO_HI_OUT_SET = crate::Reg; #[doc = "QSPI output value set"] pub mod gpio_hi_out_set; -#[doc = "GPIO_HI_OUT_CLR (w) register accessor: QSPI output value clear +#[doc = "GPIO_HI_OUT_CLR (rw) register accessor: QSPI output value clear -You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_hi_out_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`gpio_hi_out_clr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_hi_out_clr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@gpio_hi_out_clr`] module"] pub type GPIO_HI_OUT_CLR = crate::Reg; #[doc = "QSPI output value clear"] pub mod gpio_hi_out_clr; -#[doc = "GPIO_HI_OUT_XOR (w) register accessor: QSPI output value XOR +#[doc = "GPIO_HI_OUT_XOR (rw) register accessor: QSPI output value XOR -You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_hi_out_xor::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`gpio_hi_out_xor::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_hi_out_xor::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@gpio_hi_out_xor`] module"] @@ -581,178 +534,126 @@ module"] pub type GPIO_HI_OE = crate::Reg; #[doc = "QSPI output enable"] pub mod gpio_hi_oe; -#[doc = "GPIO_HI_OE_SET (w) register accessor: QSPI output enable set +#[doc = "GPIO_HI_OE_SET (rw) register accessor: QSPI output enable set -You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_hi_oe_set::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`gpio_hi_oe_set::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_hi_oe_set::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@gpio_hi_oe_set`] module"] pub type GPIO_HI_OE_SET = crate::Reg; #[doc = "QSPI output enable set"] pub mod gpio_hi_oe_set; -#[doc = "GPIO_HI_OE_CLR (w) register accessor: QSPI output enable clear +#[doc = "GPIO_HI_OE_CLR (rw) register accessor: QSPI output enable clear -You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_hi_oe_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`gpio_hi_oe_clr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_hi_oe_clr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@gpio_hi_oe_clr`] module"] pub type GPIO_HI_OE_CLR = crate::Reg; #[doc = "QSPI output enable clear"] pub mod gpio_hi_oe_clr; -#[doc = "GPIO_HI_OE_XOR (w) register accessor: QSPI output enable XOR +#[doc = "GPIO_HI_OE_XOR (rw) register accessor: QSPI output enable XOR -You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_hi_oe_xor::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`gpio_hi_oe_xor::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_hi_oe_xor::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@gpio_hi_oe_xor`] module"] pub type GPIO_HI_OE_XOR = crate::Reg; #[doc = "QSPI output enable XOR"] pub mod gpio_hi_oe_xor; -#[doc = "FIFO_ST (rw) register accessor: Status register for inter-core FIFOs (mailboxes). - There is one FIFO in the core 0 -> core 1 direction, and one core 1 -> core 0. Both are 32 bits wide and 8 words deep. - Core 0 can see the read side of the 1->0 FIFO (RX), and the write side of 0->1 FIFO (TX). - Core 1 can see the read side of the 0->1 FIFO (RX), and the write side of 1->0 FIFO (TX). - The SIO IRQ for each core is the logical OR of the VLD, WOF and ROE fields of its FIFO_ST register. +#[doc = "FIFO_ST (rw) register accessor: Status register for inter-core FIFOs (mailboxes). There is one FIFO in the core 0 -> core 1 direction, and one core 1 -> core 0. Both are 32 bits wide and 8 words deep. Core 0 can see the read side of the 1->0 FIFO (RX), and the write side of 0->1 FIFO (TX). Core 1 can see the read side of the 0->1 FIFO (RX), and the write side of 1->0 FIFO (TX). The SIO IRQ for each core is the logical OR of the VLD, WOF and ROE fields of its FIFO_ST register. You can [`read`](crate::generic::Reg::read) this register and get [`fifo_st::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo_st::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@fifo_st`] module"] pub type FIFO_ST = crate::Reg; -#[doc = "Status register for inter-core FIFOs (mailboxes). - There is one FIFO in the core 0 -> core 1 direction, and one core 1 -> core 0. Both are 32 bits wide and 8 words deep. - Core 0 can see the read side of the 1->0 FIFO (RX), and the write side of 0->1 FIFO (TX). - Core 1 can see the read side of the 0->1 FIFO (RX), and the write side of 1->0 FIFO (TX). - The SIO IRQ for each core is the logical OR of the VLD, WOF and ROE fields of its FIFO_ST register."] +#[doc = "Status register for inter-core FIFOs (mailboxes). There is one FIFO in the core 0 -> core 1 direction, and one core 1 -> core 0. Both are 32 bits wide and 8 words deep. Core 0 can see the read side of the 1->0 FIFO (RX), and the write side of 0->1 FIFO (TX). Core 1 can see the read side of the 0->1 FIFO (RX), and the write side of 1->0 FIFO (TX). The SIO IRQ for each core is the logical OR of the VLD, WOF and ROE fields of its FIFO_ST register."] pub mod fifo_st; -#[doc = "FIFO_WR (w) register accessor: Write access to this core's TX FIFO +#[doc = "FIFO_WR (rw) register accessor: Write access to this core's TX FIFO -You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo_wr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`fifo_wr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo_wr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@fifo_wr`] module"] pub type FIFO_WR = crate::Reg; #[doc = "Write access to this core's TX FIFO"] pub mod fifo_wr; -#[doc = "FIFO_RD (r) register accessor: Read access to this core's RX FIFO +#[doc = "FIFO_RD (rw) register accessor: Read access to this core's RX FIFO -You can [`read`](crate::generic::Reg::read) this register and get [`fifo_rd::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`fifo_rd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo_rd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@fifo_rd`] module"] pub type FIFO_RD = crate::Reg; #[doc = "Read access to this core's RX FIFO"] pub mod fifo_rd; -#[doc = "SPINLOCK_ST (r) register accessor: Spinlock state - A bitmap containing the state of all 32 spinlocks (1=locked). - Mainly intended for debugging. +#[doc = "SPINLOCK_ST (rw) register accessor: Spinlock state A bitmap containing the state of all 32 spinlocks (1=locked). Mainly intended for debugging. -You can [`read`](crate::generic::Reg::read) this register and get [`spinlock_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`spinlock_st::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spinlock_st::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@spinlock_st`] module"] pub type SPINLOCK_ST = crate::Reg; -#[doc = "Spinlock state - A bitmap containing the state of all 32 spinlocks (1=locked). - Mainly intended for debugging."] +#[doc = "Spinlock state A bitmap containing the state of all 32 spinlocks (1=locked). Mainly intended for debugging."] pub mod spinlock_st; -#[doc = "DIV_UDIVIDEND (rw) register accessor: Divider unsigned dividend - Write to the DIVIDEND operand of the divider, i.e. the p in `p / q`. - Any operand write starts a new calculation. The results appear in QUOTIENT, REMAINDER. - UDIVIDEND/SDIVIDEND are aliases of the same internal register. The U alias starts an - unsigned calculation, and the S alias starts a signed calculation. +#[doc = "DIV_UDIVIDEND (rw) register accessor: Divider unsigned dividend Write to the DIVIDEND operand of the divider, i.e. the p in `p / q`. Any operand write starts a new calculation. The results appear in QUOTIENT, REMAINDER. UDIVIDEND/SDIVIDEND are aliases of the same internal register. The U alias starts an unsigned calculation, and the S alias starts a signed calculation. You can [`read`](crate::generic::Reg::read) this register and get [`div_udividend::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`div_udividend::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@div_udividend`] module"] pub type DIV_UDIVIDEND = crate::Reg; -#[doc = "Divider unsigned dividend - Write to the DIVIDEND operand of the divider, i.e. the p in `p / q`. - Any operand write starts a new calculation. The results appear in QUOTIENT, REMAINDER. - UDIVIDEND/SDIVIDEND are aliases of the same internal register. The U alias starts an - unsigned calculation, and the S alias starts a signed calculation."] +#[doc = "Divider unsigned dividend Write to the DIVIDEND operand of the divider, i.e. the p in `p / q`. Any operand write starts a new calculation. The results appear in QUOTIENT, REMAINDER. UDIVIDEND/SDIVIDEND are aliases of the same internal register. The U alias starts an unsigned calculation, and the S alias starts a signed calculation."] pub mod div_udividend; -#[doc = "DIV_UDIVISOR (rw) register accessor: Divider unsigned divisor - Write to the DIVISOR operand of the divider, i.e. the q in `p / q`. - Any operand write starts a new calculation. The results appear in QUOTIENT, REMAINDER. - UDIVISOR/SDIVISOR are aliases of the same internal register. The U alias starts an - unsigned calculation, and the S alias starts a signed calculation. +#[doc = "DIV_UDIVISOR (rw) register accessor: Divider unsigned divisor Write to the DIVISOR operand of the divider, i.e. the q in `p / q`. Any operand write starts a new calculation. The results appear in QUOTIENT, REMAINDER. UDIVISOR/SDIVISOR are aliases of the same internal register. The U alias starts an unsigned calculation, and the S alias starts a signed calculation. You can [`read`](crate::generic::Reg::read) this register and get [`div_udivisor::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`div_udivisor::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@div_udivisor`] module"] pub type DIV_UDIVISOR = crate::Reg; -#[doc = "Divider unsigned divisor - Write to the DIVISOR operand of the divider, i.e. the q in `p / q`. - Any operand write starts a new calculation. The results appear in QUOTIENT, REMAINDER. - UDIVISOR/SDIVISOR are aliases of the same internal register. The U alias starts an - unsigned calculation, and the S alias starts a signed calculation."] +#[doc = "Divider unsigned divisor Write to the DIVISOR operand of the divider, i.e. the q in `p / q`. Any operand write starts a new calculation. The results appear in QUOTIENT, REMAINDER. UDIVISOR/SDIVISOR are aliases of the same internal register. The U alias starts an unsigned calculation, and the S alias starts a signed calculation."] pub mod div_udivisor; -#[doc = "DIV_SDIVIDEND (rw) register accessor: Divider signed dividend - The same as UDIVIDEND, but starts a signed calculation, rather than unsigned. +#[doc = "DIV_SDIVIDEND (rw) register accessor: Divider signed dividend The same as UDIVIDEND, but starts a signed calculation, rather than unsigned. You can [`read`](crate::generic::Reg::read) this register and get [`div_sdividend::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`div_sdividend::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@div_sdividend`] module"] pub type DIV_SDIVIDEND = crate::Reg; -#[doc = "Divider signed dividend - The same as UDIVIDEND, but starts a signed calculation, rather than unsigned."] +#[doc = "Divider signed dividend The same as UDIVIDEND, but starts a signed calculation, rather than unsigned."] pub mod div_sdividend; -#[doc = "DIV_SDIVISOR (rw) register accessor: Divider signed divisor - The same as UDIVISOR, but starts a signed calculation, rather than unsigned. +#[doc = "DIV_SDIVISOR (rw) register accessor: Divider signed divisor The same as UDIVISOR, but starts a signed calculation, rather than unsigned. You can [`read`](crate::generic::Reg::read) this register and get [`div_sdivisor::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`div_sdivisor::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@div_sdivisor`] module"] pub type DIV_SDIVISOR = crate::Reg; -#[doc = "Divider signed divisor - The same as UDIVISOR, but starts a signed calculation, rather than unsigned."] +#[doc = "Divider signed divisor The same as UDIVISOR, but starts a signed calculation, rather than unsigned."] pub mod div_sdivisor; -#[doc = "DIV_QUOTIENT (rw) register accessor: Divider result quotient - The result of `DIVIDEND / DIVISOR` (division). Contents undefined while CSR_READY is low. - For signed calculations, QUOTIENT is negative when the signs of DIVIDEND and DIVISOR differ. - This register can be written to directly, for context save/restore purposes. This halts any - in-progress calculation and sets the CSR_READY and CSR_DIRTY flags. - Reading from QUOTIENT clears the CSR_DIRTY flag, so should read results in the order - REMAINDER, QUOTIENT if CSR_DIRTY is used. +#[doc = "DIV_QUOTIENT (rw) register accessor: Divider result quotient The result of `DIVIDEND / DIVISOR` (division). Contents undefined while CSR_READY is low. For signed calculations, QUOTIENT is negative when the signs of DIVIDEND and DIVISOR differ. This register can be written to directly, for context save/restore purposes. This halts any in-progress calculation and sets the CSR_READY and CSR_DIRTY flags. Reading from QUOTIENT clears the CSR_DIRTY flag, so should read results in the order REMAINDER, QUOTIENT if CSR_DIRTY is used. You can [`read`](crate::generic::Reg::read) this register and get [`div_quotient::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`div_quotient::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@div_quotient`] module"] pub type DIV_QUOTIENT = crate::Reg; -#[doc = "Divider result quotient - The result of `DIVIDEND / DIVISOR` (division). Contents undefined while CSR_READY is low. - For signed calculations, QUOTIENT is negative when the signs of DIVIDEND and DIVISOR differ. - This register can be written to directly, for context save/restore purposes. This halts any - in-progress calculation and sets the CSR_READY and CSR_DIRTY flags. - Reading from QUOTIENT clears the CSR_DIRTY flag, so should read results in the order - REMAINDER, QUOTIENT if CSR_DIRTY is used."] +#[doc = "Divider result quotient The result of `DIVIDEND / DIVISOR` (division). Contents undefined while CSR_READY is low. For signed calculations, QUOTIENT is negative when the signs of DIVIDEND and DIVISOR differ. This register can be written to directly, for context save/restore purposes. This halts any in-progress calculation and sets the CSR_READY and CSR_DIRTY flags. Reading from QUOTIENT clears the CSR_DIRTY flag, so should read results in the order REMAINDER, QUOTIENT if CSR_DIRTY is used."] pub mod div_quotient; -#[doc = "DIV_REMAINDER (rw) register accessor: Divider result remainder - The result of `DIVIDEND % DIVISOR` (modulo). Contents undefined while CSR_READY is low. - For signed calculations, REMAINDER is negative only when DIVIDEND is negative. - This register can be written to directly, for context save/restore purposes. This halts any - in-progress calculation and sets the CSR_READY and CSR_DIRTY flags. +#[doc = "DIV_REMAINDER (rw) register accessor: Divider result remainder The result of `DIVIDEND % DIVISOR` (modulo). Contents undefined while CSR_READY is low. For signed calculations, REMAINDER is negative only when DIVIDEND is negative. This register can be written to directly, for context save/restore purposes. This halts any in-progress calculation and sets the CSR_READY and CSR_DIRTY flags. You can [`read`](crate::generic::Reg::read) this register and get [`div_remainder::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`div_remainder::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@div_remainder`] module"] pub type DIV_REMAINDER = crate::Reg; -#[doc = "Divider result remainder - The result of `DIVIDEND % DIVISOR` (modulo). Contents undefined while CSR_READY is low. - For signed calculations, REMAINDER is negative only when DIVIDEND is negative. - This register can be written to directly, for context save/restore purposes. This halts any - in-progress calculation and sets the CSR_READY and CSR_DIRTY flags."] +#[doc = "Divider result remainder The result of `DIVIDEND % DIVISOR` (modulo). Contents undefined while CSR_READY is low. For signed calculations, REMAINDER is negative only when DIVIDEND is negative. This register can be written to directly, for context save/restore purposes. This halts any in-progress calculation and sets the CSR_READY and CSR_DIRTY flags."] pub mod div_remainder; -#[doc = "DIV_CSR (r) register accessor: Control and status register for divider. +#[doc = "DIV_CSR (rw) register accessor: Control and status register for divider. -You can [`read`](crate::generic::Reg::read) this register and get [`div_csr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`div_csr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`div_csr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@div_csr`] module"] @@ -804,54 +705,54 @@ module"] pub type INTERP0_BASE2 = crate::Reg; #[doc = "Read/write access to BASE2 register."] pub mod interp0_base2; -#[doc = "INTERP0_POP_LANE0 (r) register accessor: Read LANE0 result, and simultaneously write lane results to both accumulators (POP). +#[doc = "INTERP0_POP_LANE0 (rw) register accessor: Read LANE0 result, and simultaneously write lane results to both accumulators (POP). -You can [`read`](crate::generic::Reg::read) this register and get [`interp0_pop_lane0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`interp0_pop_lane0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp0_pop_lane0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@interp0_pop_lane0`] module"] pub type INTERP0_POP_LANE0 = crate::Reg; #[doc = "Read LANE0 result, and simultaneously write lane results to both accumulators (POP)."] pub mod interp0_pop_lane0; -#[doc = "INTERP0_POP_LANE1 (r) register accessor: Read LANE1 result, and simultaneously write lane results to both accumulators (POP). +#[doc = "INTERP0_POP_LANE1 (rw) register accessor: Read LANE1 result, and simultaneously write lane results to both accumulators (POP). -You can [`read`](crate::generic::Reg::read) this register and get [`interp0_pop_lane1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`interp0_pop_lane1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp0_pop_lane1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@interp0_pop_lane1`] module"] pub type INTERP0_POP_LANE1 = crate::Reg; #[doc = "Read LANE1 result, and simultaneously write lane results to both accumulators (POP)."] pub mod interp0_pop_lane1; -#[doc = "INTERP0_POP_FULL (r) register accessor: Read FULL result, and simultaneously write lane results to both accumulators (POP). +#[doc = "INTERP0_POP_FULL (rw) register accessor: Read FULL result, and simultaneously write lane results to both accumulators (POP). -You can [`read`](crate::generic::Reg::read) this register and get [`interp0_pop_full::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`interp0_pop_full::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp0_pop_full::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@interp0_pop_full`] module"] pub type INTERP0_POP_FULL = crate::Reg; #[doc = "Read FULL result, and simultaneously write lane results to both accumulators (POP)."] pub mod interp0_pop_full; -#[doc = "INTERP0_PEEK_LANE0 (r) register accessor: Read LANE0 result, without altering any internal state (PEEK). +#[doc = "INTERP0_PEEK_LANE0 (rw) register accessor: Read LANE0 result, without altering any internal state (PEEK). -You can [`read`](crate::generic::Reg::read) this register and get [`interp0_peek_lane0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`interp0_peek_lane0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp0_peek_lane0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@interp0_peek_lane0`] module"] pub type INTERP0_PEEK_LANE0 = crate::Reg; #[doc = "Read LANE0 result, without altering any internal state (PEEK)."] pub mod interp0_peek_lane0; -#[doc = "INTERP0_PEEK_LANE1 (r) register accessor: Read LANE1 result, without altering any internal state (PEEK). +#[doc = "INTERP0_PEEK_LANE1 (rw) register accessor: Read LANE1 result, without altering any internal state (PEEK). -You can [`read`](crate::generic::Reg::read) this register and get [`interp0_peek_lane1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`interp0_peek_lane1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp0_peek_lane1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@interp0_peek_lane1`] module"] pub type INTERP0_PEEK_LANE1 = crate::Reg; #[doc = "Read LANE1 result, without altering any internal state (PEEK)."] pub mod interp0_peek_lane1; -#[doc = "INTERP0_PEEK_FULL (r) register accessor: Read FULL result, without altering any internal state (PEEK). +#[doc = "INTERP0_PEEK_FULL (rw) register accessor: Read FULL result, without altering any internal state (PEEK). -You can [`read`](crate::generic::Reg::read) this register and get [`interp0_peek_full::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`interp0_peek_full::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp0_peek_full::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@interp0_peek_full`] module"] @@ -876,38 +777,32 @@ module"] pub type INTERP0_CTRL_LANE1 = crate::Reg; #[doc = "Control register for lane 1"] pub mod interp0_ctrl_lane1; -#[doc = "INTERP0_ACCUM0_ADD (rw) register accessor: Values written here are atomically added to ACCUM0 - Reading yields lane 0's raw shift and mask value (BASE0 not added). +#[doc = "INTERP0_ACCUM0_ADD (rw) register accessor: Values written here are atomically added to ACCUM0 Reading yields lane 0's raw shift and mask value (BASE0 not added). You can [`read`](crate::generic::Reg::read) this register and get [`interp0_accum0_add::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp0_accum0_add::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@interp0_accum0_add`] module"] pub type INTERP0_ACCUM0_ADD = crate::Reg; -#[doc = "Values written here are atomically added to ACCUM0 - Reading yields lane 0's raw shift and mask value (BASE0 not added)."] +#[doc = "Values written here are atomically added to ACCUM0 Reading yields lane 0's raw shift and mask value (BASE0 not added)."] pub mod interp0_accum0_add; -#[doc = "INTERP0_ACCUM1_ADD (rw) register accessor: Values written here are atomically added to ACCUM1 - Reading yields lane 1's raw shift and mask value (BASE1 not added). +#[doc = "INTERP0_ACCUM1_ADD (rw) register accessor: Values written here are atomically added to ACCUM1 Reading yields lane 1's raw shift and mask value (BASE1 not added). You can [`read`](crate::generic::Reg::read) this register and get [`interp0_accum1_add::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp0_accum1_add::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@interp0_accum1_add`] module"] pub type INTERP0_ACCUM1_ADD = crate::Reg; -#[doc = "Values written here are atomically added to ACCUM1 - Reading yields lane 1's raw shift and mask value (BASE1 not added)."] +#[doc = "Values written here are atomically added to ACCUM1 Reading yields lane 1's raw shift and mask value (BASE1 not added)."] pub mod interp0_accum1_add; -#[doc = "INTERP0_BASE_1AND0 (w) register accessor: On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously. - Each half is sign-extended to 32 bits if that lane's SIGNED flag is set. +#[doc = "INTERP0_BASE_1AND0 (rw) register accessor: On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously. Each half is sign-extended to 32 bits if that lane's SIGNED flag is set. -You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp0_base_1and0::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`interp0_base_1and0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp0_base_1and0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@interp0_base_1and0`] module"] pub type INTERP0_BASE_1AND0 = crate::Reg; -#[doc = "On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously. - Each half is sign-extended to 32 bits if that lane's SIGNED flag is set."] +#[doc = "On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously. Each half is sign-extended to 32 bits if that lane's SIGNED flag is set."] pub mod interp0_base_1and0; #[doc = "INTERP1_ACCUM0 (rw) register accessor: Read/write access to accumulator 0 @@ -954,54 +849,54 @@ module"] pub type INTERP1_BASE2 = crate::Reg; #[doc = "Read/write access to BASE2 register."] pub mod interp1_base2; -#[doc = "INTERP1_POP_LANE0 (r) register accessor: Read LANE0 result, and simultaneously write lane results to both accumulators (POP). +#[doc = "INTERP1_POP_LANE0 (rw) register accessor: Read LANE0 result, and simultaneously write lane results to both accumulators (POP). -You can [`read`](crate::generic::Reg::read) this register and get [`interp1_pop_lane0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`interp1_pop_lane0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp1_pop_lane0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@interp1_pop_lane0`] module"] pub type INTERP1_POP_LANE0 = crate::Reg; #[doc = "Read LANE0 result, and simultaneously write lane results to both accumulators (POP)."] pub mod interp1_pop_lane0; -#[doc = "INTERP1_POP_LANE1 (r) register accessor: Read LANE1 result, and simultaneously write lane results to both accumulators (POP). +#[doc = "INTERP1_POP_LANE1 (rw) register accessor: Read LANE1 result, and simultaneously write lane results to both accumulators (POP). -You can [`read`](crate::generic::Reg::read) this register and get [`interp1_pop_lane1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`interp1_pop_lane1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp1_pop_lane1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@interp1_pop_lane1`] module"] pub type INTERP1_POP_LANE1 = crate::Reg; #[doc = "Read LANE1 result, and simultaneously write lane results to both accumulators (POP)."] pub mod interp1_pop_lane1; -#[doc = "INTERP1_POP_FULL (r) register accessor: Read FULL result, and simultaneously write lane results to both accumulators (POP). +#[doc = "INTERP1_POP_FULL (rw) register accessor: Read FULL result, and simultaneously write lane results to both accumulators (POP). -You can [`read`](crate::generic::Reg::read) this register and get [`interp1_pop_full::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`interp1_pop_full::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp1_pop_full::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@interp1_pop_full`] module"] pub type INTERP1_POP_FULL = crate::Reg; #[doc = "Read FULL result, and simultaneously write lane results to both accumulators (POP)."] pub mod interp1_pop_full; -#[doc = "INTERP1_PEEK_LANE0 (r) register accessor: Read LANE0 result, without altering any internal state (PEEK). +#[doc = "INTERP1_PEEK_LANE0 (rw) register accessor: Read LANE0 result, without altering any internal state (PEEK). -You can [`read`](crate::generic::Reg::read) this register and get [`interp1_peek_lane0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`interp1_peek_lane0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp1_peek_lane0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@interp1_peek_lane0`] module"] pub type INTERP1_PEEK_LANE0 = crate::Reg; #[doc = "Read LANE0 result, without altering any internal state (PEEK)."] pub mod interp1_peek_lane0; -#[doc = "INTERP1_PEEK_LANE1 (r) register accessor: Read LANE1 result, without altering any internal state (PEEK). +#[doc = "INTERP1_PEEK_LANE1 (rw) register accessor: Read LANE1 result, without altering any internal state (PEEK). -You can [`read`](crate::generic::Reg::read) this register and get [`interp1_peek_lane1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`interp1_peek_lane1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp1_peek_lane1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@interp1_peek_lane1`] module"] pub type INTERP1_PEEK_LANE1 = crate::Reg; #[doc = "Read LANE1 result, without altering any internal state (PEEK)."] pub mod interp1_peek_lane1; -#[doc = "INTERP1_PEEK_FULL (r) register accessor: Read FULL result, without altering any internal state (PEEK). +#[doc = "INTERP1_PEEK_FULL (rw) register accessor: Read FULL result, without altering any internal state (PEEK). -You can [`read`](crate::generic::Reg::read) this register and get [`interp1_peek_full::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`interp1_peek_full::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp1_peek_full::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@interp1_peek_full`] module"] @@ -1026,57 +921,39 @@ module"] pub type INTERP1_CTRL_LANE1 = crate::Reg; #[doc = "Control register for lane 1"] pub mod interp1_ctrl_lane1; -#[doc = "INTERP1_ACCUM0_ADD (rw) register accessor: Values written here are atomically added to ACCUM0 - Reading yields lane 0's raw shift and mask value (BASE0 not added). +#[doc = "INTERP1_ACCUM0_ADD (rw) register accessor: Values written here are atomically added to ACCUM0 Reading yields lane 0's raw shift and mask value (BASE0 not added). You can [`read`](crate::generic::Reg::read) this register and get [`interp1_accum0_add::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp1_accum0_add::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@interp1_accum0_add`] module"] pub type INTERP1_ACCUM0_ADD = crate::Reg; -#[doc = "Values written here are atomically added to ACCUM0 - Reading yields lane 0's raw shift and mask value (BASE0 not added)."] +#[doc = "Values written here are atomically added to ACCUM0 Reading yields lane 0's raw shift and mask value (BASE0 not added)."] pub mod interp1_accum0_add; -#[doc = "INTERP1_ACCUM1_ADD (rw) register accessor: Values written here are atomically added to ACCUM1 - Reading yields lane 1's raw shift and mask value (BASE1 not added). +#[doc = "INTERP1_ACCUM1_ADD (rw) register accessor: Values written here are atomically added to ACCUM1 Reading yields lane 1's raw shift and mask value (BASE1 not added). You can [`read`](crate::generic::Reg::read) this register and get [`interp1_accum1_add::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp1_accum1_add::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@interp1_accum1_add`] module"] pub type INTERP1_ACCUM1_ADD = crate::Reg; -#[doc = "Values written here are atomically added to ACCUM1 - Reading yields lane 1's raw shift and mask value (BASE1 not added)."] +#[doc = "Values written here are atomically added to ACCUM1 Reading yields lane 1's raw shift and mask value (BASE1 not added)."] pub mod interp1_accum1_add; -#[doc = "INTERP1_BASE_1AND0 (w) register accessor: On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously. - Each half is sign-extended to 32 bits if that lane's SIGNED flag is set. +#[doc = "INTERP1_BASE_1AND0 (rw) register accessor: On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously. Each half is sign-extended to 32 bits if that lane's SIGNED flag is set. -You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp1_base_1and0::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`interp1_base_1and0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp1_base_1and0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@interp1_base_1and0`] module"] pub type INTERP1_BASE_1AND0 = crate::Reg; -#[doc = "On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously. - Each half is sign-extended to 32 bits if that lane's SIGNED flag is set."] +#[doc = "On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously. Each half is sign-extended to 32 bits if that lane's SIGNED flag is set."] pub mod interp1_base_1and0; -#[doc = "SPINLOCK (rw) register accessor: Reading from a spinlock address will: - - Return 0 if lock is already locked - - Otherwise return nonzero, and simultaneously claim the lock - - Writing (any value) releases the lock. - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. - The value returned on success is 0x1 << lock number. +#[doc = "SPINLOCK (rw) register accessor: Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. You can [`read`](crate::generic::Reg::read) this register and get [`spinlock::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spinlock::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@spinlock`] module"] pub type SPINLOCK = crate::Reg; -#[doc = "Reading from a spinlock address will: - - Return 0 if lock is already locked - - Otherwise return nonzero, and simultaneously claim the lock - - Writing (any value) releases the lock. - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. - The value returned on success is 0x1 << lock number."] +#[doc = "Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number."] pub mod spinlock; diff --git a/src/sio/cpuid.rs b/src/sio/cpuid.rs index f9cfebe71..b80c27712 100644 --- a/src/sio/cpuid.rs +++ b/src/sio/cpuid.rs @@ -1,25 +1,32 @@ #[doc = "Register `CPUID` reader"] pub type R = crate::R; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) - } -} -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +#[doc = "Register `CPUID` writer"] +pub type W = crate::W; +#[doc = "Field `CPUID` reader - Value is 0 when read from processor core 0, and 1 when read from processor core 1."] +pub type CPUID_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Value is 0 when read from processor core 0, and 1 when read from processor core 1."] + #[inline(always)] + pub fn cpuid(&self) -> CPUID_R { + CPUID_R::new(self.bits) } } +impl W {} #[doc = "Processor core identifier - Value is 0 when read from processor core 0, and 1 when read from processor core 1. -You can [`read`](crate::generic::Reg::read) this register and get [`cpuid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`cpuid::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cpuid::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CPUID_SPEC; impl crate::RegisterSpec for CPUID_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`cpuid::R`](R) reader structure"] impl crate::Readable for CPUID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cpuid::W`](W) writer structure"] +impl crate::Writable for CPUID_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets CPUID to value 0"] impl crate::Resettable for CPUID_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/sio/div_csr.rs b/src/sio/div_csr.rs index a4d4ca012..aa991e381 100644 --- a/src/sio/div_csr.rs +++ b/src/sio/div_csr.rs @@ -1,44 +1,39 @@ #[doc = "Register `DIV_CSR` reader"] pub type R = crate::R; -#[doc = "Field `READY` reader - Reads as 0 when a calculation is in progress, 1 otherwise. - Writing an operand (xDIVIDEND, xDIVISOR) will immediately start a new calculation, no - matter if one is already in progress. - Writing to a result register will immediately terminate any in-progress calculation - and set the READY and DIRTY flags."] +#[doc = "Register `DIV_CSR` writer"] +pub type W = crate::W; +#[doc = "Field `READY` reader - Reads as 0 when a calculation is in progress, 1 otherwise. Writing an operand (xDIVIDEND, xDIVISOR) will immediately start a new calculation, no matter if one is already in progress. Writing to a result register will immediately terminate any in-progress calculation and set the READY and DIRTY flags."] pub type READY_R = crate::BitReader; -#[doc = "Field `DIRTY` reader - Changes to 1 when any register is written, and back to 0 when QUOTIENT is read. - Software can use this flag to make save/restore more efficient (skip if not DIRTY). - If the flag is used in this way, it's recommended to either read QUOTIENT only, - or REMAINDER and then QUOTIENT, to prevent data loss on context switch."] +#[doc = "Field `DIRTY` reader - Changes to 1 when any register is written, and back to 0 when QUOTIENT is read. Software can use this flag to make save/restore more efficient (skip if not DIRTY). If the flag is used in this way, it's recommended to either read QUOTIENT only, or REMAINDER and then QUOTIENT, to prevent data loss on context switch."] pub type DIRTY_R = crate::BitReader; impl R { - #[doc = "Bit 0 - Reads as 0 when a calculation is in progress, 1 otherwise. - Writing an operand (xDIVIDEND, xDIVISOR) will immediately start a new calculation, no - matter if one is already in progress. - Writing to a result register will immediately terminate any in-progress calculation - and set the READY and DIRTY flags."] + #[doc = "Bit 0 - Reads as 0 when a calculation is in progress, 1 otherwise. Writing an operand (xDIVIDEND, xDIVISOR) will immediately start a new calculation, no matter if one is already in progress. Writing to a result register will immediately terminate any in-progress calculation and set the READY and DIRTY flags."] #[inline(always)] pub fn ready(&self) -> READY_R { READY_R::new((self.bits & 1) != 0) } - #[doc = "Bit 1 - Changes to 1 when any register is written, and back to 0 when QUOTIENT is read. - Software can use this flag to make save/restore more efficient (skip if not DIRTY). - If the flag is used in this way, it's recommended to either read QUOTIENT only, - or REMAINDER and then QUOTIENT, to prevent data loss on context switch."] + #[doc = "Bit 1 - Changes to 1 when any register is written, and back to 0 when QUOTIENT is read. Software can use this flag to make save/restore more efficient (skip if not DIRTY). If the flag is used in this way, it's recommended to either read QUOTIENT only, or REMAINDER and then QUOTIENT, to prevent data loss on context switch."] #[inline(always)] pub fn dirty(&self) -> DIRTY_R { DIRTY_R::new(((self.bits >> 1) & 1) != 0) } } +impl W {} #[doc = "Control and status register for divider. -You can [`read`](crate::generic::Reg::read) this register and get [`div_csr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`div_csr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`div_csr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DIV_CSR_SPEC; impl crate::RegisterSpec for DIV_CSR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`div_csr::R`](R) reader structure"] impl crate::Readable for DIV_CSR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`div_csr::W`](W) writer structure"] +impl crate::Writable for DIV_CSR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets DIV_CSR to value 0x01"] impl crate::Resettable for DIV_CSR_SPEC { const RESET_VALUE: u32 = 0x01; diff --git a/src/sio/div_quotient.rs b/src/sio/div_quotient.rs index d16a6cda5..57390c1df 100644 --- a/src/sio/div_quotient.rs +++ b/src/sio/div_quotient.rs @@ -2,24 +2,26 @@ pub type R = crate::R; #[doc = "Register `DIV_QUOTIENT` writer"] pub type W = crate::W; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) +#[doc = "Field `DIV_QUOTIENT` reader - "] +pub type DIV_QUOTIENT_R = crate::FieldReader; +#[doc = "Field `DIV_QUOTIENT` writer - "] +pub type DIV_QUOTIENT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn div_quotient(&self) -> DIV_QUOTIENT_R { + DIV_QUOTIENT_R::new(self.bits) } } -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn div_quotient(&mut self) -> DIV_QUOTIENT_W { + DIV_QUOTIENT_W::new(self, 0) } } -impl W {} -#[doc = "Divider result quotient - The result of `DIVIDEND / DIVISOR` (division). Contents undefined while CSR_READY is low. - For signed calculations, QUOTIENT is negative when the signs of DIVIDEND and DIVISOR differ. - This register can be written to directly, for context save/restore purposes. This halts any - in-progress calculation and sets the CSR_READY and CSR_DIRTY flags. - Reading from QUOTIENT clears the CSR_DIRTY flag, so should read results in the order - REMAINDER, QUOTIENT if CSR_DIRTY is used. +#[doc = "Divider result quotient The result of `DIVIDEND / DIVISOR` (division). Contents undefined while CSR_READY is low. For signed calculations, QUOTIENT is negative when the signs of DIVIDEND and DIVISOR differ. This register can be written to directly, for context save/restore purposes. This halts any in-progress calculation and sets the CSR_READY and CSR_DIRTY flags. Reading from QUOTIENT clears the CSR_DIRTY flag, so should read results in the order REMAINDER, QUOTIENT if CSR_DIRTY is used. You can [`read`](crate::generic::Reg::read) this register and get [`div_quotient::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`div_quotient::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DIV_QUOTIENT_SPEC; diff --git a/src/sio/div_remainder.rs b/src/sio/div_remainder.rs index 12e963907..6a8a4a0fc 100644 --- a/src/sio/div_remainder.rs +++ b/src/sio/div_remainder.rs @@ -2,22 +2,26 @@ pub type R = crate::R; #[doc = "Register `DIV_REMAINDER` writer"] pub type W = crate::W; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) +#[doc = "Field `DIV_REMAINDER` reader - "] +pub type DIV_REMAINDER_R = crate::FieldReader; +#[doc = "Field `DIV_REMAINDER` writer - "] +pub type DIV_REMAINDER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn div_remainder(&self) -> DIV_REMAINDER_R { + DIV_REMAINDER_R::new(self.bits) } } -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn div_remainder(&mut self) -> DIV_REMAINDER_W { + DIV_REMAINDER_W::new(self, 0) } } -impl W {} -#[doc = "Divider result remainder - The result of `DIVIDEND % DIVISOR` (modulo). Contents undefined while CSR_READY is low. - For signed calculations, REMAINDER is negative only when DIVIDEND is negative. - This register can be written to directly, for context save/restore purposes. This halts any - in-progress calculation and sets the CSR_READY and CSR_DIRTY flags. +#[doc = "Divider result remainder The result of `DIVIDEND % DIVISOR` (modulo). Contents undefined while CSR_READY is low. For signed calculations, REMAINDER is negative only when DIVIDEND is negative. This register can be written to directly, for context save/restore purposes. This halts any in-progress calculation and sets the CSR_READY and CSR_DIRTY flags. You can [`read`](crate::generic::Reg::read) this register and get [`div_remainder::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`div_remainder::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DIV_REMAINDER_SPEC; diff --git a/src/sio/div_sdividend.rs b/src/sio/div_sdividend.rs index f94dfeefd..554d3019a 100644 --- a/src/sio/div_sdividend.rs +++ b/src/sio/div_sdividend.rs @@ -2,19 +2,26 @@ pub type R = crate::R; #[doc = "Register `DIV_SDIVIDEND` writer"] pub type W = crate::W; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) +#[doc = "Field `DIV_SDIVIDEND` reader - "] +pub type DIV_SDIVIDEND_R = crate::FieldReader; +#[doc = "Field `DIV_SDIVIDEND` writer - "] +pub type DIV_SDIVIDEND_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn div_sdividend(&self) -> DIV_SDIVIDEND_R { + DIV_SDIVIDEND_R::new(self.bits) } } -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn div_sdividend(&mut self) -> DIV_SDIVIDEND_W { + DIV_SDIVIDEND_W::new(self, 0) } } -impl W {} -#[doc = "Divider signed dividend - The same as UDIVIDEND, but starts a signed calculation, rather than unsigned. +#[doc = "Divider signed dividend The same as UDIVIDEND, but starts a signed calculation, rather than unsigned. You can [`read`](crate::generic::Reg::read) this register and get [`div_sdividend::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`div_sdividend::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DIV_SDIVIDEND_SPEC; diff --git a/src/sio/div_sdivisor.rs b/src/sio/div_sdivisor.rs index b6a93d79d..c1e36c2f3 100644 --- a/src/sio/div_sdivisor.rs +++ b/src/sio/div_sdivisor.rs @@ -2,19 +2,26 @@ pub type R = crate::R; #[doc = "Register `DIV_SDIVISOR` writer"] pub type W = crate::W; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) +#[doc = "Field `DIV_SDIVISOR` reader - "] +pub type DIV_SDIVISOR_R = crate::FieldReader; +#[doc = "Field `DIV_SDIVISOR` writer - "] +pub type DIV_SDIVISOR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn div_sdivisor(&self) -> DIV_SDIVISOR_R { + DIV_SDIVISOR_R::new(self.bits) } } -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn div_sdivisor(&mut self) -> DIV_SDIVISOR_W { + DIV_SDIVISOR_W::new(self, 0) } } -impl W {} -#[doc = "Divider signed divisor - The same as UDIVISOR, but starts a signed calculation, rather than unsigned. +#[doc = "Divider signed divisor The same as UDIVISOR, but starts a signed calculation, rather than unsigned. You can [`read`](crate::generic::Reg::read) this register and get [`div_sdivisor::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`div_sdivisor::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DIV_SDIVISOR_SPEC; diff --git a/src/sio/div_udividend.rs b/src/sio/div_udividend.rs index 7dce964b5..15f5606f7 100644 --- a/src/sio/div_udividend.rs +++ b/src/sio/div_udividend.rs @@ -2,22 +2,26 @@ pub type R = crate::R; #[doc = "Register `DIV_UDIVIDEND` writer"] pub type W = crate::W; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) +#[doc = "Field `DIV_UDIVIDEND` reader - "] +pub type DIV_UDIVIDEND_R = crate::FieldReader; +#[doc = "Field `DIV_UDIVIDEND` writer - "] +pub type DIV_UDIVIDEND_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn div_udividend(&self) -> DIV_UDIVIDEND_R { + DIV_UDIVIDEND_R::new(self.bits) } } -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn div_udividend(&mut self) -> DIV_UDIVIDEND_W { + DIV_UDIVIDEND_W::new(self, 0) } } -impl W {} -#[doc = "Divider unsigned dividend - Write to the DIVIDEND operand of the divider, i.e. the p in `p / q`. - Any operand write starts a new calculation. The results appear in QUOTIENT, REMAINDER. - UDIVIDEND/SDIVIDEND are aliases of the same internal register. The U alias starts an - unsigned calculation, and the S alias starts a signed calculation. +#[doc = "Divider unsigned dividend Write to the DIVIDEND operand of the divider, i.e. the p in `p / q`. Any operand write starts a new calculation. The results appear in QUOTIENT, REMAINDER. UDIVIDEND/SDIVIDEND are aliases of the same internal register. The U alias starts an unsigned calculation, and the S alias starts a signed calculation. You can [`read`](crate::generic::Reg::read) this register and get [`div_udividend::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`div_udividend::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DIV_UDIVIDEND_SPEC; diff --git a/src/sio/div_udivisor.rs b/src/sio/div_udivisor.rs index 835a5d191..16fcf2947 100644 --- a/src/sio/div_udivisor.rs +++ b/src/sio/div_udivisor.rs @@ -2,22 +2,26 @@ pub type R = crate::R; #[doc = "Register `DIV_UDIVISOR` writer"] pub type W = crate::W; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) +#[doc = "Field `DIV_UDIVISOR` reader - "] +pub type DIV_UDIVISOR_R = crate::FieldReader; +#[doc = "Field `DIV_UDIVISOR` writer - "] +pub type DIV_UDIVISOR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn div_udivisor(&self) -> DIV_UDIVISOR_R { + DIV_UDIVISOR_R::new(self.bits) } } -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn div_udivisor(&mut self) -> DIV_UDIVISOR_W { + DIV_UDIVISOR_W::new(self, 0) } } -impl W {} -#[doc = "Divider unsigned divisor - Write to the DIVISOR operand of the divider, i.e. the q in `p / q`. - Any operand write starts a new calculation. The results appear in QUOTIENT, REMAINDER. - UDIVISOR/SDIVISOR are aliases of the same internal register. The U alias starts an - unsigned calculation, and the S alias starts a signed calculation. +#[doc = "Divider unsigned divisor Write to the DIVISOR operand of the divider, i.e. the q in `p / q`. Any operand write starts a new calculation. The results appear in QUOTIENT, REMAINDER. UDIVISOR/SDIVISOR are aliases of the same internal register. The U alias starts an unsigned calculation, and the S alias starts a signed calculation. You can [`read`](crate::generic::Reg::read) this register and get [`div_udivisor::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`div_udivisor::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DIV_UDIVISOR_SPEC; diff --git a/src/sio/fifo_rd.rs b/src/sio/fifo_rd.rs index d087d0867..ba5036689 100644 --- a/src/sio/fifo_rd.rs +++ b/src/sio/fifo_rd.rs @@ -1,24 +1,34 @@ #[doc = "Register `FIFO_RD` reader"] pub type R = crate::R; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) - } -} -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +#[doc = "Register `FIFO_RD` writer"] +pub type W = crate::W; +#[doc = "Field `FIFO_RD` reader - + +The field is **modified** in some way after a read operation."] +pub type FIFO_RD_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn fifo_rd(&self) -> FIFO_RD_R { + FIFO_RD_R::new(self.bits) } } +impl W {} #[doc = "Read access to this core's RX FIFO -You can [`read`](crate::generic::Reg::read) this register and get [`fifo_rd::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`fifo_rd::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo_rd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FIFO_RD_SPEC; impl crate::RegisterSpec for FIFO_RD_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`fifo_rd::R`](R) reader structure"] impl crate::Readable for FIFO_RD_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fifo_rd::W`](W) writer structure"] +impl crate::Writable for FIFO_RD_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets FIFO_RD to value 0"] impl crate::Resettable for FIFO_RD_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/sio/fifo_st.rs b/src/sio/fifo_st.rs index 4429b09fd..4d7f8625c 100644 --- a/src/sio/fifo_st.rs +++ b/src/sio/fifo_st.rs @@ -50,11 +50,7 @@ impl W { ROE_W::new(self, 3) } } -#[doc = "Status register for inter-core FIFOs (mailboxes). - There is one FIFO in the core 0 -> core 1 direction, and one core 1 -> core 0. Both are 32 bits wide and 8 words deep. - Core 0 can see the read side of the 1->0 FIFO (RX), and the write side of 0->1 FIFO (TX). - Core 1 can see the read side of the 0->1 FIFO (RX), and the write side of 1->0 FIFO (TX). - The SIO IRQ for each core is the logical OR of the VLD, WOF and ROE fields of its FIFO_ST register. +#[doc = "Status register for inter-core FIFOs (mailboxes). There is one FIFO in the core 0 -> core 1 direction, and one core 1 -> core 0. Both are 32 bits wide and 8 words deep. Core 0 can see the read side of the 1->0 FIFO (RX), and the write side of 0->1 FIFO (TX). Core 1 can see the read side of the 0->1 FIFO (RX), and the write side of 1->0 FIFO (TX). The SIO IRQ for each core is the logical OR of the VLD, WOF and ROE fields of its FIFO_ST register. You can [`read`](crate::generic::Reg::read) this register and get [`fifo_st::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo_st::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FIFO_ST_SPEC; diff --git a/src/sio/fifo_wr.rs b/src/sio/fifo_wr.rs index b36d923d6..252bd28e4 100644 --- a/src/sio/fifo_wr.rs +++ b/src/sio/fifo_wr.rs @@ -1,18 +1,26 @@ +#[doc = "Register `FIFO_WR` reader"] +pub type R = crate::R; #[doc = "Register `FIFO_WR` writer"] pub type W = crate::W; -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - write!(f, "(not readable)") +#[doc = "Field `FIFO_WR` writer - "] +pub type FIFO_WR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn fifo_wr(&mut self) -> FIFO_WR_W { + FIFO_WR_W::new(self, 0) } } -impl W {} #[doc = "Write access to this core's TX FIFO -You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo_wr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`fifo_wr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo_wr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FIFO_WR_SPEC; impl crate::RegisterSpec for FIFO_WR_SPEC { type Ux = u32; } +#[doc = "`read()` method returns [`fifo_wr::R`](R) reader structure"] +impl crate::Readable for FIFO_WR_SPEC {} #[doc = "`write(|w| ..)` method takes [`fifo_wr::W`](W) writer structure"] impl crate::Writable for FIFO_WR_SPEC { type Safety = crate::Unsafe; diff --git a/src/sio/gpio_hi_in.rs b/src/sio/gpio_hi_in.rs index 5a3b133ad..e3ffdabf7 100644 --- a/src/sio/gpio_hi_in.rs +++ b/src/sio/gpio_hi_in.rs @@ -1,5 +1,7 @@ #[doc = "Register `GPIO_HI_IN` reader"] pub type R = crate::R; +#[doc = "Register `GPIO_HI_IN` writer"] +pub type W = crate::W; #[doc = "Field `GPIO_HI_IN` reader - Input value on QSPI IO in order 0..5: SCLK, SSn, SD0, SD1, SD2, SD3"] pub type GPIO_HI_IN_R = crate::FieldReader; impl R { @@ -9,15 +11,22 @@ impl R { GPIO_HI_IN_R::new((self.bits & 0x3f) as u8) } } +impl W {} #[doc = "Input value for QSPI pins -You can [`read`](crate::generic::Reg::read) this register and get [`gpio_hi_in::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`gpio_hi_in::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_hi_in::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPIO_HI_IN_SPEC; impl crate::RegisterSpec for GPIO_HI_IN_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`gpio_hi_in::R`](R) reader structure"] impl crate::Readable for GPIO_HI_IN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio_hi_in::W`](W) writer structure"] +impl crate::Writable for GPIO_HI_IN_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets GPIO_HI_IN to value 0"] impl crate::Resettable for GPIO_HI_IN_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/sio/gpio_hi_oe.rs b/src/sio/gpio_hi_oe.rs index d5dfa20da..7375d7ebe 100644 --- a/src/sio/gpio_hi_oe.rs +++ b/src/sio/gpio_hi_oe.rs @@ -2,35 +2,19 @@ pub type R = crate::R; #[doc = "Register `GPIO_HI_OE` writer"] pub type W = crate::W; -#[doc = "Field `GPIO_HI_OE` reader - Set output enable (1/0 -> output/input) for QSPI IO0...5. - Reading back gives the last value written. - If core 0 and core 1 both write to GPIO_HI_OE simultaneously (or to a SET/CLR/XOR alias), - the result is as though the write from core 0 took place first, - and the write from core 1 was then applied to that intermediate result."] +#[doc = "Field `GPIO_HI_OE` reader - Set output enable (1/0 -> output/input) for QSPI IO0...5. Reading back gives the last value written. If core 0 and core 1 both write to GPIO_HI_OE simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result."] pub type GPIO_HI_OE_R = crate::FieldReader; -#[doc = "Field `GPIO_HI_OE` writer - Set output enable (1/0 -> output/input) for QSPI IO0...5. - Reading back gives the last value written. - If core 0 and core 1 both write to GPIO_HI_OE simultaneously (or to a SET/CLR/XOR alias), - the result is as though the write from core 0 took place first, - and the write from core 1 was then applied to that intermediate result."] +#[doc = "Field `GPIO_HI_OE` writer - Set output enable (1/0 -> output/input) for QSPI IO0...5. Reading back gives the last value written. If core 0 and core 1 both write to GPIO_HI_OE simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result."] pub type GPIO_HI_OE_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; impl R { - #[doc = "Bits 0:5 - Set output enable (1/0 -> output/input) for QSPI IO0...5. - Reading back gives the last value written. - If core 0 and core 1 both write to GPIO_HI_OE simultaneously (or to a SET/CLR/XOR alias), - the result is as though the write from core 0 took place first, - and the write from core 1 was then applied to that intermediate result."] + #[doc = "Bits 0:5 - Set output enable (1/0 -> output/input) for QSPI IO0...5. Reading back gives the last value written. If core 0 and core 1 both write to GPIO_HI_OE simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result."] #[inline(always)] pub fn gpio_hi_oe(&self) -> GPIO_HI_OE_R { GPIO_HI_OE_R::new((self.bits & 0x3f) as u8) } } impl W { - #[doc = "Bits 0:5 - Set output enable (1/0 -> output/input) for QSPI IO0...5. - Reading back gives the last value written. - If core 0 and core 1 both write to GPIO_HI_OE simultaneously (or to a SET/CLR/XOR alias), - the result is as though the write from core 0 took place first, - and the write from core 1 was then applied to that intermediate result."] + #[doc = "Bits 0:5 - Set output enable (1/0 -> output/input) for QSPI IO0...5. Reading back gives the last value written. If core 0 and core 1 both write to GPIO_HI_OE simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result."] #[inline(always)] #[must_use] pub fn gpio_hi_oe(&mut self) -> GPIO_HI_OE_W { diff --git a/src/sio/gpio_hi_oe_clr.rs b/src/sio/gpio_hi_oe_clr.rs index 748742b54..7cd6f5a9d 100644 --- a/src/sio/gpio_hi_oe_clr.rs +++ b/src/sio/gpio_hi_oe_clr.rs @@ -1,3 +1,5 @@ +#[doc = "Register `GPIO_HI_OE_CLR` reader"] +pub type R = crate::R; #[doc = "Register `GPIO_HI_OE_CLR` writer"] pub type W = crate::W; #[doc = "Field `GPIO_HI_OE_CLR` writer - Perform an atomic bit-clear on GPIO_HI_OE, i.e. `GPIO_HI_OE &= ~wdata`"] @@ -12,11 +14,13 @@ impl W { } #[doc = "QSPI output enable clear -You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_hi_oe_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`gpio_hi_oe_clr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_hi_oe_clr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPIO_HI_OE_CLR_SPEC; impl crate::RegisterSpec for GPIO_HI_OE_CLR_SPEC { type Ux = u32; } +#[doc = "`read()` method returns [`gpio_hi_oe_clr::R`](R) reader structure"] +impl crate::Readable for GPIO_HI_OE_CLR_SPEC {} #[doc = "`write(|w| ..)` method takes [`gpio_hi_oe_clr::W`](W) writer structure"] impl crate::Writable for GPIO_HI_OE_CLR_SPEC { type Safety = crate::Unsafe; diff --git a/src/sio/gpio_hi_oe_set.rs b/src/sio/gpio_hi_oe_set.rs index 094595426..f9c345f4f 100644 --- a/src/sio/gpio_hi_oe_set.rs +++ b/src/sio/gpio_hi_oe_set.rs @@ -1,3 +1,5 @@ +#[doc = "Register `GPIO_HI_OE_SET` reader"] +pub type R = crate::R; #[doc = "Register `GPIO_HI_OE_SET` writer"] pub type W = crate::W; #[doc = "Field `GPIO_HI_OE_SET` writer - Perform an atomic bit-set on GPIO_HI_OE, i.e. `GPIO_HI_OE |= wdata`"] @@ -12,11 +14,13 @@ impl W { } #[doc = "QSPI output enable set -You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_hi_oe_set::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`gpio_hi_oe_set::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_hi_oe_set::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPIO_HI_OE_SET_SPEC; impl crate::RegisterSpec for GPIO_HI_OE_SET_SPEC { type Ux = u32; } +#[doc = "`read()` method returns [`gpio_hi_oe_set::R`](R) reader structure"] +impl crate::Readable for GPIO_HI_OE_SET_SPEC {} #[doc = "`write(|w| ..)` method takes [`gpio_hi_oe_set::W`](W) writer structure"] impl crate::Writable for GPIO_HI_OE_SET_SPEC { type Safety = crate::Unsafe; diff --git a/src/sio/gpio_hi_oe_xor.rs b/src/sio/gpio_hi_oe_xor.rs index 76a630857..522bcd63d 100644 --- a/src/sio/gpio_hi_oe_xor.rs +++ b/src/sio/gpio_hi_oe_xor.rs @@ -1,3 +1,5 @@ +#[doc = "Register `GPIO_HI_OE_XOR` reader"] +pub type R = crate::R; #[doc = "Register `GPIO_HI_OE_XOR` writer"] pub type W = crate::W; #[doc = "Field `GPIO_HI_OE_XOR` writer - Perform an atomic bitwise XOR on GPIO_HI_OE, i.e. `GPIO_HI_OE ^= wdata`"] @@ -12,11 +14,13 @@ impl W { } #[doc = "QSPI output enable XOR -You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_hi_oe_xor::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`gpio_hi_oe_xor::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_hi_oe_xor::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPIO_HI_OE_XOR_SPEC; impl crate::RegisterSpec for GPIO_HI_OE_XOR_SPEC { type Ux = u32; } +#[doc = "`read()` method returns [`gpio_hi_oe_xor::R`](R) reader structure"] +impl crate::Readable for GPIO_HI_OE_XOR_SPEC {} #[doc = "`write(|w| ..)` method takes [`gpio_hi_oe_xor::W`](W) writer structure"] impl crate::Writable for GPIO_HI_OE_XOR_SPEC { type Safety = crate::Unsafe; diff --git a/src/sio/gpio_hi_out.rs b/src/sio/gpio_hi_out.rs index 4bbc32ede..a430580f8 100644 --- a/src/sio/gpio_hi_out.rs +++ b/src/sio/gpio_hi_out.rs @@ -2,35 +2,19 @@ pub type R = crate::R; #[doc = "Register `GPIO_HI_OUT` writer"] pub type W = crate::W; -#[doc = "Field `GPIO_HI_OUT` reader - Set output level (1/0 -> high/low) for QSPI IO0...5. - Reading back gives the last value written, NOT the input value from the pins. - If core 0 and core 1 both write to GPIO_HI_OUT simultaneously (or to a SET/CLR/XOR alias), - the result is as though the write from core 0 took place first, - and the write from core 1 was then applied to that intermediate result."] +#[doc = "Field `GPIO_HI_OUT` reader - Set output level (1/0 -> high/low) for QSPI IO0...5. Reading back gives the last value written, NOT the input value from the pins. If core 0 and core 1 both write to GPIO_HI_OUT simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result."] pub type GPIO_HI_OUT_R = crate::FieldReader; -#[doc = "Field `GPIO_HI_OUT` writer - Set output level (1/0 -> high/low) for QSPI IO0...5. - Reading back gives the last value written, NOT the input value from the pins. - If core 0 and core 1 both write to GPIO_HI_OUT simultaneously (or to a SET/CLR/XOR alias), - the result is as though the write from core 0 took place first, - and the write from core 1 was then applied to that intermediate result."] +#[doc = "Field `GPIO_HI_OUT` writer - Set output level (1/0 -> high/low) for QSPI IO0...5. Reading back gives the last value written, NOT the input value from the pins. If core 0 and core 1 both write to GPIO_HI_OUT simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result."] pub type GPIO_HI_OUT_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; impl R { - #[doc = "Bits 0:5 - Set output level (1/0 -> high/low) for QSPI IO0...5. - Reading back gives the last value written, NOT the input value from the pins. - If core 0 and core 1 both write to GPIO_HI_OUT simultaneously (or to a SET/CLR/XOR alias), - the result is as though the write from core 0 took place first, - and the write from core 1 was then applied to that intermediate result."] + #[doc = "Bits 0:5 - Set output level (1/0 -> high/low) for QSPI IO0...5. Reading back gives the last value written, NOT the input value from the pins. If core 0 and core 1 both write to GPIO_HI_OUT simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result."] #[inline(always)] pub fn gpio_hi_out(&self) -> GPIO_HI_OUT_R { GPIO_HI_OUT_R::new((self.bits & 0x3f) as u8) } } impl W { - #[doc = "Bits 0:5 - Set output level (1/0 -> high/low) for QSPI IO0...5. - Reading back gives the last value written, NOT the input value from the pins. - If core 0 and core 1 both write to GPIO_HI_OUT simultaneously (or to a SET/CLR/XOR alias), - the result is as though the write from core 0 took place first, - and the write from core 1 was then applied to that intermediate result."] + #[doc = "Bits 0:5 - Set output level (1/0 -> high/low) for QSPI IO0...5. Reading back gives the last value written, NOT the input value from the pins. If core 0 and core 1 both write to GPIO_HI_OUT simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result."] #[inline(always)] #[must_use] pub fn gpio_hi_out(&mut self) -> GPIO_HI_OUT_W { diff --git a/src/sio/gpio_hi_out_clr.rs b/src/sio/gpio_hi_out_clr.rs index 83f98f24f..c7f34b0c5 100644 --- a/src/sio/gpio_hi_out_clr.rs +++ b/src/sio/gpio_hi_out_clr.rs @@ -1,3 +1,5 @@ +#[doc = "Register `GPIO_HI_OUT_CLR` reader"] +pub type R = crate::R; #[doc = "Register `GPIO_HI_OUT_CLR` writer"] pub type W = crate::W; #[doc = "Field `GPIO_HI_OUT_CLR` writer - Perform an atomic bit-clear on GPIO_HI_OUT, i.e. `GPIO_HI_OUT &= ~wdata`"] @@ -12,11 +14,13 @@ impl W { } #[doc = "QSPI output value clear -You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_hi_out_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`gpio_hi_out_clr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_hi_out_clr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPIO_HI_OUT_CLR_SPEC; impl crate::RegisterSpec for GPIO_HI_OUT_CLR_SPEC { type Ux = u32; } +#[doc = "`read()` method returns [`gpio_hi_out_clr::R`](R) reader structure"] +impl crate::Readable for GPIO_HI_OUT_CLR_SPEC {} #[doc = "`write(|w| ..)` method takes [`gpio_hi_out_clr::W`](W) writer structure"] impl crate::Writable for GPIO_HI_OUT_CLR_SPEC { type Safety = crate::Unsafe; diff --git a/src/sio/gpio_hi_out_set.rs b/src/sio/gpio_hi_out_set.rs index f9b7d8e8d..969e43855 100644 --- a/src/sio/gpio_hi_out_set.rs +++ b/src/sio/gpio_hi_out_set.rs @@ -1,3 +1,5 @@ +#[doc = "Register `GPIO_HI_OUT_SET` reader"] +pub type R = crate::R; #[doc = "Register `GPIO_HI_OUT_SET` writer"] pub type W = crate::W; #[doc = "Field `GPIO_HI_OUT_SET` writer - Perform an atomic bit-set on GPIO_HI_OUT, i.e. `GPIO_HI_OUT |= wdata`"] @@ -12,11 +14,13 @@ impl W { } #[doc = "QSPI output value set -You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_hi_out_set::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`gpio_hi_out_set::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_hi_out_set::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPIO_HI_OUT_SET_SPEC; impl crate::RegisterSpec for GPIO_HI_OUT_SET_SPEC { type Ux = u32; } +#[doc = "`read()` method returns [`gpio_hi_out_set::R`](R) reader structure"] +impl crate::Readable for GPIO_HI_OUT_SET_SPEC {} #[doc = "`write(|w| ..)` method takes [`gpio_hi_out_set::W`](W) writer structure"] impl crate::Writable for GPIO_HI_OUT_SET_SPEC { type Safety = crate::Unsafe; diff --git a/src/sio/gpio_hi_out_xor.rs b/src/sio/gpio_hi_out_xor.rs index 791a410bd..87608def0 100644 --- a/src/sio/gpio_hi_out_xor.rs +++ b/src/sio/gpio_hi_out_xor.rs @@ -1,3 +1,5 @@ +#[doc = "Register `GPIO_HI_OUT_XOR` reader"] +pub type R = crate::R; #[doc = "Register `GPIO_HI_OUT_XOR` writer"] pub type W = crate::W; #[doc = "Field `GPIO_HI_OUT_XOR` writer - Perform an atomic bitwise XOR on GPIO_HI_OUT, i.e. `GPIO_HI_OUT ^= wdata`"] @@ -12,11 +14,13 @@ impl W { } #[doc = "QSPI output value XOR -You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_hi_out_xor::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`gpio_hi_out_xor::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_hi_out_xor::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPIO_HI_OUT_XOR_SPEC; impl crate::RegisterSpec for GPIO_HI_OUT_XOR_SPEC { type Ux = u32; } +#[doc = "`read()` method returns [`gpio_hi_out_xor::R`](R) reader structure"] +impl crate::Readable for GPIO_HI_OUT_XOR_SPEC {} #[doc = "`write(|w| ..)` method takes [`gpio_hi_out_xor::W`](W) writer structure"] impl crate::Writable for GPIO_HI_OUT_XOR_SPEC { type Safety = crate::Unsafe; diff --git a/src/sio/gpio_in.rs b/src/sio/gpio_in.rs index 618b234ea..114c1b27f 100644 --- a/src/sio/gpio_in.rs +++ b/src/sio/gpio_in.rs @@ -1,5 +1,7 @@ #[doc = "Register `GPIO_IN` reader"] pub type R = crate::R; +#[doc = "Register `GPIO_IN` writer"] +pub type W = crate::W; #[doc = "Field `GPIO_IN` reader - Input value for GPIO0...29"] pub type GPIO_IN_R = crate::FieldReader; impl R { @@ -9,15 +11,22 @@ impl R { GPIO_IN_R::new(self.bits & 0x3fff_ffff) } } +impl W {} #[doc = "Input value for GPIO pins -You can [`read`](crate::generic::Reg::read) this register and get [`gpio_in::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`gpio_in::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_in::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPIO_IN_SPEC; impl crate::RegisterSpec for GPIO_IN_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`gpio_in::R`](R) reader structure"] impl crate::Readable for GPIO_IN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio_in::W`](W) writer structure"] +impl crate::Writable for GPIO_IN_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets GPIO_IN to value 0"] impl crate::Resettable for GPIO_IN_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/sio/gpio_oe.rs b/src/sio/gpio_oe.rs index 0856f430d..205f32152 100644 --- a/src/sio/gpio_oe.rs +++ b/src/sio/gpio_oe.rs @@ -2,35 +2,19 @@ pub type R = crate::R; #[doc = "Register `GPIO_OE` writer"] pub type W = crate::W; -#[doc = "Field `GPIO_OE` reader - Set output enable (1/0 -> output/input) for GPIO0...29. - Reading back gives the last value written. - If core 0 and core 1 both write to GPIO_OE simultaneously (or to a SET/CLR/XOR alias), - the result is as though the write from core 0 took place first, - and the write from core 1 was then applied to that intermediate result."] +#[doc = "Field `GPIO_OE` reader - Set output enable (1/0 -> output/input) for GPIO0...29. Reading back gives the last value written. If core 0 and core 1 both write to GPIO_OE simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result."] pub type GPIO_OE_R = crate::FieldReader; -#[doc = "Field `GPIO_OE` writer - Set output enable (1/0 -> output/input) for GPIO0...29. - Reading back gives the last value written. - If core 0 and core 1 both write to GPIO_OE simultaneously (or to a SET/CLR/XOR alias), - the result is as though the write from core 0 took place first, - and the write from core 1 was then applied to that intermediate result."] +#[doc = "Field `GPIO_OE` writer - Set output enable (1/0 -> output/input) for GPIO0...29. Reading back gives the last value written. If core 0 and core 1 both write to GPIO_OE simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result."] pub type GPIO_OE_W<'a, REG> = crate::FieldWriter<'a, REG, 30, u32>; impl R { - #[doc = "Bits 0:29 - Set output enable (1/0 -> output/input) for GPIO0...29. - Reading back gives the last value written. - If core 0 and core 1 both write to GPIO_OE simultaneously (or to a SET/CLR/XOR alias), - the result is as though the write from core 0 took place first, - and the write from core 1 was then applied to that intermediate result."] + #[doc = "Bits 0:29 - Set output enable (1/0 -> output/input) for GPIO0...29. Reading back gives the last value written. If core 0 and core 1 both write to GPIO_OE simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result."] #[inline(always)] pub fn gpio_oe(&self) -> GPIO_OE_R { GPIO_OE_R::new(self.bits & 0x3fff_ffff) } } impl W { - #[doc = "Bits 0:29 - Set output enable (1/0 -> output/input) for GPIO0...29. - Reading back gives the last value written. - If core 0 and core 1 both write to GPIO_OE simultaneously (or to a SET/CLR/XOR alias), - the result is as though the write from core 0 took place first, - and the write from core 1 was then applied to that intermediate result."] + #[doc = "Bits 0:29 - Set output enable (1/0 -> output/input) for GPIO0...29. Reading back gives the last value written. If core 0 and core 1 both write to GPIO_OE simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result."] #[inline(always)] #[must_use] pub fn gpio_oe(&mut self) -> GPIO_OE_W { diff --git a/src/sio/gpio_oe_clr.rs b/src/sio/gpio_oe_clr.rs index 9fe86e678..5ebf453c1 100644 --- a/src/sio/gpio_oe_clr.rs +++ b/src/sio/gpio_oe_clr.rs @@ -1,3 +1,5 @@ +#[doc = "Register `GPIO_OE_CLR` reader"] +pub type R = crate::R; #[doc = "Register `GPIO_OE_CLR` writer"] pub type W = crate::W; #[doc = "Field `GPIO_OE_CLR` writer - Perform an atomic bit-clear on GPIO_OE, i.e. `GPIO_OE &= ~wdata`"] @@ -12,11 +14,13 @@ impl W { } #[doc = "GPIO output enable clear -You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_oe_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`gpio_oe_clr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_oe_clr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPIO_OE_CLR_SPEC; impl crate::RegisterSpec for GPIO_OE_CLR_SPEC { type Ux = u32; } +#[doc = "`read()` method returns [`gpio_oe_clr::R`](R) reader structure"] +impl crate::Readable for GPIO_OE_CLR_SPEC {} #[doc = "`write(|w| ..)` method takes [`gpio_oe_clr::W`](W) writer structure"] impl crate::Writable for GPIO_OE_CLR_SPEC { type Safety = crate::Unsafe; diff --git a/src/sio/gpio_oe_set.rs b/src/sio/gpio_oe_set.rs index f2adb3c2f..982f0a41b 100644 --- a/src/sio/gpio_oe_set.rs +++ b/src/sio/gpio_oe_set.rs @@ -1,3 +1,5 @@ +#[doc = "Register `GPIO_OE_SET` reader"] +pub type R = crate::R; #[doc = "Register `GPIO_OE_SET` writer"] pub type W = crate::W; #[doc = "Field `GPIO_OE_SET` writer - Perform an atomic bit-set on GPIO_OE, i.e. `GPIO_OE |= wdata`"] @@ -12,11 +14,13 @@ impl W { } #[doc = "GPIO output enable set -You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_oe_set::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`gpio_oe_set::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_oe_set::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPIO_OE_SET_SPEC; impl crate::RegisterSpec for GPIO_OE_SET_SPEC { type Ux = u32; } +#[doc = "`read()` method returns [`gpio_oe_set::R`](R) reader structure"] +impl crate::Readable for GPIO_OE_SET_SPEC {} #[doc = "`write(|w| ..)` method takes [`gpio_oe_set::W`](W) writer structure"] impl crate::Writable for GPIO_OE_SET_SPEC { type Safety = crate::Unsafe; diff --git a/src/sio/gpio_oe_xor.rs b/src/sio/gpio_oe_xor.rs index c45870cf6..a9acb2711 100644 --- a/src/sio/gpio_oe_xor.rs +++ b/src/sio/gpio_oe_xor.rs @@ -1,3 +1,5 @@ +#[doc = "Register `GPIO_OE_XOR` reader"] +pub type R = crate::R; #[doc = "Register `GPIO_OE_XOR` writer"] pub type W = crate::W; #[doc = "Field `GPIO_OE_XOR` writer - Perform an atomic bitwise XOR on GPIO_OE, i.e. `GPIO_OE ^= wdata`"] @@ -12,11 +14,13 @@ impl W { } #[doc = "GPIO output enable XOR -You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_oe_xor::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`gpio_oe_xor::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_oe_xor::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPIO_OE_XOR_SPEC; impl crate::RegisterSpec for GPIO_OE_XOR_SPEC { type Ux = u32; } +#[doc = "`read()` method returns [`gpio_oe_xor::R`](R) reader structure"] +impl crate::Readable for GPIO_OE_XOR_SPEC {} #[doc = "`write(|w| ..)` method takes [`gpio_oe_xor::W`](W) writer structure"] impl crate::Writable for GPIO_OE_XOR_SPEC { type Safety = crate::Unsafe; diff --git a/src/sio/gpio_out.rs b/src/sio/gpio_out.rs index 77b14ae53..d3f804fab 100644 --- a/src/sio/gpio_out.rs +++ b/src/sio/gpio_out.rs @@ -2,35 +2,19 @@ pub type R = crate::R; #[doc = "Register `GPIO_OUT` writer"] pub type W = crate::W; -#[doc = "Field `GPIO_OUT` reader - Set output level (1/0 -> high/low) for GPIO0...29. - Reading back gives the last value written, NOT the input value from the pins. - If core 0 and core 1 both write to GPIO_OUT simultaneously (or to a SET/CLR/XOR alias), - the result is as though the write from core 0 took place first, - and the write from core 1 was then applied to that intermediate result."] +#[doc = "Field `GPIO_OUT` reader - Set output level (1/0 -> high/low) for GPIO0...29. Reading back gives the last value written, NOT the input value from the pins. If core 0 and core 1 both write to GPIO_OUT simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result."] pub type GPIO_OUT_R = crate::FieldReader; -#[doc = "Field `GPIO_OUT` writer - Set output level (1/0 -> high/low) for GPIO0...29. - Reading back gives the last value written, NOT the input value from the pins. - If core 0 and core 1 both write to GPIO_OUT simultaneously (or to a SET/CLR/XOR alias), - the result is as though the write from core 0 took place first, - and the write from core 1 was then applied to that intermediate result."] +#[doc = "Field `GPIO_OUT` writer - Set output level (1/0 -> high/low) for GPIO0...29. Reading back gives the last value written, NOT the input value from the pins. If core 0 and core 1 both write to GPIO_OUT simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result."] pub type GPIO_OUT_W<'a, REG> = crate::FieldWriter<'a, REG, 30, u32>; impl R { - #[doc = "Bits 0:29 - Set output level (1/0 -> high/low) for GPIO0...29. - Reading back gives the last value written, NOT the input value from the pins. - If core 0 and core 1 both write to GPIO_OUT simultaneously (or to a SET/CLR/XOR alias), - the result is as though the write from core 0 took place first, - and the write from core 1 was then applied to that intermediate result."] + #[doc = "Bits 0:29 - Set output level (1/0 -> high/low) for GPIO0...29. Reading back gives the last value written, NOT the input value from the pins. If core 0 and core 1 both write to GPIO_OUT simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result."] #[inline(always)] pub fn gpio_out(&self) -> GPIO_OUT_R { GPIO_OUT_R::new(self.bits & 0x3fff_ffff) } } impl W { - #[doc = "Bits 0:29 - Set output level (1/0 -> high/low) for GPIO0...29. - Reading back gives the last value written, NOT the input value from the pins. - If core 0 and core 1 both write to GPIO_OUT simultaneously (or to a SET/CLR/XOR alias), - the result is as though the write from core 0 took place first, - and the write from core 1 was then applied to that intermediate result."] + #[doc = "Bits 0:29 - Set output level (1/0 -> high/low) for GPIO0...29. Reading back gives the last value written, NOT the input value from the pins. If core 0 and core 1 both write to GPIO_OUT simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result."] #[inline(always)] #[must_use] pub fn gpio_out(&mut self) -> GPIO_OUT_W { diff --git a/src/sio/gpio_out_clr.rs b/src/sio/gpio_out_clr.rs index d854fc1a0..14daf1697 100644 --- a/src/sio/gpio_out_clr.rs +++ b/src/sio/gpio_out_clr.rs @@ -1,3 +1,5 @@ +#[doc = "Register `GPIO_OUT_CLR` reader"] +pub type R = crate::R; #[doc = "Register `GPIO_OUT_CLR` writer"] pub type W = crate::W; #[doc = "Field `GPIO_OUT_CLR` writer - Perform an atomic bit-clear on GPIO_OUT, i.e. `GPIO_OUT &= ~wdata`"] @@ -12,11 +14,13 @@ impl W { } #[doc = "GPIO output value clear -You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_out_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`gpio_out_clr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_out_clr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPIO_OUT_CLR_SPEC; impl crate::RegisterSpec for GPIO_OUT_CLR_SPEC { type Ux = u32; } +#[doc = "`read()` method returns [`gpio_out_clr::R`](R) reader structure"] +impl crate::Readable for GPIO_OUT_CLR_SPEC {} #[doc = "`write(|w| ..)` method takes [`gpio_out_clr::W`](W) writer structure"] impl crate::Writable for GPIO_OUT_CLR_SPEC { type Safety = crate::Unsafe; diff --git a/src/sio/gpio_out_set.rs b/src/sio/gpio_out_set.rs index 11b64976f..51f3a9be3 100644 --- a/src/sio/gpio_out_set.rs +++ b/src/sio/gpio_out_set.rs @@ -1,3 +1,5 @@ +#[doc = "Register `GPIO_OUT_SET` reader"] +pub type R = crate::R; #[doc = "Register `GPIO_OUT_SET` writer"] pub type W = crate::W; #[doc = "Field `GPIO_OUT_SET` writer - Perform an atomic bit-set on GPIO_OUT, i.e. `GPIO_OUT |= wdata`"] @@ -12,11 +14,13 @@ impl W { } #[doc = "GPIO output value set -You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_out_set::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`gpio_out_set::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_out_set::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPIO_OUT_SET_SPEC; impl crate::RegisterSpec for GPIO_OUT_SET_SPEC { type Ux = u32; } +#[doc = "`read()` method returns [`gpio_out_set::R`](R) reader structure"] +impl crate::Readable for GPIO_OUT_SET_SPEC {} #[doc = "`write(|w| ..)` method takes [`gpio_out_set::W`](W) writer structure"] impl crate::Writable for GPIO_OUT_SET_SPEC { type Safety = crate::Unsafe; diff --git a/src/sio/gpio_out_xor.rs b/src/sio/gpio_out_xor.rs index 1e51f0029..0009c07bd 100644 --- a/src/sio/gpio_out_xor.rs +++ b/src/sio/gpio_out_xor.rs @@ -1,3 +1,5 @@ +#[doc = "Register `GPIO_OUT_XOR` reader"] +pub type R = crate::R; #[doc = "Register `GPIO_OUT_XOR` writer"] pub type W = crate::W; #[doc = "Field `GPIO_OUT_XOR` writer - Perform an atomic bitwise XOR on GPIO_OUT, i.e. `GPIO_OUT ^= wdata`"] @@ -12,11 +14,13 @@ impl W { } #[doc = "GPIO output value XOR -You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_out_xor::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`gpio_out_xor::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_out_xor::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GPIO_OUT_XOR_SPEC; impl crate::RegisterSpec for GPIO_OUT_XOR_SPEC { type Ux = u32; } +#[doc = "`read()` method returns [`gpio_out_xor::R`](R) reader structure"] +impl crate::Readable for GPIO_OUT_XOR_SPEC {} #[doc = "`write(|w| ..)` method takes [`gpio_out_xor::W`](W) writer structure"] impl crate::Writable for GPIO_OUT_XOR_SPEC { type Safety = crate::Unsafe; diff --git a/src/sio/interp0_accum0.rs b/src/sio/interp0_accum0.rs index ed7c47463..34dd4443c 100644 --- a/src/sio/interp0_accum0.rs +++ b/src/sio/interp0_accum0.rs @@ -2,17 +2,25 @@ pub type R = crate::R; #[doc = "Register `INTERP0_ACCUM0` writer"] pub type W = crate::W; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) +#[doc = "Field `INTERP0_ACCUM0` reader - "] +pub type INTERP0_ACCUM0_R = crate::FieldReader; +#[doc = "Field `INTERP0_ACCUM0` writer - "] +pub type INTERP0_ACCUM0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn interp0_accum0(&self) -> INTERP0_ACCUM0_R { + INTERP0_ACCUM0_R::new(self.bits) } } -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn interp0_accum0(&mut self) -> INTERP0_ACCUM0_W { + INTERP0_ACCUM0_W::new(self, 0) } } -impl W {} #[doc = "Read/write access to accumulator 0 You can [`read`](crate::generic::Reg::read) this register and get [`interp0_accum0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp0_accum0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] diff --git a/src/sio/interp0_accum0_add.rs b/src/sio/interp0_accum0_add.rs index 1addd12d8..215f16d1b 100644 --- a/src/sio/interp0_accum0_add.rs +++ b/src/sio/interp0_accum0_add.rs @@ -21,8 +21,7 @@ impl W { INTERP0_ACCUM0_ADD_W::new(self, 0) } } -#[doc = "Values written here are atomically added to ACCUM0 - Reading yields lane 0's raw shift and mask value (BASE0 not added). +#[doc = "Values written here are atomically added to ACCUM0 Reading yields lane 0's raw shift and mask value (BASE0 not added). You can [`read`](crate::generic::Reg::read) this register and get [`interp0_accum0_add::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp0_accum0_add::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTERP0_ACCUM0_ADD_SPEC; diff --git a/src/sio/interp0_accum1.rs b/src/sio/interp0_accum1.rs index 787d98c73..2d893c82f 100644 --- a/src/sio/interp0_accum1.rs +++ b/src/sio/interp0_accum1.rs @@ -2,17 +2,25 @@ pub type R = crate::R; #[doc = "Register `INTERP0_ACCUM1` writer"] pub type W = crate::W; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) +#[doc = "Field `INTERP0_ACCUM1` reader - "] +pub type INTERP0_ACCUM1_R = crate::FieldReader; +#[doc = "Field `INTERP0_ACCUM1` writer - "] +pub type INTERP0_ACCUM1_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn interp0_accum1(&self) -> INTERP0_ACCUM1_R { + INTERP0_ACCUM1_R::new(self.bits) } } -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn interp0_accum1(&mut self) -> INTERP0_ACCUM1_W { + INTERP0_ACCUM1_W::new(self, 0) } } -impl W {} #[doc = "Read/write access to accumulator 1 You can [`read`](crate::generic::Reg::read) this register and get [`interp0_accum1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp0_accum1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] diff --git a/src/sio/interp0_accum1_add.rs b/src/sio/interp0_accum1_add.rs index 86ec6c6f5..e4c0fc5a6 100644 --- a/src/sio/interp0_accum1_add.rs +++ b/src/sio/interp0_accum1_add.rs @@ -21,8 +21,7 @@ impl W { INTERP0_ACCUM1_ADD_W::new(self, 0) } } -#[doc = "Values written here are atomically added to ACCUM1 - Reading yields lane 1's raw shift and mask value (BASE1 not added). +#[doc = "Values written here are atomically added to ACCUM1 Reading yields lane 1's raw shift and mask value (BASE1 not added). You can [`read`](crate::generic::Reg::read) this register and get [`interp0_accum1_add::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp0_accum1_add::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTERP0_ACCUM1_ADD_SPEC; diff --git a/src/sio/interp0_base0.rs b/src/sio/interp0_base0.rs index adb318c1d..75a30a3f5 100644 --- a/src/sio/interp0_base0.rs +++ b/src/sio/interp0_base0.rs @@ -2,17 +2,25 @@ pub type R = crate::R; #[doc = "Register `INTERP0_BASE0` writer"] pub type W = crate::W; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) +#[doc = "Field `INTERP0_BASE0` reader - "] +pub type INTERP0_BASE0_R = crate::FieldReader; +#[doc = "Field `INTERP0_BASE0` writer - "] +pub type INTERP0_BASE0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn interp0_base0(&self) -> INTERP0_BASE0_R { + INTERP0_BASE0_R::new(self.bits) } } -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn interp0_base0(&mut self) -> INTERP0_BASE0_W { + INTERP0_BASE0_W::new(self, 0) } } -impl W {} #[doc = "Read/write access to BASE0 register. You can [`read`](crate::generic::Reg::read) this register and get [`interp0_base0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp0_base0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] diff --git a/src/sio/interp0_base1.rs b/src/sio/interp0_base1.rs index d22741585..3775b2958 100644 --- a/src/sio/interp0_base1.rs +++ b/src/sio/interp0_base1.rs @@ -2,17 +2,25 @@ pub type R = crate::R; #[doc = "Register `INTERP0_BASE1` writer"] pub type W = crate::W; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) +#[doc = "Field `INTERP0_BASE1` reader - "] +pub type INTERP0_BASE1_R = crate::FieldReader; +#[doc = "Field `INTERP0_BASE1` writer - "] +pub type INTERP0_BASE1_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn interp0_base1(&self) -> INTERP0_BASE1_R { + INTERP0_BASE1_R::new(self.bits) } } -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn interp0_base1(&mut self) -> INTERP0_BASE1_W { + INTERP0_BASE1_W::new(self, 0) } } -impl W {} #[doc = "Read/write access to BASE1 register. You can [`read`](crate::generic::Reg::read) this register and get [`interp0_base1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp0_base1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] diff --git a/src/sio/interp0_base2.rs b/src/sio/interp0_base2.rs index 93931169f..f10e010d1 100644 --- a/src/sio/interp0_base2.rs +++ b/src/sio/interp0_base2.rs @@ -2,17 +2,25 @@ pub type R = crate::R; #[doc = "Register `INTERP0_BASE2` writer"] pub type W = crate::W; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) +#[doc = "Field `INTERP0_BASE2` reader - "] +pub type INTERP0_BASE2_R = crate::FieldReader; +#[doc = "Field `INTERP0_BASE2` writer - "] +pub type INTERP0_BASE2_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn interp0_base2(&self) -> INTERP0_BASE2_R { + INTERP0_BASE2_R::new(self.bits) } } -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn interp0_base2(&mut self) -> INTERP0_BASE2_W { + INTERP0_BASE2_W::new(self, 0) } } -impl W {} #[doc = "Read/write access to BASE2 register. You can [`read`](crate::generic::Reg::read) this register and get [`interp0_base2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp0_base2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] diff --git a/src/sio/interp0_base_1and0.rs b/src/sio/interp0_base_1and0.rs index 8f705a5da..46edd4ec0 100644 --- a/src/sio/interp0_base_1and0.rs +++ b/src/sio/interp0_base_1and0.rs @@ -1,19 +1,26 @@ +#[doc = "Register `INTERP0_BASE_1AND0` reader"] +pub type R = crate::R; #[doc = "Register `INTERP0_BASE_1AND0` writer"] pub type W = crate::W; -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - write!(f, "(not readable)") +#[doc = "Field `INTERP0_BASE_1AND0` writer - "] +pub type INTERP0_BASE_1AND0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn interp0_base_1and0(&mut self) -> INTERP0_BASE_1AND0_W { + INTERP0_BASE_1AND0_W::new(self, 0) } } -impl W {} -#[doc = "On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously. - Each half is sign-extended to 32 bits if that lane's SIGNED flag is set. +#[doc = "On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously. Each half is sign-extended to 32 bits if that lane's SIGNED flag is set. -You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp0_base_1and0::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`interp0_base_1and0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp0_base_1and0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTERP0_BASE_1AND0_SPEC; impl crate::RegisterSpec for INTERP0_BASE_1AND0_SPEC { type Ux = u32; } +#[doc = "`read()` method returns [`interp0_base_1and0::R`](R) reader structure"] +impl crate::Readable for INTERP0_BASE_1AND0_SPEC {} #[doc = "`write(|w| ..)` method takes [`interp0_base_1and0::W`](W) writer structure"] impl crate::Writable for INTERP0_BASE_1AND0_SPEC { type Safety = crate::Unsafe; diff --git a/src/sio/interp0_ctrl_lane0.rs b/src/sio/interp0_ctrl_lane0.rs index e5d70135f..bb572c9fa 100644 --- a/src/sio/interp0_ctrl_lane0.rs +++ b/src/sio/interp0_ctrl_lane0.rs @@ -10,23 +10,17 @@ pub type SHIFT_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; pub type MASK_LSB_R = crate::FieldReader; #[doc = "Field `MASK_LSB` writer - The least-significant bit allowed to pass by the mask (inclusive)"] pub type MASK_LSB_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; -#[doc = "Field `MASK_MSB` reader - The most-significant bit allowed to pass by the mask (inclusive) - Setting MSB < LSB may cause chip to turn inside-out"] +#[doc = "Field `MASK_MSB` reader - The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out"] pub type MASK_MSB_R = crate::FieldReader; -#[doc = "Field `MASK_MSB` writer - The most-significant bit allowed to pass by the mask (inclusive) - Setting MSB < LSB may cause chip to turn inside-out"] +#[doc = "Field `MASK_MSB` writer - The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out"] pub type MASK_MSB_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; -#[doc = "Field `SIGNED` reader - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits - before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor."] +#[doc = "Field `SIGNED` reader - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor."] pub type SIGNED_R = crate::BitReader; -#[doc = "Field `SIGNED` writer - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits - before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor."] +#[doc = "Field `SIGNED` writer - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor."] pub type SIGNED_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CROSS_INPUT` reader - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. - Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"] +#[doc = "Field `CROSS_INPUT` reader - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"] pub type CROSS_INPUT_R = crate::BitReader; -#[doc = "Field `CROSS_INPUT` writer - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. - Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"] +#[doc = "Field `CROSS_INPUT` writer - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"] pub type CROSS_INPUT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `CROSS_RESULT` reader - If 1, feed the opposite lane's result into this lane's accumulator on POP."] pub type CROSS_RESULT_R = crate::BitReader; @@ -36,29 +30,13 @@ pub type CROSS_RESULT_W<'a, REG> = crate::BitWriter<'a, REG>; pub type ADD_RAW_R = crate::BitReader; #[doc = "Field `ADD_RAW` writer - If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result."] pub type ADD_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `FORCE_MSB` reader - ORed into bits 29:28 of the lane result presented to the processor on the bus. - No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence - of pointers into flash or SRAM."] +#[doc = "Field `FORCE_MSB` reader - ORed into bits 29:28 of the lane result presented to the processor on the bus. No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence of pointers into flash or SRAM."] pub type FORCE_MSB_R = crate::FieldReader; -#[doc = "Field `FORCE_MSB` writer - ORed into bits 29:28 of the lane result presented to the processor on the bus. - No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence - of pointers into flash or SRAM."] +#[doc = "Field `FORCE_MSB` writer - ORed into bits 29:28 of the lane result presented to the processor on the bus. No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence of pointers into flash or SRAM."] pub type FORCE_MSB_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `BLEND` reader - Only present on INTERP0 on each core. If BLEND mode is enabled: - - LANE1 result is a linear interpolation between BASE0 and BASE1, controlled - by the 8 LSBs of lane 1 shift and mask value (a fractional number between - 0 and 255/256ths) - - LANE0 result does not have BASE0 added (yields only the 8 LSBs of lane 1 shift+mask value) - - FULL result does not have lane 1 shift+mask value added (BASE2 + lane 0 shift+mask) - LANE1 SIGNED flag controls whether the interpolation is signed or unsigned."] +#[doc = "Field `BLEND` reader - Only present on INTERP0 on each core. If BLEND mode is enabled: - LANE1 result is a linear interpolation between BASE0 and BASE1, controlled by the 8 LSBs of lane 1 shift and mask value (a fractional number between 0 and 255/256ths) - LANE0 result does not have BASE0 added (yields only the 8 LSBs of lane 1 shift+mask value) - FULL result does not have lane 1 shift+mask value added (BASE2 + lane 0 shift+mask) LANE1 SIGNED flag controls whether the interpolation is signed or unsigned."] pub type BLEND_R = crate::BitReader; -#[doc = "Field `BLEND` writer - Only present on INTERP0 on each core. If BLEND mode is enabled: - - LANE1 result is a linear interpolation between BASE0 and BASE1, controlled - by the 8 LSBs of lane 1 shift and mask value (a fractional number between - 0 and 255/256ths) - - LANE0 result does not have BASE0 added (yields only the 8 LSBs of lane 1 shift+mask value) - - FULL result does not have lane 1 shift+mask value added (BASE2 + lane 0 shift+mask) - LANE1 SIGNED flag controls whether the interpolation is signed or unsigned."] +#[doc = "Field `BLEND` writer - Only present on INTERP0 on each core. If BLEND mode is enabled: - LANE1 result is a linear interpolation between BASE0 and BASE1, controlled by the 8 LSBs of lane 1 shift and mask value (a fractional number between 0 and 255/256ths) - LANE0 result does not have BASE0 added (yields only the 8 LSBs of lane 1 shift+mask value) - FULL result does not have lane 1 shift+mask value added (BASE2 + lane 0 shift+mask) LANE1 SIGNED flag controls whether the interpolation is signed or unsigned."] pub type BLEND_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `OVERF0` reader - Indicates if any masked-off MSBs in ACCUM0 are set."] pub type OVERF0_R = crate::BitReader; @@ -77,20 +55,17 @@ impl R { pub fn mask_lsb(&self) -> MASK_LSB_R { MASK_LSB_R::new(((self.bits >> 5) & 0x1f) as u8) } - #[doc = "Bits 10:14 - The most-significant bit allowed to pass by the mask (inclusive) - Setting MSB < LSB may cause chip to turn inside-out"] + #[doc = "Bits 10:14 - The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out"] #[inline(always)] pub fn mask_msb(&self) -> MASK_MSB_R { MASK_MSB_R::new(((self.bits >> 10) & 0x1f) as u8) } - #[doc = "Bit 15 - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits - before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor."] + #[doc = "Bit 15 - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor."] #[inline(always)] pub fn signed(&self) -> SIGNED_R { SIGNED_R::new(((self.bits >> 15) & 1) != 0) } - #[doc = "Bit 16 - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. - Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"] + #[doc = "Bit 16 - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"] #[inline(always)] pub fn cross_input(&self) -> CROSS_INPUT_R { CROSS_INPUT_R::new(((self.bits >> 16) & 1) != 0) @@ -105,20 +80,12 @@ impl R { pub fn add_raw(&self) -> ADD_RAW_R { ADD_RAW_R::new(((self.bits >> 18) & 1) != 0) } - #[doc = "Bits 19:20 - ORed into bits 29:28 of the lane result presented to the processor on the bus. - No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence - of pointers into flash or SRAM."] + #[doc = "Bits 19:20 - ORed into bits 29:28 of the lane result presented to the processor on the bus. No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence of pointers into flash or SRAM."] #[inline(always)] pub fn force_msb(&self) -> FORCE_MSB_R { FORCE_MSB_R::new(((self.bits >> 19) & 3) as u8) } - #[doc = "Bit 21 - Only present on INTERP0 on each core. If BLEND mode is enabled: - - LANE1 result is a linear interpolation between BASE0 and BASE1, controlled - by the 8 LSBs of lane 1 shift and mask value (a fractional number between - 0 and 255/256ths) - - LANE0 result does not have BASE0 added (yields only the 8 LSBs of lane 1 shift+mask value) - - FULL result does not have lane 1 shift+mask value added (BASE2 + lane 0 shift+mask) - LANE1 SIGNED flag controls whether the interpolation is signed or unsigned."] + #[doc = "Bit 21 - Only present on INTERP0 on each core. If BLEND mode is enabled: - LANE1 result is a linear interpolation between BASE0 and BASE1, controlled by the 8 LSBs of lane 1 shift and mask value (a fractional number between 0 and 255/256ths) - LANE0 result does not have BASE0 added (yields only the 8 LSBs of lane 1 shift+mask value) - FULL result does not have lane 1 shift+mask value added (BASE2 + lane 0 shift+mask) LANE1 SIGNED flag controls whether the interpolation is signed or unsigned."] #[inline(always)] pub fn blend(&self) -> BLEND_R { BLEND_R::new(((self.bits >> 21) & 1) != 0) @@ -152,22 +119,19 @@ impl W { pub fn mask_lsb(&mut self) -> MASK_LSB_W { MASK_LSB_W::new(self, 5) } - #[doc = "Bits 10:14 - The most-significant bit allowed to pass by the mask (inclusive) - Setting MSB < LSB may cause chip to turn inside-out"] + #[doc = "Bits 10:14 - The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out"] #[inline(always)] #[must_use] pub fn mask_msb(&mut self) -> MASK_MSB_W { MASK_MSB_W::new(self, 10) } - #[doc = "Bit 15 - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits - before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor."] + #[doc = "Bit 15 - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor."] #[inline(always)] #[must_use] pub fn signed(&mut self) -> SIGNED_W { SIGNED_W::new(self, 15) } - #[doc = "Bit 16 - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. - Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"] + #[doc = "Bit 16 - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"] #[inline(always)] #[must_use] pub fn cross_input(&mut self) -> CROSS_INPUT_W { @@ -185,21 +149,13 @@ impl W { pub fn add_raw(&mut self) -> ADD_RAW_W { ADD_RAW_W::new(self, 18) } - #[doc = "Bits 19:20 - ORed into bits 29:28 of the lane result presented to the processor on the bus. - No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence - of pointers into flash or SRAM."] + #[doc = "Bits 19:20 - ORed into bits 29:28 of the lane result presented to the processor on the bus. No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence of pointers into flash or SRAM."] #[inline(always)] #[must_use] pub fn force_msb(&mut self) -> FORCE_MSB_W { FORCE_MSB_W::new(self, 19) } - #[doc = "Bit 21 - Only present on INTERP0 on each core. If BLEND mode is enabled: - - LANE1 result is a linear interpolation between BASE0 and BASE1, controlled - by the 8 LSBs of lane 1 shift and mask value (a fractional number between - 0 and 255/256ths) - - LANE0 result does not have BASE0 added (yields only the 8 LSBs of lane 1 shift+mask value) - - FULL result does not have lane 1 shift+mask value added (BASE2 + lane 0 shift+mask) - LANE1 SIGNED flag controls whether the interpolation is signed or unsigned."] + #[doc = "Bit 21 - Only present on INTERP0 on each core. If BLEND mode is enabled: - LANE1 result is a linear interpolation between BASE0 and BASE1, controlled by the 8 LSBs of lane 1 shift and mask value (a fractional number between 0 and 255/256ths) - LANE0 result does not have BASE0 added (yields only the 8 LSBs of lane 1 shift+mask value) - FULL result does not have lane 1 shift+mask value added (BASE2 + lane 0 shift+mask) LANE1 SIGNED flag controls whether the interpolation is signed or unsigned."] #[inline(always)] #[must_use] pub fn blend(&mut self) -> BLEND_W { diff --git a/src/sio/interp0_ctrl_lane1.rs b/src/sio/interp0_ctrl_lane1.rs index 3f27fbab6..ab843c924 100644 --- a/src/sio/interp0_ctrl_lane1.rs +++ b/src/sio/interp0_ctrl_lane1.rs @@ -10,23 +10,17 @@ pub type SHIFT_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; pub type MASK_LSB_R = crate::FieldReader; #[doc = "Field `MASK_LSB` writer - The least-significant bit allowed to pass by the mask (inclusive)"] pub type MASK_LSB_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; -#[doc = "Field `MASK_MSB` reader - The most-significant bit allowed to pass by the mask (inclusive) - Setting MSB < LSB may cause chip to turn inside-out"] +#[doc = "Field `MASK_MSB` reader - The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out"] pub type MASK_MSB_R = crate::FieldReader; -#[doc = "Field `MASK_MSB` writer - The most-significant bit allowed to pass by the mask (inclusive) - Setting MSB < LSB may cause chip to turn inside-out"] +#[doc = "Field `MASK_MSB` writer - The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out"] pub type MASK_MSB_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; -#[doc = "Field `SIGNED` reader - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits - before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor."] +#[doc = "Field `SIGNED` reader - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor."] pub type SIGNED_R = crate::BitReader; -#[doc = "Field `SIGNED` writer - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits - before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor."] +#[doc = "Field `SIGNED` writer - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor."] pub type SIGNED_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CROSS_INPUT` reader - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. - Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"] +#[doc = "Field `CROSS_INPUT` reader - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"] pub type CROSS_INPUT_R = crate::BitReader; -#[doc = "Field `CROSS_INPUT` writer - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. - Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"] +#[doc = "Field `CROSS_INPUT` writer - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"] pub type CROSS_INPUT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `CROSS_RESULT` reader - If 1, feed the opposite lane's result into this lane's accumulator on POP."] pub type CROSS_RESULT_R = crate::BitReader; @@ -36,13 +30,9 @@ pub type CROSS_RESULT_W<'a, REG> = crate::BitWriter<'a, REG>; pub type ADD_RAW_R = crate::BitReader; #[doc = "Field `ADD_RAW` writer - If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result."] pub type ADD_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `FORCE_MSB` reader - ORed into bits 29:28 of the lane result presented to the processor on the bus. - No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence - of pointers into flash or SRAM."] +#[doc = "Field `FORCE_MSB` reader - ORed into bits 29:28 of the lane result presented to the processor on the bus. No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence of pointers into flash or SRAM."] pub type FORCE_MSB_R = crate::FieldReader; -#[doc = "Field `FORCE_MSB` writer - ORed into bits 29:28 of the lane result presented to the processor on the bus. - No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence - of pointers into flash or SRAM."] +#[doc = "Field `FORCE_MSB` writer - ORed into bits 29:28 of the lane result presented to the processor on the bus. No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence of pointers into flash or SRAM."] pub type FORCE_MSB_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:4 - Logical right-shift applied to accumulator before masking"] @@ -55,20 +45,17 @@ impl R { pub fn mask_lsb(&self) -> MASK_LSB_R { MASK_LSB_R::new(((self.bits >> 5) & 0x1f) as u8) } - #[doc = "Bits 10:14 - The most-significant bit allowed to pass by the mask (inclusive) - Setting MSB < LSB may cause chip to turn inside-out"] + #[doc = "Bits 10:14 - The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out"] #[inline(always)] pub fn mask_msb(&self) -> MASK_MSB_R { MASK_MSB_R::new(((self.bits >> 10) & 0x1f) as u8) } - #[doc = "Bit 15 - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits - before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor."] + #[doc = "Bit 15 - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor."] #[inline(always)] pub fn signed(&self) -> SIGNED_R { SIGNED_R::new(((self.bits >> 15) & 1) != 0) } - #[doc = "Bit 16 - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. - Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"] + #[doc = "Bit 16 - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"] #[inline(always)] pub fn cross_input(&self) -> CROSS_INPUT_R { CROSS_INPUT_R::new(((self.bits >> 16) & 1) != 0) @@ -83,9 +70,7 @@ impl R { pub fn add_raw(&self) -> ADD_RAW_R { ADD_RAW_R::new(((self.bits >> 18) & 1) != 0) } - #[doc = "Bits 19:20 - ORed into bits 29:28 of the lane result presented to the processor on the bus. - No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence - of pointers into flash or SRAM."] + #[doc = "Bits 19:20 - ORed into bits 29:28 of the lane result presented to the processor on the bus. No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence of pointers into flash or SRAM."] #[inline(always)] pub fn force_msb(&self) -> FORCE_MSB_R { FORCE_MSB_R::new(((self.bits >> 19) & 3) as u8) @@ -104,22 +89,19 @@ impl W { pub fn mask_lsb(&mut self) -> MASK_LSB_W { MASK_LSB_W::new(self, 5) } - #[doc = "Bits 10:14 - The most-significant bit allowed to pass by the mask (inclusive) - Setting MSB < LSB may cause chip to turn inside-out"] + #[doc = "Bits 10:14 - The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out"] #[inline(always)] #[must_use] pub fn mask_msb(&mut self) -> MASK_MSB_W { MASK_MSB_W::new(self, 10) } - #[doc = "Bit 15 - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits - before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor."] + #[doc = "Bit 15 - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor."] #[inline(always)] #[must_use] pub fn signed(&mut self) -> SIGNED_W { SIGNED_W::new(self, 15) } - #[doc = "Bit 16 - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. - Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"] + #[doc = "Bit 16 - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"] #[inline(always)] #[must_use] pub fn cross_input(&mut self) -> CROSS_INPUT_W { @@ -137,9 +119,7 @@ impl W { pub fn add_raw(&mut self) -> ADD_RAW_W { ADD_RAW_W::new(self, 18) } - #[doc = "Bits 19:20 - ORed into bits 29:28 of the lane result presented to the processor on the bus. - No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence - of pointers into flash or SRAM."] + #[doc = "Bits 19:20 - ORed into bits 29:28 of the lane result presented to the processor on the bus. No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence of pointers into flash or SRAM."] #[inline(always)] #[must_use] pub fn force_msb(&mut self) -> FORCE_MSB_W { diff --git a/src/sio/interp0_peek_full.rs b/src/sio/interp0_peek_full.rs index 0098698b8..5f717aa93 100644 --- a/src/sio/interp0_peek_full.rs +++ b/src/sio/interp0_peek_full.rs @@ -1,24 +1,32 @@ #[doc = "Register `INTERP0_PEEK_FULL` reader"] pub type R = crate::R; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) - } -} -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +#[doc = "Register `INTERP0_PEEK_FULL` writer"] +pub type W = crate::W; +#[doc = "Field `INTERP0_PEEK_FULL` reader - "] +pub type INTERP0_PEEK_FULL_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn interp0_peek_full(&self) -> INTERP0_PEEK_FULL_R { + INTERP0_PEEK_FULL_R::new(self.bits) } } +impl W {} #[doc = "Read FULL result, without altering any internal state (PEEK). -You can [`read`](crate::generic::Reg::read) this register and get [`interp0_peek_full::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`interp0_peek_full::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp0_peek_full::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTERP0_PEEK_FULL_SPEC; impl crate::RegisterSpec for INTERP0_PEEK_FULL_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`interp0_peek_full::R`](R) reader structure"] impl crate::Readable for INTERP0_PEEK_FULL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`interp0_peek_full::W`](W) writer structure"] +impl crate::Writable for INTERP0_PEEK_FULL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets INTERP0_PEEK_FULL to value 0"] impl crate::Resettable for INTERP0_PEEK_FULL_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/sio/interp0_peek_lane0.rs b/src/sio/interp0_peek_lane0.rs index 12dd8e331..c5cc63e4e 100644 --- a/src/sio/interp0_peek_lane0.rs +++ b/src/sio/interp0_peek_lane0.rs @@ -1,24 +1,32 @@ #[doc = "Register `INTERP0_PEEK_LANE0` reader"] pub type R = crate::R; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) - } -} -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +#[doc = "Register `INTERP0_PEEK_LANE0` writer"] +pub type W = crate::W; +#[doc = "Field `INTERP0_PEEK_LANE0` reader - "] +pub type INTERP0_PEEK_LANE0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn interp0_peek_lane0(&self) -> INTERP0_PEEK_LANE0_R { + INTERP0_PEEK_LANE0_R::new(self.bits) } } +impl W {} #[doc = "Read LANE0 result, without altering any internal state (PEEK). -You can [`read`](crate::generic::Reg::read) this register and get [`interp0_peek_lane0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`interp0_peek_lane0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp0_peek_lane0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTERP0_PEEK_LANE0_SPEC; impl crate::RegisterSpec for INTERP0_PEEK_LANE0_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`interp0_peek_lane0::R`](R) reader structure"] impl crate::Readable for INTERP0_PEEK_LANE0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`interp0_peek_lane0::W`](W) writer structure"] +impl crate::Writable for INTERP0_PEEK_LANE0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets INTERP0_PEEK_LANE0 to value 0"] impl crate::Resettable for INTERP0_PEEK_LANE0_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/sio/interp0_peek_lane1.rs b/src/sio/interp0_peek_lane1.rs index 16de12b8b..5b63fd574 100644 --- a/src/sio/interp0_peek_lane1.rs +++ b/src/sio/interp0_peek_lane1.rs @@ -1,24 +1,32 @@ #[doc = "Register `INTERP0_PEEK_LANE1` reader"] pub type R = crate::R; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) - } -} -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +#[doc = "Register `INTERP0_PEEK_LANE1` writer"] +pub type W = crate::W; +#[doc = "Field `INTERP0_PEEK_LANE1` reader - "] +pub type INTERP0_PEEK_LANE1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn interp0_peek_lane1(&self) -> INTERP0_PEEK_LANE1_R { + INTERP0_PEEK_LANE1_R::new(self.bits) } } +impl W {} #[doc = "Read LANE1 result, without altering any internal state (PEEK). -You can [`read`](crate::generic::Reg::read) this register and get [`interp0_peek_lane1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`interp0_peek_lane1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp0_peek_lane1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTERP0_PEEK_LANE1_SPEC; impl crate::RegisterSpec for INTERP0_PEEK_LANE1_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`interp0_peek_lane1::R`](R) reader structure"] impl crate::Readable for INTERP0_PEEK_LANE1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`interp0_peek_lane1::W`](W) writer structure"] +impl crate::Writable for INTERP0_PEEK_LANE1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets INTERP0_PEEK_LANE1 to value 0"] impl crate::Resettable for INTERP0_PEEK_LANE1_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/sio/interp0_pop_full.rs b/src/sio/interp0_pop_full.rs index 85d27ade5..02dfada7f 100644 --- a/src/sio/interp0_pop_full.rs +++ b/src/sio/interp0_pop_full.rs @@ -1,24 +1,32 @@ #[doc = "Register `INTERP0_POP_FULL` reader"] pub type R = crate::R; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) - } -} -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +#[doc = "Register `INTERP0_POP_FULL` writer"] +pub type W = crate::W; +#[doc = "Field `INTERP0_POP_FULL` reader - "] +pub type INTERP0_POP_FULL_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn interp0_pop_full(&self) -> INTERP0_POP_FULL_R { + INTERP0_POP_FULL_R::new(self.bits) } } +impl W {} #[doc = "Read FULL result, and simultaneously write lane results to both accumulators (POP). -You can [`read`](crate::generic::Reg::read) this register and get [`interp0_pop_full::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`interp0_pop_full::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp0_pop_full::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTERP0_POP_FULL_SPEC; impl crate::RegisterSpec for INTERP0_POP_FULL_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`interp0_pop_full::R`](R) reader structure"] impl crate::Readable for INTERP0_POP_FULL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`interp0_pop_full::W`](W) writer structure"] +impl crate::Writable for INTERP0_POP_FULL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets INTERP0_POP_FULL to value 0"] impl crate::Resettable for INTERP0_POP_FULL_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/sio/interp0_pop_lane0.rs b/src/sio/interp0_pop_lane0.rs index 084d3f958..13bf8b4fd 100644 --- a/src/sio/interp0_pop_lane0.rs +++ b/src/sio/interp0_pop_lane0.rs @@ -1,24 +1,32 @@ #[doc = "Register `INTERP0_POP_LANE0` reader"] pub type R = crate::R; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) - } -} -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +#[doc = "Register `INTERP0_POP_LANE0` writer"] +pub type W = crate::W; +#[doc = "Field `INTERP0_POP_LANE0` reader - "] +pub type INTERP0_POP_LANE0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn interp0_pop_lane0(&self) -> INTERP0_POP_LANE0_R { + INTERP0_POP_LANE0_R::new(self.bits) } } +impl W {} #[doc = "Read LANE0 result, and simultaneously write lane results to both accumulators (POP). -You can [`read`](crate::generic::Reg::read) this register and get [`interp0_pop_lane0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`interp0_pop_lane0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp0_pop_lane0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTERP0_POP_LANE0_SPEC; impl crate::RegisterSpec for INTERP0_POP_LANE0_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`interp0_pop_lane0::R`](R) reader structure"] impl crate::Readable for INTERP0_POP_LANE0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`interp0_pop_lane0::W`](W) writer structure"] +impl crate::Writable for INTERP0_POP_LANE0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets INTERP0_POP_LANE0 to value 0"] impl crate::Resettable for INTERP0_POP_LANE0_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/sio/interp0_pop_lane1.rs b/src/sio/interp0_pop_lane1.rs index 654bc12b6..69cee3289 100644 --- a/src/sio/interp0_pop_lane1.rs +++ b/src/sio/interp0_pop_lane1.rs @@ -1,24 +1,32 @@ #[doc = "Register `INTERP0_POP_LANE1` reader"] pub type R = crate::R; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) - } -} -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +#[doc = "Register `INTERP0_POP_LANE1` writer"] +pub type W = crate::W; +#[doc = "Field `INTERP0_POP_LANE1` reader - "] +pub type INTERP0_POP_LANE1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn interp0_pop_lane1(&self) -> INTERP0_POP_LANE1_R { + INTERP0_POP_LANE1_R::new(self.bits) } } +impl W {} #[doc = "Read LANE1 result, and simultaneously write lane results to both accumulators (POP). -You can [`read`](crate::generic::Reg::read) this register and get [`interp0_pop_lane1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`interp0_pop_lane1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp0_pop_lane1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTERP0_POP_LANE1_SPEC; impl crate::RegisterSpec for INTERP0_POP_LANE1_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`interp0_pop_lane1::R`](R) reader structure"] impl crate::Readable for INTERP0_POP_LANE1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`interp0_pop_lane1::W`](W) writer structure"] +impl crate::Writable for INTERP0_POP_LANE1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets INTERP0_POP_LANE1 to value 0"] impl crate::Resettable for INTERP0_POP_LANE1_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/sio/interp1_accum0.rs b/src/sio/interp1_accum0.rs index fb71f4bbc..9367988bb 100644 --- a/src/sio/interp1_accum0.rs +++ b/src/sio/interp1_accum0.rs @@ -2,17 +2,25 @@ pub type R = crate::R; #[doc = "Register `INTERP1_ACCUM0` writer"] pub type W = crate::W; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) +#[doc = "Field `INTERP1_ACCUM0` reader - "] +pub type INTERP1_ACCUM0_R = crate::FieldReader; +#[doc = "Field `INTERP1_ACCUM0` writer - "] +pub type INTERP1_ACCUM0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn interp1_accum0(&self) -> INTERP1_ACCUM0_R { + INTERP1_ACCUM0_R::new(self.bits) } } -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn interp1_accum0(&mut self) -> INTERP1_ACCUM0_W { + INTERP1_ACCUM0_W::new(self, 0) } } -impl W {} #[doc = "Read/write access to accumulator 0 You can [`read`](crate::generic::Reg::read) this register and get [`interp1_accum0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp1_accum0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] diff --git a/src/sio/interp1_accum0_add.rs b/src/sio/interp1_accum0_add.rs index 98b58b1a9..4e30e3969 100644 --- a/src/sio/interp1_accum0_add.rs +++ b/src/sio/interp1_accum0_add.rs @@ -21,8 +21,7 @@ impl W { INTERP1_ACCUM0_ADD_W::new(self, 0) } } -#[doc = "Values written here are atomically added to ACCUM0 - Reading yields lane 0's raw shift and mask value (BASE0 not added). +#[doc = "Values written here are atomically added to ACCUM0 Reading yields lane 0's raw shift and mask value (BASE0 not added). You can [`read`](crate::generic::Reg::read) this register and get [`interp1_accum0_add::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp1_accum0_add::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTERP1_ACCUM0_ADD_SPEC; diff --git a/src/sio/interp1_accum1.rs b/src/sio/interp1_accum1.rs index cb4174a1c..a80bd6f51 100644 --- a/src/sio/interp1_accum1.rs +++ b/src/sio/interp1_accum1.rs @@ -2,17 +2,25 @@ pub type R = crate::R; #[doc = "Register `INTERP1_ACCUM1` writer"] pub type W = crate::W; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) +#[doc = "Field `INTERP1_ACCUM1` reader - "] +pub type INTERP1_ACCUM1_R = crate::FieldReader; +#[doc = "Field `INTERP1_ACCUM1` writer - "] +pub type INTERP1_ACCUM1_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn interp1_accum1(&self) -> INTERP1_ACCUM1_R { + INTERP1_ACCUM1_R::new(self.bits) } } -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn interp1_accum1(&mut self) -> INTERP1_ACCUM1_W { + INTERP1_ACCUM1_W::new(self, 0) } } -impl W {} #[doc = "Read/write access to accumulator 1 You can [`read`](crate::generic::Reg::read) this register and get [`interp1_accum1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp1_accum1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] diff --git a/src/sio/interp1_accum1_add.rs b/src/sio/interp1_accum1_add.rs index 7d4194fb6..51a10f2be 100644 --- a/src/sio/interp1_accum1_add.rs +++ b/src/sio/interp1_accum1_add.rs @@ -21,8 +21,7 @@ impl W { INTERP1_ACCUM1_ADD_W::new(self, 0) } } -#[doc = "Values written here are atomically added to ACCUM1 - Reading yields lane 1's raw shift and mask value (BASE1 not added). +#[doc = "Values written here are atomically added to ACCUM1 Reading yields lane 1's raw shift and mask value (BASE1 not added). You can [`read`](crate::generic::Reg::read) this register and get [`interp1_accum1_add::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp1_accum1_add::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTERP1_ACCUM1_ADD_SPEC; diff --git a/src/sio/interp1_base0.rs b/src/sio/interp1_base0.rs index 91dc452e4..f72ff2646 100644 --- a/src/sio/interp1_base0.rs +++ b/src/sio/interp1_base0.rs @@ -2,17 +2,25 @@ pub type R = crate::R; #[doc = "Register `INTERP1_BASE0` writer"] pub type W = crate::W; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) +#[doc = "Field `INTERP1_BASE0` reader - "] +pub type INTERP1_BASE0_R = crate::FieldReader; +#[doc = "Field `INTERP1_BASE0` writer - "] +pub type INTERP1_BASE0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn interp1_base0(&self) -> INTERP1_BASE0_R { + INTERP1_BASE0_R::new(self.bits) } } -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn interp1_base0(&mut self) -> INTERP1_BASE0_W { + INTERP1_BASE0_W::new(self, 0) } } -impl W {} #[doc = "Read/write access to BASE0 register. You can [`read`](crate::generic::Reg::read) this register and get [`interp1_base0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp1_base0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] diff --git a/src/sio/interp1_base1.rs b/src/sio/interp1_base1.rs index 35c0e3e46..363de0225 100644 --- a/src/sio/interp1_base1.rs +++ b/src/sio/interp1_base1.rs @@ -2,17 +2,25 @@ pub type R = crate::R; #[doc = "Register `INTERP1_BASE1` writer"] pub type W = crate::W; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) +#[doc = "Field `INTERP1_BASE1` reader - "] +pub type INTERP1_BASE1_R = crate::FieldReader; +#[doc = "Field `INTERP1_BASE1` writer - "] +pub type INTERP1_BASE1_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn interp1_base1(&self) -> INTERP1_BASE1_R { + INTERP1_BASE1_R::new(self.bits) } } -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn interp1_base1(&mut self) -> INTERP1_BASE1_W { + INTERP1_BASE1_W::new(self, 0) } } -impl W {} #[doc = "Read/write access to BASE1 register. You can [`read`](crate::generic::Reg::read) this register and get [`interp1_base1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp1_base1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] diff --git a/src/sio/interp1_base2.rs b/src/sio/interp1_base2.rs index 38a7dc662..b3aabce6a 100644 --- a/src/sio/interp1_base2.rs +++ b/src/sio/interp1_base2.rs @@ -2,17 +2,25 @@ pub type R = crate::R; #[doc = "Register `INTERP1_BASE2` writer"] pub type W = crate::W; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) +#[doc = "Field `INTERP1_BASE2` reader - "] +pub type INTERP1_BASE2_R = crate::FieldReader; +#[doc = "Field `INTERP1_BASE2` writer - "] +pub type INTERP1_BASE2_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn interp1_base2(&self) -> INTERP1_BASE2_R { + INTERP1_BASE2_R::new(self.bits) } } -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn interp1_base2(&mut self) -> INTERP1_BASE2_W { + INTERP1_BASE2_W::new(self, 0) } } -impl W {} #[doc = "Read/write access to BASE2 register. You can [`read`](crate::generic::Reg::read) this register and get [`interp1_base2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp1_base2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] diff --git a/src/sio/interp1_base_1and0.rs b/src/sio/interp1_base_1and0.rs index 962e327e2..cebc47526 100644 --- a/src/sio/interp1_base_1and0.rs +++ b/src/sio/interp1_base_1and0.rs @@ -1,19 +1,26 @@ +#[doc = "Register `INTERP1_BASE_1AND0` reader"] +pub type R = crate::R; #[doc = "Register `INTERP1_BASE_1AND0` writer"] pub type W = crate::W; -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - write!(f, "(not readable)") +#[doc = "Field `INTERP1_BASE_1AND0` writer - "] +pub type INTERP1_BASE_1AND0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn interp1_base_1and0(&mut self) -> INTERP1_BASE_1AND0_W { + INTERP1_BASE_1AND0_W::new(self, 0) } } -impl W {} -#[doc = "On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously. - Each half is sign-extended to 32 bits if that lane's SIGNED flag is set. +#[doc = "On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously. Each half is sign-extended to 32 bits if that lane's SIGNED flag is set. -You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp1_base_1and0::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`interp1_base_1and0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp1_base_1and0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTERP1_BASE_1AND0_SPEC; impl crate::RegisterSpec for INTERP1_BASE_1AND0_SPEC { type Ux = u32; } +#[doc = "`read()` method returns [`interp1_base_1and0::R`](R) reader structure"] +impl crate::Readable for INTERP1_BASE_1AND0_SPEC {} #[doc = "`write(|w| ..)` method takes [`interp1_base_1and0::W`](W) writer structure"] impl crate::Writable for INTERP1_BASE_1AND0_SPEC { type Safety = crate::Unsafe; diff --git a/src/sio/interp1_ctrl_lane0.rs b/src/sio/interp1_ctrl_lane0.rs index f43f516e4..3ca15d98f 100644 --- a/src/sio/interp1_ctrl_lane0.rs +++ b/src/sio/interp1_ctrl_lane0.rs @@ -10,23 +10,17 @@ pub type SHIFT_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; pub type MASK_LSB_R = crate::FieldReader; #[doc = "Field `MASK_LSB` writer - The least-significant bit allowed to pass by the mask (inclusive)"] pub type MASK_LSB_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; -#[doc = "Field `MASK_MSB` reader - The most-significant bit allowed to pass by the mask (inclusive) - Setting MSB < LSB may cause chip to turn inside-out"] +#[doc = "Field `MASK_MSB` reader - The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out"] pub type MASK_MSB_R = crate::FieldReader; -#[doc = "Field `MASK_MSB` writer - The most-significant bit allowed to pass by the mask (inclusive) - Setting MSB < LSB may cause chip to turn inside-out"] +#[doc = "Field `MASK_MSB` writer - The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out"] pub type MASK_MSB_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; -#[doc = "Field `SIGNED` reader - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits - before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor."] +#[doc = "Field `SIGNED` reader - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor."] pub type SIGNED_R = crate::BitReader; -#[doc = "Field `SIGNED` writer - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits - before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor."] +#[doc = "Field `SIGNED` writer - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor."] pub type SIGNED_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CROSS_INPUT` reader - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. - Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"] +#[doc = "Field `CROSS_INPUT` reader - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"] pub type CROSS_INPUT_R = crate::BitReader; -#[doc = "Field `CROSS_INPUT` writer - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. - Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"] +#[doc = "Field `CROSS_INPUT` writer - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"] pub type CROSS_INPUT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `CROSS_RESULT` reader - If 1, feed the opposite lane's result into this lane's accumulator on POP."] pub type CROSS_RESULT_R = crate::BitReader; @@ -36,23 +30,13 @@ pub type CROSS_RESULT_W<'a, REG> = crate::BitWriter<'a, REG>; pub type ADD_RAW_R = crate::BitReader; #[doc = "Field `ADD_RAW` writer - If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result."] pub type ADD_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `FORCE_MSB` reader - ORed into bits 29:28 of the lane result presented to the processor on the bus. - No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence - of pointers into flash or SRAM."] +#[doc = "Field `FORCE_MSB` reader - ORed into bits 29:28 of the lane result presented to the processor on the bus. No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence of pointers into flash or SRAM."] pub type FORCE_MSB_R = crate::FieldReader; -#[doc = "Field `FORCE_MSB` writer - ORed into bits 29:28 of the lane result presented to the processor on the bus. - No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence - of pointers into flash or SRAM."] +#[doc = "Field `FORCE_MSB` writer - ORed into bits 29:28 of the lane result presented to the processor on the bus. No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence of pointers into flash or SRAM."] pub type FORCE_MSB_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; -#[doc = "Field `CLAMP` reader - Only present on INTERP1 on each core. If CLAMP mode is enabled: - - LANE0 result is shifted and masked ACCUM0, clamped by a lower bound of - BASE0 and an upper bound of BASE1. - - Signedness of these comparisons is determined by LANE0_CTRL_SIGNED"] +#[doc = "Field `CLAMP` reader - Only present on INTERP1 on each core. If CLAMP mode is enabled: - LANE0 result is shifted and masked ACCUM0, clamped by a lower bound of BASE0 and an upper bound of BASE1. - Signedness of these comparisons is determined by LANE0_CTRL_SIGNED"] pub type CLAMP_R = crate::BitReader; -#[doc = "Field `CLAMP` writer - Only present on INTERP1 on each core. If CLAMP mode is enabled: - - LANE0 result is shifted and masked ACCUM0, clamped by a lower bound of - BASE0 and an upper bound of BASE1. - - Signedness of these comparisons is determined by LANE0_CTRL_SIGNED"] +#[doc = "Field `CLAMP` writer - Only present on INTERP1 on each core. If CLAMP mode is enabled: - LANE0 result is shifted and masked ACCUM0, clamped by a lower bound of BASE0 and an upper bound of BASE1. - Signedness of these comparisons is determined by LANE0_CTRL_SIGNED"] pub type CLAMP_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `OVERF0` reader - Indicates if any masked-off MSBs in ACCUM0 are set."] pub type OVERF0_R = crate::BitReader; @@ -71,20 +55,17 @@ impl R { pub fn mask_lsb(&self) -> MASK_LSB_R { MASK_LSB_R::new(((self.bits >> 5) & 0x1f) as u8) } - #[doc = "Bits 10:14 - The most-significant bit allowed to pass by the mask (inclusive) - Setting MSB < LSB may cause chip to turn inside-out"] + #[doc = "Bits 10:14 - The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out"] #[inline(always)] pub fn mask_msb(&self) -> MASK_MSB_R { MASK_MSB_R::new(((self.bits >> 10) & 0x1f) as u8) } - #[doc = "Bit 15 - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits - before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor."] + #[doc = "Bit 15 - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor."] #[inline(always)] pub fn signed(&self) -> SIGNED_R { SIGNED_R::new(((self.bits >> 15) & 1) != 0) } - #[doc = "Bit 16 - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. - Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"] + #[doc = "Bit 16 - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"] #[inline(always)] pub fn cross_input(&self) -> CROSS_INPUT_R { CROSS_INPUT_R::new(((self.bits >> 16) & 1) != 0) @@ -99,17 +80,12 @@ impl R { pub fn add_raw(&self) -> ADD_RAW_R { ADD_RAW_R::new(((self.bits >> 18) & 1) != 0) } - #[doc = "Bits 19:20 - ORed into bits 29:28 of the lane result presented to the processor on the bus. - No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence - of pointers into flash or SRAM."] + #[doc = "Bits 19:20 - ORed into bits 29:28 of the lane result presented to the processor on the bus. No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence of pointers into flash or SRAM."] #[inline(always)] pub fn force_msb(&self) -> FORCE_MSB_R { FORCE_MSB_R::new(((self.bits >> 19) & 3) as u8) } - #[doc = "Bit 22 - Only present on INTERP1 on each core. If CLAMP mode is enabled: - - LANE0 result is shifted and masked ACCUM0, clamped by a lower bound of - BASE0 and an upper bound of BASE1. - - Signedness of these comparisons is determined by LANE0_CTRL_SIGNED"] + #[doc = "Bit 22 - Only present on INTERP1 on each core. If CLAMP mode is enabled: - LANE0 result is shifted and masked ACCUM0, clamped by a lower bound of BASE0 and an upper bound of BASE1. - Signedness of these comparisons is determined by LANE0_CTRL_SIGNED"] #[inline(always)] pub fn clamp(&self) -> CLAMP_R { CLAMP_R::new(((self.bits >> 22) & 1) != 0) @@ -143,22 +119,19 @@ impl W { pub fn mask_lsb(&mut self) -> MASK_LSB_W { MASK_LSB_W::new(self, 5) } - #[doc = "Bits 10:14 - The most-significant bit allowed to pass by the mask (inclusive) - Setting MSB < LSB may cause chip to turn inside-out"] + #[doc = "Bits 10:14 - The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out"] #[inline(always)] #[must_use] pub fn mask_msb(&mut self) -> MASK_MSB_W { MASK_MSB_W::new(self, 10) } - #[doc = "Bit 15 - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits - before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor."] + #[doc = "Bit 15 - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor."] #[inline(always)] #[must_use] pub fn signed(&mut self) -> SIGNED_W { SIGNED_W::new(self, 15) } - #[doc = "Bit 16 - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. - Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"] + #[doc = "Bit 16 - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"] #[inline(always)] #[must_use] pub fn cross_input(&mut self) -> CROSS_INPUT_W { @@ -176,18 +149,13 @@ impl W { pub fn add_raw(&mut self) -> ADD_RAW_W { ADD_RAW_W::new(self, 18) } - #[doc = "Bits 19:20 - ORed into bits 29:28 of the lane result presented to the processor on the bus. - No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence - of pointers into flash or SRAM."] + #[doc = "Bits 19:20 - ORed into bits 29:28 of the lane result presented to the processor on the bus. No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence of pointers into flash or SRAM."] #[inline(always)] #[must_use] pub fn force_msb(&mut self) -> FORCE_MSB_W { FORCE_MSB_W::new(self, 19) } - #[doc = "Bit 22 - Only present on INTERP1 on each core. If CLAMP mode is enabled: - - LANE0 result is shifted and masked ACCUM0, clamped by a lower bound of - BASE0 and an upper bound of BASE1. - - Signedness of these comparisons is determined by LANE0_CTRL_SIGNED"] + #[doc = "Bit 22 - Only present on INTERP1 on each core. If CLAMP mode is enabled: - LANE0 result is shifted and masked ACCUM0, clamped by a lower bound of BASE0 and an upper bound of BASE1. - Signedness of these comparisons is determined by LANE0_CTRL_SIGNED"] #[inline(always)] #[must_use] pub fn clamp(&mut self) -> CLAMP_W { diff --git a/src/sio/interp1_ctrl_lane1.rs b/src/sio/interp1_ctrl_lane1.rs index 288187fb8..529956860 100644 --- a/src/sio/interp1_ctrl_lane1.rs +++ b/src/sio/interp1_ctrl_lane1.rs @@ -10,23 +10,17 @@ pub type SHIFT_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; pub type MASK_LSB_R = crate::FieldReader; #[doc = "Field `MASK_LSB` writer - The least-significant bit allowed to pass by the mask (inclusive)"] pub type MASK_LSB_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; -#[doc = "Field `MASK_MSB` reader - The most-significant bit allowed to pass by the mask (inclusive) - Setting MSB < LSB may cause chip to turn inside-out"] +#[doc = "Field `MASK_MSB` reader - The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out"] pub type MASK_MSB_R = crate::FieldReader; -#[doc = "Field `MASK_MSB` writer - The most-significant bit allowed to pass by the mask (inclusive) - Setting MSB < LSB may cause chip to turn inside-out"] +#[doc = "Field `MASK_MSB` writer - The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out"] pub type MASK_MSB_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; -#[doc = "Field `SIGNED` reader - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits - before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor."] +#[doc = "Field `SIGNED` reader - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor."] pub type SIGNED_R = crate::BitReader; -#[doc = "Field `SIGNED` writer - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits - before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor."] +#[doc = "Field `SIGNED` writer - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor."] pub type SIGNED_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CROSS_INPUT` reader - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. - Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"] +#[doc = "Field `CROSS_INPUT` reader - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"] pub type CROSS_INPUT_R = crate::BitReader; -#[doc = "Field `CROSS_INPUT` writer - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. - Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"] +#[doc = "Field `CROSS_INPUT` writer - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"] pub type CROSS_INPUT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `CROSS_RESULT` reader - If 1, feed the opposite lane's result into this lane's accumulator on POP."] pub type CROSS_RESULT_R = crate::BitReader; @@ -36,13 +30,9 @@ pub type CROSS_RESULT_W<'a, REG> = crate::BitWriter<'a, REG>; pub type ADD_RAW_R = crate::BitReader; #[doc = "Field `ADD_RAW` writer - If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result."] pub type ADD_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `FORCE_MSB` reader - ORed into bits 29:28 of the lane result presented to the processor on the bus. - No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence - of pointers into flash or SRAM."] +#[doc = "Field `FORCE_MSB` reader - ORed into bits 29:28 of the lane result presented to the processor on the bus. No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence of pointers into flash or SRAM."] pub type FORCE_MSB_R = crate::FieldReader; -#[doc = "Field `FORCE_MSB` writer - ORed into bits 29:28 of the lane result presented to the processor on the bus. - No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence - of pointers into flash or SRAM."] +#[doc = "Field `FORCE_MSB` writer - ORed into bits 29:28 of the lane result presented to the processor on the bus. No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence of pointers into flash or SRAM."] pub type FORCE_MSB_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; impl R { #[doc = "Bits 0:4 - Logical right-shift applied to accumulator before masking"] @@ -55,20 +45,17 @@ impl R { pub fn mask_lsb(&self) -> MASK_LSB_R { MASK_LSB_R::new(((self.bits >> 5) & 0x1f) as u8) } - #[doc = "Bits 10:14 - The most-significant bit allowed to pass by the mask (inclusive) - Setting MSB < LSB may cause chip to turn inside-out"] + #[doc = "Bits 10:14 - The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out"] #[inline(always)] pub fn mask_msb(&self) -> MASK_MSB_R { MASK_MSB_R::new(((self.bits >> 10) & 0x1f) as u8) } - #[doc = "Bit 15 - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits - before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor."] + #[doc = "Bit 15 - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor."] #[inline(always)] pub fn signed(&self) -> SIGNED_R { SIGNED_R::new(((self.bits >> 15) & 1) != 0) } - #[doc = "Bit 16 - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. - Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"] + #[doc = "Bit 16 - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"] #[inline(always)] pub fn cross_input(&self) -> CROSS_INPUT_R { CROSS_INPUT_R::new(((self.bits >> 16) & 1) != 0) @@ -83,9 +70,7 @@ impl R { pub fn add_raw(&self) -> ADD_RAW_R { ADD_RAW_R::new(((self.bits >> 18) & 1) != 0) } - #[doc = "Bits 19:20 - ORed into bits 29:28 of the lane result presented to the processor on the bus. - No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence - of pointers into flash or SRAM."] + #[doc = "Bits 19:20 - ORed into bits 29:28 of the lane result presented to the processor on the bus. No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence of pointers into flash or SRAM."] #[inline(always)] pub fn force_msb(&self) -> FORCE_MSB_R { FORCE_MSB_R::new(((self.bits >> 19) & 3) as u8) @@ -104,22 +89,19 @@ impl W { pub fn mask_lsb(&mut self) -> MASK_LSB_W { MASK_LSB_W::new(self, 5) } - #[doc = "Bits 10:14 - The most-significant bit allowed to pass by the mask (inclusive) - Setting MSB < LSB may cause chip to turn inside-out"] + #[doc = "Bits 10:14 - The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out"] #[inline(always)] #[must_use] pub fn mask_msb(&mut self) -> MASK_MSB_W { MASK_MSB_W::new(self, 10) } - #[doc = "Bit 15 - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits - before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor."] + #[doc = "Bit 15 - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor."] #[inline(always)] #[must_use] pub fn signed(&mut self) -> SIGNED_W { SIGNED_W::new(self, 15) } - #[doc = "Bit 16 - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. - Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"] + #[doc = "Bit 16 - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"] #[inline(always)] #[must_use] pub fn cross_input(&mut self) -> CROSS_INPUT_W { @@ -137,9 +119,7 @@ impl W { pub fn add_raw(&mut self) -> ADD_RAW_W { ADD_RAW_W::new(self, 18) } - #[doc = "Bits 19:20 - ORed into bits 29:28 of the lane result presented to the processor on the bus. - No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence - of pointers into flash or SRAM."] + #[doc = "Bits 19:20 - ORed into bits 29:28 of the lane result presented to the processor on the bus. No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence of pointers into flash or SRAM."] #[inline(always)] #[must_use] pub fn force_msb(&mut self) -> FORCE_MSB_W { diff --git a/src/sio/interp1_peek_full.rs b/src/sio/interp1_peek_full.rs index 715edb49a..0ce10d79d 100644 --- a/src/sio/interp1_peek_full.rs +++ b/src/sio/interp1_peek_full.rs @@ -1,24 +1,32 @@ #[doc = "Register `INTERP1_PEEK_FULL` reader"] pub type R = crate::R; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) - } -} -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +#[doc = "Register `INTERP1_PEEK_FULL` writer"] +pub type W = crate::W; +#[doc = "Field `INTERP1_PEEK_FULL` reader - "] +pub type INTERP1_PEEK_FULL_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn interp1_peek_full(&self) -> INTERP1_PEEK_FULL_R { + INTERP1_PEEK_FULL_R::new(self.bits) } } +impl W {} #[doc = "Read FULL result, without altering any internal state (PEEK). -You can [`read`](crate::generic::Reg::read) this register and get [`interp1_peek_full::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`interp1_peek_full::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp1_peek_full::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTERP1_PEEK_FULL_SPEC; impl crate::RegisterSpec for INTERP1_PEEK_FULL_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`interp1_peek_full::R`](R) reader structure"] impl crate::Readable for INTERP1_PEEK_FULL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`interp1_peek_full::W`](W) writer structure"] +impl crate::Writable for INTERP1_PEEK_FULL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets INTERP1_PEEK_FULL to value 0"] impl crate::Resettable for INTERP1_PEEK_FULL_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/sio/interp1_peek_lane0.rs b/src/sio/interp1_peek_lane0.rs index a1f693a21..29746b468 100644 --- a/src/sio/interp1_peek_lane0.rs +++ b/src/sio/interp1_peek_lane0.rs @@ -1,24 +1,32 @@ #[doc = "Register `INTERP1_PEEK_LANE0` reader"] pub type R = crate::R; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) - } -} -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +#[doc = "Register `INTERP1_PEEK_LANE0` writer"] +pub type W = crate::W; +#[doc = "Field `INTERP1_PEEK_LANE0` reader - "] +pub type INTERP1_PEEK_LANE0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn interp1_peek_lane0(&self) -> INTERP1_PEEK_LANE0_R { + INTERP1_PEEK_LANE0_R::new(self.bits) } } +impl W {} #[doc = "Read LANE0 result, without altering any internal state (PEEK). -You can [`read`](crate::generic::Reg::read) this register and get [`interp1_peek_lane0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`interp1_peek_lane0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp1_peek_lane0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTERP1_PEEK_LANE0_SPEC; impl crate::RegisterSpec for INTERP1_PEEK_LANE0_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`interp1_peek_lane0::R`](R) reader structure"] impl crate::Readable for INTERP1_PEEK_LANE0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`interp1_peek_lane0::W`](W) writer structure"] +impl crate::Writable for INTERP1_PEEK_LANE0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets INTERP1_PEEK_LANE0 to value 0"] impl crate::Resettable for INTERP1_PEEK_LANE0_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/sio/interp1_peek_lane1.rs b/src/sio/interp1_peek_lane1.rs index f026c4e94..8d9388c48 100644 --- a/src/sio/interp1_peek_lane1.rs +++ b/src/sio/interp1_peek_lane1.rs @@ -1,24 +1,32 @@ #[doc = "Register `INTERP1_PEEK_LANE1` reader"] pub type R = crate::R; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) - } -} -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +#[doc = "Register `INTERP1_PEEK_LANE1` writer"] +pub type W = crate::W; +#[doc = "Field `INTERP1_PEEK_LANE1` reader - "] +pub type INTERP1_PEEK_LANE1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn interp1_peek_lane1(&self) -> INTERP1_PEEK_LANE1_R { + INTERP1_PEEK_LANE1_R::new(self.bits) } } +impl W {} #[doc = "Read LANE1 result, without altering any internal state (PEEK). -You can [`read`](crate::generic::Reg::read) this register and get [`interp1_peek_lane1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`interp1_peek_lane1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp1_peek_lane1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTERP1_PEEK_LANE1_SPEC; impl crate::RegisterSpec for INTERP1_PEEK_LANE1_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`interp1_peek_lane1::R`](R) reader structure"] impl crate::Readable for INTERP1_PEEK_LANE1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`interp1_peek_lane1::W`](W) writer structure"] +impl crate::Writable for INTERP1_PEEK_LANE1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets INTERP1_PEEK_LANE1 to value 0"] impl crate::Resettable for INTERP1_PEEK_LANE1_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/sio/interp1_pop_full.rs b/src/sio/interp1_pop_full.rs index 9dd9ddc99..5163cb16a 100644 --- a/src/sio/interp1_pop_full.rs +++ b/src/sio/interp1_pop_full.rs @@ -1,24 +1,32 @@ #[doc = "Register `INTERP1_POP_FULL` reader"] pub type R = crate::R; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) - } -} -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +#[doc = "Register `INTERP1_POP_FULL` writer"] +pub type W = crate::W; +#[doc = "Field `INTERP1_POP_FULL` reader - "] +pub type INTERP1_POP_FULL_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn interp1_pop_full(&self) -> INTERP1_POP_FULL_R { + INTERP1_POP_FULL_R::new(self.bits) } } +impl W {} #[doc = "Read FULL result, and simultaneously write lane results to both accumulators (POP). -You can [`read`](crate::generic::Reg::read) this register and get [`interp1_pop_full::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`interp1_pop_full::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp1_pop_full::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTERP1_POP_FULL_SPEC; impl crate::RegisterSpec for INTERP1_POP_FULL_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`interp1_pop_full::R`](R) reader structure"] impl crate::Readable for INTERP1_POP_FULL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`interp1_pop_full::W`](W) writer structure"] +impl crate::Writable for INTERP1_POP_FULL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets INTERP1_POP_FULL to value 0"] impl crate::Resettable for INTERP1_POP_FULL_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/sio/interp1_pop_lane0.rs b/src/sio/interp1_pop_lane0.rs index c02444534..0a984334f 100644 --- a/src/sio/interp1_pop_lane0.rs +++ b/src/sio/interp1_pop_lane0.rs @@ -1,24 +1,32 @@ #[doc = "Register `INTERP1_POP_LANE0` reader"] pub type R = crate::R; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) - } -} -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +#[doc = "Register `INTERP1_POP_LANE0` writer"] +pub type W = crate::W; +#[doc = "Field `INTERP1_POP_LANE0` reader - "] +pub type INTERP1_POP_LANE0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn interp1_pop_lane0(&self) -> INTERP1_POP_LANE0_R { + INTERP1_POP_LANE0_R::new(self.bits) } } +impl W {} #[doc = "Read LANE0 result, and simultaneously write lane results to both accumulators (POP). -You can [`read`](crate::generic::Reg::read) this register and get [`interp1_pop_lane0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`interp1_pop_lane0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp1_pop_lane0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTERP1_POP_LANE0_SPEC; impl crate::RegisterSpec for INTERP1_POP_LANE0_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`interp1_pop_lane0::R`](R) reader structure"] impl crate::Readable for INTERP1_POP_LANE0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`interp1_pop_lane0::W`](W) writer structure"] +impl crate::Writable for INTERP1_POP_LANE0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets INTERP1_POP_LANE0 to value 0"] impl crate::Resettable for INTERP1_POP_LANE0_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/sio/interp1_pop_lane1.rs b/src/sio/interp1_pop_lane1.rs index 4a174b396..9246d0414 100644 --- a/src/sio/interp1_pop_lane1.rs +++ b/src/sio/interp1_pop_lane1.rs @@ -1,24 +1,32 @@ #[doc = "Register `INTERP1_POP_LANE1` reader"] pub type R = crate::R; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) - } -} -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +#[doc = "Register `INTERP1_POP_LANE1` writer"] +pub type W = crate::W; +#[doc = "Field `INTERP1_POP_LANE1` reader - "] +pub type INTERP1_POP_LANE1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn interp1_pop_lane1(&self) -> INTERP1_POP_LANE1_R { + INTERP1_POP_LANE1_R::new(self.bits) } } +impl W {} #[doc = "Read LANE1 result, and simultaneously write lane results to both accumulators (POP). -You can [`read`](crate::generic::Reg::read) this register and get [`interp1_pop_lane1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`interp1_pop_lane1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp1_pop_lane1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTERP1_POP_LANE1_SPEC; impl crate::RegisterSpec for INTERP1_POP_LANE1_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`interp1_pop_lane1::R`](R) reader structure"] impl crate::Readable for INTERP1_POP_LANE1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`interp1_pop_lane1::W`](W) writer structure"] +impl crate::Writable for INTERP1_POP_LANE1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets INTERP1_POP_LANE1 to value 0"] impl crate::Resettable for INTERP1_POP_LANE1_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/sio/spinlock.rs b/src/sio/spinlock.rs index f1d37fb24..3b2fbdeda 100644 --- a/src/sio/spinlock.rs +++ b/src/sio/spinlock.rs @@ -2,24 +2,28 @@ pub type R = crate::R; #[doc = "Register `SPINLOCK%s` writer"] pub type W = crate::W; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) +#[doc = "Field `SPINLOCK0` reader - + +The field is **modified** in some way after a read operation."] +pub type SPINLOCK0_R = crate::FieldReader; +#[doc = "Field `SPINLOCK0` writer - "] +pub type SPINLOCK0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn spinlock0(&self) -> SPINLOCK0_R { + SPINLOCK0_R::new(self.bits) } } -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn spinlock0(&mut self) -> SPINLOCK0_W { + SPINLOCK0_W::new(self, 0) } } -impl W {} -#[doc = "Reading from a spinlock address will: - - Return 0 if lock is already locked - - Otherwise return nonzero, and simultaneously claim the lock - - Writing (any value) releases the lock. - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. - The value returned on success is 0x1 << lock number. +#[doc = "Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. You can [`read`](crate::generic::Reg::read) this register and get [`spinlock::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spinlock::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SPINLOCK_SPEC; diff --git a/src/sio/spinlock_st.rs b/src/sio/spinlock_st.rs index da83deab1..b1ce38e1c 100644 --- a/src/sio/spinlock_st.rs +++ b/src/sio/spinlock_st.rs @@ -1,26 +1,32 @@ #[doc = "Register `SPINLOCK_ST` reader"] pub type R = crate::R; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) +#[doc = "Register `SPINLOCK_ST` writer"] +pub type W = crate::W; +#[doc = "Field `SPINLOCK_ST` reader - "] +pub type SPINLOCK_ST_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn spinlock_st(&self) -> SPINLOCK_ST_R { + SPINLOCK_ST_R::new(self.bits) } } -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -#[doc = "Spinlock state - A bitmap containing the state of all 32 spinlocks (1=locked). - Mainly intended for debugging. +impl W {} +#[doc = "Spinlock state A bitmap containing the state of all 32 spinlocks (1=locked). Mainly intended for debugging. -You can [`read`](crate::generic::Reg::read) this register and get [`spinlock_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`spinlock_st::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spinlock_st::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SPINLOCK_ST_SPEC; impl crate::RegisterSpec for SPINLOCK_ST_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`spinlock_st::R`](R) reader structure"] impl crate::Readable for SPINLOCK_ST_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spinlock_st::W`](W) writer structure"] +impl crate::Writable for SPINLOCK_ST_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets SPINLOCK_ST to value 0"] impl crate::Resettable for SPINLOCK_ST_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/spi0.rs b/src/spi0.rs index 50c0c5629..c6a1cd0fd 100644 --- a/src/spi0.rs +++ b/src/spi0.rs @@ -140,9 +140,9 @@ module"] pub type SSPDR = crate::Reg; #[doc = "Data register, SSPDR on page 3-6"] pub mod sspdr; -#[doc = "SSPSR (r) register accessor: Status register, SSPSR on page 3-7 +#[doc = "SSPSR (rw) register accessor: Status register, SSPSR on page 3-7 -You can [`read`](crate::generic::Reg::read) this register and get [`sspsr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`sspsr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sspsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@sspsr`] module"] @@ -167,18 +167,18 @@ module"] pub type SSPIMSC = crate::Reg; #[doc = "Interrupt mask set or clear register, SSPIMSC on page 3-9"] pub mod sspimsc; -#[doc = "SSPRIS (r) register accessor: Raw interrupt status register, SSPRIS on page 3-10 +#[doc = "SSPRIS (rw) register accessor: Raw interrupt status register, SSPRIS on page 3-10 -You can [`read`](crate::generic::Reg::read) this register and get [`sspris::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`sspris::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sspris::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@sspris`] module"] pub type SSPRIS = crate::Reg; #[doc = "Raw interrupt status register, SSPRIS on page 3-10"] pub mod sspris; -#[doc = "SSPMIS (r) register accessor: Masked interrupt status register, SSPMIS on page 3-11 +#[doc = "SSPMIS (rw) register accessor: Masked interrupt status register, SSPMIS on page 3-11 -You can [`read`](crate::generic::Reg::read) this register and get [`sspmis::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`sspmis::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sspmis::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@sspmis`] module"] @@ -203,72 +203,72 @@ module"] pub type SSPDMACR = crate::Reg; #[doc = "DMA control register, SSPDMACR on page 3-12"] pub mod sspdmacr; -#[doc = "SSPPERIPHID0 (r) register accessor: Peripheral identification registers, SSPPeriphID0-3 on page 3-13 +#[doc = "SSPPERIPHID0 (rw) register accessor: Peripheral identification registers, SSPPeriphID0-3 on page 3-13 -You can [`read`](crate::generic::Reg::read) this register and get [`sspperiphid0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`sspperiphid0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sspperiphid0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@sspperiphid0`] module"] pub type SSPPERIPHID0 = crate::Reg; #[doc = "Peripheral identification registers, SSPPeriphID0-3 on page 3-13"] pub mod sspperiphid0; -#[doc = "SSPPERIPHID1 (r) register accessor: Peripheral identification registers, SSPPeriphID0-3 on page 3-13 +#[doc = "SSPPERIPHID1 (rw) register accessor: Peripheral identification registers, SSPPeriphID0-3 on page 3-13 -You can [`read`](crate::generic::Reg::read) this register and get [`sspperiphid1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`sspperiphid1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sspperiphid1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@sspperiphid1`] module"] pub type SSPPERIPHID1 = crate::Reg; #[doc = "Peripheral identification registers, SSPPeriphID0-3 on page 3-13"] pub mod sspperiphid1; -#[doc = "SSPPERIPHID2 (r) register accessor: Peripheral identification registers, SSPPeriphID0-3 on page 3-13 +#[doc = "SSPPERIPHID2 (rw) register accessor: Peripheral identification registers, SSPPeriphID0-3 on page 3-13 -You can [`read`](crate::generic::Reg::read) this register and get [`sspperiphid2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`sspperiphid2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sspperiphid2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@sspperiphid2`] module"] pub type SSPPERIPHID2 = crate::Reg; #[doc = "Peripheral identification registers, SSPPeriphID0-3 on page 3-13"] pub mod sspperiphid2; -#[doc = "SSPPERIPHID3 (r) register accessor: Peripheral identification registers, SSPPeriphID0-3 on page 3-13 +#[doc = "SSPPERIPHID3 (rw) register accessor: Peripheral identification registers, SSPPeriphID0-3 on page 3-13 -You can [`read`](crate::generic::Reg::read) this register and get [`sspperiphid3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`sspperiphid3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sspperiphid3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@sspperiphid3`] module"] pub type SSPPERIPHID3 = crate::Reg; #[doc = "Peripheral identification registers, SSPPeriphID0-3 on page 3-13"] pub mod sspperiphid3; -#[doc = "SSPPCELLID0 (r) register accessor: PrimeCell identification registers, SSPPCellID0-3 on page 3-16 +#[doc = "SSPPCELLID0 (rw) register accessor: PrimeCell identification registers, SSPPCellID0-3 on page 3-16 -You can [`read`](crate::generic::Reg::read) this register and get [`ssppcellid0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`ssppcellid0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssppcellid0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@ssppcellid0`] module"] pub type SSPPCELLID0 = crate::Reg; #[doc = "PrimeCell identification registers, SSPPCellID0-3 on page 3-16"] pub mod ssppcellid0; -#[doc = "SSPPCELLID1 (r) register accessor: PrimeCell identification registers, SSPPCellID0-3 on page 3-16 +#[doc = "SSPPCELLID1 (rw) register accessor: PrimeCell identification registers, SSPPCellID0-3 on page 3-16 -You can [`read`](crate::generic::Reg::read) this register and get [`ssppcellid1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`ssppcellid1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssppcellid1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@ssppcellid1`] module"] pub type SSPPCELLID1 = crate::Reg; #[doc = "PrimeCell identification registers, SSPPCellID0-3 on page 3-16"] pub mod ssppcellid1; -#[doc = "SSPPCELLID2 (r) register accessor: PrimeCell identification registers, SSPPCellID0-3 on page 3-16 +#[doc = "SSPPCELLID2 (rw) register accessor: PrimeCell identification registers, SSPPCellID0-3 on page 3-16 -You can [`read`](crate::generic::Reg::read) this register and get [`ssppcellid2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`ssppcellid2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssppcellid2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@ssppcellid2`] module"] pub type SSPPCELLID2 = crate::Reg; #[doc = "PrimeCell identification registers, SSPPCellID0-3 on page 3-16"] pub mod ssppcellid2; -#[doc = "SSPPCELLID3 (r) register accessor: PrimeCell identification registers, SSPPCellID0-3 on page 3-16 +#[doc = "SSPPCELLID3 (rw) register accessor: PrimeCell identification registers, SSPPCellID0-3 on page 3-16 -You can [`read`](crate::generic::Reg::read) this register and get [`ssppcellid3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`ssppcellid3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssppcellid3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@ssppcellid3`] module"] diff --git a/src/spi0/sspdr.rs b/src/spi0/sspdr.rs index c438c31c6..5fd937983 100644 --- a/src/spi0/sspdr.rs +++ b/src/spi0/sspdr.rs @@ -2,7 +2,9 @@ pub type R = crate::R; #[doc = "Register `SSPDR` writer"] pub type W = crate::W; -#[doc = "Field `DATA` reader - Transmit/Receive FIFO: Read Receive FIFO. Write Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] +#[doc = "Field `DATA` reader - Transmit/Receive FIFO: Read Receive FIFO. Write Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies. + +The field is **modified** in some way after a read operation."] pub type DATA_R = crate::FieldReader; #[doc = "Field `DATA` writer - Transmit/Receive FIFO: Read Receive FIFO. Write Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] pub type DATA_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; diff --git a/src/spi0/sspmis.rs b/src/spi0/sspmis.rs index 1329ba084..64c68e6d7 100644 --- a/src/spi0/sspmis.rs +++ b/src/spi0/sspmis.rs @@ -1,5 +1,7 @@ #[doc = "Register `SSPMIS` reader"] pub type R = crate::R; +#[doc = "Register `SSPMIS` writer"] +pub type W = crate::W; #[doc = "Field `RORMIS` reader - Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt"] pub type RORMIS_R = crate::BitReader; #[doc = "Field `RTMIS` reader - Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt"] @@ -30,15 +32,22 @@ impl R { TXMIS_R::new(((self.bits >> 3) & 1) != 0) } } +impl W {} #[doc = "Masked interrupt status register, SSPMIS on page 3-11 -You can [`read`](crate::generic::Reg::read) this register and get [`sspmis::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`sspmis::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sspmis::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SSPMIS_SPEC; impl crate::RegisterSpec for SSPMIS_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`sspmis::R`](R) reader structure"] impl crate::Readable for SSPMIS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sspmis::W`](W) writer structure"] +impl crate::Writable for SSPMIS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets SSPMIS to value 0"] impl crate::Resettable for SSPMIS_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/spi0/ssppcellid0.rs b/src/spi0/ssppcellid0.rs index b8e8f7aac..88d7aaf35 100644 --- a/src/spi0/ssppcellid0.rs +++ b/src/spi0/ssppcellid0.rs @@ -1,5 +1,7 @@ #[doc = "Register `SSPPCELLID0` reader"] pub type R = crate::R; +#[doc = "Register `SSPPCELLID0` writer"] +pub type W = crate::W; #[doc = "Field `SSPPCELLID0` reader - These bits read back as 0x0D"] pub type SSPPCELLID0_R = crate::FieldReader; impl R { @@ -9,15 +11,22 @@ impl R { SSPPCELLID0_R::new((self.bits & 0xff) as u8) } } +impl W {} #[doc = "PrimeCell identification registers, SSPPCellID0-3 on page 3-16 -You can [`read`](crate::generic::Reg::read) this register and get [`ssppcellid0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`ssppcellid0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssppcellid0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SSPPCELLID0_SPEC; impl crate::RegisterSpec for SSPPCELLID0_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`ssppcellid0::R`](R) reader structure"] impl crate::Readable for SSPPCELLID0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssppcellid0::W`](W) writer structure"] +impl crate::Writable for SSPPCELLID0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets SSPPCELLID0 to value 0x0d"] impl crate::Resettable for SSPPCELLID0_SPEC { const RESET_VALUE: u32 = 0x0d; diff --git a/src/spi0/ssppcellid1.rs b/src/spi0/ssppcellid1.rs index 7510668af..e5fee6a64 100644 --- a/src/spi0/ssppcellid1.rs +++ b/src/spi0/ssppcellid1.rs @@ -1,5 +1,7 @@ #[doc = "Register `SSPPCELLID1` reader"] pub type R = crate::R; +#[doc = "Register `SSPPCELLID1` writer"] +pub type W = crate::W; #[doc = "Field `SSPPCELLID1` reader - These bits read back as 0xF0"] pub type SSPPCELLID1_R = crate::FieldReader; impl R { @@ -9,15 +11,22 @@ impl R { SSPPCELLID1_R::new((self.bits & 0xff) as u8) } } +impl W {} #[doc = "PrimeCell identification registers, SSPPCellID0-3 on page 3-16 -You can [`read`](crate::generic::Reg::read) this register and get [`ssppcellid1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`ssppcellid1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssppcellid1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SSPPCELLID1_SPEC; impl crate::RegisterSpec for SSPPCELLID1_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`ssppcellid1::R`](R) reader structure"] impl crate::Readable for SSPPCELLID1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssppcellid1::W`](W) writer structure"] +impl crate::Writable for SSPPCELLID1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets SSPPCELLID1 to value 0xf0"] impl crate::Resettable for SSPPCELLID1_SPEC { const RESET_VALUE: u32 = 0xf0; diff --git a/src/spi0/ssppcellid2.rs b/src/spi0/ssppcellid2.rs index 8e2e677ee..965c69883 100644 --- a/src/spi0/ssppcellid2.rs +++ b/src/spi0/ssppcellid2.rs @@ -1,5 +1,7 @@ #[doc = "Register `SSPPCELLID2` reader"] pub type R = crate::R; +#[doc = "Register `SSPPCELLID2` writer"] +pub type W = crate::W; #[doc = "Field `SSPPCELLID2` reader - These bits read back as 0x05"] pub type SSPPCELLID2_R = crate::FieldReader; impl R { @@ -9,15 +11,22 @@ impl R { SSPPCELLID2_R::new((self.bits & 0xff) as u8) } } +impl W {} #[doc = "PrimeCell identification registers, SSPPCellID0-3 on page 3-16 -You can [`read`](crate::generic::Reg::read) this register and get [`ssppcellid2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`ssppcellid2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssppcellid2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SSPPCELLID2_SPEC; impl crate::RegisterSpec for SSPPCELLID2_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`ssppcellid2::R`](R) reader structure"] impl crate::Readable for SSPPCELLID2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssppcellid2::W`](W) writer structure"] +impl crate::Writable for SSPPCELLID2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets SSPPCELLID2 to value 0x05"] impl crate::Resettable for SSPPCELLID2_SPEC { const RESET_VALUE: u32 = 0x05; diff --git a/src/spi0/ssppcellid3.rs b/src/spi0/ssppcellid3.rs index d4bf3d482..21cca076c 100644 --- a/src/spi0/ssppcellid3.rs +++ b/src/spi0/ssppcellid3.rs @@ -1,5 +1,7 @@ #[doc = "Register `SSPPCELLID3` reader"] pub type R = crate::R; +#[doc = "Register `SSPPCELLID3` writer"] +pub type W = crate::W; #[doc = "Field `SSPPCELLID3` reader - These bits read back as 0xB1"] pub type SSPPCELLID3_R = crate::FieldReader; impl R { @@ -9,15 +11,22 @@ impl R { SSPPCELLID3_R::new((self.bits & 0xff) as u8) } } +impl W {} #[doc = "PrimeCell identification registers, SSPPCellID0-3 on page 3-16 -You can [`read`](crate::generic::Reg::read) this register and get [`ssppcellid3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`ssppcellid3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssppcellid3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SSPPCELLID3_SPEC; impl crate::RegisterSpec for SSPPCELLID3_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`ssppcellid3::R`](R) reader structure"] impl crate::Readable for SSPPCELLID3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssppcellid3::W`](W) writer structure"] +impl crate::Writable for SSPPCELLID3_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets SSPPCELLID3 to value 0xb1"] impl crate::Resettable for SSPPCELLID3_SPEC { const RESET_VALUE: u32 = 0xb1; diff --git a/src/spi0/sspperiphid0.rs b/src/spi0/sspperiphid0.rs index 42cf2dd49..902157e8f 100644 --- a/src/spi0/sspperiphid0.rs +++ b/src/spi0/sspperiphid0.rs @@ -1,5 +1,7 @@ #[doc = "Register `SSPPERIPHID0` reader"] pub type R = crate::R; +#[doc = "Register `SSPPERIPHID0` writer"] +pub type W = crate::W; #[doc = "Field `PARTNUMBER0` reader - These bits read back as 0x22"] pub type PARTNUMBER0_R = crate::FieldReader; impl R { @@ -9,15 +11,22 @@ impl R { PARTNUMBER0_R::new((self.bits & 0xff) as u8) } } +impl W {} #[doc = "Peripheral identification registers, SSPPeriphID0-3 on page 3-13 -You can [`read`](crate::generic::Reg::read) this register and get [`sspperiphid0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`sspperiphid0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sspperiphid0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SSPPERIPHID0_SPEC; impl crate::RegisterSpec for SSPPERIPHID0_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`sspperiphid0::R`](R) reader structure"] impl crate::Readable for SSPPERIPHID0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sspperiphid0::W`](W) writer structure"] +impl crate::Writable for SSPPERIPHID0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets SSPPERIPHID0 to value 0x22"] impl crate::Resettable for SSPPERIPHID0_SPEC { const RESET_VALUE: u32 = 0x22; diff --git a/src/spi0/sspperiphid1.rs b/src/spi0/sspperiphid1.rs index 9495b3aef..c5fca1736 100644 --- a/src/spi0/sspperiphid1.rs +++ b/src/spi0/sspperiphid1.rs @@ -1,5 +1,7 @@ #[doc = "Register `SSPPERIPHID1` reader"] pub type R = crate::R; +#[doc = "Register `SSPPERIPHID1` writer"] +pub type W = crate::W; #[doc = "Field `PARTNUMBER1` reader - These bits read back as 0x0"] pub type PARTNUMBER1_R = crate::FieldReader; #[doc = "Field `DESIGNER0` reader - These bits read back as 0x1"] @@ -16,15 +18,22 @@ impl R { DESIGNER0_R::new(((self.bits >> 4) & 0x0f) as u8) } } +impl W {} #[doc = "Peripheral identification registers, SSPPeriphID0-3 on page 3-13 -You can [`read`](crate::generic::Reg::read) this register and get [`sspperiphid1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`sspperiphid1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sspperiphid1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SSPPERIPHID1_SPEC; impl crate::RegisterSpec for SSPPERIPHID1_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`sspperiphid1::R`](R) reader structure"] impl crate::Readable for SSPPERIPHID1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sspperiphid1::W`](W) writer structure"] +impl crate::Writable for SSPPERIPHID1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets SSPPERIPHID1 to value 0x10"] impl crate::Resettable for SSPPERIPHID1_SPEC { const RESET_VALUE: u32 = 0x10; diff --git a/src/spi0/sspperiphid2.rs b/src/spi0/sspperiphid2.rs index abe13bc7d..84d08d85e 100644 --- a/src/spi0/sspperiphid2.rs +++ b/src/spi0/sspperiphid2.rs @@ -1,5 +1,7 @@ #[doc = "Register `SSPPERIPHID2` reader"] pub type R = crate::R; +#[doc = "Register `SSPPERIPHID2` writer"] +pub type W = crate::W; #[doc = "Field `DESIGNER1` reader - These bits read back as 0x4"] pub type DESIGNER1_R = crate::FieldReader; #[doc = "Field `REVISION` reader - These bits return the peripheral revision"] @@ -16,15 +18,22 @@ impl R { REVISION_R::new(((self.bits >> 4) & 0x0f) as u8) } } +impl W {} #[doc = "Peripheral identification registers, SSPPeriphID0-3 on page 3-13 -You can [`read`](crate::generic::Reg::read) this register and get [`sspperiphid2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`sspperiphid2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sspperiphid2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SSPPERIPHID2_SPEC; impl crate::RegisterSpec for SSPPERIPHID2_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`sspperiphid2::R`](R) reader structure"] impl crate::Readable for SSPPERIPHID2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sspperiphid2::W`](W) writer structure"] +impl crate::Writable for SSPPERIPHID2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets SSPPERIPHID2 to value 0x34"] impl crate::Resettable for SSPPERIPHID2_SPEC { const RESET_VALUE: u32 = 0x34; diff --git a/src/spi0/sspperiphid3.rs b/src/spi0/sspperiphid3.rs index 16e371536..8811641cb 100644 --- a/src/spi0/sspperiphid3.rs +++ b/src/spi0/sspperiphid3.rs @@ -1,5 +1,7 @@ #[doc = "Register `SSPPERIPHID3` reader"] pub type R = crate::R; +#[doc = "Register `SSPPERIPHID3` writer"] +pub type W = crate::W; #[doc = "Field `CONFIGURATION` reader - These bits read back as 0x00"] pub type CONFIGURATION_R = crate::FieldReader; impl R { @@ -9,15 +11,22 @@ impl R { CONFIGURATION_R::new((self.bits & 0xff) as u8) } } +impl W {} #[doc = "Peripheral identification registers, SSPPeriphID0-3 on page 3-13 -You can [`read`](crate::generic::Reg::read) this register and get [`sspperiphid3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`sspperiphid3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sspperiphid3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SSPPERIPHID3_SPEC; impl crate::RegisterSpec for SSPPERIPHID3_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`sspperiphid3::R`](R) reader structure"] impl crate::Readable for SSPPERIPHID3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sspperiphid3::W`](W) writer structure"] +impl crate::Writable for SSPPERIPHID3_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets SSPPERIPHID3 to value 0"] impl crate::Resettable for SSPPERIPHID3_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/spi0/sspris.rs b/src/spi0/sspris.rs index f986c00f2..f6ce1f9bb 100644 --- a/src/spi0/sspris.rs +++ b/src/spi0/sspris.rs @@ -1,5 +1,7 @@ #[doc = "Register `SSPRIS` reader"] pub type R = crate::R; +#[doc = "Register `SSPRIS` writer"] +pub type W = crate::W; #[doc = "Field `RORRIS` reader - Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt"] pub type RORRIS_R = crate::BitReader; #[doc = "Field `RTRIS` reader - Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt"] @@ -30,15 +32,22 @@ impl R { TXRIS_R::new(((self.bits >> 3) & 1) != 0) } } +impl W {} #[doc = "Raw interrupt status register, SSPRIS on page 3-10 -You can [`read`](crate::generic::Reg::read) this register and get [`sspris::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`sspris::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sspris::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SSPRIS_SPEC; impl crate::RegisterSpec for SSPRIS_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`sspris::R`](R) reader structure"] impl crate::Readable for SSPRIS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sspris::W`](W) writer structure"] +impl crate::Writable for SSPRIS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets SSPRIS to value 0x08"] impl crate::Resettable for SSPRIS_SPEC { const RESET_VALUE: u32 = 0x08; diff --git a/src/spi0/sspsr.rs b/src/spi0/sspsr.rs index 145a7eca8..ef330a261 100644 --- a/src/spi0/sspsr.rs +++ b/src/spi0/sspsr.rs @@ -1,5 +1,7 @@ #[doc = "Register `SSPSR` reader"] pub type R = crate::R; +#[doc = "Register `SSPSR` writer"] +pub type W = crate::W; #[doc = "Field `TFE` reader - Transmit FIFO empty, RO: 0 Transmit FIFO is not empty. 1 Transmit FIFO is empty."] pub type TFE_R = crate::BitReader; #[doc = "Field `TNF` reader - Transmit FIFO not full, RO: 0 Transmit FIFO is full. 1 Transmit FIFO is not full."] @@ -37,15 +39,22 @@ impl R { BSY_R::new(((self.bits >> 4) & 1) != 0) } } +impl W {} #[doc = "Status register, SSPSR on page 3-7 -You can [`read`](crate::generic::Reg::read) this register and get [`sspsr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`sspsr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sspsr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SSPSR_SPEC; impl crate::RegisterSpec for SSPSR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`sspsr::R`](R) reader structure"] impl crate::Readable for SSPSR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sspsr::W`](W) writer structure"] +impl crate::Writable for SSPSR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets SSPSR to value 0x03"] impl crate::Resettable for SSPSR_SPEC { const RESET_VALUE: u32 = 0x03; diff --git a/src/xip_ssi.rs b/src/ssi.rs similarity index 78% rename from src/xip_ssi.rs rename to src/ssi.rs index 71ff0a4de..16bc12b55 100644 --- a/src/xip_ssi.rs +++ b/src/ssi.rs @@ -245,27 +245,27 @@ module"] pub type RXFTLR = crate::Reg; #[doc = "RX FIFO threshold level"] pub mod rxftlr; -#[doc = "TXFLR (r) register accessor: TX FIFO level +#[doc = "TXFLR (rw) register accessor: TX FIFO level -You can [`read`](crate::generic::Reg::read) this register and get [`txflr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`txflr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txflr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@txflr`] module"] pub type TXFLR = crate::Reg; #[doc = "TX FIFO level"] pub mod txflr; -#[doc = "RXFLR (r) register accessor: RX FIFO level +#[doc = "RXFLR (rw) register accessor: RX FIFO level -You can [`read`](crate::generic::Reg::read) this register and get [`rxflr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`rxflr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxflr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@rxflr`] module"] pub type RXFLR = crate::Reg; #[doc = "RX FIFO level"] pub mod rxflr; -#[doc = "SR (r) register accessor: Status register +#[doc = "SR (rw) register accessor: Status register -You can [`read`](crate::generic::Reg::read) this register and get [`sr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`sr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@sr`] module"] @@ -281,63 +281,63 @@ module"] pub type IMR = crate::Reg; #[doc = "Interrupt mask"] pub mod imr; -#[doc = "ISR (r) register accessor: Interrupt status +#[doc = "ISR (rw) register accessor: Interrupt status -You can [`read`](crate::generic::Reg::read) this register and get [`isr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`isr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`isr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@isr`] module"] pub type ISR = crate::Reg; #[doc = "Interrupt status"] pub mod isr; -#[doc = "RISR (r) register accessor: Raw interrupt status +#[doc = "RISR (rw) register accessor: Raw interrupt status -You can [`read`](crate::generic::Reg::read) this register and get [`risr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`risr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`risr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@risr`] module"] pub type RISR = crate::Reg; #[doc = "Raw interrupt status"] pub mod risr; -#[doc = "TXOICR (r) register accessor: TX FIFO overflow interrupt clear +#[doc = "TXOICR (rw) register accessor: TX FIFO overflow interrupt clear -You can [`read`](crate::generic::Reg::read) this register and get [`txoicr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`txoicr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txoicr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@txoicr`] module"] pub type TXOICR = crate::Reg; #[doc = "TX FIFO overflow interrupt clear"] pub mod txoicr; -#[doc = "RXOICR (r) register accessor: RX FIFO overflow interrupt clear +#[doc = "RXOICR (rw) register accessor: RX FIFO overflow interrupt clear -You can [`read`](crate::generic::Reg::read) this register and get [`rxoicr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`rxoicr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxoicr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@rxoicr`] module"] pub type RXOICR = crate::Reg; #[doc = "RX FIFO overflow interrupt clear"] pub mod rxoicr; -#[doc = "RXUICR (r) register accessor: RX FIFO underflow interrupt clear +#[doc = "RXUICR (rw) register accessor: RX FIFO underflow interrupt clear -You can [`read`](crate::generic::Reg::read) this register and get [`rxuicr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`rxuicr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxuicr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@rxuicr`] module"] pub type RXUICR = crate::Reg; #[doc = "RX FIFO underflow interrupt clear"] pub mod rxuicr; -#[doc = "MSTICR (r) register accessor: Multi-master interrupt clear +#[doc = "MSTICR (rw) register accessor: Multi-master interrupt clear -You can [`read`](crate::generic::Reg::read) this register and get [`msticr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`msticr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`msticr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@msticr`] module"] pub type MSTICR = crate::Reg; #[doc = "Multi-master interrupt clear"] pub mod msticr; -#[doc = "ICR (r) register accessor: Interrupt clear +#[doc = "ICR (rw) register accessor: Interrupt clear -You can [`read`](crate::generic::Reg::read) this register and get [`icr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`icr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`icr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@icr`] module"] @@ -371,18 +371,18 @@ module"] pub type DMARDLR = crate::Reg; #[doc = "DMA RX data level"] pub mod dmardlr; -#[doc = "IDR (r) register accessor: Identification register +#[doc = "IDR (rw) register accessor: Identification register -You can [`read`](crate::generic::Reg::read) this register and get [`idr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`idr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`idr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@idr`] module"] pub type IDR = crate::Reg; #[doc = "Identification register"] pub mod idr; -#[doc = "SSI_VERSION_ID (r) register accessor: Version ID +#[doc = "SSI_VERSION_ID (rw) register accessor: Version ID -You can [`read`](crate::generic::Reg::read) this register and get [`ssi_version_id::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`ssi_version_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssi_version_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@ssi_version_id`] module"] diff --git a/src/xip_ssi/baudr.rs b/src/ssi/baudr.rs similarity index 100% rename from src/xip_ssi/baudr.rs rename to src/ssi/baudr.rs diff --git a/src/xip_ssi/ctrlr0.rs b/src/ssi/ctrlr0.rs similarity index 94% rename from src/xip_ssi/ctrlr0.rs rename to src/ssi/ctrlr0.rs index 7c6221a3f..5644140c1 100644 --- a/src/xip_ssi/ctrlr0.rs +++ b/src/ssi/ctrlr0.rs @@ -113,17 +113,13 @@ pub type SLV_OE_W<'a, REG> = crate::BitWriter<'a, REG>; pub type SRL_R = crate::BitReader; #[doc = "Field `SRL` writer - Shift register loop (test mode)"] pub type SRL_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `CFS` reader - Control frame size - Value of n -> n+1 clocks per frame."] +#[doc = "Field `CFS` reader - Control frame size Value of n -> n+1 clocks per frame."] pub type CFS_R = crate::FieldReader; -#[doc = "Field `CFS` writer - Control frame size - Value of n -> n+1 clocks per frame."] +#[doc = "Field `CFS` writer - Control frame size Value of n -> n+1 clocks per frame."] pub type CFS_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `DFS_32` reader - Data frame size in 32b transfer mode - Value of n -> n+1 clocks per frame."] +#[doc = "Field `DFS_32` reader - Data frame size in 32b transfer mode Value of n -> n+1 clocks per frame."] pub type DFS_32_R = crate::FieldReader; -#[doc = "Field `DFS_32` writer - Data frame size in 32b transfer mode - Value of n -> n+1 clocks per frame."] +#[doc = "Field `DFS_32` writer - Data frame size in 32b transfer mode Value of n -> n+1 clocks per frame."] pub type DFS_32_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; #[doc = "SPI frame format @@ -239,14 +235,12 @@ impl R { pub fn srl(&self) -> SRL_R { SRL_R::new(((self.bits >> 11) & 1) != 0) } - #[doc = "Bits 12:15 - Control frame size - Value of n -> n+1 clocks per frame."] + #[doc = "Bits 12:15 - Control frame size Value of n -> n+1 clocks per frame."] #[inline(always)] pub fn cfs(&self) -> CFS_R { CFS_R::new(((self.bits >> 12) & 0x0f) as u8) } - #[doc = "Bits 16:20 - Data frame size in 32b transfer mode - Value of n -> n+1 clocks per frame."] + #[doc = "Bits 16:20 - Data frame size in 32b transfer mode Value of n -> n+1 clocks per frame."] #[inline(always)] pub fn dfs_32(&self) -> DFS_32_R { DFS_32_R::new(((self.bits >> 16) & 0x1f) as u8) @@ -305,15 +299,13 @@ impl W { pub fn srl(&mut self) -> SRL_W { SRL_W::new(self, 11) } - #[doc = "Bits 12:15 - Control frame size - Value of n -> n+1 clocks per frame."] + #[doc = "Bits 12:15 - Control frame size Value of n -> n+1 clocks per frame."] #[inline(always)] #[must_use] pub fn cfs(&mut self) -> CFS_W { CFS_W::new(self, 12) } - #[doc = "Bits 16:20 - Data frame size in 32b transfer mode - Value of n -> n+1 clocks per frame."] + #[doc = "Bits 16:20 - Data frame size in 32b transfer mode Value of n -> n+1 clocks per frame."] #[inline(always)] #[must_use] pub fn dfs_32(&mut self) -> DFS_32_W { diff --git a/src/xip_ssi/ctrlr1.rs b/src/ssi/ctrlr1.rs similarity index 100% rename from src/xip_ssi/ctrlr1.rs rename to src/ssi/ctrlr1.rs diff --git a/src/xip_ssi/dmacr.rs b/src/ssi/dmacr.rs similarity index 100% rename from src/xip_ssi/dmacr.rs rename to src/ssi/dmacr.rs diff --git a/src/xip_ssi/dmardlr.rs b/src/ssi/dmardlr.rs similarity index 100% rename from src/xip_ssi/dmardlr.rs rename to src/ssi/dmardlr.rs diff --git a/src/xip_ssi/dmatdlr.rs b/src/ssi/dmatdlr.rs similarity index 100% rename from src/xip_ssi/dmatdlr.rs rename to src/ssi/dmatdlr.rs diff --git a/src/xip_ssi/dr0.rs b/src/ssi/dr0.rs similarity index 100% rename from src/xip_ssi/dr0.rs rename to src/ssi/dr0.rs diff --git a/src/xip_ssi/icr.rs b/src/ssi/icr.rs similarity index 53% rename from src/xip_ssi/icr.rs rename to src/ssi/icr.rs index b800917b5..f897aca62 100644 --- a/src/xip_ssi/icr.rs +++ b/src/ssi/icr.rs @@ -1,5 +1,7 @@ #[doc = "Register `ICR` reader"] pub type R = crate::R; +#[doc = "Register `ICR` writer"] +pub type W = crate::W; #[doc = "Field `ICR` reader - Clear-on-read all active interrupts"] pub type ICR_R = crate::BitReader; impl R { @@ -9,15 +11,22 @@ impl R { ICR_R::new((self.bits & 1) != 0) } } +impl W {} #[doc = "Interrupt clear -You can [`read`](crate::generic::Reg::read) this register and get [`icr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`icr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`icr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ICR_SPEC; impl crate::RegisterSpec for ICR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`icr::R`](R) reader structure"] impl crate::Readable for ICR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`icr::W`](W) writer structure"] +impl crate::Writable for ICR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets ICR to value 0"] impl crate::Resettable for ICR_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/xip_ssi/idr.rs b/src/ssi/idr.rs similarity index 54% rename from src/xip_ssi/idr.rs rename to src/ssi/idr.rs index e7d0c696f..4752abb0e 100644 --- a/src/xip_ssi/idr.rs +++ b/src/ssi/idr.rs @@ -1,5 +1,7 @@ #[doc = "Register `IDR` reader"] pub type R = crate::R; +#[doc = "Register `IDR` writer"] +pub type W = crate::W; #[doc = "Field `IDCODE` reader - Peripheral dentification code"] pub type IDCODE_R = crate::FieldReader; impl R { @@ -9,15 +11,22 @@ impl R { IDCODE_R::new(self.bits) } } +impl W {} #[doc = "Identification register -You can [`read`](crate::generic::Reg::read) this register and get [`idr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`idr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`idr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IDR_SPEC; impl crate::RegisterSpec for IDR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`idr::R`](R) reader structure"] impl crate::Readable for IDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`idr::W`](W) writer structure"] +impl crate::Writable for IDR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets IDR to value 0x5153_5049"] impl crate::Resettable for IDR_SPEC { const RESET_VALUE: u32 = 0x5153_5049; diff --git a/src/xip_ssi/imr.rs b/src/ssi/imr.rs similarity index 100% rename from src/xip_ssi/imr.rs rename to src/ssi/imr.rs diff --git a/src/xip_ssi/isr.rs b/src/ssi/isr.rs similarity index 77% rename from src/xip_ssi/isr.rs rename to src/ssi/isr.rs index 4583ceb54..c8576d842 100644 --- a/src/xip_ssi/isr.rs +++ b/src/ssi/isr.rs @@ -1,5 +1,7 @@ #[doc = "Register `ISR` reader"] pub type R = crate::R; +#[doc = "Register `ISR` writer"] +pub type W = crate::W; #[doc = "Field `TXEIS` reader - Transmit FIFO empty interrupt status"] pub type TXEIS_R = crate::BitReader; #[doc = "Field `TXOIS` reader - Transmit FIFO overflow interrupt status"] @@ -44,15 +46,22 @@ impl R { MSTIS_R::new(((self.bits >> 5) & 1) != 0) } } +impl W {} #[doc = "Interrupt status -You can [`read`](crate::generic::Reg::read) this register and get [`isr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`isr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`isr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ISR_SPEC; impl crate::RegisterSpec for ISR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`isr::R`](R) reader structure"] impl crate::Readable for ISR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`isr::W`](W) writer structure"] +impl crate::Writable for ISR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets ISR to value 0"] impl crate::Resettable for ISR_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/xip_ssi/msticr.rs b/src/ssi/msticr.rs similarity index 55% rename from src/xip_ssi/msticr.rs rename to src/ssi/msticr.rs index 80f4b4e5e..b7f34d3c6 100644 --- a/src/xip_ssi/msticr.rs +++ b/src/ssi/msticr.rs @@ -1,5 +1,7 @@ #[doc = "Register `MSTICR` reader"] pub type R = crate::R; +#[doc = "Register `MSTICR` writer"] +pub type W = crate::W; #[doc = "Field `MSTICR` reader - Clear-on-read multi-master contention interrupt"] pub type MSTICR_R = crate::BitReader; impl R { @@ -9,15 +11,22 @@ impl R { MSTICR_R::new((self.bits & 1) != 0) } } +impl W {} #[doc = "Multi-master interrupt clear -You can [`read`](crate::generic::Reg::read) this register and get [`msticr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`msticr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`msticr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MSTICR_SPEC; impl crate::RegisterSpec for MSTICR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`msticr::R`](R) reader structure"] impl crate::Readable for MSTICR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`msticr::W`](W) writer structure"] +impl crate::Writable for MSTICR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets MSTICR to value 0"] impl crate::Resettable for MSTICR_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/xip_ssi/mwcr.rs b/src/ssi/mwcr.rs similarity index 100% rename from src/xip_ssi/mwcr.rs rename to src/ssi/mwcr.rs diff --git a/src/xip_ssi/risr.rs b/src/ssi/risr.rs similarity index 77% rename from src/xip_ssi/risr.rs rename to src/ssi/risr.rs index 7a85ad74d..3e7916830 100644 --- a/src/xip_ssi/risr.rs +++ b/src/ssi/risr.rs @@ -1,5 +1,7 @@ #[doc = "Register `RISR` reader"] pub type R = crate::R; +#[doc = "Register `RISR` writer"] +pub type W = crate::W; #[doc = "Field `TXEIR` reader - Transmit FIFO empty raw interrupt status"] pub type TXEIR_R = crate::BitReader; #[doc = "Field `TXOIR` reader - Transmit FIFO overflow raw interrupt status"] @@ -44,15 +46,22 @@ impl R { MSTIR_R::new(((self.bits >> 5) & 1) != 0) } } +impl W {} #[doc = "Raw interrupt status -You can [`read`](crate::generic::Reg::read) this register and get [`risr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`risr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`risr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RISR_SPEC; impl crate::RegisterSpec for RISR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`risr::R`](R) reader structure"] impl crate::Readable for RISR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`risr::W`](W) writer structure"] +impl crate::Writable for RISR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets RISR to value 0"] impl crate::Resettable for RISR_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/xip_ssi/rx_sample_dly.rs b/src/ssi/rx_sample_dly.rs similarity index 100% rename from src/xip_ssi/rx_sample_dly.rs rename to src/ssi/rx_sample_dly.rs diff --git a/src/xip_ssi/rxflr.rs b/src/ssi/rxflr.rs similarity index 52% rename from src/xip_ssi/rxflr.rs rename to src/ssi/rxflr.rs index c35634473..33f30aa3c 100644 --- a/src/xip_ssi/rxflr.rs +++ b/src/ssi/rxflr.rs @@ -1,5 +1,7 @@ #[doc = "Register `RXFLR` reader"] pub type R = crate::R; +#[doc = "Register `RXFLR` writer"] +pub type W = crate::W; #[doc = "Field `RXTFL` reader - Receive FIFO level"] pub type RXTFL_R = crate::FieldReader; impl R { @@ -9,15 +11,22 @@ impl R { RXTFL_R::new((self.bits & 0xff) as u8) } } +impl W {} #[doc = "RX FIFO level -You can [`read`](crate::generic::Reg::read) this register and get [`rxflr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`rxflr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxflr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RXFLR_SPEC; impl crate::RegisterSpec for RXFLR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`rxflr::R`](R) reader structure"] impl crate::Readable for RXFLR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rxflr::W`](W) writer structure"] +impl crate::Writable for RXFLR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets RXFLR to value 0"] impl crate::Resettable for RXFLR_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/xip_ssi/rxftlr.rs b/src/ssi/rxftlr.rs similarity index 100% rename from src/xip_ssi/rxftlr.rs rename to src/ssi/rxftlr.rs diff --git a/src/xip_ssi/rxoicr.rs b/src/ssi/rxoicr.rs similarity index 55% rename from src/xip_ssi/rxoicr.rs rename to src/ssi/rxoicr.rs index dd990abb3..fd30e1f6e 100644 --- a/src/xip_ssi/rxoicr.rs +++ b/src/ssi/rxoicr.rs @@ -1,5 +1,7 @@ #[doc = "Register `RXOICR` reader"] pub type R = crate::R; +#[doc = "Register `RXOICR` writer"] +pub type W = crate::W; #[doc = "Field `RXOICR` reader - Clear-on-read receive FIFO overflow interrupt"] pub type RXOICR_R = crate::BitReader; impl R { @@ -9,15 +11,22 @@ impl R { RXOICR_R::new((self.bits & 1) != 0) } } +impl W {} #[doc = "RX FIFO overflow interrupt clear -You can [`read`](crate::generic::Reg::read) this register and get [`rxoicr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`rxoicr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxoicr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RXOICR_SPEC; impl crate::RegisterSpec for RXOICR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`rxoicr::R`](R) reader structure"] impl crate::Readable for RXOICR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rxoicr::W`](W) writer structure"] +impl crate::Writable for RXOICR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets RXOICR to value 0"] impl crate::Resettable for RXOICR_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/xip_ssi/rxuicr.rs b/src/ssi/rxuicr.rs similarity index 55% rename from src/xip_ssi/rxuicr.rs rename to src/ssi/rxuicr.rs index 6201e3bf5..9b50cafd9 100644 --- a/src/xip_ssi/rxuicr.rs +++ b/src/ssi/rxuicr.rs @@ -1,5 +1,7 @@ #[doc = "Register `RXUICR` reader"] pub type R = crate::R; +#[doc = "Register `RXUICR` writer"] +pub type W = crate::W; #[doc = "Field `RXUICR` reader - Clear-on-read receive FIFO underflow interrupt"] pub type RXUICR_R = crate::BitReader; impl R { @@ -9,15 +11,22 @@ impl R { RXUICR_R::new((self.bits & 1) != 0) } } +impl W {} #[doc = "RX FIFO underflow interrupt clear -You can [`read`](crate::generic::Reg::read) this register and get [`rxuicr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`rxuicr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxuicr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RXUICR_SPEC; impl crate::RegisterSpec for RXUICR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`rxuicr::R`](R) reader structure"] impl crate::Readable for RXUICR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rxuicr::W`](W) writer structure"] +impl crate::Writable for RXUICR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets RXUICR to value 0"] impl crate::Resettable for RXUICR_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/xip_ssi/ser.rs b/src/ssi/ser.rs similarity index 79% rename from src/xip_ssi/ser.rs rename to src/ssi/ser.rs index 39966b034..3b4b62a89 100644 --- a/src/xip_ssi/ser.rs +++ b/src/ssi/ser.rs @@ -2,27 +2,19 @@ pub type R = crate::R; #[doc = "Register `SER` writer"] pub type W = crate::W; -#[doc = "Field `SER` reader - For each bit: - 0 -> slave not selected - 1 -> slave selected"] +#[doc = "Field `SER` reader - For each bit: 0 -> slave not selected 1 -> slave selected"] pub type SER_R = crate::BitReader; -#[doc = "Field `SER` writer - For each bit: - 0 -> slave not selected - 1 -> slave selected"] +#[doc = "Field `SER` writer - For each bit: 0 -> slave not selected 1 -> slave selected"] pub type SER_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { - #[doc = "Bit 0 - For each bit: - 0 -> slave not selected - 1 -> slave selected"] + #[doc = "Bit 0 - For each bit: 0 -> slave not selected 1 -> slave selected"] #[inline(always)] pub fn ser(&self) -> SER_R { SER_R::new((self.bits & 1) != 0) } } impl W { - #[doc = "Bit 0 - For each bit: - 0 -> slave not selected - 1 -> slave selected"] + #[doc = "Bit 0 - For each bit: 0 -> slave not selected 1 -> slave selected"] #[inline(always)] #[must_use] pub fn ser(&mut self) -> SER_W { diff --git a/src/xip_ssi/spi_ctrlr0.rs b/src/ssi/spi_ctrlr0.rs similarity index 100% rename from src/xip_ssi/spi_ctrlr0.rs rename to src/ssi/spi_ctrlr0.rs diff --git a/src/xip_ssi/sr.rs b/src/ssi/sr.rs similarity index 77% rename from src/xip_ssi/sr.rs rename to src/ssi/sr.rs index adf8d46fb..94b3c72d5 100644 --- a/src/xip_ssi/sr.rs +++ b/src/ssi/sr.rs @@ -1,5 +1,7 @@ #[doc = "Register `SR` reader"] pub type R = crate::R; +#[doc = "Register `SR` writer"] +pub type W = crate::W; #[doc = "Field `BUSY` reader - SSI busy flag"] pub type BUSY_R = crate::BitReader; #[doc = "Field `TFNF` reader - Transmit FIFO not full"] @@ -51,15 +53,22 @@ impl R { DCOL_R::new(((self.bits >> 6) & 1) != 0) } } +impl W {} #[doc = "Status register -You can [`read`](crate::generic::Reg::read) this register and get [`sr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`sr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SR_SPEC; impl crate::RegisterSpec for SR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`sr::R`](R) reader structure"] impl crate::Readable for SR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sr::W`](W) writer structure"] +impl crate::Writable for SR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets SR to value 0"] impl crate::Resettable for SR_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/xip_ssi/ssi_version_id.rs b/src/ssi/ssi_version_id.rs similarity index 56% rename from src/xip_ssi/ssi_version_id.rs rename to src/ssi/ssi_version_id.rs index 97b1d5847..88dab60ce 100644 --- a/src/xip_ssi/ssi_version_id.rs +++ b/src/ssi/ssi_version_id.rs @@ -1,5 +1,7 @@ #[doc = "Register `SSI_VERSION_ID` reader"] pub type R = crate::R; +#[doc = "Register `SSI_VERSION_ID` writer"] +pub type W = crate::W; #[doc = "Field `SSI_COMP_VERSION` reader - SNPS component version (format X.YY)"] pub type SSI_COMP_VERSION_R = crate::FieldReader; impl R { @@ -9,15 +11,22 @@ impl R { SSI_COMP_VERSION_R::new(self.bits) } } +impl W {} #[doc = "Version ID -You can [`read`](crate::generic::Reg::read) this register and get [`ssi_version_id::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`ssi_version_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssi_version_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SSI_VERSION_ID_SPEC; impl crate::RegisterSpec for SSI_VERSION_ID_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`ssi_version_id::R`](R) reader structure"] impl crate::Readable for SSI_VERSION_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssi_version_id::W`](W) writer structure"] +impl crate::Writable for SSI_VERSION_ID_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets SSI_VERSION_ID to value 0x3430_312a"] impl crate::Resettable for SSI_VERSION_ID_SPEC { const RESET_VALUE: u32 = 0x3430_312a; diff --git a/src/xip_ssi/ssienr.rs b/src/ssi/ssienr.rs similarity index 100% rename from src/xip_ssi/ssienr.rs rename to src/ssi/ssienr.rs diff --git a/src/xip_ssi/txd_drive_edge.rs b/src/ssi/txd_drive_edge.rs similarity index 100% rename from src/xip_ssi/txd_drive_edge.rs rename to src/ssi/txd_drive_edge.rs diff --git a/src/xip_ssi/txflr.rs b/src/ssi/txflr.rs similarity index 52% rename from src/xip_ssi/txflr.rs rename to src/ssi/txflr.rs index e84cb9dc7..7a8eacf15 100644 --- a/src/xip_ssi/txflr.rs +++ b/src/ssi/txflr.rs @@ -1,5 +1,7 @@ #[doc = "Register `TXFLR` reader"] pub type R = crate::R; +#[doc = "Register `TXFLR` writer"] +pub type W = crate::W; #[doc = "Field `TFTFL` reader - Transmit FIFO level"] pub type TFTFL_R = crate::FieldReader; impl R { @@ -9,15 +11,22 @@ impl R { TFTFL_R::new((self.bits & 0xff) as u8) } } +impl W {} #[doc = "TX FIFO level -You can [`read`](crate::generic::Reg::read) this register and get [`txflr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`txflr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txflr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TXFLR_SPEC; impl crate::RegisterSpec for TXFLR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`txflr::R`](R) reader structure"] impl crate::Readable for TXFLR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`txflr::W`](W) writer structure"] +impl crate::Writable for TXFLR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets TXFLR to value 0"] impl crate::Resettable for TXFLR_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/xip_ssi/txftlr.rs b/src/ssi/txftlr.rs similarity index 100% rename from src/xip_ssi/txftlr.rs rename to src/ssi/txftlr.rs diff --git a/src/xip_ssi/txoicr.rs b/src/ssi/txoicr.rs similarity index 55% rename from src/xip_ssi/txoicr.rs rename to src/ssi/txoicr.rs index f1e4ea1f9..7f4fb3c4d 100644 --- a/src/xip_ssi/txoicr.rs +++ b/src/ssi/txoicr.rs @@ -1,5 +1,7 @@ #[doc = "Register `TXOICR` reader"] pub type R = crate::R; +#[doc = "Register `TXOICR` writer"] +pub type W = crate::W; #[doc = "Field `TXOICR` reader - Clear-on-read transmit FIFO overflow interrupt"] pub type TXOICR_R = crate::BitReader; impl R { @@ -9,15 +11,22 @@ impl R { TXOICR_R::new((self.bits & 1) != 0) } } +impl W {} #[doc = "TX FIFO overflow interrupt clear -You can [`read`](crate::generic::Reg::read) this register and get [`txoicr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`txoicr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txoicr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TXOICR_SPEC; impl crate::RegisterSpec for TXOICR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`txoicr::R`](R) reader structure"] impl crate::Readable for TXOICR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`txoicr::W`](W) writer structure"] +impl crate::Writable for TXOICR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets TXOICR to value 0"] impl crate::Resettable for TXOICR_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/syscfg.rs b/src/syscfg.rs index 06df3a0b0..f0045f80d 100644 --- a/src/syscfg.rs +++ b/src/syscfg.rs @@ -10,14 +10,12 @@ pub struct RegisterBlock { mempowerdown: MEMPOWERDOWN, } impl RegisterBlock { - #[doc = "0x00 - Processor core 0 NMI source mask - Set a bit high to enable NMI from that IRQ"] + #[doc = "0x00 - Processor core 0 NMI source mask"] #[inline(always)] pub const fn proc0_nmi_mask(&self) -> &PROC0_NMI_MASK { &self.proc0_nmi_mask } - #[doc = "0x04 - Processor core 1 NMI source mask - Set a bit high to enable NMI from that IRQ"] + #[doc = "0x04 - Processor core 1 NMI source mask"] #[inline(always)] pub const fn proc1_nmi_mask(&self) -> &PROC1_NMI_MASK { &self.proc1_nmi_mask @@ -27,20 +25,12 @@ impl RegisterBlock { pub const fn proc_config(&self) -> &PROC_CONFIG { &self.proc_config } - #[doc = "0x0c - For each bit, if 1, bypass the input synchronizer between that GPIO - and the GPIO input register in the SIO. The input synchronizers should - generally be unbypassed, to avoid injecting metastabilities into processors. - If you're feeling brave, you can bypass to save two cycles of input - latency. This register applies to GPIO 0...29."] + #[doc = "0x0c - For each bit, if 1, bypass the input synchronizer between that GPIO and the GPIO input register in the SIO. The input synchronizers should generally be unbypassed, to avoid injecting metastabilities into processors. If you're feeling brave, you can bypass to save two cycles of input latency. This register applies to GPIO 0...29."] #[inline(always)] pub const fn proc_in_sync_bypass(&self) -> &PROC_IN_SYNC_BYPASS { &self.proc_in_sync_bypass } - #[doc = "0x10 - For each bit, if 1, bypass the input synchronizer between that GPIO - and the GPIO input register in the SIO. The input synchronizers should - generally be unbypassed, to avoid injecting metastabilities into processors. - If you're feeling brave, you can bypass to save two cycles of input - latency. This register applies to GPIO 30...35 (the QSPI IOs)."] + #[doc = "0x10 - For each bit, if 1, bypass the input synchronizer between that GPIO and the GPIO input register in the SIO. The input synchronizers should generally be unbypassed, to avoid injecting metastabilities into processors. If you're feeling brave, you can bypass to save two cycles of input latency. This register applies to GPIO 30...35 (the QSPI IOs)."] #[inline(always)] pub const fn proc_in_sync_bypass_hi(&self) -> &PROC_IN_SYNC_BYPASS_HI { &self.proc_in_sync_bypass_hi @@ -50,34 +40,29 @@ impl RegisterBlock { pub const fn dbgforce(&self) -> &DBGFORCE { &self.dbgforce } - #[doc = "0x18 - Control power downs to memories. Set high to power down memories. - Use with extreme caution"] + #[doc = "0x18 - Control power downs to memories. Set high to power down memories. Use with extreme caution"] #[inline(always)] pub const fn mempowerdown(&self) -> &MEMPOWERDOWN { &self.mempowerdown } } #[doc = "PROC0_NMI_MASK (rw) register accessor: Processor core 0 NMI source mask - Set a bit high to enable NMI from that IRQ You can [`read`](crate::generic::Reg::read) this register and get [`proc0_nmi_mask::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`proc0_nmi_mask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@proc0_nmi_mask`] module"] pub type PROC0_NMI_MASK = crate::Reg; -#[doc = "Processor core 0 NMI source mask - Set a bit high to enable NMI from that IRQ"] +#[doc = "Processor core 0 NMI source mask"] pub mod proc0_nmi_mask; #[doc = "PROC1_NMI_MASK (rw) register accessor: Processor core 1 NMI source mask - Set a bit high to enable NMI from that IRQ You can [`read`](crate::generic::Reg::read) this register and get [`proc1_nmi_mask::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`proc1_nmi_mask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@proc1_nmi_mask`] module"] pub type PROC1_NMI_MASK = crate::Reg; -#[doc = "Processor core 1 NMI source mask - Set a bit high to enable NMI from that IRQ"] +#[doc = "Processor core 1 NMI source mask"] pub mod proc1_nmi_mask; #[doc = "PROC_CONFIG (rw) register accessor: Configuration for processors @@ -88,39 +73,23 @@ module"] pub type PROC_CONFIG = crate::Reg; #[doc = "Configuration for processors"] pub mod proc_config; -#[doc = "PROC_IN_SYNC_BYPASS (rw) register accessor: For each bit, if 1, bypass the input synchronizer between that GPIO - and the GPIO input register in the SIO. The input synchronizers should - generally be unbypassed, to avoid injecting metastabilities into processors. - If you're feeling brave, you can bypass to save two cycles of input - latency. This register applies to GPIO 0...29. +#[doc = "PROC_IN_SYNC_BYPASS (rw) register accessor: For each bit, if 1, bypass the input synchronizer between that GPIO and the GPIO input register in the SIO. The input synchronizers should generally be unbypassed, to avoid injecting metastabilities into processors. If you're feeling brave, you can bypass to save two cycles of input latency. This register applies to GPIO 0...29. You can [`read`](crate::generic::Reg::read) this register and get [`proc_in_sync_bypass::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`proc_in_sync_bypass::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@proc_in_sync_bypass`] module"] pub type PROC_IN_SYNC_BYPASS = crate::Reg; -#[doc = "For each bit, if 1, bypass the input synchronizer between that GPIO - and the GPIO input register in the SIO. The input synchronizers should - generally be unbypassed, to avoid injecting metastabilities into processors. - If you're feeling brave, you can bypass to save two cycles of input - latency. This register applies to GPIO 0...29."] +#[doc = "For each bit, if 1, bypass the input synchronizer between that GPIO and the GPIO input register in the SIO. The input synchronizers should generally be unbypassed, to avoid injecting metastabilities into processors. If you're feeling brave, you can bypass to save two cycles of input latency. This register applies to GPIO 0...29."] pub mod proc_in_sync_bypass; -#[doc = "PROC_IN_SYNC_BYPASS_HI (rw) register accessor: For each bit, if 1, bypass the input synchronizer between that GPIO - and the GPIO input register in the SIO. The input synchronizers should - generally be unbypassed, to avoid injecting metastabilities into processors. - If you're feeling brave, you can bypass to save two cycles of input - latency. This register applies to GPIO 30...35 (the QSPI IOs). +#[doc = "PROC_IN_SYNC_BYPASS_HI (rw) register accessor: For each bit, if 1, bypass the input synchronizer between that GPIO and the GPIO input register in the SIO. The input synchronizers should generally be unbypassed, to avoid injecting metastabilities into processors. If you're feeling brave, you can bypass to save two cycles of input latency. This register applies to GPIO 30...35 (the QSPI IOs). You can [`read`](crate::generic::Reg::read) this register and get [`proc_in_sync_bypass_hi::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`proc_in_sync_bypass_hi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@proc_in_sync_bypass_hi`] module"] pub type PROC_IN_SYNC_BYPASS_HI = crate::Reg; -#[doc = "For each bit, if 1, bypass the input synchronizer between that GPIO - and the GPIO input register in the SIO. The input synchronizers should - generally be unbypassed, to avoid injecting metastabilities into processors. - If you're feeling brave, you can bypass to save two cycles of input - latency. This register applies to GPIO 30...35 (the QSPI IOs)."] +#[doc = "For each bit, if 1, bypass the input synchronizer between that GPIO and the GPIO input register in the SIO. The input synchronizers should generally be unbypassed, to avoid injecting metastabilities into processors. If you're feeling brave, you can bypass to save two cycles of input latency. This register applies to GPIO 30...35 (the QSPI IOs)."] pub mod proc_in_sync_bypass_hi; #[doc = "DBGFORCE (rw) register accessor: Directly control the SWD debug port of either processor @@ -131,14 +100,12 @@ module"] pub type DBGFORCE = crate::Reg; #[doc = "Directly control the SWD debug port of either processor"] pub mod dbgforce; -#[doc = "MEMPOWERDOWN (rw) register accessor: Control power downs to memories. Set high to power down memories. - Use with extreme caution +#[doc = "MEMPOWERDOWN (rw) register accessor: Control power downs to memories. Set high to power down memories. Use with extreme caution You can [`read`](crate::generic::Reg::read) this register and get [`mempowerdown::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mempowerdown::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@mempowerdown`] module"] pub type MEMPOWERDOWN = crate::Reg; -#[doc = "Control power downs to memories. Set high to power down memories. - Use with extreme caution"] +#[doc = "Control power downs to memories. Set high to power down memories. Use with extreme caution"] pub mod mempowerdown; diff --git a/src/syscfg/mempowerdown.rs b/src/syscfg/mempowerdown.rs index 255cb702f..6afd67e0d 100644 --- a/src/syscfg/mempowerdown.rs +++ b/src/syscfg/mempowerdown.rs @@ -126,8 +126,7 @@ impl W { ROM_W::new(self, 7) } } -#[doc = "Control power downs to memories. Set high to power down memories. - Use with extreme caution +#[doc = "Control power downs to memories. Set high to power down memories. Use with extreme caution You can [`read`](crate::generic::Reg::read) this register and get [`mempowerdown::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mempowerdown::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MEMPOWERDOWN_SPEC; diff --git a/src/syscfg/proc0_nmi_mask.rs b/src/syscfg/proc0_nmi_mask.rs index 76d02c5ae..009f36e59 100644 --- a/src/syscfg/proc0_nmi_mask.rs +++ b/src/syscfg/proc0_nmi_mask.rs @@ -2,19 +2,26 @@ pub type R = crate::R; #[doc = "Register `PROC0_NMI_MASK` writer"] pub type W = crate::W; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) +#[doc = "Field `PROC0_NMI_MASK` reader - Set a bit high to enable NMI from that IRQ"] +pub type PROC0_NMI_MASK_R = crate::FieldReader; +#[doc = "Field `PROC0_NMI_MASK` writer - Set a bit high to enable NMI from that IRQ"] +pub type PROC0_NMI_MASK_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Set a bit high to enable NMI from that IRQ"] + #[inline(always)] + pub fn proc0_nmi_mask(&self) -> PROC0_NMI_MASK_R { + PROC0_NMI_MASK_R::new(self.bits) } } -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +impl W { + #[doc = "Bits 0:31 - Set a bit high to enable NMI from that IRQ"] + #[inline(always)] + #[must_use] + pub fn proc0_nmi_mask(&mut self) -> PROC0_NMI_MASK_W { + PROC0_NMI_MASK_W::new(self, 0) } } -impl W {} #[doc = "Processor core 0 NMI source mask - Set a bit high to enable NMI from that IRQ You can [`read`](crate::generic::Reg::read) this register and get [`proc0_nmi_mask::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`proc0_nmi_mask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PROC0_NMI_MASK_SPEC; diff --git a/src/syscfg/proc1_nmi_mask.rs b/src/syscfg/proc1_nmi_mask.rs index ca0b40bec..f66b94d20 100644 --- a/src/syscfg/proc1_nmi_mask.rs +++ b/src/syscfg/proc1_nmi_mask.rs @@ -2,19 +2,26 @@ pub type R = crate::R; #[doc = "Register `PROC1_NMI_MASK` writer"] pub type W = crate::W; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) +#[doc = "Field `PROC1_NMI_MASK` reader - Set a bit high to enable NMI from that IRQ"] +pub type PROC1_NMI_MASK_R = crate::FieldReader; +#[doc = "Field `PROC1_NMI_MASK` writer - Set a bit high to enable NMI from that IRQ"] +pub type PROC1_NMI_MASK_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Set a bit high to enable NMI from that IRQ"] + #[inline(always)] + pub fn proc1_nmi_mask(&self) -> PROC1_NMI_MASK_R { + PROC1_NMI_MASK_R::new(self.bits) } } -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +impl W { + #[doc = "Bits 0:31 - Set a bit high to enable NMI from that IRQ"] + #[inline(always)] + #[must_use] + pub fn proc1_nmi_mask(&mut self) -> PROC1_NMI_MASK_W { + PROC1_NMI_MASK_W::new(self, 0) } } -impl W {} #[doc = "Processor core 1 NMI source mask - Set a bit high to enable NMI from that IRQ You can [`read`](crate::generic::Reg::read) this register and get [`proc1_nmi_mask::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`proc1_nmi_mask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PROC1_NMI_MASK_SPEC; diff --git a/src/syscfg/proc_config.rs b/src/syscfg/proc_config.rs index 6358aff53..4aa122c0a 100644 --- a/src/syscfg/proc_config.rs +++ b/src/syscfg/proc_config.rs @@ -6,21 +6,13 @@ pub type W = crate::W; pub type PROC0_HALTED_R = crate::BitReader; #[doc = "Field `PROC1_HALTED` reader - Indication that proc1 has halted"] pub type PROC1_HALTED_R = crate::BitReader; -#[doc = "Field `PROC0_DAP_INSTID` reader - Configure proc0 DAP instance ID. - Recommend that this is NOT changed until you require debug access in multi-chip environment - WARNING: do not set to 15 as this is reserved for RescueDP"] +#[doc = "Field `PROC0_DAP_INSTID` reader - Configure proc0 DAP instance ID. Recommend that this is NOT changed until you require debug access in multi-chip environment WARNING: do not set to 15 as this is reserved for RescueDP"] pub type PROC0_DAP_INSTID_R = crate::FieldReader; -#[doc = "Field `PROC0_DAP_INSTID` writer - Configure proc0 DAP instance ID. - Recommend that this is NOT changed until you require debug access in multi-chip environment - WARNING: do not set to 15 as this is reserved for RescueDP"] +#[doc = "Field `PROC0_DAP_INSTID` writer - Configure proc0 DAP instance ID. Recommend that this is NOT changed until you require debug access in multi-chip environment WARNING: do not set to 15 as this is reserved for RescueDP"] pub type PROC0_DAP_INSTID_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `PROC1_DAP_INSTID` reader - Configure proc1 DAP instance ID. - Recommend that this is NOT changed until you require debug access in multi-chip environment - WARNING: do not set to 15 as this is reserved for RescueDP"] +#[doc = "Field `PROC1_DAP_INSTID` reader - Configure proc1 DAP instance ID. Recommend that this is NOT changed until you require debug access in multi-chip environment WARNING: do not set to 15 as this is reserved for RescueDP"] pub type PROC1_DAP_INSTID_R = crate::FieldReader; -#[doc = "Field `PROC1_DAP_INSTID` writer - Configure proc1 DAP instance ID. - Recommend that this is NOT changed until you require debug access in multi-chip environment - WARNING: do not set to 15 as this is reserved for RescueDP"] +#[doc = "Field `PROC1_DAP_INSTID` writer - Configure proc1 DAP instance ID. Recommend that this is NOT changed until you require debug access in multi-chip environment WARNING: do not set to 15 as this is reserved for RescueDP"] pub type PROC1_DAP_INSTID_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; impl R { #[doc = "Bit 0 - Indication that proc0 has halted"] @@ -33,33 +25,25 @@ impl R { pub fn proc1_halted(&self) -> PROC1_HALTED_R { PROC1_HALTED_R::new(((self.bits >> 1) & 1) != 0) } - #[doc = "Bits 24:27 - Configure proc0 DAP instance ID. - Recommend that this is NOT changed until you require debug access in multi-chip environment - WARNING: do not set to 15 as this is reserved for RescueDP"] + #[doc = "Bits 24:27 - Configure proc0 DAP instance ID. Recommend that this is NOT changed until you require debug access in multi-chip environment WARNING: do not set to 15 as this is reserved for RescueDP"] #[inline(always)] pub fn proc0_dap_instid(&self) -> PROC0_DAP_INSTID_R { PROC0_DAP_INSTID_R::new(((self.bits >> 24) & 0x0f) as u8) } - #[doc = "Bits 28:31 - Configure proc1 DAP instance ID. - Recommend that this is NOT changed until you require debug access in multi-chip environment - WARNING: do not set to 15 as this is reserved for RescueDP"] + #[doc = "Bits 28:31 - Configure proc1 DAP instance ID. Recommend that this is NOT changed until you require debug access in multi-chip environment WARNING: do not set to 15 as this is reserved for RescueDP"] #[inline(always)] pub fn proc1_dap_instid(&self) -> PROC1_DAP_INSTID_R { PROC1_DAP_INSTID_R::new(((self.bits >> 28) & 0x0f) as u8) } } impl W { - #[doc = "Bits 24:27 - Configure proc0 DAP instance ID. - Recommend that this is NOT changed until you require debug access in multi-chip environment - WARNING: do not set to 15 as this is reserved for RescueDP"] + #[doc = "Bits 24:27 - Configure proc0 DAP instance ID. Recommend that this is NOT changed until you require debug access in multi-chip environment WARNING: do not set to 15 as this is reserved for RescueDP"] #[inline(always)] #[must_use] pub fn proc0_dap_instid(&mut self) -> PROC0_DAP_INSTID_W { PROC0_DAP_INSTID_W::new(self, 24) } - #[doc = "Bits 28:31 - Configure proc1 DAP instance ID. - Recommend that this is NOT changed until you require debug access in multi-chip environment - WARNING: do not set to 15 as this is reserved for RescueDP"] + #[doc = "Bits 28:31 - Configure proc1 DAP instance ID. Recommend that this is NOT changed until you require debug access in multi-chip environment WARNING: do not set to 15 as this is reserved for RescueDP"] #[inline(always)] #[must_use] pub fn proc1_dap_instid(&mut self) -> PROC1_DAP_INSTID_W { diff --git a/src/syscfg/proc_in_sync_bypass.rs b/src/syscfg/proc_in_sync_bypass.rs index 52db7ddc6..16ce1caa2 100644 --- a/src/syscfg/proc_in_sync_bypass.rs +++ b/src/syscfg/proc_in_sync_bypass.rs @@ -21,11 +21,7 @@ impl W { PROC_IN_SYNC_BYPASS_W::new(self, 0) } } -#[doc = "For each bit, if 1, bypass the input synchronizer between that GPIO - and the GPIO input register in the SIO. The input synchronizers should - generally be unbypassed, to avoid injecting metastabilities into processors. - If you're feeling brave, you can bypass to save two cycles of input - latency. This register applies to GPIO 0...29. +#[doc = "For each bit, if 1, bypass the input synchronizer between that GPIO and the GPIO input register in the SIO. The input synchronizers should generally be unbypassed, to avoid injecting metastabilities into processors. If you're feeling brave, you can bypass to save two cycles of input latency. This register applies to GPIO 0...29. You can [`read`](crate::generic::Reg::read) this register and get [`proc_in_sync_bypass::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`proc_in_sync_bypass::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PROC_IN_SYNC_BYPASS_SPEC; diff --git a/src/syscfg/proc_in_sync_bypass_hi.rs b/src/syscfg/proc_in_sync_bypass_hi.rs index 28e7a8072..05f85b9ed 100644 --- a/src/syscfg/proc_in_sync_bypass_hi.rs +++ b/src/syscfg/proc_in_sync_bypass_hi.rs @@ -23,11 +23,7 @@ impl W { PROC_IN_SYNC_BYPASS_HI_W::new(self, 0) } } -#[doc = "For each bit, if 1, bypass the input synchronizer between that GPIO - and the GPIO input register in the SIO. The input synchronizers should - generally be unbypassed, to avoid injecting metastabilities into processors. - If you're feeling brave, you can bypass to save two cycles of input - latency. This register applies to GPIO 30...35 (the QSPI IOs). +#[doc = "For each bit, if 1, bypass the input synchronizer between that GPIO and the GPIO input register in the SIO. The input synchronizers should generally be unbypassed, to avoid injecting metastabilities into processors. If you're feeling brave, you can bypass to save two cycles of input latency. This register applies to GPIO 30...35 (the QSPI IOs). You can [`read`](crate::generic::Reg::read) this register and get [`proc_in_sync_bypass_hi::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`proc_in_sync_bypass_hi::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PROC_IN_SYNC_BYPASS_HI_SPEC; diff --git a/src/sysinfo.rs b/src/sysinfo.rs index 6396a522d..95b3009a4 100644 --- a/src/sysinfo.rs +++ b/src/sysinfo.rs @@ -3,7 +3,7 @@ pub struct RegisterBlock { chip_id: CHIP_ID, platform: PLATFORM, - _reserved2: [u8; 0x38], + _reserved2: [u8; 0x08], gitref_rp2040: GITREF_RP2040, } impl RegisterBlock { @@ -17,33 +17,33 @@ impl RegisterBlock { pub const fn platform(&self) -> &PLATFORM { &self.platform } - #[doc = "0x40 - Git hash of the chip source. Used to identify chip version."] + #[doc = "0x10 - Git hash of the chip source. Used to identify chip version."] #[inline(always)] pub const fn gitref_rp2040(&self) -> &GITREF_RP2040 { &self.gitref_rp2040 } } -#[doc = "CHIP_ID (r) register accessor: JEDEC JEP-106 compliant chip identifier. +#[doc = "CHIP_ID (rw) register accessor: JEDEC JEP-106 compliant chip identifier. -You can [`read`](crate::generic::Reg::read) this register and get [`chip_id::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`chip_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`chip_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@chip_id`] module"] pub type CHIP_ID = crate::Reg; #[doc = "JEDEC JEP-106 compliant chip identifier."] pub mod chip_id; -#[doc = "PLATFORM (r) register accessor: Platform register. Allows software to know what environment it is running in. +#[doc = "PLATFORM (rw) register accessor: Platform register. Allows software to know what environment it is running in. -You can [`read`](crate::generic::Reg::read) this register and get [`platform::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`platform::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`platform::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@platform`] module"] pub type PLATFORM = crate::Reg; #[doc = "Platform register. Allows software to know what environment it is running in."] pub mod platform; -#[doc = "GITREF_RP2040 (r) register accessor: Git hash of the chip source. Used to identify chip version. +#[doc = "GITREF_RP2040 (rw) register accessor: Git hash of the chip source. Used to identify chip version. -You can [`read`](crate::generic::Reg::read) this register and get [`gitref_rp2040::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`gitref_rp2040::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gitref_rp2040::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@gitref_rp2040`] module"] diff --git a/src/sysinfo/chip_id.rs b/src/sysinfo/chip_id.rs index 8801dc74e..852db3ee5 100644 --- a/src/sysinfo/chip_id.rs +++ b/src/sysinfo/chip_id.rs @@ -1,5 +1,7 @@ #[doc = "Register `CHIP_ID` reader"] pub type R = crate::R; +#[doc = "Register `CHIP_ID` writer"] +pub type W = crate::W; #[doc = "Field `MANUFACTURER` reader - "] pub type MANUFACTURER_R = crate::FieldReader; #[doc = "Field `PART` reader - "] @@ -23,15 +25,22 @@ impl R { REVISION_R::new(((self.bits >> 28) & 0x0f) as u8) } } +impl W {} #[doc = "JEDEC JEP-106 compliant chip identifier. -You can [`read`](crate::generic::Reg::read) this register and get [`chip_id::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`chip_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`chip_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CHIP_ID_SPEC; impl crate::RegisterSpec for CHIP_ID_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`chip_id::R`](R) reader structure"] impl crate::Readable for CHIP_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`chip_id::W`](W) writer structure"] +impl crate::Writable for CHIP_ID_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets CHIP_ID to value 0"] impl crate::Resettable for CHIP_ID_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/sysinfo/gitref_rp2040.rs b/src/sysinfo/gitref_rp2040.rs index 400ea57b5..1af9e95c0 100644 --- a/src/sysinfo/gitref_rp2040.rs +++ b/src/sysinfo/gitref_rp2040.rs @@ -1,24 +1,32 @@ #[doc = "Register `GITREF_RP2040` reader"] pub type R = crate::R; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) - } -} -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +#[doc = "Register `GITREF_RP2040` writer"] +pub type W = crate::W; +#[doc = "Field `GITREF_RP2040` reader - "] +pub type GITREF_RP2040_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn gitref_rp2040(&self) -> GITREF_RP2040_R { + GITREF_RP2040_R::new(self.bits) } } +impl W {} #[doc = "Git hash of the chip source. Used to identify chip version. -You can [`read`](crate::generic::Reg::read) this register and get [`gitref_rp2040::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`gitref_rp2040::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gitref_rp2040::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GITREF_RP2040_SPEC; impl crate::RegisterSpec for GITREF_RP2040_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`gitref_rp2040::R`](R) reader structure"] impl crate::Readable for GITREF_RP2040_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gitref_rp2040::W`](W) writer structure"] +impl crate::Writable for GITREF_RP2040_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets GITREF_RP2040 to value 0"] impl crate::Resettable for GITREF_RP2040_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/sysinfo/platform.rs b/src/sysinfo/platform.rs index 42b7f4f9d..415c7550c 100644 --- a/src/sysinfo/platform.rs +++ b/src/sysinfo/platform.rs @@ -1,5 +1,7 @@ #[doc = "Register `PLATFORM` reader"] pub type R = crate::R; +#[doc = "Register `PLATFORM` writer"] +pub type W = crate::W; #[doc = "Field `FPGA` reader - "] pub type FPGA_R = crate::BitReader; #[doc = "Field `ASIC` reader - "] @@ -16,15 +18,22 @@ impl R { ASIC_R::new(((self.bits >> 1) & 1) != 0) } } +impl W {} #[doc = "Platform register. Allows software to know what environment it is running in. -You can [`read`](crate::generic::Reg::read) this register and get [`platform::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`platform::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`platform::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PLATFORM_SPEC; impl crate::RegisterSpec for PLATFORM_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`platform::R`](R) reader structure"] impl crate::Readable for PLATFORM_SPEC {} +#[doc = "`write(|w| ..)` method takes [`platform::W`](W) writer structure"] +impl crate::Writable for PLATFORM_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets PLATFORM to value 0"] impl crate::Resettable for PLATFORM_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/tbman.rs b/src/tbman.rs index 85ad7fd3e..410392f76 100644 --- a/src/tbman.rs +++ b/src/tbman.rs @@ -10,9 +10,9 @@ impl RegisterBlock { &self.platform } } -#[doc = "PLATFORM (r) register accessor: Indicates the type of platform in use +#[doc = "PLATFORM (rw) register accessor: Indicates the type of platform in use -You can [`read`](crate::generic::Reg::read) this register and get [`platform::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`platform::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`platform::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@platform`] module"] diff --git a/src/tbman/platform.rs b/src/tbman/platform.rs index c0bacd525..ba6015453 100644 --- a/src/tbman/platform.rs +++ b/src/tbman/platform.rs @@ -1,5 +1,7 @@ #[doc = "Register `PLATFORM` reader"] pub type R = crate::R; +#[doc = "Register `PLATFORM` writer"] +pub type W = crate::W; #[doc = "Field `ASIC` reader - Indicates the platform is an ASIC"] pub type ASIC_R = crate::BitReader; #[doc = "Field `FPGA` reader - Indicates the platform is an FPGA"] @@ -16,15 +18,22 @@ impl R { FPGA_R::new(((self.bits >> 1) & 1) != 0) } } +impl W {} #[doc = "Indicates the type of platform in use -You can [`read`](crate::generic::Reg::read) this register and get [`platform::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`platform::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`platform::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PLATFORM_SPEC; impl crate::RegisterSpec for PLATFORM_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`platform::R`](R) reader structure"] impl crate::Readable for PLATFORM_SPEC {} +#[doc = "`write(|w| ..)` method takes [`platform::W`](W) writer structure"] +impl crate::Writable for PLATFORM_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets PLATFORM to value 0x05"] impl crate::Resettable for PLATFORM_SPEC { const RESET_VALUE: u32 = 0x05; diff --git a/src/timer.rs b/src/timer.rs index e61a6f28b..4852e4536 100644 --- a/src/timer.rs +++ b/src/timer.rs @@ -20,20 +20,17 @@ pub struct RegisterBlock { ints: INTS, } impl RegisterBlock { - #[doc = "0x00 - Write to bits 63:32 of time - always write timelw before timehw"] + #[doc = "0x00 - Write to bits 63:32 of time always write timelw before timehw"] #[inline(always)] pub const fn timehw(&self) -> &TIMEHW { &self.timehw } - #[doc = "0x04 - Write to bits 31:0 of time - writes do not get copied to time until timehw is written"] + #[doc = "0x04 - Write to bits 31:0 of time writes do not get copied to time until timehw is written"] #[inline(always)] pub const fn timelw(&self) -> &TIMELW { &self.timelw } - #[doc = "0x08 - Read from bits 63:32 of time - always read timelr before timehr"] + #[doc = "0x08 - Read from bits 63:32 of time always read timelr before timehr"] #[inline(always)] pub const fn timehr(&self) -> &TIMEHR { &self.timehr @@ -43,42 +40,27 @@ impl RegisterBlock { pub const fn timelr(&self) -> &TIMELR { &self.timelr } - #[doc = "0x10 - Arm alarm 0, and configure the time it will fire. - Once armed, the alarm fires when TIMER_ALARM0 == TIMELR. - The alarm will disarm itself once it fires, and can - be disarmed early using the ARMED status register."] + #[doc = "0x10 - Arm alarm 0, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM0 == TIMELR. The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register."] #[inline(always)] pub const fn alarm0(&self) -> &ALARM0 { &self.alarm0 } - #[doc = "0x14 - Arm alarm 1, and configure the time it will fire. - Once armed, the alarm fires when TIMER_ALARM1 == TIMELR. - The alarm will disarm itself once it fires, and can - be disarmed early using the ARMED status register."] + #[doc = "0x14 - Arm alarm 1, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM1 == TIMELR. The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register."] #[inline(always)] pub const fn alarm1(&self) -> &ALARM1 { &self.alarm1 } - #[doc = "0x18 - Arm alarm 2, and configure the time it will fire. - Once armed, the alarm fires when TIMER_ALARM2 == TIMELR. - The alarm will disarm itself once it fires, and can - be disarmed early using the ARMED status register."] + #[doc = "0x18 - Arm alarm 2, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM2 == TIMELR. The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register."] #[inline(always)] pub const fn alarm2(&self) -> &ALARM2 { &self.alarm2 } - #[doc = "0x1c - Arm alarm 3, and configure the time it will fire. - Once armed, the alarm fires when TIMER_ALARM3 == TIMELR. - The alarm will disarm itself once it fires, and can - be disarmed early using the ARMED status register."] + #[doc = "0x1c - Arm alarm 3, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM3 == TIMELR. The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register."] #[inline(always)] pub const fn alarm3(&self) -> &ALARM3 { &self.alarm3 } - #[doc = "0x20 - Indicates the armed/disarmed status of each alarm. - A write to the corresponding ALARMx register arms the alarm. - Alarms automatically disarm upon firing, but writing ones here - will disarm immediately without waiting to fire."] + #[doc = "0x20 - Indicates the armed/disarmed status of each alarm. A write to the corresponding ALARMx register arms the alarm. Alarms automatically disarm upon firing, but writing ones here will disarm immediately without waiting to fire."] #[inline(always)] pub const fn armed(&self) -> &ARMED { &self.armed @@ -124,135 +106,99 @@ impl RegisterBlock { &self.ints } } -#[doc = "TIMEHW (w) register accessor: Write to bits 63:32 of time - always write timelw before timehw +#[doc = "TIMEHW (rw) register accessor: Write to bits 63:32 of time always write timelw before timehw -You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timehw::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`timehw::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timehw::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@timehw`] module"] pub type TIMEHW = crate::Reg; -#[doc = "Write to bits 63:32 of time - always write timelw before timehw"] +#[doc = "Write to bits 63:32 of time always write timelw before timehw"] pub mod timehw; -#[doc = "TIMELW (w) register accessor: Write to bits 31:0 of time - writes do not get copied to time until timehw is written +#[doc = "TIMELW (rw) register accessor: Write to bits 31:0 of time writes do not get copied to time until timehw is written -You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timelw::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`timelw::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timelw::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@timelw`] module"] pub type TIMELW = crate::Reg; -#[doc = "Write to bits 31:0 of time - writes do not get copied to time until timehw is written"] +#[doc = "Write to bits 31:0 of time writes do not get copied to time until timehw is written"] pub mod timelw; -#[doc = "TIMEHR (r) register accessor: Read from bits 63:32 of time - always read timelr before timehr +#[doc = "TIMEHR (rw) register accessor: Read from bits 63:32 of time always read timelr before timehr -You can [`read`](crate::generic::Reg::read) this register and get [`timehr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`timehr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timehr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@timehr`] module"] pub type TIMEHR = crate::Reg; -#[doc = "Read from bits 63:32 of time - always read timelr before timehr"] +#[doc = "Read from bits 63:32 of time always read timelr before timehr"] pub mod timehr; -#[doc = "TIMELR (r) register accessor: Read from bits 31:0 of time +#[doc = "TIMELR (rw) register accessor: Read from bits 31:0 of time -You can [`read`](crate::generic::Reg::read) this register and get [`timelr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`timelr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timelr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@timelr`] module"] pub type TIMELR = crate::Reg; #[doc = "Read from bits 31:0 of time"] pub mod timelr; -#[doc = "ALARM0 (rw) register accessor: Arm alarm 0, and configure the time it will fire. - Once armed, the alarm fires when TIMER_ALARM0 == TIMELR. - The alarm will disarm itself once it fires, and can - be disarmed early using the ARMED status register. +#[doc = "ALARM0 (rw) register accessor: Arm alarm 0, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM0 == TIMELR. The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register. You can [`read`](crate::generic::Reg::read) this register and get [`alarm0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`alarm0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@alarm0`] module"] pub type ALARM0 = crate::Reg; -#[doc = "Arm alarm 0, and configure the time it will fire. - Once armed, the alarm fires when TIMER_ALARM0 == TIMELR. - The alarm will disarm itself once it fires, and can - be disarmed early using the ARMED status register."] +#[doc = "Arm alarm 0, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM0 == TIMELR. The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register."] pub mod alarm0; -#[doc = "ALARM1 (rw) register accessor: Arm alarm 1, and configure the time it will fire. - Once armed, the alarm fires when TIMER_ALARM1 == TIMELR. - The alarm will disarm itself once it fires, and can - be disarmed early using the ARMED status register. +#[doc = "ALARM1 (rw) register accessor: Arm alarm 1, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM1 == TIMELR. The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register. You can [`read`](crate::generic::Reg::read) this register and get [`alarm1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`alarm1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@alarm1`] module"] pub type ALARM1 = crate::Reg; -#[doc = "Arm alarm 1, and configure the time it will fire. - Once armed, the alarm fires when TIMER_ALARM1 == TIMELR. - The alarm will disarm itself once it fires, and can - be disarmed early using the ARMED status register."] +#[doc = "Arm alarm 1, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM1 == TIMELR. The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register."] pub mod alarm1; -#[doc = "ALARM2 (rw) register accessor: Arm alarm 2, and configure the time it will fire. - Once armed, the alarm fires when TIMER_ALARM2 == TIMELR. - The alarm will disarm itself once it fires, and can - be disarmed early using the ARMED status register. +#[doc = "ALARM2 (rw) register accessor: Arm alarm 2, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM2 == TIMELR. The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register. You can [`read`](crate::generic::Reg::read) this register and get [`alarm2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`alarm2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@alarm2`] module"] pub type ALARM2 = crate::Reg; -#[doc = "Arm alarm 2, and configure the time it will fire. - Once armed, the alarm fires when TIMER_ALARM2 == TIMELR. - The alarm will disarm itself once it fires, and can - be disarmed early using the ARMED status register."] +#[doc = "Arm alarm 2, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM2 == TIMELR. The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register."] pub mod alarm2; -#[doc = "ALARM3 (rw) register accessor: Arm alarm 3, and configure the time it will fire. - Once armed, the alarm fires when TIMER_ALARM3 == TIMELR. - The alarm will disarm itself once it fires, and can - be disarmed early using the ARMED status register. +#[doc = "ALARM3 (rw) register accessor: Arm alarm 3, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM3 == TIMELR. The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register. You can [`read`](crate::generic::Reg::read) this register and get [`alarm3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`alarm3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@alarm3`] module"] pub type ALARM3 = crate::Reg; -#[doc = "Arm alarm 3, and configure the time it will fire. - Once armed, the alarm fires when TIMER_ALARM3 == TIMELR. - The alarm will disarm itself once it fires, and can - be disarmed early using the ARMED status register."] +#[doc = "Arm alarm 3, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM3 == TIMELR. The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register."] pub mod alarm3; -#[doc = "ARMED (rw) register accessor: Indicates the armed/disarmed status of each alarm. - A write to the corresponding ALARMx register arms the alarm. - Alarms automatically disarm upon firing, but writing ones here - will disarm immediately without waiting to fire. +#[doc = "ARMED (rw) register accessor: Indicates the armed/disarmed status of each alarm. A write to the corresponding ALARMx register arms the alarm. Alarms automatically disarm upon firing, but writing ones here will disarm immediately without waiting to fire. You can [`read`](crate::generic::Reg::read) this register and get [`armed::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`armed::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@armed`] module"] pub type ARMED = crate::Reg; -#[doc = "Indicates the armed/disarmed status of each alarm. - A write to the corresponding ALARMx register arms the alarm. - Alarms automatically disarm upon firing, but writing ones here - will disarm immediately without waiting to fire."] +#[doc = "Indicates the armed/disarmed status of each alarm. A write to the corresponding ALARMx register arms the alarm. Alarms automatically disarm upon firing, but writing ones here will disarm immediately without waiting to fire."] pub mod armed; -#[doc = "TIMERAWH (r) register accessor: Raw read from bits 63:32 of time (no side effects) +#[doc = "TIMERAWH (rw) register accessor: Raw read from bits 63:32 of time (no side effects) -You can [`read`](crate::generic::Reg::read) this register and get [`timerawh::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`timerawh::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timerawh::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@timerawh`] module"] pub type TIMERAWH = crate::Reg; #[doc = "Raw read from bits 63:32 of time (no side effects)"] pub mod timerawh; -#[doc = "TIMERAWL (r) register accessor: Raw read from bits 31:0 of time (no side effects) +#[doc = "TIMERAWL (rw) register accessor: Raw read from bits 31:0 of time (no side effects) -You can [`read`](crate::generic::Reg::read) this register and get [`timerawl::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`timerawl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timerawl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@timerawl`] module"] @@ -304,9 +250,9 @@ module"] pub type INTF = crate::Reg; #[doc = "Interrupt Force"] pub mod intf; -#[doc = "INTS (r) register accessor: Interrupt status after masking & forcing +#[doc = "INTS (rw) register accessor: Interrupt status after masking & forcing -You can [`read`](crate::generic::Reg::read) this register and get [`ints::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`ints::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ints::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@ints`] module"] diff --git a/src/timer/alarm0.rs b/src/timer/alarm0.rs index f1e81b6ed..2eacd87c9 100644 --- a/src/timer/alarm0.rs +++ b/src/timer/alarm0.rs @@ -2,21 +2,26 @@ pub type R = crate::R; #[doc = "Register `ALARM0` writer"] pub type W = crate::W; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) +#[doc = "Field `ALARM0` reader - "] +pub type ALARM0_R = crate::FieldReader; +#[doc = "Field `ALARM0` writer - "] +pub type ALARM0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn alarm0(&self) -> ALARM0_R { + ALARM0_R::new(self.bits) } } -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn alarm0(&mut self) -> ALARM0_W { + ALARM0_W::new(self, 0) } } -impl W {} -#[doc = "Arm alarm 0, and configure the time it will fire. - Once armed, the alarm fires when TIMER_ALARM0 == TIMELR. - The alarm will disarm itself once it fires, and can - be disarmed early using the ARMED status register. +#[doc = "Arm alarm 0, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM0 == TIMELR. The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register. You can [`read`](crate::generic::Reg::read) this register and get [`alarm0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`alarm0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ALARM0_SPEC; diff --git a/src/timer/alarm1.rs b/src/timer/alarm1.rs index 777798520..cdb405299 100644 --- a/src/timer/alarm1.rs +++ b/src/timer/alarm1.rs @@ -2,21 +2,26 @@ pub type R = crate::R; #[doc = "Register `ALARM1` writer"] pub type W = crate::W; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) +#[doc = "Field `ALARM1` reader - "] +pub type ALARM1_R = crate::FieldReader; +#[doc = "Field `ALARM1` writer - "] +pub type ALARM1_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn alarm1(&self) -> ALARM1_R { + ALARM1_R::new(self.bits) } } -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn alarm1(&mut self) -> ALARM1_W { + ALARM1_W::new(self, 0) } } -impl W {} -#[doc = "Arm alarm 1, and configure the time it will fire. - Once armed, the alarm fires when TIMER_ALARM1 == TIMELR. - The alarm will disarm itself once it fires, and can - be disarmed early using the ARMED status register. +#[doc = "Arm alarm 1, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM1 == TIMELR. The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register. You can [`read`](crate::generic::Reg::read) this register and get [`alarm1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`alarm1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ALARM1_SPEC; diff --git a/src/timer/alarm2.rs b/src/timer/alarm2.rs index fc9df4b3b..138a38379 100644 --- a/src/timer/alarm2.rs +++ b/src/timer/alarm2.rs @@ -2,21 +2,26 @@ pub type R = crate::R; #[doc = "Register `ALARM2` writer"] pub type W = crate::W; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) +#[doc = "Field `ALARM2` reader - "] +pub type ALARM2_R = crate::FieldReader; +#[doc = "Field `ALARM2` writer - "] +pub type ALARM2_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn alarm2(&self) -> ALARM2_R { + ALARM2_R::new(self.bits) } } -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn alarm2(&mut self) -> ALARM2_W { + ALARM2_W::new(self, 0) } } -impl W {} -#[doc = "Arm alarm 2, and configure the time it will fire. - Once armed, the alarm fires when TIMER_ALARM2 == TIMELR. - The alarm will disarm itself once it fires, and can - be disarmed early using the ARMED status register. +#[doc = "Arm alarm 2, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM2 == TIMELR. The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register. You can [`read`](crate::generic::Reg::read) this register and get [`alarm2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`alarm2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ALARM2_SPEC; diff --git a/src/timer/alarm3.rs b/src/timer/alarm3.rs index 1cfb87e31..5a822ef00 100644 --- a/src/timer/alarm3.rs +++ b/src/timer/alarm3.rs @@ -2,21 +2,26 @@ pub type R = crate::R; #[doc = "Register `ALARM3` writer"] pub type W = crate::W; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) +#[doc = "Field `ALARM3` reader - "] +pub type ALARM3_R = crate::FieldReader; +#[doc = "Field `ALARM3` writer - "] +pub type ALARM3_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn alarm3(&self) -> ALARM3_R { + ALARM3_R::new(self.bits) } } -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn alarm3(&mut self) -> ALARM3_W { + ALARM3_W::new(self, 0) } } -impl W {} -#[doc = "Arm alarm 3, and configure the time it will fire. - Once armed, the alarm fires when TIMER_ALARM3 == TIMELR. - The alarm will disarm itself once it fires, and can - be disarmed early using the ARMED status register. +#[doc = "Arm alarm 3, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM3 == TIMELR. The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register. You can [`read`](crate::generic::Reg::read) this register and get [`alarm3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`alarm3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ALARM3_SPEC; diff --git a/src/timer/armed.rs b/src/timer/armed.rs index b904725f3..dc6b07daa 100644 --- a/src/timer/armed.rs +++ b/src/timer/armed.rs @@ -21,10 +21,7 @@ impl W { ARMED_W::new(self, 0) } } -#[doc = "Indicates the armed/disarmed status of each alarm. - A write to the corresponding ALARMx register arms the alarm. - Alarms automatically disarm upon firing, but writing ones here - will disarm immediately without waiting to fire. +#[doc = "Indicates the armed/disarmed status of each alarm. A write to the corresponding ALARMx register arms the alarm. Alarms automatically disarm upon firing, but writing ones here will disarm immediately without waiting to fire. You can [`read`](crate::generic::Reg::read) this register and get [`armed::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`armed::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ARMED_SPEC; diff --git a/src/timer/ints.rs b/src/timer/ints.rs index 07c304dee..25727cd64 100644 --- a/src/timer/ints.rs +++ b/src/timer/ints.rs @@ -1,5 +1,7 @@ #[doc = "Register `INTS` reader"] pub type R = crate::R; +#[doc = "Register `INTS` writer"] +pub type W = crate::W; #[doc = "Field `ALARM_0` reader - "] pub type ALARM_0_R = crate::BitReader; #[doc = "Field `ALARM_1` reader - "] @@ -30,15 +32,22 @@ impl R { ALARM_3_R::new(((self.bits >> 3) & 1) != 0) } } +impl W {} #[doc = "Interrupt status after masking & forcing -You can [`read`](crate::generic::Reg::read) this register and get [`ints::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`ints::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ints::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTS_SPEC; impl crate::RegisterSpec for INTS_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`ints::R`](R) reader structure"] impl crate::Readable for INTS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ints::W`](W) writer structure"] +impl crate::Writable for INTS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets INTS to value 0"] impl crate::Resettable for INTS_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/timer/timehr.rs b/src/timer/timehr.rs index d2b74ad15..6cc6ca652 100644 --- a/src/timer/timehr.rs +++ b/src/timer/timehr.rs @@ -1,25 +1,32 @@ #[doc = "Register `TIMEHR` reader"] pub type R = crate::R; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) +#[doc = "Register `TIMEHR` writer"] +pub type W = crate::W; +#[doc = "Field `TIMEHR` reader - "] +pub type TIMEHR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn timehr(&self) -> TIMEHR_R { + TIMEHR_R::new(self.bits) } } -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} -#[doc = "Read from bits 63:32 of time - always read timelr before timehr +impl W {} +#[doc = "Read from bits 63:32 of time always read timelr before timehr -You can [`read`](crate::generic::Reg::read) this register and get [`timehr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`timehr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timehr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TIMEHR_SPEC; impl crate::RegisterSpec for TIMEHR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`timehr::R`](R) reader structure"] impl crate::Readable for TIMEHR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`timehr::W`](W) writer structure"] +impl crate::Writable for TIMEHR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets TIMEHR to value 0"] impl crate::Resettable for TIMEHR_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/timer/timehw.rs b/src/timer/timehw.rs index 86dfb59ab..1818b2169 100644 --- a/src/timer/timehw.rs +++ b/src/timer/timehw.rs @@ -1,19 +1,26 @@ +#[doc = "Register `TIMEHW` reader"] +pub type R = crate::R; #[doc = "Register `TIMEHW` writer"] pub type W = crate::W; -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - write!(f, "(not readable)") +#[doc = "Field `TIMEHW` writer - "] +pub type TIMEHW_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn timehw(&mut self) -> TIMEHW_W { + TIMEHW_W::new(self, 0) } } -impl W {} -#[doc = "Write to bits 63:32 of time - always write timelw before timehw +#[doc = "Write to bits 63:32 of time always write timelw before timehw -You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timehw::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`timehw::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timehw::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TIMEHW_SPEC; impl crate::RegisterSpec for TIMEHW_SPEC { type Ux = u32; } +#[doc = "`read()` method returns [`timehw::R`](R) reader structure"] +impl crate::Readable for TIMEHW_SPEC {} #[doc = "`write(|w| ..)` method takes [`timehw::W`](W) writer structure"] impl crate::Writable for TIMEHW_SPEC { type Safety = crate::Unsafe; diff --git a/src/timer/timelr.rs b/src/timer/timelr.rs index c61b62115..db7f094a7 100644 --- a/src/timer/timelr.rs +++ b/src/timer/timelr.rs @@ -1,24 +1,34 @@ #[doc = "Register `TIMELR` reader"] pub type R = crate::R; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) - } -} -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +#[doc = "Register `TIMELR` writer"] +pub type W = crate::W; +#[doc = "Field `TIMELR` reader - + +The field is **modified** in some way after a read operation."] +pub type TIMELR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn timelr(&self) -> TIMELR_R { + TIMELR_R::new(self.bits) } } +impl W {} #[doc = "Read from bits 31:0 of time -You can [`read`](crate::generic::Reg::read) this register and get [`timelr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`timelr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timelr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TIMELR_SPEC; impl crate::RegisterSpec for TIMELR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`timelr::R`](R) reader structure"] impl crate::Readable for TIMELR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`timelr::W`](W) writer structure"] +impl crate::Writable for TIMELR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets TIMELR to value 0"] impl crate::Resettable for TIMELR_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/timer/timelw.rs b/src/timer/timelw.rs index 0ef1b5cb6..9d91cc9d9 100644 --- a/src/timer/timelw.rs +++ b/src/timer/timelw.rs @@ -1,19 +1,26 @@ +#[doc = "Register `TIMELW` reader"] +pub type R = crate::R; #[doc = "Register `TIMELW` writer"] pub type W = crate::W; -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - write!(f, "(not readable)") +#[doc = "Field `TIMELW` writer - "] +pub type TIMELW_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn timelw(&mut self) -> TIMELW_W { + TIMELW_W::new(self, 0) } } -impl W {} -#[doc = "Write to bits 31:0 of time - writes do not get copied to time until timehw is written +#[doc = "Write to bits 31:0 of time writes do not get copied to time until timehw is written -You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timelw::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`timelw::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timelw::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TIMELW_SPEC; impl crate::RegisterSpec for TIMELW_SPEC { type Ux = u32; } +#[doc = "`read()` method returns [`timelw::R`](R) reader structure"] +impl crate::Readable for TIMELW_SPEC {} #[doc = "`write(|w| ..)` method takes [`timelw::W`](W) writer structure"] impl crate::Writable for TIMELW_SPEC { type Safety = crate::Unsafe; diff --git a/src/timer/timerawh.rs b/src/timer/timerawh.rs index 6606249a8..1db39cda6 100644 --- a/src/timer/timerawh.rs +++ b/src/timer/timerawh.rs @@ -1,24 +1,32 @@ #[doc = "Register `TIMERAWH` reader"] pub type R = crate::R; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) - } -} -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +#[doc = "Register `TIMERAWH` writer"] +pub type W = crate::W; +#[doc = "Field `TIMERAWH` reader - "] +pub type TIMERAWH_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn timerawh(&self) -> TIMERAWH_R { + TIMERAWH_R::new(self.bits) } } +impl W {} #[doc = "Raw read from bits 63:32 of time (no side effects) -You can [`read`](crate::generic::Reg::read) this register and get [`timerawh::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`timerawh::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timerawh::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TIMERAWH_SPEC; impl crate::RegisterSpec for TIMERAWH_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`timerawh::R`](R) reader structure"] impl crate::Readable for TIMERAWH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`timerawh::W`](W) writer structure"] +impl crate::Writable for TIMERAWH_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets TIMERAWH to value 0"] impl crate::Resettable for TIMERAWH_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/timer/timerawl.rs b/src/timer/timerawl.rs index d64a58ffd..04695939a 100644 --- a/src/timer/timerawl.rs +++ b/src/timer/timerawl.rs @@ -1,24 +1,32 @@ #[doc = "Register `TIMERAWL` reader"] pub type R = crate::R; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) - } -} -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +#[doc = "Register `TIMERAWL` writer"] +pub type W = crate::W; +#[doc = "Field `TIMERAWL` reader - "] +pub type TIMERAWL_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn timerawl(&self) -> TIMERAWL_R { + TIMERAWL_R::new(self.bits) } } +impl W {} #[doc = "Raw read from bits 31:0 of time (no side effects) -You can [`read`](crate::generic::Reg::read) this register and get [`timerawl::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`timerawl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timerawl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TIMERAWL_SPEC; impl crate::RegisterSpec for TIMERAWL_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`timerawl::R`](R) reader structure"] impl crate::Readable for TIMERAWL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`timerawl::W`](W) writer structure"] +impl crate::Writable for TIMERAWL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets TIMERAWL to value 0"] impl crate::Resettable for TIMERAWL_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/uart0.rs b/src/uart0.rs index fd19a9339..ca35b3898 100644 --- a/src/uart0.rs +++ b/src/uart0.rs @@ -157,9 +157,9 @@ module"] pub type UARTRSR = crate::Reg; #[doc = "Receive Status Register/Error Clear Register, UARTRSR/UARTECR"] pub mod uartrsr; -#[doc = "UARTFR (r) register accessor: Flag Register, UARTFR +#[doc = "UARTFR (rw) register accessor: Flag Register, UARTFR -You can [`read`](crate::generic::Reg::read) this register and get [`uartfr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`uartfr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uartfr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@uartfr`] module"] @@ -229,18 +229,18 @@ module"] pub type UARTIMSC = crate::Reg; #[doc = "Interrupt Mask Set/Clear Register, UARTIMSC"] pub mod uartimsc; -#[doc = "UARTRIS (r) register accessor: Raw Interrupt Status Register, UARTRIS +#[doc = "UARTRIS (rw) register accessor: Raw Interrupt Status Register, UARTRIS -You can [`read`](crate::generic::Reg::read) this register and get [`uartris::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`uartris::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uartris::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@uartris`] module"] pub type UARTRIS = crate::Reg; #[doc = "Raw Interrupt Status Register, UARTRIS"] pub mod uartris; -#[doc = "UARTMIS (r) register accessor: Masked Interrupt Status Register, UARTMIS +#[doc = "UARTMIS (rw) register accessor: Masked Interrupt Status Register, UARTMIS -You can [`read`](crate::generic::Reg::read) this register and get [`uartmis::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`uartmis::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uartmis::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@uartmis`] module"] @@ -265,72 +265,72 @@ module"] pub type UARTDMACR = crate::Reg; #[doc = "DMA Control Register, UARTDMACR"] pub mod uartdmacr; -#[doc = "UARTPERIPHID0 (r) register accessor: UARTPeriphID0 Register +#[doc = "UARTPERIPHID0 (rw) register accessor: UARTPeriphID0 Register -You can [`read`](crate::generic::Reg::read) this register and get [`uartperiphid0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`uartperiphid0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uartperiphid0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@uartperiphid0`] module"] pub type UARTPERIPHID0 = crate::Reg; #[doc = "UARTPeriphID0 Register"] pub mod uartperiphid0; -#[doc = "UARTPERIPHID1 (r) register accessor: UARTPeriphID1 Register +#[doc = "UARTPERIPHID1 (rw) register accessor: UARTPeriphID1 Register -You can [`read`](crate::generic::Reg::read) this register and get [`uartperiphid1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`uartperiphid1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uartperiphid1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@uartperiphid1`] module"] pub type UARTPERIPHID1 = crate::Reg; #[doc = "UARTPeriphID1 Register"] pub mod uartperiphid1; -#[doc = "UARTPERIPHID2 (r) register accessor: UARTPeriphID2 Register +#[doc = "UARTPERIPHID2 (rw) register accessor: UARTPeriphID2 Register -You can [`read`](crate::generic::Reg::read) this register and get [`uartperiphid2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`uartperiphid2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uartperiphid2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@uartperiphid2`] module"] pub type UARTPERIPHID2 = crate::Reg; #[doc = "UARTPeriphID2 Register"] pub mod uartperiphid2; -#[doc = "UARTPERIPHID3 (r) register accessor: UARTPeriphID3 Register +#[doc = "UARTPERIPHID3 (rw) register accessor: UARTPeriphID3 Register -You can [`read`](crate::generic::Reg::read) this register and get [`uartperiphid3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`uartperiphid3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uartperiphid3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@uartperiphid3`] module"] pub type UARTPERIPHID3 = crate::Reg; #[doc = "UARTPeriphID3 Register"] pub mod uartperiphid3; -#[doc = "UARTPCELLID0 (r) register accessor: UARTPCellID0 Register +#[doc = "UARTPCELLID0 (rw) register accessor: UARTPCellID0 Register -You can [`read`](crate::generic::Reg::read) this register and get [`uartpcellid0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`uartpcellid0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uartpcellid0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@uartpcellid0`] module"] pub type UARTPCELLID0 = crate::Reg; #[doc = "UARTPCellID0 Register"] pub mod uartpcellid0; -#[doc = "UARTPCELLID1 (r) register accessor: UARTPCellID1 Register +#[doc = "UARTPCELLID1 (rw) register accessor: UARTPCellID1 Register -You can [`read`](crate::generic::Reg::read) this register and get [`uartpcellid1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`uartpcellid1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uartpcellid1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@uartpcellid1`] module"] pub type UARTPCELLID1 = crate::Reg; #[doc = "UARTPCellID1 Register"] pub mod uartpcellid1; -#[doc = "UARTPCELLID2 (r) register accessor: UARTPCellID2 Register +#[doc = "UARTPCELLID2 (rw) register accessor: UARTPCellID2 Register -You can [`read`](crate::generic::Reg::read) this register and get [`uartpcellid2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`uartpcellid2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uartpcellid2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@uartpcellid2`] module"] pub type UARTPCELLID2 = crate::Reg; #[doc = "UARTPCellID2 Register"] pub mod uartpcellid2; -#[doc = "UARTPCELLID3 (r) register accessor: UARTPCellID3 Register +#[doc = "UARTPCELLID3 (rw) register accessor: UARTPCellID3 Register -You can [`read`](crate::generic::Reg::read) this register and get [`uartpcellid3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`uartpcellid3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uartpcellid3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@uartpcellid3`] module"] diff --git a/src/uart0/uartdr.rs b/src/uart0/uartdr.rs index 536a5856a..38545c7ad 100644 --- a/src/uart0/uartdr.rs +++ b/src/uart0/uartdr.rs @@ -2,7 +2,9 @@ pub type R = crate::R; #[doc = "Register `UARTDR` writer"] pub type W = crate::W; -#[doc = "Field `DATA` reader - Receive (read) data character. Transmit (write) data character."] +#[doc = "Field `DATA` reader - Receive (read) data character. Transmit (write) data character. + +The field is **modified** in some way after a read operation."] pub type DATA_R = crate::FieldReader; #[doc = "Field `DATA` writer - Receive (read) data character. Transmit (write) data character."] pub type DATA_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; diff --git a/src/uart0/uartfr.rs b/src/uart0/uartfr.rs index 5c0a90224..fdb81f60d 100644 --- a/src/uart0/uartfr.rs +++ b/src/uart0/uartfr.rs @@ -1,5 +1,7 @@ #[doc = "Register `UARTFR` reader"] pub type R = crate::R; +#[doc = "Register `UARTFR` writer"] +pub type W = crate::W; #[doc = "Field `CTS` reader - Clear to send. This bit is the complement of the UART clear to send, nUARTCTS, modem status input. That is, the bit is 1 when nUARTCTS is LOW."] pub type CTS_R = crate::BitReader; #[doc = "Field `DSR` reader - Data set ready. This bit is the complement of the UART data set ready, nUARTDSR, modem status input. That is, the bit is 1 when nUARTDSR is LOW."] @@ -65,15 +67,22 @@ impl R { RI_R::new(((self.bits >> 8) & 1) != 0) } } +impl W {} #[doc = "Flag Register, UARTFR -You can [`read`](crate::generic::Reg::read) this register and get [`uartfr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`uartfr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uartfr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct UARTFR_SPEC; impl crate::RegisterSpec for UARTFR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`uartfr::R`](R) reader structure"] impl crate::Readable for UARTFR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`uartfr::W`](W) writer structure"] +impl crate::Writable for UARTFR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets UARTFR to value 0x90"] impl crate::Resettable for UARTFR_SPEC { const RESET_VALUE: u32 = 0x90; diff --git a/src/uart0/uartmis.rs b/src/uart0/uartmis.rs index 6e6a75b24..cb323bfe0 100644 --- a/src/uart0/uartmis.rs +++ b/src/uart0/uartmis.rs @@ -1,5 +1,7 @@ #[doc = "Register `UARTMIS` reader"] pub type R = crate::R; +#[doc = "Register `UARTMIS` writer"] +pub type W = crate::W; #[doc = "Field `RIMMIS` reader - nUARTRI modem masked interrupt status. Returns the masked interrupt state of the UARTRIINTR interrupt."] pub type RIMMIS_R = crate::BitReader; #[doc = "Field `CTSMMIS` reader - nUARTCTS modem masked interrupt status. Returns the masked interrupt state of the UARTCTSINTR interrupt."] @@ -79,15 +81,22 @@ impl R { OEMIS_R::new(((self.bits >> 10) & 1) != 0) } } +impl W {} #[doc = "Masked Interrupt Status Register, UARTMIS -You can [`read`](crate::generic::Reg::read) this register and get [`uartmis::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`uartmis::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uartmis::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct UARTMIS_SPEC; impl crate::RegisterSpec for UARTMIS_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`uartmis::R`](R) reader structure"] impl crate::Readable for UARTMIS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`uartmis::W`](W) writer structure"] +impl crate::Writable for UARTMIS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets UARTMIS to value 0"] impl crate::Resettable for UARTMIS_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/uart0/uartpcellid0.rs b/src/uart0/uartpcellid0.rs index 267869f30..72c661926 100644 --- a/src/uart0/uartpcellid0.rs +++ b/src/uart0/uartpcellid0.rs @@ -1,5 +1,7 @@ #[doc = "Register `UARTPCELLID0` reader"] pub type R = crate::R; +#[doc = "Register `UARTPCELLID0` writer"] +pub type W = crate::W; #[doc = "Field `UARTPCELLID0` reader - These bits read back as 0x0D"] pub type UARTPCELLID0_R = crate::FieldReader; impl R { @@ -9,15 +11,22 @@ impl R { UARTPCELLID0_R::new((self.bits & 0xff) as u8) } } +impl W {} #[doc = "UARTPCellID0 Register -You can [`read`](crate::generic::Reg::read) this register and get [`uartpcellid0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`uartpcellid0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uartpcellid0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct UARTPCELLID0_SPEC; impl crate::RegisterSpec for UARTPCELLID0_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`uartpcellid0::R`](R) reader structure"] impl crate::Readable for UARTPCELLID0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`uartpcellid0::W`](W) writer structure"] +impl crate::Writable for UARTPCELLID0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets UARTPCELLID0 to value 0x0d"] impl crate::Resettable for UARTPCELLID0_SPEC { const RESET_VALUE: u32 = 0x0d; diff --git a/src/uart0/uartpcellid1.rs b/src/uart0/uartpcellid1.rs index 3a6e0aaa8..534cbba1d 100644 --- a/src/uart0/uartpcellid1.rs +++ b/src/uart0/uartpcellid1.rs @@ -1,5 +1,7 @@ #[doc = "Register `UARTPCELLID1` reader"] pub type R = crate::R; +#[doc = "Register `UARTPCELLID1` writer"] +pub type W = crate::W; #[doc = "Field `UARTPCELLID1` reader - These bits read back as 0xF0"] pub type UARTPCELLID1_R = crate::FieldReader; impl R { @@ -9,15 +11,22 @@ impl R { UARTPCELLID1_R::new((self.bits & 0xff) as u8) } } +impl W {} #[doc = "UARTPCellID1 Register -You can [`read`](crate::generic::Reg::read) this register and get [`uartpcellid1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`uartpcellid1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uartpcellid1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct UARTPCELLID1_SPEC; impl crate::RegisterSpec for UARTPCELLID1_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`uartpcellid1::R`](R) reader structure"] impl crate::Readable for UARTPCELLID1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`uartpcellid1::W`](W) writer structure"] +impl crate::Writable for UARTPCELLID1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets UARTPCELLID1 to value 0xf0"] impl crate::Resettable for UARTPCELLID1_SPEC { const RESET_VALUE: u32 = 0xf0; diff --git a/src/uart0/uartpcellid2.rs b/src/uart0/uartpcellid2.rs index aca6be310..29ecdab47 100644 --- a/src/uart0/uartpcellid2.rs +++ b/src/uart0/uartpcellid2.rs @@ -1,5 +1,7 @@ #[doc = "Register `UARTPCELLID2` reader"] pub type R = crate::R; +#[doc = "Register `UARTPCELLID2` writer"] +pub type W = crate::W; #[doc = "Field `UARTPCELLID2` reader - These bits read back as 0x05"] pub type UARTPCELLID2_R = crate::FieldReader; impl R { @@ -9,15 +11,22 @@ impl R { UARTPCELLID2_R::new((self.bits & 0xff) as u8) } } +impl W {} #[doc = "UARTPCellID2 Register -You can [`read`](crate::generic::Reg::read) this register and get [`uartpcellid2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`uartpcellid2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uartpcellid2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct UARTPCELLID2_SPEC; impl crate::RegisterSpec for UARTPCELLID2_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`uartpcellid2::R`](R) reader structure"] impl crate::Readable for UARTPCELLID2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`uartpcellid2::W`](W) writer structure"] +impl crate::Writable for UARTPCELLID2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets UARTPCELLID2 to value 0x05"] impl crate::Resettable for UARTPCELLID2_SPEC { const RESET_VALUE: u32 = 0x05; diff --git a/src/uart0/uartpcellid3.rs b/src/uart0/uartpcellid3.rs index 20c3cbbd8..0b6fa2aab 100644 --- a/src/uart0/uartpcellid3.rs +++ b/src/uart0/uartpcellid3.rs @@ -1,5 +1,7 @@ #[doc = "Register `UARTPCELLID3` reader"] pub type R = crate::R; +#[doc = "Register `UARTPCELLID3` writer"] +pub type W = crate::W; #[doc = "Field `UARTPCELLID3` reader - These bits read back as 0xB1"] pub type UARTPCELLID3_R = crate::FieldReader; impl R { @@ -9,15 +11,22 @@ impl R { UARTPCELLID3_R::new((self.bits & 0xff) as u8) } } +impl W {} #[doc = "UARTPCellID3 Register -You can [`read`](crate::generic::Reg::read) this register and get [`uartpcellid3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`uartpcellid3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uartpcellid3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct UARTPCELLID3_SPEC; impl crate::RegisterSpec for UARTPCELLID3_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`uartpcellid3::R`](R) reader structure"] impl crate::Readable for UARTPCELLID3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`uartpcellid3::W`](W) writer structure"] +impl crate::Writable for UARTPCELLID3_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets UARTPCELLID3 to value 0xb1"] impl crate::Resettable for UARTPCELLID3_SPEC { const RESET_VALUE: u32 = 0xb1; diff --git a/src/uart0/uartperiphid0.rs b/src/uart0/uartperiphid0.rs index 2adb7b15b..7d1282791 100644 --- a/src/uart0/uartperiphid0.rs +++ b/src/uart0/uartperiphid0.rs @@ -1,5 +1,7 @@ #[doc = "Register `UARTPERIPHID0` reader"] pub type R = crate::R; +#[doc = "Register `UARTPERIPHID0` writer"] +pub type W = crate::W; #[doc = "Field `PARTNUMBER0` reader - These bits read back as 0x11"] pub type PARTNUMBER0_R = crate::FieldReader; impl R { @@ -9,15 +11,22 @@ impl R { PARTNUMBER0_R::new((self.bits & 0xff) as u8) } } +impl W {} #[doc = "UARTPeriphID0 Register -You can [`read`](crate::generic::Reg::read) this register and get [`uartperiphid0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`uartperiphid0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uartperiphid0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct UARTPERIPHID0_SPEC; impl crate::RegisterSpec for UARTPERIPHID0_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`uartperiphid0::R`](R) reader structure"] impl crate::Readable for UARTPERIPHID0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`uartperiphid0::W`](W) writer structure"] +impl crate::Writable for UARTPERIPHID0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets UARTPERIPHID0 to value 0x11"] impl crate::Resettable for UARTPERIPHID0_SPEC { const RESET_VALUE: u32 = 0x11; diff --git a/src/uart0/uartperiphid1.rs b/src/uart0/uartperiphid1.rs index 83365ed0c..51426a259 100644 --- a/src/uart0/uartperiphid1.rs +++ b/src/uart0/uartperiphid1.rs @@ -1,5 +1,7 @@ #[doc = "Register `UARTPERIPHID1` reader"] pub type R = crate::R; +#[doc = "Register `UARTPERIPHID1` writer"] +pub type W = crate::W; #[doc = "Field `PARTNUMBER1` reader - These bits read back as 0x0"] pub type PARTNUMBER1_R = crate::FieldReader; #[doc = "Field `DESIGNER0` reader - These bits read back as 0x1"] @@ -16,15 +18,22 @@ impl R { DESIGNER0_R::new(((self.bits >> 4) & 0x0f) as u8) } } +impl W {} #[doc = "UARTPeriphID1 Register -You can [`read`](crate::generic::Reg::read) this register and get [`uartperiphid1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`uartperiphid1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uartperiphid1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct UARTPERIPHID1_SPEC; impl crate::RegisterSpec for UARTPERIPHID1_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`uartperiphid1::R`](R) reader structure"] impl crate::Readable for UARTPERIPHID1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`uartperiphid1::W`](W) writer structure"] +impl crate::Writable for UARTPERIPHID1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets UARTPERIPHID1 to value 0x10"] impl crate::Resettable for UARTPERIPHID1_SPEC { const RESET_VALUE: u32 = 0x10; diff --git a/src/uart0/uartperiphid2.rs b/src/uart0/uartperiphid2.rs index 814a1623a..e0e0dd35c 100644 --- a/src/uart0/uartperiphid2.rs +++ b/src/uart0/uartperiphid2.rs @@ -1,5 +1,7 @@ #[doc = "Register `UARTPERIPHID2` reader"] pub type R = crate::R; +#[doc = "Register `UARTPERIPHID2` writer"] +pub type W = crate::W; #[doc = "Field `DESIGNER1` reader - These bits read back as 0x4"] pub type DESIGNER1_R = crate::FieldReader; #[doc = "Field `REVISION` reader - This field depends on the revision of the UART: r1p0 0x0 r1p1 0x1 r1p3 0x2 r1p4 0x2 r1p5 0x3"] @@ -16,15 +18,22 @@ impl R { REVISION_R::new(((self.bits >> 4) & 0x0f) as u8) } } +impl W {} #[doc = "UARTPeriphID2 Register -You can [`read`](crate::generic::Reg::read) this register and get [`uartperiphid2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`uartperiphid2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uartperiphid2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct UARTPERIPHID2_SPEC; impl crate::RegisterSpec for UARTPERIPHID2_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`uartperiphid2::R`](R) reader structure"] impl crate::Readable for UARTPERIPHID2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`uartperiphid2::W`](W) writer structure"] +impl crate::Writable for UARTPERIPHID2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets UARTPERIPHID2 to value 0x34"] impl crate::Resettable for UARTPERIPHID2_SPEC { const RESET_VALUE: u32 = 0x34; diff --git a/src/uart0/uartperiphid3.rs b/src/uart0/uartperiphid3.rs index f0469f93b..33561b335 100644 --- a/src/uart0/uartperiphid3.rs +++ b/src/uart0/uartperiphid3.rs @@ -1,5 +1,7 @@ #[doc = "Register `UARTPERIPHID3` reader"] pub type R = crate::R; +#[doc = "Register `UARTPERIPHID3` writer"] +pub type W = crate::W; #[doc = "Field `CONFIGURATION` reader - These bits read back as 0x00"] pub type CONFIGURATION_R = crate::FieldReader; impl R { @@ -9,15 +11,22 @@ impl R { CONFIGURATION_R::new((self.bits & 0xff) as u8) } } +impl W {} #[doc = "UARTPeriphID3 Register -You can [`read`](crate::generic::Reg::read) this register and get [`uartperiphid3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`uartperiphid3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uartperiphid3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct UARTPERIPHID3_SPEC; impl crate::RegisterSpec for UARTPERIPHID3_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`uartperiphid3::R`](R) reader structure"] impl crate::Readable for UARTPERIPHID3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`uartperiphid3::W`](W) writer structure"] +impl crate::Writable for UARTPERIPHID3_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets UARTPERIPHID3 to value 0"] impl crate::Resettable for UARTPERIPHID3_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/uart0/uartris.rs b/src/uart0/uartris.rs index fc94789fc..02ce2ce27 100644 --- a/src/uart0/uartris.rs +++ b/src/uart0/uartris.rs @@ -1,5 +1,7 @@ #[doc = "Register `UARTRIS` reader"] pub type R = crate::R; +#[doc = "Register `UARTRIS` writer"] +pub type W = crate::W; #[doc = "Field `RIRMIS` reader - nUARTRI modem interrupt status. Returns the raw interrupt state of the UARTRIINTR interrupt."] pub type RIRMIS_R = crate::BitReader; #[doc = "Field `CTSRMIS` reader - nUARTCTS modem interrupt status. Returns the raw interrupt state of the UARTCTSINTR interrupt."] @@ -79,15 +81,22 @@ impl R { OERIS_R::new(((self.bits >> 10) & 1) != 0) } } +impl W {} #[doc = "Raw Interrupt Status Register, UARTRIS -You can [`read`](crate::generic::Reg::read) this register and get [`uartris::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`uartris::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uartris::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct UARTRIS_SPEC; impl crate::RegisterSpec for UARTRIS_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`uartris::R`](R) reader structure"] impl crate::Readable for UARTRIS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`uartris::W`](W) writer structure"] +impl crate::Writable for UARTRIS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets UARTRIS to value 0"] impl crate::Resettable for UARTRIS_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/usbctrl_dpram/ep_buffer_control.rs b/src/usbctrl_dpram/ep_buffer_control.rs index c977f2907..7f1cdde08 100644 --- a/src/usbctrl_dpram/ep_buffer_control.rs +++ b/src/usbctrl_dpram/ep_buffer_control.rs @@ -38,8 +38,7 @@ pub type LENGTH_1_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; pub type AVAILABLE_1_R = crate::BitReader; #[doc = "Field `AVAILABLE_1` writer - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back."] pub type AVAILABLE_1_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. - For a non Isochronous endpoint the offset is always 64 bytes. +#[doc = "The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. For a non Isochronous endpoint the offset is always 64 bytes. Value on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -63,8 +62,7 @@ impl From for u8 { impl crate::FieldSpec for DOUBLE_BUFFER_ISO_OFFSET_A { type Ux = u8; } -#[doc = "Field `DOUBLE_BUFFER_ISO_OFFSET` reader - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. - For a non Isochronous endpoint the offset is always 64 bytes."] +#[doc = "Field `DOUBLE_BUFFER_ISO_OFFSET` reader - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. For a non Isochronous endpoint the offset is always 64 bytes."] pub type DOUBLE_BUFFER_ISO_OFFSET_R = crate::FieldReader; impl DOUBLE_BUFFER_ISO_OFFSET_R { #[doc = "Get enumerated values variant"] @@ -99,8 +97,7 @@ impl DOUBLE_BUFFER_ISO_OFFSET_R { *self == DOUBLE_BUFFER_ISO_OFFSET_A::_1024 } } -#[doc = "Field `DOUBLE_BUFFER_ISO_OFFSET` writer - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. - For a non Isochronous endpoint the offset is always 64 bytes."] +#[doc = "Field `DOUBLE_BUFFER_ISO_OFFSET` writer - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. For a non Isochronous endpoint the offset is always 64 bytes."] pub type DOUBLE_BUFFER_ISO_OFFSET_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, DOUBLE_BUFFER_ISO_OFFSET_A>; impl<'a, REG> DOUBLE_BUFFER_ISO_OFFSET_W<'a, REG> @@ -187,8 +184,7 @@ impl R { pub fn available_1(&self) -> AVAILABLE_1_R { AVAILABLE_1_R::new(((self.bits >> 26) & 1) != 0) } - #[doc = "Bits 27:28 - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. - For a non Isochronous endpoint the offset is always 64 bytes."] + #[doc = "Bits 27:28 - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. For a non Isochronous endpoint the offset is always 64 bytes."] #[inline(always)] pub fn double_buffer_iso_offset(&self) -> DOUBLE_BUFFER_ISO_OFFSET_R { DOUBLE_BUFFER_ISO_OFFSET_R::new(((self.bits >> 27) & 3) as u8) @@ -264,8 +260,7 @@ impl W { pub fn available_1(&mut self) -> AVAILABLE_1_W { AVAILABLE_1_W::new(self, 26) } - #[doc = "Bits 27:28 - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. - For a non Isochronous endpoint the offset is always 64 bytes."] + #[doc = "Bits 27:28 - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. For a non Isochronous endpoint the offset is always 64 bytes."] #[inline(always)] #[must_use] pub fn double_buffer_iso_offset( diff --git a/src/usbctrl_regs.rs b/src/usbctrl_regs.rs index 621027c35..62766aaab 100644 --- a/src/usbctrl_regs.rs +++ b/src/usbctrl_regs.rs @@ -189,22 +189,22 @@ impl RegisterBlock { pub const fn usb_muxing(&self) -> &USB_MUXING { &self.usb_muxing } - #[doc = "0x78 - Overrides for the power signals in the event that the VBUS signals are not hooked up to GPIO. Set the value of the override and then the override enable to switch over to the override value."] + #[doc = "0x78 - Overrides for the power signals in the event that the VBUS signals are not hooked up to GPIO. Set the value of the override and then the override enable so switch over to the override value."] #[inline(always)] pub const fn usb_pwr(&self) -> &USB_PWR { &self.usb_pwr } - #[doc = "0x7c - This register allows for direct control of the USB phy. Use in conjunction with usbphy_direct_override register to enable each override bit."] + #[doc = "0x7c - Note that most functions are driven directly from usb_fsls controller. This register allows more detailed control/status from the USB PHY. Useful for debug but not expected to be used in normal operation Use in conjunction with usbphy_direct_override register"] #[inline(always)] pub const fn usbphy_direct(&self) -> &USBPHY_DIRECT { &self.usbphy_direct } - #[doc = "0x80 - Override enable for each control in usbphy_direct"] + #[doc = "0x80 - "] #[inline(always)] pub const fn usbphy_direct_override(&self) -> &USBPHY_DIRECT_OVERRIDE { &self.usbphy_direct_override } - #[doc = "0x84 - Used to adjust trim values of USB phy pull down resistors."] + #[doc = "0x84 - Note that most functions are driven directly from usb_fsls controller. This register allows more detailed control/status from the USB PHY. Useful for debug but not expected to be used in normal operation"] #[inline(always)] pub const fn usbphy_trim(&self) -> &USBPHY_TRIM { &self.usbphy_trim @@ -257,18 +257,18 @@ module"] pub type MAIN_CTRL = crate::Reg; #[doc = "Main control register"] pub mod main_ctrl; -#[doc = "SOF_WR (w) register accessor: Set the SOF (Start of Frame) frame number in the host controller. The SOF packet is sent every 1ms and the host will increment the frame number by 1 each time. +#[doc = "SOF_WR (rw) register accessor: Set the SOF (Start of Frame) frame number in the host controller. The SOF packet is sent every 1ms and the host will increment the frame number by 1 each time. -You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sof_wr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`sof_wr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sof_wr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@sof_wr`] module"] pub type SOF_WR = crate::Reg; #[doc = "Set the SOF (Start of Frame) frame number in the host controller. The SOF packet is sent every 1ms and the host will increment the frame number by 1 each time."] pub mod sof_wr; -#[doc = "SOF_RD (r) register accessor: Read the last SOF (Start of Frame) frame number seen. In device mode the last SOF received from the host. In host mode the last SOF sent by the host. +#[doc = "SOF_RD (rw) register accessor: Read the last SOF (Start of Frame) frame number seen. In device mode the last SOF received from the host. In host mode the last SOF sent by the host. -You can [`read`](crate::generic::Reg::read) this register and get [`sof_rd::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`sof_rd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sof_rd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@sof_rd`] module"] @@ -311,9 +311,9 @@ module"] pub type BUFF_STATUS = crate::Reg; #[doc = "Buffer status register. A bit set here indicates that a buffer has completed on the endpoint (if the buffer interrupt is enabled). It is possible for 2 buffers to be completed, so clearing the buffer status bit may instantly re set it on the next clock cycle."] pub mod buff_status; -#[doc = "BUFF_CPU_SHOULD_HANDLE (r) register accessor: Which of the double buffers should be handled. Only valid if using an interrupt per buffer (i.e. not per 2 buffers). Not valid for host interrupt endpoint polling because they are only single buffered. +#[doc = "BUFF_CPU_SHOULD_HANDLE (rw) register accessor: Which of the double buffers should be handled. Only valid if using an interrupt per buffer (i.e. not per 2 buffers). Not valid for host interrupt endpoint polling because they are only single buffered. -You can [`read`](crate::generic::Reg::read) this register and get [`buff_cpu_should_handle::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`buff_cpu_should_handle::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`buff_cpu_should_handle::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@buff_cpu_should_handle`] module"] @@ -374,45 +374,45 @@ module"] pub type USB_MUXING = crate::Reg; #[doc = "Where to connect the USB controller. Should be to_phy by default."] pub mod usb_muxing; -#[doc = "USB_PWR (rw) register accessor: Overrides for the power signals in the event that the VBUS signals are not hooked up to GPIO. Set the value of the override and then the override enable to switch over to the override value. +#[doc = "USB_PWR (rw) register accessor: Overrides for the power signals in the event that the VBUS signals are not hooked up to GPIO. Set the value of the override and then the override enable so switch over to the override value. You can [`read`](crate::generic::Reg::read) this register and get [`usb_pwr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usb_pwr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@usb_pwr`] module"] pub type USB_PWR = crate::Reg; -#[doc = "Overrides for the power signals in the event that the VBUS signals are not hooked up to GPIO. Set the value of the override and then the override enable to switch over to the override value."] +#[doc = "Overrides for the power signals in the event that the VBUS signals are not hooked up to GPIO. Set the value of the override and then the override enable so switch over to the override value."] pub mod usb_pwr; -#[doc = "USBPHY_DIRECT (rw) register accessor: This register allows for direct control of the USB phy. Use in conjunction with usbphy_direct_override register to enable each override bit. +#[doc = "USBPHY_DIRECT (rw) register accessor: Note that most functions are driven directly from usb_fsls controller. This register allows more detailed control/status from the USB PHY. Useful for debug but not expected to be used in normal operation Use in conjunction with usbphy_direct_override register You can [`read`](crate::generic::Reg::read) this register and get [`usbphy_direct::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usbphy_direct::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@usbphy_direct`] module"] pub type USBPHY_DIRECT = crate::Reg; -#[doc = "This register allows for direct control of the USB phy. Use in conjunction with usbphy_direct_override register to enable each override bit."] +#[doc = "Note that most functions are driven directly from usb_fsls controller. This register allows more detailed control/status from the USB PHY. Useful for debug but not expected to be used in normal operation Use in conjunction with usbphy_direct_override register"] pub mod usbphy_direct; -#[doc = "USBPHY_DIRECT_OVERRIDE (rw) register accessor: Override enable for each control in usbphy_direct +#[doc = "USBPHY_DIRECT_OVERRIDE (rw) register accessor: You can [`read`](crate::generic::Reg::read) this register and get [`usbphy_direct_override::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usbphy_direct_override::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@usbphy_direct_override`] module"] pub type USBPHY_DIRECT_OVERRIDE = crate::Reg; -#[doc = "Override enable for each control in usbphy_direct"] +#[doc = ""] pub mod usbphy_direct_override; -#[doc = "USBPHY_TRIM (rw) register accessor: Used to adjust trim values of USB phy pull down resistors. +#[doc = "USBPHY_TRIM (rw) register accessor: Note that most functions are driven directly from usb_fsls controller. This register allows more detailed control/status from the USB PHY. Useful for debug but not expected to be used in normal operation You can [`read`](crate::generic::Reg::read) this register and get [`usbphy_trim::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usbphy_trim::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@usbphy_trim`] module"] pub type USBPHY_TRIM = crate::Reg; -#[doc = "Used to adjust trim values of USB phy pull down resistors."] +#[doc = "Note that most functions are driven directly from usb_fsls controller. This register allows more detailed control/status from the USB PHY. Useful for debug but not expected to be used in normal operation"] pub mod usbphy_trim; -#[doc = "INTR (r) register accessor: Raw Interrupts +#[doc = "INTR (rw) register accessor: Raw Interrupts -You can [`read`](crate::generic::Reg::read) this register and get [`intr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`intr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@intr`] module"] @@ -437,9 +437,9 @@ module"] pub type INTF = crate::Reg; #[doc = "Interrupt Force"] pub mod intf; -#[doc = "INTS (r) register accessor: Interrupt status after masking & forcing +#[doc = "INTS (rw) register accessor: Interrupt status after masking & forcing -You can [`read`](crate::generic::Reg::read) this register and get [`ints::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`ints::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ints::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@ints`] module"] diff --git a/src/usbctrl_regs/buff_cpu_should_handle.rs b/src/usbctrl_regs/buff_cpu_should_handle.rs index b16e18a1e..9e4a41953 100644 --- a/src/usbctrl_regs/buff_cpu_should_handle.rs +++ b/src/usbctrl_regs/buff_cpu_should_handle.rs @@ -1,5 +1,7 @@ #[doc = "Register `BUFF_CPU_SHOULD_HANDLE` reader"] pub type R = crate::R; +#[doc = "Register `BUFF_CPU_SHOULD_HANDLE` writer"] +pub type W = crate::W; #[doc = "Field `EP0_IN` reader - "] pub type EP0_IN_R = crate::BitReader; #[doc = "Field `EP0_OUT` reader - "] @@ -226,15 +228,22 @@ impl R { EP15_OUT_R::new(((self.bits >> 31) & 1) != 0) } } +impl W {} #[doc = "Which of the double buffers should be handled. Only valid if using an interrupt per buffer (i.e. not per 2 buffers). Not valid for host interrupt endpoint polling because they are only single buffered. -You can [`read`](crate::generic::Reg::read) this register and get [`buff_cpu_should_handle::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`buff_cpu_should_handle::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`buff_cpu_should_handle::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct BUFF_CPU_SHOULD_HANDLE_SPEC; impl crate::RegisterSpec for BUFF_CPU_SHOULD_HANDLE_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`buff_cpu_should_handle::R`](R) reader structure"] impl crate::Readable for BUFF_CPU_SHOULD_HANDLE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`buff_cpu_should_handle::W`](W) writer structure"] +impl crate::Writable for BUFF_CPU_SHOULD_HANDLE_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets BUFF_CPU_SHOULD_HANDLE to value 0"] impl crate::Resettable for BUFF_CPU_SHOULD_HANDLE_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/usbctrl_regs/int_ep_ctrl.rs b/src/usbctrl_regs/int_ep_ctrl.rs index 9a2797a76..6c2050b2d 100644 --- a/src/usbctrl_regs/int_ep_ctrl.rs +++ b/src/usbctrl_regs/int_ep_ctrl.rs @@ -2,19 +2,19 @@ pub type R = crate::R; #[doc = "Register `INT_EP_CTRL` writer"] pub type W = crate::W; -#[doc = "Field `INT_EP_ACTIVE` reader - Host: Enable interrupt endpoint 1 -> 15"] +#[doc = "Field `INT_EP_ACTIVE` reader - Host: Enable interrupt endpoint 1 => 15"] pub type INT_EP_ACTIVE_R = crate::FieldReader; -#[doc = "Field `INT_EP_ACTIVE` writer - Host: Enable interrupt endpoint 1 -> 15"] +#[doc = "Field `INT_EP_ACTIVE` writer - Host: Enable interrupt endpoint 1 => 15"] pub type INT_EP_ACTIVE_W<'a, REG> = crate::FieldWriter<'a, REG, 15, u16>; impl R { - #[doc = "Bits 1:15 - Host: Enable interrupt endpoint 1 -> 15"] + #[doc = "Bits 1:15 - Host: Enable interrupt endpoint 1 => 15"] #[inline(always)] pub fn int_ep_active(&self) -> INT_EP_ACTIVE_R { INT_EP_ACTIVE_R::new(((self.bits >> 1) & 0x7fff) as u16) } } impl W { - #[doc = "Bits 1:15 - Host: Enable interrupt endpoint 1 -> 15"] + #[doc = "Bits 1:15 - Host: Enable interrupt endpoint 1 => 15"] #[inline(always)] #[must_use] pub fn int_ep_active(&mut self) -> INT_EP_ACTIVE_W { diff --git a/src/usbctrl_regs/inte.rs b/src/usbctrl_regs/inte.rs index 2bd0946d8..925a0d567 100644 --- a/src/usbctrl_regs/inte.rs +++ b/src/usbctrl_regs/inte.rs @@ -6,9 +6,9 @@ pub type W = crate::W; pub type HOST_CONN_DIS_R = crate::BitReader; #[doc = "Field `HOST_CONN_DIS` writer - Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED"] pub type HOST_CONN_DIS_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `HOST_RESUME` reader - Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME"] +#[doc = "Field `HOST_RESUME` reader - Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME_REMOTE"] pub type HOST_RESUME_R = crate::BitReader; -#[doc = "Field `HOST_RESUME` writer - Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME"] +#[doc = "Field `HOST_RESUME` writer - Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME_REMOTE"] pub type HOST_RESUME_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `HOST_SOF` reader - Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD"] pub type HOST_SOF_R = crate::BitReader; @@ -46,9 +46,9 @@ pub type ERROR_CRC_W<'a, REG> = crate::BitWriter<'a, REG>; pub type STALL_R = crate::BitReader; #[doc = "Field `STALL` writer - Source: SIE_STATUS.STALL_REC"] pub type STALL_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `VBUS_DETECT` reader - Source: SIE_STATUS.VBUS_DETECTED"] +#[doc = "Field `VBUS_DETECT` reader - Source: SIE_STATUS.VBUS_DETECT"] pub type VBUS_DETECT_R = crate::BitReader; -#[doc = "Field `VBUS_DETECT` writer - Source: SIE_STATUS.VBUS_DETECTED"] +#[doc = "Field `VBUS_DETECT` writer - Source: SIE_STATUS.VBUS_DETECT"] pub type VBUS_DETECT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `BUS_RESET` reader - Source: SIE_STATUS.BUS_RESET"] pub type BUS_RESET_R = crate::BitReader; @@ -62,9 +62,9 @@ pub type DEV_CONN_DIS_W<'a, REG> = crate::BitWriter<'a, REG>; pub type DEV_SUSPEND_R = crate::BitReader; #[doc = "Field `DEV_SUSPEND` writer - Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED"] pub type DEV_SUSPEND_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `DEV_RESUME_FROM_HOST` reader - Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME"] +#[doc = "Field `DEV_RESUME_FROM_HOST` reader - Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME_REMOTE"] pub type DEV_RESUME_FROM_HOST_R = crate::BitReader; -#[doc = "Field `DEV_RESUME_FROM_HOST` writer - Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME"] +#[doc = "Field `DEV_RESUME_FROM_HOST` writer - Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME_REMOTE"] pub type DEV_RESUME_FROM_HOST_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `SETUP_REQ` reader - Device. Source: SIE_STATUS.SETUP_REC"] pub type SETUP_REQ_R = crate::BitReader; @@ -88,7 +88,7 @@ impl R { pub fn host_conn_dis(&self) -> HOST_CONN_DIS_R { HOST_CONN_DIS_R::new((self.bits & 1) != 0) } - #[doc = "Bit 1 - Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME"] + #[doc = "Bit 1 - Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME_REMOTE"] #[inline(always)] pub fn host_resume(&self) -> HOST_RESUME_R { HOST_RESUME_R::new(((self.bits >> 1) & 1) != 0) @@ -138,7 +138,7 @@ impl R { pub fn stall(&self) -> STALL_R { STALL_R::new(((self.bits >> 10) & 1) != 0) } - #[doc = "Bit 11 - Source: SIE_STATUS.VBUS_DETECTED"] + #[doc = "Bit 11 - Source: SIE_STATUS.VBUS_DETECT"] #[inline(always)] pub fn vbus_detect(&self) -> VBUS_DETECT_R { VBUS_DETECT_R::new(((self.bits >> 11) & 1) != 0) @@ -158,7 +158,7 @@ impl R { pub fn dev_suspend(&self) -> DEV_SUSPEND_R { DEV_SUSPEND_R::new(((self.bits >> 14) & 1) != 0) } - #[doc = "Bit 15 - Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME"] + #[doc = "Bit 15 - Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME_REMOTE"] #[inline(always)] pub fn dev_resume_from_host(&self) -> DEV_RESUME_FROM_HOST_R { DEV_RESUME_FROM_HOST_R::new(((self.bits >> 15) & 1) != 0) @@ -191,7 +191,7 @@ impl W { pub fn host_conn_dis(&mut self) -> HOST_CONN_DIS_W { HOST_CONN_DIS_W::new(self, 0) } - #[doc = "Bit 1 - Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME"] + #[doc = "Bit 1 - Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME_REMOTE"] #[inline(always)] #[must_use] pub fn host_resume(&mut self) -> HOST_RESUME_W { @@ -251,7 +251,7 @@ impl W { pub fn stall(&mut self) -> STALL_W { STALL_W::new(self, 10) } - #[doc = "Bit 11 - Source: SIE_STATUS.VBUS_DETECTED"] + #[doc = "Bit 11 - Source: SIE_STATUS.VBUS_DETECT"] #[inline(always)] #[must_use] pub fn vbus_detect(&mut self) -> VBUS_DETECT_W { @@ -275,7 +275,7 @@ impl W { pub fn dev_suspend(&mut self) -> DEV_SUSPEND_W { DEV_SUSPEND_W::new(self, 14) } - #[doc = "Bit 15 - Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME"] + #[doc = "Bit 15 - Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME_REMOTE"] #[inline(always)] #[must_use] pub fn dev_resume_from_host(&mut self) -> DEV_RESUME_FROM_HOST_W { diff --git a/src/usbctrl_regs/intf.rs b/src/usbctrl_regs/intf.rs index 3a5fb3f64..fcfd7be18 100644 --- a/src/usbctrl_regs/intf.rs +++ b/src/usbctrl_regs/intf.rs @@ -6,9 +6,9 @@ pub type W = crate::W; pub type HOST_CONN_DIS_R = crate::BitReader; #[doc = "Field `HOST_CONN_DIS` writer - Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED"] pub type HOST_CONN_DIS_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `HOST_RESUME` reader - Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME"] +#[doc = "Field `HOST_RESUME` reader - Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME_REMOTE"] pub type HOST_RESUME_R = crate::BitReader; -#[doc = "Field `HOST_RESUME` writer - Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME"] +#[doc = "Field `HOST_RESUME` writer - Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME_REMOTE"] pub type HOST_RESUME_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `HOST_SOF` reader - Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD"] pub type HOST_SOF_R = crate::BitReader; @@ -46,9 +46,9 @@ pub type ERROR_CRC_W<'a, REG> = crate::BitWriter<'a, REG>; pub type STALL_R = crate::BitReader; #[doc = "Field `STALL` writer - Source: SIE_STATUS.STALL_REC"] pub type STALL_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `VBUS_DETECT` reader - Source: SIE_STATUS.VBUS_DETECTED"] +#[doc = "Field `VBUS_DETECT` reader - Source: SIE_STATUS.VBUS_DETECT"] pub type VBUS_DETECT_R = crate::BitReader; -#[doc = "Field `VBUS_DETECT` writer - Source: SIE_STATUS.VBUS_DETECTED"] +#[doc = "Field `VBUS_DETECT` writer - Source: SIE_STATUS.VBUS_DETECT"] pub type VBUS_DETECT_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `BUS_RESET` reader - Source: SIE_STATUS.BUS_RESET"] pub type BUS_RESET_R = crate::BitReader; @@ -62,9 +62,9 @@ pub type DEV_CONN_DIS_W<'a, REG> = crate::BitWriter<'a, REG>; pub type DEV_SUSPEND_R = crate::BitReader; #[doc = "Field `DEV_SUSPEND` writer - Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED"] pub type DEV_SUSPEND_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `DEV_RESUME_FROM_HOST` reader - Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME"] +#[doc = "Field `DEV_RESUME_FROM_HOST` reader - Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME_REMOTE"] pub type DEV_RESUME_FROM_HOST_R = crate::BitReader; -#[doc = "Field `DEV_RESUME_FROM_HOST` writer - Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME"] +#[doc = "Field `DEV_RESUME_FROM_HOST` writer - Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME_REMOTE"] pub type DEV_RESUME_FROM_HOST_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `SETUP_REQ` reader - Device. Source: SIE_STATUS.SETUP_REC"] pub type SETUP_REQ_R = crate::BitReader; @@ -88,7 +88,7 @@ impl R { pub fn host_conn_dis(&self) -> HOST_CONN_DIS_R { HOST_CONN_DIS_R::new((self.bits & 1) != 0) } - #[doc = "Bit 1 - Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME"] + #[doc = "Bit 1 - Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME_REMOTE"] #[inline(always)] pub fn host_resume(&self) -> HOST_RESUME_R { HOST_RESUME_R::new(((self.bits >> 1) & 1) != 0) @@ -138,7 +138,7 @@ impl R { pub fn stall(&self) -> STALL_R { STALL_R::new(((self.bits >> 10) & 1) != 0) } - #[doc = "Bit 11 - Source: SIE_STATUS.VBUS_DETECTED"] + #[doc = "Bit 11 - Source: SIE_STATUS.VBUS_DETECT"] #[inline(always)] pub fn vbus_detect(&self) -> VBUS_DETECT_R { VBUS_DETECT_R::new(((self.bits >> 11) & 1) != 0) @@ -158,7 +158,7 @@ impl R { pub fn dev_suspend(&self) -> DEV_SUSPEND_R { DEV_SUSPEND_R::new(((self.bits >> 14) & 1) != 0) } - #[doc = "Bit 15 - Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME"] + #[doc = "Bit 15 - Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME_REMOTE"] #[inline(always)] pub fn dev_resume_from_host(&self) -> DEV_RESUME_FROM_HOST_R { DEV_RESUME_FROM_HOST_R::new(((self.bits >> 15) & 1) != 0) @@ -191,7 +191,7 @@ impl W { pub fn host_conn_dis(&mut self) -> HOST_CONN_DIS_W { HOST_CONN_DIS_W::new(self, 0) } - #[doc = "Bit 1 - Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME"] + #[doc = "Bit 1 - Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME_REMOTE"] #[inline(always)] #[must_use] pub fn host_resume(&mut self) -> HOST_RESUME_W { @@ -251,7 +251,7 @@ impl W { pub fn stall(&mut self) -> STALL_W { STALL_W::new(self, 10) } - #[doc = "Bit 11 - Source: SIE_STATUS.VBUS_DETECTED"] + #[doc = "Bit 11 - Source: SIE_STATUS.VBUS_DETECT"] #[inline(always)] #[must_use] pub fn vbus_detect(&mut self) -> VBUS_DETECT_W { @@ -275,7 +275,7 @@ impl W { pub fn dev_suspend(&mut self) -> DEV_SUSPEND_W { DEV_SUSPEND_W::new(self, 14) } - #[doc = "Bit 15 - Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME"] + #[doc = "Bit 15 - Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME_REMOTE"] #[inline(always)] #[must_use] pub fn dev_resume_from_host(&mut self) -> DEV_RESUME_FROM_HOST_W { diff --git a/src/usbctrl_regs/intr.rs b/src/usbctrl_regs/intr.rs index 3738efb2f..9b725756c 100644 --- a/src/usbctrl_regs/intr.rs +++ b/src/usbctrl_regs/intr.rs @@ -1,8 +1,10 @@ #[doc = "Register `INTR` reader"] pub type R = crate::R; +#[doc = "Register `INTR` writer"] +pub type W = crate::W; #[doc = "Field `HOST_CONN_DIS` reader - Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED"] pub type HOST_CONN_DIS_R = crate::BitReader; -#[doc = "Field `HOST_RESUME` reader - Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME"] +#[doc = "Field `HOST_RESUME` reader - Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME_REMOTE"] pub type HOST_RESUME_R = crate::BitReader; #[doc = "Field `HOST_SOF` reader - Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD"] pub type HOST_SOF_R = crate::BitReader; @@ -22,7 +24,7 @@ pub type ERROR_BIT_STUFF_R = crate::BitReader; pub type ERROR_CRC_R = crate::BitReader; #[doc = "Field `STALL` reader - Source: SIE_STATUS.STALL_REC"] pub type STALL_R = crate::BitReader; -#[doc = "Field `VBUS_DETECT` reader - Source: SIE_STATUS.VBUS_DETECTED"] +#[doc = "Field `VBUS_DETECT` reader - Source: SIE_STATUS.VBUS_DETECT"] pub type VBUS_DETECT_R = crate::BitReader; #[doc = "Field `BUS_RESET` reader - Source: SIE_STATUS.BUS_RESET"] pub type BUS_RESET_R = crate::BitReader; @@ -30,7 +32,7 @@ pub type BUS_RESET_R = crate::BitReader; pub type DEV_CONN_DIS_R = crate::BitReader; #[doc = "Field `DEV_SUSPEND` reader - Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED"] pub type DEV_SUSPEND_R = crate::BitReader; -#[doc = "Field `DEV_RESUME_FROM_HOST` reader - Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME"] +#[doc = "Field `DEV_RESUME_FROM_HOST` reader - Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME_REMOTE"] pub type DEV_RESUME_FROM_HOST_R = crate::BitReader; #[doc = "Field `SETUP_REQ` reader - Device. Source: SIE_STATUS.SETUP_REC"] pub type SETUP_REQ_R = crate::BitReader; @@ -46,7 +48,7 @@ impl R { pub fn host_conn_dis(&self) -> HOST_CONN_DIS_R { HOST_CONN_DIS_R::new((self.bits & 1) != 0) } - #[doc = "Bit 1 - Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME"] + #[doc = "Bit 1 - Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME_REMOTE"] #[inline(always)] pub fn host_resume(&self) -> HOST_RESUME_R { HOST_RESUME_R::new(((self.bits >> 1) & 1) != 0) @@ -96,7 +98,7 @@ impl R { pub fn stall(&self) -> STALL_R { STALL_R::new(((self.bits >> 10) & 1) != 0) } - #[doc = "Bit 11 - Source: SIE_STATUS.VBUS_DETECTED"] + #[doc = "Bit 11 - Source: SIE_STATUS.VBUS_DETECT"] #[inline(always)] pub fn vbus_detect(&self) -> VBUS_DETECT_R { VBUS_DETECT_R::new(((self.bits >> 11) & 1) != 0) @@ -116,7 +118,7 @@ impl R { pub fn dev_suspend(&self) -> DEV_SUSPEND_R { DEV_SUSPEND_R::new(((self.bits >> 14) & 1) != 0) } - #[doc = "Bit 15 - Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME"] + #[doc = "Bit 15 - Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME_REMOTE"] #[inline(always)] pub fn dev_resume_from_host(&self) -> DEV_RESUME_FROM_HOST_R { DEV_RESUME_FROM_HOST_R::new(((self.bits >> 15) & 1) != 0) @@ -142,15 +144,22 @@ impl R { EP_STALL_NAK_R::new(((self.bits >> 19) & 1) != 0) } } +impl W {} #[doc = "Raw Interrupts -You can [`read`](crate::generic::Reg::read) this register and get [`intr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`intr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTR_SPEC; impl crate::RegisterSpec for INTR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`intr::R`](R) reader structure"] impl crate::Readable for INTR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`intr::W`](W) writer structure"] +impl crate::Writable for INTR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets INTR to value 0"] impl crate::Resettable for INTR_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/usbctrl_regs/ints.rs b/src/usbctrl_regs/ints.rs index 9154e7a74..974ba90a2 100644 --- a/src/usbctrl_regs/ints.rs +++ b/src/usbctrl_regs/ints.rs @@ -1,8 +1,10 @@ #[doc = "Register `INTS` reader"] pub type R = crate::R; +#[doc = "Register `INTS` writer"] +pub type W = crate::W; #[doc = "Field `HOST_CONN_DIS` reader - Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED"] pub type HOST_CONN_DIS_R = crate::BitReader; -#[doc = "Field `HOST_RESUME` reader - Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME"] +#[doc = "Field `HOST_RESUME` reader - Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME_REMOTE"] pub type HOST_RESUME_R = crate::BitReader; #[doc = "Field `HOST_SOF` reader - Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD"] pub type HOST_SOF_R = crate::BitReader; @@ -22,7 +24,7 @@ pub type ERROR_BIT_STUFF_R = crate::BitReader; pub type ERROR_CRC_R = crate::BitReader; #[doc = "Field `STALL` reader - Source: SIE_STATUS.STALL_REC"] pub type STALL_R = crate::BitReader; -#[doc = "Field `VBUS_DETECT` reader - Source: SIE_STATUS.VBUS_DETECTED"] +#[doc = "Field `VBUS_DETECT` reader - Source: SIE_STATUS.VBUS_DETECT"] pub type VBUS_DETECT_R = crate::BitReader; #[doc = "Field `BUS_RESET` reader - Source: SIE_STATUS.BUS_RESET"] pub type BUS_RESET_R = crate::BitReader; @@ -30,7 +32,7 @@ pub type BUS_RESET_R = crate::BitReader; pub type DEV_CONN_DIS_R = crate::BitReader; #[doc = "Field `DEV_SUSPEND` reader - Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED"] pub type DEV_SUSPEND_R = crate::BitReader; -#[doc = "Field `DEV_RESUME_FROM_HOST` reader - Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME"] +#[doc = "Field `DEV_RESUME_FROM_HOST` reader - Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME_REMOTE"] pub type DEV_RESUME_FROM_HOST_R = crate::BitReader; #[doc = "Field `SETUP_REQ` reader - Device. Source: SIE_STATUS.SETUP_REC"] pub type SETUP_REQ_R = crate::BitReader; @@ -46,7 +48,7 @@ impl R { pub fn host_conn_dis(&self) -> HOST_CONN_DIS_R { HOST_CONN_DIS_R::new((self.bits & 1) != 0) } - #[doc = "Bit 1 - Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME"] + #[doc = "Bit 1 - Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME_REMOTE"] #[inline(always)] pub fn host_resume(&self) -> HOST_RESUME_R { HOST_RESUME_R::new(((self.bits >> 1) & 1) != 0) @@ -96,7 +98,7 @@ impl R { pub fn stall(&self) -> STALL_R { STALL_R::new(((self.bits >> 10) & 1) != 0) } - #[doc = "Bit 11 - Source: SIE_STATUS.VBUS_DETECTED"] + #[doc = "Bit 11 - Source: SIE_STATUS.VBUS_DETECT"] #[inline(always)] pub fn vbus_detect(&self) -> VBUS_DETECT_R { VBUS_DETECT_R::new(((self.bits >> 11) & 1) != 0) @@ -116,7 +118,7 @@ impl R { pub fn dev_suspend(&self) -> DEV_SUSPEND_R { DEV_SUSPEND_R::new(((self.bits >> 14) & 1) != 0) } - #[doc = "Bit 15 - Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME"] + #[doc = "Bit 15 - Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME_REMOTE"] #[inline(always)] pub fn dev_resume_from_host(&self) -> DEV_RESUME_FROM_HOST_R { DEV_RESUME_FROM_HOST_R::new(((self.bits >> 15) & 1) != 0) @@ -142,15 +144,22 @@ impl R { EP_STALL_NAK_R::new(((self.bits >> 19) & 1) != 0) } } +impl W {} #[doc = "Interrupt status after masking & forcing -You can [`read`](crate::generic::Reg::read) this register and get [`ints::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`ints::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ints::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INTS_SPEC; impl crate::RegisterSpec for INTS_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`ints::R`](R) reader structure"] impl crate::Readable for INTS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ints::W`](W) writer structure"] +impl crate::Writable for INTS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets INTS to value 0"] impl crate::Resettable for INTS_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/usbctrl_regs/sie_ctrl.rs b/src/usbctrl_regs/sie_ctrl.rs index c49bffb7c..83928f1a3 100644 --- a/src/usbctrl_regs/sie_ctrl.rs +++ b/src/usbctrl_regs/sie_ctrl.rs @@ -2,8 +2,6 @@ pub type R = crate::R; #[doc = "Register `SIE_CTRL` writer"] pub type W = crate::W; -#[doc = "Field `START_TRANS` reader - Host: Start transaction"] -pub type START_TRANS_R = crate::BitReader; #[doc = "Field `START_TRANS` writer - Host: Start transaction"] pub type START_TRANS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `SEND_SETUP` reader - Host: Send Setup packet"] @@ -18,8 +16,6 @@ pub type SEND_DATA_W<'a, REG> = crate::BitWriter<'a, REG>; pub type RECEIVE_DATA_R = crate::BitReader; #[doc = "Field `RECEIVE_DATA` writer - Host: Receive transaction (IN to host)"] pub type RECEIVE_DATA_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `STOP_TRANS` reader - Host: Stop transaction"] -pub type STOP_TRANS_R = crate::BitReader; #[doc = "Field `STOP_TRANS` writer - Host: Stop transaction"] pub type STOP_TRANS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `PREAMBLE_EN` reader - Host: Preable enable for LS device on FS hub"] @@ -42,12 +38,8 @@ pub type KEEP_ALIVE_EN_W<'a, REG> = crate::BitWriter<'a, REG>; pub type VBUS_EN_R = crate::BitReader; #[doc = "Field `VBUS_EN` writer - Host: Enable VBUS"] pub type VBUS_EN_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `RESUME` reader - Device: Remote wakeup. Device can initiate its own resume after suspend."] -pub type RESUME_R = crate::BitReader; #[doc = "Field `RESUME` writer - Device: Remote wakeup. Device can initiate its own resume after suspend."] pub type RESUME_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `RESET_BUS` reader - Host: Reset bus"] -pub type RESET_BUS_R = crate::BitReader; #[doc = "Field `RESET_BUS` writer - Host: Reset bus"] pub type RESET_BUS_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `PULLDOWN_EN` reader - Host: Enable pull down resistors"] @@ -99,11 +91,6 @@ pub type EP0_INT_STALL_R = crate::BitReader; #[doc = "Field `EP0_INT_STALL` writer - Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a STALL"] pub type EP0_INT_STALL_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { - #[doc = "Bit 0 - Host: Start transaction"] - #[inline(always)] - pub fn start_trans(&self) -> START_TRANS_R { - START_TRANS_R::new((self.bits & 1) != 0) - } #[doc = "Bit 1 - Host: Send Setup packet"] #[inline(always)] pub fn send_setup(&self) -> SEND_SETUP_R { @@ -119,11 +106,6 @@ impl R { pub fn receive_data(&self) -> RECEIVE_DATA_R { RECEIVE_DATA_R::new(((self.bits >> 3) & 1) != 0) } - #[doc = "Bit 4 - Host: Stop transaction"] - #[inline(always)] - pub fn stop_trans(&self) -> STOP_TRANS_R { - STOP_TRANS_R::new(((self.bits >> 4) & 1) != 0) - } #[doc = "Bit 6 - Host: Preable enable for LS device on FS hub"] #[inline(always)] pub fn preamble_en(&self) -> PREAMBLE_EN_R { @@ -149,16 +131,6 @@ impl R { pub fn vbus_en(&self) -> VBUS_EN_R { VBUS_EN_R::new(((self.bits >> 11) & 1) != 0) } - #[doc = "Bit 12 - Device: Remote wakeup. Device can initiate its own resume after suspend."] - #[inline(always)] - pub fn resume(&self) -> RESUME_R { - RESUME_R::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bit 13 - Host: Reset bus"] - #[inline(always)] - pub fn reset_bus(&self) -> RESET_BUS_R { - RESET_BUS_R::new(((self.bits >> 13) & 1) != 0) - } #[doc = "Bit 15 - Host: Enable pull down resistors"] #[inline(always)] pub fn pulldown_en(&self) -> PULLDOWN_EN_R { diff --git a/src/usbctrl_regs/sie_status.rs b/src/usbctrl_regs/sie_status.rs index 56bea6d3d..97f7b0ac6 100644 --- a/src/usbctrl_regs/sie_status.rs +++ b/src/usbctrl_regs/sie_status.rs @@ -69,8 +69,6 @@ pub type SUSPENDED_R = crate::BitReader; pub type SUSPENDED_W<'a, REG> = crate::BitWriter1C<'a, REG>; #[doc = "Field `SPEED` reader - Host: device speed. Disconnected = 00, LS = 01, FS = 10"] pub type SPEED_R = crate::FieldReader; -#[doc = "Field `SPEED` writer - Host: device speed. Disconnected = 00, LS = 01, FS = 10"] -pub type SPEED_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; #[doc = "Field `VBUS_OVER_CURR` reader - VBUS over current detected"] pub type VBUS_OVER_CURR_R = crate::BitReader; #[doc = "Field `RESUME` reader - Host: Device has initiated a remote resume. Device: host has initiated a resume."] @@ -79,31 +77,13 @@ pub type RESUME_R = crate::BitReader; pub type RESUME_W<'a, REG> = crate::BitWriter1C<'a, REG>; #[doc = "Field `CONNECTED` reader - Device: connected"] pub type CONNECTED_R = crate::BitReader; -#[doc = "Field `CONNECTED` writer - Device: connected"] -pub type CONNECTED_W<'a, REG> = crate::BitWriter1C<'a, REG>; #[doc = "Field `SETUP_REC` reader - Device: Setup packet received"] pub type SETUP_REC_R = crate::BitReader; #[doc = "Field `SETUP_REC` writer - Device: Setup packet received"] pub type SETUP_REC_W<'a, REG> = crate::BitWriter1C<'a, REG>; -#[doc = "Field `TRANS_COMPLETE` reader - Transaction complete. - - Raised by device if: - - * An IN or OUT packet is sent with the `LAST_BUFF` bit set in the buffer control register - - Raised by host if: - - * A setup packet is sent when no data in or data out transaction follows * An IN packet is received and the `LAST_BUFF` bit is set in the buffer control register * An IN packet is received with zero length * An OUT packet is sent and the `LAST_BUFF` bit is set"] +#[doc = "Field `TRANS_COMPLETE` reader - Transaction complete. Raised by device if: * An IN or OUT packet is sent with the `LAST_BUFF` bit set in the buffer control register Raised by host if: * A setup packet is sent when no data in or data out transaction follows * An IN packet is received and the `LAST_BUFF` bit is set in the buffer control register * An IN packet is received with zero length * An OUT packet is sent and the `LAST_BUFF` bit is set"] pub type TRANS_COMPLETE_R = crate::BitReader; -#[doc = "Field `TRANS_COMPLETE` writer - Transaction complete. - - Raised by device if: - - * An IN or OUT packet is sent with the `LAST_BUFF` bit set in the buffer control register - - Raised by host if: - - * A setup packet is sent when no data in or data out transaction follows * An IN packet is received and the `LAST_BUFF` bit is set in the buffer control register * An IN packet is received with zero length * An OUT packet is sent and the `LAST_BUFF` bit is set"] +#[doc = "Field `TRANS_COMPLETE` writer - Transaction complete. Raised by device if: * An IN or OUT packet is sent with the `LAST_BUFF` bit set in the buffer control register Raised by host if: * A setup packet is sent when no data in or data out transaction follows * An IN packet is received and the `LAST_BUFF` bit is set in the buffer control register * An IN packet is received with zero length * An OUT packet is sent and the `LAST_BUFF` bit is set"] pub type TRANS_COMPLETE_W<'a, REG> = crate::BitWriter1C<'a, REG>; #[doc = "Field `BUS_RESET` reader - Device: bus reset received"] pub type BUS_RESET_R = crate::BitReader; @@ -137,25 +117,9 @@ pub type STALL_REC_W<'a, REG> = crate::BitWriter1C<'a, REG>; pub type ACK_REC_R = crate::BitReader; #[doc = "Field `ACK_REC` writer - ACK received. Raised by both host and device."] pub type ACK_REC_W<'a, REG> = crate::BitWriter1C<'a, REG>; -#[doc = "Field `DATA_SEQ_ERROR` reader - Data Sequence Error. - - The device can raise a sequence error in the following conditions: - - * A SETUP packet is received followed by a DATA1 packet (data phase should always be DATA0) * An OUT packet is received from the host but doesn't match the data pid in the buffer control register read from DPSRAM - - The host can raise a data sequence error in the following conditions: - - * An IN packet from the device has the wrong data PID"] +#[doc = "Field `DATA_SEQ_ERROR` reader - Data Sequence Error. The device can raise a sequence error in the following conditions: * A SETUP packet is received followed by a DATA1 packet (data phase should always be DATA0) * An OUT packet is received from the host but doesn't match the data pid in the buffer control register read from DPSRAM The host can raise a data sequence error in the following conditions: * An IN packet from the device has the wrong data PID"] pub type DATA_SEQ_ERROR_R = crate::BitReader; -#[doc = "Field `DATA_SEQ_ERROR` writer - Data Sequence Error. - - The device can raise a sequence error in the following conditions: - - * A SETUP packet is received followed by a DATA1 packet (data phase should always be DATA0) * An OUT packet is received from the host but doesn't match the data pid in the buffer control register read from DPSRAM - - The host can raise a data sequence error in the following conditions: - - * An IN packet from the device has the wrong data PID"] +#[doc = "Field `DATA_SEQ_ERROR` writer - Data Sequence Error. The device can raise a sequence error in the following conditions: * A SETUP packet is received followed by a DATA1 packet (data phase should always be DATA0) * An OUT packet is received from the host but doesn't match the data pid in the buffer control register read from DPSRAM The host can raise a data sequence error in the following conditions: * An IN packet from the device has the wrong data PID"] pub type DATA_SEQ_ERROR_W<'a, REG> = crate::BitWriter1C<'a, REG>; impl R { #[doc = "Bit 0 - Device: VBUS Detected"] @@ -198,15 +162,7 @@ impl R { pub fn setup_rec(&self) -> SETUP_REC_R { SETUP_REC_R::new(((self.bits >> 17) & 1) != 0) } - #[doc = "Bit 18 - Transaction complete. - - Raised by device if: - - * An IN or OUT packet is sent with the `LAST_BUFF` bit set in the buffer control register - - Raised by host if: - - * A setup packet is sent when no data in or data out transaction follows * An IN packet is received and the `LAST_BUFF` bit is set in the buffer control register * An IN packet is received with zero length * An OUT packet is sent and the `LAST_BUFF` bit is set"] + #[doc = "Bit 18 - Transaction complete. Raised by device if: * An IN or OUT packet is sent with the `LAST_BUFF` bit set in the buffer control register Raised by host if: * A setup packet is sent when no data in or data out transaction follows * An IN packet is received and the `LAST_BUFF` bit is set in the buffer control register * An IN packet is received with zero length * An OUT packet is sent and the `LAST_BUFF` bit is set"] #[inline(always)] pub fn trans_complete(&self) -> TRANS_COMPLETE_R { TRANS_COMPLETE_R::new(((self.bits >> 18) & 1) != 0) @@ -251,15 +207,7 @@ impl R { pub fn ack_rec(&self) -> ACK_REC_R { ACK_REC_R::new(((self.bits >> 30) & 1) != 0) } - #[doc = "Bit 31 - Data Sequence Error. - - The device can raise a sequence error in the following conditions: - - * A SETUP packet is received followed by a DATA1 packet (data phase should always be DATA0) * An OUT packet is received from the host but doesn't match the data pid in the buffer control register read from DPSRAM - - The host can raise a data sequence error in the following conditions: - - * An IN packet from the device has the wrong data PID"] + #[doc = "Bit 31 - Data Sequence Error. The device can raise a sequence error in the following conditions: * A SETUP packet is received followed by a DATA1 packet (data phase should always be DATA0) * An OUT packet is received from the host but doesn't match the data pid in the buffer control register read from DPSRAM The host can raise a data sequence error in the following conditions: * An IN packet from the device has the wrong data PID"] #[inline(always)] pub fn data_seq_error(&self) -> DATA_SEQ_ERROR_R { DATA_SEQ_ERROR_R::new(((self.bits >> 31) & 1) != 0) @@ -272,39 +220,19 @@ impl W { pub fn suspended(&mut self) -> SUSPENDED_W { SUSPENDED_W::new(self, 4) } - #[doc = "Bits 8:9 - Host: device speed. Disconnected = 00, LS = 01, FS = 10"] - #[inline(always)] - #[must_use] - pub fn speed(&mut self) -> SPEED_W { - SPEED_W::new(self, 8) - } #[doc = "Bit 11 - Host: Device has initiated a remote resume. Device: host has initiated a resume."] #[inline(always)] #[must_use] pub fn resume(&mut self) -> RESUME_W { RESUME_W::new(self, 11) } - #[doc = "Bit 16 - Device: connected"] - #[inline(always)] - #[must_use] - pub fn connected(&mut self) -> CONNECTED_W { - CONNECTED_W::new(self, 16) - } #[doc = "Bit 17 - Device: Setup packet received"] #[inline(always)] #[must_use] pub fn setup_rec(&mut self) -> SETUP_REC_W { SETUP_REC_W::new(self, 17) } - #[doc = "Bit 18 - Transaction complete. - - Raised by device if: - - * An IN or OUT packet is sent with the `LAST_BUFF` bit set in the buffer control register - - Raised by host if: - - * A setup packet is sent when no data in or data out transaction follows * An IN packet is received and the `LAST_BUFF` bit is set in the buffer control register * An IN packet is received with zero length * An OUT packet is sent and the `LAST_BUFF` bit is set"] + #[doc = "Bit 18 - Transaction complete. Raised by device if: * An IN or OUT packet is sent with the `LAST_BUFF` bit set in the buffer control register Raised by host if: * A setup packet is sent when no data in or data out transaction follows * An IN packet is received and the `LAST_BUFF` bit is set in the buffer control register * An IN packet is received with zero length * An OUT packet is sent and the `LAST_BUFF` bit is set"] #[inline(always)] #[must_use] pub fn trans_complete(&mut self) -> TRANS_COMPLETE_W { @@ -358,15 +286,7 @@ impl W { pub fn ack_rec(&mut self) -> ACK_REC_W { ACK_REC_W::new(self, 30) } - #[doc = "Bit 31 - Data Sequence Error. - - The device can raise a sequence error in the following conditions: - - * A SETUP packet is received followed by a DATA1 packet (data phase should always be DATA0) * An OUT packet is received from the host but doesn't match the data pid in the buffer control register read from DPSRAM - - The host can raise a data sequence error in the following conditions: - - * An IN packet from the device has the wrong data PID"] + #[doc = "Bit 31 - Data Sequence Error. The device can raise a sequence error in the following conditions: * A SETUP packet is received followed by a DATA1 packet (data phase should always be DATA0) * An OUT packet is received from the host but doesn't match the data pid in the buffer control register read from DPSRAM The host can raise a data sequence error in the following conditions: * An IN packet from the device has the wrong data PID"] #[inline(always)] #[must_use] pub fn data_seq_error(&mut self) -> DATA_SEQ_ERROR_W { @@ -386,7 +306,7 @@ impl crate::Readable for SIE_STATUS_SPEC {} impl crate::Writable for SIE_STATUS_SPEC { type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0xff0f_0b10; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0xff0e_0810; } #[doc = "`reset()` method sets SIE_STATUS to value 0"] impl crate::Resettable for SIE_STATUS_SPEC { diff --git a/src/usbctrl_regs/sof_rd.rs b/src/usbctrl_regs/sof_rd.rs index 841ab00e9..29700faf6 100644 --- a/src/usbctrl_regs/sof_rd.rs +++ b/src/usbctrl_regs/sof_rd.rs @@ -1,5 +1,7 @@ #[doc = "Register `SOF_RD` reader"] pub type R = crate::R; +#[doc = "Register `SOF_RD` writer"] +pub type W = crate::W; #[doc = "Field `COUNT` reader - "] pub type COUNT_R = crate::FieldReader; impl R { @@ -9,15 +11,22 @@ impl R { COUNT_R::new((self.bits & 0x07ff) as u16) } } +impl W {} #[doc = "Read the last SOF (Start of Frame) frame number seen. In device mode the last SOF received from the host. In host mode the last SOF sent by the host. -You can [`read`](crate::generic::Reg::read) this register and get [`sof_rd::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`sof_rd::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sof_rd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SOF_RD_SPEC; impl crate::RegisterSpec for SOF_RD_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`sof_rd::R`](R) reader structure"] impl crate::Readable for SOF_RD_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sof_rd::W`](W) writer structure"] +impl crate::Writable for SOF_RD_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets SOF_RD to value 0"] impl crate::Resettable for SOF_RD_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/usbctrl_regs/sof_wr.rs b/src/usbctrl_regs/sof_wr.rs index e5f59e1fe..44a8792e7 100644 --- a/src/usbctrl_regs/sof_wr.rs +++ b/src/usbctrl_regs/sof_wr.rs @@ -1,3 +1,5 @@ +#[doc = "Register `SOF_WR` reader"] +pub type R = crate::R; #[doc = "Register `SOF_WR` writer"] pub type W = crate::W; #[doc = "Field `COUNT` writer - "] @@ -12,11 +14,13 @@ impl W { } #[doc = "Set the SOF (Start of Frame) frame number in the host controller. The SOF packet is sent every 1ms and the host will increment the frame number by 1 each time. -You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sof_wr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`sof_wr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sof_wr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SOF_WR_SPEC; impl crate::RegisterSpec for SOF_WR_SPEC { type Ux = u32; } +#[doc = "`read()` method returns [`sof_wr::R`](R) reader structure"] +impl crate::Readable for SOF_WR_SPEC {} #[doc = "`write(|w| ..)` method takes [`sof_wr::W`](W) writer structure"] impl crate::Writable for SOF_WR_SPEC { type Safety = crate::Unsafe; diff --git a/src/usbctrl_regs/usb_pwr.rs b/src/usbctrl_regs/usb_pwr.rs index 18c2502cc..4e271777d 100644 --- a/src/usbctrl_regs/usb_pwr.rs +++ b/src/usbctrl_regs/usb_pwr.rs @@ -96,7 +96,7 @@ impl W { OVERCURR_DETECT_EN_W::new(self, 5) } } -#[doc = "Overrides for the power signals in the event that the VBUS signals are not hooked up to GPIO. Set the value of the override and then the override enable to switch over to the override value. +#[doc = "Overrides for the power signals in the event that the VBUS signals are not hooked up to GPIO. Set the value of the override and then the override enable so switch over to the override value. You can [`read`](crate::generic::Reg::read) this register and get [`usb_pwr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usb_pwr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct USB_PWR_SPEC; diff --git a/src/usbctrl_regs/usbphy_direct.rs b/src/usbctrl_regs/usbphy_direct.rs index 92262e905..489bf1bff 100644 --- a/src/usbctrl_regs/usbphy_direct.rs +++ b/src/usbctrl_regs/usbphy_direct.rs @@ -2,294 +2,270 @@ pub type R = crate::R; #[doc = "Register `USBPHY_DIRECT` writer"] pub type W = crate::W; -#[doc = "Field `DP_PULLUP_HISEL` reader - Enable the second DP pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2"] +#[doc = "Field `DP_PULLUP_HISEL` reader - when dp_pullup_en is set high, this enables second resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2"] pub type DP_PULLUP_HISEL_R = crate::BitReader; -#[doc = "Field `DP_PULLUP_HISEL` writer - Enable the second DP pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2"] +#[doc = "Field `DP_PULLUP_HISEL` writer - when dp_pullup_en is set high, this enables second resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2"] pub type DP_PULLUP_HISEL_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `DP_PULLUP_EN` reader - DP pull up enable"] +#[doc = "Field `DP_PULLUP_EN` reader - Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller"] pub type DP_PULLUP_EN_R = crate::BitReader; -#[doc = "Field `DP_PULLUP_EN` writer - DP pull up enable"] +#[doc = "Field `DP_PULLUP_EN` writer - Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller"] pub type DP_PULLUP_EN_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `DP_PULLDN_EN` reader - DP pull down enable"] +#[doc = "Field `DP_PULLDN_EN` reader - Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller 1 - Enable Rpd on DPP"] pub type DP_PULLDN_EN_R = crate::BitReader; -#[doc = "Field `DP_PULLDN_EN` writer - DP pull down enable"] +#[doc = "Field `DP_PULLDN_EN` writer - Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller 1 - Enable Rpd on DPP"] pub type DP_PULLDN_EN_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `DM_PULLUP_HISEL` reader - Enable the second DM pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2"] +#[doc = "Field `DM_PULLUP_HISEL` reader - when dm_pullup_en is set high, this enables second resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2"] pub type DM_PULLUP_HISEL_R = crate::BitReader; -#[doc = "Field `DM_PULLUP_HISEL` writer - Enable the second DM pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2"] +#[doc = "Field `DM_PULLUP_HISEL` writer - when dm_pullup_en is set high, this enables second resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2"] pub type DM_PULLUP_HISEL_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `DM_PULLUP_EN` reader - DM pull up enable"] +#[doc = "Field `DM_PULLUP_EN` reader - Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller 1 - Enable Rpu on DPM"] pub type DM_PULLUP_EN_R = crate::BitReader; -#[doc = "Field `DM_PULLUP_EN` writer - DM pull up enable"] +#[doc = "Field `DM_PULLUP_EN` writer - Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller 1 - Enable Rpu on DPM"] pub type DM_PULLUP_EN_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `DM_PULLDN_EN` reader - DM pull down enable"] +#[doc = "Field `DM_PULLDN_EN` reader - Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller 1 - Enable Rpd on DPM"] pub type DM_PULLDN_EN_R = crate::BitReader; -#[doc = "Field `DM_PULLDN_EN` writer - DM pull down enable"] +#[doc = "Field `DM_PULLDN_EN` writer - Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller 1 - Enable Rpd on DPM"] pub type DM_PULLDN_EN_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `TX_DP_OE` reader - Output enable. If TX_DIFFMODE=1, OE for DPP/DPM diff pair. 0 - DPP/DPM in Hi-Z state; 1 - DPP/DPM driving - If TX_DIFFMODE=0, OE for DPP only. 0 - DPP in Hi-Z state; 1 - DPP driving"] +#[doc = "Field `TX_DP_OE` reader - Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller TX_SEMODE=0, OE for DPP/DPM diff pair. 0 - DPP/DPM in Hi-Z state; 1 - DPP/DPM driving TX_SEMODE=1, OE for DPP only. 0 - DPP in Hi-Z state; 1 - DPP driving"] pub type TX_DP_OE_R = crate::BitReader; -#[doc = "Field `TX_DP_OE` writer - Output enable. If TX_DIFFMODE=1, OE for DPP/DPM diff pair. 0 - DPP/DPM in Hi-Z state; 1 - DPP/DPM driving - If TX_DIFFMODE=0, OE for DPP only. 0 - DPP in Hi-Z state; 1 - DPP driving"] +#[doc = "Field `TX_DP_OE` writer - Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller TX_SEMODE=0, OE for DPP/DPM diff pair. 0 - DPP/DPM in Hi-Z state; 1 - DPP/DPM driving TX_SEMODE=1, OE for DPP only. 0 - DPP in Hi-Z state; 1 - DPP driving"] pub type TX_DP_OE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `TX_DM_OE` reader - Output enable. If TX_DIFFMODE=1, Ignored. - If TX_DIFFMODE=0, OE for DPM only. 0 - DPM in Hi-Z state; 1 - DPM driving"] +#[doc = "Field `TX_DM_OE` reader - Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller TX_SEMODE=0, Ignored. TX_SEMODE=1, OE for DPM only. 0 - DPM in Hi-Z state; 1 - DPM driving"] pub type TX_DM_OE_R = crate::BitReader; -#[doc = "Field `TX_DM_OE` writer - Output enable. If TX_DIFFMODE=1, Ignored. - If TX_DIFFMODE=0, OE for DPM only. 0 - DPM in Hi-Z state; 1 - DPM driving"] +#[doc = "Field `TX_DM_OE` writer - Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller TX_SEMODE=0, Ignored. TX_SEMODE=1, OE for DPM only. 0 - DPM in Hi-Z state; 1 - DPM driving"] pub type TX_DM_OE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `TX_DP` reader - Output data. If TX_DIFFMODE=1, Drives DPP/DPM diff pair. TX_DP_OE=1 to enable drive. DPP=TX_DP, DPM=~TX_DP - If TX_DIFFMODE=0, Drives DPP only. TX_DP_OE=1 to enable drive. DPP=TX_DP"] +#[doc = "Field `TX_DP` reader - Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller TX_SEMODE=0, Drives DPP/DPM diff pair. TX_DP_OE=1 to enable drive. DPP=TX_DP, DPM=~TX_DP TX_SEMODE=1, Drives DPP only. TX_DP_OE=1 to enable drive. DPP=TX_DP"] pub type TX_DP_R = crate::BitReader; -#[doc = "Field `TX_DP` writer - Output data. If TX_DIFFMODE=1, Drives DPP/DPM diff pair. TX_DP_OE=1 to enable drive. DPP=TX_DP, DPM=~TX_DP - If TX_DIFFMODE=0, Drives DPP only. TX_DP_OE=1 to enable drive. DPP=TX_DP"] +#[doc = "Field `TX_DP` writer - Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller TX_SEMODE=0, Drives DPP/DPM diff pair. TX_DP_OE=1 to enable drive. DPP=TX_DP, DPM=~TX_DP TX_SEMODE=1, Drives DPP only. TX_DP_OE=1 to enable drive. DPP=TX_DP"] pub type TX_DP_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `TX_DM` reader - Output data. TX_DIFFMODE=1, Ignored - TX_DIFFMODE=0, Drives DPM only. TX_DM_OE=1 to enable drive. DPM=TX_DM"] +#[doc = "Field `TX_DM` reader - Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller TX_SEMODE=0, Ignored TX_SEMODE=1, Drives DPM only. TX_DM_OE=1 to enable drive. DPM=TX_DM"] pub type TX_DM_R = crate::BitReader; -#[doc = "Field `TX_DM` writer - Output data. TX_DIFFMODE=1, Ignored - TX_DIFFMODE=0, Drives DPM only. TX_DM_OE=1 to enable drive. DPM=TX_DM"] +#[doc = "Field `TX_DM` writer - Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller TX_SEMODE=0, Ignored TX_SEMODE=1, Drives DPM only. TX_DM_OE=1 to enable drive. DPM=TX_DM"] pub type TX_DM_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `RX_PD` reader - RX power down override (if override enable is set). 1 = powered down."] +#[doc = "Field `RX_PD` reader - "] pub type RX_PD_R = crate::BitReader; -#[doc = "Field `RX_PD` writer - RX power down override (if override enable is set). 1 = powered down."] +#[doc = "Field `RX_PD` writer - "] pub type RX_PD_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `TX_PD` reader - TX power down override (if override enable is set). 1 = powered down."] +#[doc = "Field `TX_PD` reader - "] pub type TX_PD_R = crate::BitReader; -#[doc = "Field `TX_PD` writer - TX power down override (if override enable is set). 1 = powered down."] +#[doc = "Field `TX_PD` writer - "] pub type TX_PD_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `TX_FSSLEW` reader - TX_FSSLEW=0: Low speed slew rate - TX_FSSLEW=1: Full speed slew rate"] +#[doc = "Field `TX_FSSLEW` reader - "] pub type TX_FSSLEW_R = crate::BitReader; -#[doc = "Field `TX_FSSLEW` writer - TX_FSSLEW=0: Low speed slew rate - TX_FSSLEW=1: Full speed slew rate"] +#[doc = "Field `TX_FSSLEW` writer - "] pub type TX_FSSLEW_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `TX_DIFFMODE` reader - TX_DIFFMODE=0: Single ended mode - TX_DIFFMODE=1: Differential drive mode (TX_DM, TX_DM_OE ignored)"] +#[doc = "Field `TX_DIFFMODE` reader - "] pub type TX_DIFFMODE_R = crate::BitReader; -#[doc = "Field `TX_DIFFMODE` writer - TX_DIFFMODE=0: Single ended mode - TX_DIFFMODE=1: Differential drive mode (TX_DM, TX_DM_OE ignored)"] +#[doc = "Field `TX_DIFFMODE` writer - "] pub type TX_DIFFMODE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `RX_DD` reader - Differential RX"] +#[doc = "Field `RX_DD` reader - Status bit from USB PHY RX Diff data"] pub type RX_DD_R = crate::BitReader; -#[doc = "Field `RX_DP` reader - DPP pin state"] +#[doc = "Field `RX_DP` reader - Status bit from USB PHY DPP pin state"] pub type RX_DP_R = crate::BitReader; -#[doc = "Field `RX_DM` reader - DPM pin state"] +#[doc = "Field `RX_DM` reader - Status bit from USB PHY DPM pin state"] pub type RX_DM_R = crate::BitReader; -#[doc = "Field `DP_OVCN` reader - DP overcurrent"] +#[doc = "Field `DP_OVCN` reader - Status bit from USB PHY"] pub type DP_OVCN_R = crate::BitReader; -#[doc = "Field `DM_OVCN` reader - DM overcurrent"] +#[doc = "Field `DM_OVCN` reader - Status bit from USB PHY"] pub type DM_OVCN_R = crate::BitReader; -#[doc = "Field `DP_OVV` reader - DP over voltage"] +#[doc = "Field `DP_OVV` reader - Status bit from USB PHY"] pub type DP_OVV_R = crate::BitReader; -#[doc = "Field `DM_OVV` reader - DM over voltage"] +#[doc = "Field `DM_OVV` reader - Status bit from USB PHY"] pub type DM_OVV_R = crate::BitReader; impl R { - #[doc = "Bit 0 - Enable the second DP pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2"] + #[doc = "Bit 0 - when dp_pullup_en is set high, this enables second resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2"] #[inline(always)] pub fn dp_pullup_hisel(&self) -> DP_PULLUP_HISEL_R { DP_PULLUP_HISEL_R::new((self.bits & 1) != 0) } - #[doc = "Bit 1 - DP pull up enable"] + #[doc = "Bit 1 - Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller"] #[inline(always)] pub fn dp_pullup_en(&self) -> DP_PULLUP_EN_R { DP_PULLUP_EN_R::new(((self.bits >> 1) & 1) != 0) } - #[doc = "Bit 2 - DP pull down enable"] + #[doc = "Bit 2 - Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller 1 - Enable Rpd on DPP"] #[inline(always)] pub fn dp_pulldn_en(&self) -> DP_PULLDN_EN_R { DP_PULLDN_EN_R::new(((self.bits >> 2) & 1) != 0) } - #[doc = "Bit 4 - Enable the second DM pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2"] + #[doc = "Bit 4 - when dm_pullup_en is set high, this enables second resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2"] #[inline(always)] pub fn dm_pullup_hisel(&self) -> DM_PULLUP_HISEL_R { DM_PULLUP_HISEL_R::new(((self.bits >> 4) & 1) != 0) } - #[doc = "Bit 5 - DM pull up enable"] + #[doc = "Bit 5 - Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller 1 - Enable Rpu on DPM"] #[inline(always)] pub fn dm_pullup_en(&self) -> DM_PULLUP_EN_R { DM_PULLUP_EN_R::new(((self.bits >> 5) & 1) != 0) } - #[doc = "Bit 6 - DM pull down enable"] + #[doc = "Bit 6 - Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller 1 - Enable Rpd on DPM"] #[inline(always)] pub fn dm_pulldn_en(&self) -> DM_PULLDN_EN_R { DM_PULLDN_EN_R::new(((self.bits >> 6) & 1) != 0) } - #[doc = "Bit 8 - Output enable. If TX_DIFFMODE=1, OE for DPP/DPM diff pair. 0 - DPP/DPM in Hi-Z state; 1 - DPP/DPM driving - If TX_DIFFMODE=0, OE for DPP only. 0 - DPP in Hi-Z state; 1 - DPP driving"] + #[doc = "Bit 8 - Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller TX_SEMODE=0, OE for DPP/DPM diff pair. 0 - DPP/DPM in Hi-Z state; 1 - DPP/DPM driving TX_SEMODE=1, OE for DPP only. 0 - DPP in Hi-Z state; 1 - DPP driving"] #[inline(always)] pub fn tx_dp_oe(&self) -> TX_DP_OE_R { TX_DP_OE_R::new(((self.bits >> 8) & 1) != 0) } - #[doc = "Bit 9 - Output enable. If TX_DIFFMODE=1, Ignored. - If TX_DIFFMODE=0, OE for DPM only. 0 - DPM in Hi-Z state; 1 - DPM driving"] + #[doc = "Bit 9 - Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller TX_SEMODE=0, Ignored. TX_SEMODE=1, OE for DPM only. 0 - DPM in Hi-Z state; 1 - DPM driving"] #[inline(always)] pub fn tx_dm_oe(&self) -> TX_DM_OE_R { TX_DM_OE_R::new(((self.bits >> 9) & 1) != 0) } - #[doc = "Bit 10 - Output data. If TX_DIFFMODE=1, Drives DPP/DPM diff pair. TX_DP_OE=1 to enable drive. DPP=TX_DP, DPM=~TX_DP - If TX_DIFFMODE=0, Drives DPP only. TX_DP_OE=1 to enable drive. DPP=TX_DP"] + #[doc = "Bit 10 - Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller TX_SEMODE=0, Drives DPP/DPM diff pair. TX_DP_OE=1 to enable drive. DPP=TX_DP, DPM=~TX_DP TX_SEMODE=1, Drives DPP only. TX_DP_OE=1 to enable drive. DPP=TX_DP"] #[inline(always)] pub fn tx_dp(&self) -> TX_DP_R { TX_DP_R::new(((self.bits >> 10) & 1) != 0) } - #[doc = "Bit 11 - Output data. TX_DIFFMODE=1, Ignored - TX_DIFFMODE=0, Drives DPM only. TX_DM_OE=1 to enable drive. DPM=TX_DM"] + #[doc = "Bit 11 - Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller TX_SEMODE=0, Ignored TX_SEMODE=1, Drives DPM only. TX_DM_OE=1 to enable drive. DPM=TX_DM"] #[inline(always)] pub fn tx_dm(&self) -> TX_DM_R { TX_DM_R::new(((self.bits >> 11) & 1) != 0) } - #[doc = "Bit 12 - RX power down override (if override enable is set). 1 = powered down."] + #[doc = "Bit 12"] #[inline(always)] pub fn rx_pd(&self) -> RX_PD_R { RX_PD_R::new(((self.bits >> 12) & 1) != 0) } - #[doc = "Bit 13 - TX power down override (if override enable is set). 1 = powered down."] + #[doc = "Bit 13"] #[inline(always)] pub fn tx_pd(&self) -> TX_PD_R { TX_PD_R::new(((self.bits >> 13) & 1) != 0) } - #[doc = "Bit 14 - TX_FSSLEW=0: Low speed slew rate - TX_FSSLEW=1: Full speed slew rate"] + #[doc = "Bit 14"] #[inline(always)] pub fn tx_fsslew(&self) -> TX_FSSLEW_R { TX_FSSLEW_R::new(((self.bits >> 14) & 1) != 0) } - #[doc = "Bit 15 - TX_DIFFMODE=0: Single ended mode - TX_DIFFMODE=1: Differential drive mode (TX_DM, TX_DM_OE ignored)"] + #[doc = "Bit 15"] #[inline(always)] pub fn tx_diffmode(&self) -> TX_DIFFMODE_R { TX_DIFFMODE_R::new(((self.bits >> 15) & 1) != 0) } - #[doc = "Bit 16 - Differential RX"] + #[doc = "Bit 16 - Status bit from USB PHY RX Diff data"] #[inline(always)] pub fn rx_dd(&self) -> RX_DD_R { RX_DD_R::new(((self.bits >> 16) & 1) != 0) } - #[doc = "Bit 17 - DPP pin state"] + #[doc = "Bit 17 - Status bit from USB PHY DPP pin state"] #[inline(always)] pub fn rx_dp(&self) -> RX_DP_R { RX_DP_R::new(((self.bits >> 17) & 1) != 0) } - #[doc = "Bit 18 - DPM pin state"] + #[doc = "Bit 18 - Status bit from USB PHY DPM pin state"] #[inline(always)] pub fn rx_dm(&self) -> RX_DM_R { RX_DM_R::new(((self.bits >> 18) & 1) != 0) } - #[doc = "Bit 19 - DP overcurrent"] + #[doc = "Bit 19 - Status bit from USB PHY"] #[inline(always)] pub fn dp_ovcn(&self) -> DP_OVCN_R { DP_OVCN_R::new(((self.bits >> 19) & 1) != 0) } - #[doc = "Bit 20 - DM overcurrent"] + #[doc = "Bit 20 - Status bit from USB PHY"] #[inline(always)] pub fn dm_ovcn(&self) -> DM_OVCN_R { DM_OVCN_R::new(((self.bits >> 20) & 1) != 0) } - #[doc = "Bit 21 - DP over voltage"] + #[doc = "Bit 21 - Status bit from USB PHY"] #[inline(always)] pub fn dp_ovv(&self) -> DP_OVV_R { DP_OVV_R::new(((self.bits >> 21) & 1) != 0) } - #[doc = "Bit 22 - DM over voltage"] + #[doc = "Bit 22 - Status bit from USB PHY"] #[inline(always)] pub fn dm_ovv(&self) -> DM_OVV_R { DM_OVV_R::new(((self.bits >> 22) & 1) != 0) } } impl W { - #[doc = "Bit 0 - Enable the second DP pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2"] + #[doc = "Bit 0 - when dp_pullup_en is set high, this enables second resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2"] #[inline(always)] #[must_use] pub fn dp_pullup_hisel(&mut self) -> DP_PULLUP_HISEL_W { DP_PULLUP_HISEL_W::new(self, 0) } - #[doc = "Bit 1 - DP pull up enable"] + #[doc = "Bit 1 - Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller"] #[inline(always)] #[must_use] pub fn dp_pullup_en(&mut self) -> DP_PULLUP_EN_W { DP_PULLUP_EN_W::new(self, 1) } - #[doc = "Bit 2 - DP pull down enable"] + #[doc = "Bit 2 - Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller 1 - Enable Rpd on DPP"] #[inline(always)] #[must_use] pub fn dp_pulldn_en(&mut self) -> DP_PULLDN_EN_W { DP_PULLDN_EN_W::new(self, 2) } - #[doc = "Bit 4 - Enable the second DM pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2"] + #[doc = "Bit 4 - when dm_pullup_en is set high, this enables second resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2"] #[inline(always)] #[must_use] pub fn dm_pullup_hisel(&mut self) -> DM_PULLUP_HISEL_W { DM_PULLUP_HISEL_W::new(self, 4) } - #[doc = "Bit 5 - DM pull up enable"] + #[doc = "Bit 5 - Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller 1 - Enable Rpu on DPM"] #[inline(always)] #[must_use] pub fn dm_pullup_en(&mut self) -> DM_PULLUP_EN_W { DM_PULLUP_EN_W::new(self, 5) } - #[doc = "Bit 6 - DM pull down enable"] + #[doc = "Bit 6 - Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller 1 - Enable Rpd on DPM"] #[inline(always)] #[must_use] pub fn dm_pulldn_en(&mut self) -> DM_PULLDN_EN_W { DM_PULLDN_EN_W::new(self, 6) } - #[doc = "Bit 8 - Output enable. If TX_DIFFMODE=1, OE for DPP/DPM diff pair. 0 - DPP/DPM in Hi-Z state; 1 - DPP/DPM driving - If TX_DIFFMODE=0, OE for DPP only. 0 - DPP in Hi-Z state; 1 - DPP driving"] + #[doc = "Bit 8 - Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller TX_SEMODE=0, OE for DPP/DPM diff pair. 0 - DPP/DPM in Hi-Z state; 1 - DPP/DPM driving TX_SEMODE=1, OE for DPP only. 0 - DPP in Hi-Z state; 1 - DPP driving"] #[inline(always)] #[must_use] pub fn tx_dp_oe(&mut self) -> TX_DP_OE_W { TX_DP_OE_W::new(self, 8) } - #[doc = "Bit 9 - Output enable. If TX_DIFFMODE=1, Ignored. - If TX_DIFFMODE=0, OE for DPM only. 0 - DPM in Hi-Z state; 1 - DPM driving"] + #[doc = "Bit 9 - Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller TX_SEMODE=0, Ignored. TX_SEMODE=1, OE for DPM only. 0 - DPM in Hi-Z state; 1 - DPM driving"] #[inline(always)] #[must_use] pub fn tx_dm_oe(&mut self) -> TX_DM_OE_W { TX_DM_OE_W::new(self, 9) } - #[doc = "Bit 10 - Output data. If TX_DIFFMODE=1, Drives DPP/DPM diff pair. TX_DP_OE=1 to enable drive. DPP=TX_DP, DPM=~TX_DP - If TX_DIFFMODE=0, Drives DPP only. TX_DP_OE=1 to enable drive. DPP=TX_DP"] + #[doc = "Bit 10 - Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller TX_SEMODE=0, Drives DPP/DPM diff pair. TX_DP_OE=1 to enable drive. DPP=TX_DP, DPM=~TX_DP TX_SEMODE=1, Drives DPP only. TX_DP_OE=1 to enable drive. DPP=TX_DP"] #[inline(always)] #[must_use] pub fn tx_dp(&mut self) -> TX_DP_W { TX_DP_W::new(self, 10) } - #[doc = "Bit 11 - Output data. TX_DIFFMODE=1, Ignored - TX_DIFFMODE=0, Drives DPM only. TX_DM_OE=1 to enable drive. DPM=TX_DM"] + #[doc = "Bit 11 - Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller TX_SEMODE=0, Ignored TX_SEMODE=1, Drives DPM only. TX_DM_OE=1 to enable drive. DPM=TX_DM"] #[inline(always)] #[must_use] pub fn tx_dm(&mut self) -> TX_DM_W { TX_DM_W::new(self, 11) } - #[doc = "Bit 12 - RX power down override (if override enable is set). 1 = powered down."] + #[doc = "Bit 12"] #[inline(always)] #[must_use] pub fn rx_pd(&mut self) -> RX_PD_W { RX_PD_W::new(self, 12) } - #[doc = "Bit 13 - TX power down override (if override enable is set). 1 = powered down."] + #[doc = "Bit 13"] #[inline(always)] #[must_use] pub fn tx_pd(&mut self) -> TX_PD_W { TX_PD_W::new(self, 13) } - #[doc = "Bit 14 - TX_FSSLEW=0: Low speed slew rate - TX_FSSLEW=1: Full speed slew rate"] + #[doc = "Bit 14"] #[inline(always)] #[must_use] pub fn tx_fsslew(&mut self) -> TX_FSSLEW_W { TX_FSSLEW_W::new(self, 14) } - #[doc = "Bit 15 - TX_DIFFMODE=0: Single ended mode - TX_DIFFMODE=1: Differential drive mode (TX_DM, TX_DM_OE ignored)"] + #[doc = "Bit 15"] #[inline(always)] #[must_use] pub fn tx_diffmode(&mut self) -> TX_DIFFMODE_W { TX_DIFFMODE_W::new(self, 15) } } -#[doc = "This register allows for direct control of the USB phy. Use in conjunction with usbphy_direct_override register to enable each override bit. +#[doc = "Note that most functions are driven directly from usb_fsls controller. This register allows more detailed control/status from the USB PHY. Useful for debug but not expected to be used in normal operation Use in conjunction with usbphy_direct_override register You can [`read`](crate::generic::Reg::read) this register and get [`usbphy_direct::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usbphy_direct::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct USBPHY_DIRECT_SPEC; diff --git a/src/usbctrl_regs/usbphy_direct_override.rs b/src/usbctrl_regs/usbphy_direct_override.rs index f0e4ede99..bc53b1cb4 100644 --- a/src/usbctrl_regs/usbphy_direct_override.rs +++ b/src/usbctrl_regs/usbphy_direct_override.rs @@ -10,33 +10,33 @@ pub type DP_PULLUP_HISEL_OVERRIDE_EN_W<'a, REG> = crate::BitWriter<'a, REG>; pub type DM_PULLUP_HISEL_OVERRIDE_EN_R = crate::BitReader; #[doc = "Field `DM_PULLUP_HISEL_OVERRIDE_EN` writer - "] pub type DM_PULLUP_HISEL_OVERRIDE_EN_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `DP_PULLUP_EN_OVERRIDE_EN` reader - "] +#[doc = "Field `DP_PULLUP_EN_OVERRIDE_EN` reader - Override default value or value driven from USB Controller to PHY"] pub type DP_PULLUP_EN_OVERRIDE_EN_R = crate::BitReader; -#[doc = "Field `DP_PULLUP_EN_OVERRIDE_EN` writer - "] +#[doc = "Field `DP_PULLUP_EN_OVERRIDE_EN` writer - Override default value or value driven from USB Controller to PHY"] pub type DP_PULLUP_EN_OVERRIDE_EN_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `DP_PULLDN_EN_OVERRIDE_EN` reader - "] +#[doc = "Field `DP_PULLDN_EN_OVERRIDE_EN` reader - Override default value or value driven from USB Controller to PHY"] pub type DP_PULLDN_EN_OVERRIDE_EN_R = crate::BitReader; -#[doc = "Field `DP_PULLDN_EN_OVERRIDE_EN` writer - "] +#[doc = "Field `DP_PULLDN_EN_OVERRIDE_EN` writer - Override default value or value driven from USB Controller to PHY"] pub type DP_PULLDN_EN_OVERRIDE_EN_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `DM_PULLDN_EN_OVERRIDE_EN` reader - "] +#[doc = "Field `DM_PULLDN_EN_OVERRIDE_EN` reader - Override default value or value driven from USB Controller to PHY"] pub type DM_PULLDN_EN_OVERRIDE_EN_R = crate::BitReader; -#[doc = "Field `DM_PULLDN_EN_OVERRIDE_EN` writer - "] +#[doc = "Field `DM_PULLDN_EN_OVERRIDE_EN` writer - Override default value or value driven from USB Controller to PHY"] pub type DM_PULLDN_EN_OVERRIDE_EN_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `TX_DP_OE_OVERRIDE_EN` reader - "] +#[doc = "Field `TX_DP_OE_OVERRIDE_EN` reader - Override default value or value driven from USB Controller to PHY"] pub type TX_DP_OE_OVERRIDE_EN_R = crate::BitReader; -#[doc = "Field `TX_DP_OE_OVERRIDE_EN` writer - "] +#[doc = "Field `TX_DP_OE_OVERRIDE_EN` writer - Override default value or value driven from USB Controller to PHY"] pub type TX_DP_OE_OVERRIDE_EN_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `TX_DM_OE_OVERRIDE_EN` reader - "] +#[doc = "Field `TX_DM_OE_OVERRIDE_EN` reader - Override default value or value driven from USB Controller to PHY"] pub type TX_DM_OE_OVERRIDE_EN_R = crate::BitReader; -#[doc = "Field `TX_DM_OE_OVERRIDE_EN` writer - "] +#[doc = "Field `TX_DM_OE_OVERRIDE_EN` writer - Override default value or value driven from USB Controller to PHY"] pub type TX_DM_OE_OVERRIDE_EN_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `TX_DP_OVERRIDE_EN` reader - "] +#[doc = "Field `TX_DP_OVERRIDE_EN` reader - Override default value or value driven from USB Controller to PHY"] pub type TX_DP_OVERRIDE_EN_R = crate::BitReader; -#[doc = "Field `TX_DP_OVERRIDE_EN` writer - "] +#[doc = "Field `TX_DP_OVERRIDE_EN` writer - Override default value or value driven from USB Controller to PHY"] pub type TX_DP_OVERRIDE_EN_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `TX_DM_OVERRIDE_EN` reader - "] +#[doc = "Field `TX_DM_OVERRIDE_EN` reader - Override default value or value driven from USB Controller to PHY"] pub type TX_DM_OVERRIDE_EN_R = crate::BitReader; -#[doc = "Field `TX_DM_OVERRIDE_EN` writer - "] +#[doc = "Field `TX_DM_OVERRIDE_EN` writer - Override default value or value driven from USB Controller to PHY"] pub type TX_DM_OVERRIDE_EN_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `RX_PD_OVERRIDE_EN` reader - "] pub type RX_PD_OVERRIDE_EN_R = crate::BitReader; @@ -69,37 +69,37 @@ impl R { pub fn dm_pullup_hisel_override_en(&self) -> DM_PULLUP_HISEL_OVERRIDE_EN_R { DM_PULLUP_HISEL_OVERRIDE_EN_R::new(((self.bits >> 1) & 1) != 0) } - #[doc = "Bit 2"] + #[doc = "Bit 2 - Override default value or value driven from USB Controller to PHY"] #[inline(always)] pub fn dp_pullup_en_override_en(&self) -> DP_PULLUP_EN_OVERRIDE_EN_R { DP_PULLUP_EN_OVERRIDE_EN_R::new(((self.bits >> 2) & 1) != 0) } - #[doc = "Bit 3"] + #[doc = "Bit 3 - Override default value or value driven from USB Controller to PHY"] #[inline(always)] pub fn dp_pulldn_en_override_en(&self) -> DP_PULLDN_EN_OVERRIDE_EN_R { DP_PULLDN_EN_OVERRIDE_EN_R::new(((self.bits >> 3) & 1) != 0) } - #[doc = "Bit 4"] + #[doc = "Bit 4 - Override default value or value driven from USB Controller to PHY"] #[inline(always)] pub fn dm_pulldn_en_override_en(&self) -> DM_PULLDN_EN_OVERRIDE_EN_R { DM_PULLDN_EN_OVERRIDE_EN_R::new(((self.bits >> 4) & 1) != 0) } - #[doc = "Bit 5"] + #[doc = "Bit 5 - Override default value or value driven from USB Controller to PHY"] #[inline(always)] pub fn tx_dp_oe_override_en(&self) -> TX_DP_OE_OVERRIDE_EN_R { TX_DP_OE_OVERRIDE_EN_R::new(((self.bits >> 5) & 1) != 0) } - #[doc = "Bit 6"] + #[doc = "Bit 6 - Override default value or value driven from USB Controller to PHY"] #[inline(always)] pub fn tx_dm_oe_override_en(&self) -> TX_DM_OE_OVERRIDE_EN_R { TX_DM_OE_OVERRIDE_EN_R::new(((self.bits >> 6) & 1) != 0) } - #[doc = "Bit 7"] + #[doc = "Bit 7 - Override default value or value driven from USB Controller to PHY"] #[inline(always)] pub fn tx_dp_override_en(&self) -> TX_DP_OVERRIDE_EN_R { TX_DP_OVERRIDE_EN_R::new(((self.bits >> 7) & 1) != 0) } - #[doc = "Bit 8"] + #[doc = "Bit 8 - Override default value or value driven from USB Controller to PHY"] #[inline(always)] pub fn tx_dm_override_en(&self) -> TX_DM_OVERRIDE_EN_R { TX_DM_OVERRIDE_EN_R::new(((self.bits >> 8) & 1) != 0) @@ -147,7 +147,7 @@ impl W { ) -> DM_PULLUP_HISEL_OVERRIDE_EN_W { DM_PULLUP_HISEL_OVERRIDE_EN_W::new(self, 1) } - #[doc = "Bit 2"] + #[doc = "Bit 2 - Override default value or value driven from USB Controller to PHY"] #[inline(always)] #[must_use] pub fn dp_pullup_en_override_en( @@ -155,7 +155,7 @@ impl W { ) -> DP_PULLUP_EN_OVERRIDE_EN_W { DP_PULLUP_EN_OVERRIDE_EN_W::new(self, 2) } - #[doc = "Bit 3"] + #[doc = "Bit 3 - Override default value or value driven from USB Controller to PHY"] #[inline(always)] #[must_use] pub fn dp_pulldn_en_override_en( @@ -163,7 +163,7 @@ impl W { ) -> DP_PULLDN_EN_OVERRIDE_EN_W { DP_PULLDN_EN_OVERRIDE_EN_W::new(self, 3) } - #[doc = "Bit 4"] + #[doc = "Bit 4 - Override default value or value driven from USB Controller to PHY"] #[inline(always)] #[must_use] pub fn dm_pulldn_en_override_en( @@ -171,25 +171,25 @@ impl W { ) -> DM_PULLDN_EN_OVERRIDE_EN_W { DM_PULLDN_EN_OVERRIDE_EN_W::new(self, 4) } - #[doc = "Bit 5"] + #[doc = "Bit 5 - Override default value or value driven from USB Controller to PHY"] #[inline(always)] #[must_use] pub fn tx_dp_oe_override_en(&mut self) -> TX_DP_OE_OVERRIDE_EN_W { TX_DP_OE_OVERRIDE_EN_W::new(self, 5) } - #[doc = "Bit 6"] + #[doc = "Bit 6 - Override default value or value driven from USB Controller to PHY"] #[inline(always)] #[must_use] pub fn tx_dm_oe_override_en(&mut self) -> TX_DM_OE_OVERRIDE_EN_W { TX_DM_OE_OVERRIDE_EN_W::new(self, 6) } - #[doc = "Bit 7"] + #[doc = "Bit 7 - Override default value or value driven from USB Controller to PHY"] #[inline(always)] #[must_use] pub fn tx_dp_override_en(&mut self) -> TX_DP_OVERRIDE_EN_W { TX_DP_OVERRIDE_EN_W::new(self, 7) } - #[doc = "Bit 8"] + #[doc = "Bit 8 - Override default value or value driven from USB Controller to PHY"] #[inline(always)] #[must_use] pub fn tx_dm_override_en(&mut self) -> TX_DM_OVERRIDE_EN_W { @@ -232,7 +232,7 @@ impl W { TX_DIFFMODE_OVERRIDE_EN_W::new(self, 15) } } -#[doc = "Override enable for each control in usbphy_direct +#[doc = " You can [`read`](crate::generic::Reg::read) this register and get [`usbphy_direct_override::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usbphy_direct_override::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct USBPHY_DIRECT_OVERRIDE_SPEC; diff --git a/src/usbctrl_regs/usbphy_trim.rs b/src/usbctrl_regs/usbphy_trim.rs index 072f3d20d..e0cc0a1ed 100644 --- a/src/usbctrl_regs/usbphy_trim.rs +++ b/src/usbctrl_regs/usbphy_trim.rs @@ -2,57 +2,41 @@ pub type R = crate::R; #[doc = "Register `USBPHY_TRIM` writer"] pub type W = crate::W; -#[doc = "Field `DP_PULLDN_TRIM` reader - Value to drive to USB PHY - DP pulldown resistor trim control - Experimental data suggests that the reset value will work, but this register allows adjustment if required"] +#[doc = "Field `DP_PULLDN_TRIM` reader - Value to drive to USB PHY DP pulldown resistor trim control Experimental data suggests that the reset value will work, but this register allows adjustment if required"] pub type DP_PULLDN_TRIM_R = crate::FieldReader; -#[doc = "Field `DP_PULLDN_TRIM` writer - Value to drive to USB PHY - DP pulldown resistor trim control - Experimental data suggests that the reset value will work, but this register allows adjustment if required"] +#[doc = "Field `DP_PULLDN_TRIM` writer - Value to drive to USB PHY DP pulldown resistor trim control Experimental data suggests that the reset value will work, but this register allows adjustment if required"] pub type DP_PULLDN_TRIM_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; -#[doc = "Field `DM_PULLDN_TRIM` reader - Value to drive to USB PHY - DM pulldown resistor trim control - Experimental data suggests that the reset value will work, but this register allows adjustment if required"] +#[doc = "Field `DM_PULLDN_TRIM` reader - Value to drive to USB PHY DM pulldown resistor trim control Experimental data suggests that the reset value will work, but this register allows adjustment if required"] pub type DM_PULLDN_TRIM_R = crate::FieldReader; -#[doc = "Field `DM_PULLDN_TRIM` writer - Value to drive to USB PHY - DM pulldown resistor trim control - Experimental data suggests that the reset value will work, but this register allows adjustment if required"] +#[doc = "Field `DM_PULLDN_TRIM` writer - Value to drive to USB PHY DM pulldown resistor trim control Experimental data suggests that the reset value will work, but this register allows adjustment if required"] pub type DM_PULLDN_TRIM_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; impl R { - #[doc = "Bits 0:4 - Value to drive to USB PHY - DP pulldown resistor trim control - Experimental data suggests that the reset value will work, but this register allows adjustment if required"] + #[doc = "Bits 0:4 - Value to drive to USB PHY DP pulldown resistor trim control Experimental data suggests that the reset value will work, but this register allows adjustment if required"] #[inline(always)] pub fn dp_pulldn_trim(&self) -> DP_PULLDN_TRIM_R { DP_PULLDN_TRIM_R::new((self.bits & 0x1f) as u8) } - #[doc = "Bits 8:12 - Value to drive to USB PHY - DM pulldown resistor trim control - Experimental data suggests that the reset value will work, but this register allows adjustment if required"] + #[doc = "Bits 8:12 - Value to drive to USB PHY DM pulldown resistor trim control Experimental data suggests that the reset value will work, but this register allows adjustment if required"] #[inline(always)] pub fn dm_pulldn_trim(&self) -> DM_PULLDN_TRIM_R { DM_PULLDN_TRIM_R::new(((self.bits >> 8) & 0x1f) as u8) } } impl W { - #[doc = "Bits 0:4 - Value to drive to USB PHY - DP pulldown resistor trim control - Experimental data suggests that the reset value will work, but this register allows adjustment if required"] + #[doc = "Bits 0:4 - Value to drive to USB PHY DP pulldown resistor trim control Experimental data suggests that the reset value will work, but this register allows adjustment if required"] #[inline(always)] #[must_use] pub fn dp_pulldn_trim(&mut self) -> DP_PULLDN_TRIM_W { DP_PULLDN_TRIM_W::new(self, 0) } - #[doc = "Bits 8:12 - Value to drive to USB PHY - DM pulldown resistor trim control - Experimental data suggests that the reset value will work, but this register allows adjustment if required"] + #[doc = "Bits 8:12 - Value to drive to USB PHY DM pulldown resistor trim control Experimental data suggests that the reset value will work, but this register allows adjustment if required"] #[inline(always)] #[must_use] pub fn dm_pulldn_trim(&mut self) -> DM_PULLDN_TRIM_W { DM_PULLDN_TRIM_W::new(self, 8) } } -#[doc = "Used to adjust trim values of USB phy pull down resistors. +#[doc = "Note that most functions are driven directly from usb_fsls controller. This register allows more detailed control/status from the USB PHY. Useful for debug but not expected to be used in normal operation You can [`read`](crate::generic::Reg::read) this register and get [`usbphy_trim::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usbphy_trim::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct USBPHY_TRIM_SPEC; diff --git a/src/vreg_and_chip_reset/bod.rs b/src/vreg_and_chip_reset/bod.rs index ca8451f8e..61fc0951a 100644 --- a/src/vreg_and_chip_reset/bod.rs +++ b/src/vreg_and_chip_reset/bod.rs @@ -2,102 +2,34 @@ pub type R = crate::R; #[doc = "Register `BOD` writer"] pub type W = crate::W; -#[doc = "Field `EN` reader - enable - 0=not enabled, 1=enabled"] +#[doc = "Field `EN` reader - enable 0=not enabled, 1=enabled"] pub type EN_R = crate::BitReader; -#[doc = "Field `EN` writer - enable - 0=not enabled, 1=enabled"] +#[doc = "Field `EN` writer - enable 0=not enabled, 1=enabled"] pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `VSEL` reader - threshold select - 0000 - 0.473V - 0001 - 0.516V - 0010 - 0.559V - 0011 - 0.602V - 0100 - 0.645V - 0101 - 0.688V - 0110 - 0.731V - 0111 - 0.774V - 1000 - 0.817V - 1001 - 0.860V (default) - 1010 - 0.903V - 1011 - 0.946V - 1100 - 0.989V - 1101 - 1.032V - 1110 - 1.075V - 1111 - 1.118V"] +#[doc = "Field `VSEL` reader - threshold select 0000 - 0.473V 0001 - 0.516V 0010 - 0.559V 0011 - 0.602V 0100 - 0.645V 0101 - 0.688V 0110 - 0.731V 0111 - 0.774V 1000 - 0.817V 1001 - 0.860V (default) 1010 - 0.903V 1011 - 0.946V 1100 - 0.989V 1101 - 1.032V 1110 - 1.075V 1111 - 1.118V"] pub type VSEL_R = crate::FieldReader; -#[doc = "Field `VSEL` writer - threshold select - 0000 - 0.473V - 0001 - 0.516V - 0010 - 0.559V - 0011 - 0.602V - 0100 - 0.645V - 0101 - 0.688V - 0110 - 0.731V - 0111 - 0.774V - 1000 - 0.817V - 1001 - 0.860V (default) - 1010 - 0.903V - 1011 - 0.946V - 1100 - 0.989V - 1101 - 1.032V - 1110 - 1.075V - 1111 - 1.118V"] +#[doc = "Field `VSEL` writer - threshold select 0000 - 0.473V 0001 - 0.516V 0010 - 0.559V 0011 - 0.602V 0100 - 0.645V 0101 - 0.688V 0110 - 0.731V 0111 - 0.774V 1000 - 0.817V 1001 - 0.860V (default) 1010 - 0.903V 1011 - 0.946V 1100 - 0.989V 1101 - 1.032V 1110 - 1.075V 1111 - 1.118V"] pub type VSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; impl R { - #[doc = "Bit 0 - enable - 0=not enabled, 1=enabled"] + #[doc = "Bit 0 - enable 0=not enabled, 1=enabled"] #[inline(always)] pub fn en(&self) -> EN_R { EN_R::new((self.bits & 1) != 0) } - #[doc = "Bits 4:7 - threshold select - 0000 - 0.473V - 0001 - 0.516V - 0010 - 0.559V - 0011 - 0.602V - 0100 - 0.645V - 0101 - 0.688V - 0110 - 0.731V - 0111 - 0.774V - 1000 - 0.817V - 1001 - 0.860V (default) - 1010 - 0.903V - 1011 - 0.946V - 1100 - 0.989V - 1101 - 1.032V - 1110 - 1.075V - 1111 - 1.118V"] + #[doc = "Bits 4:7 - threshold select 0000 - 0.473V 0001 - 0.516V 0010 - 0.559V 0011 - 0.602V 0100 - 0.645V 0101 - 0.688V 0110 - 0.731V 0111 - 0.774V 1000 - 0.817V 1001 - 0.860V (default) 1010 - 0.903V 1011 - 0.946V 1100 - 0.989V 1101 - 1.032V 1110 - 1.075V 1111 - 1.118V"] #[inline(always)] pub fn vsel(&self) -> VSEL_R { VSEL_R::new(((self.bits >> 4) & 0x0f) as u8) } } impl W { - #[doc = "Bit 0 - enable - 0=not enabled, 1=enabled"] + #[doc = "Bit 0 - enable 0=not enabled, 1=enabled"] #[inline(always)] #[must_use] pub fn en(&mut self) -> EN_W { EN_W::new(self, 0) } - #[doc = "Bits 4:7 - threshold select - 0000 - 0.473V - 0001 - 0.516V - 0010 - 0.559V - 0011 - 0.602V - 0100 - 0.645V - 0101 - 0.688V - 0110 - 0.731V - 0111 - 0.774V - 1000 - 0.817V - 1001 - 0.860V (default) - 1010 - 0.903V - 1011 - 0.946V - 1100 - 0.989V - 1101 - 1.032V - 1110 - 1.075V - 1111 - 1.118V"] + #[doc = "Bits 4:7 - threshold select 0000 - 0.473V 0001 - 0.516V 0010 - 0.559V 0011 - 0.602V 0100 - 0.645V 0101 - 0.688V 0110 - 0.731V 0111 - 0.774V 1000 - 0.817V 1001 - 0.860V (default) 1010 - 0.903V 1011 - 0.946V 1100 - 0.989V 1101 - 1.032V 1110 - 1.075V 1111 - 1.118V"] #[inline(always)] #[must_use] pub fn vsel(&mut self) -> VSEL_W { diff --git a/src/vreg_and_chip_reset/chip_reset.rs b/src/vreg_and_chip_reset/chip_reset.rs index f8d0ef6f2..541fd0f7d 100644 --- a/src/vreg_and_chip_reset/chip_reset.rs +++ b/src/vreg_and_chip_reset/chip_reset.rs @@ -8,13 +8,9 @@ pub type HAD_POR_R = crate::BitReader; pub type HAD_RUN_R = crate::BitReader; #[doc = "Field `HAD_PSM_RESTART` reader - Last reset was from the debug port"] pub type HAD_PSM_RESTART_R = crate::BitReader; -#[doc = "Field `PSM_RESTART_FLAG` reader - This is set by psm_restart from the debugger. - Its purpose is to branch bootcode to a safe mode when the debugger has issued a psm_restart in order to recover from a boot lock-up. - In the safe mode the debugger can repair the boot code, clear this flag then reboot the processor."] +#[doc = "Field `PSM_RESTART_FLAG` reader - This is set by psm_restart from the debugger. Its purpose is to branch bootcode to a safe mode when the debugger has issued a psm_restart in order to recover from a boot lock-up. In the safe mode the debugger can repair the boot code, clear this flag then reboot the processor."] pub type PSM_RESTART_FLAG_R = crate::BitReader; -#[doc = "Field `PSM_RESTART_FLAG` writer - This is set by psm_restart from the debugger. - Its purpose is to branch bootcode to a safe mode when the debugger has issued a psm_restart in order to recover from a boot lock-up. - In the safe mode the debugger can repair the boot code, clear this flag then reboot the processor."] +#[doc = "Field `PSM_RESTART_FLAG` writer - This is set by psm_restart from the debugger. Its purpose is to branch bootcode to a safe mode when the debugger has issued a psm_restart in order to recover from a boot lock-up. In the safe mode the debugger can repair the boot code, clear this flag then reboot the processor."] pub type PSM_RESTART_FLAG_W<'a, REG> = crate::BitWriter1C<'a, REG>; impl R { #[doc = "Bit 8 - Last reset was from the power-on reset or brown-out detection blocks"] @@ -32,18 +28,14 @@ impl R { pub fn had_psm_restart(&self) -> HAD_PSM_RESTART_R { HAD_PSM_RESTART_R::new(((self.bits >> 20) & 1) != 0) } - #[doc = "Bit 24 - This is set by psm_restart from the debugger. - Its purpose is to branch bootcode to a safe mode when the debugger has issued a psm_restart in order to recover from a boot lock-up. - In the safe mode the debugger can repair the boot code, clear this flag then reboot the processor."] + #[doc = "Bit 24 - This is set by psm_restart from the debugger. Its purpose is to branch bootcode to a safe mode when the debugger has issued a psm_restart in order to recover from a boot lock-up. In the safe mode the debugger can repair the boot code, clear this flag then reboot the processor."] #[inline(always)] pub fn psm_restart_flag(&self) -> PSM_RESTART_FLAG_R { PSM_RESTART_FLAG_R::new(((self.bits >> 24) & 1) != 0) } } impl W { - #[doc = "Bit 24 - This is set by psm_restart from the debugger. - Its purpose is to branch bootcode to a safe mode when the debugger has issued a psm_restart in order to recover from a boot lock-up. - In the safe mode the debugger can repair the boot code, clear this flag then reboot the processor."] + #[doc = "Bit 24 - This is set by psm_restart from the debugger. Its purpose is to branch bootcode to a safe mode when the debugger has issued a psm_restart in order to recover from a boot lock-up. In the safe mode the debugger can repair the boot code, clear this flag then reboot the processor."] #[inline(always)] #[must_use] pub fn psm_restart_flag(&mut self) -> PSM_RESTART_FLAG_W { diff --git a/src/vreg_and_chip_reset/vreg.rs b/src/vreg_and_chip_reset/vreg.rs index fe1362f68..deeed29ef 100644 --- a/src/vreg_and_chip_reset/vreg.rs +++ b/src/vreg_and_chip_reset/vreg.rs @@ -2,17 +2,13 @@ pub type R = crate::R; #[doc = "Register `VREG` writer"] pub type W = crate::W; -#[doc = "Field `EN` reader - enable - 0=not enabled, 1=enabled"] +#[doc = "Field `EN` reader - enable 0=not enabled, 1=enabled"] pub type EN_R = crate::BitReader; -#[doc = "Field `EN` writer - enable - 0=not enabled, 1=enabled"] +#[doc = "Field `EN` writer - enable 0=not enabled, 1=enabled"] pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `HIZ` reader - high impedance mode select - 0=not in high impedance mode, 1=in high impedance mode"] +#[doc = "Field `HIZ` reader - high impedance mode select 0=not in high impedance mode, 1=in high impedance mode"] pub type HIZ_R = crate::BitReader; -#[doc = "Field `HIZ` writer - high impedance mode select - 0=not in high impedance mode, 1=in high impedance mode"] +#[doc = "Field `HIZ` writer - high impedance mode select 0=not in high impedance mode, 1=in high impedance mode"] pub type HIZ_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Output voltage select for on-chip voltage regulator. @@ -192,18 +188,15 @@ where self.variant(VSEL_A::VOLTAGE1_30) } } -#[doc = "Field `ROK` reader - regulation status - 0=not in regulation, 1=in regulation"] +#[doc = "Field `ROK` reader - regulation status 0=not in regulation, 1=in regulation"] pub type ROK_R = crate::BitReader; impl R { - #[doc = "Bit 0 - enable - 0=not enabled, 1=enabled"] + #[doc = "Bit 0 - enable 0=not enabled, 1=enabled"] #[inline(always)] pub fn en(&self) -> EN_R { EN_R::new((self.bits & 1) != 0) } - #[doc = "Bit 1 - high impedance mode select - 0=not in high impedance mode, 1=in high impedance mode"] + #[doc = "Bit 1 - high impedance mode select 0=not in high impedance mode, 1=in high impedance mode"] #[inline(always)] pub fn hiz(&self) -> HIZ_R { HIZ_R::new(((self.bits >> 1) & 1) != 0) @@ -213,23 +206,20 @@ impl R { pub fn vsel(&self) -> VSEL_R { VSEL_R::new(((self.bits >> 4) & 0x0f) as u8) } - #[doc = "Bit 12 - regulation status - 0=not in regulation, 1=in regulation"] + #[doc = "Bit 12 - regulation status 0=not in regulation, 1=in regulation"] #[inline(always)] pub fn rok(&self) -> ROK_R { ROK_R::new(((self.bits >> 12) & 1) != 0) } } impl W { - #[doc = "Bit 0 - enable - 0=not enabled, 1=enabled"] + #[doc = "Bit 0 - enable 0=not enabled, 1=enabled"] #[inline(always)] #[must_use] pub fn en(&mut self) -> EN_W { EN_W::new(self, 0) } - #[doc = "Bit 1 - high impedance mode select - 0=not in high impedance mode, 1=in high impedance mode"] + #[doc = "Bit 1 - high impedance mode select 0=not in high impedance mode, 1=in high impedance mode"] #[inline(always)] #[must_use] pub fn hiz(&mut self) -> HIZ_W { diff --git a/src/watchdog.rs b/src/watchdog.rs index 1be794984..9b57f3e92 100644 --- a/src/watchdog.rs +++ b/src/watchdog.rs @@ -15,9 +15,7 @@ pub struct RegisterBlock { tick: TICK, } impl RegisterBlock { - #[doc = "0x00 - Watchdog control - The rst_wdsel register determines which subsystems are reset when the watchdog is triggered. - The watchdog can be triggered in software."] + #[doc = "0x00 - Watchdog control The rst_wdsel register determines which subsystems are reset when the watchdog is triggered. The watchdog can be triggered in software."] #[inline(always)] pub const fn ctrl(&self) -> &CTRL { &self.ctrl @@ -78,31 +76,27 @@ impl RegisterBlock { &self.tick } } -#[doc = "CTRL (rw) register accessor: Watchdog control - The rst_wdsel register determines which subsystems are reset when the watchdog is triggered. - The watchdog can be triggered in software. +#[doc = "CTRL (rw) register accessor: Watchdog control The rst_wdsel register determines which subsystems are reset when the watchdog is triggered. The watchdog can be triggered in software. You can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@ctrl`] module"] pub type CTRL = crate::Reg; -#[doc = "Watchdog control - The rst_wdsel register determines which subsystems are reset when the watchdog is triggered. - The watchdog can be triggered in software."] +#[doc = "Watchdog control The rst_wdsel register determines which subsystems are reset when the watchdog is triggered. The watchdog can be triggered in software."] pub mod ctrl; -#[doc = "LOAD (w) register accessor: Load the watchdog timer. The maximum setting is 0xffffff which corresponds to 0xffffff / 2 ticks before triggering a watchdog reset (see errata RP2040-E1). +#[doc = "LOAD (rw) register accessor: Load the watchdog timer. The maximum setting is 0xffffff which corresponds to 0xffffff / 2 ticks before triggering a watchdog reset (see errata RP2040-E1). -You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`load::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`load::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`load::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@load`] module"] pub type LOAD = crate::Reg; #[doc = "Load the watchdog timer. The maximum setting is 0xffffff which corresponds to 0xffffff / 2 ticks before triggering a watchdog reset (see errata RP2040-E1)."] pub mod load; -#[doc = "REASON (r) register accessor: Logs the reason for the last reset. Both bits are zero for the case of a hardware reset. +#[doc = "REASON (rw) register accessor: Logs the reason for the last reset. Both bits are zero for the case of a hardware reset. -You can [`read`](crate::generic::Reg::read) this register and get [`reason::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`reason::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`reason::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@reason`] module"] diff --git a/src/watchdog/ctrl.rs b/src/watchdog/ctrl.rs index 001919eca..192542bc2 100644 --- a/src/watchdog/ctrl.rs +++ b/src/watchdog/ctrl.rs @@ -20,8 +20,6 @@ pub type PAUSE_DBG1_W<'a, REG> = crate::BitWriter<'a, REG>; pub type ENABLE_R = crate::BitReader; #[doc = "Field `ENABLE` writer - When not enabled the watchdog timer is paused"] pub type ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `TRIGGER` reader - Trigger a watchdog reset"] -pub type TRIGGER_R = crate::BitReader; #[doc = "Field `TRIGGER` writer - Trigger a watchdog reset"] pub type TRIGGER_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { @@ -50,11 +48,6 @@ impl R { pub fn enable(&self) -> ENABLE_R { ENABLE_R::new(((self.bits >> 30) & 1) != 0) } - #[doc = "Bit 31 - Trigger a watchdog reset"] - #[inline(always)] - pub fn trigger(&self) -> TRIGGER_R { - TRIGGER_R::new(((self.bits >> 31) & 1) != 0) - } } impl W { #[doc = "Bit 24 - Pause the watchdog timer when JTAG is accessing the bus fabric"] @@ -88,9 +81,7 @@ impl W { TRIGGER_W::new(self, 31) } } -#[doc = "Watchdog control - The rst_wdsel register determines which subsystems are reset when the watchdog is triggered. - The watchdog can be triggered in software. +#[doc = "Watchdog control The rst_wdsel register determines which subsystems are reset when the watchdog is triggered. The watchdog can be triggered in software. You can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CTRL_SPEC; diff --git a/src/watchdog/load.rs b/src/watchdog/load.rs index 2825a6257..6c938fcda 100644 --- a/src/watchdog/load.rs +++ b/src/watchdog/load.rs @@ -1,3 +1,5 @@ +#[doc = "Register `LOAD` reader"] +pub type R = crate::R; #[doc = "Register `LOAD` writer"] pub type W = crate::W; #[doc = "Field `LOAD` writer - "] @@ -12,11 +14,13 @@ impl W { } #[doc = "Load the watchdog timer. The maximum setting is 0xffffff which corresponds to 0xffffff / 2 ticks before triggering a watchdog reset (see errata RP2040-E1). -You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`load::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`load::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`load::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct LOAD_SPEC; impl crate::RegisterSpec for LOAD_SPEC { type Ux = u32; } +#[doc = "`read()` method returns [`load::R`](R) reader structure"] +impl crate::Readable for LOAD_SPEC {} #[doc = "`write(|w| ..)` method takes [`load::W`](W) writer structure"] impl crate::Writable for LOAD_SPEC { type Safety = crate::Unsafe; diff --git a/src/watchdog/reason.rs b/src/watchdog/reason.rs index 7820acdd6..a3c677a4e 100644 --- a/src/watchdog/reason.rs +++ b/src/watchdog/reason.rs @@ -1,5 +1,7 @@ #[doc = "Register `REASON` reader"] pub type R = crate::R; +#[doc = "Register `REASON` writer"] +pub type W = crate::W; #[doc = "Field `TIMER` reader - "] pub type TIMER_R = crate::BitReader; #[doc = "Field `FORCE` reader - "] @@ -16,15 +18,22 @@ impl R { FORCE_R::new(((self.bits >> 1) & 1) != 0) } } +impl W {} #[doc = "Logs the reason for the last reset. Both bits are zero for the case of a hardware reset. -You can [`read`](crate::generic::Reg::read) this register and get [`reason::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`reason::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`reason::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct REASON_SPEC; impl crate::RegisterSpec for REASON_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`reason::R`](R) reader structure"] impl crate::Readable for REASON_SPEC {} +#[doc = "`write(|w| ..)` method takes [`reason::W`](W) writer structure"] +impl crate::Writable for REASON_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets REASON to value 0"] impl crate::Resettable for REASON_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/watchdog/scratch0.rs b/src/watchdog/scratch0.rs index a2eae729a..9f49433f7 100644 --- a/src/watchdog/scratch0.rs +++ b/src/watchdog/scratch0.rs @@ -2,17 +2,25 @@ pub type R = crate::R; #[doc = "Register `SCRATCH0` writer"] pub type W = crate::W; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) +#[doc = "Field `SCRATCH0` reader - "] +pub type SCRATCH0_R = crate::FieldReader; +#[doc = "Field `SCRATCH0` writer - "] +pub type SCRATCH0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn scratch0(&self) -> SCRATCH0_R { + SCRATCH0_R::new(self.bits) } } -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn scratch0(&mut self) -> SCRATCH0_W { + SCRATCH0_W::new(self, 0) } } -impl W {} #[doc = "Scratch register. Information persists through soft reset of the chip. You can [`read`](crate::generic::Reg::read) this register and get [`scratch0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scratch0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] diff --git a/src/watchdog/scratch1.rs b/src/watchdog/scratch1.rs index 0bb7e84bc..576c70fb6 100644 --- a/src/watchdog/scratch1.rs +++ b/src/watchdog/scratch1.rs @@ -2,17 +2,25 @@ pub type R = crate::R; #[doc = "Register `SCRATCH1` writer"] pub type W = crate::W; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) +#[doc = "Field `SCRATCH1` reader - "] +pub type SCRATCH1_R = crate::FieldReader; +#[doc = "Field `SCRATCH1` writer - "] +pub type SCRATCH1_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn scratch1(&self) -> SCRATCH1_R { + SCRATCH1_R::new(self.bits) } } -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn scratch1(&mut self) -> SCRATCH1_W { + SCRATCH1_W::new(self, 0) } } -impl W {} #[doc = "Scratch register. Information persists through soft reset of the chip. You can [`read`](crate::generic::Reg::read) this register and get [`scratch1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scratch1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] diff --git a/src/watchdog/scratch2.rs b/src/watchdog/scratch2.rs index 32f137a3d..21d59d6de 100644 --- a/src/watchdog/scratch2.rs +++ b/src/watchdog/scratch2.rs @@ -2,17 +2,25 @@ pub type R = crate::R; #[doc = "Register `SCRATCH2` writer"] pub type W = crate::W; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) +#[doc = "Field `SCRATCH2` reader - "] +pub type SCRATCH2_R = crate::FieldReader; +#[doc = "Field `SCRATCH2` writer - "] +pub type SCRATCH2_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn scratch2(&self) -> SCRATCH2_R { + SCRATCH2_R::new(self.bits) } } -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn scratch2(&mut self) -> SCRATCH2_W { + SCRATCH2_W::new(self, 0) } } -impl W {} #[doc = "Scratch register. Information persists through soft reset of the chip. You can [`read`](crate::generic::Reg::read) this register and get [`scratch2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scratch2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] diff --git a/src/watchdog/scratch3.rs b/src/watchdog/scratch3.rs index ac456ffae..de8496034 100644 --- a/src/watchdog/scratch3.rs +++ b/src/watchdog/scratch3.rs @@ -2,17 +2,25 @@ pub type R = crate::R; #[doc = "Register `SCRATCH3` writer"] pub type W = crate::W; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) +#[doc = "Field `SCRATCH3` reader - "] +pub type SCRATCH3_R = crate::FieldReader; +#[doc = "Field `SCRATCH3` writer - "] +pub type SCRATCH3_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn scratch3(&self) -> SCRATCH3_R { + SCRATCH3_R::new(self.bits) } } -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn scratch3(&mut self) -> SCRATCH3_W { + SCRATCH3_W::new(self, 0) } } -impl W {} #[doc = "Scratch register. Information persists through soft reset of the chip. You can [`read`](crate::generic::Reg::read) this register and get [`scratch3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scratch3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] diff --git a/src/watchdog/scratch4.rs b/src/watchdog/scratch4.rs index 70cc061ee..647d39f42 100644 --- a/src/watchdog/scratch4.rs +++ b/src/watchdog/scratch4.rs @@ -2,17 +2,25 @@ pub type R = crate::R; #[doc = "Register `SCRATCH4` writer"] pub type W = crate::W; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) +#[doc = "Field `SCRATCH4` reader - "] +pub type SCRATCH4_R = crate::FieldReader; +#[doc = "Field `SCRATCH4` writer - "] +pub type SCRATCH4_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn scratch4(&self) -> SCRATCH4_R { + SCRATCH4_R::new(self.bits) } } -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn scratch4(&mut self) -> SCRATCH4_W { + SCRATCH4_W::new(self, 0) } } -impl W {} #[doc = "Scratch register. Information persists through soft reset of the chip. You can [`read`](crate::generic::Reg::read) this register and get [`scratch4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scratch4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] diff --git a/src/watchdog/scratch5.rs b/src/watchdog/scratch5.rs index f4326a151..44acc8e7c 100644 --- a/src/watchdog/scratch5.rs +++ b/src/watchdog/scratch5.rs @@ -2,17 +2,25 @@ pub type R = crate::R; #[doc = "Register `SCRATCH5` writer"] pub type W = crate::W; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) +#[doc = "Field `SCRATCH5` reader - "] +pub type SCRATCH5_R = crate::FieldReader; +#[doc = "Field `SCRATCH5` writer - "] +pub type SCRATCH5_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn scratch5(&self) -> SCRATCH5_R { + SCRATCH5_R::new(self.bits) } } -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn scratch5(&mut self) -> SCRATCH5_W { + SCRATCH5_W::new(self, 0) } } -impl W {} #[doc = "Scratch register. Information persists through soft reset of the chip. You can [`read`](crate::generic::Reg::read) this register and get [`scratch5::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scratch5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] diff --git a/src/watchdog/scratch6.rs b/src/watchdog/scratch6.rs index f6b084e35..17b0c2ed7 100644 --- a/src/watchdog/scratch6.rs +++ b/src/watchdog/scratch6.rs @@ -2,17 +2,25 @@ pub type R = crate::R; #[doc = "Register `SCRATCH6` writer"] pub type W = crate::W; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) +#[doc = "Field `SCRATCH6` reader - "] +pub type SCRATCH6_R = crate::FieldReader; +#[doc = "Field `SCRATCH6` writer - "] +pub type SCRATCH6_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn scratch6(&self) -> SCRATCH6_R { + SCRATCH6_R::new(self.bits) } } -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn scratch6(&mut self) -> SCRATCH6_W { + SCRATCH6_W::new(self, 0) } } -impl W {} #[doc = "Scratch register. Information persists through soft reset of the chip. You can [`read`](crate::generic::Reg::read) this register and get [`scratch6::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scratch6::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] diff --git a/src/watchdog/scratch7.rs b/src/watchdog/scratch7.rs index 7366acd53..2039633ad 100644 --- a/src/watchdog/scratch7.rs +++ b/src/watchdog/scratch7.rs @@ -2,17 +2,25 @@ pub type R = crate::R; #[doc = "Register `SCRATCH7` writer"] pub type W = crate::W; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) +#[doc = "Field `SCRATCH7` reader - "] +pub type SCRATCH7_R = crate::FieldReader; +#[doc = "Field `SCRATCH7` writer - "] +pub type SCRATCH7_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn scratch7(&self) -> SCRATCH7_R { + SCRATCH7_R::new(self.bits) } } -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn scratch7(&mut self) -> SCRATCH7_W { + SCRATCH7_W::new(self, 0) } } -impl W {} #[doc = "Scratch register. Information persists through soft reset of the chip. You can [`read`](crate::generic::Reg::read) this register and get [`scratch7::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scratch7::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] diff --git a/src/xip_ctrl.rs b/src/xip_ctrl.rs index 7e89236fa..e63635bf9 100644 --- a/src/xip_ctrl.rs +++ b/src/xip_ctrl.rs @@ -26,18 +26,12 @@ impl RegisterBlock { pub const fn stat(&self) -> &STAT { &self.stat } - #[doc = "0x0c - Cache Hit counter - A 32 bit saturating counter that increments upon each cache hit, - i.e. when an XIP access is serviced directly from cached data. - Write any value to clear."] + #[doc = "0x0c - Cache Hit counter"] #[inline(always)] pub const fn ctr_hit(&self) -> &CTR_HIT { &self.ctr_hit } - #[doc = "0x10 - Cache Access counter - A 32 bit saturating counter that increments upon each XIP access, - whether the cache is hit or not. This includes noncacheable accesses. - Write any value to clear."] + #[doc = "0x10 - Cache Access counter"] #[inline(always)] pub const fn ctr_acc(&self) -> &CTR_ACC { &self.ctr_acc @@ -52,10 +46,7 @@ impl RegisterBlock { pub const fn stream_ctr(&self) -> &STREAM_CTR { &self.stream_ctr } - #[doc = "0x1c - FIFO stream data - Streamed data is buffered here, for retrieval by the system DMA. - This FIFO can also be accessed via the XIP_AUX slave, to avoid exposing - the DMA to bus stalls caused by other XIP traffic."] + #[doc = "0x1c - FIFO stream data"] #[inline(always)] pub const fn stream_fifo(&self) -> &STREAM_FIFO { &self.stream_fifo @@ -79,9 +70,9 @@ module"] pub type FLUSH = crate::Reg; #[doc = "Cache Flush control"] pub mod flush; -#[doc = "STAT (r) register accessor: Cache Status +#[doc = "STAT (rw) register accessor: Cache Status -You can [`read`](crate::generic::Reg::read) this register and get [`stat::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`stat::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@stat`] module"] @@ -89,34 +80,22 @@ pub type STAT = crate::Reg; #[doc = "Cache Status"] pub mod stat; #[doc = "CTR_HIT (rw) register accessor: Cache Hit counter - A 32 bit saturating counter that increments upon each cache hit, - i.e. when an XIP access is serviced directly from cached data. - Write any value to clear. You can [`read`](crate::generic::Reg::read) this register and get [`ctr_hit::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctr_hit::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@ctr_hit`] module"] pub type CTR_HIT = crate::Reg; -#[doc = "Cache Hit counter - A 32 bit saturating counter that increments upon each cache hit, - i.e. when an XIP access is serviced directly from cached data. - Write any value to clear."] +#[doc = "Cache Hit counter"] pub mod ctr_hit; #[doc = "CTR_ACC (rw) register accessor: Cache Access counter - A 32 bit saturating counter that increments upon each XIP access, - whether the cache is hit or not. This includes noncacheable accesses. - Write any value to clear. You can [`read`](crate::generic::Reg::read) this register and get [`ctr_acc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctr_acc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@ctr_acc`] module"] pub type CTR_ACC = crate::Reg; -#[doc = "Cache Access counter - A 32 bit saturating counter that increments upon each XIP access, - whether the cache is hit or not. This includes noncacheable accesses. - Write any value to clear."] +#[doc = "Cache Access counter"] pub mod ctr_acc; #[doc = "STREAM_ADDR (rw) register accessor: FIFO stream address @@ -136,18 +115,12 @@ module"] pub type STREAM_CTR = crate::Reg; #[doc = "FIFO stream control"] pub mod stream_ctr; -#[doc = "STREAM_FIFO (r) register accessor: FIFO stream data - Streamed data is buffered here, for retrieval by the system DMA. - This FIFO can also be accessed via the XIP_AUX slave, to avoid exposing - the DMA to bus stalls caused by other XIP traffic. +#[doc = "STREAM_FIFO (rw) register accessor: FIFO stream data -You can [`read`](crate::generic::Reg::read) this register and get [`stream_fifo::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). +You can [`read`](crate::generic::Reg::read) this register and get [`stream_fifo::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stream_fifo::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@stream_fifo`] module"] pub type STREAM_FIFO = crate::Reg; -#[doc = "FIFO stream data - Streamed data is buffered here, for retrieval by the system DMA. - This FIFO can also be accessed via the XIP_AUX slave, to avoid exposing - the DMA to bus stalls caused by other XIP traffic."] +#[doc = "FIFO stream data"] pub mod stream_fifo; diff --git a/src/xip_ctrl/ctr_acc.rs b/src/xip_ctrl/ctr_acc.rs index f22926893..af1966ba4 100644 --- a/src/xip_ctrl/ctr_acc.rs +++ b/src/xip_ctrl/ctr_acc.rs @@ -2,21 +2,26 @@ pub type R = crate::R; #[doc = "Register `CTR_ACC` writer"] pub type W = crate::W; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) +#[doc = "Field `CTR_ACC` reader - A 32 bit saturating counter that increments upon each XIP access, whether the cache is hit or not. This includes noncacheable accesses. Write any value to clear."] +pub type CTR_ACC_R = crate::FieldReader; +#[doc = "Field `CTR_ACC` writer - A 32 bit saturating counter that increments upon each XIP access, whether the cache is hit or not. This includes noncacheable accesses. Write any value to clear."] +pub type CTR_ACC_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - A 32 bit saturating counter that increments upon each XIP access, whether the cache is hit or not. This includes noncacheable accesses. Write any value to clear."] + #[inline(always)] + pub fn ctr_acc(&self) -> CTR_ACC_R { + CTR_ACC_R::new(self.bits) } } -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +impl W { + #[doc = "Bits 0:31 - A 32 bit saturating counter that increments upon each XIP access, whether the cache is hit or not. This includes noncacheable accesses. Write any value to clear."] + #[inline(always)] + #[must_use] + pub fn ctr_acc(&mut self) -> CTR_ACC_W { + CTR_ACC_W::new(self, 0) } } -impl W {} #[doc = "Cache Access counter - A 32 bit saturating counter that increments upon each XIP access, - whether the cache is hit or not. This includes noncacheable accesses. - Write any value to clear. You can [`read`](crate::generic::Reg::read) this register and get [`ctr_acc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctr_acc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CTR_ACC_SPEC; @@ -29,7 +34,7 @@ impl crate::Readable for CTR_ACC_SPEC {} impl crate::Writable for CTR_ACC_SPEC { type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0xffff_ffff; } #[doc = "`reset()` method sets CTR_ACC to value 0"] impl crate::Resettable for CTR_ACC_SPEC { diff --git a/src/xip_ctrl/ctr_hit.rs b/src/xip_ctrl/ctr_hit.rs index 1ec689767..e613a3fb7 100644 --- a/src/xip_ctrl/ctr_hit.rs +++ b/src/xip_ctrl/ctr_hit.rs @@ -2,21 +2,26 @@ pub type R = crate::R; #[doc = "Register `CTR_HIT` writer"] pub type W = crate::W; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) +#[doc = "Field `CTR_HIT` reader - A 32 bit saturating counter that increments upon each cache hit, i.e. when an XIP access is serviced directly from cached data. Write any value to clear."] +pub type CTR_HIT_R = crate::FieldReader; +#[doc = "Field `CTR_HIT` writer - A 32 bit saturating counter that increments upon each cache hit, i.e. when an XIP access is serviced directly from cached data. Write any value to clear."] +pub type CTR_HIT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - A 32 bit saturating counter that increments upon each cache hit, i.e. when an XIP access is serviced directly from cached data. Write any value to clear."] + #[inline(always)] + pub fn ctr_hit(&self) -> CTR_HIT_R { + CTR_HIT_R::new(self.bits) } } -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +impl W { + #[doc = "Bits 0:31 - A 32 bit saturating counter that increments upon each cache hit, i.e. when an XIP access is serviced directly from cached data. Write any value to clear."] + #[inline(always)] + #[must_use] + pub fn ctr_hit(&mut self) -> CTR_HIT_W { + CTR_HIT_W::new(self, 0) } } -impl W {} #[doc = "Cache Hit counter - A 32 bit saturating counter that increments upon each cache hit, - i.e. when an XIP access is serviced directly from cached data. - Write any value to clear. You can [`read`](crate::generic::Reg::read) this register and get [`ctr_hit::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctr_hit::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CTR_HIT_SPEC; @@ -29,7 +34,7 @@ impl crate::Readable for CTR_HIT_SPEC {} impl crate::Writable for CTR_HIT_SPEC { type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0xffff_ffff; } #[doc = "`reset()` method sets CTR_HIT to value 0"] impl crate::Resettable for CTR_HIT_SPEC { diff --git a/src/xip_ctrl/ctrl.rs b/src/xip_ctrl/ctrl.rs index 30068d207..601d4379e 100644 --- a/src/xip_ctrl/ctrl.rs +++ b/src/xip_ctrl/ctrl.rs @@ -2,105 +2,49 @@ pub type R = crate::R; #[doc = "Register `CTRL` writer"] pub type W = crate::W; -#[doc = "Field `EN` reader - When 1, enable the cache. When the cache is disabled, all XIP accesses - will go straight to the flash, without querying the cache. When enabled, - cacheable XIP accesses will query the cache, and the flash will - not be accessed if the tag matches and the valid bit is set. - - If the cache is enabled, cache-as-SRAM accesses have no effect on the - cache data RAM, and will produce a bus error response."] +#[doc = "Field `EN` reader - When 1, enable the cache. When the cache is disabled, all XIP accesses will go straight to the flash, without querying the cache. When enabled, cacheable XIP accesses will query the cache, and the flash will not be accessed if the tag matches and the valid bit is set. If the cache is enabled, cache-as-SRAM accesses have no effect on the cache data RAM, and will produce a bus error response."] pub type EN_R = crate::BitReader; -#[doc = "Field `EN` writer - When 1, enable the cache. When the cache is disabled, all XIP accesses - will go straight to the flash, without querying the cache. When enabled, - cacheable XIP accesses will query the cache, and the flash will - not be accessed if the tag matches and the valid bit is set. - - If the cache is enabled, cache-as-SRAM accesses have no effect on the - cache data RAM, and will produce a bus error response."] +#[doc = "Field `EN` writer - When 1, enable the cache. When the cache is disabled, all XIP accesses will go straight to the flash, without querying the cache. When enabled, cacheable XIP accesses will query the cache, and the flash will not be accessed if the tag matches and the valid bit is set. If the cache is enabled, cache-as-SRAM accesses have no effect on the cache data RAM, and will produce a bus error response."] pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `ERR_BADWRITE` reader - When 1, writes to any alias other than 0x0 (caching, allocating) - will produce a bus fault. When 0, these writes are silently ignored. - In either case, writes to the 0x0 alias will deallocate on tag match, - as usual."] +#[doc = "Field `ERR_BADWRITE` reader - When 1, writes to any alias other than 0x0 (caching, allocating) will produce a bus fault. When 0, these writes are silently ignored. In either case, writes to the 0x0 alias will deallocate on tag match, as usual."] pub type ERR_BADWRITE_R = crate::BitReader; -#[doc = "Field `ERR_BADWRITE` writer - When 1, writes to any alias other than 0x0 (caching, allocating) - will produce a bus fault. When 0, these writes are silently ignored. - In either case, writes to the 0x0 alias will deallocate on tag match, - as usual."] +#[doc = "Field `ERR_BADWRITE` writer - When 1, writes to any alias other than 0x0 (caching, allocating) will produce a bus fault. When 0, these writes are silently ignored. In either case, writes to the 0x0 alias will deallocate on tag match, as usual."] pub type ERR_BADWRITE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `POWER_DOWN` reader - When 1, the cache memories are powered down. They retain state, - but can not be accessed. This reduces static power dissipation. - Writing 1 to this bit forces CTRL_EN to 0, i.e. the cache cannot - be enabled when powered down. - Cache-as-SRAM accesses will produce a bus error response when - the cache is powered down."] +#[doc = "Field `POWER_DOWN` reader - When 1, the cache memories are powered down. They retain state, but can not be accessed. This reduces static power dissipation. Writing 1 to this bit forces CTRL_EN to 0, i.e. the cache cannot be enabled when powered down. Cache-as-SRAM accesses will produce a bus error response when the cache is powered down."] pub type POWER_DOWN_R = crate::BitReader; -#[doc = "Field `POWER_DOWN` writer - When 1, the cache memories are powered down. They retain state, - but can not be accessed. This reduces static power dissipation. - Writing 1 to this bit forces CTRL_EN to 0, i.e. the cache cannot - be enabled when powered down. - Cache-as-SRAM accesses will produce a bus error response when - the cache is powered down."] +#[doc = "Field `POWER_DOWN` writer - When 1, the cache memories are powered down. They retain state, but can not be accessed. This reduces static power dissipation. Writing 1 to this bit forces CTRL_EN to 0, i.e. the cache cannot be enabled when powered down. Cache-as-SRAM accesses will produce a bus error response when the cache is powered down."] pub type POWER_DOWN_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { - #[doc = "Bit 0 - When 1, enable the cache. When the cache is disabled, all XIP accesses - will go straight to the flash, without querying the cache. When enabled, - cacheable XIP accesses will query the cache, and the flash will - not be accessed if the tag matches and the valid bit is set. - - If the cache is enabled, cache-as-SRAM accesses have no effect on the - cache data RAM, and will produce a bus error response."] + #[doc = "Bit 0 - When 1, enable the cache. When the cache is disabled, all XIP accesses will go straight to the flash, without querying the cache. When enabled, cacheable XIP accesses will query the cache, and the flash will not be accessed if the tag matches and the valid bit is set. If the cache is enabled, cache-as-SRAM accesses have no effect on the cache data RAM, and will produce a bus error response."] #[inline(always)] pub fn en(&self) -> EN_R { EN_R::new((self.bits & 1) != 0) } - #[doc = "Bit 1 - When 1, writes to any alias other than 0x0 (caching, allocating) - will produce a bus fault. When 0, these writes are silently ignored. - In either case, writes to the 0x0 alias will deallocate on tag match, - as usual."] + #[doc = "Bit 1 - When 1, writes to any alias other than 0x0 (caching, allocating) will produce a bus fault. When 0, these writes are silently ignored. In either case, writes to the 0x0 alias will deallocate on tag match, as usual."] #[inline(always)] pub fn err_badwrite(&self) -> ERR_BADWRITE_R { ERR_BADWRITE_R::new(((self.bits >> 1) & 1) != 0) } - #[doc = "Bit 3 - When 1, the cache memories are powered down. They retain state, - but can not be accessed. This reduces static power dissipation. - Writing 1 to this bit forces CTRL_EN to 0, i.e. the cache cannot - be enabled when powered down. - Cache-as-SRAM accesses will produce a bus error response when - the cache is powered down."] + #[doc = "Bit 3 - When 1, the cache memories are powered down. They retain state, but can not be accessed. This reduces static power dissipation. Writing 1 to this bit forces CTRL_EN to 0, i.e. the cache cannot be enabled when powered down. Cache-as-SRAM accesses will produce a bus error response when the cache is powered down."] #[inline(always)] pub fn power_down(&self) -> POWER_DOWN_R { POWER_DOWN_R::new(((self.bits >> 3) & 1) != 0) } } impl W { - #[doc = "Bit 0 - When 1, enable the cache. When the cache is disabled, all XIP accesses - will go straight to the flash, without querying the cache. When enabled, - cacheable XIP accesses will query the cache, and the flash will - not be accessed if the tag matches and the valid bit is set. - - If the cache is enabled, cache-as-SRAM accesses have no effect on the - cache data RAM, and will produce a bus error response."] + #[doc = "Bit 0 - When 1, enable the cache. When the cache is disabled, all XIP accesses will go straight to the flash, without querying the cache. When enabled, cacheable XIP accesses will query the cache, and the flash will not be accessed if the tag matches and the valid bit is set. If the cache is enabled, cache-as-SRAM accesses have no effect on the cache data RAM, and will produce a bus error response."] #[inline(always)] #[must_use] pub fn en(&mut self) -> EN_W { EN_W::new(self, 0) } - #[doc = "Bit 1 - When 1, writes to any alias other than 0x0 (caching, allocating) - will produce a bus fault. When 0, these writes are silently ignored. - In either case, writes to the 0x0 alias will deallocate on tag match, - as usual."] + #[doc = "Bit 1 - When 1, writes to any alias other than 0x0 (caching, allocating) will produce a bus fault. When 0, these writes are silently ignored. In either case, writes to the 0x0 alias will deallocate on tag match, as usual."] #[inline(always)] #[must_use] pub fn err_badwrite(&mut self) -> ERR_BADWRITE_W { ERR_BADWRITE_W::new(self, 1) } - #[doc = "Bit 3 - When 1, the cache memories are powered down. They retain state, - but can not be accessed. This reduces static power dissipation. - Writing 1 to this bit forces CTRL_EN to 0, i.e. the cache cannot - be enabled when powered down. - Cache-as-SRAM accesses will produce a bus error response when - the cache is powered down."] + #[doc = "Bit 3 - When 1, the cache memories are powered down. They retain state, but can not be accessed. This reduces static power dissipation. Writing 1 to this bit forces CTRL_EN to 0, i.e. the cache cannot be enabled when powered down. Cache-as-SRAM accesses will produce a bus error response when the cache is powered down."] #[inline(always)] #[must_use] pub fn power_down(&mut self) -> POWER_DOWN_W { diff --git a/src/xip_ctrl/flush.rs b/src/xip_ctrl/flush.rs index 8598d60d1..9f3cd0578 100644 --- a/src/xip_ctrl/flush.rs +++ b/src/xip_ctrl/flush.rs @@ -2,35 +2,10 @@ pub type R = crate::R; #[doc = "Register `FLUSH` writer"] pub type W = crate::W; -#[doc = "Field `FLUSH` reader - Write 1 to flush the cache. This clears the tag memory, but - the data memory retains its contents. (This means cache-as-SRAM - contents is not affected by flush or reset.) - Reading will hold the bus (stall the processor) until the flush - completes. Alternatively STAT can be polled until completion."] -pub type FLUSH_R = crate::BitReader; -#[doc = "Field `FLUSH` writer - Write 1 to flush the cache. This clears the tag memory, but - the data memory retains its contents. (This means cache-as-SRAM - contents is not affected by flush or reset.) - Reading will hold the bus (stall the processor) until the flush - completes. Alternatively STAT can be polled until completion."] +#[doc = "Field `FLUSH` writer - Write 1 to flush the cache. This clears the tag memory, but the data memory retains its contents. (This means cache-as-SRAM contents is not affected by flush or reset.) Reading will hold the bus (stall the processor) until the flush completes. Alternatively STAT can be polled until completion."] pub type FLUSH_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 0 - Write 1 to flush the cache. This clears the tag memory, but - the data memory retains its contents. (This means cache-as-SRAM - contents is not affected by flush or reset.) - Reading will hold the bus (stall the processor) until the flush - completes. Alternatively STAT can be polled until completion."] - #[inline(always)] - pub fn flush(&self) -> FLUSH_R { - FLUSH_R::new((self.bits & 1) != 0) - } -} impl W { - #[doc = "Bit 0 - Write 1 to flush the cache. This clears the tag memory, but - the data memory retains its contents. (This means cache-as-SRAM - contents is not affected by flush or reset.) - Reading will hold the bus (stall the processor) until the flush - completes. Alternatively STAT can be polled until completion."] + #[doc = "Bit 0 - Write 1 to flush the cache. This clears the tag memory, but the data memory retains its contents. (This means cache-as-SRAM contents is not affected by flush or reset.) Reading will hold the bus (stall the processor) until the flush completes. Alternatively STAT can be polled until completion."] #[inline(always)] #[must_use] pub fn flush(&mut self) -> FLUSH_W { diff --git a/src/xip_ctrl/stat.rs b/src/xip_ctrl/stat.rs index b5710094b..0e6810177 100644 --- a/src/xip_ctrl/stat.rs +++ b/src/xip_ctrl/stat.rs @@ -1,19 +1,15 @@ #[doc = "Register `STAT` reader"] pub type R = crate::R; -#[doc = "Field `FLUSH_READY` reader - Reads as 0 while a cache flush is in progress, and 1 otherwise. - The cache is flushed whenever the XIP block is reset, and also - when requested via the FLUSH register."] +#[doc = "Register `STAT` writer"] +pub type W = crate::W; +#[doc = "Field `FLUSH_READY` reader - Reads as 0 while a cache flush is in progress, and 1 otherwise. The cache is flushed whenever the XIP block is reset, and also when requested via the FLUSH register."] pub type FLUSH_READY_R = crate::BitReader; #[doc = "Field `FIFO_EMPTY` reader - When 1, indicates the XIP streaming FIFO is completely empty."] pub type FIFO_EMPTY_R = crate::BitReader; -#[doc = "Field `FIFO_FULL` reader - When 1, indicates the XIP streaming FIFO is completely full. - The streaming FIFO is 2 entries deep, so the full and empty - flag allow its level to be ascertained."] +#[doc = "Field `FIFO_FULL` reader - When 1, indicates the XIP streaming FIFO is completely full. The streaming FIFO is 2 entries deep, so the full and empty flag allow its level to be ascertained."] pub type FIFO_FULL_R = crate::BitReader; impl R { - #[doc = "Bit 0 - Reads as 0 while a cache flush is in progress, and 1 otherwise. - The cache is flushed whenever the XIP block is reset, and also - when requested via the FLUSH register."] + #[doc = "Bit 0 - Reads as 0 while a cache flush is in progress, and 1 otherwise. The cache is flushed whenever the XIP block is reset, and also when requested via the FLUSH register."] #[inline(always)] pub fn flush_ready(&self) -> FLUSH_READY_R { FLUSH_READY_R::new((self.bits & 1) != 0) @@ -23,23 +19,28 @@ impl R { pub fn fifo_empty(&self) -> FIFO_EMPTY_R { FIFO_EMPTY_R::new(((self.bits >> 1) & 1) != 0) } - #[doc = "Bit 2 - When 1, indicates the XIP streaming FIFO is completely full. - The streaming FIFO is 2 entries deep, so the full and empty - flag allow its level to be ascertained."] + #[doc = "Bit 2 - When 1, indicates the XIP streaming FIFO is completely full. The streaming FIFO is 2 entries deep, so the full and empty flag allow its level to be ascertained."] #[inline(always)] pub fn fifo_full(&self) -> FIFO_FULL_R { FIFO_FULL_R::new(((self.bits >> 2) & 1) != 0) } } +impl W {} #[doc = "Cache Status -You can [`read`](crate::generic::Reg::read) this register and get [`stat::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`stat::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stat::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct STAT_SPEC; impl crate::RegisterSpec for STAT_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`stat::R`](R) reader structure"] impl crate::Readable for STAT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`stat::W`](W) writer structure"] +impl crate::Writable for STAT_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets STAT to value 0x02"] impl crate::Resettable for STAT_SPEC { const RESET_VALUE: u32 = 0x02; diff --git a/src/xip_ctrl/stream_addr.rs b/src/xip_ctrl/stream_addr.rs index 384aaf518..d06b2996a 100644 --- a/src/xip_ctrl/stream_addr.rs +++ b/src/xip_ctrl/stream_addr.rs @@ -2,27 +2,19 @@ pub type R = crate::R; #[doc = "Register `STREAM_ADDR` writer"] pub type W = crate::W; -#[doc = "Field `STREAM_ADDR` reader - The address of the next word to be streamed from flash to the streaming FIFO. - Increments automatically after each flash access. - Write the initial access address here before starting a streaming read."] +#[doc = "Field `STREAM_ADDR` reader - The address of the next word to be streamed from flash to the streaming FIFO. Increments automatically after each flash access. Write the initial access address here before starting a streaming read."] pub type STREAM_ADDR_R = crate::FieldReader; -#[doc = "Field `STREAM_ADDR` writer - The address of the next word to be streamed from flash to the streaming FIFO. - Increments automatically after each flash access. - Write the initial access address here before starting a streaming read."] +#[doc = "Field `STREAM_ADDR` writer - The address of the next word to be streamed from flash to the streaming FIFO. Increments automatically after each flash access. Write the initial access address here before starting a streaming read."] pub type STREAM_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 30, u32>; impl R { - #[doc = "Bits 2:31 - The address of the next word to be streamed from flash to the streaming FIFO. - Increments automatically after each flash access. - Write the initial access address here before starting a streaming read."] + #[doc = "Bits 2:31 - The address of the next word to be streamed from flash to the streaming FIFO. Increments automatically after each flash access. Write the initial access address here before starting a streaming read."] #[inline(always)] pub fn stream_addr(&self) -> STREAM_ADDR_R { STREAM_ADDR_R::new((self.bits >> 2) & 0x3fff_ffff) } } impl W { - #[doc = "Bits 2:31 - The address of the next word to be streamed from flash to the streaming FIFO. - Increments automatically after each flash access. - Write the initial access address here before starting a streaming read."] + #[doc = "Bits 2:31 - The address of the next word to be streamed from flash to the streaming FIFO. Increments automatically after each flash access. Write the initial access address here before starting a streaming read."] #[inline(always)] #[must_use] pub fn stream_addr(&mut self) -> STREAM_ADDR_W { diff --git a/src/xip_ctrl/stream_ctr.rs b/src/xip_ctrl/stream_ctr.rs index 430b2d567..4dad41312 100644 --- a/src/xip_ctrl/stream_ctr.rs +++ b/src/xip_ctrl/stream_ctr.rs @@ -2,47 +2,19 @@ pub type R = crate::R; #[doc = "Register `STREAM_CTR` writer"] pub type W = crate::W; -#[doc = "Field `STREAM_CTR` reader - Write a nonzero value to start a streaming read. This will then - progress in the background, using flash idle cycles to transfer - a linear data block from flash to the streaming FIFO. - Decrements automatically (1 at a time) as the stream - progresses, and halts on reaching 0. - Write 0 to halt an in-progress stream, and discard any in-flight - read, so that a new stream can immediately be started (after - draining the FIFO and reinitialising STREAM_ADDR)"] +#[doc = "Field `STREAM_CTR` reader - Write a nonzero value to start a streaming read. This will then progress in the background, using flash idle cycles to transfer a linear data block from flash to the streaming FIFO. Decrements automatically (1 at a time) as the stream progresses, and halts on reaching 0. Write 0 to halt an in-progress stream, and discard any in-flight read, so that a new stream can immediately be started (after draining the FIFO and reinitialising STREAM_ADDR)"] pub type STREAM_CTR_R = crate::FieldReader; -#[doc = "Field `STREAM_CTR` writer - Write a nonzero value to start a streaming read. This will then - progress in the background, using flash idle cycles to transfer - a linear data block from flash to the streaming FIFO. - Decrements automatically (1 at a time) as the stream - progresses, and halts on reaching 0. - Write 0 to halt an in-progress stream, and discard any in-flight - read, so that a new stream can immediately be started (after - draining the FIFO and reinitialising STREAM_ADDR)"] +#[doc = "Field `STREAM_CTR` writer - Write a nonzero value to start a streaming read. This will then progress in the background, using flash idle cycles to transfer a linear data block from flash to the streaming FIFO. Decrements automatically (1 at a time) as the stream progresses, and halts on reaching 0. Write 0 to halt an in-progress stream, and discard any in-flight read, so that a new stream can immediately be started (after draining the FIFO and reinitialising STREAM_ADDR)"] pub type STREAM_CTR_W<'a, REG> = crate::FieldWriter<'a, REG, 22, u32>; impl R { - #[doc = "Bits 0:21 - Write a nonzero value to start a streaming read. This will then - progress in the background, using flash idle cycles to transfer - a linear data block from flash to the streaming FIFO. - Decrements automatically (1 at a time) as the stream - progresses, and halts on reaching 0. - Write 0 to halt an in-progress stream, and discard any in-flight - read, so that a new stream can immediately be started (after - draining the FIFO and reinitialising STREAM_ADDR)"] + #[doc = "Bits 0:21 - Write a nonzero value to start a streaming read. This will then progress in the background, using flash idle cycles to transfer a linear data block from flash to the streaming FIFO. Decrements automatically (1 at a time) as the stream progresses, and halts on reaching 0. Write 0 to halt an in-progress stream, and discard any in-flight read, so that a new stream can immediately be started (after draining the FIFO and reinitialising STREAM_ADDR)"] #[inline(always)] pub fn stream_ctr(&self) -> STREAM_CTR_R { STREAM_CTR_R::new(self.bits & 0x003f_ffff) } } impl W { - #[doc = "Bits 0:21 - Write a nonzero value to start a streaming read. This will then - progress in the background, using flash idle cycles to transfer - a linear data block from flash to the streaming FIFO. - Decrements automatically (1 at a time) as the stream - progresses, and halts on reaching 0. - Write 0 to halt an in-progress stream, and discard any in-flight - read, so that a new stream can immediately be started (after - draining the FIFO and reinitialising STREAM_ADDR)"] + #[doc = "Bits 0:21 - Write a nonzero value to start a streaming read. This will then progress in the background, using flash idle cycles to transfer a linear data block from flash to the streaming FIFO. Decrements automatically (1 at a time) as the stream progresses, and halts on reaching 0. Write 0 to halt an in-progress stream, and discard any in-flight read, so that a new stream can immediately be started (after draining the FIFO and reinitialising STREAM_ADDR)"] #[inline(always)] #[must_use] pub fn stream_ctr(&mut self) -> STREAM_CTR_W { diff --git a/src/xip_ctrl/stream_fifo.rs b/src/xip_ctrl/stream_fifo.rs index 1d7533062..cf932d1bd 100644 --- a/src/xip_ctrl/stream_fifo.rs +++ b/src/xip_ctrl/stream_fifo.rs @@ -1,27 +1,34 @@ #[doc = "Register `STREAM_FIFO` reader"] pub type R = crate::R; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) - } -} -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +#[doc = "Register `STREAM_FIFO` writer"] +pub type W = crate::W; +#[doc = "Field `STREAM_FIFO` reader - Streamed data is buffered here, for retrieval by the system DMA. This FIFO can also be accessed via the XIP_AUX slave, to avoid exposing the DMA to bus stalls caused by other XIP traffic. + +The field is **modified** in some way after a read operation."] +pub type STREAM_FIFO_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Streamed data is buffered here, for retrieval by the system DMA. This FIFO can also be accessed via the XIP_AUX slave, to avoid exposing the DMA to bus stalls caused by other XIP traffic."] + #[inline(always)] + pub fn stream_fifo(&self) -> STREAM_FIFO_R { + STREAM_FIFO_R::new(self.bits) } } +impl W {} #[doc = "FIFO stream data - Streamed data is buffered here, for retrieval by the system DMA. - This FIFO can also be accessed via the XIP_AUX slave, to avoid exposing - the DMA to bus stalls caused by other XIP traffic. -You can [`read`](crate::generic::Reg::read) this register and get [`stream_fifo::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +You can [`read`](crate::generic::Reg::read) this register and get [`stream_fifo::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stream_fifo::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct STREAM_FIFO_SPEC; impl crate::RegisterSpec for STREAM_FIFO_SPEC { type Ux = u32; } #[doc = "`read()` method returns [`stream_fifo::R`](R) reader structure"] impl crate::Readable for STREAM_FIFO_SPEC {} +#[doc = "`write(|w| ..)` method takes [`stream_fifo::W`](W) writer structure"] +impl crate::Writable for STREAM_FIFO_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} #[doc = "`reset()` method sets STREAM_FIFO to value 0"] impl crate::Resettable for STREAM_FIFO_SPEC { const RESET_VALUE: u32 = 0; diff --git a/src/xosc.rs b/src/xosc.rs index 5602a887a..652a4c8e6 100644 --- a/src/xosc.rs +++ b/src/xosc.rs @@ -17,12 +17,7 @@ impl RegisterBlock { pub const fn status(&self) -> &STATUS { &self.status } - #[doc = "0x08 - Crystal Oscillator pause control - This is used to save power by pausing the XOSC - On power-up this field is initialised to WAKE - An invalid write will also select WAKE - WARNING: stop the PLLs before selecting dormant mode - WARNING: setup the irq before selecting dormant mode"] + #[doc = "0x08 - Crystal Oscillator pause control"] #[inline(always)] pub const fn dormant(&self) -> &DORMANT { &self.dormant @@ -52,23 +47,13 @@ pub type STATUS = crate::Reg; #[doc = "Crystal Oscillator Status"] pub mod status; #[doc = "DORMANT (rw) register accessor: Crystal Oscillator pause control - This is used to save power by pausing the XOSC - On power-up this field is initialised to WAKE - An invalid write will also select WAKE - WARNING: stop the PLLs before selecting dormant mode - WARNING: setup the irq before selecting dormant mode You can [`read`](crate::generic::Reg::read) this register and get [`dormant::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dormant::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). For information about available fields see [`mod@dormant`] module"] pub type DORMANT = crate::Reg; -#[doc = "Crystal Oscillator pause control - This is used to save power by pausing the XOSC - On power-up this field is initialised to WAKE - An invalid write will also select WAKE - WARNING: stop the PLLs before selecting dormant mode - WARNING: setup the irq before selecting dormant mode"] +#[doc = "Crystal Oscillator pause control"] pub mod dormant; #[doc = "STARTUP (rw) register accessor: Controls the startup delay diff --git a/src/xosc/ctrl.rs b/src/xosc/ctrl.rs index 3251a3d4c..46a2c332c 100644 --- a/src/xosc/ctrl.rs +++ b/src/xosc/ctrl.rs @@ -2,7 +2,7 @@ pub type R = crate::R; #[doc = "Register `CTRL` writer"] pub type W = crate::W; -#[doc = "Frequency range. This resets to 0xAA0 and cannot be changed. +#[doc = "Frequency range. An invalid setting will retain the previous value. The actual value being used can be read from STATUS_FREQ_RANGE. This resets to 0xAA0 and cannot be changed. Value on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -26,7 +26,7 @@ impl From for u16 { impl crate::FieldSpec for FREQ_RANGE_A { type Ux = u16; } -#[doc = "Field `FREQ_RANGE` reader - Frequency range. This resets to 0xAA0 and cannot be changed."] +#[doc = "Field `FREQ_RANGE` reader - Frequency range. An invalid setting will retain the previous value. The actual value being used can be read from STATUS_FREQ_RANGE. This resets to 0xAA0 and cannot be changed."] pub type FREQ_RANGE_R = crate::FieldReader; impl FREQ_RANGE_R { #[doc = "Get enumerated values variant"] @@ -61,7 +61,7 @@ impl FREQ_RANGE_R { *self == FREQ_RANGE_A::RESERVED_3 } } -#[doc = "Field `FREQ_RANGE` writer - Frequency range. This resets to 0xAA0 and cannot be changed."] +#[doc = "Field `FREQ_RANGE` writer - Frequency range. An invalid setting will retain the previous value. The actual value being used can be read from STATUS_FREQ_RANGE. This resets to 0xAA0 and cannot be changed."] pub type FREQ_RANGE_W<'a, REG> = crate::FieldWriter<'a, REG, 12, FREQ_RANGE_A>; impl<'a, REG> FREQ_RANGE_W<'a, REG> where @@ -89,9 +89,7 @@ where self.variant(FREQ_RANGE_A::RESERVED_3) } } -#[doc = "On power-up this field is initialised to DISABLE and the chip runs from the ROSC. - If the chip has subsequently been programmed to run from the XOSC then setting this field to DISABLE may lock-up the chip. If this is a concern then run the clk_ref from the ROSC and enable the clk_sys RESUS feature. - The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator. +#[doc = "On power-up this field is initialised to DISABLE and the chip runs from the ROSC. If the chip has subsequently been programmed to run from the XOSC then DISABLE may lock-up the chip. If this is a concern then run the clk_ref from the ROSC and enable the clk_sys RESUS feature. The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator. Value on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] @@ -111,9 +109,7 @@ impl From for u16 { impl crate::FieldSpec for ENABLE_A { type Ux = u16; } -#[doc = "Field `ENABLE` reader - On power-up this field is initialised to DISABLE and the chip runs from the ROSC. - If the chip has subsequently been programmed to run from the XOSC then setting this field to DISABLE may lock-up the chip. If this is a concern then run the clk_ref from the ROSC and enable the clk_sys RESUS feature. - The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator."] +#[doc = "Field `ENABLE` reader - On power-up this field is initialised to DISABLE and the chip runs from the ROSC. If the chip has subsequently been programmed to run from the XOSC then DISABLE may lock-up the chip. If this is a concern then run the clk_ref from the ROSC and enable the clk_sys RESUS feature. The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator."] pub type ENABLE_R = crate::FieldReader; impl ENABLE_R { #[doc = "Get enumerated values variant"] @@ -136,9 +132,7 @@ impl ENABLE_R { *self == ENABLE_A::ENABLE } } -#[doc = "Field `ENABLE` writer - On power-up this field is initialised to DISABLE and the chip runs from the ROSC. - If the chip has subsequently been programmed to run from the XOSC then setting this field to DISABLE may lock-up the chip. If this is a concern then run the clk_ref from the ROSC and enable the clk_sys RESUS feature. - The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator."] +#[doc = "Field `ENABLE` writer - On power-up this field is initialised to DISABLE and the chip runs from the ROSC. If the chip has subsequently been programmed to run from the XOSC then DISABLE may lock-up the chip. If this is a concern then run the clk_ref from the ROSC and enable the clk_sys RESUS feature. The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator."] pub type ENABLE_W<'a, REG> = crate::FieldWriter<'a, REG, 12, ENABLE_A>; impl<'a, REG> ENABLE_W<'a, REG> where @@ -157,29 +151,25 @@ where } } impl R { - #[doc = "Bits 0:11 - Frequency range. This resets to 0xAA0 and cannot be changed."] + #[doc = "Bits 0:11 - Frequency range. An invalid setting will retain the previous value. The actual value being used can be read from STATUS_FREQ_RANGE. This resets to 0xAA0 and cannot be changed."] #[inline(always)] pub fn freq_range(&self) -> FREQ_RANGE_R { FREQ_RANGE_R::new((self.bits & 0x0fff) as u16) } - #[doc = "Bits 12:23 - On power-up this field is initialised to DISABLE and the chip runs from the ROSC. - If the chip has subsequently been programmed to run from the XOSC then setting this field to DISABLE may lock-up the chip. If this is a concern then run the clk_ref from the ROSC and enable the clk_sys RESUS feature. - The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator."] + #[doc = "Bits 12:23 - On power-up this field is initialised to DISABLE and the chip runs from the ROSC. If the chip has subsequently been programmed to run from the XOSC then DISABLE may lock-up the chip. If this is a concern then run the clk_ref from the ROSC and enable the clk_sys RESUS feature. The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator."] #[inline(always)] pub fn enable(&self) -> ENABLE_R { ENABLE_R::new(((self.bits >> 12) & 0x0fff) as u16) } } impl W { - #[doc = "Bits 0:11 - Frequency range. This resets to 0xAA0 and cannot be changed."] + #[doc = "Bits 0:11 - Frequency range. An invalid setting will retain the previous value. The actual value being used can be read from STATUS_FREQ_RANGE. This resets to 0xAA0 and cannot be changed."] #[inline(always)] #[must_use] pub fn freq_range(&mut self) -> FREQ_RANGE_W { FREQ_RANGE_W::new(self, 0) } - #[doc = "Bits 12:23 - On power-up this field is initialised to DISABLE and the chip runs from the ROSC. - If the chip has subsequently been programmed to run from the XOSC then setting this field to DISABLE may lock-up the chip. If this is a concern then run the clk_ref from the ROSC and enable the clk_sys RESUS feature. - The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator."] + #[doc = "Bits 12:23 - On power-up this field is initialised to DISABLE and the chip runs from the ROSC. If the chip has subsequently been programmed to run from the XOSC then DISABLE may lock-up the chip. If this is a concern then run the clk_ref from the ROSC and enable the clk_sys RESUS feature. The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator."] #[inline(always)] #[must_use] pub fn enable(&mut self) -> ENABLE_W { diff --git a/src/xosc/dormant.rs b/src/xosc/dormant.rs index 05a6f0650..fc238f4ef 100644 --- a/src/xosc/dormant.rs +++ b/src/xosc/dormant.rs @@ -2,23 +2,83 @@ pub type R = crate::R; #[doc = "Register `DORMANT` writer"] pub type W = crate::W; -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) +#[doc = "This is used to save power by pausing the XOSC On power-up this field is initialised to WAKE An invalid write will also select WAKE Warning: stop the PLLs before selecting dormant mode Warning: setup the irq before selecting dormant mode + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u32)] +pub enum DORMANT_A { + #[doc = "1668246881: `1100011011011110110110101100001`"] + DORMANT = 1668246881, + #[doc = "2002873189: `1110111011000010110101101100101`"] + WAKE = 2002873189, +} +impl From for u32 { + #[inline(always)] + fn from(variant: DORMANT_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for DORMANT_A { + type Ux = u32; +} +#[doc = "Field `DORMANT` reader - This is used to save power by pausing the XOSC On power-up this field is initialised to WAKE An invalid write will also select WAKE Warning: stop the PLLs before selecting dormant mode Warning: setup the irq before selecting dormant mode"] +pub type DORMANT_R = crate::FieldReader; +impl DORMANT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1668246881 => Some(DORMANT_A::DORMANT), + 2002873189 => Some(DORMANT_A::WAKE), + _ => None, + } + } + #[doc = "`1100011011011110110110101100001`"] + #[inline(always)] + pub fn is_dormant(&self) -> bool { + *self == DORMANT_A::DORMANT + } + #[doc = "`1110111011000010110101101100101`"] + #[inline(always)] + pub fn is_wake(&self) -> bool { + *self == DORMANT_A::WAKE + } +} +#[doc = "Field `DORMANT` writer - This is used to save power by pausing the XOSC On power-up this field is initialised to WAKE An invalid write will also select WAKE Warning: stop the PLLs before selecting dormant mode Warning: setup the irq before selecting dormant mode"] +pub type DORMANT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, DORMANT_A>; +impl<'a, REG> DORMANT_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`1100011011011110110110101100001`"] + #[inline(always)] + pub fn dormant(self) -> &'a mut crate::W { + self.variant(DORMANT_A::DORMANT) + } + #[doc = "`1110111011000010110101101100101`"] + #[inline(always)] + pub fn wake(self) -> &'a mut crate::W { + self.variant(DORMANT_A::WAKE) + } +} +impl R { + #[doc = "Bits 0:31 - This is used to save power by pausing the XOSC On power-up this field is initialised to WAKE An invalid write will also select WAKE Warning: stop the PLLs before selecting dormant mode Warning: setup the irq before selecting dormant mode"] + #[inline(always)] + pub fn dormant(&self) -> DORMANT_R { + DORMANT_R::new(self.bits) } } -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) +impl W { + #[doc = "Bits 0:31 - This is used to save power by pausing the XOSC On power-up this field is initialised to WAKE An invalid write will also select WAKE Warning: stop the PLLs before selecting dormant mode Warning: setup the irq before selecting dormant mode"] + #[inline(always)] + #[must_use] + pub fn dormant(&mut self) -> DORMANT_W { + DORMANT_W::new(self, 0) } } -impl W {} #[doc = "Crystal Oscillator pause control - This is used to save power by pausing the XOSC - On power-up this field is initialised to WAKE - An invalid write will also select WAKE - WARNING: stop the PLLs before selecting dormant mode - WARNING: setup the irq before selecting dormant mode You can [`read`](crate::generic::Reg::read) this register and get [`dormant::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dormant::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DORMANT_SPEC; diff --git a/src/xosc/startup.rs b/src/xosc/startup.rs index 7bb4f02a9..e1130baaa 100644 --- a/src/xosc/startup.rs +++ b/src/xosc/startup.rs @@ -51,7 +51,7 @@ impl crate::Writable for STARTUP_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } -#[doc = "`reset()` method sets STARTUP to value 0xc4"] +#[doc = "`reset()` method sets STARTUP to value 0"] impl crate::Resettable for STARTUP_SPEC { - const RESET_VALUE: u32 = 0xc4; + const RESET_VALUE: u32 = 0; } diff --git a/svd/rp2040.svd.patched b/svd/rp2040.svd.patched index a57dfd308..2f6ac8293 100644 --- a/svd/rp2040.svd.patched +++ b/svd/rp2040.svd.patched @@ -2,22 +2,23 @@ Raspberry Pi RP2040 + RP 0.1 - Dual-core Arm Cortex-M0+ processor, flexible clock running up to 133 MHz\n - 264KB on-chip SRAM\n - 2 x UART, 2 x SPI controllers, 2 x I2C controllers, 16 x PWM channels\n - 1 x USB 1.1 controller and PHY, with host and device support\n - 8 x Programmable I/O (PIO) state machines for custom peripheral support\n - Supported input power 1.8-5.5V DC\n - Operating temperature -20C to +85C\n - Drag-and-drop programming using mass storage over USB\n - Low-power sleep and dormant modes\n - Accurate on-chip clock\n - Temperature sensor\n - Accelerated integer and floating-point libraries on-chip - Copyright (c) 2020 Raspberry Pi (Trading) Ltd.\n - \n - SPDX-License-Identifier: BSD-3-Clause + Dual-core Arm Cortex-M0+ processor, flexible clock running up to 133 MHz + 264KB on-chip SRAM + 2 x UART, 2 x SPI controllers, 2 x I2C controllers, 16 x PWM channels + 1 x USB 1.1 controller and PHY, with host and device support + 8 x Programmable I/O (PIO) state machines for custom peripheral support + Supported input power 1.8-5.5V DC + Operating temperature -20C to +85C + Drag-and-drop programming using mass storage over USB + Low-power sleep and dormant modes + Accurate on-chip clock + Temperature sensor + Accelerated integer and floating-point libraries on-chip + Copyright (c) 2024 Raspberry Pi Ltd. + + SPDX-License-Identifier: BSD-3-Clause CM0PLUS r0p1 @@ -31,1286 +32,881 @@ 8 32 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF - XIP_CTRL - 1 - QSPI flash execute-in-place block - 0x14000000 - 0x20 + RESETS + 0x4000C000 0x0 - 0x20 + 0xC registers - - XIP_IRQ - 6 - - CTRL - Cache control + RESET + Reset control. If a bit is set it means the peripheral is in reset. 0 means the peripheral's reset is deasserted. 0x0 - 0x00000003 + 0x01FFFFFF - POWER_DOWN - When 1, the cache memories are powered down. They retain state,\n - but can not be accessed. This reduces static power dissipation.\n - Writing 1 to this bit forces CTRL_EN to 0, i.e. the cache cannot\n - be enabled when powered down.\n - Cache-as-SRAM accesses will produce a bus error response when\n - the cache is powered down. - [3:3] + USBCTRL + [24:24] read-write - ERR_BADWRITE - When 1, writes to any alias other than 0x0 (caching, allocating)\n - will produce a bus fault. When 0, these writes are silently ignored.\n - In either case, writes to the 0x0 alias will deallocate on tag match,\n - as usual. - [1:1] + UART1 + [23:23] read-write - EN - When 1, enable the cache. When the cache is disabled, all XIP accesses\n - will go straight to the flash, without querying the cache. When enabled,\n - cacheable XIP accesses will query the cache, and the flash will\n - not be accessed if the tag matches and the valid bit is set.\n\n - If the cache is enabled, cache-as-SRAM accesses have no effect on the\n - cache data RAM, and will produce a bus error response. - [0:0] + UART0 + [22:22] read-write - - - - FLUSH - Cache Flush control - 0x4 - 0x00000000 - - FLUSH - Write 1 to flush the cache. This clears the tag memory, but\n - the data memory retains its contents. (This means cache-as-SRAM\n - contents is not affected by flush or reset.)\n - Reading will hold the bus (stall the processor) until the flush\n - completes. Alternatively STAT can be polled until completion. - [0:0] + TIMER + [21:21] read-write - clear - - - - STAT - Cache Status - 0x8 - 0x00000002 - - FIFO_FULL - When 1, indicates the XIP streaming FIFO is completely full.\n - The streaming FIFO is 2 entries deep, so the full and empty\n - flag allow its level to be ascertained. - [2:2] - read-only + TBMAN + [20:20] + read-write - FIFO_EMPTY - When 1, indicates the XIP streaming FIFO is completely empty. - [1:1] - read-only + SYSINFO + [19:19] + read-write - FLUSH_READY - Reads as 0 while a cache flush is in progress, and 1 otherwise.\n - The cache is flushed whenever the XIP block is reset, and also\n - when requested via the FLUSH register. - [0:0] - read-only + SYSCFG + [18:18] + read-write - - - - CTR_HIT - Cache Hit counter\n - A 32 bit saturating counter that increments upon each cache hit,\n - i.e. when an XIP access is serviced directly from cached data.\n - Write any value to clear. - 0xC - read-write - 0x00000000 - oneToClear - - - CTR_ACC - Cache Access counter\n - A 32 bit saturating counter that increments upon each XIP access,\n - whether the cache is hit or not. This includes noncacheable accesses.\n - Write any value to clear. - 0x10 - read-write - 0x00000000 - oneToClear - - - STREAM_ADDR - FIFO stream address - 0x14 - 0x00000000 - - STREAM_ADDR - The address of the next word to be streamed from flash to the streaming FIFO.\n - Increments automatically after each flash access.\n - Write the initial access address here before starting a streaming read. - [31:2] + SPI1 + [17:17] read-write - - - - STREAM_CTR - FIFO stream control - 0x18 - 0x00000000 - - STREAM_CTR - Write a nonzero value to start a streaming read. This will then\n - progress in the background, using flash idle cycles to transfer\n - a linear data block from flash to the streaming FIFO.\n - Decrements automatically (1 at a time) as the stream\n - progresses, and halts on reaching 0.\n - Write 0 to halt an in-progress stream, and discard any in-flight\n - read, so that a new stream can immediately be started (after\n - draining the FIFO and reinitialising STREAM_ADDR) - [21:0] + SPI0 + [16:16] read-write - - - - STREAM_FIFO - FIFO stream data\n - Streamed data is buffered here, for retrieval by the system DMA.\n - This FIFO can also be accessed via the XIP_AUX slave, to avoid exposing\n - the DMA to bus stalls caused by other XIP traffic. - 0x1C - read-only - 0x00000000 - - - - - XIP_SSI - 1 - DW_apb_ssi has the following features:\n - * APB interface - Allows for easy integration into a DesignWare Synthesizable Components for AMBA 2 implementation.\n - * APB3 and APB4 protocol support.\n - * Scalable APB data bus width - Supports APB data bus widths of 8, 16, and 32 bits.\n - * Serial-master or serial-slave operation - Enables serial communication with serial-master or serial-slave peripheral devices.\n - * Programmable Dual/Quad/Octal SPI support in Master Mode.\n - * Dual Data Rate (DDR) and Read Data Strobe (RDS) Support - Enables the DW_apb_ssi master to perform operations with the device in DDR and RDS modes when working in Dual/Quad/Octal mode of operation.\n - * Data Mask Support - Enables the DW_apb_ssi to selectively update the bytes in the device. This feature is applicable only in enhanced SPI modes.\n - * eXecute-In-Place (XIP) support - Enables the DW_apb_ssi master to behave as a memory mapped I/O and fetches the data from the device based on the APB read request. This feature is applicable only in enhanced SPI modes.\n - * DMA Controller Interface - Enables the DW_apb_ssi to interface to a DMA controller over the bus using a handshaking interface for transfer requests.\n - * Independent masking of interrupts - Master collision, transmit FIFO overflow, transmit FIFO empty, receive FIFO full, receive FIFO underflow, and receive FIFO overflow interrupts can all be masked independently.\n - * Multi-master contention detection - Informs the processor of multiple serial-master accesses on the serial bus.\n - * Bypass of meta-stability flip-flops for synchronous clocks - When the APB clock (pclk) and the DW_apb_ssi serial clock (ssi_clk) are synchronous, meta-stable flip-flops are not used when transferring control signals across these clock domains.\n - * Programmable delay on the sample time of the received serial data bit (rxd); enables programmable control of routing delays resulting in higher serial data-bit rates.\n - * Programmable features:\n - - Serial interface operation - Choice of Motorola SPI, Texas Instruments Synchronous Serial Protocol or National Semiconductor Microwire.\n - - Clock bit-rate - Dynamic control of the serial bit rate of the data transfer; used in only serial-master mode of operation.\n - - Data Item size (4 to 32 bits) - Item size of each data transfer under the control of the programmer.\n - * Configured features:\n - - FIFO depth - 16 words deep. The FIFO width is fixed at 32 bits.\n - - 1 slave select output.\n - - Hardware slave-select - Dedicated hardware slave-select line.\n - - Combined interrupt line - one combined interrupt line from the DW_apb_ssi to the interrupt controller.\n - - Interrupt polarity - active high interrupt lines.\n - - Serial clock polarity - low serial-clock polarity directly after reset.\n - - Serial clock phase - capture on first edge of serial-clock directly after reset. - 0x18000000 - 0x20 - - 0x0 - 0x100 - registers - - - - CTRLR0 - Control register 0 - 0x0 - 0x00000000 - - SSTE - Slave select toggle enable - [24:24] + RTC + [15:15] read-write - SPI_FRF - SPI frame format - [22:21] + PWM + [14:14] read-write - - - STD - Standard 1-bit SPI frame format; 1 bit per SCK, full-duplex - 0 - - - DUAL - Dual-SPI frame format; two bits per SCK, half-duplex - 1 - - - QUAD - Quad-SPI frame format; four bits per SCK, half-duplex - 2 - - - DFS_32 - Data frame size in 32b transfer mode\n - Value of n -> n+1 clocks per frame. - [20:16] + PLL_USB + [13:13] read-write - CFS - Control frame size\n - Value of n -> n+1 clocks per frame. - [15:12] + PLL_SYS + [12:12] read-write - SRL - Shift register loop (test mode) + PIO1 [11:11] read-write - SLV_OE - Slave output enable + PIO0 [10:10] read-write - TMOD - Transfer mode - [9:8] + PADS_QSPI + [9:9] read-write - - - TX_AND_RX - Both transmit and receive - 0 - - - TX_ONLY - Transmit only (not for FRF == 0, standard SPI mode) - 1 - - - RX_ONLY - Receive only (not for FRF == 0, standard SPI mode) - 2 - - - EEPROM_READ - EEPROM read mode (TX then RX; RX starts after control data TX'd) - 3 - - - SCPOL - Serial clock polarity - [7:7] + PADS_BANK0 + [8:8] read-write - SCPH - Serial clock phase - [6:6] + JTAG + [7:7] read-write - FRF - Frame format - [5:4] + IO_QSPI + [6:6] read-write - DFS - Data frame size - [3:0] + IO_BANK0 + [5:5] read-write - - - - CTRLR1 - Master Control register 1 - 0x4 - 0x00000000 - - NDF - Number of data frames - [15:0] + I2C1 + [4:4] read-write - - - - SSIENR - SSI Enable - 0x8 - 0x00000000 - - SSI_EN - SSI enable - [0:0] + I2C0 + [3:3] read-write - - - - MWCR - Microwire Control - 0xC - 0x00000000 - - MHS - Microwire handshaking + DMA [2:2] read-write - MDD - Microwire control + BUSCTRL [1:1] read-write - MWMOD - Microwire transfer mode + ADC [0:0] read-write - SER - Slave enable - 0x10 + WDSEL + Watchdog select. If a bit is set then the watchdog will reset this peripheral when the watchdog fires. + 0x4 0x00000000 - SER - For each bit:\n - 0 -> slave not selected\n - 1 -> slave selected - [0:0] + USBCTRL + [24:24] read-write - - - - BAUDR - Baud rate - 0x14 - 0x00000000 - - SCKDV - SSI clock divider - [15:0] + UART1 + [23:23] read-write - - - - TXFTLR - TX FIFO threshold level - 0x18 - 0x00000000 - - TFT - Transmit FIFO threshold - [7:0] + UART0 + [22:22] read-write - - - - RXFTLR - RX FIFO threshold level - 0x1C - 0x00000000 - - RFT - Receive FIFO threshold - [7:0] + TIMER + [21:21] read-write - - - - TXFLR - TX FIFO level - 0x20 - 0x00000000 - - TFTFL - Transmit FIFO level - [7:0] - read-only + TBMAN + [20:20] + read-write - - - - RXFLR - RX FIFO level - 0x24 - 0x00000000 - - RXTFL - Receive FIFO level - [7:0] - read-only + SYSINFO + [19:19] + read-write - - - - SR - Status register - 0x28 - 0x00000000 - - DCOL - Data collision error - [6:6] - read-only + SYSCFG + [18:18] + read-write - TXE - Transmission error - [5:5] - read-only + SPI1 + [17:17] + read-write - RFF - Receive FIFO full - [4:4] - read-only + SPI0 + [16:16] + read-write - RFNE - Receive FIFO not empty - [3:3] - read-only + RTC + [15:15] + read-write - TFE - Transmit FIFO empty - [2:2] - read-only + PWM + [14:14] + read-write - TFNF - Transmit FIFO not full - [1:1] - read-only + PLL_USB + [13:13] + read-write - BUSY - SSI busy flag - [0:0] - read-only + PLL_SYS + [12:12] + read-write - - - - IMR - Interrupt mask - 0x2C - 0x00000000 - - MSTIM - Multi-master contention interrupt mask + PIO1 + [11:11] + read-write + + + PIO0 + [10:10] + read-write + + + PADS_QSPI + [9:9] + read-write + + + PADS_BANK0 + [8:8] + read-write + + + JTAG + [7:7] + read-write + + + IO_QSPI + [6:6] + read-write + + + IO_BANK0 [5:5] read-write - RXFIM - Receive FIFO full interrupt mask + I2C1 [4:4] read-write - RXOIM - Receive FIFO overflow interrupt mask + I2C0 [3:3] read-write - RXUIM - Receive FIFO underflow interrupt mask + DMA [2:2] read-write - TXOIM - Transmit FIFO overflow interrupt mask + BUSCTRL [1:1] read-write - TXEIM - Transmit FIFO empty interrupt mask + ADC [0:0] read-write - ISR - Interrupt status - 0x30 + RESET_DONE + Reset done. If a bit is set then a reset done signal has been returned by the peripheral. This indicates that the peripheral's registers are ready to be accessed. + 0x8 0x00000000 - MSTIS - Multi-master contention interrupt status - [5:5] + USBCTRL + [24:24] read-only - RXFIS - Receive FIFO full interrupt status - [4:4] + UART1 + [23:23] read-only - RXOIS - Receive FIFO overflow interrupt status - [3:3] + UART0 + [22:22] read-only - RXUIS - Receive FIFO underflow interrupt status - [2:2] + TIMER + [21:21] read-only - TXOIS - Transmit FIFO overflow interrupt status - [1:1] + TBMAN + [20:20] read-only - TXEIS - Transmit FIFO empty interrupt status - [0:0] + SYSINFO + [19:19] read-only - - - - RISR - Raw interrupt status - 0x34 - 0x00000000 - - MSTIR - Multi-master contention raw interrupt status - [5:5] + SYSCFG + [18:18] read-only - RXFIR - Receive FIFO full raw interrupt status - [4:4] + SPI1 + [17:17] read-only - RXOIR - Receive FIFO overflow raw interrupt status - [3:3] + SPI0 + [16:16] read-only - RXUIR - Receive FIFO underflow raw interrupt status - [2:2] + RTC + [15:15] read-only - TXOIR - Transmit FIFO overflow raw interrupt status - [1:1] + PWM + [14:14] read-only - TXEIR - Transmit FIFO empty raw interrupt status - [0:0] + PLL_USB + [13:13] read-only - - - - TXOICR - TX FIFO overflow interrupt clear - 0x38 - 0x00000000 - - TXOICR - Clear-on-read transmit FIFO overflow interrupt - [0:0] + PLL_SYS + [12:12] read-only - - - - RXOICR - RX FIFO overflow interrupt clear - 0x3C - 0x00000000 - - RXOICR - Clear-on-read receive FIFO overflow interrupt - [0:0] + PIO1 + [11:11] read-only - - - - RXUICR - RX FIFO underflow interrupt clear - 0x40 - 0x00000000 - - RXUICR - Clear-on-read receive FIFO underflow interrupt - [0:0] + PIO0 + [10:10] read-only - - - - MSTICR - Multi-master interrupt clear - 0x44 - 0x00000000 - - MSTICR - Clear-on-read multi-master contention interrupt - [0:0] + PADS_QSPI + [9:9] read-only - - - - ICR - Interrupt clear - 0x48 - 0x00000000 - - ICR - Clear-on-read all active interrupts + PADS_BANK0 + [8:8] + read-only + + + JTAG + [7:7] + read-only + + + IO_QSPI + [6:6] + read-only + + + IO_BANK0 + [5:5] + read-only + + + I2C1 + [4:4] + read-only + + + I2C0 + [3:3] + read-only + + + DMA + [2:2] + read-only + + + BUSCTRL + [1:1] + read-only + + + ADC [0:0] read-only + + + + PSM + 0x40010000 + + 0x0 + 0x10 + registers + + - DMACR - DMA control - 0x4C + FRCE_ON + Force block out of reset (i.e. power it on) + 0x0 0x00000000 - TDMAE - Transmit DMA enable - [1:1] + PROC1 + [16:16] read-write - RDMAE - Receive DMA enable - [0:0] + PROC0 + [15:15] read-write - - - - DMATDLR - DMA TX data level - 0x50 - 0x00000000 - - DMATDL - Transmit data watermark level - [7:0] + SIO + [14:14] read-write - - - - DMARDLR - DMA RX data level - 0x54 - 0x00000000 - - DMARDL - Receive data watermark level (DMARDLR+1) - [7:0] + VREG_AND_CHIP_RESET + [13:13] read-write - - - - IDR - Identification register - 0x58 - 0x51535049 - - IDCODE - Peripheral dentification code - [31:0] - read-only + XIP + [12:12] + read-write - - - - SSI_VERSION_ID - Version ID - 0x5C - 0x3430312A - - SSI_COMP_VERSION - SNPS component version (format X.YY) - [31:0] - read-only + SRAM5 + [11:11] + read-write - - - - DR0 - Data Register 0 (of 36) - 0x60 - 0x00000000 - - DR - First data register of 36 - [31:0] + SRAM4 + [10:10] read-write - - - - RX_SAMPLE_DLY - RX sample delay - 0xF0 - 0x00000000 - - RSD - RXD sample delay (in SCLK cycles) - [7:0] + SRAM3 + [9:9] read-write - - - - SPI_CTRLR0 - SPI control - 0xF4 - 0x03000000 - - XIP_CMD - SPI Command to send in XIP mode (INST_L = 8-bit) or to append to Address (INST_L = 0-bit) - [31:24] + SRAM2 + [8:8] read-write - SPI_RXDS_EN - Read data strobe enable - [18:18] + SRAM1 + [7:7] read-write - INST_DDR_EN - Instruction DDR transfer enable - [17:17] + SRAM0 + [6:6] read-write - SPI_DDR_EN - SPI DDR transfer enable - [16:16] + ROM + [5:5] read-write - WAIT_CYCLES - Wait cycles between control frame transmit and data reception (in SCLK cycles) - [15:11] + BUSFABRIC + [4:4] read-write - INST_L - Instruction length (0/4/8/16b) - [9:8] + RESETS + [3:3] read-write - - - NONE - No instruction - 0 - - - 4B - 4-bit instruction - 1 - - - 8B - 8-bit instruction - 2 - - - 16B - 16-bit instruction - 3 - - - ADDR_L - Address length (0b-60b in 4b increments) - [5:2] + CLOCKS + [2:2] read-write - TRANS_TYPE - Address and instruction transfer format - [1:0] + XOSC + [1:1] + read-write + + + ROSC + [0:0] read-write - - - 1C1A - Command and address both in standard SPI frame format - 0 - - - 1C2A - Command in standard SPI format, address in format specified by FRF - 1 - - - 2C2A - Command and address both in format specified by FRF (e.g. Dual-SPI) - 2 - - - TXD_DRIVE_EDGE - TX drive edge - 0xF8 + FRCE_OFF + Force into reset (i.e. power it off) + 0x4 0x00000000 - TDE - TXD drive edge - [7:0] + PROC1 + [16:16] read-write - - - - - - SYSINFO - 1 - 0x40000000 - 0x20 - - 0x0 - 0x1000 - registers - - - - CHIP_ID - JEDEC JEP-106 compliant chip identifier. - 0x0 - 0x00000000 - - - REVISION - [31:28] - read-only - - - PART - [27:12] - read-only - - - MANUFACTURER - [11:0] - read-only - - - - - PLATFORM - Platform register. Allows software to know what environment it is running in. - 0x4 - 0x00000000 - - ASIC - [1:1] - read-only + PROC0 + [15:15] + read-write - FPGA - [0:0] - read-only + SIO + [14:14] + read-write - - - - GITREF_RP2040 - Git hash of the chip source. Used to identify chip version. - 0x40 - read-only - 0x00000000 - - - - - SYSCFG - 1 - Register block for various chip control signals - 0x40004000 - 0x20 - - 0x0 - 0x1000 - registers - - - - PROC0_NMI_MASK - Processor core 0 NMI source mask\n - Set a bit high to enable NMI from that IRQ - 0x0 - read-write - 0x00000000 - - - PROC1_NMI_MASK - Processor core 1 NMI source mask\n - Set a bit high to enable NMI from that IRQ - 0x4 - read-write - 0x00000000 - - - PROC_CONFIG - Configuration for processors - 0x8 - 0x10000000 - - PROC1_DAP_INSTID - Configure proc1 DAP instance ID.\n - Recommend that this is NOT changed until you require debug access in multi-chip environment\n - WARNING: do not set to 15 as this is reserved for RescueDP - [31:28] + VREG_AND_CHIP_RESET + [13:13] read-write - PROC0_DAP_INSTID - Configure proc0 DAP instance ID.\n - Recommend that this is NOT changed until you require debug access in multi-chip environment\n - WARNING: do not set to 15 as this is reserved for RescueDP - [27:24] + XIP + [12:12] read-write - PROC1_HALTED - Indication that proc1 has halted - [1:1] - read-only + SRAM5 + [11:11] + read-write - PROC0_HALTED - Indication that proc0 has halted - [0:0] - read-only + SRAM4 + [10:10] + read-write - - - - PROC_IN_SYNC_BYPASS - For each bit, if 1, bypass the input synchronizer between that GPIO\n - and the GPIO input register in the SIO. The input synchronizers should\n - generally be unbypassed, to avoid injecting metastabilities into processors.\n - If you're feeling brave, you can bypass to save two cycles of input\n - latency. This register applies to GPIO 0...29. - 0xC - 0x00000000 - - PROC_IN_SYNC_BYPASS - [29:0] + SRAM3 + [9:9] read-write - - - - PROC_IN_SYNC_BYPASS_HI - For each bit, if 1, bypass the input synchronizer between that GPIO\n - and the GPIO input register in the SIO. The input synchronizers should\n - generally be unbypassed, to avoid injecting metastabilities into processors.\n - If you're feeling brave, you can bypass to save two cycles of input\n - latency. This register applies to GPIO 30...35 (the QSPI IOs). - 0x10 - 0x00000000 - - PROC_IN_SYNC_BYPASS_HI - [5:0] + SRAM2 + [8:8] read-write - - - - DBGFORCE - Directly control the SWD debug port of either processor - 0x14 - 0x00000066 - - PROC1_ATTACH - Attach processor 1 debug port to syscfg controls, and disconnect it from external SWD pads. + SRAM1 [7:7] read-write - PROC1_SWCLK - Directly drive processor 1 SWCLK, if PROC1_ATTACH is set + SRAM0 [6:6] read-write - PROC1_SWDI - Directly drive processor 1 SWDIO input, if PROC1_ATTACH is set + ROM [5:5] read-write - PROC1_SWDO - Observe the value of processor 1 SWDIO output. + BUSFABRIC [4:4] - read-only + read-write - PROC0_ATTACH - Attach processor 0 debug port to syscfg controls, and disconnect it from external SWD pads. + RESETS [3:3] read-write - PROC0_SWCLK - Directly drive processor 0 SWCLK, if PROC0_ATTACH is set + CLOCKS [2:2] read-write - PROC0_SWDI - Directly drive processor 0 SWDIO input, if PROC0_ATTACH is set + XOSC [1:1] read-write - PROC0_SWDO - Observe the value of processor 0 SWDIO output. + ROSC [0:0] - read-only + read-write - MEMPOWERDOWN - Control power downs to memories. Set high to power down memories.\n - Use with extreme caution - 0x18 + WDSEL + Set to 1 if this peripheral should be reset when the watchdog fires. + 0x8 0x00000000 - ROM - [7:7] + PROC1 + [16:16] read-write - USB - [6:6] + PROC0 + [15:15] + read-write + + + SIO + [14:14] + read-write + + + VREG_AND_CHIP_RESET + [13:13] + read-write + + + XIP + [12:12] read-write SRAM5 - [5:5] + [11:11] read-write SRAM4 - [4:4] + [10:10] read-write SRAM3 - [3:3] + [9:9] read-write SRAM2 - [2:2] + [8:8] read-write SRAM1 - [1:1] + [7:7] read-write SRAM0 - [0:0] + [6:6] read-write - - - - - - CLOCKS - 1 - 0x40008000 - 0x20 - - 0x0 - 0x1000 - registers - - - CLOCKS_IRQ - 17 - - - - CLK_GPOUT0_CTRL - Clock control, can be changed on-the-fly (except for auxsrc) - 0x0 - 0x00000000 - - NUDGE - An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n - This can be done at any time - [20:20] + ROM + [5:5] read-write - PHASE - This delays the enable signal by up to 3 cycles of the input clock\n - This must be set before the clock is enabled to have any effect - [17:16] + BUSFABRIC + [4:4] read-write - DC50 - Enables duty cycle correction for odd divisors - [12:12] + RESETS + [3:3] read-write - ENABLE - Starts and stops the clock generator cleanly - [11:11] + CLOCKS + [2:2] read-write - KILL - Asynchronously kills the clock generator - [10:10] + XOSC + [1:1] read-write - AUXSRC - Selects the auxiliary clock source, will glitch when switching - [8:5] + ROSC + [0:0] read-write - - - clksrc_pll_sys - 0 - - - clksrc_gpin0 - 1 - - - clksrc_gpin1 - 2 - - - clksrc_pll_usb - 3 - - - rosc_clksrc - 4 - + + + + + DONE + Indicates the peripheral's registers are ready to access. + 0xC + 0x00000000 + + + PROC1 + [16:16] + read-only + + + PROC0 + [15:15] + read-only + + + SIO + [14:14] + read-only + + + VREG_AND_CHIP_RESET + [13:13] + read-only + + + XIP + [12:12] + read-only + + + SRAM5 + [11:11] + read-only + + + SRAM4 + [10:10] + read-only + + + SRAM3 + [9:9] + read-only + + + SRAM2 + [8:8] + read-only + + + SRAM1 + [7:7] + read-only + + + SRAM0 + [6:6] + read-only + + + ROM + [5:5] + read-only + + + BUSFABRIC + [4:4] + read-only + + + RESETS + [3:3] + read-only + + + CLOCKS + [2:2] + read-only + + + XOSC + [1:1] + read-only + + + ROSC + [0:0] + read-only + + + + + + + CLOCKS + 0x40008000 + + 0x0 + 0xC8 + registers + + + CLOCKS_IRQ + 17 + + + + CLK_GPOUT0_CTRL + Clock control, can be changed on-the-fly (except for auxsrc) + 0x0 + 0x00000000 + + + NUDGE + An edge on this signal shifts the phase of the output by 1 cycle of the input clock + This can be done at any time + [20:20] + read-write + + + PHASE + This delays the enable signal by up to 3 cycles of the input clock + This must be set before the clock is enabled to have any effect + [17:16] + read-write + + + DC50 + Enables duty cycle correction for odd divisors + [12:12] + read-write + + + ENABLE + Starts and stops the clock generator cleanly + [11:11] + read-write + + + KILL + Asynchronously kills the clock generator + [10:10] + read-write + + + AUXSRC + Selects the auxiliary clock source, will glitch when switching + [8:5] + read-write + + + clksrc_pll_sys + 0 + + + clksrc_gpin0 + 1 + + + clksrc_gpin1 + 2 + + + clksrc_pll_usb + 3 + + + rosc_clksrc + 4 + xosc_clksrc 5 @@ -1361,11 +957,17 @@ CLK_GPOUT0_SELECTED - Indicates which SRC is currently selected by the glitchless mux (one-hot).\n - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. + Indicates which SRC is currently selected by the glitchless mux (one-hot). 0x8 - read-only 0x00000001 + + + CLK_GPOUT0_SELECTED + This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. + [31:0] + read-only + + CLK_GPOUT1_CTRL @@ -1375,15 +977,15 @@ NUDGE - An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n - This can be done at any time + An edge on this signal shifts the phase of the output by 1 cycle of the input clock + This can be done at any time [20:20] read-write PHASE - This delays the enable signal by up to 3 cycles of the input clock\n - This must be set before the clock is enabled to have any effect + This delays the enable signal by up to 3 cycles of the input clock + This must be set before the clock is enabled to have any effect [17:16] read-write @@ -1481,11 +1083,17 @@ CLK_GPOUT1_SELECTED - Indicates which SRC is currently selected by the glitchless mux (one-hot).\n - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. + Indicates which SRC is currently selected by the glitchless mux (one-hot). 0x14 - read-only 0x00000001 + + + CLK_GPOUT1_SELECTED + This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. + [31:0] + read-only + + CLK_GPOUT2_CTRL @@ -1495,15 +1103,15 @@ NUDGE - An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n - This can be done at any time + An edge on this signal shifts the phase of the output by 1 cycle of the input clock + This can be done at any time [20:20] read-write PHASE - This delays the enable signal by up to 3 cycles of the input clock\n - This must be set before the clock is enabled to have any effect + This delays the enable signal by up to 3 cycles of the input clock + This must be set before the clock is enabled to have any effect [17:16] read-write @@ -1601,11 +1209,17 @@ CLK_GPOUT2_SELECTED - Indicates which SRC is currently selected by the glitchless mux (one-hot).\n - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. + Indicates which SRC is currently selected by the glitchless mux (one-hot). 0x20 - read-only 0x00000001 + + + CLK_GPOUT2_SELECTED + This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. + [31:0] + read-only + + CLK_GPOUT3_CTRL @@ -1615,15 +1229,15 @@ NUDGE - An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n - This can be done at any time + An edge on this signal shifts the phase of the output by 1 cycle of the input clock + This can be done at any time [20:20] read-write PHASE - This delays the enable signal by up to 3 cycles of the input clock\n - This must be set before the clock is enabled to have any effect + This delays the enable signal by up to 3 cycles of the input clock + This must be set before the clock is enabled to have any effect [17:16] read-write @@ -1721,11 +1335,17 @@ CLK_GPOUT3_SELECTED - Indicates which SRC is currently selected by the glitchless mux (one-hot).\n - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. + Indicates which SRC is currently selected by the glitchless mux (one-hot). 0x2C - read-only 0x00000001 + + + CLK_GPOUT3_SELECTED + This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. + [31:0] + read-only + + CLK_REF_CTRL @@ -1791,11 +1411,17 @@ CLK_REF_SELECTED - Indicates which SRC is currently selected by the glitchless mux (one-hot).\n - The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s. + Indicates which SRC is currently selected by the glitchless mux (one-hot). 0x38 - read-only 0x00000001 + + + CLK_REF_SELECTED + The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s. + [31:0] + read-only + + CLK_SYS_CTRL @@ -1875,11 +1501,17 @@ CLK_SYS_SELECTED - Indicates which SRC is currently selected by the glitchless mux (one-hot).\n - The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s. + Indicates which SRC is currently selected by the glitchless mux (one-hot). 0x44 - read-only 0x00000001 + + + CLK_SYS_SELECTED + The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s. + [31:0] + read-only + + CLK_PERI_CTRL @@ -1937,13 +1569,39 @@ + + CLK_PERI_DIV + Clock divisor, can be changed on-the-fly + 0x4C + 0x00000100 + + + INT + Integer component of the divisor, 0 -> divide by 2^16 + [31:8] + read-write + + + FRAC + Fractional component of the divisor + [7:0] + read-write + + + CLK_PERI_SELECTED - Indicates which SRC is currently selected by the glitchless mux (one-hot).\n - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. + Indicates which SRC is currently selected by the glitchless mux (one-hot). 0x50 - read-only 0x00000001 + + + CLK_PERI_SELECTED + This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. + [31:0] + read-only + + CLK_USB_CTRL @@ -1953,15 +1611,15 @@ NUDGE - An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n - This can be done at any time + An edge on this signal shifts the phase of the output by 1 cycle of the input clock + This can be done at any time [20:20] read-write PHASE - This delays the enable signal by up to 3 cycles of the input clock\n - This must be set before the clock is enabled to have any effect + This delays the enable signal by up to 3 cycles of the input clock + This must be set before the clock is enabled to have any effect [17:16] read-write @@ -2027,11 +1685,17 @@ CLK_USB_SELECTED - Indicates which SRC is currently selected by the glitchless mux (one-hot).\n - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. + Indicates which SRC is currently selected by the glitchless mux (one-hot). 0x5C - read-only 0x00000001 + + + CLK_USB_SELECTED + This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. + [31:0] + read-only + + CLK_ADC_CTRL @@ -2041,15 +1705,15 @@ NUDGE - An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n - This can be done at any time + An edge on this signal shifts the phase of the output by 1 cycle of the input clock + This can be done at any time [20:20] read-write PHASE - This delays the enable signal by up to 3 cycles of the input clock\n - This must be set before the clock is enabled to have any effect + This delays the enable signal by up to 3 cycles of the input clock + This must be set before the clock is enabled to have any effect [17:16] read-write @@ -2115,11 +1779,17 @@ CLK_ADC_SELECTED - Indicates which SRC is currently selected by the glitchless mux (one-hot).\n - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. + Indicates which SRC is currently selected by the glitchless mux (one-hot). 0x68 - read-only 0x00000001 + + + CLK_ADC_SELECTED + This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. + [31:0] + read-only + + CLK_RTC_CTRL @@ -2129,15 +1799,15 @@ NUDGE - An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n - This can be done at any time + An edge on this signal shifts the phase of the output by 1 cycle of the input clock + This can be done at any time [20:20] read-write PHASE - This delays the enable signal by up to 3 cycles of the input clock\n - This must be set before the clock is enabled to have any effect + This delays the enable signal by up to 3 cycles of the input clock + This must be set before the clock is enabled to have any effect [17:16] read-write @@ -2209,11 +1879,17 @@ CLK_RTC_SELECTED - Indicates which SRC is currently selected by the glitchless mux (one-hot).\n - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. + Indicates which SRC is currently selected by the glitchless mux (one-hot). 0x74 - read-only 0x00000001 + + + CLK_RTC_SELECTED + This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. + [31:0] + read-only + + CLK_SYS_RESUS_CTRL @@ -2240,8 +1916,8 @@ TIMEOUT - This is expressed as a number of clk_ref cycles\n - and must be >= 2x clk_ref_freq/min_clk_tst_freq + This is expressed as a number of clk_ref cycles + and must be >= 2x clk_ref_freq/min_clk_tst_freq [7:0] read-write @@ -2301,8 +1977,8 @@ FC0_DELAY - Delays the start of frequency counting to allow the mux to settle\n - Delay is measured in multiples of the reference clock period + Delays the start of frequency counting to allow the mux to settle + Delay is measured in multiples of the reference clock period 0x8C 0x00000001 @@ -2315,8 +1991,8 @@ FC0_INTERVAL - The test interval is 0.98us * 2**interval, but let's call it 1us * 2**interval\n - The default gives a test interval of 250us + The test interval is 0.98us * 2**interval, but let's call it 1us * 2**interval + The default gives a test interval of 250us 0x90 0x00000008 @@ -2329,8 +2005,8 @@ FC0_SRC - Clock sent to frequency counter, set to 0 when not required\n - Writing to this register initiates the frequency count + Clock sent to frequency counter, set to 0 when not required + Writing to this register initiates the frequency count 0x94 0x00000000 @@ -2480,162 +2156,162 @@ 0xFFFFFFFF - clk_sys_sram3 + CLK_SYS_SRAM3 [31:31] read-write - clk_sys_sram2 + CLK_SYS_SRAM2 [30:30] read-write - clk_sys_sram1 + CLK_SYS_SRAM1 [29:29] read-write - clk_sys_sram0 + CLK_SYS_SRAM0 [28:28] read-write - clk_sys_spi1 + CLK_SYS_SPI1 [27:27] read-write - clk_peri_spi1 + CLK_PERI_SPI1 [26:26] read-write - clk_sys_spi0 + CLK_SYS_SPI0 [25:25] read-write - clk_peri_spi0 + CLK_PERI_SPI0 [24:24] read-write - clk_sys_sio + CLK_SYS_SIO [23:23] read-write - clk_sys_rtc + CLK_SYS_RTC [22:22] read-write - clk_rtc_rtc + CLK_RTC_RTC [21:21] read-write - clk_sys_rosc + CLK_SYS_ROSC [20:20] read-write - clk_sys_rom + CLK_SYS_ROM [19:19] read-write - clk_sys_resets + CLK_SYS_RESETS [18:18] read-write - clk_sys_pwm + CLK_SYS_PWM [17:17] read-write - clk_sys_psm + CLK_SYS_PSM [16:16] read-write - clk_sys_pll_usb + CLK_SYS_PLL_USB [15:15] read-write - clk_sys_pll_sys + CLK_SYS_PLL_SYS [14:14] read-write - clk_sys_pio1 + CLK_SYS_PIO1 [13:13] read-write - clk_sys_pio0 + CLK_SYS_PIO0 [12:12] read-write - clk_sys_pads + CLK_SYS_PADS [11:11] read-write - clk_sys_vreg_and_chip_reset + CLK_SYS_VREG_AND_CHIP_RESET [10:10] read-write - clk_sys_jtag + CLK_SYS_JTAG [9:9] read-write - clk_sys_io + CLK_SYS_IO [8:8] read-write - clk_sys_i2c1 + CLK_SYS_I2C1 [7:7] read-write - clk_sys_i2c0 + CLK_SYS_I2C0 [6:6] read-write - clk_sys_dma + CLK_SYS_DMA [5:5] read-write - clk_sys_busfabric + CLK_SYS_BUSFABRIC [4:4] read-write - clk_sys_busctrl + CLK_SYS_BUSCTRL [3:3] read-write - clk_sys_adc + CLK_SYS_ADC [2:2] read-write - clk_adc_adc + CLK_ADC_ADC [1:1] read-write - clk_sys_clocks + CLK_SYS_CLOCKS [0:0] read-write @@ -2648,77 +2324,77 @@ 0x00007FFF - clk_sys_xosc + CLK_SYS_XOSC [14:14] read-write - clk_sys_xip + CLK_SYS_XIP [13:13] read-write - clk_sys_watchdog + CLK_SYS_WATCHDOG [12:12] read-write - clk_usb_usbctrl + CLK_USB_USBCTRL [11:11] read-write - clk_sys_usbctrl + CLK_SYS_USBCTRL [10:10] read-write - clk_sys_uart1 + CLK_SYS_UART1 [9:9] read-write - clk_peri_uart1 + CLK_PERI_UART1 [8:8] read-write - clk_sys_uart0 + CLK_SYS_UART0 [7:7] read-write - clk_peri_uart0 + CLK_PERI_UART0 [6:6] read-write - clk_sys_timer + CLK_SYS_TIMER [5:5] read-write - clk_sys_tbman + CLK_SYS_TBMAN [4:4] read-write - clk_sys_sysinfo + CLK_SYS_SYSINFO [3:3] read-write - clk_sys_syscfg + CLK_SYS_SYSCFG [2:2] read-write - clk_sys_sram5 + CLK_SYS_SRAM5 [1:1] read-write - clk_sys_sram4 + CLK_SYS_SRAM4 [0:0] read-write @@ -2731,162 +2407,162 @@ 0xFFFFFFFF - clk_sys_sram3 + CLK_SYS_SRAM3 [31:31] read-write - clk_sys_sram2 + CLK_SYS_SRAM2 [30:30] read-write - clk_sys_sram1 + CLK_SYS_SRAM1 [29:29] read-write - clk_sys_sram0 + CLK_SYS_SRAM0 [28:28] read-write - clk_sys_spi1 + CLK_SYS_SPI1 [27:27] read-write - clk_peri_spi1 + CLK_PERI_SPI1 [26:26] read-write - clk_sys_spi0 + CLK_SYS_SPI0 [25:25] read-write - clk_peri_spi0 + CLK_PERI_SPI0 [24:24] read-write - clk_sys_sio + CLK_SYS_SIO [23:23] read-write - clk_sys_rtc + CLK_SYS_RTC [22:22] read-write - clk_rtc_rtc + CLK_RTC_RTC [21:21] read-write - clk_sys_rosc + CLK_SYS_ROSC [20:20] read-write - clk_sys_rom + CLK_SYS_ROM [19:19] read-write - clk_sys_resets + CLK_SYS_RESETS [18:18] read-write - clk_sys_pwm + CLK_SYS_PWM [17:17] read-write - clk_sys_psm + CLK_SYS_PSM [16:16] read-write - clk_sys_pll_usb + CLK_SYS_PLL_USB [15:15] read-write - clk_sys_pll_sys + CLK_SYS_PLL_SYS [14:14] read-write - clk_sys_pio1 + CLK_SYS_PIO1 [13:13] read-write - clk_sys_pio0 + CLK_SYS_PIO0 [12:12] read-write - clk_sys_pads + CLK_SYS_PADS [11:11] read-write - clk_sys_vreg_and_chip_reset + CLK_SYS_VREG_AND_CHIP_RESET [10:10] read-write - clk_sys_jtag + CLK_SYS_JTAG [9:9] read-write - clk_sys_io + CLK_SYS_IO [8:8] read-write - clk_sys_i2c1 + CLK_SYS_I2C1 [7:7] read-write - clk_sys_i2c0 + CLK_SYS_I2C0 [6:6] read-write - clk_sys_dma + CLK_SYS_DMA [5:5] read-write - clk_sys_busfabric + CLK_SYS_BUSFABRIC [4:4] read-write - clk_sys_busctrl + CLK_SYS_BUSCTRL [3:3] read-write - clk_sys_adc + CLK_SYS_ADC [2:2] read-write - clk_adc_adc + CLK_ADC_ADC [1:1] read-write - clk_sys_clocks + CLK_SYS_CLOCKS [0:0] read-write @@ -2899,77 +2575,77 @@ 0x00007FFF - clk_sys_xosc + CLK_SYS_XOSC [14:14] read-write - clk_sys_xip + CLK_SYS_XIP [13:13] read-write - clk_sys_watchdog + CLK_SYS_WATCHDOG [12:12] read-write - clk_usb_usbctrl + CLK_USB_USBCTRL [11:11] read-write - clk_sys_usbctrl + CLK_SYS_USBCTRL [10:10] read-write - clk_sys_uart1 + CLK_SYS_UART1 [9:9] read-write - clk_peri_uart1 + CLK_PERI_UART1 [8:8] read-write - clk_sys_uart0 + CLK_SYS_UART0 [7:7] read-write - clk_peri_uart0 + CLK_PERI_UART0 [6:6] read-write - clk_sys_timer + CLK_SYS_TIMER [5:5] read-write - clk_sys_tbman + CLK_SYS_TBMAN [4:4] read-write - clk_sys_sysinfo + CLK_SYS_SYSINFO [3:3] read-write - clk_sys_syscfg + CLK_SYS_SYSCFG [2:2] read-write - clk_sys_sram5 + CLK_SYS_SRAM5 [1:1] read-write - clk_sys_sram4 + CLK_SYS_SRAM4 [0:0] read-write @@ -2982,162 +2658,162 @@ 0x00000000 - clk_sys_sram3 + CLK_SYS_SRAM3 [31:31] read-only - clk_sys_sram2 + CLK_SYS_SRAM2 [30:30] read-only - clk_sys_sram1 + CLK_SYS_SRAM1 [29:29] read-only - clk_sys_sram0 + CLK_SYS_SRAM0 [28:28] read-only - clk_sys_spi1 + CLK_SYS_SPI1 [27:27] read-only - clk_peri_spi1 + CLK_PERI_SPI1 [26:26] read-only - clk_sys_spi0 + CLK_SYS_SPI0 [25:25] read-only - clk_peri_spi0 + CLK_PERI_SPI0 [24:24] read-only - clk_sys_sio + CLK_SYS_SIO [23:23] read-only - clk_sys_rtc + CLK_SYS_RTC [22:22] read-only - clk_rtc_rtc + CLK_RTC_RTC [21:21] read-only - clk_sys_rosc + CLK_SYS_ROSC [20:20] read-only - clk_sys_rom + CLK_SYS_ROM [19:19] read-only - clk_sys_resets + CLK_SYS_RESETS [18:18] read-only - clk_sys_pwm + CLK_SYS_PWM [17:17] read-only - clk_sys_psm + CLK_SYS_PSM [16:16] read-only - clk_sys_pll_usb + CLK_SYS_PLL_USB [15:15] read-only - clk_sys_pll_sys + CLK_SYS_PLL_SYS [14:14] read-only - clk_sys_pio1 + CLK_SYS_PIO1 [13:13] read-only - clk_sys_pio0 + CLK_SYS_PIO0 [12:12] read-only - clk_sys_pads + CLK_SYS_PADS [11:11] read-only - clk_sys_vreg_and_chip_reset + CLK_SYS_VREG_AND_CHIP_RESET [10:10] read-only - clk_sys_jtag + CLK_SYS_JTAG [9:9] read-only - clk_sys_io + CLK_SYS_IO [8:8] read-only - clk_sys_i2c1 + CLK_SYS_I2C1 [7:7] read-only - clk_sys_i2c0 + CLK_SYS_I2C0 [6:6] read-only - clk_sys_dma + CLK_SYS_DMA [5:5] read-only - clk_sys_busfabric + CLK_SYS_BUSFABRIC [4:4] read-only - clk_sys_busctrl + CLK_SYS_BUSCTRL [3:3] read-only - clk_sys_adc + CLK_SYS_ADC [2:2] read-only - clk_adc_adc + CLK_ADC_ADC [1:1] read-only - clk_sys_clocks + CLK_SYS_CLOCKS [0:0] read-only @@ -3150,77 +2826,77 @@ 0x00000000 - clk_sys_xosc + CLK_SYS_XOSC [14:14] read-only - clk_sys_xip + CLK_SYS_XIP [13:13] read-only - clk_sys_watchdog + CLK_SYS_WATCHDOG [12:12] read-only - clk_usb_usbctrl + CLK_USB_USBCTRL [11:11] read-only - clk_sys_usbctrl + CLK_SYS_USBCTRL [10:10] read-only - clk_sys_uart1 + CLK_SYS_UART1 [9:9] read-only - clk_peri_uart1 + CLK_PERI_UART1 [8:8] read-only - clk_sys_uart0 + CLK_SYS_UART0 [7:7] read-only - clk_peri_uart0 + CLK_PERI_UART0 [6:6] read-only - clk_sys_timer + CLK_SYS_TIMER [5:5] read-only - clk_sys_tbman + CLK_SYS_TBMAN [4:4] read-only - clk_sys_sysinfo + CLK_SYS_SYSINFO [3:3] read-only - clk_sys_syscfg + CLK_SYS_SYSCFG [2:2] read-only - clk_sys_sram5 + CLK_SYS_SRAM5 [1:1] read-only - clk_sys_sram4 + CLK_SYS_SRAM4 [0:0] read-only @@ -3281,823 +2957,711 @@ - RESETS - 1 - 0x4000C000 - 0x20 + PADS_BANK0 + 0x4001C000 0x0 - 0x1000 + 0x84 registers - RESET - Reset control. If a bit is set it means the peripheral is in reset. 0 means the peripheral's reset is deasserted. + VOLTAGE_SELECT + Voltage select. Per bank control 0x0 - 0x01FFFFFF + 0x00000000 - usbctrl - [24:24] - read-write - - - uart1 - [23:23] - read-write - - - uart0 - [22:22] + VOLTAGE_SELECT + [0:0] read-write + + + 3v3 + Set voltage to 3.3V (DVDD >= 2V5) + 0 + + + 1v8 + Set voltage to 1.8V (DVDD <= 1V8) + 1 + + + + + + 30 + 0x4 + 0-29 + GPIO%s + Pad control register + 0x4 + 0x00000056 + - timer - [21:21] + OD + Output disable. Has priority over output enable from peripherals + [7:7] read-write - tbman - [20:20] + IE + Input enable + [6:6] read-write - sysinfo - [19:19] + DRIVE + Drive strength. + [5:4] read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + - syscfg - [18:18] + PUE + Pull up enable + [3:3] read-write - spi1 - [17:17] + PDE + Pull down enable + [2:2] read-write - spi0 - [16:16] + SCHMITT + Enable schmitt trigger + [1:1] read-write - rtc - [15:15] + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] read-write + + + + SWCLK + Pad control register + 0x7C + 0x000000DA + - pwm - [14:14] + OD + Output disable. Has priority over output enable from peripherals + [7:7] read-write - pll_usb - [13:13] + IE + Input enable + [6:6] read-write - pll_sys - [12:12] + DRIVE + Drive strength. + [5:4] read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + - pio1 - [11:11] + PUE + Pull up enable + [3:3] read-write - pio0 - [10:10] + PDE + Pull down enable + [2:2] read-write - pads_qspi - [9:9] + SCHMITT + Enable schmitt trigger + [1:1] read-write - pads_bank0 - [8:8] + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] read-write + + + + SWD + Pad control register + 0x80 + 0x0000005A + - jtag + OD + Output disable. Has priority over output enable from peripherals [7:7] read-write - io_qspi + IE + Input enable [6:6] read-write - io_bank0 - [5:5] - read-write - - - i2c1 - [4:4] + DRIVE + Drive strength. + [5:4] read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + - i2c0 + PUE + Pull up enable [3:3] read-write - dma + PDE + Pull down enable [2:2] read-write - busctrl + SCHMITT + Enable schmitt trigger [1:1] read-write - adc + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow [0:0] read-write + + + + PADS_QSPI + 0x40020000 + + 0x0 + 0x1C + registers + + - WDSEL - Watchdog select. If a bit is set then the watchdog will reset this peripheral when the watchdog fires. - 0x4 + VOLTAGE_SELECT + Voltage select. Per bank control + 0x0 0x00000000 - usbctrl - [24:24] + VOLTAGE_SELECT + [0:0] read-write + + + 3v3 + Set voltage to 3.3V (DVDD >= 2V5) + 0 + + + 1v8 + Set voltage to 1.8V (DVDD <= 1V8) + 1 + + + + + + GPIO_QSPI_SCLK + Pad control register + 0x4 + 0x00000056 + - uart1 - [23:23] + OD + Output disable. Has priority over output enable from peripherals + [7:7] read-write - uart0 - [22:22] + IE + Input enable + [6:6] read-write - timer - [21:21] + DRIVE + Drive strength. + [5:4] read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + - tbman - [20:20] + PUE + Pull up enable + [3:3] read-write - sysinfo - [19:19] + PDE + Pull down enable + [2:2] read-write - syscfg - [18:18] - read-write - - - spi1 - [17:17] - read-write - - - spi0 - [16:16] + SCHMITT + Enable schmitt trigger + [1:1] read-write - rtc - [15:15] + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] read-write + + + + GPIO_QSPI_SD0 + Pad control register + 0x8 + 0x00000052 + - pwm - [14:14] + OD + Output disable. Has priority over output enable from peripherals + [7:7] read-write - pll_usb - [13:13] + IE + Input enable + [6:6] read-write - pll_sys - [12:12] + DRIVE + Drive strength. + [5:4] read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + - pio1 - [11:11] + PUE + Pull up enable + [3:3] read-write - pio0 - [10:10] + PDE + Pull down enable + [2:2] read-write - pads_qspi - [9:9] + SCHMITT + Enable schmitt trigger + [1:1] read-write - pads_bank0 - [8:8] + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] read-write + + + + GPIO_QSPI_SD1 + Pad control register + 0xC + 0x00000052 + - jtag + OD + Output disable. Has priority over output enable from peripherals [7:7] read-write - io_qspi + IE + Input enable [6:6] read-write - io_bank0 - [5:5] - read-write - - - i2c1 - [4:4] + DRIVE + Drive strength. + [5:4] read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + - i2c0 + PUE + Pull up enable [3:3] read-write - dma + PDE + Pull down enable [2:2] read-write - busctrl + SCHMITT + Enable schmitt trigger [1:1] read-write - adc + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow [0:0] read-write - RESET_DONE - Reset done. If a bit is set then a reset done signal has been returned by the peripheral. This indicates that the peripheral's registers are ready to be accessed. - 0x8 - 0x00000000 + GPIO_QSPI_SD2 + Pad control register + 0x10 + 0x00000052 - usbctrl - [24:24] - read-only - - - uart1 - [23:23] - read-only + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write - uart0 - [22:22] - read-only + IE + Input enable + [6:6] + read-write - timer - [21:21] - read-only + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + - tbman - [20:20] - read-only + PUE + Pull up enable + [3:3] + read-write - sysinfo - [19:19] - read-only + PDE + Pull down enable + [2:2] + read-write - syscfg - [18:18] - read-only + SCHMITT + Enable schmitt trigger + [1:1] + read-write - spi1 - [17:17] - read-only + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + GPIO_QSPI_SD3 + Pad control register + 0x14 + 0x00000052 + - spi0 - [16:16] - read-only + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write - rtc - [15:15] - read-only + IE + Input enable + [6:6] + read-write - pwm - [14:14] - read-only + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + - pll_usb - [13:13] - read-only + PUE + Pull up enable + [3:3] + read-write - pll_sys - [12:12] - read-only + PDE + Pull down enable + [2:2] + read-write - pio1 - [11:11] - read-only + SCHMITT + Enable schmitt trigger + [1:1] + read-write - pio0 - [10:10] - read-only - - - pads_qspi - [9:9] - read-only - - - pads_bank0 - [8:8] - read-only - - - jtag - [7:7] - read-only - - - io_qspi - [6:6] - read-only - - - io_bank0 - [5:5] - read-only - - - i2c1 - [4:4] - read-only - - - i2c0 - [3:3] - read-only - - - dma - [2:2] - read-only - - - busctrl - [1:1] - read-only - - - adc - [0:0] - read-only - - - - - - - PSM - 1 - 0x40010000 - 0x20 - - 0x0 - 0x1000 - registers - - - - FRCE_ON - Force block out of reset (i.e. power it on) - 0x0 - 0x00000000 - - - proc1 - [16:16] - read-write - - - proc0 - [15:15] - read-write - - - sio - [14:14] - read-write - - - vreg_and_chip_reset - [13:13] - read-write - - - xip - [12:12] - read-write - - - sram5 - [11:11] - read-write - - - sram4 - [10:10] - read-write - - - sram3 - [9:9] - read-write - - - sram2 - [8:8] - read-write - - - sram1 - [7:7] - read-write - - - sram0 - [6:6] - read-write - - - rom - [5:5] - read-write - - - busfabric - [4:4] - read-write - - - resets - [3:3] - read-write - - - clocks - [2:2] - read-write - - - xosc - [1:1] - read-write - - - rosc - [0:0] - read-write + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write - FRCE_OFF - Force into reset (i.e. power it off) - 0x4 - 0x00000000 + GPIO_QSPI_SS + Pad control register + 0x18 + 0x0000005A - proc1 - [16:16] - read-write - - - proc0 - [15:15] - read-write - - - sio - [14:14] - read-write - - - vreg_and_chip_reset - [13:13] - read-write - - - xip - [12:12] - read-write - - - sram5 - [11:11] - read-write - - - sram4 - [10:10] - read-write - - - sram3 - [9:9] - read-write - - - sram2 - [8:8] - read-write - - - sram1 + OD + Output disable. Has priority over output enable from peripherals [7:7] read-write - sram0 + IE + Input enable [6:6] read-write - rom - [5:5] - read-write - - - busfabric - [4:4] + DRIVE + Drive strength. + [5:4] read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + - resets + PUE + Pull up enable [3:3] read-write - clocks + PDE + Pull down enable [2:2] read-write - xosc + SCHMITT + Enable schmitt trigger [1:1] read-write - rosc + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow [0:0] read-write - - WDSEL - Set to 1 if this peripheral should be reset when the watchdog fires. - 0x8 - 0x00000000 - - - proc1 - [16:16] - read-write - - - proc0 - [15:15] - read-write - - - sio - [14:14] - read-write - - - vreg_and_chip_reset - [13:13] - read-write - - - xip - [12:12] - read-write - - - sram5 - [11:11] - read-write - - - sram4 - [10:10] - read-write - - - sram3 - [9:9] - read-write - - - sram2 - [8:8] - read-write - - - sram1 - [7:7] - read-write - - - sram0 - [6:6] - read-write - - - rom - [5:5] - read-write - - - busfabric - [4:4] - read-write - - - resets - [3:3] - read-write - - - clocks - [2:2] - read-write - - - xosc - [1:1] - read-write - - - rosc - [0:0] - read-write - - - - - DONE - Indicates the peripheral's registers are ready to access. - 0xC - 0x00000000 - - - proc1 - [16:16] - read-only - - - proc0 - [15:15] - read-only - - - sio - [14:14] - read-only - - - vreg_and_chip_reset - [13:13] - read-only - - - xip - [12:12] - read-only - - - sram5 - [11:11] - read-only - - - sram4 - [10:10] - read-only - - - sram3 - [9:9] - read-only - - - sram2 - [8:8] - read-only - - - sram1 - [7:7] - read-only - - - sram0 - [6:6] - read-only - - - rom - [5:5] - read-only - - - busfabric - [4:4] - read-only - - - resets - [3:3] - read-only - - - clocks - [2:2] - read-only - - - xosc - [1:1] - read-only - - - rosc - [0:0] - read-only - - - - IO_BANK0 - 1 - 0x40014000 - 0x20 + IO_QSPI + 0x40018000 0x0 - 0x1000 + 0x58 registers - IO_IRQ_BANK0 - 13 + IO_IRQ_QSPI + 14 - 30 + 6 0x8 - 0-29 - GPIO%s - Cluster GPIO%s, containing GPIO*_STATUS, GPIO*_CTRL + SCLK,SS,SD0,SD1,SD2,SD3 + GPIO_QSPI%s + Cluster GPIO_QSPI%s, containing GPIO_QSPI_*_STATUS, GPIO_QSPI_*_CTRL 0x0 GPIO_STATUS @@ -4271,64 +3835,21 @@ FUNCSEL - 0-31 -> selects pin function according to the GPIO table. Not all options are valid for all GPIO pins. + 0-31 -> selects pin function according to the gpio table + 31 == NULL [4:0] read-write - FUNCSEL - jtag - Connect to JTAG peripheral + xip_sclk 0 - spi - Connect to matching SPI peripheral - 1 - - - uart - Connect to matching UART peripheral - 2 - - - i2c - Connect to matching I2C peripheral - 3 - - - pwm - Connect to matching PWM peripheral - 4 - - - sio - Use as a GPIO pin (connect to SIO peripheral) + sio_30 5 - - pio0 - Connect to PIO0 peripheral - 6 - - - pio1 - Connect to PIO1 peripheral - 7 - - - clock - Connect to Clock peripheral - 8 - - - usb - Connect to USB peripheral - 9 - null - Connect to nothing 31 @@ -4337,1726 +3858,1292 @@ - 4 - 0x4 - 0-3 - INTR%s + INTR Raw Interrupts - 0xF0 + 0x30 0x00000000 - GPIO7_EDGE_HIGH - [31:31] - read-write - oneToClear - - - GPIO7_EDGE_LOW - [30:30] - read-write - oneToClear - - - GPIO7_LEVEL_HIGH - [29:29] - read-only - - - GPIO7_LEVEL_LOW - [28:28] - read-only - - - GPIO6_EDGE_HIGH - [27:27] - read-write - oneToClear - - - GPIO6_EDGE_LOW - [26:26] - read-write - oneToClear - - - GPIO6_LEVEL_HIGH - [25:25] - read-only - - - GPIO6_LEVEL_LOW - [24:24] - read-only - - - GPIO5_EDGE_HIGH + GPIO_QSPI_SD3_EDGE_HIGH [23:23] read-write oneToClear - GPIO5_EDGE_LOW + GPIO_QSPI_SD3_EDGE_LOW [22:22] read-write oneToClear - GPIO5_LEVEL_HIGH + GPIO_QSPI_SD3_LEVEL_HIGH [21:21] read-only - GPIO5_LEVEL_LOW + GPIO_QSPI_SD3_LEVEL_LOW [20:20] read-only - GPIO4_EDGE_HIGH + GPIO_QSPI_SD2_EDGE_HIGH [19:19] read-write oneToClear - GPIO4_EDGE_LOW + GPIO_QSPI_SD2_EDGE_LOW [18:18] read-write oneToClear - GPIO4_LEVEL_HIGH + GPIO_QSPI_SD2_LEVEL_HIGH [17:17] read-only - GPIO4_LEVEL_LOW + GPIO_QSPI_SD2_LEVEL_LOW [16:16] read-only - GPIO3_EDGE_HIGH + GPIO_QSPI_SD1_EDGE_HIGH [15:15] read-write oneToClear - GPIO3_EDGE_LOW + GPIO_QSPI_SD1_EDGE_LOW [14:14] read-write oneToClear - GPIO3_LEVEL_HIGH + GPIO_QSPI_SD1_LEVEL_HIGH [13:13] read-only - GPIO3_LEVEL_LOW + GPIO_QSPI_SD1_LEVEL_LOW [12:12] read-only - GPIO2_EDGE_HIGH + GPIO_QSPI_SD0_EDGE_HIGH [11:11] read-write oneToClear - GPIO2_EDGE_LOW + GPIO_QSPI_SD0_EDGE_LOW [10:10] read-write oneToClear - GPIO2_LEVEL_HIGH + GPIO_QSPI_SD0_LEVEL_HIGH [9:9] read-only - GPIO2_LEVEL_LOW + GPIO_QSPI_SD0_LEVEL_LOW [8:8] read-only - GPIO1_EDGE_HIGH + GPIO_QSPI_SS_EDGE_HIGH [7:7] read-write oneToClear - GPIO1_EDGE_LOW + GPIO_QSPI_SS_EDGE_LOW [6:6] read-write oneToClear - GPIO1_LEVEL_HIGH + GPIO_QSPI_SS_LEVEL_HIGH [5:5] read-only - GPIO1_LEVEL_LOW + GPIO_QSPI_SS_LEVEL_LOW [4:4] read-only - GPIO0_EDGE_HIGH + GPIO_QSPI_SCLK_EDGE_HIGH [3:3] read-write oneToClear - GPIO0_EDGE_LOW + GPIO_QSPI_SCLK_EDGE_LOW [2:2] read-write oneToClear - GPIO0_LEVEL_HIGH + GPIO_QSPI_SCLK_LEVEL_HIGH [1:1] read-only - GPIO0_LEVEL_LOW + GPIO_QSPI_SCLK_LEVEL_LOW [0:0] read-only - 4 - 0x4 - 0-3 - PROC0_INTE%s + PROC0_INTE Interrupt Enable for proc0 - 0x100 + 0x34 0x00000000 - GPIO7_EDGE_HIGH - [31:31] - read-write - - - GPIO7_EDGE_LOW - [30:30] - read-write - - - GPIO7_LEVEL_HIGH - [29:29] - read-write - - - GPIO7_LEVEL_LOW - [28:28] - read-write - - - GPIO6_EDGE_HIGH - [27:27] - read-write - - - GPIO6_EDGE_LOW - [26:26] - read-write - - - GPIO6_LEVEL_HIGH - [25:25] - read-write - - - GPIO6_LEVEL_LOW - [24:24] - read-write - - - GPIO5_EDGE_HIGH + GPIO_QSPI_SD3_EDGE_HIGH [23:23] read-write - GPIO5_EDGE_LOW + GPIO_QSPI_SD3_EDGE_LOW [22:22] read-write - GPIO5_LEVEL_HIGH + GPIO_QSPI_SD3_LEVEL_HIGH [21:21] read-write - GPIO5_LEVEL_LOW + GPIO_QSPI_SD3_LEVEL_LOW [20:20] read-write - GPIO4_EDGE_HIGH + GPIO_QSPI_SD2_EDGE_HIGH [19:19] read-write - GPIO4_EDGE_LOW + GPIO_QSPI_SD2_EDGE_LOW [18:18] read-write - GPIO4_LEVEL_HIGH + GPIO_QSPI_SD2_LEVEL_HIGH [17:17] read-write - GPIO4_LEVEL_LOW + GPIO_QSPI_SD2_LEVEL_LOW [16:16] read-write - GPIO3_EDGE_HIGH + GPIO_QSPI_SD1_EDGE_HIGH [15:15] read-write - GPIO3_EDGE_LOW + GPIO_QSPI_SD1_EDGE_LOW [14:14] read-write - GPIO3_LEVEL_HIGH + GPIO_QSPI_SD1_LEVEL_HIGH [13:13] read-write - GPIO3_LEVEL_LOW + GPIO_QSPI_SD1_LEVEL_LOW [12:12] read-write - GPIO2_EDGE_HIGH + GPIO_QSPI_SD0_EDGE_HIGH [11:11] read-write - GPIO2_EDGE_LOW + GPIO_QSPI_SD0_EDGE_LOW [10:10] read-write - GPIO2_LEVEL_HIGH + GPIO_QSPI_SD0_LEVEL_HIGH [9:9] read-write - GPIO2_LEVEL_LOW + GPIO_QSPI_SD0_LEVEL_LOW [8:8] read-write - GPIO1_EDGE_HIGH + GPIO_QSPI_SS_EDGE_HIGH [7:7] read-write - GPIO1_EDGE_LOW + GPIO_QSPI_SS_EDGE_LOW [6:6] read-write - GPIO1_LEVEL_HIGH + GPIO_QSPI_SS_LEVEL_HIGH [5:5] read-write - GPIO1_LEVEL_LOW + GPIO_QSPI_SS_LEVEL_LOW [4:4] read-write - GPIO0_EDGE_HIGH + GPIO_QSPI_SCLK_EDGE_HIGH [3:3] read-write - GPIO0_EDGE_LOW + GPIO_QSPI_SCLK_EDGE_LOW [2:2] read-write - GPIO0_LEVEL_HIGH + GPIO_QSPI_SCLK_LEVEL_HIGH [1:1] read-write - GPIO0_LEVEL_LOW + GPIO_QSPI_SCLK_LEVEL_LOW [0:0] read-write - 4 - 0x4 - 0-3 - PROC0_INTF%s + PROC0_INTF Interrupt Force for proc0 - 0x110 + 0x38 0x00000000 - GPIO7_EDGE_HIGH - [31:31] - read-write - - - GPIO7_EDGE_LOW - [30:30] - read-write - - - GPIO7_LEVEL_HIGH - [29:29] - read-write - - - GPIO7_LEVEL_LOW - [28:28] - read-write - - - GPIO6_EDGE_HIGH - [27:27] - read-write - - - GPIO6_EDGE_LOW - [26:26] - read-write - - - GPIO6_LEVEL_HIGH - [25:25] - read-write - - - GPIO6_LEVEL_LOW - [24:24] - read-write - - - GPIO5_EDGE_HIGH + GPIO_QSPI_SD3_EDGE_HIGH [23:23] read-write - GPIO5_EDGE_LOW + GPIO_QSPI_SD3_EDGE_LOW [22:22] read-write - GPIO5_LEVEL_HIGH + GPIO_QSPI_SD3_LEVEL_HIGH [21:21] read-write - GPIO5_LEVEL_LOW + GPIO_QSPI_SD3_LEVEL_LOW [20:20] read-write - GPIO4_EDGE_HIGH + GPIO_QSPI_SD2_EDGE_HIGH [19:19] read-write - GPIO4_EDGE_LOW + GPIO_QSPI_SD2_EDGE_LOW [18:18] read-write - GPIO4_LEVEL_HIGH + GPIO_QSPI_SD2_LEVEL_HIGH [17:17] read-write - GPIO4_LEVEL_LOW + GPIO_QSPI_SD2_LEVEL_LOW [16:16] read-write - GPIO3_EDGE_HIGH + GPIO_QSPI_SD1_EDGE_HIGH [15:15] read-write - GPIO3_EDGE_LOW + GPIO_QSPI_SD1_EDGE_LOW [14:14] read-write - GPIO3_LEVEL_HIGH + GPIO_QSPI_SD1_LEVEL_HIGH [13:13] read-write - GPIO3_LEVEL_LOW + GPIO_QSPI_SD1_LEVEL_LOW [12:12] read-write - GPIO2_EDGE_HIGH + GPIO_QSPI_SD0_EDGE_HIGH [11:11] read-write - GPIO2_EDGE_LOW + GPIO_QSPI_SD0_EDGE_LOW [10:10] read-write - GPIO2_LEVEL_HIGH + GPIO_QSPI_SD0_LEVEL_HIGH [9:9] read-write - GPIO2_LEVEL_LOW + GPIO_QSPI_SD0_LEVEL_LOW [8:8] read-write - GPIO1_EDGE_HIGH + GPIO_QSPI_SS_EDGE_HIGH [7:7] read-write - GPIO1_EDGE_LOW + GPIO_QSPI_SS_EDGE_LOW [6:6] read-write - GPIO1_LEVEL_HIGH + GPIO_QSPI_SS_LEVEL_HIGH [5:5] read-write - GPIO1_LEVEL_LOW + GPIO_QSPI_SS_LEVEL_LOW [4:4] read-write - GPIO0_EDGE_HIGH + GPIO_QSPI_SCLK_EDGE_HIGH [3:3] read-write - GPIO0_EDGE_LOW + GPIO_QSPI_SCLK_EDGE_LOW [2:2] read-write - GPIO0_LEVEL_HIGH + GPIO_QSPI_SCLK_LEVEL_HIGH [1:1] read-write - GPIO0_LEVEL_LOW + GPIO_QSPI_SCLK_LEVEL_LOW [0:0] read-write - 4 - 0x4 - 0-3 - PROC0_INTS%s + PROC0_INTS Interrupt status after masking & forcing for proc0 - 0x120 + 0x3C 0x00000000 - GPIO7_EDGE_HIGH - [31:31] + GPIO_QSPI_SD3_EDGE_HIGH + [23:23] read-only - GPIO7_EDGE_LOW - [30:30] + GPIO_QSPI_SD3_EDGE_LOW + [22:22] read-only - GPIO7_LEVEL_HIGH - [29:29] + GPIO_QSPI_SD3_LEVEL_HIGH + [21:21] read-only - GPIO7_LEVEL_LOW - [28:28] + GPIO_QSPI_SD3_LEVEL_LOW + [20:20] read-only - GPIO6_EDGE_HIGH - [27:27] + GPIO_QSPI_SD2_EDGE_HIGH + [19:19] read-only - GPIO6_EDGE_LOW - [26:26] + GPIO_QSPI_SD2_EDGE_LOW + [18:18] read-only - GPIO6_LEVEL_HIGH - [25:25] + GPIO_QSPI_SD2_LEVEL_HIGH + [17:17] read-only - GPIO6_LEVEL_LOW - [24:24] + GPIO_QSPI_SD2_LEVEL_LOW + [16:16] read-only - GPIO5_EDGE_HIGH - [23:23] + GPIO_QSPI_SD1_EDGE_HIGH + [15:15] read-only - GPIO5_EDGE_LOW - [22:22] + GPIO_QSPI_SD1_EDGE_LOW + [14:14] read-only - GPIO5_LEVEL_HIGH - [21:21] + GPIO_QSPI_SD1_LEVEL_HIGH + [13:13] read-only - GPIO5_LEVEL_LOW - [20:20] + GPIO_QSPI_SD1_LEVEL_LOW + [12:12] read-only - GPIO4_EDGE_HIGH - [19:19] - read-only - - - GPIO4_EDGE_LOW - [18:18] - read-only - - - GPIO4_LEVEL_HIGH - [17:17] - read-only - - - GPIO4_LEVEL_LOW - [16:16] - read-only - - - GPIO3_EDGE_HIGH - [15:15] - read-only - - - GPIO3_EDGE_LOW - [14:14] - read-only - - - GPIO3_LEVEL_HIGH - [13:13] - read-only - - - GPIO3_LEVEL_LOW - [12:12] - read-only - - - GPIO2_EDGE_HIGH + GPIO_QSPI_SD0_EDGE_HIGH [11:11] read-only - GPIO2_EDGE_LOW + GPIO_QSPI_SD0_EDGE_LOW [10:10] read-only - GPIO2_LEVEL_HIGH + GPIO_QSPI_SD0_LEVEL_HIGH [9:9] read-only - GPIO2_LEVEL_LOW + GPIO_QSPI_SD0_LEVEL_LOW [8:8] read-only - GPIO1_EDGE_HIGH + GPIO_QSPI_SS_EDGE_HIGH [7:7] read-only - GPIO1_EDGE_LOW + GPIO_QSPI_SS_EDGE_LOW [6:6] read-only - GPIO1_LEVEL_HIGH + GPIO_QSPI_SS_LEVEL_HIGH [5:5] read-only - GPIO1_LEVEL_LOW + GPIO_QSPI_SS_LEVEL_LOW [4:4] read-only - GPIO0_EDGE_HIGH + GPIO_QSPI_SCLK_EDGE_HIGH [3:3] read-only - GPIO0_EDGE_LOW + GPIO_QSPI_SCLK_EDGE_LOW [2:2] read-only - GPIO0_LEVEL_HIGH + GPIO_QSPI_SCLK_LEVEL_HIGH [1:1] read-only - GPIO0_LEVEL_LOW + GPIO_QSPI_SCLK_LEVEL_LOW [0:0] read-only - 4 - 0x4 - 0-3 - PROC1_INTE%s + PROC1_INTE Interrupt Enable for proc1 - 0x130 + 0x40 0x00000000 - GPIO7_EDGE_HIGH - [31:31] - read-write - - - GPIO7_EDGE_LOW - [30:30] - read-write - - - GPIO7_LEVEL_HIGH - [29:29] - read-write - - - GPIO7_LEVEL_LOW - [28:28] - read-write - - - GPIO6_EDGE_HIGH - [27:27] - read-write - - - GPIO6_EDGE_LOW - [26:26] - read-write - - - GPIO6_LEVEL_HIGH - [25:25] - read-write - - - GPIO6_LEVEL_LOW - [24:24] - read-write - - - GPIO5_EDGE_HIGH + GPIO_QSPI_SD3_EDGE_HIGH [23:23] read-write - GPIO5_EDGE_LOW + GPIO_QSPI_SD3_EDGE_LOW [22:22] read-write - GPIO5_LEVEL_HIGH + GPIO_QSPI_SD3_LEVEL_HIGH [21:21] read-write - GPIO5_LEVEL_LOW + GPIO_QSPI_SD3_LEVEL_LOW [20:20] read-write - GPIO4_EDGE_HIGH + GPIO_QSPI_SD2_EDGE_HIGH [19:19] read-write - GPIO4_EDGE_LOW + GPIO_QSPI_SD2_EDGE_LOW [18:18] read-write - GPIO4_LEVEL_HIGH + GPIO_QSPI_SD2_LEVEL_HIGH [17:17] read-write - GPIO4_LEVEL_LOW + GPIO_QSPI_SD2_LEVEL_LOW [16:16] read-write - GPIO3_EDGE_HIGH + GPIO_QSPI_SD1_EDGE_HIGH [15:15] read-write - GPIO3_EDGE_LOW + GPIO_QSPI_SD1_EDGE_LOW [14:14] read-write - GPIO3_LEVEL_HIGH + GPIO_QSPI_SD1_LEVEL_HIGH [13:13] read-write - GPIO3_LEVEL_LOW + GPIO_QSPI_SD1_LEVEL_LOW [12:12] read-write - GPIO2_EDGE_HIGH + GPIO_QSPI_SD0_EDGE_HIGH [11:11] read-write - GPIO2_EDGE_LOW + GPIO_QSPI_SD0_EDGE_LOW [10:10] read-write - GPIO2_LEVEL_HIGH + GPIO_QSPI_SD0_LEVEL_HIGH [9:9] read-write - GPIO2_LEVEL_LOW + GPIO_QSPI_SD0_LEVEL_LOW [8:8] read-write - GPIO1_EDGE_HIGH + GPIO_QSPI_SS_EDGE_HIGH [7:7] read-write - GPIO1_EDGE_LOW + GPIO_QSPI_SS_EDGE_LOW [6:6] read-write - GPIO1_LEVEL_HIGH + GPIO_QSPI_SS_LEVEL_HIGH [5:5] read-write - GPIO1_LEVEL_LOW + GPIO_QSPI_SS_LEVEL_LOW [4:4] read-write - GPIO0_EDGE_HIGH + GPIO_QSPI_SCLK_EDGE_HIGH [3:3] read-write - GPIO0_EDGE_LOW + GPIO_QSPI_SCLK_EDGE_LOW [2:2] read-write - GPIO0_LEVEL_HIGH + GPIO_QSPI_SCLK_LEVEL_HIGH [1:1] read-write - GPIO0_LEVEL_LOW + GPIO_QSPI_SCLK_LEVEL_LOW [0:0] read-write - 4 - 0x4 - 0-3 - PROC1_INTF%s + PROC1_INTF Interrupt Force for proc1 - 0x140 + 0x44 0x00000000 - GPIO7_EDGE_HIGH - [31:31] - read-write - - - GPIO7_EDGE_LOW - [30:30] - read-write - - - GPIO7_LEVEL_HIGH - [29:29] - read-write - - - GPIO7_LEVEL_LOW - [28:28] - read-write - - - GPIO6_EDGE_HIGH - [27:27] - read-write - - - GPIO6_EDGE_LOW - [26:26] - read-write - - - GPIO6_LEVEL_HIGH - [25:25] - read-write - - - GPIO6_LEVEL_LOW - [24:24] - read-write - - - GPIO5_EDGE_HIGH + GPIO_QSPI_SD3_EDGE_HIGH [23:23] read-write - GPIO5_EDGE_LOW + GPIO_QSPI_SD3_EDGE_LOW [22:22] read-write - GPIO5_LEVEL_HIGH + GPIO_QSPI_SD3_LEVEL_HIGH [21:21] read-write - GPIO5_LEVEL_LOW + GPIO_QSPI_SD3_LEVEL_LOW [20:20] read-write - GPIO4_EDGE_HIGH + GPIO_QSPI_SD2_EDGE_HIGH [19:19] read-write - GPIO4_EDGE_LOW + GPIO_QSPI_SD2_EDGE_LOW [18:18] read-write - GPIO4_LEVEL_HIGH + GPIO_QSPI_SD2_LEVEL_HIGH [17:17] read-write - GPIO4_LEVEL_LOW + GPIO_QSPI_SD2_LEVEL_LOW [16:16] read-write - GPIO3_EDGE_HIGH + GPIO_QSPI_SD1_EDGE_HIGH [15:15] read-write - GPIO3_EDGE_LOW + GPIO_QSPI_SD1_EDGE_LOW [14:14] read-write - GPIO3_LEVEL_HIGH + GPIO_QSPI_SD1_LEVEL_HIGH [13:13] read-write - GPIO3_LEVEL_LOW + GPIO_QSPI_SD1_LEVEL_LOW [12:12] read-write - GPIO2_EDGE_HIGH + GPIO_QSPI_SD0_EDGE_HIGH [11:11] read-write - GPIO2_EDGE_LOW + GPIO_QSPI_SD0_EDGE_LOW [10:10] read-write - GPIO2_LEVEL_HIGH + GPIO_QSPI_SD0_LEVEL_HIGH [9:9] read-write - GPIO2_LEVEL_LOW + GPIO_QSPI_SD0_LEVEL_LOW [8:8] read-write - GPIO1_EDGE_HIGH + GPIO_QSPI_SS_EDGE_HIGH [7:7] read-write - GPIO1_EDGE_LOW + GPIO_QSPI_SS_EDGE_LOW [6:6] read-write - GPIO1_LEVEL_HIGH + GPIO_QSPI_SS_LEVEL_HIGH [5:5] read-write - GPIO1_LEVEL_LOW + GPIO_QSPI_SS_LEVEL_LOW [4:4] read-write - GPIO0_EDGE_HIGH + GPIO_QSPI_SCLK_EDGE_HIGH [3:3] read-write - GPIO0_EDGE_LOW + GPIO_QSPI_SCLK_EDGE_LOW [2:2] read-write - GPIO0_LEVEL_HIGH + GPIO_QSPI_SCLK_LEVEL_HIGH [1:1] read-write - GPIO0_LEVEL_LOW + GPIO_QSPI_SCLK_LEVEL_LOW [0:0] read-write - 4 - 0x4 - 0-3 - PROC1_INTS%s + PROC1_INTS Interrupt status after masking & forcing for proc1 - 0x150 + 0x48 0x00000000 - GPIO7_EDGE_HIGH - [31:31] - read-only - - - GPIO7_EDGE_LOW - [30:30] - read-only - - - GPIO7_LEVEL_HIGH - [29:29] - read-only - - - GPIO7_LEVEL_LOW - [28:28] - read-only - - - GPIO6_EDGE_HIGH - [27:27] - read-only - - - GPIO6_EDGE_LOW - [26:26] - read-only - - - GPIO6_LEVEL_HIGH - [25:25] - read-only - - - GPIO6_LEVEL_LOW - [24:24] - read-only - - - GPIO5_EDGE_HIGH + GPIO_QSPI_SD3_EDGE_HIGH [23:23] read-only - GPIO5_EDGE_LOW + GPIO_QSPI_SD3_EDGE_LOW [22:22] read-only - GPIO5_LEVEL_HIGH + GPIO_QSPI_SD3_LEVEL_HIGH [21:21] read-only - GPIO5_LEVEL_LOW + GPIO_QSPI_SD3_LEVEL_LOW [20:20] read-only - GPIO4_EDGE_HIGH + GPIO_QSPI_SD2_EDGE_HIGH [19:19] read-only - GPIO4_EDGE_LOW + GPIO_QSPI_SD2_EDGE_LOW [18:18] read-only - GPIO4_LEVEL_HIGH + GPIO_QSPI_SD2_LEVEL_HIGH [17:17] read-only - GPIO4_LEVEL_LOW + GPIO_QSPI_SD2_LEVEL_LOW [16:16] read-only - GPIO3_EDGE_HIGH + GPIO_QSPI_SD1_EDGE_HIGH [15:15] read-only - GPIO3_EDGE_LOW + GPIO_QSPI_SD1_EDGE_LOW [14:14] read-only - GPIO3_LEVEL_HIGH + GPIO_QSPI_SD1_LEVEL_HIGH [13:13] read-only - GPIO3_LEVEL_LOW + GPIO_QSPI_SD1_LEVEL_LOW [12:12] read-only - GPIO2_EDGE_HIGH + GPIO_QSPI_SD0_EDGE_HIGH [11:11] read-only - GPIO2_EDGE_LOW + GPIO_QSPI_SD0_EDGE_LOW [10:10] read-only - GPIO2_LEVEL_HIGH + GPIO_QSPI_SD0_LEVEL_HIGH [9:9] read-only - GPIO2_LEVEL_LOW + GPIO_QSPI_SD0_LEVEL_LOW [8:8] read-only - GPIO1_EDGE_HIGH + GPIO_QSPI_SS_EDGE_HIGH [7:7] read-only - GPIO1_EDGE_LOW + GPIO_QSPI_SS_EDGE_LOW [6:6] read-only - GPIO1_LEVEL_HIGH + GPIO_QSPI_SS_LEVEL_HIGH [5:5] read-only - GPIO1_LEVEL_LOW + GPIO_QSPI_SS_LEVEL_LOW [4:4] read-only - GPIO0_EDGE_HIGH + GPIO_QSPI_SCLK_EDGE_HIGH [3:3] read-only - GPIO0_EDGE_LOW + GPIO_QSPI_SCLK_EDGE_LOW [2:2] read-only - GPIO0_LEVEL_HIGH + GPIO_QSPI_SCLK_LEVEL_HIGH [1:1] read-only - GPIO0_LEVEL_LOW + GPIO_QSPI_SCLK_LEVEL_LOW [0:0] read-only - 4 - 0x4 - 0-3 - DORMANT_WAKE_INTE%s + DORMANT_WAKE_INTE Interrupt Enable for dormant_wake - 0x160 + 0x4C 0x00000000 - GPIO7_EDGE_HIGH - [31:31] - read-write - - - GPIO7_EDGE_LOW - [30:30] - read-write - - - GPIO7_LEVEL_HIGH - [29:29] - read-write - - - GPIO7_LEVEL_LOW - [28:28] - read-write - - - GPIO6_EDGE_HIGH - [27:27] - read-write - - - GPIO6_EDGE_LOW - [26:26] - read-write - - - GPIO6_LEVEL_HIGH - [25:25] - read-write - - - GPIO6_LEVEL_LOW - [24:24] - read-write - - - GPIO5_EDGE_HIGH + GPIO_QSPI_SD3_EDGE_HIGH [23:23] read-write - GPIO5_EDGE_LOW + GPIO_QSPI_SD3_EDGE_LOW [22:22] read-write - GPIO5_LEVEL_HIGH + GPIO_QSPI_SD3_LEVEL_HIGH [21:21] read-write - GPIO5_LEVEL_LOW + GPIO_QSPI_SD3_LEVEL_LOW [20:20] read-write - GPIO4_EDGE_HIGH + GPIO_QSPI_SD2_EDGE_HIGH [19:19] read-write - GPIO4_EDGE_LOW + GPIO_QSPI_SD2_EDGE_LOW [18:18] read-write - GPIO4_LEVEL_HIGH + GPIO_QSPI_SD2_LEVEL_HIGH [17:17] read-write - GPIO4_LEVEL_LOW + GPIO_QSPI_SD2_LEVEL_LOW [16:16] read-write - GPIO3_EDGE_HIGH + GPIO_QSPI_SD1_EDGE_HIGH [15:15] read-write - GPIO3_EDGE_LOW + GPIO_QSPI_SD1_EDGE_LOW [14:14] read-write - GPIO3_LEVEL_HIGH + GPIO_QSPI_SD1_LEVEL_HIGH [13:13] read-write - GPIO3_LEVEL_LOW + GPIO_QSPI_SD1_LEVEL_LOW [12:12] read-write - GPIO2_EDGE_HIGH + GPIO_QSPI_SD0_EDGE_HIGH [11:11] read-write - GPIO2_EDGE_LOW + GPIO_QSPI_SD0_EDGE_LOW [10:10] read-write - GPIO2_LEVEL_HIGH + GPIO_QSPI_SD0_LEVEL_HIGH [9:9] read-write - GPIO2_LEVEL_LOW + GPIO_QSPI_SD0_LEVEL_LOW [8:8] read-write - GPIO1_EDGE_HIGH + GPIO_QSPI_SS_EDGE_HIGH [7:7] read-write - GPIO1_EDGE_LOW + GPIO_QSPI_SS_EDGE_LOW [6:6] read-write - GPIO1_LEVEL_HIGH + GPIO_QSPI_SS_LEVEL_HIGH [5:5] read-write - GPIO1_LEVEL_LOW + GPIO_QSPI_SS_LEVEL_LOW [4:4] read-write - GPIO0_EDGE_HIGH + GPIO_QSPI_SCLK_EDGE_HIGH [3:3] read-write - GPIO0_EDGE_LOW + GPIO_QSPI_SCLK_EDGE_LOW [2:2] read-write - GPIO0_LEVEL_HIGH + GPIO_QSPI_SCLK_LEVEL_HIGH [1:1] read-write - GPIO0_LEVEL_LOW + GPIO_QSPI_SCLK_LEVEL_LOW [0:0] read-write - 4 - 0x4 - 0-3 - DORMANT_WAKE_INTF%s + DORMANT_WAKE_INTF Interrupt Force for dormant_wake - 0x170 + 0x50 0x00000000 - GPIO7_EDGE_HIGH - [31:31] + GPIO_QSPI_SD3_EDGE_HIGH + [23:23] read-write - GPIO7_EDGE_LOW - [30:30] + GPIO_QSPI_SD3_EDGE_LOW + [22:22] read-write - GPIO7_LEVEL_HIGH - [29:29] + GPIO_QSPI_SD3_LEVEL_HIGH + [21:21] read-write - GPIO7_LEVEL_LOW - [28:28] + GPIO_QSPI_SD3_LEVEL_LOW + [20:20] read-write - GPIO6_EDGE_HIGH - [27:27] + GPIO_QSPI_SD2_EDGE_HIGH + [19:19] read-write - GPIO6_EDGE_LOW - [26:26] + GPIO_QSPI_SD2_EDGE_LOW + [18:18] read-write - GPIO6_LEVEL_HIGH - [25:25] + GPIO_QSPI_SD2_LEVEL_HIGH + [17:17] read-write - GPIO6_LEVEL_LOW - [24:24] + GPIO_QSPI_SD2_LEVEL_LOW + [16:16] read-write - GPIO5_EDGE_HIGH - [23:23] + GPIO_QSPI_SD1_EDGE_HIGH + [15:15] read-write - GPIO5_EDGE_LOW - [22:22] + GPIO_QSPI_SD1_EDGE_LOW + [14:14] read-write - GPIO5_LEVEL_HIGH - [21:21] + GPIO_QSPI_SD1_LEVEL_HIGH + [13:13] read-write - GPIO5_LEVEL_LOW - [20:20] + GPIO_QSPI_SD1_LEVEL_LOW + [12:12] read-write - GPIO4_EDGE_HIGH - [19:19] + GPIO_QSPI_SD0_EDGE_HIGH + [11:11] read-write - GPIO4_EDGE_LOW - [18:18] + GPIO_QSPI_SD0_EDGE_LOW + [10:10] read-write - GPIO4_LEVEL_HIGH - [17:17] + GPIO_QSPI_SD0_LEVEL_HIGH + [9:9] read-write - GPIO4_LEVEL_LOW - [16:16] - read-write - - - GPIO3_EDGE_HIGH - [15:15] - read-write - - - GPIO3_EDGE_LOW - [14:14] - read-write - - - GPIO3_LEVEL_HIGH - [13:13] - read-write - - - GPIO3_LEVEL_LOW - [12:12] - read-write - - - GPIO2_EDGE_HIGH - [11:11] - read-write - - - GPIO2_EDGE_LOW - [10:10] - read-write - - - GPIO2_LEVEL_HIGH - [9:9] - read-write - - - GPIO2_LEVEL_LOW + GPIO_QSPI_SD0_LEVEL_LOW [8:8] read-write - GPIO1_EDGE_HIGH + GPIO_QSPI_SS_EDGE_HIGH [7:7] read-write - GPIO1_EDGE_LOW + GPIO_QSPI_SS_EDGE_LOW [6:6] read-write - GPIO1_LEVEL_HIGH + GPIO_QSPI_SS_LEVEL_HIGH [5:5] read-write - GPIO1_LEVEL_LOW + GPIO_QSPI_SS_LEVEL_LOW [4:4] read-write - GPIO0_EDGE_HIGH + GPIO_QSPI_SCLK_EDGE_HIGH [3:3] read-write - GPIO0_EDGE_LOW + GPIO_QSPI_SCLK_EDGE_LOW [2:2] read-write - GPIO0_LEVEL_HIGH + GPIO_QSPI_SCLK_LEVEL_HIGH [1:1] read-write - GPIO0_LEVEL_LOW + GPIO_QSPI_SCLK_LEVEL_LOW [0:0] read-write - 4 - 0x4 - 0-3 - DORMANT_WAKE_INTS%s + DORMANT_WAKE_INTS Interrupt status after masking & forcing for dormant_wake - 0x180 + 0x54 0x00000000 - GPIO7_EDGE_HIGH - [31:31] - read-only - - - GPIO7_EDGE_LOW - [30:30] - read-only - - - GPIO7_LEVEL_HIGH - [29:29] - read-only - - - GPIO7_LEVEL_LOW - [28:28] - read-only - - - GPIO6_EDGE_HIGH - [27:27] - read-only - - - GPIO6_EDGE_LOW - [26:26] - read-only - - - GPIO6_LEVEL_HIGH - [25:25] - read-only - - - GPIO6_LEVEL_LOW - [24:24] - read-only - - - GPIO5_EDGE_HIGH + GPIO_QSPI_SD3_EDGE_HIGH [23:23] read-only - GPIO5_EDGE_LOW + GPIO_QSPI_SD3_EDGE_LOW [22:22] read-only - GPIO5_LEVEL_HIGH + GPIO_QSPI_SD3_LEVEL_HIGH [21:21] read-only - GPIO5_LEVEL_LOW + GPIO_QSPI_SD3_LEVEL_LOW [20:20] read-only - GPIO4_EDGE_HIGH + GPIO_QSPI_SD2_EDGE_HIGH [19:19] read-only - GPIO4_EDGE_LOW + GPIO_QSPI_SD2_EDGE_LOW [18:18] read-only - GPIO4_LEVEL_HIGH + GPIO_QSPI_SD2_LEVEL_HIGH [17:17] read-only - GPIO4_LEVEL_LOW + GPIO_QSPI_SD2_LEVEL_LOW [16:16] read-only - GPIO3_EDGE_HIGH + GPIO_QSPI_SD1_EDGE_HIGH [15:15] read-only - GPIO3_EDGE_LOW + GPIO_QSPI_SD1_EDGE_LOW [14:14] read-only - GPIO3_LEVEL_HIGH + GPIO_QSPI_SD1_LEVEL_HIGH [13:13] read-only - GPIO3_LEVEL_LOW + GPIO_QSPI_SD1_LEVEL_LOW [12:12] read-only - GPIO2_EDGE_HIGH + GPIO_QSPI_SD0_EDGE_HIGH [11:11] read-only - GPIO2_EDGE_LOW + GPIO_QSPI_SD0_EDGE_LOW [10:10] read-only - GPIO2_LEVEL_HIGH + GPIO_QSPI_SD0_LEVEL_HIGH [9:9] read-only - GPIO2_LEVEL_LOW + GPIO_QSPI_SD0_LEVEL_LOW [8:8] read-only - GPIO1_EDGE_HIGH + GPIO_QSPI_SS_EDGE_HIGH [7:7] read-only - GPIO1_EDGE_LOW + GPIO_QSPI_SS_EDGE_LOW [6:6] read-only - GPIO1_LEVEL_HIGH + GPIO_QSPI_SS_LEVEL_HIGH [5:5] read-only - GPIO1_LEVEL_LOW + GPIO_QSPI_SS_LEVEL_LOW [4:4] read-only - GPIO0_EDGE_HIGH + GPIO_QSPI_SCLK_EDGE_HIGH [3:3] read-only - GPIO0_EDGE_LOW + GPIO_QSPI_SCLK_EDGE_LOW [2:2] read-only - GPIO0_LEVEL_HIGH + GPIO_QSPI_SCLK_LEVEL_HIGH [1:1] read-only - GPIO0_LEVEL_LOW + GPIO_QSPI_SCLK_LEVEL_LOW [0:0] read-only @@ -6065,26 +5152,24 @@ - IO_QSPI - 1 - 0x40018000 - 0x20 + IO_BANK0 + 0x40014000 0x0 - 0x1000 + 0x190 registers - IO_IRQ_QSPI - 14 + IO_IRQ_BANK0 + 13 - 6 + 30 0x8 - SCLK,SS,SD0,SD1,SD2,SD3 - GPIO_QSPI%s - Cluster GPIO_QSPI%s, containing GPIO_QSPI_*_STATUS, GPIO_QSPI_*_CTRL + 0-29 + GPIO%s + Cluster GPIO%s, containing GPIO*_STATUS, GPIO*_CTRL 0x0 GPIO_STATUS @@ -6258,21 +5343,64 @@ FUNCSEL - 0-31 -> selects pin function according to the gpio table\n - 31 == NULL + 0-31 -> selects pin function according to the GPIO table. Not all options are valid for all GPIO pins. [4:0] read-write + FUNCSEL - xip_sclk + jtag + Connect to JTAG peripheral 0 - sio_30 + spi + Connect to matching SPI peripheral + 1 + + + uart + Connect to matching UART peripheral + 2 + + + i2c + Connect to matching I2C peripheral + 3 + + + pwm + Connect to matching PWM peripheral + 4 + + + sio + Use as a GPIO pin (connect to SIO peripheral) 5 + + pio0 + Connect to PIO0 peripheral + 6 + + + pio1 + Connect to PIO1 peripheral + 7 + + + clock + Connect to Clock peripheral + 8 + + + usb + Connect to USB peripheral + 9 + null + Connect to nothing 31 @@ -6281,1292 +5409,1726 @@ - INTR + 4 + 0x4 + 0-3 + INTR%s Raw Interrupts - 0x30 + 0xF0 0x00000000 - GPIO_QSPI_SD3_EDGE_HIGH - [23:23] + GPIO7_EDGE_HIGH + [31:31] read-write oneToClear - GPIO_QSPI_SD3_EDGE_LOW - [22:22] + GPIO7_EDGE_LOW + [30:30] read-write oneToClear - GPIO_QSPI_SD3_LEVEL_HIGH - [21:21] + GPIO7_LEVEL_HIGH + [29:29] read-only - GPIO_QSPI_SD3_LEVEL_LOW - [20:20] + GPIO7_LEVEL_LOW + [28:28] read-only - GPIO_QSPI_SD2_EDGE_HIGH - [19:19] + GPIO6_EDGE_HIGH + [27:27] read-write oneToClear - GPIO_QSPI_SD2_EDGE_LOW - [18:18] + GPIO6_EDGE_LOW + [26:26] read-write oneToClear - GPIO_QSPI_SD2_LEVEL_HIGH - [17:17] + GPIO6_LEVEL_HIGH + [25:25] read-only - GPIO_QSPI_SD2_LEVEL_LOW - [16:16] - read-only + GPIO6_LEVEL_LOW + [24:24] + read-only - GPIO_QSPI_SD1_EDGE_HIGH + GPIO5_EDGE_HIGH + [23:23] + read-write + oneToClear + + + GPIO5_EDGE_LOW + [22:22] + read-write + oneToClear + + + GPIO5_LEVEL_HIGH + [21:21] + read-only + + + GPIO5_LEVEL_LOW + [20:20] + read-only + + + GPIO4_EDGE_HIGH + [19:19] + read-write + oneToClear + + + GPIO4_EDGE_LOW + [18:18] + read-write + oneToClear + + + GPIO4_LEVEL_HIGH + [17:17] + read-only + + + GPIO4_LEVEL_LOW + [16:16] + read-only + + + GPIO3_EDGE_HIGH [15:15] read-write oneToClear - GPIO_QSPI_SD1_EDGE_LOW + GPIO3_EDGE_LOW [14:14] read-write oneToClear - GPIO_QSPI_SD1_LEVEL_HIGH + GPIO3_LEVEL_HIGH [13:13] read-only - GPIO_QSPI_SD1_LEVEL_LOW + GPIO3_LEVEL_LOW [12:12] read-only - GPIO_QSPI_SD0_EDGE_HIGH + GPIO2_EDGE_HIGH [11:11] read-write oneToClear - GPIO_QSPI_SD0_EDGE_LOW + GPIO2_EDGE_LOW [10:10] read-write oneToClear - GPIO_QSPI_SD0_LEVEL_HIGH + GPIO2_LEVEL_HIGH [9:9] read-only - GPIO_QSPI_SD0_LEVEL_LOW + GPIO2_LEVEL_LOW [8:8] read-only - GPIO_QSPI_SS_EDGE_HIGH + GPIO1_EDGE_HIGH [7:7] read-write oneToClear - GPIO_QSPI_SS_EDGE_LOW + GPIO1_EDGE_LOW [6:6] read-write oneToClear - GPIO_QSPI_SS_LEVEL_HIGH + GPIO1_LEVEL_HIGH [5:5] read-only - GPIO_QSPI_SS_LEVEL_LOW + GPIO1_LEVEL_LOW [4:4] read-only - GPIO_QSPI_SCLK_EDGE_HIGH + GPIO0_EDGE_HIGH [3:3] read-write oneToClear - GPIO_QSPI_SCLK_EDGE_LOW + GPIO0_EDGE_LOW [2:2] read-write oneToClear - GPIO_QSPI_SCLK_LEVEL_HIGH + GPIO0_LEVEL_HIGH [1:1] read-only - GPIO_QSPI_SCLK_LEVEL_LOW + GPIO0_LEVEL_LOW [0:0] read-only - PROC0_INTE + 4 + 0x4 + 0-3 + PROC0_INTE%s Interrupt Enable for proc0 - 0x34 + 0x100 0x00000000 - GPIO_QSPI_SD3_EDGE_HIGH + GPIO7_EDGE_HIGH + [31:31] + read-write + + + GPIO7_EDGE_LOW + [30:30] + read-write + + + GPIO7_LEVEL_HIGH + [29:29] + read-write + + + GPIO7_LEVEL_LOW + [28:28] + read-write + + + GPIO6_EDGE_HIGH + [27:27] + read-write + + + GPIO6_EDGE_LOW + [26:26] + read-write + + + GPIO6_LEVEL_HIGH + [25:25] + read-write + + + GPIO6_LEVEL_LOW + [24:24] + read-write + + + GPIO5_EDGE_HIGH [23:23] read-write - GPIO_QSPI_SD3_EDGE_LOW + GPIO5_EDGE_LOW [22:22] read-write - GPIO_QSPI_SD3_LEVEL_HIGH + GPIO5_LEVEL_HIGH [21:21] read-write - GPIO_QSPI_SD3_LEVEL_LOW + GPIO5_LEVEL_LOW [20:20] read-write - GPIO_QSPI_SD2_EDGE_HIGH + GPIO4_EDGE_HIGH [19:19] read-write - GPIO_QSPI_SD2_EDGE_LOW + GPIO4_EDGE_LOW [18:18] read-write - GPIO_QSPI_SD2_LEVEL_HIGH + GPIO4_LEVEL_HIGH [17:17] read-write - GPIO_QSPI_SD2_LEVEL_LOW + GPIO4_LEVEL_LOW [16:16] read-write - GPIO_QSPI_SD1_EDGE_HIGH + GPIO3_EDGE_HIGH [15:15] read-write - GPIO_QSPI_SD1_EDGE_LOW + GPIO3_EDGE_LOW [14:14] read-write - GPIO_QSPI_SD1_LEVEL_HIGH + GPIO3_LEVEL_HIGH [13:13] read-write - GPIO_QSPI_SD1_LEVEL_LOW + GPIO3_LEVEL_LOW [12:12] read-write - GPIO_QSPI_SD0_EDGE_HIGH + GPIO2_EDGE_HIGH [11:11] read-write - GPIO_QSPI_SD0_EDGE_LOW + GPIO2_EDGE_LOW [10:10] read-write - GPIO_QSPI_SD0_LEVEL_HIGH + GPIO2_LEVEL_HIGH [9:9] read-write - GPIO_QSPI_SD0_LEVEL_LOW + GPIO2_LEVEL_LOW [8:8] read-write - GPIO_QSPI_SS_EDGE_HIGH + GPIO1_EDGE_HIGH [7:7] read-write - GPIO_QSPI_SS_EDGE_LOW + GPIO1_EDGE_LOW [6:6] read-write - GPIO_QSPI_SS_LEVEL_HIGH + GPIO1_LEVEL_HIGH [5:5] read-write - GPIO_QSPI_SS_LEVEL_LOW + GPIO1_LEVEL_LOW [4:4] read-write - GPIO_QSPI_SCLK_EDGE_HIGH + GPIO0_EDGE_HIGH [3:3] read-write - GPIO_QSPI_SCLK_EDGE_LOW + GPIO0_EDGE_LOW [2:2] read-write - GPIO_QSPI_SCLK_LEVEL_HIGH + GPIO0_LEVEL_HIGH [1:1] read-write - GPIO_QSPI_SCLK_LEVEL_LOW + GPIO0_LEVEL_LOW [0:0] read-write - PROC0_INTF + 4 + 0x4 + 0-3 + PROC0_INTF%s Interrupt Force for proc0 - 0x38 + 0x110 0x00000000 - GPIO_QSPI_SD3_EDGE_HIGH + GPIO7_EDGE_HIGH + [31:31] + read-write + + + GPIO7_EDGE_LOW + [30:30] + read-write + + + GPIO7_LEVEL_HIGH + [29:29] + read-write + + + GPIO7_LEVEL_LOW + [28:28] + read-write + + + GPIO6_EDGE_HIGH + [27:27] + read-write + + + GPIO6_EDGE_LOW + [26:26] + read-write + + + GPIO6_LEVEL_HIGH + [25:25] + read-write + + + GPIO6_LEVEL_LOW + [24:24] + read-write + + + GPIO5_EDGE_HIGH [23:23] read-write - GPIO_QSPI_SD3_EDGE_LOW + GPIO5_EDGE_LOW [22:22] read-write - GPIO_QSPI_SD3_LEVEL_HIGH + GPIO5_LEVEL_HIGH [21:21] read-write - GPIO_QSPI_SD3_LEVEL_LOW + GPIO5_LEVEL_LOW [20:20] read-write - GPIO_QSPI_SD2_EDGE_HIGH + GPIO4_EDGE_HIGH [19:19] read-write - GPIO_QSPI_SD2_EDGE_LOW + GPIO4_EDGE_LOW [18:18] read-write - GPIO_QSPI_SD2_LEVEL_HIGH + GPIO4_LEVEL_HIGH [17:17] read-write - GPIO_QSPI_SD2_LEVEL_LOW + GPIO4_LEVEL_LOW [16:16] read-write - GPIO_QSPI_SD1_EDGE_HIGH + GPIO3_EDGE_HIGH [15:15] read-write - GPIO_QSPI_SD1_EDGE_LOW + GPIO3_EDGE_LOW [14:14] read-write - GPIO_QSPI_SD1_LEVEL_HIGH + GPIO3_LEVEL_HIGH [13:13] read-write - GPIO_QSPI_SD1_LEVEL_LOW + GPIO3_LEVEL_LOW [12:12] read-write - GPIO_QSPI_SD0_EDGE_HIGH + GPIO2_EDGE_HIGH [11:11] read-write - GPIO_QSPI_SD0_EDGE_LOW + GPIO2_EDGE_LOW [10:10] read-write - GPIO_QSPI_SD0_LEVEL_HIGH + GPIO2_LEVEL_HIGH [9:9] read-write - GPIO_QSPI_SD0_LEVEL_LOW + GPIO2_LEVEL_LOW [8:8] read-write - GPIO_QSPI_SS_EDGE_HIGH + GPIO1_EDGE_HIGH [7:7] read-write - GPIO_QSPI_SS_EDGE_LOW + GPIO1_EDGE_LOW [6:6] read-write - GPIO_QSPI_SS_LEVEL_HIGH + GPIO1_LEVEL_HIGH [5:5] read-write - GPIO_QSPI_SS_LEVEL_LOW + GPIO1_LEVEL_LOW [4:4] read-write - GPIO_QSPI_SCLK_EDGE_HIGH + GPIO0_EDGE_HIGH [3:3] read-write - GPIO_QSPI_SCLK_EDGE_LOW + GPIO0_EDGE_LOW [2:2] read-write - GPIO_QSPI_SCLK_LEVEL_HIGH + GPIO0_LEVEL_HIGH [1:1] read-write - GPIO_QSPI_SCLK_LEVEL_LOW + GPIO0_LEVEL_LOW [0:0] read-write - PROC0_INTS + 4 + 0x4 + 0-3 + PROC0_INTS%s Interrupt status after masking & forcing for proc0 - 0x3C + 0x120 0x00000000 - GPIO_QSPI_SD3_EDGE_HIGH + GPIO7_EDGE_HIGH + [31:31] + read-only + + + GPIO7_EDGE_LOW + [30:30] + read-only + + + GPIO7_LEVEL_HIGH + [29:29] + read-only + + + GPIO7_LEVEL_LOW + [28:28] + read-only + + + GPIO6_EDGE_HIGH + [27:27] + read-only + + + GPIO6_EDGE_LOW + [26:26] + read-only + + + GPIO6_LEVEL_HIGH + [25:25] + read-only + + + GPIO6_LEVEL_LOW + [24:24] + read-only + + + GPIO5_EDGE_HIGH [23:23] read-only - GPIO_QSPI_SD3_EDGE_LOW + GPIO5_EDGE_LOW [22:22] read-only - GPIO_QSPI_SD3_LEVEL_HIGH + GPIO5_LEVEL_HIGH [21:21] read-only - GPIO_QSPI_SD3_LEVEL_LOW + GPIO5_LEVEL_LOW [20:20] read-only - GPIO_QSPI_SD2_EDGE_HIGH + GPIO4_EDGE_HIGH [19:19] read-only - GPIO_QSPI_SD2_EDGE_LOW + GPIO4_EDGE_LOW [18:18] read-only - GPIO_QSPI_SD2_LEVEL_HIGH + GPIO4_LEVEL_HIGH [17:17] read-only - GPIO_QSPI_SD2_LEVEL_LOW + GPIO4_LEVEL_LOW [16:16] read-only - GPIO_QSPI_SD1_EDGE_HIGH + GPIO3_EDGE_HIGH [15:15] read-only - GPIO_QSPI_SD1_EDGE_LOW + GPIO3_EDGE_LOW [14:14] read-only - GPIO_QSPI_SD1_LEVEL_HIGH + GPIO3_LEVEL_HIGH [13:13] read-only - GPIO_QSPI_SD1_LEVEL_LOW + GPIO3_LEVEL_LOW [12:12] read-only - GPIO_QSPI_SD0_EDGE_HIGH + GPIO2_EDGE_HIGH [11:11] read-only - GPIO_QSPI_SD0_EDGE_LOW + GPIO2_EDGE_LOW [10:10] read-only - GPIO_QSPI_SD0_LEVEL_HIGH + GPIO2_LEVEL_HIGH [9:9] read-only - GPIO_QSPI_SD0_LEVEL_LOW + GPIO2_LEVEL_LOW [8:8] read-only - GPIO_QSPI_SS_EDGE_HIGH + GPIO1_EDGE_HIGH [7:7] read-only - GPIO_QSPI_SS_EDGE_LOW + GPIO1_EDGE_LOW [6:6] read-only - GPIO_QSPI_SS_LEVEL_HIGH + GPIO1_LEVEL_HIGH [5:5] read-only - GPIO_QSPI_SS_LEVEL_LOW + GPIO1_LEVEL_LOW [4:4] read-only - GPIO_QSPI_SCLK_EDGE_HIGH + GPIO0_EDGE_HIGH [3:3] read-only - GPIO_QSPI_SCLK_EDGE_LOW + GPIO0_EDGE_LOW [2:2] read-only - GPIO_QSPI_SCLK_LEVEL_HIGH + GPIO0_LEVEL_HIGH [1:1] read-only - GPIO_QSPI_SCLK_LEVEL_LOW + GPIO0_LEVEL_LOW [0:0] read-only - PROC1_INTE + 4 + 0x4 + 0-3 + PROC1_INTE%s Interrupt Enable for proc1 - 0x40 + 0x130 0x00000000 - GPIO_QSPI_SD3_EDGE_HIGH + GPIO7_EDGE_HIGH + [31:31] + read-write + + + GPIO7_EDGE_LOW + [30:30] + read-write + + + GPIO7_LEVEL_HIGH + [29:29] + read-write + + + GPIO7_LEVEL_LOW + [28:28] + read-write + + + GPIO6_EDGE_HIGH + [27:27] + read-write + + + GPIO6_EDGE_LOW + [26:26] + read-write + + + GPIO6_LEVEL_HIGH + [25:25] + read-write + + + GPIO6_LEVEL_LOW + [24:24] + read-write + + + GPIO5_EDGE_HIGH [23:23] read-write - GPIO_QSPI_SD3_EDGE_LOW + GPIO5_EDGE_LOW [22:22] read-write - GPIO_QSPI_SD3_LEVEL_HIGH + GPIO5_LEVEL_HIGH [21:21] read-write - GPIO_QSPI_SD3_LEVEL_LOW + GPIO5_LEVEL_LOW [20:20] read-write - GPIO_QSPI_SD2_EDGE_HIGH + GPIO4_EDGE_HIGH [19:19] read-write - GPIO_QSPI_SD2_EDGE_LOW + GPIO4_EDGE_LOW [18:18] read-write - GPIO_QSPI_SD2_LEVEL_HIGH + GPIO4_LEVEL_HIGH [17:17] read-write - GPIO_QSPI_SD2_LEVEL_LOW + GPIO4_LEVEL_LOW [16:16] read-write - GPIO_QSPI_SD1_EDGE_HIGH + GPIO3_EDGE_HIGH [15:15] read-write - GPIO_QSPI_SD1_EDGE_LOW + GPIO3_EDGE_LOW [14:14] read-write - GPIO_QSPI_SD1_LEVEL_HIGH + GPIO3_LEVEL_HIGH [13:13] read-write - GPIO_QSPI_SD1_LEVEL_LOW + GPIO3_LEVEL_LOW [12:12] read-write - GPIO_QSPI_SD0_EDGE_HIGH + GPIO2_EDGE_HIGH [11:11] read-write - GPIO_QSPI_SD0_EDGE_LOW + GPIO2_EDGE_LOW [10:10] read-write - GPIO_QSPI_SD0_LEVEL_HIGH + GPIO2_LEVEL_HIGH [9:9] read-write - GPIO_QSPI_SD0_LEVEL_LOW + GPIO2_LEVEL_LOW [8:8] read-write - GPIO_QSPI_SS_EDGE_HIGH + GPIO1_EDGE_HIGH [7:7] read-write - GPIO_QSPI_SS_EDGE_LOW + GPIO1_EDGE_LOW [6:6] read-write - GPIO_QSPI_SS_LEVEL_HIGH + GPIO1_LEVEL_HIGH [5:5] read-write - GPIO_QSPI_SS_LEVEL_LOW + GPIO1_LEVEL_LOW [4:4] read-write - GPIO_QSPI_SCLK_EDGE_HIGH + GPIO0_EDGE_HIGH [3:3] read-write - GPIO_QSPI_SCLK_EDGE_LOW + GPIO0_EDGE_LOW [2:2] read-write - GPIO_QSPI_SCLK_LEVEL_HIGH + GPIO0_LEVEL_HIGH [1:1] read-write - GPIO_QSPI_SCLK_LEVEL_LOW + GPIO0_LEVEL_LOW [0:0] read-write - PROC1_INTF + 4 + 0x4 + 0-3 + PROC1_INTF%s Interrupt Force for proc1 - 0x44 + 0x140 0x00000000 - GPIO_QSPI_SD3_EDGE_HIGH - [23:23] + GPIO7_EDGE_HIGH + [31:31] read-write - GPIO_QSPI_SD3_EDGE_LOW - [22:22] + GPIO7_EDGE_LOW + [30:30] read-write - GPIO_QSPI_SD3_LEVEL_HIGH - [21:21] + GPIO7_LEVEL_HIGH + [29:29] read-write - GPIO_QSPI_SD3_LEVEL_LOW - [20:20] + GPIO7_LEVEL_LOW + [28:28] read-write - GPIO_QSPI_SD2_EDGE_HIGH - [19:19] + GPIO6_EDGE_HIGH + [27:27] read-write - GPIO_QSPI_SD2_EDGE_LOW - [18:18] + GPIO6_EDGE_LOW + [26:26] read-write - GPIO_QSPI_SD2_LEVEL_HIGH - [17:17] + GPIO6_LEVEL_HIGH + [25:25] read-write - GPIO_QSPI_SD2_LEVEL_LOW - [16:16] + GPIO6_LEVEL_LOW + [24:24] read-write - GPIO_QSPI_SD1_EDGE_HIGH - [15:15] + GPIO5_EDGE_HIGH + [23:23] read-write - GPIO_QSPI_SD1_EDGE_LOW - [14:14] + GPIO5_EDGE_LOW + [22:22] read-write - GPIO_QSPI_SD1_LEVEL_HIGH - [13:13] + GPIO5_LEVEL_HIGH + [21:21] read-write - GPIO_QSPI_SD1_LEVEL_LOW - [12:12] + GPIO5_LEVEL_LOW + [20:20] read-write - GPIO_QSPI_SD0_EDGE_HIGH + GPIO4_EDGE_HIGH + [19:19] + read-write + + + GPIO4_EDGE_LOW + [18:18] + read-write + + + GPIO4_LEVEL_HIGH + [17:17] + read-write + + + GPIO4_LEVEL_LOW + [16:16] + read-write + + + GPIO3_EDGE_HIGH + [15:15] + read-write + + + GPIO3_EDGE_LOW + [14:14] + read-write + + + GPIO3_LEVEL_HIGH + [13:13] + read-write + + + GPIO3_LEVEL_LOW + [12:12] + read-write + + + GPIO2_EDGE_HIGH [11:11] read-write - GPIO_QSPI_SD0_EDGE_LOW + GPIO2_EDGE_LOW [10:10] read-write - GPIO_QSPI_SD0_LEVEL_HIGH + GPIO2_LEVEL_HIGH [9:9] read-write - GPIO_QSPI_SD0_LEVEL_LOW + GPIO2_LEVEL_LOW [8:8] read-write - GPIO_QSPI_SS_EDGE_HIGH + GPIO1_EDGE_HIGH [7:7] read-write - GPIO_QSPI_SS_EDGE_LOW + GPIO1_EDGE_LOW [6:6] read-write - GPIO_QSPI_SS_LEVEL_HIGH + GPIO1_LEVEL_HIGH [5:5] read-write - GPIO_QSPI_SS_LEVEL_LOW + GPIO1_LEVEL_LOW [4:4] read-write - GPIO_QSPI_SCLK_EDGE_HIGH + GPIO0_EDGE_HIGH [3:3] read-write - GPIO_QSPI_SCLK_EDGE_LOW + GPIO0_EDGE_LOW [2:2] read-write - GPIO_QSPI_SCLK_LEVEL_HIGH + GPIO0_LEVEL_HIGH [1:1] read-write - GPIO_QSPI_SCLK_LEVEL_LOW + GPIO0_LEVEL_LOW [0:0] read-write - PROC1_INTS + 4 + 0x4 + 0-3 + PROC1_INTS%s Interrupt status after masking & forcing for proc1 - 0x48 + 0x150 0x00000000 - GPIO_QSPI_SD3_EDGE_HIGH + GPIO7_EDGE_HIGH + [31:31] + read-only + + + GPIO7_EDGE_LOW + [30:30] + read-only + + + GPIO7_LEVEL_HIGH + [29:29] + read-only + + + GPIO7_LEVEL_LOW + [28:28] + read-only + + + GPIO6_EDGE_HIGH + [27:27] + read-only + + + GPIO6_EDGE_LOW + [26:26] + read-only + + + GPIO6_LEVEL_HIGH + [25:25] + read-only + + + GPIO6_LEVEL_LOW + [24:24] + read-only + + + GPIO5_EDGE_HIGH [23:23] read-only - GPIO_QSPI_SD3_EDGE_LOW + GPIO5_EDGE_LOW [22:22] read-only - GPIO_QSPI_SD3_LEVEL_HIGH + GPIO5_LEVEL_HIGH [21:21] read-only - GPIO_QSPI_SD3_LEVEL_LOW + GPIO5_LEVEL_LOW [20:20] read-only - GPIO_QSPI_SD2_EDGE_HIGH + GPIO4_EDGE_HIGH [19:19] read-only - GPIO_QSPI_SD2_EDGE_LOW + GPIO4_EDGE_LOW [18:18] read-only - GPIO_QSPI_SD2_LEVEL_HIGH + GPIO4_LEVEL_HIGH [17:17] read-only - GPIO_QSPI_SD2_LEVEL_LOW + GPIO4_LEVEL_LOW [16:16] read-only - GPIO_QSPI_SD1_EDGE_HIGH + GPIO3_EDGE_HIGH [15:15] read-only - GPIO_QSPI_SD1_EDGE_LOW + GPIO3_EDGE_LOW [14:14] read-only - GPIO_QSPI_SD1_LEVEL_HIGH + GPIO3_LEVEL_HIGH [13:13] read-only - GPIO_QSPI_SD1_LEVEL_LOW + GPIO3_LEVEL_LOW [12:12] read-only - GPIO_QSPI_SD0_EDGE_HIGH + GPIO2_EDGE_HIGH [11:11] read-only - GPIO_QSPI_SD0_EDGE_LOW + GPIO2_EDGE_LOW [10:10] read-only - GPIO_QSPI_SD0_LEVEL_HIGH + GPIO2_LEVEL_HIGH [9:9] read-only - GPIO_QSPI_SD0_LEVEL_LOW + GPIO2_LEVEL_LOW [8:8] read-only - GPIO_QSPI_SS_EDGE_HIGH + GPIO1_EDGE_HIGH [7:7] read-only - GPIO_QSPI_SS_EDGE_LOW + GPIO1_EDGE_LOW [6:6] read-only - GPIO_QSPI_SS_LEVEL_HIGH + GPIO1_LEVEL_HIGH [5:5] read-only - GPIO_QSPI_SS_LEVEL_LOW + GPIO1_LEVEL_LOW [4:4] read-only - GPIO_QSPI_SCLK_EDGE_HIGH + GPIO0_EDGE_HIGH [3:3] read-only - GPIO_QSPI_SCLK_EDGE_LOW + GPIO0_EDGE_LOW [2:2] read-only - GPIO_QSPI_SCLK_LEVEL_HIGH + GPIO0_LEVEL_HIGH [1:1] read-only - GPIO_QSPI_SCLK_LEVEL_LOW + GPIO0_LEVEL_LOW [0:0] read-only - DORMANT_WAKE_INTE + 4 + 0x4 + 0-3 + DORMANT_WAKE_INTE%s Interrupt Enable for dormant_wake - 0x4C + 0x160 0x00000000 - GPIO_QSPI_SD3_EDGE_HIGH + GPIO7_EDGE_HIGH + [31:31] + read-write + + + GPIO7_EDGE_LOW + [30:30] + read-write + + + GPIO7_LEVEL_HIGH + [29:29] + read-write + + + GPIO7_LEVEL_LOW + [28:28] + read-write + + + GPIO6_EDGE_HIGH + [27:27] + read-write + + + GPIO6_EDGE_LOW + [26:26] + read-write + + + GPIO6_LEVEL_HIGH + [25:25] + read-write + + + GPIO6_LEVEL_LOW + [24:24] + read-write + + + GPIO5_EDGE_HIGH [23:23] read-write - GPIO_QSPI_SD3_EDGE_LOW + GPIO5_EDGE_LOW [22:22] read-write - GPIO_QSPI_SD3_LEVEL_HIGH + GPIO5_LEVEL_HIGH [21:21] read-write - GPIO_QSPI_SD3_LEVEL_LOW + GPIO5_LEVEL_LOW [20:20] read-write - GPIO_QSPI_SD2_EDGE_HIGH + GPIO4_EDGE_HIGH [19:19] read-write - GPIO_QSPI_SD2_EDGE_LOW + GPIO4_EDGE_LOW [18:18] read-write - GPIO_QSPI_SD2_LEVEL_HIGH + GPIO4_LEVEL_HIGH [17:17] read-write - GPIO_QSPI_SD2_LEVEL_LOW + GPIO4_LEVEL_LOW [16:16] read-write - GPIO_QSPI_SD1_EDGE_HIGH + GPIO3_EDGE_HIGH [15:15] read-write - GPIO_QSPI_SD1_EDGE_LOW + GPIO3_EDGE_LOW [14:14] read-write - GPIO_QSPI_SD1_LEVEL_HIGH + GPIO3_LEVEL_HIGH [13:13] read-write - GPIO_QSPI_SD1_LEVEL_LOW + GPIO3_LEVEL_LOW [12:12] read-write - GPIO_QSPI_SD0_EDGE_HIGH + GPIO2_EDGE_HIGH [11:11] read-write - GPIO_QSPI_SD0_EDGE_LOW + GPIO2_EDGE_LOW [10:10] read-write - GPIO_QSPI_SD0_LEVEL_HIGH + GPIO2_LEVEL_HIGH [9:9] read-write - GPIO_QSPI_SD0_LEVEL_LOW + GPIO2_LEVEL_LOW [8:8] read-write - GPIO_QSPI_SS_EDGE_HIGH + GPIO1_EDGE_HIGH [7:7] read-write - GPIO_QSPI_SS_EDGE_LOW + GPIO1_EDGE_LOW [6:6] read-write - GPIO_QSPI_SS_LEVEL_HIGH + GPIO1_LEVEL_HIGH [5:5] read-write - GPIO_QSPI_SS_LEVEL_LOW + GPIO1_LEVEL_LOW [4:4] read-write - GPIO_QSPI_SCLK_EDGE_HIGH + GPIO0_EDGE_HIGH [3:3] read-write - GPIO_QSPI_SCLK_EDGE_LOW + GPIO0_EDGE_LOW [2:2] read-write - GPIO_QSPI_SCLK_LEVEL_HIGH + GPIO0_LEVEL_HIGH [1:1] read-write - GPIO_QSPI_SCLK_LEVEL_LOW + GPIO0_LEVEL_LOW [0:0] read-write - DORMANT_WAKE_INTF + 4 + 0x4 + 0-3 + DORMANT_WAKE_INTF%s Interrupt Force for dormant_wake - 0x50 + 0x170 0x00000000 - GPIO_QSPI_SD3_EDGE_HIGH + GPIO7_EDGE_HIGH + [31:31] + read-write + + + GPIO7_EDGE_LOW + [30:30] + read-write + + + GPIO7_LEVEL_HIGH + [29:29] + read-write + + + GPIO7_LEVEL_LOW + [28:28] + read-write + + + GPIO6_EDGE_HIGH + [27:27] + read-write + + + GPIO6_EDGE_LOW + [26:26] + read-write + + + GPIO6_LEVEL_HIGH + [25:25] + read-write + + + GPIO6_LEVEL_LOW + [24:24] + read-write + + + GPIO5_EDGE_HIGH [23:23] read-write - GPIO_QSPI_SD3_EDGE_LOW + GPIO5_EDGE_LOW [22:22] read-write - GPIO_QSPI_SD3_LEVEL_HIGH + GPIO5_LEVEL_HIGH [21:21] read-write - GPIO_QSPI_SD3_LEVEL_LOW + GPIO5_LEVEL_LOW [20:20] read-write - GPIO_QSPI_SD2_EDGE_HIGH + GPIO4_EDGE_HIGH [19:19] read-write - GPIO_QSPI_SD2_EDGE_LOW + GPIO4_EDGE_LOW [18:18] read-write - GPIO_QSPI_SD2_LEVEL_HIGH + GPIO4_LEVEL_HIGH [17:17] read-write - GPIO_QSPI_SD2_LEVEL_LOW + GPIO4_LEVEL_LOW [16:16] read-write - GPIO_QSPI_SD1_EDGE_HIGH + GPIO3_EDGE_HIGH [15:15] read-write - GPIO_QSPI_SD1_EDGE_LOW + GPIO3_EDGE_LOW [14:14] read-write - GPIO_QSPI_SD1_LEVEL_HIGH + GPIO3_LEVEL_HIGH [13:13] read-write - GPIO_QSPI_SD1_LEVEL_LOW + GPIO3_LEVEL_LOW [12:12] read-write - GPIO_QSPI_SD0_EDGE_HIGH + GPIO2_EDGE_HIGH [11:11] read-write - GPIO_QSPI_SD0_EDGE_LOW + GPIO2_EDGE_LOW [10:10] read-write - GPIO_QSPI_SD0_LEVEL_HIGH + GPIO2_LEVEL_HIGH [9:9] read-write - GPIO_QSPI_SD0_LEVEL_LOW + GPIO2_LEVEL_LOW [8:8] read-write - GPIO_QSPI_SS_EDGE_HIGH + GPIO1_EDGE_HIGH [7:7] read-write - GPIO_QSPI_SS_EDGE_LOW + GPIO1_EDGE_LOW [6:6] read-write - GPIO_QSPI_SS_LEVEL_HIGH + GPIO1_LEVEL_HIGH [5:5] read-write - GPIO_QSPI_SS_LEVEL_LOW + GPIO1_LEVEL_LOW [4:4] read-write - GPIO_QSPI_SCLK_EDGE_HIGH + GPIO0_EDGE_HIGH [3:3] read-write - GPIO_QSPI_SCLK_EDGE_LOW + GPIO0_EDGE_LOW [2:2] read-write - GPIO_QSPI_SCLK_LEVEL_HIGH + GPIO0_LEVEL_HIGH [1:1] read-write - GPIO_QSPI_SCLK_LEVEL_LOW + GPIO0_LEVEL_LOW [0:0] read-write - DORMANT_WAKE_INTS + 4 + 0x4 + 0-3 + DORMANT_WAKE_INTS%s Interrupt status after masking & forcing for dormant_wake - 0x54 + 0x180 0x00000000 - GPIO_QSPI_SD3_EDGE_HIGH + GPIO7_EDGE_HIGH + [31:31] + read-only + + + GPIO7_EDGE_LOW + [30:30] + read-only + + + GPIO7_LEVEL_HIGH + [29:29] + read-only + + + GPIO7_LEVEL_LOW + [28:28] + read-only + + + GPIO6_EDGE_HIGH + [27:27] + read-only + + + GPIO6_EDGE_LOW + [26:26] + read-only + + + GPIO6_LEVEL_HIGH + [25:25] + read-only + + + GPIO6_LEVEL_LOW + [24:24] + read-only + + + GPIO5_EDGE_HIGH [23:23] read-only - GPIO_QSPI_SD3_EDGE_LOW + GPIO5_EDGE_LOW [22:22] read-only - GPIO_QSPI_SD3_LEVEL_HIGH + GPIO5_LEVEL_HIGH [21:21] read-only - GPIO_QSPI_SD3_LEVEL_LOW + GPIO5_LEVEL_LOW [20:20] read-only - GPIO_QSPI_SD2_EDGE_HIGH + GPIO4_EDGE_HIGH [19:19] read-only - GPIO_QSPI_SD2_EDGE_LOW + GPIO4_EDGE_LOW [18:18] read-only - GPIO_QSPI_SD2_LEVEL_HIGH + GPIO4_LEVEL_HIGH [17:17] read-only - GPIO_QSPI_SD2_LEVEL_LOW + GPIO4_LEVEL_LOW [16:16] read-only - GPIO_QSPI_SD1_EDGE_HIGH + GPIO3_EDGE_HIGH [15:15] read-only - GPIO_QSPI_SD1_EDGE_LOW + GPIO3_EDGE_LOW [14:14] read-only - GPIO_QSPI_SD1_LEVEL_HIGH + GPIO3_LEVEL_HIGH [13:13] read-only - GPIO_QSPI_SD1_LEVEL_LOW + GPIO3_LEVEL_LOW [12:12] read-only - GPIO_QSPI_SD0_EDGE_HIGH + GPIO2_EDGE_HIGH [11:11] read-only - GPIO_QSPI_SD0_EDGE_LOW + GPIO2_EDGE_LOW [10:10] read-only - GPIO_QSPI_SD0_LEVEL_HIGH + GPIO2_LEVEL_HIGH [9:9] read-only - GPIO_QSPI_SD0_LEVEL_LOW + GPIO2_LEVEL_LOW [8:8] read-only - GPIO_QSPI_SS_EDGE_HIGH + GPIO1_EDGE_HIGH [7:7] read-only - GPIO_QSPI_SS_EDGE_LOW + GPIO1_EDGE_LOW [6:6] read-only - GPIO_QSPI_SS_LEVEL_HIGH + GPIO1_LEVEL_HIGH [5:5] read-only - GPIO_QSPI_SS_LEVEL_LOW + GPIO1_LEVEL_LOW [4:4] read-only - GPIO_QSPI_SCLK_EDGE_HIGH + GPIO0_EDGE_HIGH [3:3] read-only - GPIO_QSPI_SCLK_EDGE_LOW + GPIO0_EDGE_LOW [2:2] read-only - GPIO_QSPI_SCLK_LEVEL_HIGH + GPIO0_LEVEL_HIGH [1:1] read-only - GPIO_QSPI_SCLK_LEVEL_LOW + GPIO0_LEVEL_LOW [0:0] read-only @@ -7575,7665 +7137,4239 @@ - PADS_BANK0 - 1 - 0x4001C000 - 0x20 + SYSINFO + 0x40000000 0x0 - 0x1000 + 0x14 registers - VOLTAGE_SELECT - Voltage select. Per bank control + CHIP_ID + JEDEC JEP-106 compliant chip identifier. 0x0 0x00000000 - VOLTAGE_SELECT - [0:0] - read-write - - - 3v3 - Set voltage to 3.3V (DVDD >= 2V5) - 0 - - - 1v8 - Set voltage to 1.8V (DVDD <= 1V8) - 1 - - + REVISION + [31:28] + read-only + + + PART + [27:12] + read-only + + + MANUFACTURER + [11:0] + read-only - 30 - 0x4 - 0-29 - GPIO%s - Pad control register + PLATFORM + Platform register. Allows software to know what environment it is running in. 0x4 - 0x00000056 + 0x00000000 - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write + ASIC + [1:1] + read-only - IE - Input enable - [6:6] - read-write + FPGA + [0:0] + read-only - - DRIVE - Drive strength. - [5:4] - read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - + + + + GITREF_RP2040 + Git hash of the chip source. Used to identify chip version. + 0x10 + 0x00000000 + + + GITREF_RP2040 + [31:0] + read-only + + + + + + PPB + 0xE0000000 + + 0x0 + 0xEDA4 + registers + + + + SYST_CSR + Use the SysTick Control and Status Register to enable the SysTick features. + 0xE010 + 0x00000000 + - PUE - Pull up enable - [3:3] - read-write + COUNTFLAG + Returns 1 if timer counted to 0 since last time this was read. Clears on read by application or debugger. + [16:16] + read-only - PDE - Pull down enable + CLKSOURCE + SysTick clock source. Always reads as one if SYST_CALIB reports NOREF. + Selects the SysTick timer clock source: + 0 = External reference clock. + 1 = Processor clock. [2:2] read-write - SCHMITT - Enable schmitt trigger + TICKINT + Enables SysTick exception request: + 0 = Counting down to zero does not assert the SysTick exception request. + 1 = Counting down to zero to asserts the SysTick exception request. [1:1] read-write - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow + ENABLE + Enable SysTick counter: + 0 = Counter disabled. + 1 = Counter enabled. [0:0] read-write - SWCLK - Pad control register - 0x7C - 0x000000DA + SYST_RVR + Use the SysTick Reload Value Register to specify the start value to load into the current value register when the counter reaches 0. It can be any value between 0 and 0x00FFFFFF. A start value of 0 is possible, but has no effect because the SysTick interrupt and COUNTFLAG are activated when counting from 1 to 0. The reset value of this register is UNKNOWN. + To generate a multi-shot timer with a period of N processor clock cycles, use a RELOAD value of N-1. For example, if the SysTick interrupt is required every 100 clock pulses, set RELOAD to 99. + 0xE014 + 0x00000000 - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] + RELOAD + Value to load into the SysTick Current Value Register when the counter reaches 0. + [23:0] read-write + + + + SYST_CVR + Use the SysTick Current Value Register to find the current value in the register. The reset value of this register is UNKNOWN. + 0xE018 + 0x00000000 + - DRIVE - Drive strength. - [5:4] + CURRENT + Reads return the current value of the SysTick counter. This register is write-clear. Writing to it with any value clears the register to 0. Clearing this register also clears the COUNTFLAG bit of the SysTick Control and Status Register. + [23:0] read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - + + + + SYST_CALIB + Use the SysTick Calibration Value Register to enable software to scale to any required speed using divide and multiply. + 0xE01C + 0x00000000 + - PUE - Pull up enable - [3:3] - read-write + NOREF + If reads as 1, the Reference clock is not provided - the CLKSOURCE bit of the SysTick Control and Status register will be forced to 1 and cannot be cleared to 0. + [31:31] + read-only - PDE - Pull down enable - [2:2] - read-write + SKEW + If reads as 1, the calibration value for 10ms is inexact (due to clock frequency). + [30:30] + read-only - SCHMITT - Enable schmitt trigger - [1:1] - read-write + TENMS + An optional Reload value to be used for 10ms (100Hz) timing, subject to system clock skew errors. If the value reads as 0, the calibration value is not known. + [23:0] + read-only + + + + NVIC_ISER + Use the Interrupt Set-Enable Register to enable interrupts and determine which interrupts are currently enabled. + If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC never activates the interrupt, regardless of its priority. + 0xE100 + 0x00000000 + - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] + SETENA + Interrupt set-enable bits. + Write: + 0 = No effect. + 1 = Enable interrupt. + Read: + 0 = Interrupt disabled. + 1 = Interrupt enabled. + [31:0] read-write - SWD - Pad control register - 0x80 - 0x0000005A + NVIC_ICER + Use the Interrupt Clear-Enable Registers to disable interrupts and determine which interrupts are currently enabled. + 0xE180 + 0x00000000 - OD - Output disable. Has priority over output enable from peripherals - [7:7] + CLRENA + Interrupt clear-enable bits. + Write: + 0 = No effect. + 1 = Disable interrupt. + Read: + 0 = Interrupt disabled. + 1 = Interrupt enabled. + [31:0] read-write + + + + NVIC_ISPR + The NVIC_ISPR forces interrupts into the pending state, and shows which interrupts are pending. + 0xE200 + 0x00000000 + - IE - Input enable - [6:6] + SETPEND + Interrupt set-pending bits. + Write: + 0 = No effect. + 1 = Changes interrupt state to pending. + Read: + 0 = Interrupt is not pending. + 1 = Interrupt is pending. + Note: Writing 1 to the NVIC_ISPR bit corresponding to: + An interrupt that is pending has no effect. + A disabled interrupt sets the state of that interrupt to pending. + [31:0] read-write + + + + NVIC_ICPR + Use the Interrupt Clear-Pending Register to clear pending interrupts and determine which interrupts are currently pending. + 0xE280 + 0x00000000 + - DRIVE - Drive strength. - [5:4] + CLRPEND + Interrupt clear-pending bits. + Write: + 0 = No effect. + 1 = Removes pending state and interrupt. + Read: + 0 = Interrupt is not pending. + 1 = Interrupt is pending. + [31:0] read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - + + + + NVIC_IPR0 + Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. + Note: Writing 1 to an NVIC_ICPR bit does not affect the active state of the corresponding interrupt. + These registers are only word-accessible + 0xE400 + 0x00000000 + - PUE - Pull up enable - [3:3] + IP_3 + Priority of interrupt 3 + [31:30] read-write - PDE - Pull down enable - [2:2] + IP_2 + Priority of interrupt 2 + [23:22] read-write - SCHMITT - Enable schmitt trigger - [1:1] + IP_1 + Priority of interrupt 1 + [15:14] read-write - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] + IP_0 + Priority of interrupt 0 + [7:6] read-write - - - - PADS_QSPI - 1 - 0x40020000 - 0x20 - - 0x0 - 0x1000 - registers - - - VOLTAGE_SELECT - Voltage select. Per bank control - 0x0 + NVIC_IPR1 + Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. + 0xE404 0x00000000 - VOLTAGE_SELECT - [0:0] + IP_7 + Priority of interrupt 7 + [31:30] read-write - - - 3v3 - Set voltage to 3.3V (DVDD >= 2V5) - 0 - - - 1v8 - Set voltage to 1.8V (DVDD <= 1V8) - 1 - - - - - - GPIO_QSPI_SCLK - Pad control register - 0x4 - 0x00000056 - - OD - Output disable. Has priority over output enable from peripherals - [7:7] + IP_6 + Priority of interrupt 6 + [23:22] read-write - IE - Input enable - [6:6] + IP_5 + Priority of interrupt 5 + [15:14] read-write - DRIVE - Drive strength. - [5:4] + IP_4 + Priority of interrupt 4 + [7:6] read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - + + + + NVIC_IPR2 + Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. + 0xE408 + 0x00000000 + - PUE - Pull up enable - [3:3] + IP_11 + Priority of interrupt 11 + [31:30] read-write - PDE - Pull down enable - [2:2] + IP_10 + Priority of interrupt 10 + [23:22] read-write - SCHMITT - Enable schmitt trigger - [1:1] + IP_9 + Priority of interrupt 9 + [15:14] read-write - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] + IP_8 + Priority of interrupt 8 + [7:6] read-write - GPIO_QSPI_SD0 - Pad control register - 0x8 - 0x00000052 + NVIC_IPR3 + Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. + 0xE40C + 0x00000000 - OD - Output disable. Has priority over output enable from peripherals - [7:7] + IP_15 + Priority of interrupt 15 + [31:30] read-write - IE - Input enable - [6:6] + IP_14 + Priority of interrupt 14 + [23:22] read-write - DRIVE - Drive strength. - [5:4] + IP_13 + Priority of interrupt 13 + [15:14] read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - PUE - Pull up enable - [3:3] + IP_12 + Priority of interrupt 12 + [7:6] read-write + + + + NVIC_IPR4 + Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. + 0xE410 + 0x00000000 + - PDE - Pull down enable - [2:2] + IP_19 + Priority of interrupt 19 + [31:30] read-write - SCHMITT - Enable schmitt trigger - [1:1] + IP_18 + Priority of interrupt 18 + [23:22] read-write - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] + IP_17 + Priority of interrupt 17 + [15:14] + read-write + + + IP_16 + Priority of interrupt 16 + [7:6] read-write - GPIO_QSPI_SD1 - Pad control register - 0xC - 0x00000052 + NVIC_IPR5 + Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. + 0xE414 + 0x00000000 - OD - Output disable. Has priority over output enable from peripherals - [7:7] + IP_23 + Priority of interrupt 23 + [31:30] read-write - IE - Input enable - [6:6] + IP_22 + Priority of interrupt 22 + [23:22] read-write - DRIVE - Drive strength. - [5:4] + IP_21 + Priority of interrupt 21 + [15:14] read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - PUE - Pull up enable - [3:3] + IP_20 + Priority of interrupt 20 + [7:6] read-write + + + + NVIC_IPR6 + Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. + 0xE418 + 0x00000000 + - PDE - Pull down enable - [2:2] + IP_27 + Priority of interrupt 27 + [31:30] read-write - SCHMITT - Enable schmitt trigger - [1:1] + IP_26 + Priority of interrupt 26 + [23:22] read-write - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - + IP_25 + Priority of interrupt 25 + [15:14] + read-write + + + IP_24 + Priority of interrupt 24 + [7:6] + read-write + - GPIO_QSPI_SD2 - Pad control register - 0x10 - 0x00000052 + NVIC_IPR7 + Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. + 0xE41C + 0x00000000 - OD - Output disable. Has priority over output enable from peripherals - [7:7] + IP_31 + Priority of interrupt 31 + [31:30] read-write - IE - Input enable - [6:6] + IP_30 + Priority of interrupt 30 + [23:22] read-write - DRIVE - Drive strength. - [5:4] + IP_29 + Priority of interrupt 29 + [15:14] read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - PUE - Pull up enable - [3:3] + IP_28 + Priority of interrupt 28 + [7:6] read-write + + + + CPUID + Read the CPU ID Base Register to determine: the ID number of the processor core, the version number of the processor core, the implementation details of the processor core. + 0xED00 + 0x410CC601 + + + IMPLEMENTER + Implementor code: 0x41 = ARM + [31:24] + read-only + - PDE - Pull down enable - [2:2] - read-write + VARIANT + Major revision number n in the rnpm revision status: + 0x0 = Revision 0. + [23:20] + read-only - SCHMITT - Enable schmitt trigger - [1:1] - read-write + ARCHITECTURE + Constant that defines the architecture of the processor: + 0xC = ARMv6-M architecture. + [19:16] + read-only - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write + PARTNO + Number of processor within family: 0xC60 = Cortex-M0+ + [15:4] + read-only + + + REVISION + Minor revision number m in the rnpm revision status: + 0x1 = Patch 1. + [3:0] + read-only - GPIO_QSPI_SD3 - Pad control register - 0x14 - 0x00000052 + ICSR + Use the Interrupt Control State Register to set a pending Non-Maskable Interrupt (NMI), set or clear a pending PendSV, set or clear a pending SysTick, check for pending exceptions, check the vector number of the highest priority pended exception, check the vector number of the active exception. + 0xED04 + 0x00000000 - OD - Output disable. Has priority over output enable from peripherals - [7:7] + NMIPENDSET + Setting this bit will activate an NMI. Since NMI is the highest priority exception, it will activate as soon as it is registered. + NMI set-pending bit. + Write: + 0 = No effect. + 1 = Changes NMI exception state to pending. + Read: + 0 = NMI exception is not pending. + 1 = NMI exception is pending. + Because NMI is the highest-priority exception, normally the processor enters the NMI + exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears + this bit to 0. This means a read of this bit by the NMI exception handler returns 1 only if the + NMI signal is reasserted while the processor is executing that handler. + [31:31] read-write - IE - Input enable - [6:6] + PENDSVSET + PendSV set-pending bit. + Write: + 0 = No effect. + 1 = Changes PendSV exception state to pending. + Read: + 0 = PendSV exception is not pending. + 1 = PendSV exception is pending. + Writing 1 to this bit is the only way to set the PendSV exception state to pending. + [28:28] read-write - DRIVE - Drive strength. - [5:4] + PENDSVCLR + PendSV clear-pending bit. + Write: + 0 = No effect. + 1 = Removes the pending state from the PendSV exception. + [27:27] read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - PUE - Pull up enable - [3:3] + PENDSTSET + SysTick exception set-pending bit. + Write: + 0 = No effect. + 1 = Changes SysTick exception state to pending. + Read: + 0 = SysTick exception is not pending. + 1 = SysTick exception is pending. + [26:26] read-write - PDE - Pull down enable - [2:2] + PENDSTCLR + SysTick exception clear-pending bit. + Write: + 0 = No effect. + 1 = Removes the pending state from the SysTick exception. + This bit is WO. On a register read its value is Unknown. + [25:25] read-write - SCHMITT - Enable schmitt trigger - [1:1] - read-write + ISRPREEMPT + The system can only access this bit when the core is halted. It indicates that a pending interrupt is to be taken in the next running cycle. If C_MASKINTS is clear in the Debug Halting Control and Status Register, the interrupt is serviced. + [23:23] + read-only - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write + ISRPENDING + External interrupt pending flag + [22:22] + read-only + + + VECTPENDING + Indicates the exception number for the highest priority pending exception: 0 = no pending exceptions. Non zero = The pending state includes the effect of memory-mapped enable and mask registers. It does not include the PRIMASK special-purpose register qualifier. + [20:12] + read-only + + + VECTACTIVE + Active exception number field. Reset clears the VECTACTIVE field. + [8:0] + read-only - GPIO_QSPI_SS - Pad control register - 0x18 - 0x0000005A + VTOR + The VTOR holds the vector table offset address. + 0xED08 + 0x00000000 - OD - Output disable. Has priority over output enable from peripherals - [7:7] - read-write - - - IE - Input enable - [6:6] + TBLOFF + Bits [31:8] of the indicate the vector table offset address. + [31:8] read-write + + + + AIRCR + Use the Application Interrupt and Reset Control Register to: determine data endianness, clear all active state information from debug halt mode, request a system reset. + 0xED0C + 0x00000000 + - DRIVE - Drive strength. - [5:4] + VECTKEY + Register key: + Reads as Unknown + On writes, write 0x05FA to VECTKEY, otherwise the write is ignored. + [31:16] read-write - - - 2mA - 0 - - - 4mA - 1 - - - 8mA - 2 - - - 12mA - 3 - - - PUE - Pull up enable - [3:3] - read-write + ENDIANESS + Data endianness implemented: + 0 = Little-endian. + [15:15] + read-only - PDE - Pull down enable + SYSRESETREQ + Writing 1 to this bit causes the SYSRESETREQ signal to the outer system to be asserted to request a reset. The intention is to force a large system reset of all major components except for debug. The C_HALT bit in the DHCSR is cleared as a result of the system reset requested. The debugger does not lose contact with the device. [2:2] read-write - SCHMITT - Enable schmitt trigger + VECTCLRACTIVE + Clears all active state information for fixed and configurable exceptions. This bit: is self-clearing, can only be set by the DAP when the core is halted. When set: clears all active exception status of the processor, forces a return to Thread mode, forces an IPSR of 0. A debugger must re-initialize the stack. [1:1] read-write - - SLEWFAST - Slew rate control. 1 = Fast, 0 = Slow - [0:0] - read-write - - - - - XOSC - 1 - Controls the crystal oscillator - 0x40024000 - 0x20 - - 0x0 - 0x1000 - registers - - - CTRL - Crystal Oscillator Control - 0x0 + SCR + System Control Register. Use the System Control Register for power-management functions: signal to the system when the processor can enter a low power state, control how the processor enters and exits low power states. + 0xED10 0x00000000 - ENABLE - On power-up this field is initialised to DISABLE and the chip runs from the ROSC.\n - If the chip has subsequently been programmed to run from the XOSC then setting this field to DISABLE may lock-up the chip. If this is a concern then run the clk_ref from the ROSC and enable the clk_sys RESUS feature.\n - The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator. - [23:12] + SEVONPEND + Send Event on Pending bit: + 0 = Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded. + 1 = Enabled events and all interrupts, including disabled interrupts, can wakeup the processor. + When an event or interrupt becomes pending, the event signal wakes up the processor from WFE. If the + processor is not waiting for an event, the event is registered and affects the next WFE. + The processor also wakes up on execution of an SEV instruction or an external event. + [4:4] read-write - - - DISABLE - 3358 - - - ENABLE - 4011 - - - FREQ_RANGE - Frequency range. This resets to 0xAA0 and cannot be changed. - [11:0] + SLEEPDEEP + Controls whether the processor uses sleep or deep sleep as its low power mode: + 0 = Sleep. + 1 = Deep sleep. + [2:2] + read-write + + + SLEEPONEXIT + Indicates sleep-on-exit when returning from Handler mode to Thread mode: + 0 = Do not sleep when returning to Thread mode. + 1 = Enter sleep, or deep sleep, on return from an ISR to Thread mode. + Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application. + [1:1] read-write - - - 1_15MHZ - 2720 - - - RESERVED_1 - 2721 - - - RESERVED_2 - 2722 - - - RESERVED_3 - 2723 - - - STATUS - Crystal Oscillator Status - 0x4 + CCR + The Configuration and Control Register permanently enables stack alignment and causes unaligned accesses to result in a Hard Fault. + 0xED14 0x00000000 - STABLE - Oscillator is running and stable - [31:31] - read-only - - - BADWRITE - An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or DORMANT - [24:24] - read-write - oneToClear - - - ENABLED - Oscillator is enabled but not necessarily running and stable, resets to 0 - [12:12] + STKALIGN + Always reads as one, indicates 8-byte stack alignment on exception entry. On exception entry, the processor uses bit[9] of the stacked PSR to indicate the stack alignment. On return from the exception it uses this stacked bit to restore the correct stack alignment. + [9:9] read-only - FREQ_RANGE - The current frequency range setting, always reads 0 - [1:0] + UNALIGN_TRP + Always reads as one, indicates that all unaligned accesses generate a HardFault. + [3:3] read-only - - - 1_15MHZ - 0 - - - RESERVED_1 - 1 - - - RESERVED_2 - 2 - - - RESERVED_3 - 3 - - - DORMANT - Crystal Oscillator pause control\n - This is used to save power by pausing the XOSC\n - On power-up this field is initialised to WAKE\n - An invalid write will also select WAKE\n - WARNING: stop the PLLs before selecting dormant mode\n - WARNING: setup the irq before selecting dormant mode - 0x8 - read-write + SHPR2 + System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Use the System Handler Priority Register 2 to set the priority of SVCall. + 0xED1C 0x00000000 + + + PRI_11 + Priority of system handler 11, SVCall + [31:30] + read-write + + - STARTUP - Controls the startup delay - 0xC - 0x000000C4 + SHPR3 + System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Use the System Handler Priority Register 3 to set the priority of PendSV and SysTick. + 0xED20 + 0x00000000 - X4 - Multiplies the startup_delay by 4. This is of little value to the user given that the delay can be programmed directly. - [20:20] + PRI_15 + Priority of system handler 15, SysTick + [31:30] read-write - DELAY - in multiples of 256*xtal_period. The reset value of 0xc4 corresponds to approx 50 000 cycles. - [13:0] + PRI_14 + Priority of system handler 14, PendSV + [23:22] read-write - - - - PLL_SYS - 1 - 0x40028000 - 0x20 - - 0x0 - 0x1000 - registers - - - CS - Control and Status\n - GENERAL CONSTRAINTS:\n - Reference clock frequency min=5MHz, max=800MHz\n - Feedback divider min=16, max=320\n - VCO frequency min=750MHz, max=1600MHz - 0x0 - 0x00000001 + SHCSR + Use the System Handler Control and State Register to determine or clear the pending status of SVCall. + 0xED24 + 0x00000000 - LOCK - PLL is locked - [31:31] + SVCALLPENDED + Reads as 1 if SVCall is Pending. Write 1 to set pending SVCall, write 0 to clear pending SVCall. + [15:15] + read-write + + + + + MPU_TYPE + Read the MPU Type Register to determine if the processor implements an MPU, and how many regions the MPU supports. + 0xED90 + 0x00000800 + + + IREGION + Instruction region. Reads as zero as ARMv6-M only supports a unified MPU. + [23:16] read-only - BYPASS - Passes the reference clock to the output instead of the divided VCO. The VCO continues to run so the user can switch between the reference clock and the divided VCO but the output will glitch when doing so. - [8:8] - read-write + DREGION + Number of regions supported by the MPU. + [15:8] + read-only - REFDIV - Divides the PLL input reference clock.\n - Behaviour is undefined for div=0.\n - PLL output will be unpredictable during refdiv changes, wait for lock=1 before using it. - [5:0] - read-write + SEPARATE + Indicates support for separate instruction and data address maps. Reads as 0 as ARMv6-M only supports a unified MPU. + [0:0] + read-only - PWR - Controls the PLL power modes. - 0x4 - 0x0000002D + MPU_CTRL + Use the MPU Control Register to enable and disable the MPU, and to control whether the default memory map is enabled as a background region for privileged accesses, and whether the MPU is enabled for HardFaults and NMIs. + 0xED94 + 0x00000000 - VCOPD - PLL VCO powerdown\n - To save power set high when PLL output not required or bypass=1. - [5:5] - read-write - - - POSTDIVPD - PLL post divider powerdown\n - To save power set high when PLL output not required or bypass=1. - [3:3] + PRIVDEFENA + Controls whether the default memory map is enabled as a background region for privileged accesses. This bit is ignored when ENABLE is clear. + 0 = If the MPU is enabled, disables use of the default memory map. Any memory access to a location not + covered by any enabled region causes a fault. + 1 = If the MPU is enabled, enables use of the default memory map as a background region for privileged software accesses. + When enabled, the background region acts as if it is region number -1. Any region that is defined and enabled has priority over this default map. + [2:2] read-write - DSMPD - PLL DSM powerdown\n - Nothing is achieved by setting this low. - [2:2] + HFNMIENA + Controls the use of the MPU for HardFaults and NMIs. Setting this bit when ENABLE is clear results in UNPREDICTABLE behaviour. + When the MPU is enabled: + 0 = MPU is disabled during HardFault and NMI handlers, regardless of the value of the ENABLE bit. + 1 = the MPU is enabled during HardFault and NMI handlers. + [1:1] read-write - PD - PLL powerdown\n - To save power set high when PLL output not required. + ENABLE + Enables the MPU. If the MPU is disabled, privileged and unprivileged accesses use the default memory map. + 0 = MPU disabled. + 1 = MPU enabled. [0:0] read-write - FBDIV_INT - Feedback divisor\n - (note: this PLL does not support fractional division) - 0x8 + MPU_RNR + Use the MPU Region Number Register to select the region currently accessed by MPU_RBAR and MPU_RASR. + 0xED98 0x00000000 - FBDIV_INT - see ctrl reg description for constraints - [11:0] + REGION + Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers. + The MPU supports 8 memory regions, so the permitted values of this field are 0-7. + [3:0] read-write - PRIM - Controls the PLL post dividers for the primary output\n - (note: this PLL does not have a secondary output)\n - the primary output is driven from VCO divided by postdiv1*postdiv2 - 0xC - 0x00077000 + MPU_RBAR + Read the MPU Region Base Address Register to determine the base address of the region identified by MPU_RNR. Write to update the base address of said region or that of a specified region, with whose number MPU_RNR will also be updated. + 0xED9C + 0x00000000 - POSTDIV1 - divide by 1-7 - [18:16] + ADDR + Base address of the region. + [31:8] read-write - POSTDIV2 - divide by 1-7 - [14:12] + VALID + On writes, indicates whether the write must update the base address of the region identified by the REGION field, updating the MPU_RNR to indicate this new region. + Write: + 0 = MPU_RNR not changed, and the processor: + Updates the base address for the region specified in the MPU_RNR. + Ignores the value of the REGION field. + 1 = The processor: + Updates the value of the MPU_RNR to the value of the REGION field. + Updates the base address for the region specified in the REGION field. + Always reads as zero. + [4:4] + read-write + + + REGION + On writes, specifies the number of the region whose base address to update provided VALID is set written as 1. On reads, returns bits [3:0] of MPU_RNR. + [3:0] read-write - - - - PLL_USB - 0x4002C000 - - - BUSCTRL - 1 - Register block for busfabric control signals and performance counters - 0x40030000 - 0x20 - - 0x0 - 0x1000 - registers - - - BUS_PRIORITY - Set the priority of each master for bus arbitration. - 0x0 + MPU_RASR + Use the MPU Region Attribute and Size Register to define the size, access behaviour and memory type of the region identified by MPU_RNR, and enable that region. + 0xEDA0 0x00000000 - DMA_W - 0 - low priority, 1 - high priority - [12:12] + ATTRS + The MPU Region Attribute field. Use to define the region attribute control. + 28 = XN: Instruction access disable bit: + 0 = Instruction fetches enabled. + 1 = Instruction fetches disabled. + 26:24 = AP: Access permission field + 18 = S: Shareable bit + 17 = C: Cacheable bit + 16 = B: Bufferable bit + [31:16] read-write - DMA_R - 0 - low priority, 1 - high priority - [8:8] + SRD + Subregion Disable. For regions of 256 bytes or larger, each bit of this field controls whether one of the eight equal subregions is enabled. + [15:8] read-write - PROC1 - 0 - low priority, 1 - high priority - [4:4] + SIZE + Indicates the region size. Region size in bytes = 2^(SIZE+1). The minimum permitted value is 7 (b00111) = 256Bytes + [5:1] read-write - PROC0 - 0 - low priority, 1 - high priority + ENABLE + Enables the region. [0:0] read-write + + + + SSI + DW_apb_ssi has the following features: + * APB interface – Allows for easy integration into a DesignWare Synthesizable Components for AMBA 2 implementation. + * APB3 and APB4 protocol support. + * Scalable APB data bus width – Supports APB data bus widths of 8, 16, and 32 bits. + * Serial-master or serial-slave operation – Enables serial communication with serial-master or serial-slave peripheral devices. + * Programmable Dual/Quad/Octal SPI support in Master Mode. + * Dual Data Rate (DDR) and Read Data Strobe (RDS) Support - Enables the DW_apb_ssi master to perform operations with the device in DDR and RDS modes when working in Dual/Quad/Octal mode of operation. + * Data Mask Support - Enables the DW_apb_ssi to selectively update the bytes in the device. This feature is applicable only in enhanced SPI modes. + * eXecute-In-Place (XIP) support - Enables the DW_apb_ssi master to behave as a memory mapped I/O and fetches the data from the device based on the APB read request. This feature is applicable only in enhanced SPI modes. + * DMA Controller Interface – Enables the DW_apb_ssi to interface to a DMA controller over the bus using a handshaking interface for transfer requests. + * Independent masking of interrupts – Master collision, transmit FIFO overflow, transmit FIFO empty, receive FIFO full, receive FIFO underflow, and receive FIFO overflow interrupts can all be masked independently. + * Multi-master contention detection – Informs the processor of multiple serial-master accesses on the serial bus. + * Bypass of meta-stability flip-flops for synchronous clocks – When the APB clock (pclk) and the DW_apb_ssi serial clock (ssi_clk) are synchronous, meta-stable flip-flops are not used when transferring control signals across these clock domains. + * Programmable delay on the sample time of the received serial data bit (rxd); enables programmable control of routing delays resulting in higher serial data-bit rates. + * Programmable features: + - Serial interface operation – Choice of Motorola SPI, Texas Instruments Synchronous Serial Protocol or National Semiconductor Microwire. + - Clock bit-rate – Dynamic control of the serial bit rate of the data transfer; used in only serial-master mode of operation. + - Data Item size (4 to 32 bits) – Item size of each data transfer under the control of the programmer. + * Configured features: + - FIFO depth – 16 words deep. The FIFO width is fixed at 32 bits. + - 1 slave select output. + - Hardware slave-select – Dedicated hardware slave-select line. + - Combined interrupt line - one combined interrupt line from the DW_apb_ssi to the interrupt controller. + - Interrupt polarity – active high interrupt lines. + - Serial clock polarity – low serial-clock polarity directly after reset. + - Serial clock phase – capture on first edge of serial-clock directly after reset. + 0x18000000 + + 0x0 + 0xFC + registers + + - BUS_PRIORITY_ACK - Bus priority acknowledge - 0x4 - 0x00000000 - - - BUS_PRIORITY_ACK - Goes to 1 once all arbiters have registered the new global priority levels.\n - Arbiters update their local priority when servicing a new nonsequential access.\n - In normal circumstances this will happen almost immediately. - [0:0] - read-only - - - - - PERFCTR0 - Bus fabric performance counter 0 - 0x8 + CTRLR0 + Control register 0 + 0x0 0x00000000 - PERFCTR0 - Busfabric saturating performance counter 0\n - Count some event signal from the busfabric arbiters.\n - Write any value to clear. Select an event to count using PERFSEL0 - [23:0] + SSTE + Slave select toggle enable + [24:24] read-write - oneToClear - - - - PERFSEL0 - Bus fabric performance event select for PERFCTR0 - 0xC - 0x0000001F - - PERFSEL0 - Select an event for PERFCTR0. Count either contested accesses, or all accesses, on a downstream port of the main crossbar. - [4:0] + SPI_FRF + SPI frame format + [22:21] read-write - apb_contested + STD + Standard 1-bit SPI frame format; 1 bit per SCK, full-duplex 0 - apb + DUAL + Dual-SPI frame format; two bits per SCK, half-duplex 1 - fastperi_contested + QUAD + Quad-SPI frame format; four bits per SCK, half-duplex 2 + + + + DFS_32 + Data frame size in 32b transfer mode + Value of n -> n+1 clocks per frame. + [20:16] + read-write + + + CFS + Control frame size + Value of n -> n+1 clocks per frame. + [15:12] + read-write + + + SRL + Shift register loop (test mode) + [11:11] + read-write + + + SLV_OE + Slave output enable + [10:10] + read-write + + + TMOD + Transfer mode + [9:8] + read-write + - fastperi - 3 - - - sram5_contested - 4 - - - sram5 - 5 - - - sram4_contested - 6 - - - sram4 - 7 - - - sram3_contested - 8 - - - sram3 - 9 - - - sram2_contested - 10 - - - sram2 - 11 - - - sram1_contested - 12 - - - sram1 - 13 - - - sram0_contested - 14 - - - sram0 - 15 - - - xip_main_contested - 16 + TX_AND_RX + Both transmit and receive + 0 - xip_main - 17 + TX_ONLY + Transmit only (not for FRF == 0, standard SPI mode) + 1 - rom_contested - 18 + RX_ONLY + Receive only (not for FRF == 0, standard SPI mode) + 2 - rom - 19 + EEPROM_READ + EEPROM read mode (TX then RX; RX starts after control data TX'd) + 3 + + SCPOL + Serial clock polarity + [7:7] + read-write + + + SCPH + Serial clock phase + [6:6] + read-write + + + FRF + Frame format + [5:4] + read-write + + + DFS + Data frame size + [3:0] + read-write + - PERFCTR1 - Bus fabric performance counter 1 - 0x10 + CTRLR1 + Master Control register 1 + 0x4 0x00000000 - PERFCTR1 - Busfabric saturating performance counter 1\n - Count some event signal from the busfabric arbiters.\n - Write any value to clear. Select an event to count using PERFSEL1 - [23:0] + NDF + Number of data frames + [15:0] read-write - oneToClear - PERFSEL1 - Bus fabric performance event select for PERFCTR1 - 0x14 - 0x0000001F + SSIENR + SSI Enable + 0x8 + 0x00000000 - PERFSEL1 - Select an event for PERFCTR1. Count either contested accesses, or all accesses, on a downstream port of the main crossbar. - [4:0] + SSI_EN + SSI enable + [0:0] read-write - - - apb_contested - 0 - - - apb - 1 - - - fastperi_contested - 2 - - - fastperi - 3 - - - sram5_contested - 4 - - - sram5 - 5 - - - sram4_contested - 6 - - - sram4 - 7 - - - sram3_contested - 8 - - - sram3 - 9 - - - sram2_contested - 10 - - - sram2 - 11 - - - sram1_contested - 12 - - - sram1 - 13 - - - sram0_contested - 14 - - - sram0 - 15 - - - xip_main_contested - 16 - - - xip_main - 17 - - - rom_contested - 18 - - - rom - 19 - - - PERFCTR2 - Bus fabric performance counter 2 + MWCR + Microwire Control + 0xC + 0x00000000 + + + MHS + Microwire handshaking + [2:2] + read-write + + + MDD + Microwire control + [1:1] + read-write + + + MWMOD + Microwire transfer mode + [0:0] + read-write + + + + + SER + Slave enable + 0x10 + 0x00000000 + + + SER + For each bit: + 0 -> slave not selected + 1 -> slave selected + [0:0] + read-write + + + + + BAUDR + Baud rate + 0x14 + 0x00000000 + + + SCKDV + SSI clock divider + [15:0] + read-write + + + + + TXFTLR + TX FIFO threshold level 0x18 0x00000000 - PERFCTR2 - Busfabric saturating performance counter 2\n - Count some event signal from the busfabric arbiters.\n - Write any value to clear. Select an event to count using PERFSEL2 - [23:0] + TFT + Transmit FIFO threshold + [7:0] read-write - oneToClear - PERFSEL2 - Bus fabric performance event select for PERFCTR2 + RXFTLR + RX FIFO threshold level 0x1C - 0x0000001F + 0x00000000 - PERFSEL2 - Select an event for PERFCTR2. Count either contested accesses, or all accesses, on a downstream port of the main crossbar. - [4:0] + RFT + Receive FIFO threshold + [7:0] read-write - - - apb_contested - 0 - - - apb - 1 - - - fastperi_contested - 2 - - - fastperi - 3 - - - sram5_contested - 4 - - - sram5 - 5 - - - sram4_contested - 6 - - - sram4 - 7 - - - sram3_contested - 8 - - - sram3 - 9 - - - sram2_contested - 10 - - - sram2 - 11 - - - sram1_contested - 12 - - - sram1 - 13 - - - sram0_contested - 14 - - - sram0 - 15 - - - xip_main_contested - 16 - - - xip_main - 17 - - - rom_contested - 18 - - - rom - 19 - - - PERFCTR3 - Bus fabric performance counter 3 + TXFLR + TX FIFO level 0x20 0x00000000 - PERFCTR3 - Busfabric saturating performance counter 3\n - Count some event signal from the busfabric arbiters.\n - Write any value to clear. Select an event to count using PERFSEL3 - [23:0] - read-write - oneToClear + TFTFL + Transmit FIFO level + [7:0] + read-only - PERFSEL3 - Bus fabric performance event select for PERFCTR3 + RXFLR + RX FIFO level 0x24 - 0x0000001F + 0x00000000 - PERFSEL3 - Select an event for PERFCTR3. Count either contested accesses, or all accesses, on a downstream port of the main crossbar. - [4:0] - read-write - - - apb_contested - 0 - - - apb - 1 - - - fastperi_contested - 2 - - - fastperi - 3 - - - sram5_contested - 4 - - - sram5 - 5 - - - sram4_contested - 6 - - - sram4 - 7 - - - sram3_contested - 8 - - - sram3 - 9 - - - sram2_contested - 10 - - - sram2 - 11 - - - sram1_contested - 12 - - - sram1 - 13 - - - sram0_contested - 14 - - - sram0 - 15 - - - xip_main_contested - 16 - - - xip_main - 17 - - - rom_contested - 18 - - - rom - 19 - - + RXTFL + Receive FIFO level + [7:0] + read-only - - - - UART0 - 1 - 0x40034000 - 0x20 - - 0x0 - 0x1000 - registers - - - UART0_IRQ - 20 - - - UARTDR - Data Register, UARTDR - 0x0 + SR + Status register + 0x28 0x00000000 - OE - Overrun error. This bit is set to 1 if data is received and the receive FIFO is already full. This is cleared to 0 once there is an empty space in the FIFO and a new character can be written to it. - [11:11] + DCOL + Data collision error + [6:6] read-only - BE - Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity and stop bits). In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state), and the next valid start bit is received. - [10:10] + TXE + Transmission error + [5:5] read-only - PE - Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. In FIFO mode, this error is associated with the character at the top of the FIFO. - [9:9] + RFF + Receive FIFO full + [4:4] read-only - FE - Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). In FIFO mode, this error is associated with the character at the top of the FIFO. - [8:8] + RFNE + Receive FIFO not empty + [3:3] read-only - DATA - Receive (read) data character. Transmit (write) data character. - [7:0] - read-write + TFE + Transmit FIFO empty + [2:2] + read-only + + + TFNF + Transmit FIFO not full + [1:1] + read-only + + + BUSY + SSI busy flag + [0:0] + read-only - UARTRSR - Receive Status Register/Error Clear Register, UARTRSR/UARTECR - 0x4 + IMR + Interrupt mask + 0x2C 0x00000000 - OE - Overrun error. This bit is set to 1 if data is received and the FIFO is already full. This bit is cleared to 0 by a write to UARTECR. The FIFO contents remain valid because no more data is written when the FIFO is full, only the contents of the shift register are overwritten. The CPU must now read the data, to empty the FIFO. + MSTIM + Multi-master contention interrupt mask + [5:5] + read-write + + + RXFIM + Receive FIFO full interrupt mask + [4:4] + read-write + + + RXOIM + Receive FIFO overflow interrupt mask [3:3] read-write - oneToClear - BE - Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity, and stop bits). This bit is cleared to 0 after a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received. + RXUIM + Receive FIFO underflow interrupt mask [2:2] read-write - oneToClear - PE - Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. + TXOIM + Transmit FIFO overflow interrupt mask [1:1] read-write - oneToClear - FE - Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. + TXEIM + Transmit FIFO empty interrupt mask [0:0] read-write - oneToClear - UARTFR - Flag Register, UARTFR - 0x18 - 0x00000090 + ISR + Interrupt status + 0x30 + 0x00000000 - RI - Ring indicator. This bit is the complement of the UART ring indicator, nUARTRI, modem status input. That is, the bit is 1 when nUARTRI is LOW. - [8:8] - read-only - - - TXFE - Transmit FIFO empty. The meaning of this bit depends on the state of the FEN bit in the Line Control Register, UARTLCR_H. If the FIFO is disabled, this bit is set when the transmit holding register is empty. If the FIFO is enabled, the TXFE bit is set when the transmit FIFO is empty. This bit does not indicate if there is data in the transmit shift register. - [7:7] - read-only - - - RXFF - Receive FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the receive holding register is full. If the FIFO is enabled, the RXFF bit is set when the receive FIFO is full. - [6:6] - read-only - - - TXFF - Transmit FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the transmit holding register is full. If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full. + MSTIS + Multi-master contention interrupt status [5:5] read-only - RXFE - Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the receive holding register is empty. If the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty. + RXFIS + Receive FIFO full interrupt status [4:4] read-only - BUSY - UART busy. If this bit is set to 1, the UART is busy transmitting data. This bit remains set until the complete byte, including all the stop bits, has been sent from the shift register. This bit is set as soon as the transmit FIFO becomes non-empty, regardless of whether the UART is enabled or not. + RXOIS + Receive FIFO overflow interrupt status [3:3] read-only - DCD - Data carrier detect. This bit is the complement of the UART data carrier detect, nUARTDCD, modem status input. That is, the bit is 1 when nUARTDCD is LOW. + RXUIS + Receive FIFO underflow interrupt status [2:2] read-only - DSR - Data set ready. This bit is the complement of the UART data set ready, nUARTDSR, modem status input. That is, the bit is 1 when nUARTDSR is LOW. + TXOIS + Transmit FIFO overflow interrupt status [1:1] read-only - CTS - Clear to send. This bit is the complement of the UART clear to send, nUARTCTS, modem status input. That is, the bit is 1 when nUARTCTS is LOW. + TXEIS + Transmit FIFO empty interrupt status [0:0] read-only - UARTILPR - IrDA Low-Power Counter Register, UARTILPR - 0x20 + RISR + Raw interrupt status + 0x34 0x00000000 - ILPDVSR - 8-bit low-power divisor value. These bits are cleared to 0 at reset. - [7:0] - read-write + MSTIR + Multi-master contention raw interrupt status + [5:5] + read-only - - - - UARTIBRD - Integer Baud Rate Register, UARTIBRD - 0x24 - 0x00000000 - - BAUD_DIVINT - The integer baud rate divisor. These bits are cleared to 0 on reset. - [15:0] - read-write + RXFIR + Receive FIFO full raw interrupt status + [4:4] + read-only + + + RXOIR + Receive FIFO overflow raw interrupt status + [3:3] + read-only + + + RXUIR + Receive FIFO underflow raw interrupt status + [2:2] + read-only + + + TXOIR + Transmit FIFO overflow raw interrupt status + [1:1] + read-only + + + TXEIR + Transmit FIFO empty raw interrupt status + [0:0] + read-only - UARTFBRD - Fractional Baud Rate Register, UARTFBRD - 0x28 + TXOICR + TX FIFO overflow interrupt clear + 0x38 0x00000000 - BAUD_DIVFRAC - The fractional baud rate divisor. These bits are cleared to 0 on reset. - [5:0] - read-write + TXOICR + Clear-on-read transmit FIFO overflow interrupt + [0:0] + read-only - UARTLCR_H - Line Control Register, UARTLCR_H - 0x2C + RXOICR + RX FIFO overflow interrupt clear + 0x3C 0x00000000 - SPS - Stick parity select. 0 = stick parity is disabled 1 = either: * if the EPS bit is 0 then the parity bit is transmitted and checked as a 1 * if the EPS bit is 1 then the parity bit is transmitted and checked as a 0. This bit has no effect when the PEN bit disables parity checking and generation. - [7:7] - read-write - - - WLEN - Word length. These bits indicate the number of data bits transmitted or received in a frame as follows: b11 = 8 bits b10 = 7 bits b01 = 6 bits b00 = 5 bits. - [6:5] - read-write + RXOICR + Clear-on-read receive FIFO overflow interrupt + [0:0] + read-only + + + + RXUICR + RX FIFO underflow interrupt clear + 0x40 + 0x00000000 + - FEN - Enable FIFOs: 0 = FIFOs are disabled (character mode) that is, the FIFOs become 1-byte-deep holding registers 1 = transmit and receive FIFO buffers are enabled (FIFO mode). - [4:4] - read-write + RXUICR + Clear-on-read receive FIFO underflow interrupt + [0:0] + read-only + + + + MSTICR + Multi-master interrupt clear + 0x44 + 0x00000000 + - STP2 - Two stop bits select. If this bit is set to 1, two stop bits are transmitted at the end of the frame. The receive logic does not check for two stop bits being received. - [3:3] - read-write + MSTICR + Clear-on-read multi-master contention interrupt + [0:0] + read-only + + + + ICR + Interrupt clear + 0x48 + 0x00000000 + - EPS - Even parity select. Controls the type of parity the UART uses during transmission and reception: 0 = odd parity. The UART generates or checks for an odd number of 1s in the data and parity bits. 1 = even parity. The UART generates or checks for an even number of 1s in the data and parity bits. This bit has no effect when the PEN bit disables parity checking and generation. - [2:2] - read-write + ICR + Clear-on-read all active interrupts + [0:0] + read-only + + + + DMACR + DMA control + 0x4C + 0x00000000 + - PEN - Parity enable: 0 = parity is disabled and no parity bit added to the data frame 1 = parity checking and generation is enabled. + TDMAE + Transmit DMA enable [1:1] read-write - BRK - Send break. If this bit is set to 1, a low-level is continually output on the UARTTXD output, after completing transmission of the current character. For the proper execution of the break command, the software must set this bit for at least two complete frames. For normal use, this bit must be cleared to 0. + RDMAE + Receive DMA enable [0:0] read-write - UARTCR - Control Register, UARTCR - 0x30 - 0x00000300 + DMATDLR + DMA TX data level + 0x50 + 0x00000000 - CTSEN - CTS hardware flow control enable. If this bit is set to 1, CTS hardware flow control is enabled. Data is only transmitted when the nUARTCTS signal is asserted. - [15:15] + DMATDL + Transmit data watermark level + [7:0] read-write + + + + DMARDLR + DMA RX data level + 0x54 + 0x00000000 + - RTSEN - RTS hardware flow control enable. If this bit is set to 1, RTS hardware flow control is enabled. Data is only requested when there is space in the receive FIFO for it to be received. - [14:14] + DMARDL + Receive data watermark level (DMARDLR+1) + [7:0] read-write + + + + IDR + Identification register + 0x58 + 0x51535049 + - OUT2 - This bit is the complement of the UART Out2 (nUARTOut2) modem status output. That is, when the bit is programmed to a 1, the output is 0. For DTE this can be used as Ring Indicator (RI). - [13:13] - read-write + IDCODE + Peripheral dentification code + [31:0] + read-only + + + + SSI_VERSION_ID + Version ID + 0x5C + 0x3430312A + - OUT1 - This bit is the complement of the UART Out1 (nUARTOut1) modem status output. That is, when the bit is programmed to a 1 the output is 0. For DTE this can be used as Data Carrier Detect (DCD). - [12:12] - read-write + SSI_COMP_VERSION + SNPS component version (format X.YY) + [31:0] + read-only + + + + DR0 + Data Register 0 (of 36) + 0x60 + 0x00000000 + - RTS - Request to send. This bit is the complement of the UART request to send, nUARTRTS, modem status output. That is, when the bit is programmed to a 1 then nUARTRTS is LOW. - [11:11] + DR + First data register of 36 + [31:0] read-write + + + + RX_SAMPLE_DLY + RX sample delay + 0xF0 + 0x00000000 + - DTR - Data transmit ready. This bit is the complement of the UART data transmit ready, nUARTDTR, modem status output. That is, when the bit is programmed to a 1 then nUARTDTR is LOW. - [10:10] + RSD + RXD sample delay (in SCLK cycles) + [7:0] read-write + + + + SPI_CTRLR0 + SPI control + 0xF4 + 0x03000000 + - RXE - Receive enable. If this bit is set to 1, the receive section of the UART is enabled. Data reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of reception, it completes the current character before stopping. - [9:9] + XIP_CMD + SPI Command to send in XIP mode (INST_L = 8-bit) or to append to Address (INST_L = 0-bit) + [31:24] read-write - TXE - Transmit enable. If this bit is set to 1, the transmit section of the UART is enabled. Data transmission occurs for either UART signals, or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of transmission, it completes the current character before stopping. - [8:8] + SPI_RXDS_EN + Read data strobe enable + [18:18] read-write - LBE - Loopback enable. If this bit is set to 1 and the SIREN bit is set to 1 and the SIRTEST bit in the Test Control Register, UARTTCR is set to 1, then the nSIROUT path is inverted, and fed through to the SIRIN path. The SIRTEST bit in the test register must be set to 1 to override the normal half-duplex SIR operation. This must be the requirement for accessing the test registers during normal operation, and SIRTEST must be cleared to 0 when loopback testing is finished. This feature reduces the amount of external coupling required during system test. If this bit is set to 1, and the SIRTEST bit is set to 0, the UARTTXD path is fed through to the UARTRXD path. In either SIR mode or UART mode, when this bit is set, the modem outputs are also fed through to the modem inputs. This bit is cleared to 0 on reset, to disable loopback. - [7:7] + INST_DDR_EN + Instruction DDR transfer enable + [17:17] read-write - SIRLP - SIR low-power IrDA mode. This bit selects the IrDA encoding mode. If this bit is cleared to 0, low-level bits are transmitted as an active high pulse with a width of 3 / 16th of the bit period. If this bit is set to 1, low-level bits are transmitted with a pulse width that is 3 times the period of the IrLPBaud16 input signal, regardless of the selected bit rate. Setting this bit uses less power, but might reduce transmission distances. - [2:2] + SPI_DDR_EN + SPI DDR transfer enable + [16:16] read-write - SIREN - SIR enable: 0 = IrDA SIR ENDEC is disabled. nSIROUT remains LOW (no light pulse generated), and signal transitions on SIRIN have no effect. 1 = IrDA SIR ENDEC is enabled. Data is transmitted and received on nSIROUT and SIRIN. UARTTXD remains HIGH, in the marking state. Signal transitions on UARTRXD or modem status inputs have no effect. This bit has no effect if the UARTEN bit disables the UART. - [1:1] + WAIT_CYCLES + Wait cycles between control frame transmit and data reception (in SCLK cycles) + [15:11] read-write - UARTEN - UART enable: 0 = UART is disabled. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. 1 = the UART is enabled. Data transmission and reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. - [0:0] + INST_L + Instruction length (0/4/8/16b) + [9:8] read-write + + + NONE + No instruction + 0 + + + 4B + 4-bit instruction + 1 + + + 8B + 8-bit instruction + 2 + + + 16B + 16-bit instruction + 3 + + - - - - UARTIFLS - Interrupt FIFO Level Select Register, UARTIFLS - 0x34 - 0x00000012 - - RXIFLSEL - Receive interrupt FIFO level select. The trigger points for the receive interrupt are as follows: b000 = Receive FIFO becomes >= 1 / 8 full b001 = Receive FIFO becomes >= 1 / 4 full b010 = Receive FIFO becomes >= 1 / 2 full b011 = Receive FIFO becomes >= 3 / 4 full b100 = Receive FIFO becomes >= 7 / 8 full b101-b111 = reserved. - [5:3] + ADDR_L + Address length (0b-60b in 4b increments) + [5:2] read-write - TXIFLSEL - Transmit interrupt FIFO level select. The trigger points for the transmit interrupt are as follows: b000 = Transmit FIFO becomes <= 1 / 8 full b001 = Transmit FIFO becomes <= 1 / 4 full b010 = Transmit FIFO becomes <= 1 / 2 full b011 = Transmit FIFO becomes <= 3 / 4 full b100 = Transmit FIFO becomes <= 7 / 8 full b101-b111 = reserved. - [2:0] + TRANS_TYPE + Address and instruction transfer format + [1:0] read-write + + + 1C1A + Command and address both in standard SPI frame format + 0 + + + 1C2A + Command in standard SPI format, address in format specified by FRF + 1 + + + 2C2A + Command and address both in format specified by FRF (e.g. Dual-SPI) + 2 + + - UARTIMSC - Interrupt Mask Set/Clear Register, UARTIMSC - 0x38 + TXD_DRIVE_EDGE + TX drive edge + 0xF8 0x00000000 - OEIM - Overrun error interrupt mask. A read returns the current mask for the UARTOEINTR interrupt. On a write of 1, the mask of the UARTOEINTR interrupt is set. A write of 0 clears the mask. - [10:10] - read-write - - - BEIM - Break error interrupt mask. A read returns the current mask for the UARTBEINTR interrupt. On a write of 1, the mask of the UARTBEINTR interrupt is set. A write of 0 clears the mask. - [9:9] - read-write - - - PEIM - Parity error interrupt mask. A read returns the current mask for the UARTPEINTR interrupt. On a write of 1, the mask of the UARTPEINTR interrupt is set. A write of 0 clears the mask. - [8:8] - read-write - - - FEIM - Framing error interrupt mask. A read returns the current mask for the UARTFEINTR interrupt. On a write of 1, the mask of the UARTFEINTR interrupt is set. A write of 0 clears the mask. - [7:7] - read-write - - - RTIM - Receive timeout interrupt mask. A read returns the current mask for the UARTRTINTR interrupt. On a write of 1, the mask of the UARTRTINTR interrupt is set. A write of 0 clears the mask. - [6:6] - read-write - - - TXIM - Transmit interrupt mask. A read returns the current mask for the UARTTXINTR interrupt. On a write of 1, the mask of the UARTTXINTR interrupt is set. A write of 0 clears the mask. - [5:5] - read-write - - - RXIM - Receive interrupt mask. A read returns the current mask for the UARTRXINTR interrupt. On a write of 1, the mask of the UARTRXINTR interrupt is set. A write of 0 clears the mask. - [4:4] + TDE + TXD drive edge + [7:0] read-write + + + + + + XIP_CTRL + QSPI flash execute-in-place block + 0x14000000 + + 0x0 + 0x20 + registers + + + XIP_IRQ + 6 + + + + CTRL + Cache control + 0x0 + 0x00000003 + - DSRMIM - nUARTDSR modem interrupt mask. A read returns the current mask for the UARTDSRINTR interrupt. On a write of 1, the mask of the UARTDSRINTR interrupt is set. A write of 0 clears the mask. + POWER_DOWN + When 1, the cache memories are powered down. They retain state, + but can not be accessed. This reduces static power dissipation. + Writing 1 to this bit forces CTRL_EN to 0, i.e. the cache cannot + be enabled when powered down. + Cache-as-SRAM accesses will produce a bus error response when + the cache is powered down. [3:3] read-write - DCDMIM - nUARTDCD modem interrupt mask. A read returns the current mask for the UARTDCDINTR interrupt. On a write of 1, the mask of the UARTDCDINTR interrupt is set. A write of 0 clears the mask. - [2:2] - read-write - - - CTSMIM - nUARTCTS modem interrupt mask. A read returns the current mask for the UARTCTSINTR interrupt. On a write of 1, the mask of the UARTCTSINTR interrupt is set. A write of 0 clears the mask. + ERR_BADWRITE + When 1, writes to any alias other than 0x0 (caching, allocating) + will produce a bus fault. When 0, these writes are silently ignored. + In either case, writes to the 0x0 alias will deallocate on tag match, + as usual. [1:1] read-write - RIMIM - nUARTRI modem interrupt mask. A read returns the current mask for the UARTRIINTR interrupt. On a write of 1, the mask of the UARTRIINTR interrupt is set. A write of 0 clears the mask. + EN + When 1, enable the cache. When the cache is disabled, all XIP accesses + will go straight to the flash, without querying the cache. When enabled, + cacheable XIP accesses will query the cache, and the flash will + not be accessed if the tag matches and the valid bit is set. + + If the cache is enabled, cache-as-SRAM accesses have no effect on the + cache data RAM, and will produce a bus error response. [0:0] read-write - UARTRIS - Raw Interrupt Status Register, UARTRIS - 0x3C + FLUSH + Cache Flush control + 0x4 0x00000000 - OERIS - Overrun error interrupt status. Returns the raw interrupt state of the UARTOEINTR interrupt. - [10:10] - read-only - - - BERIS - Break error interrupt status. Returns the raw interrupt state of the UARTBEINTR interrupt. - [9:9] - read-only - - - PERIS - Parity error interrupt status. Returns the raw interrupt state of the UARTPEINTR interrupt. - [8:8] - read-only - - - FERIS - Framing error interrupt status. Returns the raw interrupt state of the UARTFEINTR interrupt. - [7:7] - read-only - - - RTRIS - Receive timeout interrupt status. Returns the raw interrupt state of the UARTRTINTR interrupt. a - [6:6] - read-only - - - TXRIS - Transmit interrupt status. Returns the raw interrupt state of the UARTTXINTR interrupt. - [5:5] - read-only - - - RXRIS - Receive interrupt status. Returns the raw interrupt state of the UARTRXINTR interrupt. - [4:4] - read-only - - - DSRRMIS - nUARTDSR modem interrupt status. Returns the raw interrupt state of the UARTDSRINTR interrupt. - [3:3] - read-only + FLUSH + Write 1 to flush the cache. This clears the tag memory, but + the data memory retains its contents. (This means cache-as-SRAM + contents is not affected by flush or reset.) + Reading will hold the bus (stall the processor) until the flush + completes. Alternatively STAT can be polled until completion. + [0:0] + write-only + + + + STAT + Cache Status + 0x8 + 0x00000002 + - DCDRMIS - nUARTDCD modem interrupt status. Returns the raw interrupt state of the UARTDCDINTR interrupt. + FIFO_FULL + When 1, indicates the XIP streaming FIFO is completely full. + The streaming FIFO is 2 entries deep, so the full and empty + flag allow its level to be ascertained. [2:2] read-only - CTSRMIS - nUARTCTS modem interrupt status. Returns the raw interrupt state of the UARTCTSINTR interrupt. + FIFO_EMPTY + When 1, indicates the XIP streaming FIFO is completely empty. [1:1] read-only - RIRMIS - nUARTRI modem interrupt status. Returns the raw interrupt state of the UARTRIINTR interrupt. + FLUSH_READY + Reads as 0 while a cache flush is in progress, and 1 otherwise. + The cache is flushed whenever the XIP block is reset, and also + when requested via the FLUSH register. [0:0] read-only - UARTMIS - Masked Interrupt Status Register, UARTMIS - 0x40 + CTR_HIT + Cache Hit counter + 0xC 0x00000000 - OEMIS - Overrun error masked interrupt status. Returns the masked interrupt state of the UARTOEINTR interrupt. - [10:10] - read-only + CTR_HIT + A 32 bit saturating counter that increments upon each cache hit, + i.e. when an XIP access is serviced directly from cached data. + Write any value to clear. + [31:0] + read-write + oneToClear + + + + CTR_ACC + Cache Access counter + 0x10 + 0x00000000 + - BEMIS - Break error masked interrupt status. Returns the masked interrupt state of the UARTBEINTR interrupt. - [9:9] - read-only + CTR_ACC + A 32 bit saturating counter that increments upon each XIP access, + whether the cache is hit or not. This includes noncacheable accesses. + Write any value to clear. + [31:0] + read-write + oneToClear + + + + STREAM_ADDR + FIFO stream address + 0x14 + 0x00000000 + - PEMIS - Parity error masked interrupt status. Returns the masked interrupt state of the UARTPEINTR interrupt. - [8:8] - read-only + STREAM_ADDR + The address of the next word to be streamed from flash to the streaming FIFO. + Increments automatically after each flash access. + Write the initial access address here before starting a streaming read. + [31:2] + read-write + + + + STREAM_CTR + FIFO stream control + 0x18 + 0x00000000 + - FEMIS - Framing error masked interrupt status. Returns the masked interrupt state of the UARTFEINTR interrupt. - [7:7] - read-only + STREAM_CTR + Write a nonzero value to start a streaming read. This will then + progress in the background, using flash idle cycles to transfer + a linear data block from flash to the streaming FIFO. + Decrements automatically (1 at a time) as the stream + progresses, and halts on reaching 0. + Write 0 to halt an in-progress stream, and discard any in-flight + read, so that a new stream can immediately be started (after + draining the FIFO and reinitialising STREAM_ADDR) + [21:0] + read-write + + + + STREAM_FIFO + FIFO stream data + 0x1C + 0x00000000 + - RTMIS - Receive timeout masked interrupt status. Returns the masked interrupt state of the UARTRTINTR interrupt. - [6:6] + STREAM_FIFO + Streamed data is buffered here, for retrieval by the system DMA. + This FIFO can also be accessed via the XIP_AUX slave, to avoid exposing + the DMA to bus stalls caused by other XIP traffic. + [31:0] read-only + modify + + + + + + SYSCFG + Register block for various chip control signals + 0x40004000 + + 0x0 + 0x1C + registers + + + + PROC0_NMI_MASK + Processor core 0 NMI source mask + 0x0 + 0x00000000 + - TXMIS - Transmit masked interrupt status. Returns the masked interrupt state of the UARTTXINTR interrupt. - [5:5] - read-only + PROC0_NMI_MASK + Set a bit high to enable NMI from that IRQ + [31:0] + read-write + + + + PROC1_NMI_MASK + Processor core 1 NMI source mask + 0x4 + 0x00000000 + - RXMIS - Receive masked interrupt status. Returns the masked interrupt state of the UARTRXINTR interrupt. - [4:4] - read-only + PROC1_NMI_MASK + Set a bit high to enable NMI from that IRQ + [31:0] + read-write + + + + PROC_CONFIG + Configuration for processors + 0x8 + 0x10000000 + - DSRMMIS - nUARTDSR modem masked interrupt status. Returns the masked interrupt state of the UARTDSRINTR interrupt. - [3:3] - read-only + PROC1_DAP_INSTID + Configure proc1 DAP instance ID. + Recommend that this is NOT changed until you require debug access in multi-chip environment + WARNING: do not set to 15 as this is reserved for RescueDP + [31:28] + read-write - DCDMMIS - nUARTDCD modem masked interrupt status. Returns the masked interrupt state of the UARTDCDINTR interrupt. - [2:2] - read-only + PROC0_DAP_INSTID + Configure proc0 DAP instance ID. + Recommend that this is NOT changed until you require debug access in multi-chip environment + WARNING: do not set to 15 as this is reserved for RescueDP + [27:24] + read-write - CTSMMIS - nUARTCTS modem masked interrupt status. Returns the masked interrupt state of the UARTCTSINTR interrupt. + PROC1_HALTED + Indication that proc1 has halted [1:1] read-only - RIMMIS - nUARTRI modem masked interrupt status. Returns the masked interrupt state of the UARTRIINTR interrupt. + PROC0_HALTED + Indication that proc0 has halted [0:0] read-only - UARTICR - Interrupt Clear Register, UARTICR - 0x44 + PROC_IN_SYNC_BYPASS + For each bit, if 1, bypass the input synchronizer between that GPIO + and the GPIO input register in the SIO. The input synchronizers should + generally be unbypassed, to avoid injecting metastabilities into processors. + If you're feeling brave, you can bypass to save two cycles of input + latency. This register applies to GPIO 0...29. + 0xC 0x00000000 - OEIC - Overrun error interrupt clear. Clears the UARTOEINTR interrupt. - [10:10] - read-write - oneToClear - - - BEIC - Break error interrupt clear. Clears the UARTBEINTR interrupt. - [9:9] + PROC_IN_SYNC_BYPASS + [29:0] read-write - oneToClear + + + + PROC_IN_SYNC_BYPASS_HI + For each bit, if 1, bypass the input synchronizer between that GPIO + and the GPIO input register in the SIO. The input synchronizers should + generally be unbypassed, to avoid injecting metastabilities into processors. + If you're feeling brave, you can bypass to save two cycles of input + latency. This register applies to GPIO 30...35 (the QSPI IOs). + 0x10 + 0x00000000 + - PEIC - Parity error interrupt clear. Clears the UARTPEINTR interrupt. - [8:8] + PROC_IN_SYNC_BYPASS_HI + [5:0] read-write - oneToClear + + + + DBGFORCE + Directly control the SWD debug port of either processor + 0x14 + 0x00000066 + - FEIC - Framing error interrupt clear. Clears the UARTFEINTR interrupt. + PROC1_ATTACH + Attach processor 1 debug port to syscfg controls, and disconnect it from external SWD pads. [7:7] read-write - oneToClear - RTIC - Receive timeout interrupt clear. Clears the UARTRTINTR interrupt. + PROC1_SWCLK + Directly drive processor 1 SWCLK, if PROC1_ATTACH is set [6:6] read-write - oneToClear - TXIC - Transmit interrupt clear. Clears the UARTTXINTR interrupt. + PROC1_SWDI + Directly drive processor 1 SWDIO input, if PROC1_ATTACH is set [5:5] read-write - oneToClear - RXIC - Receive interrupt clear. Clears the UARTRXINTR interrupt. + PROC1_SWDO + Observe the value of processor 1 SWDIO output. [4:4] - read-write - oneToClear + read-only - DSRMIC - nUARTDSR modem interrupt clear. Clears the UARTDSRINTR interrupt. + PROC0_ATTACH + Attach processor 0 debug port to syscfg controls, and disconnect it from external SWD pads. [3:3] read-write - oneToClear - DCDMIC - nUARTDCD modem interrupt clear. Clears the UARTDCDINTR interrupt. + PROC0_SWCLK + Directly drive processor 0 SWCLK, if PROC0_ATTACH is set [2:2] read-write - oneToClear - CTSMIC - nUARTCTS modem interrupt clear. Clears the UARTCTSINTR interrupt. + PROC0_SWDI + Directly drive processor 0 SWDIO input, if PROC0_ATTACH is set [1:1] read-write - oneToClear - RIMIC - nUARTRI modem interrupt clear. Clears the UARTRIINTR interrupt. + PROC0_SWDO + Observe the value of processor 0 SWDIO output. [0:0] - read-write - oneToClear + read-only - UARTDMACR - DMA Control Register, UARTDMACR - 0x48 + MEMPOWERDOWN + Control power downs to memories. Set high to power down memories. + Use with extreme caution + 0x18 0x00000000 - DMAONERR - DMA on error. If this bit is set to 1, the DMA receive request outputs, UARTRXDMASREQ or UARTRXDMABREQ, are disabled when the UART error interrupt is asserted. - [2:2] + ROM + [7:7] read-write - TXDMAE - Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. - [1:1] + USB + [6:6] read-write - RXDMAE - Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is enabled. - [0:0] + SRAM5 + [5:5] read-write - - - - UARTPERIPHID0 - UARTPeriphID0 Register - 0xFE0 - 0x00000011 - - PARTNUMBER0 - These bits read back as 0x11 - [7:0] - read-only + SRAM4 + [4:4] + read-write - - - - UARTPERIPHID1 - UARTPeriphID1 Register - 0xFE4 - 0x00000010 - - DESIGNER0 - These bits read back as 0x1 - [7:4] - read-only + SRAM3 + [3:3] + read-write - PARTNUMBER1 - These bits read back as 0x0 - [3:0] - read-only + SRAM2 + [2:2] + read-write - - - - UARTPERIPHID2 - UARTPeriphID2 Register - 0xFE8 - 0x00000034 - - REVISION - This field depends on the revision of the UART: r1p0 0x0 r1p1 0x1 r1p3 0x2 r1p4 0x2 r1p5 0x3 - [7:4] - read-only + SRAM1 + [1:1] + read-write - DESIGNER1 - These bits read back as 0x4 - [3:0] - read-only + SRAM0 + [0:0] + read-write + + + + XOSC + Controls the crystal oscillator + 0x40024000 + + 0x0 + 0x20 + registers + + - UARTPERIPHID3 - UARTPeriphID3 Register - 0xFEC + CTRL + Crystal Oscillator Control + 0x0 0x00000000 - CONFIGURATION - These bits read back as 0x00 - [7:0] - read-only + ENABLE + On power-up this field is initialised to DISABLE and the chip runs from the ROSC. + If the chip has subsequently been programmed to run from the XOSC then DISABLE may lock-up the chip. If this is a concern then run the clk_ref from the ROSC and enable the clk_sys RESUS feature. + The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator. + [23:12] + read-write + + + DISABLE + 3358 + + + ENABLE + 4011 + + + + + FREQ_RANGE + Frequency range. An invalid setting will retain the previous value. The actual value being used can be read from STATUS_FREQ_RANGE. This resets to 0xAA0 and cannot be changed. + [11:0] + read-write + + + 1_15MHZ + 2720 + + + RESERVED_1 + 2721 + + + RESERVED_2 + 2722 + + + RESERVED_3 + 2723 + + - UARTPCELLID0 - UARTPCellID0 Register - 0xFF0 - 0x0000000D + STATUS + Crystal Oscillator Status + 0x4 + 0x00000000 - UARTPCELLID0 - These bits read back as 0x0D - [7:0] + STABLE + Oscillator is running and stable + [31:31] read-only - - - - UARTPCELLID1 - UARTPCellID1 Register - 0xFF4 - 0x000000F0 - - UARTPCELLID1 - These bits read back as 0xF0 - [7:0] + BADWRITE + An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or DORMANT + [24:24] + read-write + oneToClear + + + ENABLED + Oscillator is enabled but not necessarily running and stable, resets to 0 + [12:12] + read-only + + + FREQ_RANGE + The current frequency range setting, always reads 0 + [1:0] read-only + + + 1_15MHZ + 0 + + + RESERVED_1 + 1 + + + RESERVED_2 + 2 + + + RESERVED_3 + 3 + + - UARTPCELLID2 - UARTPCellID2 Register - 0xFF8 - 0x00000005 + DORMANT + Crystal Oscillator pause control + 0x8 + 0x00000000 - UARTPCELLID2 - These bits read back as 0x05 - [7:0] - read-only + DORMANT + This is used to save power by pausing the XOSC + On power-up this field is initialised to WAKE + An invalid write will also select WAKE + Warning: stop the PLLs before selecting dormant mode + Warning: setup the irq before selecting dormant mode + [31:0] + read-write + + + dormant + 1668246881 + + + WAKE + 2002873189 + + - UARTPCELLID3 - UARTPCellID3 Register - 0xFFC - 0x000000B1 + STARTUP + Controls the startup delay + 0xC + 0x00000000 - UARTPCELLID3 - These bits read back as 0xB1 - [7:0] - read-only + X4 + Multiplies the startup_delay by 4. This is of little value to the user given that the delay can be programmed directly. + [20:20] + read-write + + + DELAY + in multiples of 256*xtal_period. The reset value of 0xc4 corresponds to approx 50 000 cycles. + [13:0] + read-write - - UART1 - 0x40038000 - - UART1_IRQ - 21 - - - SPI0 - 1 - 0x4003C000 - 0x20 + PLL_SYS + 0x40028000 0x0 - 0x1000 + 0x10 registers - - SPI0_IRQ - 18 - - SSPCR0 - Control register 0, SSPCR0 on page 3-4 + CS + Control and Status + GENERAL CONSTRAINTS: + Reference clock frequency min=5MHz, max=800MHz + Feedback divider min=16, max=320 + VCO frequency min=750MHz, max=1600MHz 0x0 - 0x00000000 + 0x00000001 - SCR - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: F SSPCLK CPSDVSR x (1+SCR) where CPSDVSR is an even value from 2-254, programmed through the SSPCPSR register and SCR is a value from 0-255. - [15:8] - read-write - - - SPH - SSPCLKOUT phase, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10. - [7:7] - read-write - - - SPO - SSPCLKOUT polarity, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10. - [6:6] - read-write + LOCK + PLL is locked + [31:31] + read-only - FRF - Frame format. - [5:4] + BYPASS + Passes the reference clock to the output instead of the divided VCO. The VCO continues to run so the user can switch between the reference clock and the divided VCO but the output will glitch when doing so. + [8:8] read-write - - FRF - - Motorola - Motorola SPI frame format - 0 - - - Texas_Instruments - Texas Instruments synchronous serial frame format - 1 - - - National_Semiconductor_Microwire - National Semiconductor Microwire frame format - 2 - - - DSS - Data Size Select: 0000 Reserved, undefined operation. 0001 Reserved, undefined operation. 0010 Reserved, undefined operation. 0011 4-bit data. 0100 5-bit data. 0101 6-bit data. 0110 7-bit data. 0111 8-bit data. 1000 9-bit data. 1001 10-bit data. 1010 11-bit data. 1011 12-bit data. 1100 13-bit data. 1101 14-bit data. 1110 15-bit data. 1111 16-bit data. - [3:0] + REFDIV + Divides the PLL input reference clock. + Behaviour is undefined for div=0. + PLL output will be unpredictable during refdiv changes, wait for lock=1 before using it. + [5:0] read-write - SSPCR1 - Control register 1, SSPCR1 on page 3-5 + PWR + Controls the PLL power modes. 0x4 - 0x00000000 + 0x0000002D - SOD - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line: 0 SSP can drive the SSPTXD output in slave mode. 1 SSP must not drive the SSPTXD output in slave mode. + VCOPD + PLL VCO powerdown + To save power set high when PLL output not required or bypass=1. + [5:5] + read-write + + + POSTDIVPD + PLL post divider powerdown + To save power set high when PLL output not required or bypass=1. [3:3] read-write - MS - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0: 0 Device configured as master, default. 1 Device configured as slave. + DSMPD + PLL DSM powerdown + Nothing is achieved by setting this low. [2:2] read-write - SSE - Synchronous serial port enable: 0 SSP operation disabled. 1 SSP operation enabled. - [1:1] - read-write - - - LBM - Loop back mode: 0 Normal serial port operation enabled. 1 Output of transmit serial shifter is connected to input of receive serial shifter internally. - [0:0] + PD + PLL powerdown + To save power set high when PLL output not required. + [0:0] read-write - SSPDR - Data register, SSPDR on page 3-6 + FBDIV_INT + Feedback divisor + (note: this PLL does not support fractional division) 0x8 0x00000000 - DATA - Transmit/Receive FIFO: Read Receive FIFO. Write Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies. - [15:0] + FBDIV_INT + see ctrl reg description for constraints + [11:0] read-write - SSPSR - Status register, SSPSR on page 3-7 + PRIM + Controls the PLL post dividers for the primary output + (note: this PLL does not have a secondary output) + the primary output is driven from VCO divided by postdiv1*postdiv2 0xC - 0x00000003 + 0x00077000 - BSY - PrimeCell SSP busy flag, RO: 0 SSP is idle. 1 SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty. - [4:4] - read-only + POSTDIV1 + divide by 1-7 + [18:16] + read-write - RFF - Receive FIFO full, RO: 0 Receive FIFO is not full. 1 Receive FIFO is full. - [3:3] + POSTDIV2 + divide by 1-7 + [14:12] + read-write + + + + + + + PLL_USB + 0x4002C000 + + + UART0 + 0x40034000 + + 0x0 + 0x1000 + registers + + + UART0_IRQ + 20 + + + + UARTDR + Data Register, UARTDR + 0x0 + 0x00000000 + + + OE + Overrun error. This bit is set to 1 if data is received and the receive FIFO is already full. This is cleared to 0 once there is an empty space in the FIFO and a new character can be written to it. + [11:11] read-only - RNE - Receive FIFO not empty, RO: 0 Receive FIFO is empty. 1 Receive FIFO is not empty. - [2:2] + BE + Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity and stop bits). In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state), and the next valid start bit is received. + [10:10] read-only - TNF - Transmit FIFO not full, RO: 0 Transmit FIFO is full. 1 Transmit FIFO is not full. - [1:1] + PE + Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. In FIFO mode, this error is associated with the character at the top of the FIFO. + [9:9] read-only - TFE - Transmit FIFO empty, RO: 0 Transmit FIFO is not empty. 1 Transmit FIFO is empty. - [0:0] + FE + Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). In FIFO mode, this error is associated with the character at the top of the FIFO. + [8:8] read-only - - - - SSPCPSR - Clock prescale register, SSPCPSR on page 3-8 - 0x10 - 0x00000000 - - CPSDVSR - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads. + DATA + Receive (read) data character. Transmit (write) data character. [7:0] read-write + modify - SSPIMSC - Interrupt mask set or clear register, SSPIMSC on page 3-9 - 0x14 + UARTRSR + Receive Status Register/Error Clear Register, UARTRSR/UARTECR + 0x4 0x00000000 - TXIM - Transmit FIFO interrupt mask: 0 Transmit FIFO half empty or less condition interrupt is masked. 1 Transmit FIFO half empty or less condition interrupt is not masked. + OE + Overrun error. This bit is set to 1 if data is received and the FIFO is already full. This bit is cleared to 0 by a write to UARTECR. The FIFO contents remain valid because no more data is written when the FIFO is full, only the contents of the shift register are overwritten. The CPU must now read the data, to empty the FIFO. [3:3] read-write + oneToClear - RXIM - Receive FIFO interrupt mask: 0 Receive FIFO half full or less condition interrupt is masked. 1 Receive FIFO half full or less condition interrupt is not masked. + BE + Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity, and stop bits). This bit is cleared to 0 after a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received. [2:2] read-write + oneToClear - RTIM - Receive timeout interrupt mask: 0 Receive FIFO not empty and no read prior to timeout period interrupt is masked. 1 Receive FIFO not empty and no read prior to timeout period interrupt is not masked. + PE + Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. [1:1] read-write + oneToClear - RORIM - Receive overrun interrupt mask: 0 Receive FIFO written to while full condition interrupt is masked. 1 Receive FIFO written to while full condition interrupt is not masked. + FE + Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. [0:0] read-write + oneToClear - SSPRIS - Raw interrupt status register, SSPRIS on page 3-10 + UARTFR + Flag Register, UARTFR 0x18 - 0x00000008 + 0x00000090 - TXRIS - Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt - [3:3] + RI + Ring indicator. This bit is the complement of the UART ring indicator, nUARTRI, modem status input. That is, the bit is 1 when nUARTRI is LOW. + [8:8] read-only - RXRIS - Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt - [2:2] + TXFE + Transmit FIFO empty. The meaning of this bit depends on the state of the FEN bit in the Line Control Register, UARTLCR_H. If the FIFO is disabled, this bit is set when the transmit holding register is empty. If the FIFO is enabled, the TXFE bit is set when the transmit FIFO is empty. This bit does not indicate if there is data in the transmit shift register. + [7:7] read-only - RTRIS - Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt - [1:1] + RXFF + Receive FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the receive holding register is full. If the FIFO is enabled, the RXFF bit is set when the receive FIFO is full. + [6:6] read-only - RORRIS - Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt - [0:0] + TXFF + Transmit FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the transmit holding register is full. If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full. + [5:5] read-only - - - - SSPMIS - Masked interrupt status register, SSPMIS on page 3-11 - 0x1C - 0x00000000 - - TXMIS - Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt + RXFE + Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the receive holding register is empty. If the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty. + [4:4] + read-only + + + BUSY + UART busy. If this bit is set to 1, the UART is busy transmitting data. This bit remains set until the complete byte, including all the stop bits, has been sent from the shift register. This bit is set as soon as the transmit FIFO becomes non-empty, regardless of whether the UART is enabled or not. [3:3] read-only - RXMIS - Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt + DCD + Data carrier detect. This bit is the complement of the UART data carrier detect, nUARTDCD, modem status input. That is, the bit is 1 when nUARTDCD is LOW. [2:2] read-only - RTMIS - Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt + DSR + Data set ready. This bit is the complement of the UART data set ready, nUARTDSR, modem status input. That is, the bit is 1 when nUARTDSR is LOW. [1:1] read-only - RORMIS - Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt + CTS + Clear to send. This bit is the complement of the UART clear to send, nUARTCTS, modem status input. That is, the bit is 1 when nUARTCTS is LOW. [0:0] read-only - SSPICR - Interrupt clear register, SSPICR on page 3-11 + UARTILPR + IrDA Low-Power Counter Register, UARTILPR 0x20 0x00000000 - RTIC - Clears the SSPRTINTR interrupt - [1:1] - read-write - oneToClear - - - RORIC - Clears the SSPRORINTR interrupt - [0:0] + ILPDVSR + 8-bit low-power divisor value. These bits are cleared to 0 at reset. + [7:0] read-write - oneToClear - SSPDMACR - DMA control register, SSPDMACR on page 3-12 + UARTIBRD + Integer Baud Rate Register, UARTIBRD 0x24 0x00000000 - TXDMAE - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. - [1:1] - read-write - - - RXDMAE - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled. - [0:0] + BAUD_DIVINT + The integer baud rate divisor. These bits are cleared to 0 on reset. + [15:0] read-write - SSPPERIPHID0 - Peripheral identification registers, SSPPeriphID0-3 on page 3-13 - 0xFE0 - 0x00000022 + UARTFBRD + Fractional Baud Rate Register, UARTFBRD + 0x28 + 0x00000000 - PARTNUMBER0 - These bits read back as 0x22 - [7:0] - read-only + BAUD_DIVFRAC + The fractional baud rate divisor. These bits are cleared to 0 on reset. + [5:0] + read-write - SSPPERIPHID1 - Peripheral identification registers, SSPPeriphID0-3 on page 3-13 - 0xFE4 - 0x00000010 + UARTLCR_H + Line Control Register, UARTLCR_H + 0x2C + 0x00000000 - DESIGNER0 - These bits read back as 0x1 - [7:4] - read-only + SPS + Stick parity select. 0 = stick parity is disabled 1 = either: * if the EPS bit is 0 then the parity bit is transmitted and checked as a 1 * if the EPS bit is 1 then the parity bit is transmitted and checked as a 0. This bit has no effect when the PEN bit disables parity checking and generation. + [7:7] + read-write - PARTNUMBER1 - These bits read back as 0x0 - [3:0] - read-only - - - - - SSPPERIPHID2 - Peripheral identification registers, SSPPeriphID0-3 on page 3-13 - 0xFE8 - 0x00000034 - + WLEN + Word length. These bits indicate the number of data bits transmitted or received in a frame as follows: b11 = 8 bits b10 = 7 bits b01 = 6 bits b00 = 5 bits. + [6:5] + read-write + - REVISION - These bits return the peripheral revision - [7:4] - read-only + FEN + Enable FIFOs: 0 = FIFOs are disabled (character mode) that is, the FIFOs become 1-byte-deep holding registers 1 = transmit and receive FIFO buffers are enabled (FIFO mode). + [4:4] + read-write - DESIGNER1 - These bits read back as 0x4 - [3:0] - read-only + STP2 + Two stop bits select. If this bit is set to 1, two stop bits are transmitted at the end of the frame. The receive logic does not check for two stop bits being received. + [3:3] + read-write - - - - SSPPERIPHID3 - Peripheral identification registers, SSPPeriphID0-3 on page 3-13 - 0xFEC - 0x00000000 - - CONFIGURATION - These bits read back as 0x00 - [7:0] - read-only + EPS + Even parity select. Controls the type of parity the UART uses during transmission and reception: 0 = odd parity. The UART generates or checks for an odd number of 1s in the data and parity bits. 1 = even parity. The UART generates or checks for an even number of 1s in the data and parity bits. This bit has no effect when the PEN bit disables parity checking and generation. + [2:2] + read-write - - - - SSPPCELLID0 - PrimeCell identification registers, SSPPCellID0-3 on page 3-16 - 0xFF0 - 0x0000000D - - SSPPCELLID0 - These bits read back as 0x0D - [7:0] - read-only + PEN + Parity enable: 0 = parity is disabled and no parity bit added to the data frame 1 = parity checking and generation is enabled. + [1:1] + read-write - - - - SSPPCELLID1 - PrimeCell identification registers, SSPPCellID0-3 on page 3-16 - 0xFF4 - 0x000000F0 - - SSPPCELLID1 - These bits read back as 0xF0 - [7:0] - read-only + BRK + Send break. If this bit is set to 1, a low-level is continually output on the UARTTXD output, after completing transmission of the current character. For the proper execution of the break command, the software must set this bit for at least two complete frames. For normal use, this bit must be cleared to 0. + [0:0] + read-write - SSPPCELLID2 - PrimeCell identification registers, SSPPCellID0-3 on page 3-16 - 0xFF8 - 0x00000005 + UARTCR + Control Register, UARTCR + 0x30 + 0x00000300 - SSPPCELLID2 - These bits read back as 0x05 - [7:0] - read-only + CTSEN + CTS hardware flow control enable. If this bit is set to 1, CTS hardware flow control is enabled. Data is only transmitted when the nUARTCTS signal is asserted. + [15:15] + read-write - - - - SSPPCELLID3 - PrimeCell identification registers, SSPPCellID0-3 on page 3-16 - 0xFFC - 0x000000B1 - - SSPPCELLID3 - These bits read back as 0xB1 - [7:0] - read-only + RTSEN + RTS hardware flow control enable. If this bit is set to 1, RTS hardware flow control is enabled. Data is only requested when there is space in the receive FIFO for it to be received. + [14:14] + read-write - - - - - - SPI1 - 0x40040000 - - SPI1_IRQ - 19 - - - - I2C0 - 1 - DW_apb_i2c address block\n\n - List of configuration constants for the Synopsys I2C hardware (you may see references to these in I2C register header; these are *fixed* values, set at hardware design time):\n\n - IC_ULTRA_FAST_MODE ................ 0x0\n - IC_UFM_TBUF_CNT_DEFAULT ........... 0x8\n - IC_UFM_SCL_LOW_COUNT .............. 0x0008\n - IC_UFM_SCL_HIGH_COUNT ............. 0x0006\n - IC_TX_TL .......................... 0x0\n - IC_TX_CMD_BLOCK ................... 0x1\n - IC_HAS_DMA ........................ 0x1\n - IC_HAS_ASYNC_FIFO ................. 0x0\n - IC_SMBUS_ARP ...................... 0x0\n - IC_FIRST_DATA_BYTE_STATUS ......... 0x1\n - IC_INTR_IO ........................ 0x1\n - IC_MASTER_MODE .................... 0x1\n - IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1\n - IC_INTR_POL ....................... 0x1\n - IC_OPTIONAL_SAR ................... 0x0\n - IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055\n - IC_DEFAULT_SLAVE_ADDR ............. 0x055\n - IC_DEFAULT_HS_SPKLEN .............. 0x1\n - IC_FS_SCL_HIGH_COUNT .............. 0x0006\n - IC_HS_SCL_LOW_COUNT ............... 0x0008\n - IC_DEVICE_ID_VALUE ................ 0x0\n - IC_10BITADDR_MASTER ............... 0x0\n - IC_CLK_FREQ_OPTIMIZATION .......... 0x0\n - IC_DEFAULT_FS_SPKLEN .............. 0x7\n - IC_ADD_ENCODED_PARAMS ............. 0x0\n - IC_DEFAULT_SDA_HOLD ............... 0x000001\n - IC_DEFAULT_SDA_SETUP .............. 0x64\n - IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0\n - IC_CLOCK_PERIOD ................... 100\n - IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1\n - IC_RESTART_EN ..................... 0x1\n - IC_TX_CMD_BLOCK_DEFAULT ........... 0x0\n - IC_BUS_CLEAR_FEATURE .............. 0x0\n - IC_CAP_LOADING .................... 100\n - IC_FS_SCL_LOW_COUNT ............... 0x000d\n - APB_DATA_WIDTH .................... 32\n - IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff\n - IC_SLV_DATA_NACK_ONLY ............. 0x1\n - IC_10BITADDR_SLAVE ................ 0x0\n - IC_CLK_TYPE ....................... 0x0\n - IC_SMBUS_UDID_MSB ................. 0x0\n - IC_SMBUS_SUSPEND_ALERT ............ 0x0\n - IC_HS_SCL_HIGH_COUNT .............. 0x0006\n - IC_SLV_RESTART_DET_EN ............. 0x1\n - IC_SMBUS .......................... 0x0\n - IC_OPTIONAL_SAR_DEFAULT ........... 0x0\n - IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0\n - IC_USE_COUNTS ..................... 0x0\n - IC_RX_BUFFER_DEPTH ................ 16\n - IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff\n - IC_RX_FULL_HLD_BUS_EN ............. 0x1\n - IC_SLAVE_DISABLE .................. 0x1\n - IC_RX_TL .......................... 0x0\n - IC_DEVICE_ID ...................... 0x0\n - IC_HC_COUNT_VALUES ................ 0x0\n - I2C_DYNAMIC_TAR_UPDATE ............ 0\n - IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff\n - IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff\n - IC_HS_MASTER_CODE ................. 0x1\n - IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff\n - IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff\n - IC_SS_SCL_HIGH_COUNT .............. 0x0028\n - IC_SS_SCL_LOW_COUNT ............... 0x002f\n - IC_MAX_SPEED_MODE ................. 0x2\n - IC_STAT_FOR_CLK_STRETCH ........... 0x0\n - IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0\n - IC_DEFAULT_UFM_SPKLEN ............. 0x1\n - IC_TX_BUFFER_DEPTH ................ 16 - 0x40044000 - 0x20 - - 0x0 - 0x100 - registers - - - I2C0_IRQ - 23 - - - - IC_CON - I2C Control Register. This register can be written only when the DW_apb_i2c is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.\n\n - Read/Write Access: - bit 10 is read only. - bit 11 is read only - bit 16 is read only - bit 17 is read only - bits 18 and 19 are read only. - 0x0 - 0x00000065 - - STOP_DET_IF_MASTER_ACTIVE - Master issues the STOP_DET interrupt irrespective of whether master is active or not + OUT2 + This bit is the complement of the UART Out2 (nUARTOut2) modem status output. That is, when the bit is programmed to a 1, the output is 0. For DTE this can be used as Ring Indicator (RI). + [13:13] + read-write + + + OUT1 + This bit is the complement of the UART Out1 (nUARTOut1) modem status output. That is, when the bit is programmed to a 1 the output is 0. For DTE this can be used as Data Carrier Detect (DCD). + [12:12] + read-write + + + RTS + Request to send. This bit is the complement of the UART request to send, nUARTRTS, modem status output. That is, when the bit is programmed to a 1 then nUARTRTS is LOW. + [11:11] + read-write + + + DTR + Data transmit ready. This bit is the complement of the UART data transmit ready, nUARTDTR, modem status output. That is, when the bit is programmed to a 1 then nUARTDTR is LOW. [10:10] - read-only + read-write - RX_FIFO_FULL_HLD_CTRL - This bit controls whether DW_apb_i2c should hold the bus when the Rx FIFO is physically full to its RX_BUFFER_DEPTH, as described in the IC_RX_FULL_HLD_BUS_EN parameter.\n\n - Reset value: 0x0. + RXE + Receive enable. If this bit is set to 1, the receive section of the UART is enabled. Data reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of reception, it completes the current character before stopping. [9:9] read-write - - - DISABLED - Overflow when RX_FIFO is full - 0 - - - ENABLED - Hold bus when RX_FIFO is full - 1 - - - TX_EMPTY_CTRL - This bit controls the generation of the TX_EMPTY interrupt, as described in the IC_RAW_INTR_STAT register.\n\n - Reset value: 0x0. + TXE + Transmit enable. If this bit is set to 1, the transmit section of the UART is enabled. Data transmission occurs for either UART signals, or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of transmission, it completes the current character before stopping. [8:8] read-write - - - DISABLED - Default behaviour of TX_EMPTY interrupt - 0 - - - ENABLED - Controlled generation of TX_EMPTY interrupt - 1 - - - STOP_DET_IFADDRESSED - In slave mode: - 1'b1: issues the STOP_DET interrupt only when it is addressed. - 1'b0: issues the STOP_DET irrespective of whether it's addressed or not. Reset value: 0x0\n\n - NOTE: During a general call address, this slave does not issue the STOP_DET interrupt if STOP_DET_IF_ADDRESSED = 1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR). + LBE + Loopback enable. If this bit is set to 1 and the SIREN bit is set to 1 and the SIRTEST bit in the Test Control Register, UARTTCR is set to 1, then the nSIROUT path is inverted, and fed through to the SIRIN path. The SIRTEST bit in the test register must be set to 1 to override the normal half-duplex SIR operation. This must be the requirement for accessing the test registers during normal operation, and SIRTEST must be cleared to 0 when loopback testing is finished. This feature reduces the amount of external coupling required during system test. If this bit is set to 1, and the SIRTEST bit is set to 0, the UARTTXD path is fed through to the UARTRXD path. In either SIR mode or UART mode, when this bit is set, the modem outputs are also fed through to the modem inputs. This bit is cleared to 0 on reset, to disable loopback. [7:7] read-write - - - DISABLED - slave issues STOP_DET intr always - 0 - - - ENABLED - slave issues STOP_DET intr only if addressed - 1 - - - IC_SLAVE_DISABLE - This bit controls whether I2C has its slave disabled, which means once the presetn signal is applied, then this bit is set and the slave is disabled.\n\n - If this bit is set (slave is disabled), DW_apb_i2c functions only as a master and does not perform any action that requires a slave.\n\n - NOTE: Software should ensure that if this bit is written with 0, then bit 0 should also be written with a 0. - [6:6] + SIRLP + SIR low-power IrDA mode. This bit selects the IrDA encoding mode. If this bit is cleared to 0, low-level bits are transmitted as an active high pulse with a width of 3 / 16th of the bit period. If this bit is set to 1, low-level bits are transmitted with a pulse width that is 3 times the period of the IrLPBaud16 input signal, regardless of the selected bit rate. Setting this bit uses less power, but might reduce transmission distances. + [2:2] read-write - - - SLAVE_ENABLED - Slave mode is enabled - 0 - - - SLAVE_DISABLED - Slave mode is disabled - 1 - - - IC_RESTART_EN - Determines whether RESTART conditions may be sent when acting as a master. Some older slaves do not support handling RESTART conditions; however, RESTART conditions are used in several DW_apb_i2c operations. When RESTART is disabled, the master is prohibited from performing the following functions: - Sending a START BYTE - Performing any high-speed mode operation - High-speed mode operation - Performing direction changes in combined format mode - Performing a read operation with a 10-bit address By replacing RESTART condition followed by a STOP and a subsequent START condition, split operations are broken down into multiple DW_apb_i2c transfers. If the above operations are performed, it will result in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register.\n\n - Reset value: ENABLED - [5:5] + SIREN + SIR enable: 0 = IrDA SIR ENDEC is disabled. nSIROUT remains LOW (no light pulse generated), and signal transitions on SIRIN have no effect. 1 = IrDA SIR ENDEC is enabled. Data is transmitted and received on nSIROUT and SIRIN. UARTTXD remains HIGH, in the marking state. Signal transitions on UARTRXD or modem status inputs have no effect. This bit has no effect if the UARTEN bit disables the UART. + [1:1] read-write - - - DISABLED - Master restart disabled - 0 - - - ENABLED - Master restart enabled - 1 - - - IC_10BITADDR_MASTER - Controls whether the DW_apb_i2c starts its transfers in 7- or 10-bit addressing mode when acting as a master. - 0: 7-bit addressing - 1: 10-bit addressing - [4:4] + UARTEN + UART enable: 0 = UART is disabled. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. 1 = the UART is enabled. Data transmission and reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. + [0:0] read-write - - - ADDR_7BITS - Master 7Bit addressing mode - 0 - - - ADDR_10BITS - Master 10Bit addressing mode - 1 - - - - - IC_10BITADDR_SLAVE - When acting as a slave, this bit controls whether the DW_apb_i2c responds to 7- or 10-bit addresses. - 0: 7-bit addressing. The DW_apb_i2c ignores transactions that involve 10-bit addressing; for 7-bit addressing, only the lower 7 bits of the IC_SAR register are compared. - 1: 10-bit addressing. The DW_apb_i2c responds to only 10-bit addressing transfers that match the full 10 bits of the IC_SAR register. - [3:3] - read-write - - - ADDR_7BITS - Slave 7Bit addressing - 0 - - - ADDR_10BITS - Slave 10Bit addressing - 1 - - + + + + UARTIFLS + Interrupt FIFO Level Select Register, UARTIFLS + 0x34 + 0x00000012 + - SPEED - These bits control at which speed the DW_apb_i2c operates; its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode also, as it is used to capture correct value of spike filter as per the speed mode.\n\n - This register should be programmed only with a value in the range of 1 to IC_MAX_SPEED_MODE; otherwise, hardware updates this register with the value of IC_MAX_SPEED_MODE.\n\n - 1: standard mode (100 kbit/s)\n\n - 2: fast mode (<=400 kbit/s) or fast mode plus (<=1000Kbit/s)\n\n - 3: high speed mode (3.4 Mbit/s)\n\n - Note: This field is not applicable when IC_ULTRA_FAST_MODE=1 - [2:1] + RXIFLSEL + Receive interrupt FIFO level select. The trigger points for the receive interrupt are as follows: b000 = Receive FIFO becomes >= 1 / 8 full b001 = Receive FIFO becomes >= 1 / 4 full b010 = Receive FIFO becomes >= 1 / 2 full b011 = Receive FIFO becomes >= 3 / 4 full b100 = Receive FIFO becomes >= 7 / 8 full b101-b111 = reserved. + [5:3] read-write - - - STANDARD - Standard Speed mode of operation - 1 - - - FAST - Fast or Fast Plus mode of operation - 2 - - - HIGH - High Speed mode of operation - 3 - - - MASTER_MODE - This bit controls whether the DW_apb_i2c master is enabled.\n\n - NOTE: Software should ensure that if this bit is written with '1' then bit 6 should also be written with a '1'. - [0:0] + TXIFLSEL + Transmit interrupt FIFO level select. The trigger points for the transmit interrupt are as follows: b000 = Transmit FIFO becomes <= 1 / 8 full b001 = Transmit FIFO becomes <= 1 / 4 full b010 = Transmit FIFO becomes <= 1 / 2 full b011 = Transmit FIFO becomes <= 3 / 4 full b100 = Transmit FIFO becomes <= 7 / 8 full b101-b111 = reserved. + [2:0] read-write - - - DISABLED - Master mode is disabled - 0 - - - ENABLED - Master mode is enabled - 1 - - - IC_TAR - I2C Target Address Register\n\n - This register is 12 bits wide, and bits 31:12 are reserved. This register can be written to only when IC_ENABLE[0] is set to 0.\n\n - Note: If the software or application is aware that the DW_apb_i2c is not using the TAR address for the pending commands in the Tx FIFO, then it is possible to update the TAR address even while the Tx FIFO has entries (IC_STATUS[2]= 0). - It is not necessary to perform any write to this register if DW_apb_i2c is enabled as an I2C slave only. - 0x4 - 0x00000055 + UARTIMSC + Interrupt Mask Set/Clear Register, UARTIMSC + 0x38 + 0x00000000 - SPECIAL - This bit indicates whether software performs a Device-ID or General Call or START BYTE command. - 0: ignore bit 10 GC_OR_START and use IC_TAR normally - 1: perform special I2C command as specified in Device_ID or GC_OR_START bit Reset value: 0x0 - [11:11] - read-write - - - DISABLED - Disables programming of GENERAL_CALL or START_BYTE transmission - 0 - - - ENABLED - Enables programming of GENERAL_CALL or START_BYTE transmission - 1 - - - - - GC_OR_START - If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to 0, then this bit indicates whether a General Call or START byte command is to be performed by the DW_apb_i2c. - 0: General Call Address - after issuing a General Call, only writes may be performed. Attempting to issue a read command results in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. The DW_apb_i2c remains in General Call mode until the SPECIAL bit value (bit 11) is cleared. - 1: START BYTE Reset value: 0x0 + OEIM + Overrun error interrupt mask. A read returns the current mask for the UARTOEINTR interrupt. On a write of 1, the mask of the UARTOEINTR interrupt is set. A write of 0 clears the mask. [10:10] read-write - - - GENERAL_CALL - GENERAL_CALL byte transmission - 0 - - - START_BYTE - START byte transmission - 1 - - - IC_TAR - This is the target address for any master transaction. When transmitting a General Call, these bits are ignored. To generate a START BYTE, the CPU needs to write only once into these bits.\n\n - If the IC_TAR and IC_SAR are the same, loopback exists but the FIFOs are shared between master and slave, so full loopback is not feasible. Only one direction loopback mode is supported (simplex), not duplex. A master cannot transmit to itself; it can transmit to only a slave. - [9:0] + BEIM + Break error interrupt mask. A read returns the current mask for the UARTBEINTR interrupt. On a write of 1, the mask of the UARTBEINTR interrupt is set. A write of 0 clears the mask. + [9:9] read-write - - - - IC_SAR - I2C Slave Address Register - 0x8 - 0x00000055 - - IC_SAR - The IC_SAR holds the slave address when the I2C is operating as a slave. For 7-bit addressing, only IC_SAR[6:0] is used.\n\n - This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.\n\n - Note: The default values cannot be any of the reserved address locations: that is, 0x00 to 0x07, or 0x78 to 0x7f. The correct operation of the device is not guaranteed if you program the IC_SAR or IC_TAR to a reserved value. Refer to <<table_I2C_firstbyte_bit_defs>> for a complete list of these reserved values. - [9:0] + PEIM + Parity error interrupt mask. A read returns the current mask for the UARTPEINTR interrupt. On a write of 1, the mask of the UARTPEINTR interrupt is set. A write of 0 clears the mask. + [8:8] read-write - - - - IC_DATA_CMD - I2C Rx/Tx Data Buffer and Command Register; this is the register the CPU writes to when filling the TX FIFO and the CPU reads from when retrieving bytes from RX FIFO.\n\n - The size of the register changes as follows:\n\n - Write: - 11 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=1 - 9 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=0 Read: - 12 bits when IC_FIRST_DATA_BYTE_STATUS = 1 - 8 bits when IC_FIRST_DATA_BYTE_STATUS = 0 Note: In order for the DW_apb_i2c to continue acknowledging reads, a read command should be written for every byte that is to be received; otherwise the DW_apb_i2c will stop acknowledging. - 0x10 - 0x00000000 - - FIRST_DATA_BYTE - Indicates the first data byte received after the address phase for receive transfer in Master receiver or Slave receiver mode.\n\n - Reset value : 0x0\n\n - NOTE: In case of APB_DATA_WIDTH=8,\n\n - 1. The user has to perform two APB Reads to IC_DATA_CMD in order to get status on 11 bit.\n\n - 2. In order to read the 11 bit, the user has to perform the first data byte read [7:0] (offset 0x10) and then perform the second read [15:8] (offset 0x11) in order to know the status of 11 bit (whether the data received in previous read is a first data byte or not).\n\n - 3. The 11th bit is an optional read field, user can ignore 2nd byte read [15:8] (offset 0x11) if not interested in FIRST_DATA_BYTE status. - [11:11] - read-only - - - INACTIVE - Sequential data byte received - 0 - - - ACTIVE - Non sequential data byte received - 1 - - + FEIM + Framing error interrupt mask. A read returns the current mask for the UARTFEINTR interrupt. On a write of 1, the mask of the UARTFEINTR interrupt is set. A write of 0 clears the mask. + [7:7] + read-write - RESTART - This bit controls whether a RESTART is issued before the byte is sent or received.\n\n - 1 - If IC_RESTART_EN is 1, a RESTART is issued before the data is sent/received (according to the value of CMD), regardless of whether or not the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead.\n\n - 0 - If IC_RESTART_EN is 1, a RESTART is issued only if the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead.\n\n - Reset value: 0x0 - [10:10] + RTIM + Receive timeout interrupt mask. A read returns the current mask for the UARTRTINTR interrupt. On a write of 1, the mask of the UARTRTINTR interrupt is set. A write of 0 clears the mask. + [6:6] read-write - clear - - - DISABLE - Don't Issue RESTART before this command - 0 - - - ENABLE - Issue RESTART before this command - 1 - - - STOP - This bit controls whether a STOP is issued after the byte is sent or received.\n\n - - 1 - STOP is issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master immediately tries to start a new transfer by issuing a START and arbitrating for the bus. - 0 - STOP is not issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master continues the current transfer by sending/receiving data bytes according to the value of the CMD bit. If the Tx FIFO is empty, the master holds the SCL line low and stalls the bus until a new command is available in the Tx FIFO. Reset value: 0x0 - [9:9] + TXIM + Transmit interrupt mask. A read returns the current mask for the UARTTXINTR interrupt. On a write of 1, the mask of the UARTTXINTR interrupt is set. A write of 0 clears the mask. + [5:5] read-write - clear - - - DISABLE - Don't Issue STOP after this command - 0 - - - ENABLE - Issue STOP after this command - 1 - - - CMD - This bit controls whether a read or a write is performed. This bit does not control the direction when the DW_apb_i2con acts as a slave. It controls only the direction when it acts as a master.\n\n - When a command is entered in the TX FIFO, this bit distinguishes the write and read commands. In slave-receiver mode, this bit is a 'don't care' because writes to this register are not required. In slave-transmitter mode, a '0' indicates that the data in IC_DATA_CMD is to be transmitted.\n\n - When programming this bit, you should remember the following: attempting to perform a read operation after a General Call command has been sent results in a TX_ABRT interrupt (bit 6 of the IC_RAW_INTR_STAT register), unless bit 11 (SPECIAL) in the IC_TAR register has been cleared. If a '1' is written to this bit after receiving a RD_REQ interrupt, then a TX_ABRT interrupt occurs.\n\n - Reset value: 0x0 - [8:8] + RXIM + Receive interrupt mask. A read returns the current mask for the UARTRXINTR interrupt. On a write of 1, the mask of the UARTRXINTR interrupt is set. A write of 0 clears the mask. + [4:4] read-write - clear - - - WRITE - Master Write Command - 0 - - - READ - Master Read Command - 1 - - - DAT - This register contains the data to be transmitted or received on the I2C bus. If you are writing to this register and want to perform a read, bits 7:0 (DAT) are ignored by the DW_apb_i2c. However, when you read this register, these bits return the value of data received on the DW_apb_i2c interface.\n\n - Reset value: 0x0 - [7:0] + DSRMIM + nUARTDSR modem interrupt mask. A read returns the current mask for the UARTDSRINTR interrupt. On a write of 1, the mask of the UARTDSRINTR interrupt is set. A write of 0 clears the mask. + [3:3] read-write - - - - IC_SS_SCL_HCNT - Standard Speed I2C Clock SCL High Count Register - 0x14 - 0x00000028 - - IC_SS_SCL_HCNT - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration'.\n\n - This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.\n\n - The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed.\n\n - NOTE: This register must not be programmed to a value higher than 65525, because DW_apb_i2c uses a 16-bit counter to flag an I2C bus idle condition when this counter reaches a value of IC_SS_SCL_HCNT + 10. - [15:0] + DCDMIM + nUARTDCD modem interrupt mask. A read returns the current mask for the UARTDCDINTR interrupt. On a write of 1, the mask of the UARTDCDINTR interrupt is set. A write of 0 clears the mask. + [2:2] read-write - - - - IC_SS_SCL_LCNT - Standard Speed I2C Clock SCL Low Count Register - 0x18 - 0x0000002F - - IC_SS_SCL_LCNT - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration'\n\n - This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.\n\n - The minimum valid value is 8; hardware prevents values less than this being written, and if attempted, results in 8 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of DW_apb_i2c. The lower byte must be programmed first, and then the upper byte is programmed. - [15:0] + CTSMIM + nUARTCTS modem interrupt mask. A read returns the current mask for the UARTCTSINTR interrupt. On a write of 1, the mask of the UARTCTSINTR interrupt is set. A write of 0 clears the mask. + [1:1] read-write - - - - IC_FS_SCL_HCNT - Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register - 0x1C - 0x00000006 - - IC_FS_SCL_HCNT - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for fast mode or fast mode plus. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'.\n\n - This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.\n\n - The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH == 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. - [15:0] + RIMIM + nUARTRI modem interrupt mask. A read returns the current mask for the UARTRIINTR interrupt. On a write of 1, the mask of the UARTRIINTR interrupt is set. A write of 0 clears the mask. + [0:0] read-write - IC_FS_SCL_LCNT - Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register - 0x20 - 0x0000000D + UARTRIS + Raw Interrupt Status Register, UARTRIS + 0x3C + 0x00000000 - IC_FS_SCL_LCNT - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for fast speed. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'.\n\n - This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard.\n\n - This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.\n\n - The minimum valid value is 8; hardware prevents values less than this being written, and if attempted results in 8 being set. For designs with APB_DATA_WIDTH = 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. If the value is less than 8 then the count value gets changed to 8. - [15:0] - read-write - - - - - IC_INTR_STAT - I2C Interrupt Status Register\n\n - Each bit in this register has a corresponding mask bit in the IC_INTR_MASK register. These bits are cleared by reading the matching interrupt clear register. The unmasked raw versions of these bits are available in the IC_RAW_INTR_STAT register. - 0x2C - 0x00000000 - - - R_RESTART_DET - See IC_RAW_INTR_STAT for a detailed description of R_RESTART_DET bit.\n\n - Reset value: 0x0 - [12:12] - read-only - - - INACTIVE - R_RESTART_DET interrupt is inactive - 0 - - - ACTIVE - R_RESTART_DET interrupt is active - 1 - - - - - R_GEN_CALL - See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL bit.\n\n - Reset value: 0x0 - [11:11] - read-only - - - INACTIVE - R_GEN_CALL interrupt is inactive - 0 - - - ACTIVE - R_GEN_CALL interrupt is active - 1 - - - - - R_START_DET - See IC_RAW_INTR_STAT for a detailed description of R_START_DET bit.\n\n - Reset value: 0x0 + OERIS + Overrun error interrupt status. Returns the raw interrupt state of the UARTOEINTR interrupt. [10:10] read-only - - - INACTIVE - R_START_DET interrupt is inactive - 0 - - - ACTIVE - R_START_DET interrupt is active - 1 - - - R_STOP_DET - See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET bit.\n\n - Reset value: 0x0 + BERIS + Break error interrupt status. Returns the raw interrupt state of the UARTBEINTR interrupt. [9:9] read-only - - - INACTIVE - R_STOP_DET interrupt is inactive - 0 - - - ACTIVE - R_STOP_DET interrupt is active - 1 - - - R_ACTIVITY - See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY bit.\n\n - Reset value: 0x0 + PERIS + Parity error interrupt status. Returns the raw interrupt state of the UARTPEINTR interrupt. [8:8] read-only - - - INACTIVE - R_ACTIVITY interrupt is inactive - 0 - - - ACTIVE - R_ACTIVITY interrupt is active - 1 - - - R_RX_DONE - See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE bit.\n\n - Reset value: 0x0 + FERIS + Framing error interrupt status. Returns the raw interrupt state of the UARTFEINTR interrupt. [7:7] read-only - - - INACTIVE - R_RX_DONE interrupt is inactive - 0 - - - ACTIVE - R_RX_DONE interrupt is active - 1 - - - R_TX_ABRT - See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT bit.\n\n - Reset value: 0x0 + RTRIS + Receive timeout interrupt status. Returns the raw interrupt state of the UARTRTINTR interrupt. a [6:6] read-only - - - INACTIVE - R_TX_ABRT interrupt is inactive - 0 - - - ACTIVE - R_TX_ABRT interrupt is active - 1 - - - R_RD_REQ - See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ bit.\n\n - Reset value: 0x0 + TXRIS + Transmit interrupt status. Returns the raw interrupt state of the UARTTXINTR interrupt. [5:5] read-only - - - INACTIVE - R_RD_REQ interrupt is inactive - 0 - - - ACTIVE - R_RD_REQ interrupt is active - 1 - - - R_TX_EMPTY - See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY bit.\n\n - Reset value: 0x0 + RXRIS + Receive interrupt status. Returns the raw interrupt state of the UARTRXINTR interrupt. [4:4] read-only - - - INACTIVE - R_TX_EMPTY interrupt is inactive - 0 - - - ACTIVE - R_TX_EMPTY interrupt is active - 1 - - - R_TX_OVER - See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER bit.\n\n - Reset value: 0x0 + DSRRMIS + nUARTDSR modem interrupt status. Returns the raw interrupt state of the UARTDSRINTR interrupt. [3:3] read-only - - - INACTIVE - R_TX_OVER interrupt is inactive - 0 - - - ACTIVE - R_TX_OVER interrupt is active - 1 - - - R_RX_FULL - See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL bit.\n\n - Reset value: 0x0 + DCDRMIS + nUARTDCD modem interrupt status. Returns the raw interrupt state of the UARTDCDINTR interrupt. [2:2] read-only - - - INACTIVE - R_RX_FULL interrupt is inactive - 0 - - - ACTIVE - R_RX_FULL interrupt is active - 1 - - - R_RX_OVER - See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER bit.\n\n - Reset value: 0x0 + CTSRMIS + nUARTCTS modem interrupt status. Returns the raw interrupt state of the UARTCTSINTR interrupt. [1:1] read-only - - - INACTIVE - R_RX_OVER interrupt is inactive - 0 - - - ACTIVE - R_RX_OVER interrupt is active - 1 - - - R_RX_UNDER - See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER bit.\n\n - Reset value: 0x0 + RIRMIS + nUARTRI modem interrupt status. Returns the raw interrupt state of the UARTRIINTR interrupt. [0:0] read-only - - - INACTIVE - RX_UNDER interrupt is inactive - 0 - - - ACTIVE - RX_UNDER interrupt is active - 1 - - - IC_INTR_MASK - I2C Interrupt Mask Register.\n\n - These bits mask their corresponding interrupt status bits. This register is active low; a value of 0 masks the interrupt, whereas a value of 1 unmasks the interrupt. - 0x30 - 0x000008FF + UARTMIS + Masked Interrupt Status Register, UARTMIS + 0x40 + 0x00000000 - M_RESTART_DET - This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register.\n\n - Reset value: 0x0 - [12:12] - read-write - - - ENABLED - RESTART_DET interrupt is masked - 0 - - - DISABLED - RESTART_DET interrupt is unmasked - 1 - - + OEMIS + Overrun error masked interrupt status. Returns the masked interrupt state of the UARTOEINTR interrupt. + [10:10] + read-only - M_GEN_CALL - This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register.\n\n - Reset value: 0x1 - [11:11] - read-write - - - ENABLED - GEN_CALL interrupt is masked - 0 - - - DISABLED - GEN_CALL interrupt is unmasked - 1 - - + BEMIS + Break error masked interrupt status. Returns the masked interrupt state of the UARTBEINTR interrupt. + [9:9] + read-only - M_START_DET - This bit masks the R_START_DET interrupt in IC_INTR_STAT register.\n\n - Reset value: 0x0 + PEMIS + Parity error masked interrupt status. Returns the masked interrupt state of the UARTPEINTR interrupt. + [8:8] + read-only + + + FEMIS + Framing error masked interrupt status. Returns the masked interrupt state of the UARTFEINTR interrupt. + [7:7] + read-only + + + RTMIS + Receive timeout masked interrupt status. Returns the masked interrupt state of the UARTRTINTR interrupt. + [6:6] + read-only + + + TXMIS + Transmit masked interrupt status. Returns the masked interrupt state of the UARTTXINTR interrupt. + [5:5] + read-only + + + RXMIS + Receive masked interrupt status. Returns the masked interrupt state of the UARTRXINTR interrupt. + [4:4] + read-only + + + DSRMMIS + nUARTDSR modem masked interrupt status. Returns the masked interrupt state of the UARTDSRINTR interrupt. + [3:3] + read-only + + + DCDMMIS + nUARTDCD modem masked interrupt status. Returns the masked interrupt state of the UARTDCDINTR interrupt. + [2:2] + read-only + + + CTSMMIS + nUARTCTS modem masked interrupt status. Returns the masked interrupt state of the UARTCTSINTR interrupt. + [1:1] + read-only + + + RIMMIS + nUARTRI modem masked interrupt status. Returns the masked interrupt state of the UARTRIINTR interrupt. + [0:0] + read-only + + + + + UARTICR + Interrupt Clear Register, UARTICR + 0x44 + 0x00000000 + + + OEIC + Overrun error interrupt clear. Clears the UARTOEINTR interrupt. [10:10] read-write - - - ENABLED - START_DET interrupt is masked - 0 - - - DISABLED - START_DET interrupt is unmasked - 1 - - + oneToClear - M_STOP_DET - This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register.\n\n - Reset value: 0x0 + BEIC + Break error interrupt clear. Clears the UARTBEINTR interrupt. [9:9] read-write - - - ENABLED - STOP_DET interrupt is masked - 0 - - - DISABLED - STOP_DET interrupt is unmasked - 1 - - + oneToClear - M_ACTIVITY - This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register.\n\n - Reset value: 0x0 + PEIC + Parity error interrupt clear. Clears the UARTPEINTR interrupt. [8:8] read-write - - - ENABLED - ACTIVITY interrupt is masked - 0 - - - DISABLED - ACTIVITY interrupt is unmasked - 1 - - + oneToClear - M_RX_DONE - This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register.\n\n - Reset value: 0x1 + FEIC + Framing error interrupt clear. Clears the UARTFEINTR interrupt. [7:7] read-write - - - ENABLED - RX_DONE interrupt is masked - 0 - - - DISABLED - RX_DONE interrupt is unmasked - 1 - - + oneToClear - M_TX_ABRT - This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register.\n\n - Reset value: 0x1 + RTIC + Receive timeout interrupt clear. Clears the UARTRTINTR interrupt. [6:6] read-write - - - ENABLED - TX_ABORT interrupt is masked - 0 - - - DISABLED - TX_ABORT interrupt is unmasked - 1 - - + oneToClear - M_RD_REQ - This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register.\n\n - Reset value: 0x1 + TXIC + Transmit interrupt clear. Clears the UARTTXINTR interrupt. [5:5] read-write - - - ENABLED - RD_REQ interrupt is masked - 0 - - - DISABLED - RD_REQ interrupt is unmasked - 1 - - + oneToClear - M_TX_EMPTY - This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register.\n\n - Reset value: 0x1 + RXIC + Receive interrupt clear. Clears the UARTRXINTR interrupt. [4:4] read-write - - - ENABLED - TX_EMPTY interrupt is masked - 0 - - - DISABLED - TX_EMPTY interrupt is unmasked - 1 - - + oneToClear - M_TX_OVER - This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register.\n\n - Reset value: 0x1 + DSRMIC + nUARTDSR modem interrupt clear. Clears the UARTDSRINTR interrupt. [3:3] read-write - - - ENABLED - TX_OVER interrupt is masked - 0 - - - DISABLED - TX_OVER interrupt is unmasked - 1 - - + oneToClear - M_RX_FULL - This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register.\n\n - Reset value: 0x1 + DCDMIC + nUARTDCD modem interrupt clear. Clears the UARTDCDINTR interrupt. [2:2] read-write - - - ENABLED - RX_FULL interrupt is masked - 0 - - - DISABLED - RX_FULL interrupt is unmasked - 1 - - + oneToClear - M_RX_OVER - This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register.\n\n - Reset value: 0x1 + CTSMIC + nUARTCTS modem interrupt clear. Clears the UARTCTSINTR interrupt. [1:1] read-write - - - ENABLED - RX_OVER interrupt is masked - 0 - - - DISABLED - RX_OVER interrupt is unmasked - 1 - - + oneToClear - M_RX_UNDER - This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register.\n\n - Reset value: 0x1 + RIMIC + nUARTRI modem interrupt clear. Clears the UARTRIINTR interrupt. [0:0] read-write - - - ENABLED - RX_UNDER interrupt is masked - 0 - - - DISABLED - RX_UNDER interrupt is unmasked - 1 - - + oneToClear - IC_RAW_INTR_STAT - I2C Raw Interrupt Status Register\n\n - Unlike the IC_INTR_STAT register, these bits are not masked so they always show the true status of the DW_apb_i2c. - 0x34 + UARTDMACR + DMA Control Register, UARTDMACR + 0x48 0x00000000 - RESTART_DET - Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in Slave mode and the slave is being addressed. Enabled only when IC_SLV_RESTART_DET_EN=1.\n\n - Note: However, in high-speed mode or during a START BYTE transfer, the RESTART comes before the address field as per the I2C protocol. In this case, the slave is not the addressed slave when the RESTART is issued, therefore DW_apb_i2c does not generate the RESTART_DET interrupt.\n\n - Reset value: 0x0 - [12:12] - read-only - - - INACTIVE - RESTART_DET interrupt is inactive - 0 - - - ACTIVE - RESTART_DET interrupt is active - 1 - - - - - GEN_CALL - Set only when a General Call address is received and it is acknowledged. It stays set until it is cleared either by disabling DW_apb_i2c or when the CPU reads bit 0 of the IC_CLR_GEN_CALL register. DW_apb_i2c stores the received data in the Rx buffer.\n\n - Reset value: 0x0 - [11:11] - read-only - - - INACTIVE - GEN_CALL interrupt is inactive - 0 - - - ACTIVE - GEN_CALL interrupt is active - 1 - - - - - START_DET - Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode.\n\n - Reset value: 0x0 - [10:10] - read-only - - - INACTIVE - START_DET interrupt is inactive - 0 - - - ACTIVE - START_DET interrupt is active - 1 - - - - - STOP_DET - Indicates whether a STOP condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode.\n\n - In Slave Mode: - If IC_CON[7]=1'b1 (STOP_DET_IFADDRESSED), the STOP_DET interrupt will be issued only if slave is addressed. Note: During a general call address, this slave does not issue a STOP_DET interrupt if STOP_DET_IF_ADDRESSED=1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR). - If IC_CON[7]=1'b0 (STOP_DET_IFADDRESSED), the STOP_DET interrupt is issued irrespective of whether it is being addressed. In Master Mode: - If IC_CON[10]=1'b1 (STOP_DET_IF_MASTER_ACTIVE),the STOP_DET interrupt will be issued only if Master is active. - If IC_CON[10]=1'b0 (STOP_DET_IFADDRESSED),the STOP_DET interrupt will be issued irrespective of whether master is active or not. Reset value: 0x0 - [9:9] - read-only - - - INACTIVE - STOP_DET interrupt is inactive - 0 - - - ACTIVE - STOP_DET interrupt is active - 1 - - - - - ACTIVITY - This bit captures DW_apb_i2c activity and stays set until it is cleared. There are four ways to clear it: - Disabling the DW_apb_i2c - Reading the IC_CLR_ACTIVITY register - Reading the IC_CLR_INTR register - System reset Once this bit is set, it stays set unless one of the four methods is used to clear it. Even if the DW_apb_i2c module is idle, this bit remains set until cleared, indicating that there was activity on the bus.\n\n - Reset value: 0x0 - [8:8] - read-only - - - INACTIVE - RAW_INTR_ACTIVITY interrupt is inactive - 0 - - - ACTIVE - RAW_INTR_ACTIVITY interrupt is active - 1 - - - - - RX_DONE - When the DW_apb_i2c is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte. This occurs on the last byte of the transmission, indicating that the transmission is done.\n\n - Reset value: 0x0 - [7:7] - read-only - - - INACTIVE - RX_DONE interrupt is inactive - 0 - - - ACTIVE - RX_DONE interrupt is active - 1 - - + DMAONERR + DMA on error. If this bit is set to 1, the DMA receive request outputs, UARTRXDMASREQ or UARTRXDMABREQ, are disabled when the UART error interrupt is asserted. + [2:2] + read-write - TX_ABRT - This bit indicates if DW_apb_i2c, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO. This situation can occur both as an I2C master or an I2C slave, and is referred to as a 'transmit abort'. When this bit is set to 1, the IC_TX_ABRT_SOURCE register indicates the reason why the transmit abort takes places.\n\n - Note: The DW_apb_i2c flushes/resets/empties the TX_FIFO and RX_FIFO whenever there is a transmit abort caused by any of the events tracked by the IC_TX_ABRT_SOURCE register. The FIFOs remains in this flushed state until the register IC_CLR_TX_ABRT is read. Once this read is performed, the Tx FIFO is then ready to accept more data bytes from the APB interface.\n\n - Reset value: 0x0 - [6:6] - read-only - - - INACTIVE - TX_ABRT interrupt is inactive - 0 - - - ACTIVE - TX_ABRT interrupt is active - 1 - - + TXDMAE + Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. + [1:1] + read-write - RD_REQ - This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C master is attempting to read data from DW_apb_i2c. The DW_apb_i2c holds the I2C bus in a wait state (SCL=0) until this interrupt is serviced, which means that the slave has been addressed by a remote master that is asking for data to be transferred. The processor must respond to this interrupt and then write the requested data to the IC_DATA_CMD register. This bit is set to 0 just after the processor reads the IC_CLR_RD_REQ register.\n\n - Reset value: 0x0 - [5:5] - read-only - - - INACTIVE - RD_REQ interrupt is inactive - 0 - - - ACTIVE - RD_REQ interrupt is active - 1 - - + RXDMAE + Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is enabled. + [0:0] + read-write + + + + UARTPERIPHID0 + UARTPeriphID0 Register + 0xFE0 + 0x00000011 + - TX_EMPTY - The behavior of the TX_EMPTY interrupt status differs based on the TX_EMPTY_CTRL selection in the IC_CON register. - When TX_EMPTY_CTRL = 0: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register. - When TX_EMPTY_CTRL = 1: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register and the transmission of the address/data from the internal shift register for the most recently popped command is completed. It is automatically cleared by hardware when the buffer level goes above the threshold. When IC_ENABLE[0] is set to 0, the TX FIFO is flushed and held in reset. There the TX FIFO looks like it has no data within it, so this bit is set to 1, provided there is activity in the master or slave state machines. When there is no longer any activity, then with ic_en=0, this bit is set to 0.\n\n - Reset value: 0x0. - [4:4] + PARTNUMBER0 + These bits read back as 0x11 + [7:0] read-only - - - INACTIVE - TX_EMPTY interrupt is inactive - 0 - - - ACTIVE - TX_EMPTY interrupt is active - 1 - - + + + + UARTPERIPHID1 + UARTPeriphID1 Register + 0xFE4 + 0x00000010 + - TX_OVER - Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register. When the module is disabled, this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared.\n\n - Reset value: 0x0 - [3:3] + DESIGNER0 + These bits read back as 0x1 + [7:4] read-only - - - INACTIVE - TX_OVER interrupt is inactive - 0 - - - ACTIVE - TX_OVER interrupt is active - 1 - - - RX_FULL - Set when the receive buffer reaches or goes above the RX_TL threshold in the IC_RX_TL register. It is automatically cleared by hardware when buffer level goes below the threshold. If the module is disabled (IC_ENABLE[0]=0), the RX FIFO is flushed and held in reset; therefore the RX FIFO is not full. So this bit is cleared once the IC_ENABLE bit 0 is programmed with a 0, regardless of the activity that continues.\n\n - Reset value: 0x0 - [2:2] + PARTNUMBER1 + These bits read back as 0x0 + [3:0] read-only - - - INACTIVE - RX_FULL interrupt is inactive - 0 - - - ACTIVE - RX_FULL interrupt is active - 1 - - + + + + UARTPERIPHID2 + UARTPeriphID2 Register + 0xFE8 + 0x00000034 + - RX_OVER - Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an additional byte is received from an external I2C device. The DW_apb_i2c acknowledges this, but any data bytes received after the FIFO is full are lost. If the module is disabled (IC_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared.\n\n - Note: If bit 9 of the IC_CON register (RX_FIFO_FULL_HLD_CTRL) is programmed to HIGH, then the RX_OVER interrupt never occurs, because the Rx FIFO never overflows.\n\n - Reset value: 0x0 - [1:1] + REVISION + This field depends on the revision of the UART: r1p0 0x0 r1p1 0x1 r1p3 0x2 r1p4 0x2 r1p5 0x3 + [7:4] read-only - - - INACTIVE - RX_OVER interrupt is inactive - 0 - - - ACTIVE - RX_OVER interrupt is active - 1 - - - RX_UNDER - Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register. If the module is disabled (IC_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared.\n\n - Reset value: 0x0 - [0:0] + DESIGNER1 + These bits read back as 0x4 + [3:0] read-only - - - INACTIVE - RX_UNDER interrupt is inactive - 0 - - - ACTIVE - RX_UNDER interrupt is active - 1 - - - IC_RX_TL - I2C Receive FIFO Threshold Register - 0x38 + UARTPERIPHID3 + UARTPeriphID3 Register + 0xFEC 0x00000000 - RX_TL - Receive FIFO Threshold Level.\n\n - Controls the level of entries (or above) that triggers the RX_FULL interrupt (bit 2 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that hardware does not allow this value to be set to a value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 1 entry, and a value of 255 sets the threshold for 256 entries. + CONFIGURATION + These bits read back as 0x00 [7:0] - read-write + read-only - IC_TX_TL - I2C Transmit FIFO Threshold Register - 0x3C - 0x00000000 + UARTPCELLID0 + UARTPCellID0 Register + 0xFF0 + 0x0000000D - TX_TL - Transmit FIFO Threshold Level.\n\n - Controls the level of entries (or below) that trigger the TX_EMPTY interrupt (bit 4 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that it may not be set to value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 0 entries, and a value of 255 sets the threshold for 255 entries. + UARTPCELLID0 + These bits read back as 0x0D [7:0] - read-write + read-only - IC_CLR_INTR - Clear Combined and Individual Interrupt Register - 0x40 - 0x00000000 + UARTPCELLID1 + UARTPCellID1 Register + 0xFF4 + 0x000000F0 - CLR_INTR - Read this register to clear the combined interrupt, all individual interrupts, and the IC_TX_ABRT_SOURCE register. This bit does not clear hardware clearable interrupts but software clearable interrupts. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE.\n\n - Reset value: 0x0 - [0:0] + UARTPCELLID1 + These bits read back as 0xF0 + [7:0] read-only - IC_CLR_RX_UNDER - Clear RX_UNDER Interrupt Register - 0x44 - 0x00000000 + UARTPCELLID2 + UARTPCellID2 Register + 0xFF8 + 0x00000005 - CLR_RX_UNDER - Read this register to clear the RX_UNDER interrupt (bit 0) of the IC_RAW_INTR_STAT register.\n\n - Reset value: 0x0 - [0:0] + UARTPCELLID2 + These bits read back as 0x05 + [7:0] read-only - IC_CLR_RX_OVER - Clear RX_OVER Interrupt Register - 0x48 - 0x00000000 + UARTPCELLID3 + UARTPCellID3 Register + 0xFFC + 0x000000B1 - CLR_RX_OVER - Read this register to clear the RX_OVER interrupt (bit 1) of the IC_RAW_INTR_STAT register.\n\n - Reset value: 0x0 - [0:0] + UARTPCELLID3 + These bits read back as 0xB1 + [7:0] read-only + + + + UART1 + 0x40038000 + + UART1_IRQ + 21 + + + + ROSC + 0x40060000 + + 0x0 + 0x24 + registers + + - IC_CLR_TX_OVER - Clear TX_OVER Interrupt Register - 0x4C - 0x00000000 + CTRL + Ring Oscillator control + 0x0 + 0x00000AA0 - CLR_TX_OVER - Read this register to clear the TX_OVER interrupt (bit 3) of the IC_RAW_INTR_STAT register.\n\n - Reset value: 0x0 - [0:0] - read-only + ENABLE + On power-up this field is initialised to ENABLE + The system clock must be switched to another source before setting this field to DISABLE otherwise the chip will lock up + The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator. + [23:12] + read-write + + + DISABLE + 3358 + + + ENABLE + 4011 + + - - - - IC_CLR_RD_REQ - Clear RD_REQ Interrupt Register - 0x50 - 0x00000000 - - CLR_RD_REQ - Read this register to clear the RD_REQ interrupt (bit 5) of the IC_RAW_INTR_STAT register.\n\n - Reset value: 0x0 - [0:0] - read-only + FREQ_RANGE + Controls the number of delay stages in the ROSC ring + LOW uses stages 0 to 7 + MEDIUM uses stages 2 to 7 + HIGH uses stages 4 to 7 + TOOHIGH uses stages 6 to 7 and should not be used because its frequency exceeds design specifications + The clock output will not glitch when changing the range up one step at a time + The clock output will glitch when changing the range down + Note: the values here are gray coded which is why HIGH comes before TOOHIGH + [11:0] + read-write + + + LOW + 4004 + + + MEDIUM + 4005 + + + HIGH + 4007 + + + TOOHIGH + 4006 + + - IC_CLR_TX_ABRT - Clear TX_ABRT Interrupt Register - 0x54 + FREQA + The FREQA & FREQB registers control the frequency by controlling the drive strength of each stage + The drive strength has 4 levels determined by the number of bits set + Increasing the number of bits set increases the drive strength and increases the oscillation frequency + 0 bits set is the default drive strength + 1 bit set doubles the drive strength + 2 bits set triples drive strength + 3 bits set quadruples drive strength + 0x4 0x00000000 - CLR_TX_ABRT - Read this register to clear the TX_ABRT interrupt (bit 6) of the IC_RAW_INTR_STAT register, and the IC_TX_ABRT_SOURCE register. This also releases the TX FIFO from the flushed/reset state, allowing more writes to the TX FIFO. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE.\n\n - Reset value: 0x0 - [0:0] - read-only + PASSWD + Set to 0x9696 to apply the settings + Any other value in this field will set all drive strengths to 0 + [31:16] + read-write + + + PASS + 38550 + + - - - - IC_CLR_RX_DONE - Clear RX_DONE Interrupt Register - 0x58 - 0x00000000 - - CLR_RX_DONE - Read this register to clear the RX_DONE interrupt (bit 7) of the IC_RAW_INTR_STAT register.\n\n - Reset value: 0x0 - [0:0] - read-only + DS3 + Stage 3 drive strength + [14:12] + read-write - - - - IC_CLR_ACTIVITY - Clear ACTIVITY Interrupt Register - 0x5C - 0x00000000 - - CLR_ACTIVITY - Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore. If the I2C module is still active on the bus, the ACTIVITY interrupt bit continues to be set. It is automatically cleared by hardware if the module is disabled and if there is no further activity on the bus. The value read from this register to get status of the ACTIVITY interrupt (bit 8) of the IC_RAW_INTR_STAT register.\n\n - Reset value: 0x0 - [0:0] - read-only + DS2 + Stage 2 drive strength + [10:8] + read-write - - - - IC_CLR_STOP_DET - Clear STOP_DET Interrupt Register - 0x60 - 0x00000000 - - CLR_STOP_DET - Read this register to clear the STOP_DET interrupt (bit 9) of the IC_RAW_INTR_STAT register.\n\n - Reset value: 0x0 - [0:0] - read-only + DS1 + Stage 1 drive strength + [6:4] + read-write - - - - IC_CLR_START_DET - Clear START_DET Interrupt Register - 0x64 - 0x00000000 - - CLR_START_DET - Read this register to clear the START_DET interrupt (bit 10) of the IC_RAW_INTR_STAT register.\n\n - Reset value: 0x0 - [0:0] - read-only + DS0 + Stage 0 drive strength + [2:0] + read-write - IC_CLR_GEN_CALL - Clear GEN_CALL Interrupt Register - 0x68 + FREQB + For a detailed description see freqa register + 0x8 0x00000000 - CLR_GEN_CALL - Read this register to clear the GEN_CALL interrupt (bit 11) of IC_RAW_INTR_STAT register.\n\n - Reset value: 0x0 - [0:0] - read-only + PASSWD + Set to 0x9696 to apply the settings + Any other value in this field will set all drive strengths to 0 + [31:16] + read-write + + + PASS + 38550 + + + + + DS7 + Stage 7 drive strength + [14:12] + read-write + + + DS6 + Stage 6 drive strength + [10:8] + read-write + + + DS5 + Stage 5 drive strength + [6:4] + read-write + + + DS4 + Stage 4 drive strength + [2:0] + read-write - IC_ENABLE - I2C Enable Register - 0x6C - 0x00000000 + DORMANT + Ring Oscillator pause control + 0xC + 0x00000000 - TX_CMD_BLOCK - In Master mode: - 1'b1: Blocks the transmission of data on I2C bus even if Tx FIFO has data to transmit. - 1'b0: The transmission of data starts on I2C bus automatically, as soon as the first data is available in the Tx FIFO. Note: To block the execution of Master commands, set the TX_CMD_BLOCK bit only when Tx FIFO is empty (IC_STATUS[2]==1) and Master is in Idle state (IC_STATUS[5] == 0). Any further commands put in the Tx FIFO are not executed until TX_CMD_BLOCK bit is unset. Reset value: IC_TX_CMD_BLOCK_DEFAULT - [2:2] + DORMANT + This is used to save power by pausing the ROSC + On power-up this field is initialised to WAKE + An invalid write will also select WAKE + Warning: setup the irq before selecting dormant mode + [31:0] read-write - NOT_BLOCKED - Tx Command execution not blocked - 0 + dormant + 1668246881 - BLOCKED - Tx Command execution blocked - 1 - - - - - ABORT - When set, the controller initiates the transfer abort. - 0: ABORT not initiated or ABORT done - 1: ABORT operation in progress The software can abort the I2C transfer in master mode by setting this bit. The software can set this bit only when ENABLE is already set; otherwise, the controller ignores any write to ABORT bit. The software cannot clear the ABORT bit once set. In response to an ABORT, the controller issues a STOP and flushes the Tx FIFO after completing the current transfer, then sets the TX_ABORT interrupt after the abort operation. The ABORT bit is cleared automatically after the abort operation.\n\n - For a detailed description on how to abort I2C transfers, refer to 'Aborting I2C Transfers'.\n\n - Reset value: 0x0 - [1:1] - read-write - - - DISABLE - ABORT operation not in progress - 0 - - - ENABLED - ABORT operation in progress - 1 + WAKE + 2002873189 + + + + DIV + Controls the output divider + 0x10 + 0x00000000 + - ENABLE - Controls whether the DW_apb_i2c is enabled. - 0: Disables DW_apb_i2c (TX and RX FIFOs are held in an erased state) - 1: Enables DW_apb_i2c Software can disable DW_apb_i2c while it is active. However, it is important that care be taken to ensure that DW_apb_i2c is disabled properly. A recommended procedure is described in 'Disabling DW_apb_i2c'.\n\n - When DW_apb_i2c is disabled, the following occurs: - The TX FIFO and RX FIFO get flushed. - Status bits in the IC_INTR_STAT register are still active until DW_apb_i2c goes into IDLE state. If the module is transmitting, it stops as well as deletes the contents of the transmit buffer after the current transfer is complete. If the module is receiving, the DW_apb_i2c stops the current transfer at the end of the current byte and does not acknowledge the transfer.\n\n - In systems with asynchronous pclk and ic_clk when IC_CLK_TYPE parameter set to asynchronous (1), there is a two ic_clk delay when enabling or disabling the DW_apb_i2c. For a detailed description on how to disable DW_apb_i2c, refer to 'Disabling DW_apb_i2c'\n\n - Reset value: 0x0 - [0:0] + DIV + set to 0xaa0 + div where + div = 0 divides by 32 + div = 1-31 divides by div + any other value sets div=31 + this register resets to div=16 + [11:0] read-write - DISABLED - I2C is disabled - 0 - - - ENABLED - I2C is enabled - 1 + PASS + 2720 - IC_STATUS - I2C Status Register\n\n - This is a read-only register used to indicate the current transfer status and FIFO status. The status register may be read at any time. None of the bits in this register request an interrupt.\n\n - When the I2C is disabled by writing 0 in bit 0 of the IC_ENABLE register: - Bits 1 and 2 are set to 1 - Bits 3 and 10 are set to 0 When the master or slave state machines goes to idle and ic_en=0: - Bits 5 and 6 are set to 0 - 0x70 - 0x00000006 + PHASE + Controls the phase shifted output + 0x14 + 0x00000008 - SLV_ACTIVITY - Slave FSM Activity Status. When the Slave Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Slave FSM is in IDLE state so the Slave part of DW_apb_i2c is not Active - 1: Slave FSM is not in IDLE state so the Slave part of DW_apb_i2c is Active Reset value: 0x0 - [6:6] - read-only - - - IDLE - Slave is idle - 0 - - - ACTIVE - Slave not idle - 1 - - - - - MST_ACTIVITY - Master FSM Activity Status. When the Master Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Master FSM is in IDLE state so the Master part of DW_apb_i2c is not Active - 1: Master FSM is not in IDLE state so the Master part of DW_apb_i2c is Active Note: IC_STATUS[0]-that is, ACTIVITY bit-is the OR of SLV_ACTIVITY and MST_ACTIVITY bits.\n\n - Reset value: 0x0 - [5:5] - read-only - - - IDLE - Master is idle - 0 - - - ACTIVE - Master not idle - 1 - - - - - RFF - Receive FIFO Completely Full. When the receive FIFO is completely full, this bit is set. When the receive FIFO contains one or more empty location, this bit is cleared. - 0: Receive FIFO is not full - 1: Receive FIFO is full Reset value: 0x0 - [4:4] - read-only - - - NOT_FULL - Rx FIFO not full - 0 - - - FULL - Rx FIFO is full - 1 - - + PASSWD + set to 0xaa + any other value enables the output with shift=0 + [11:4] + read-write - RFNE - Receive FIFO Not Empty. This bit is set when the receive FIFO contains one or more entries; it is cleared when the receive FIFO is empty. - 0: Receive FIFO is empty - 1: Receive FIFO is not empty Reset value: 0x0 + ENABLE + enable the phase-shifted output + this can be changed on-the-fly [3:3] - read-only - - - EMPTY - Rx FIFO is empty - 0 - - - NOT_EMPTY - Rx FIFO not empty - 1 - - + read-write - TFE - Transmit FIFO Completely Empty. When the transmit FIFO is completely empty, this bit is set. When it contains one or more valid entries, this bit is cleared. This bit field does not request an interrupt. - 0: Transmit FIFO is not empty - 1: Transmit FIFO is empty Reset value: 0x1 + FLIP + invert the phase-shifted output + this is ignored when div=1 [2:2] - read-only - - - NON_EMPTY - Tx FIFO not empty - 0 - - - EMPTY - Tx FIFO is empty - 1 - - - - - TFNF - Transmit FIFO Not Full. Set when the transmit FIFO contains one or more empty locations, and is cleared when the FIFO is full. - 0: Transmit FIFO is full - 1: Transmit FIFO is not full Reset value: 0x1 - [1:1] - read-only - - - FULL - Tx FIFO is full - 0 - - - NOT_FULL - Tx FIFO not full - 1 - - + read-write - ACTIVITY - I2C Activity Status. Reset value: 0x0 - [0:0] - read-only - - - INACTIVE - I2C is idle - 0 - - - ACTIVE - I2C is active - 1 - - + SHIFT + phase shift the phase-shifted output by SHIFT input clocks + this can be changed on-the-fly + must be set to 0 before setting div=1 + [1:0] + read-write - IC_TXFLR - I2C Transmit FIFO Level Register This register contains the number of valid data entries in the transmit FIFO buffer. It is cleared whenever: - The I2C is disabled - There is a transmit abort - that is, TX_ABRT bit is set in the IC_RAW_INTR_STAT register - The slave bulk transmit mode is aborted The register increments whenever data is placed into the transmit FIFO and decrements when data is taken from the transmit FIFO. - 0x74 - 0x00000000 + RANDOMBIT + This just reads the state of the oscillator output so randomness is compromised if the ring oscillator is stopped or run at a harmonic of the bus frequency + 0x1C + 0x00000001 - TXFLR - Transmit FIFO Level. Contains the number of valid data entries in the transmit FIFO.\n\n - Reset value: 0x0 - [4:0] + RANDOMBIT + [0:0] read-only - IC_RXFLR - I2C Receive FIFO Level Register This register contains the number of valid data entries in the receive FIFO buffer. It is cleared whenever: - The I2C is disabled - Whenever there is a transmit abort caused by any of the events tracked in IC_TX_ABRT_SOURCE The register increments whenever data is placed into the receive FIFO and decrements when data is taken from the receive FIFO. - 0x78 + STATUS + Ring Oscillator Status + 0x18 0x00000000 - RXFLR - Receive FIFO Level. Contains the number of valid data entries in the receive FIFO.\n\n - Reset value: 0x0 - [4:0] + STABLE + Oscillator is running and stable + 31 + 1 + read-only + + + DIV_RUNNING + post-divider is running + this resets to 0 but transitions to 1 during chip startup + 16 + 1 + read-only + + + ENABLED + Oscillator is enabled but not necessarily running and stable + this resets to 0 but transitions to 1 during chip startup + 12 + 1 read-only + + + + WATCHDOG + 0x40058000 + + 0x0 + 0x30 + registers + + - IC_SDA_HOLD - I2C SDA Hold Time Length Register\n\n - The bits [15:0] of this register are used to control the hold time of SDA during transmit in both slave and master mode (after SCL goes from HIGH to LOW).\n\n - The bits [23:16] of this register are used to extend the SDA transition (if any) whenever SCL is HIGH in the receiver in either master or slave mode.\n\n - Writes to this register succeed only when IC_ENABLE[0]=0.\n\n - The values in this register are in units of ic_clk period. The value programmed in IC_SDA_TX_HOLD must be greater than the minimum hold time in each mode (one cycle in master mode, seven cycles in slave mode) for the value to be implemented.\n\n - The programmed SDA hold time during transmit (IC_SDA_TX_HOLD) cannot exceed at any time the duration of the low part of scl. Therefore the programmed value cannot be larger than N_SCL_LOW-2, where N_SCL_LOW is the duration of the low part of the scl period measured in ic_clk cycles. - 0x7C - 0x00000001 + CTRL + Watchdog control + The rst_wdsel register determines which subsystems are reset when the watchdog is triggered. + The watchdog can be triggered in software. + 0x0 + 0x07000000 - IC_SDA_RX_HOLD - Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a receiver.\n\n - Reset value: IC_DEFAULT_SDA_HOLD[23:16]. - [23:16] + TRIGGER + Trigger a watchdog reset + [31:31] + write-only + + + ENABLE + When not enabled the watchdog timer is paused + [30:30] read-write - IC_SDA_TX_HOLD - Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a transmitter.\n\n - Reset value: IC_DEFAULT_SDA_HOLD[15:0]. - [15:0] + PAUSE_DBG1 + Pause the watchdog timer when processor 1 is in debug mode + [26:26] read-write - - - - IC_TX_ABRT_SOURCE - I2C Transmit Abort Source Register\n\n - This register has 32 bits that indicate the source of the TX_ABRT bit. Except for Bit 9, this register is cleared whenever the IC_CLR_TX_ABRT register or the IC_CLR_INTR register is read. To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; RESTART must be enabled (IC_CON[5]=1), the SPECIAL bit must be cleared (IC_TAR[11]), or the GC_OR_START bit must be cleared (IC_TAR[10]).\n\n - Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, Bit 9 clears for one cycle and is then re-asserted. - 0x80 - 0x00000000 - - TX_FLUSH_CNT - This field indicates the number of Tx FIFO Data Commands which are flushed due to TX_ABRT interrupt. It is cleared whenever I2C is disabled.\n\n - Reset value: 0x0\n\n - Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter - [31:23] - read-only + PAUSE_DBG0 + Pause the watchdog timer when processor 0 is in debug mode + [25:25] + read-write - ABRT_USER_ABRT - This is a master-mode-only bit. Master has detected the transfer abort (IC_ENABLE[1])\n\n - Reset value: 0x0\n\n - Role of DW_apb_i2c: Master-Transmitter - [16:16] - read-only - - - ABRT_USER_ABRT_VOID - Transfer abort detected by master- scenario not present - 0 - - - ABRT_USER_ABRT_GENERATED - Transfer abort detected by master - 1 - - + PAUSE_JTAG + Pause the watchdog timer when JTAG is accessing the bus fabric + [24:24] + read-write - ABRT_SLVRD_INTX - 1: When the processor side responds to a slave mode request for data to be transmitted to a remote master and user writes a 1 in CMD (bit 8) of IC_DATA_CMD register.\n\n - Reset value: 0x0\n\n - Role of DW_apb_i2c: Slave-Transmitter - [15:15] + TIME + Indicates the number of ticks / 2 (see errata RP2040-E1) before a watchdog reset will be triggered + [23:0] read-only - - - ABRT_SLVRD_INTX_VOID - Slave trying to transmit to remote master in read mode- scenario not present - 0 - - - ABRT_SLVRD_INTX_GENERATED - Slave trying to transmit to remote master in read mode - 1 - - + + + + LOAD + Load the watchdog timer. The maximum setting is 0xffffff which corresponds to 0xffffff / 2 ticks before triggering a watchdog reset (see errata RP2040-E1). + 0x4 + 0x00000000 + - ABRT_SLV_ARBLOST - This field indicates that a Slave has lost the bus while transmitting data to a remote master. IC_TX_ABRT_SOURCE[12] is set at the same time. Note: Even though the slave never 'owns' the bus, something could go wrong on the bus. This is a fail safe check. For instance, during a data transmission at the low-to-high transition of SCL, if what is on the data bus is not what is supposed to be transmitted, then DW_apb_i2c no longer own the bus.\n\n - Reset value: 0x0\n\n - Role of DW_apb_i2c: Slave-Transmitter - [14:14] - read-only - - - ABRT_SLV_ARBLOST_VOID - Slave lost arbitration to remote master- scenario not present - 0 - - - ABRT_SLV_ARBLOST_GENERATED - Slave lost arbitration to remote master - 1 - - + LOAD + [23:0] + write-only + + + + REASON + Logs the reason for the last reset. Both bits are zero for the case of a hardware reset. + 0x8 + 0x00000000 + - ABRT_SLVFLUSH_TXFIFO - This field specifies that the Slave has received a read command and some data exists in the TX FIFO, so the slave issues a TX_ABRT interrupt to flush old data in TX FIFO.\n\n - Reset value: 0x0\n\n - Role of DW_apb_i2c: Slave-Transmitter - [13:13] + FORCE + [1:1] read-only - - - ABRT_SLVFLUSH_TXFIFO_VOID - Slave flushes existing data in TX-FIFO upon getting read command- scenario not present - 0 - - - ABRT_SLVFLUSH_TXFIFO_GENERATED - Slave flushes existing data in TX-FIFO upon getting read command - 1 - - - ARB_LOST - This field specifies that the Master has lost arbitration, or if IC_TX_ABRT_SOURCE[14] is also set, then the slave transmitter has lost arbitration.\n\n - Reset value: 0x0\n\n - Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter - [12:12] + TIMER + [0:0] read-only - - - ABRT_LOST_VOID - Master or Slave-Transmitter lost arbitration- scenario not present - 0 - - - ABRT_LOST_GENERATED - Master or Slave-Transmitter lost arbitration - 1 - - + + + + SCRATCH0 + Scratch register. Information persists through soft reset of the chip. + 0xC + 0x00000000 + - ABRT_MASTER_DIS - This field indicates that the User tries to initiate a Master operation with the Master mode disabled.\n\n - Reset value: 0x0\n\n - Role of DW_apb_i2c: Master-Transmitter or Master-Receiver - [11:11] - read-only - - - ABRT_MASTER_DIS_VOID - User initiating master operation when MASTER disabled- scenario not present - 0 - - - ABRT_MASTER_DIS_GENERATED - User initiating master operation when MASTER disabled - 1 - - + SCRATCH0 + [31:0] + read-write + + + + SCRATCH1 + Scratch register. Information persists through soft reset of the chip. + 0x10 + 0x00000000 + - ABRT_10B_RD_NORSTRT - This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the master sends a read command in 10-bit addressing mode.\n\n - Reset value: 0x0\n\n - Role of DW_apb_i2c: Master-Receiver - [10:10] - read-only - - - ABRT_10B_RD_VOID - Master not trying to read in 10Bit addressing mode when RESTART disabled - 0 - - - ABRT_10B_RD_GENERATED - Master trying to read in 10Bit addressing mode when RESTART disabled - 1 - - + SCRATCH1 + [31:0] + read-write + + + + SCRATCH2 + Scratch register. Information persists through soft reset of the chip. + 0x14 + 0x00000000 + - ABRT_SBYTE_NORSTRT - To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; restart must be enabled (IC_CON[5]=1), the SPECIAL bit must be cleared (IC_TAR[11]), or the GC_OR_START bit must be cleared (IC_TAR[10]). Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, bit 9 clears for one cycle and then gets reasserted. When this field is set to 1, the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to send a START Byte.\n\n - Reset value: 0x0\n\n - Role of DW_apb_i2c: Master - [9:9] - read-only - - - ABRT_SBYTE_NORSTRT_VOID - User trying to send START byte when RESTART disabled- scenario not present - 0 - - - ABRT_SBYTE_NORSTRT_GENERATED - User trying to send START byte when RESTART disabled - 1 - - + SCRATCH2 + [31:0] + read-write + + + + SCRATCH3 + Scratch register. Information persists through soft reset of the chip. + 0x18 + 0x00000000 + - ABRT_HS_NORSTRT - This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to use the master to transfer data in High Speed mode.\n\n - Reset value: 0x0\n\n - Role of DW_apb_i2c: Master-Transmitter or Master-Receiver - [8:8] - read-only - - - ABRT_HS_NORSTRT_VOID - User trying to switch Master to HS mode when RESTART disabled- scenario not present - 0 - - - ABRT_HS_NORSTRT_GENERATED - User trying to switch Master to HS mode when RESTART disabled - 1 - - + SCRATCH3 + [31:0] + read-write + + + + SCRATCH4 + Scratch register. Information persists through soft reset of the chip. + 0x1C + 0x00000000 + - ABRT_SBYTE_ACKDET - This field indicates that the Master has sent a START Byte and the START Byte was acknowledged (wrong behavior).\n\n - Reset value: 0x0\n\n - Role of DW_apb_i2c: Master - [7:7] - read-only - - - ABRT_SBYTE_ACKDET_VOID - ACK detected for START byte- scenario not present - 0 - - - ABRT_SBYTE_ACKDET_GENERATED - ACK detected for START byte - 1 - - + SCRATCH4 + [31:0] + read-write + + + + SCRATCH5 + Scratch register. Information persists through soft reset of the chip. + 0x20 + 0x00000000 + - ABRT_HS_ACKDET - This field indicates that the Master is in High Speed mode and the High Speed Master code was acknowledged (wrong behavior).\n\n - Reset value: 0x0\n\n - Role of DW_apb_i2c: Master - [6:6] - read-only - - - ABRT_HS_ACK_VOID - HS Master code ACKed in HS Mode- scenario not present - 0 - - - ABRT_HS_ACK_GENERATED - HS Master code ACKed in HS Mode - 1 - - - - - ABRT_GCALL_READ - This field indicates that DW_apb_i2c in the master mode has sent a General Call but the user programmed the byte following the General Call to be a read from the bus (IC_DATA_CMD[9] is set to 1).\n\n - Reset value: 0x0\n\n - Role of DW_apb_i2c: Master-Transmitter - [5:5] - read-only - - - ABRT_GCALL_READ_VOID - GCALL is followed by read from bus-scenario not present - 0 - - - ABRT_GCALL_READ_GENERATED - GCALL is followed by read from bus - 1 - - - - - ABRT_GCALL_NOACK - This field indicates that DW_apb_i2c in master mode has sent a General Call and no slave on the bus acknowledged the General Call.\n\n - Reset value: 0x0\n\n - Role of DW_apb_i2c: Master-Transmitter - [4:4] - read-only - - - ABRT_GCALL_NOACK_VOID - GCALL not ACKed by any slave-scenario not present - 0 - - - ABRT_GCALL_NOACK_GENERATED - GCALL not ACKed by any slave - 1 - - - - - ABRT_TXDATA_NOACK - This field indicates the master-mode only bit. When the master receives an acknowledgement for the address, but when it sends data byte(s) following the address, it did not receive an acknowledge from the remote slave(s).\n\n - Reset value: 0x0\n\n - Role of DW_apb_i2c: Master-Transmitter - [3:3] - read-only - - - ABRT_TXDATA_NOACK_VOID - Transmitted data non-ACKed by addressed slave-scenario not present - 0 - - - ABRT_TXDATA_NOACK_GENERATED - Transmitted data not ACKed by addressed slave - 1 - - - - - ABRT_10ADDR2_NOACK - This field indicates that the Master is in 10-bit address mode and that the second address byte of the 10-bit address was not acknowledged by any slave.\n\n - Reset value: 0x0\n\n - Role of DW_apb_i2c: Master-Transmitter or Master-Receiver - [2:2] - read-only - - - INACTIVE - This abort is not generated - 0 - - - ACTIVE - Byte 2 of 10Bit Address not ACKed by any slave - 1 - - - - - ABRT_10ADDR1_NOACK - This field indicates that the Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave.\n\n - Reset value: 0x0\n\n - Role of DW_apb_i2c: Master-Transmitter or Master-Receiver - [1:1] - read-only - - - INACTIVE - This abort is not generated - 0 - - - ACTIVE - Byte 1 of 10Bit Address not ACKed by any slave - 1 - - - - - ABRT_7B_ADDR_NOACK - This field indicates that the Master is in 7-bit addressing mode and the address sent was not acknowledged by any slave.\n\n - Reset value: 0x0\n\n - Role of DW_apb_i2c: Master-Transmitter or Master-Receiver - [0:0] - read-only - - - INACTIVE - This abort is not generated - 0 - - - ACTIVE - This abort is generated because of NOACK for 7-bit address - 1 - - + SCRATCH5 + [31:0] + read-write - IC_SLV_DATA_NACK_ONLY - Generate Slave Data NACK Register\n\n - The register is used to generate a NACK for the data part of a transfer when DW_apb_i2c is acting as a slave-receiver. This register only exists when the IC_SLV_DATA_NACK_ONLY parameter is set to 1. When this parameter disabled, this register does not exist and writing to the register's address has no effect.\n\n - A write can occur on this register if both of the following conditions are met: - DW_apb_i2c is disabled (IC_ENABLE[0] = 0) - Slave part is inactive (IC_STATUS[6] = 0) Note: The IC_STATUS[6] is a register read-back location for the internal slv_activity signal; the user should poll this before writing the ic_slv_data_nack_only bit. - 0x84 + SCRATCH6 + Scratch register. Information persists through soft reset of the chip. + 0x24 0x00000000 - NACK - Generate NACK. This NACK generation only occurs when DW_apb_i2c is a slave-receiver. If this register is set to a value of 1, it can only generate a NACK after a data byte is received; hence, the data transfer is aborted and the data received is not pushed to the receive buffer.\n\n - When the register is set to a value of 0, it generates NACK/ACK, depending on normal criteria. - 1: generate NACK after data byte received - 0: generate NACK/ACK normally Reset value: 0x0 - [0:0] + SCRATCH6 + [31:0] read-write - - - DISABLED - Slave receiver generates NACK normally - 0 - - - ENABLED - Slave receiver generates NACK upon data reception only - 1 - - - IC_DMA_CR - DMA Control Register\n\n - The register is used to enable the DMA Controller interface operation. There is a separate bit for transmit and receive. This can be programmed regardless of the state of IC_ENABLE. - 0x88 + SCRATCH7 + Scratch register. Information persists through soft reset of the chip. + 0x28 0x00000000 - TDMAE - Transmit DMA Enable. This bit enables/disables the transmit FIFO DMA channel. Reset value: 0x0 - [1:1] - read-write - - - DISABLED - transmit FIFO DMA channel disabled - 0 - - - ENABLED - Transmit FIFO DMA channel enabled - 1 - - - - - RDMAE - Receive DMA Enable. This bit enables/disables the receive FIFO DMA channel. Reset value: 0x0 - [0:0] + SCRATCH7 + [31:0] read-write - - - DISABLED - Receive FIFO DMA channel disabled - 0 - - - ENABLED - Receive FIFO DMA channel enabled - 1 - - - IC_DMA_TDLR - DMA Transmit Data Level Register - 0x8C - 0x00000000 + TICK + Controls the tick generator + 0x2C + 0x00000200 - DMATDL - Transmit Data Level. This bit field controls the level at which a DMA request is made by the transmit logic. It is equal to the watermark level; that is, the dma_tx_req signal is generated when the number of valid data entries in the transmit FIFO is equal to or below this field value, and TDMAE = 1.\n\n - Reset value: 0x0 - [3:0] - read-write + COUNT + Count down timer: the remaining number clk_tick cycles before the next tick is generated. + [19:11] + read-only - - - - IC_DMA_RDLR - I2C Receive Data Level Register - 0x90 - 0x00000000 - - DMARDL - Receive Data Level. This bit field controls the level at which a DMA request is made by the receive logic. The watermark level = DMARDL+1; that is, dma_rx_req is generated when the number of valid data entries in the receive FIFO is equal to or more than this field value + 1, and RDMAE =1. For instance, when DMARDL is 0, then dma_rx_req is asserted when 1 or more data entries are present in the receive FIFO.\n\n - Reset value: 0x0 - [3:0] - read-write + RUNNING + Is the tick generator running? + [10:10] + read-only - - - - IC_SDA_SETUP - I2C SDA Setup Register\n\n - This register controls the amount of time delay (in terms of number of ic_clk clock periods) introduced in the rising edge of SCL - relative to SDA changing - when DW_apb_i2c services a read request in a slave-transmitter operation. The relevant I2C requirement is tSU:DAT (note 4) as detailed in the I2C Bus Specification. This register must be programmed with a value equal to or greater than 2.\n\n - Writes to this register succeed only when IC_ENABLE[0] = 0.\n\n - Note: The length of setup time is calculated using [(IC_SDA_SETUP - 1) * (ic_clk_period)], so if the user requires 10 ic_clk periods of setup time, they should program a value of 11. The IC_SDA_SETUP register is only used by the DW_apb_i2c when operating as a slave transmitter. - 0x94 - 0x00000064 - - SDA_SETUP - SDA Setup. It is recommended that if the required delay is 1000ns, then for an ic_clk frequency of 10 MHz, IC_SDA_SETUP should be programmed to a value of 11. IC_SDA_SETUP must be programmed with a minimum value of 2. - [7:0] + ENABLE + start / stop tick generation + [9:9] read-write - - - - IC_ACK_GENERAL_CALL - I2C ACK General Call Register\n\n - The register controls whether DW_apb_i2c responds with a ACK or NACK when it receives an I2C General Call address.\n\n - This register is applicable only when the DW_apb_i2c is in slave mode. - 0x98 - 0x00000001 - - ACK_GEN_CALL - ACK General Call. When set to 1, DW_apb_i2c responds with a ACK (by asserting ic_data_oe) when it receives a General Call. Otherwise, DW_apb_i2c responds with a NACK (by negating ic_data_oe). - [0:0] + CYCLES + Total number of clk_tick cycles before the next tick. + [8:0] read-write - - - DISABLED - Generate NACK for a General Call - 0 - - - ENABLED - Generate ACK for a General Call - 1 - - - - - - - IC_ENABLE_STATUS - I2C Enable Status Register\n\n - The register is used to report the DW_apb_i2c hardware status when the IC_ENABLE[0] register is set from 1 to 0; that is, when DW_apb_i2c is disabled.\n\n - If IC_ENABLE[0] has been set to 1, bits 2:1 are forced to 0, and bit 0 is forced to 1.\n\n - If IC_ENABLE[0] has been set to 0, bits 2:1 is only be valid as soon as bit 0 is read as '0'.\n\n - Note: When IC_ENABLE[0] has been set to 0, a delay occurs for bit 0 to be read as 0 because disabling the DW_apb_i2c depends on I2C bus activities. - 0x9C - 0x00000000 - - - SLV_RX_DATA_LOST - Slave Received Data Lost. This bit indicates if a Slave-Receiver operation has been aborted with at least one data byte received from an I2C transfer due to the setting bit 0 of IC_ENABLE from 1 to 0. When read as 1, DW_apb_i2c is deemed to have been actively engaged in an aborted I2C transfer (with matching address) and the data phase of the I2C transfer has been entered, even though a data byte has been responded with a NACK.\n\n - Note: If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE[0] has been set to 0, then this bit is also set to 1.\n\n - When read as 0, DW_apb_i2c is deemed to have been disabled without being actively involved in the data phase of a Slave-Receiver transfer.\n\n - Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0.\n\n - Reset value: 0x0 - [2:2] - read-only - - - INACTIVE - Slave RX Data is not lost - 0 - - - ACTIVE - Slave RX Data is lost - 1 - - - - - SLV_DISABLED_WHILE_BUSY - Slave Disabled While Busy (Transmit, Receive). This bit indicates if a potential or active Slave operation has been aborted due to the setting bit 0 of the IC_ENABLE register from 1 to 0. This bit is set when the CPU writes a 0 to the IC_ENABLE register while:\n\n - (a) DW_apb_i2c is receiving the address byte of the Slave-Transmitter operation from a remote master;\n\n - OR,\n\n - (b) address and data bytes of the Slave-Receiver operation from a remote master.\n\n - When read as 1, DW_apb_i2c is deemed to have forced a NACK during any part of an I2C transfer, irrespective of whether the I2C address matches the slave address set in DW_apb_i2c (IC_SAR register) OR if the transfer is completed before IC_ENABLE is set to 0 but has not taken effect.\n\n - Note: If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE[0] has been set to 0, then this bit will also be set to 1.\n\n - When read as 0, DW_apb_i2c is deemed to have been disabled when there is master activity, or when the I2C bus is idle.\n\n - Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0.\n\n - Reset value: 0x0 - [1:1] - read-only - - - INACTIVE - Slave is disabled when it is idle - 0 - - - ACTIVE - Slave is disabled when it is active - 1 - - - - - IC_EN - ic_en Status. This bit always reflects the value driven on the output port ic_en. - When read as 1, DW_apb_i2c is deemed to be in an enabled state. - When read as 0, DW_apb_i2c is deemed completely inactive. Note: The CPU can safely read this bit anytime. When this bit is read as 0, the CPU can safely read SLV_RX_DATA_LOST (bit 2) and SLV_DISABLED_WHILE_BUSY (bit 1).\n\n - Reset value: 0x0 - [0:0] - read-only - - - DISABLED - I2C disabled - 0 - - - ENABLED - I2C enabled - 1 - - - - - - - IC_FS_SPKLEN - I2C SS, FS or FM+ spike suppression limit\n\n - This register is used to store the duration, measured in ic_clk cycles, of the longest spike that is filtered out by the spike suppression logic when the component is operating in SS, FS or FM+ modes. The relevant I2C requirement is tSP (table 4) as detailed in the I2C Bus Specification. This register must be programmed with a minimum value of 1. - 0xA0 - 0x00000007 - - - IC_FS_SPKLEN - This register must be set before any I2C bus transaction can take place to ensure stable operation. This register sets the duration, measured in ic_clk cycles, of the longest spike in the SCL or SDA lines that will be filtered out by the spike suppression logic. This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. The minimum valid value is 1; hardware prevents values less than this being written, and if attempted results in 1 being set. or more information, refer to 'Spike Suppression'. - [7:0] - read-write - - - - - IC_CLR_RESTART_DET - Clear RESTART_DET Interrupt Register - 0xA8 - 0x00000000 - - - CLR_RESTART_DET - Read this register to clear the RESTART_DET interrupt (bit 12) of IC_RAW_INTR_STAT register.\n\n - Reset value: 0x0 - [0:0] - read-only - - - - - IC_COMP_PARAM_1 - Component Parameter Register 1\n\n - Note This register is not implemented and therefore reads as 0. If it was implemented it would be a constant read-only register that contains encoded information about the component's parameter settings. Fields shown below are the settings for those parameters - 0xF4 - 0x00000000 - - - TX_BUFFER_DEPTH - TX Buffer Depth = 16 - [23:16] - read-only - - - RX_BUFFER_DEPTH - RX Buffer Depth = 16 - [15:8] - read-only - - - ADD_ENCODED_PARAMS - Encoded parameters not visible - [7:7] - read-only - - - HAS_DMA - DMA handshaking signals are enabled - [6:6] - read-only - - - INTR_IO - COMBINED Interrupt outputs - [5:5] - read-only - - - HC_COUNT_VALUES - Programmable count values for each mode. - [4:4] - read-only - - - MAX_SPEED_MODE - MAX SPEED MODE = FAST MODE - [3:2] - read-only - - - APB_DATA_WIDTH - APB data bus width is 32 bits - [1:0] - read-only - - - - - IC_COMP_VERSION - I2C Component Version Register - 0xF8 - 0x3230312A - - - IC_COMP_VERSION - [31:0] - read-only - - - - - IC_COMP_TYPE - I2C Component Type Register - 0xFC - 0x44570140 - - - IC_COMP_TYPE - Designware Component Type number = 0x44_57_01_40. This assigned unique hex value is constant and is derived from the two ASCII letters 'DW' followed by a 16-bit unsigned number. - [31:0] - read-only - - I2C1 - 0x40048000 - - I2C1_IRQ - 24 - - - ADC - 2 - Control and data interface to SAR ADC - 0x4004C000 - 0x20 + DMA + DMA with separate read and write masters + 0x50000000 0x0 - 0x1000 + 0xAC8 registers - ADC_IRQ_FIFO - 22 + DMA_IRQ_0 + 11 + + + DMA_IRQ_1 + 12 - - CS - ADC Control and Status - 0x0 - 0x00000000 - - - RROBIN - Round-robin sampling. 1 bit per channel. Set all bits to 0 to disable.\n - Otherwise, the ADC will cycle through each enabled channel in a round-robin fashion.\n - The first channel to be sampled will be the one currently indicated by AINSEL.\n - AINSEL will be updated after each conversion with the newly-selected channel. - [20:16] - read-write - - - AINSEL - Select analog mux input. Updated automatically in round-robin mode. - [14:12] - read-write - - - ERR_STICKY - Some past ADC conversion encountered an error. Write 1 to clear. - [10:10] - read-write - oneToClear - - - ERR - The most recent ADC conversion encountered an error; result is undefined or noisy. - [9:9] - read-only - - - READY - 1 if the ADC is ready to start a new conversion. Implies any previous conversion has completed.\n - 0 whilst conversion in progress. - [8:8] - read-only - - - START_MANY - Continuously perform conversions whilst this bit is 1. A new conversion will start immediately after the previous finishes. - [3:3] - read-write - - - START_ONCE - Start a single conversion. Self-clearing. Ignored if start_many is asserted. - [2:2] - read-write - clear - - - TS_EN - Power on temperature sensor. 1 - enabled. 0 - disabled. - [1:1] - read-write - - - EN - Power on ADC and enable its clock.\n - 1 - enabled. 0 - disabled. - [0:0] - read-write - - - - - RESULT - Result of most recent ADC conversion - 0x4 - 0x00000000 - - - RESULT - [11:0] - read-only - - - - - FCS - FIFO control and status - 0x8 - 0x00000000 - - - THRESH - DREQ/IRQ asserted when level >= threshold - [27:24] - read-write - - - LEVEL - The number of conversion results currently waiting in the FIFO - [19:16] - read-only - - - OVER - 1 if the FIFO has been overflowed. Write 1 to clear. - [11:11] - read-write - oneToClear - - - UNDER - 1 if the FIFO has been underflowed. Write 1 to clear. - [10:10] - read-write - oneToClear - - - FULL - [9:9] - read-only - - - EMPTY - [8:8] - read-only - - - DREQ_EN - If 1: assert DMA requests when FIFO contains data - [3:3] - read-write - - - ERR - If 1: conversion error bit appears in the FIFO alongside the result - [2:2] - read-write - - - SHIFT - If 1: FIFO results are right-shifted to be one byte in size. Enables DMA to byte buffers. - [1:1] - read-write - - - EN - If 1: write result to the FIFO after each conversion. - [0:0] - read-write - - - - - FIFO - Conversion result FIFO - 0xC - 0x00000000 - - - ERR - 1 if this particular sample experienced a conversion error. Remains in the same location if the sample is shifted. - [15:15] - read-only - - - VAL - [11:0] - read-only - - - - - DIV - Clock divider. If non-zero, CS_START_MANY will start conversions\n - at regular intervals rather than back-to-back.\n - The divider is reset when either of these fields are written.\n - Total period is 1 + INT + FRAC / 256 - 0x10 - 0x00000000 - - - INT - Integer part of clock divisor. - [23:8] - read-write - - - FRAC - Fractional part of clock divisor. First-order delta-sigma. - [7:0] - read-write - - - - - INTR - Raw Interrupts - 0x14 - 0x00000000 - - - FIFO - Triggered when the sample FIFO reaches a certain level.\n - This level can be programmed via the FCS_THRESH field. - [0:0] - read-only - - - - - INTE - Interrupt Enable - 0x18 - 0x00000000 - - - FIFO - Triggered when the sample FIFO reaches a certain level.\n - This level can be programmed via the FCS_THRESH field. - [0:0] - read-write - - - - - INTF - Interrupt Force - 0x1C - 0x00000000 - - - FIFO - Triggered when the sample FIFO reaches a certain level.\n - This level can be programmed via the FCS_THRESH field. - [0:0] - read-write - - - - - INTS - Interrupt status after masking & forcing - 0x20 - 0x00000000 - - - FIFO - Triggered when the sample FIFO reaches a certain level.\n - This level can be programmed via the FCS_THRESH field. - [0:0] - read-only - - - - - - - PWM - 1 - Simple PWM - 0x40050000 - 0x20 - - 0x0 - 0x1000 - registers - - - PWM_IRQ_WRAP - 4 - - - - 8 - 0x14 - 0-7 - CH%s - Cluster CH%s, containing CH*_CC, CH*_CSR, CH*_CTR, CH*_DIV, CH*_TOP + + 12 + 0x40 + 0-11 + CH%s + Cluster CH%s, containing CH?_READ_ADDR,CH??_READ_ADDR, CH?_WRITE_ADDR,CH??_WRITE_ADDR, CH?_TRANS_COUNT,CH??_TRANS_COUNT, CH?_CTRL_TRIG,CH??_CTRL_TRIG, CH?_AL1_CTRL,CH??_AL1_CTRL, CH?_AL1_READ_ADDR,CH??_AL1_READ_ADDR, CH?_AL1_WRITE_ADDR,CH??_AL1_WRITE_ADDR, CH?_AL1_TRANS_COUNT_TRIG,CH??_AL1_TRANS_COUNT_TRIG, CH?_AL2_CTRL,CH??_AL2_CTRL, CH?_AL2_TRANS_COUNT,CH??_AL2_TRANS_COUNT, CH?_AL2_READ_ADDR,CH??_AL2_READ_ADDR, CH?_AL2_WRITE_ADDR_TRIG,CH??_AL2_WRITE_ADDR_TRIG, CH?_AL3_CTRL,CH??_AL3_CTRL, CH?_AL3_WRITE_ADDR,CH??_AL3_WRITE_ADDR, CH?_AL3_TRANS_COUNT,CH??_AL3_TRANS_COUNT, CH?_AL3_READ_ADDR_TRIG,CH??_AL3_READ_ADDR_TRIG 0x0 - CC - Counter compare values - 0xC + CH_READ_ADDR + DMA Channel 0 Read Address pointer + 0x0 0x00000000 - B - [31:16] + CH0_READ_ADDR + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + [31:0] read-write + + + + CH_WRITE_ADDR + DMA Channel 0 Write Address pointer + 0x4 + 0x00000000 + - A - [15:0] + CH0_WRITE_ADDR + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + [31:0] read-write - CSR - Control and status register - 0x0 + CH_TRANS_COUNT + DMA Channel 0 Transfer Count + 0x8 0x00000000 - PH_ADV - Advance the phase of the counter by 1 count, while it is running.\n - Self-clearing. Write a 1, and poll until low. Counter must be running\n - at less than full speed (div_int + div_frac / 16 > 1) - [7:7] + CH0_TRANS_COUNT + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). + + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. + + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. + + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + [31:0] read-write - clear + + + + CH_CTRL_TRIG + DMA Channel 0 Control and Status + 0xC + 0x00000000 + - PH_RET - Retard the phase of the counter by 1 count, while it is running.\n - Self-clearing. Write a 1, and poll until low. Counter must be running. - [6:6] + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] read-write - clear + oneToClear - DIVMODE - [5:4] + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. + + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [24:24] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis. + [23:23] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [22:22] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [21:21] + read-write + + + TREQ_SEL + Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ + [20:15] read-write + TREQ_SEL - div - Free-running counting at rate dictated by fractional divider + PIO0_TX0 + Select PIO0's TX FIFO 0 as TREQ 0 - level - Fractional divider operation is gated by the PWM B pin. + PIO0_TX1 + Select PIO0's TX FIFO 1 as TREQ 1 - rise - Counter advances with each rising edge of the PWM B pin. + PIO0_TX2 + Select PIO0's TX FIFO 2 as TREQ 2 - fall - Counter advances with each falling edge of the PWM B pin. + PIO0_TX3 + Select PIO0's TX FIFO 3 as TREQ 3 - - - - B_INV - Invert output B - [3:3] - read-write - - - A_INV - Invert output A - [2:2] - read-write + + PIO0_RX0 + Select PIO0's RX FIFO 0 as TREQ + 4 + + + PIO0_RX1 + Select PIO0's RX FIFO 1 as TREQ + 5 + + + PIO0_RX2 + Select PIO0's RX FIFO 2 as TREQ + 6 + + + PIO0_RX3 + Select PIO0's RX FIFO 3 as TREQ + 7 + + + PIO1_TX0 + Select PIO1's TX FIFO 0 as TREQ + 8 + + + PIO1_TX1 + Select PIO1's TX FIFO 1 as TREQ + 9 + + + PIO1_TX2 + Select PIO1's TX FIFO 2 as TREQ + 10 + + + PIO1_TX3 + Select PIO1's TX FIFO 3 as TREQ + 11 + + + PIO1_RX0 + Select PIO1's RX FIFO 0 as TREQ + 12 + + + PIO1_RX1 + Select PIO1's RX FIFO 1 as TREQ + 13 + + + PIO1_RX2 + Select PIO1's RX FIFO 2 as TREQ + 14 + + + PIO1_RX3 + Select PIO1's RX FIFO 3 as TREQ + 15 + + + SPI0_TX + Select SPI0's TX FIFO as TREQ + 16 + + + SPI0_RX + Select SPI0's RX FIFO as TREQ + 17 + + + SPI1_TX + Select SPI1's TX FIFO as TREQ + 18 + + + SPI1_RX + Select SPI1's RX FIFO as TREQ + 19 + + + UART0_TX + Select UART0's TX FIFO as TREQ + 20 + + + UART0_RX + Select UART0's RX FIFO as TREQ + 21 + + + UART1_TX + Select UART1's TX FIFO as TREQ + 22 + + + UART1_RX + Select UART1's RX FIFO as TREQ + 23 + + + PWM_WRAP0 + Select PWM Counter 0's Wrap Value as TREQ + 24 + + + PWM_WRAP1 + Select PWM Counter 1's Wrap Value as TREQ + 25 + + + PWM_WRAP2 + Select PWM Counter 2's Wrap Value as TREQ + 26 + + + PWM_WRAP3 + Select PWM Counter 3's Wrap Value as TREQ + 27 + + + PWM_WRAP4 + Select PWM Counter 4's Wrap Value as TREQ + 28 + + + PWM_WRAP5 + Select PWM Counter 5's Wrap Value as TREQ + 29 + + + PWM_WRAP6 + Select PWM Counter 6's Wrap Value as TREQ + 30 + + + PWM_WRAP7 + Select PWM Counter 7's Wrap Value as TREQ + 31 + + + I2C0_TX + Select I2C0's TX FIFO as TREQ + 32 + + + I2C0_RX + Select I2C0's RX FIFO as TREQ + 33 + + + I2C1_TX + Select I2C1's TX FIFO as TREQ + 34 + + + I2C1_RX + Select I2C1's RX FIFO as TREQ + 35 + + + ADC + Select the ADC as TREQ + 36 + + + XIP_STREAM + Select the XIP Streaming FIFO as TREQ + 37 + + + XIP_SSITX + Select the XIP SSI TX FIFO as TREQ + 38 + + + XIP_SSIRX + Select the XIP SSI RX FIFO as TREQ + 39 + + + TIMER0 + Select Timer 0 as TREQ + 59 + + + TIMER1 + Select Timer 1 as TREQ + 60 + + + TIMER2 + Select Timer 2 as TREQ (Optional) + 61 + + + TIMER3 + Select Timer 3 as TREQ (Optional) + 62 + + + PERMANENT + Permanent request, for unpaced transfers. + 63 + + - PH_CORRECT - 1: Enable phase-correct modulation. 0: Trailing-edge - [1:1] + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. \n Reset value is 0, which means for channels 1 and above the default will be to chain to channel 0 - set this field to avoid this behaviour. + [14:11] read-write - EN - Enable the PWM channel. - [0:0] + RING_SEL + Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [10:10] read-write - - - - CTR - Direct access to the PWM counter - 0x8 - 0x00000000 - - CTR - [15:0] + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [9:6] read-write + + + RING_NONE + 0 + + - - - - DIV - INT and FRAC form a fixed-point fractional number.\n - Counting rate is system clock frequency divided by this number.\n - Fractional division uses simple 1st-order sigma-delta. - 0x4 - 0x00000010 - - INT - [11:4] + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers. + [5:5] read-write - FRAC - [3:0] + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] read-write - - + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + - TOP - Counter wrap value + CH_AL1_CTRL + DMA Channel 0 Control and Status 0x10 - 0x0000FFFF + 0x00000000 - TOP - [15:0] + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] read-write - - - - - - EN - This register aliases the CSR_EN bits for all channels.\n - Writing to this register allows multiple channels to be enabled\n - or disabled simultaneously, so they can run in perfect sync.\n - For each channel, there is only one physical EN register bit,\n - which can be accessed through here or CHx_CSR. - 0xA0 - 0x00000000 - - - CH7 - [7:7] - read-write - - - CH6 - [6:6] - read-write - - - CH5 - [5:5] - read-write - - - CH4 - [4:4] - read-write - - - CH3 - [3:3] - read-write - - - CH2 - [2:2] - read-write - - - CH1 - [1:1] - read-write - - - CH0 - [0:0] - read-write - - - - - INTR - Raw Interrupts - 0xA4 - 0x00000000 - - - CH7 - [7:7] - read-write - oneToClear - - - CH6 - [6:6] - read-write - oneToClear - - - CH5 - [5:5] - read-write - oneToClear - - - CH4 - [4:4] - read-write - oneToClear - - - CH3 - [3:3] - read-write - oneToClear - - - CH2 - [2:2] - read-write - oneToClear - - - CH1 - [1:1] - read-write - oneToClear - - - CH0 - [0:0] - read-write - oneToClear - - - - - INTE - Interrupt Enable - 0xA8 - 0x00000000 - - - CH7 - [7:7] - read-write - - - CH6 - [6:6] - read-write - - - CH5 - [5:5] - read-write - - - CH4 - [4:4] - read-write - - - CH3 - [3:3] - read-write - - - CH2 - [2:2] - read-write - - - CH1 - [1:1] - read-write - - - CH0 - [0:0] - read-write - - - - - INTF - Interrupt Force - 0xAC - 0x00000000 - - - CH7 - [7:7] - read-write - - - CH6 - [6:6] - read-write - - - CH5 - [5:5] - read-write - - - CH4 - [4:4] - read-write - - - CH3 - [3:3] - read-write - - - CH2 - [2:2] - read-write - - - CH1 - [1:1] - read-write - - - CH0 - [0:0] - read-write - - - - - INTS - Interrupt status after masking & forcing - 0xB0 - 0x00000000 - - - CH7 - [7:7] - read-only - - - CH6 - [6:6] - read-only - - - CH5 - [5:5] - read-only - - - CH4 - [4:4] - read-only - - - CH3 - [3:3] - read-only - - - CH2 - [2:2] - read-only - - - CH1 - [1:1] - read-only - - - CH0 - [0:0] - read-only - - - - - - - TIMER - 1 - Controls time and alarms\n - time is a 64 bit value indicating the time in usec since power-on\n - timeh is the top 32 bits of time & timel is the bottom 32 bits\n - to change time write to timelw before timehw\n - to read time read from timelr before timehr\n - An alarm is set by setting alarm_enable and writing to the corresponding alarm register\n - When an alarm is pending, the corresponding alarm_running signal will be high\n - An alarm can be cancelled before it has finished by clearing the alarm_enable\n - When an alarm fires, the corresponding alarm_irq is set and alarm_running is cleared\n - To clear the interrupt write a 1 to the corresponding alarm_irq - 0x40054000 - 0x20 - - 0x0 - 0x1000 - registers - - - TIMER_IRQ_0 - 0 - - - TIMER_IRQ_1 - 1 - - - TIMER_IRQ_2 - 2 - - - TIMER_IRQ_3 - 3 - - - - TIMEHW - Write to bits 63:32 of time\n - always write timelw before timehw - 0x0 - write-only - 0x00000000 - - - TIMELW - Write to bits 31:0 of time\n - writes do not get copied to time until timehw is written - 0x4 - write-only - 0x00000000 - - - TIMEHR - Read from bits 63:32 of time\n - always read timelr before timehr - 0x8 - read-only - 0x00000000 - - - TIMELR - Read from bits 31:0 of time - 0xC - read-only - 0x00000000 - - - ALARM0 - Arm alarm 0, and configure the time it will fire.\n - Once armed, the alarm fires when TIMER_ALARM0 == TIMELR.\n - The alarm will disarm itself once it fires, and can\n - be disarmed early using the ARMED status register. - 0x10 - read-write - 0x00000000 - - - ALARM1 - Arm alarm 1, and configure the time it will fire.\n - Once armed, the alarm fires when TIMER_ALARM1 == TIMELR.\n - The alarm will disarm itself once it fires, and can\n - be disarmed early using the ARMED status register. - 0x14 - read-write - 0x00000000 - - - ALARM2 - Arm alarm 2, and configure the time it will fire.\n - Once armed, the alarm fires when TIMER_ALARM2 == TIMELR.\n - The alarm will disarm itself once it fires, and can\n - be disarmed early using the ARMED status register. - 0x18 - read-write - 0x00000000 - - - ALARM3 - Arm alarm 3, and configure the time it will fire.\n - Once armed, the alarm fires when TIMER_ALARM3 == TIMELR.\n - The alarm will disarm itself once it fires, and can\n - be disarmed early using the ARMED status register. - 0x1C - read-write - 0x00000000 - - - ARMED - Indicates the armed/disarmed status of each alarm.\n - A write to the corresponding ALARMx register arms the alarm.\n - Alarms automatically disarm upon firing, but writing ones here\n - will disarm immediately without waiting to fire. - 0x20 - 0x00000000 - - - ARMED - [3:0] - read-write - oneToClear - - - - - TIMERAWH - Raw read from bits 63:32 of time (no side effects) - 0x24 - read-only - 0x00000000 - - - TIMERAWL - Raw read from bits 31:0 of time (no side effects) - 0x28 - read-only - 0x00000000 - - - DBGPAUSE - Set bits high to enable pause when the corresponding debug ports are active - 0x2C - 0x00000007 - - - DBG1 - Pause when processor 1 is in debug mode - [2:2] - read-write - - - DBG0 - Pause when processor 0 is in debug mode - [1:1] - read-write - - - - - PAUSE - Set high to pause the timer - 0x30 - 0x00000000 - - - PAUSE - [0:0] - read-write - - - - - INTR - Raw Interrupts - 0x34 - 0x00000000 - - - ALARM_3 - [3:3] - read-write - oneToClear - - - ALARM_2 - [2:2] - read-write - oneToClear - - - ALARM_1 - [1:1] - read-write - oneToClear - - - ALARM_0 - [0:0] - read-write - oneToClear - - - - - INTE - Interrupt Enable - 0x38 - 0x00000000 - - - ALARM_3 - [3:3] - read-write - - - ALARM_2 - [2:2] - read-write - - - ALARM_1 - [1:1] - read-write - - - ALARM_0 - [0:0] - read-write - - - - - INTF - Interrupt Force - 0x3C - 0x00000000 - - - ALARM_3 - [3:3] - read-write - - - ALARM_2 - [2:2] - read-write - - - ALARM_1 - [1:1] - read-write - - - ALARM_0 - [0:0] - read-write - - - - - INTS - Interrupt status after masking & forcing - 0x40 - 0x00000000 - - - ALARM_3 - [3:3] - read-only - - - ALARM_2 - [2:2] - read-only - - - ALARM_1 - [1:1] - read-only - - - ALARM_0 - [0:0] - read-only - - - - - - - WATCHDOG - 1 - 0x40058000 - 0x20 - - 0x0 - 0x1000 - registers - - - - CTRL - Watchdog control\n - The rst_wdsel register determines which subsystems are reset when the watchdog is triggered.\n - The watchdog can be triggered in software. - 0x0 - 0x07000000 - - - TRIGGER - Trigger a watchdog reset - [31:31] - read-write - clear - - - ENABLE - When not enabled the watchdog timer is paused - [30:30] - read-write - - - PAUSE_DBG1 - Pause the watchdog timer when processor 1 is in debug mode - [26:26] - read-write - - - PAUSE_DBG0 - Pause the watchdog timer when processor 0 is in debug mode - [25:25] - read-write - - - PAUSE_JTAG - Pause the watchdog timer when JTAG is accessing the bus fabric - [24:24] - read-write - - - TIME - Indicates the number of ticks / 2 (see errata RP2040-E1) before a watchdog reset will be triggered - [23:0] - read-only - - - - - LOAD - Load the watchdog timer. The maximum setting is 0xffffff which corresponds to 0xffffff / 2 ticks before triggering a watchdog reset (see errata RP2040-E1). - 0x4 - 0x00000000 - - - LOAD - [23:0] - write-only - - - - - REASON - Logs the reason for the last reset. Both bits are zero for the case of a hardware reset. - 0x8 - 0x00000000 - - - FORCE - [1:1] - read-only - - - TIMER - [0:0] - read-only - - - - - SCRATCH0 - Scratch register. Information persists through soft reset of the chip. - 0xC - read-write - 0x00000000 - - - SCRATCH1 - Scratch register. Information persists through soft reset of the chip. - 0x10 - read-write - 0x00000000 - - - SCRATCH2 - Scratch register. Information persists through soft reset of the chip. - 0x14 - read-write - 0x00000000 - - - SCRATCH3 - Scratch register. Information persists through soft reset of the chip. - 0x18 - read-write - 0x00000000 - - - SCRATCH4 - Scratch register. Information persists through soft reset of the chip. - 0x1C - read-write - 0x00000000 - - - SCRATCH5 - Scratch register. Information persists through soft reset of the chip. - 0x20 - read-write - 0x00000000 - - - SCRATCH6 - Scratch register. Information persists through soft reset of the chip. - 0x24 - read-write - 0x00000000 - - - SCRATCH7 - Scratch register. Information persists through soft reset of the chip. - 0x28 - read-write - 0x00000000 - - - TICK - Controls the tick generator - 0x2C - 0x00000200 - - - COUNT - Count down timer: the remaining number clk_tick cycles before the next tick is generated. - [19:11] - read-only - - - RUNNING - Is the tick generator running? - [10:10] - read-only - - - ENABLE - start / stop tick generation - [9:9] - read-write - - - CYCLES - Total number of clk_tick cycles before the next tick. - [8:0] - read-write - - - - - - - RTC - 1 - Register block to control RTC - 0x4005C000 - 0x20 - - 0x0 - 0x1000 - registers - - - RTC_IRQ - 25 - - - - CLKDIV_M1 - Divider minus 1 for the 1 second counter. Safe to change the value when RTC is not enabled. - 0x0 - 0x00000000 - - - CLKDIV_M1 - [15:0] - read-write - - - - - SETUP_0 - RTC setup register 0 - 0x4 - 0x00000000 - - - YEAR - Year - [23:12] - read-write - - - MONTH - Month (1..12) - [11:8] - read-write - - - DAY - Day of the month (1..31) - [4:0] - read-write - - - - - SETUP_1 - RTC setup register 1 - 0x8 - 0x00000000 - - - DOTW - Day of the week: 1-Monday...0-Sunday ISO 8601 mod 7 - [26:24] - read-write - - - HOUR - Hours - [20:16] - read-write - - - MIN - Minutes - [13:8] - read-write - - - SEC - Seconds - [5:0] - read-write - - - - - CTRL - RTC Control and status - 0xC - 0x00000000 - - - FORCE_NOTLEAPYEAR - If set, leapyear is forced off.\n - Useful for years divisible by 100 but not by 400 - [8:8] - read-write - - - LOAD - Load RTC - [4:4] - read-write - clear - - - RTC_ACTIVE - RTC enabled (running) - [1:1] - read-only - - - RTC_ENABLE - Enable RTC - [0:0] - read-write - - - - - IRQ_SETUP_0 - Interrupt setup register 0 - 0x10 - 0x00000000 - - - MATCH_ACTIVE - [29:29] - read-only - - - MATCH_ENA - Global match enable. Don't change any other value while this one is enabled - [28:28] - read-write - - - YEAR_ENA - Enable year matching - [26:26] - read-write - - - MONTH_ENA - Enable month matching - [25:25] - read-write - - - DAY_ENA - Enable day matching - [24:24] - read-write - - - YEAR - Year - [23:12] - read-write - - - MONTH - Month (1..12) - [11:8] - read-write - - - DAY - Day of the month (1..31) - [4:0] - read-write - - - - - IRQ_SETUP_1 - Interrupt setup register 1 - 0x14 - 0x00000000 - - - DOTW_ENA - Enable day of the week matching - [31:31] - read-write - - - HOUR_ENA - Enable hour matching - [30:30] - read-write - - - MIN_ENA - Enable minute matching - [29:29] - read-write - - - SEC_ENA - Enable second matching - [28:28] - read-write - - - DOTW - Day of the week - [26:24] - read-write - - - HOUR - Hours - [20:16] - read-write - - - MIN - Minutes - [13:8] - read-write - - - SEC - Seconds - [5:0] - read-write - - - - - RTC_1 - RTC register 1. - 0x18 - 0x00000000 - - - YEAR - Year - [23:12] - read-only - - - MONTH - Month (1..12) - [11:8] - read-only - - - DAY - Day of the month (1..31) - [4:0] - read-only - - - - - RTC_0 - RTC register 0\n - Read this before RTC 1! - 0x1C - 0x00000000 - - - DOTW - Day of the week - [26:24] - read-only - - - HOUR - Hours - [20:16] - read-only - - - MIN - Minutes - [13:8] - read-only - - - SEC - Seconds - [5:0] - read-only - - - - - INTR - Raw Interrupts - 0x20 - 0x00000000 - - - RTC - [0:0] - read-only - - - - - INTE - Interrupt Enable - 0x24 - 0x00000000 - - - RTC - [0:0] - read-write - - - - - INTF - Interrupt Force - 0x28 - 0x00000000 - - - RTC - [0:0] - read-write - - - - - INTS - Interrupt status after masking & forcing - 0x2C - 0x00000000 - - - RTC - [0:0] - read-only - - - - - - - ROSC - 1 - 0x40060000 - 0x20 - - 0x0 - 0x1000 - registers - - - - CTRL - Ring Oscillator control - 0x0 - 0x00000AA0 - - - ENABLE - On power-up this field is initialised to ENABLE\n - The system clock must be switched to another source before setting this field to DISABLE otherwise the chip will lock up\n - The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator. - [23:12] - read-write - - - DISABLE - 3358 - - - ENABLE - 4011 - - - - - FREQ_RANGE - Controls the number of delay stages in the ROSC ring\n - LOW uses stages 0 to 7\n - MEDIUM uses stages 0 to 5\n - HIGH uses stages 0 to 3\n - TOOHIGH uses stages 0 to 1 and should not be used because its frequency exceeds design specifications\n - The clock output will not glitch when changing the range up one step at a time\n - The clock output will glitch when changing the range down\n - Note: the values here are gray coded which is why HIGH comes before TOOHIGH - [11:0] - read-write - - - LOW - 4004 - - - MEDIUM - 4005 - - - HIGH - 4007 - - - TOOHIGH - 4006 - - - - - - - FREQA - The FREQA & FREQB registers control the frequency by controlling the drive strength of each stage\n - The drive strength has 4 levels determined by the number of bits set\n - Increasing the number of bits set increases the drive strength and increases the oscillation frequency\n - 0 bits set is the default drive strength\n - 1 bit set doubles the drive strength\n - 2 bits set triples drive strength\n - 3 bits set quadruples drive strength - 0x4 - 0x00000000 - - - PASSWD - Set to 0x9696 to apply the settings\n - Any other value in this field will set all drive strengths to 0 - [31:16] - read-write - - - PASS - 38550 - - - - - DS3 - Stage 3 drive strength - [14:12] - read-write - - - DS2 - Stage 2 drive strength - [10:8] - read-write - - - DS1 - Stage 1 drive strength - [6:4] - read-write - - - DS0 - Stage 0 drive strength - [2:0] - read-write - - - - - FREQB - For a detailed description see freqa register - 0x8 - 0x00000000 - - - PASSWD - Set to 0x9696 to apply the settings\n - Any other value in this field will set all drive strengths to 0 - [31:16] - read-write - - - PASS - 38550 - - - - - DS7 - Stage 7 drive strength - [14:12] - read-write - - - DS6 - Stage 6 drive strength - [10:8] - read-write - - - DS5 - Stage 5 drive strength - [6:4] - read-write - - - DS4 - Stage 4 drive strength - [2:0] - read-write - - - - - DORMANT - Ring Oscillator pause control\n - This is used to save power by pausing the ROSC\n - On power-up this field is initialised to WAKE\n - An invalid write will also select WAKE\n - Warning: setup the irq before selecting dormant mode - 0xC - read-write - 0x00000000 - - - DIV - Controls the output divider - 0x10 - 0x00000000 - - - DIV - set to 0xaa0 + div where\n - div = 0 divides by 32\n - div = 1-31 divides by div\n - any other value sets div=31\n - this register resets to div=16 - [11:0] - read-write - - - PASS - 2720 - - - - - - - PHASE - Controls the phase shifted output - 0x14 - 0x00000008 - - - PASSWD - set to 0xaa\n - any other value enables the output with shift=0 - [11:4] - read-write - - - ENABLE - enable the phase-shifted output\n - this can be changed on-the-fly - [3:3] - read-write - - - FLIP - invert the phase-shifted output\n - this is ignored when div=1 - [2:2] - read-write - - - SHIFT - phase shift the phase-shifted output by SHIFT input clocks\n - this can be changed on-the-fly\n - must be set to 0 before setting div=1 - [1:0] - read-write - - - - - RANDOMBIT - This just reads the state of the oscillator output so randomness is compromised if the ring oscillator is stopped or run at a harmonic of the bus frequency - 0x1C - 0x00000001 - - - RANDOMBIT - [0:0] - read-only - - - - - STATUS - Ring Oscillator Status - 0x18 - 0x00000000 - - - STABLE - Oscillator is running and stable - 31 - 1 - read-only - - - DIV_RUNNING - post-divider is running - this resets to 0 but transitions to 1 during chip startup - 16 - 1 - read-only - - - ENABLED - Oscillator is enabled but not necessarily running and stable - this resets to 0 but transitions to 1 during chip startup - 12 - 1 - read-only - - - - - - - VREG_AND_CHIP_RESET - 1 - control and status for on-chip voltage regulator and chip level reset subsystem - 0x40064000 - 0x20 - - 0x0 - 0x1000 - registers - - - - VREG - Voltage regulator control and status - 0x0 - 0x000000B1 - - - ROK - regulation status\n - 0=not in regulation, 1=in regulation - [12:12] - read-only - - - VSEL - Output voltage select for on-chip voltage regulator. - [7:4] - read-write - - VSEL - - Voltage0_80 - 0.80V - 5 - - - Voltage0_85 - 0.85V - 6 - - - Voltage0_90 - 0.90V - 7 - - - Voltage0_95 - 0.95V - 8 - - - Voltage1_00 - 1.00V - 9 - - - Voltage1_05 - 1.05V - 10 - - - Voltage1_10 - 1.10V (default) - 11 - - - Voltage1_15 - 1.15V - 12 - - - Voltage1_20 - 1.20V - 13 - - - Voltage1_25 - 1.25V - 14 - - - Voltage1_30 - 1.30V - 15 - - - - - HIZ - high impedance mode select\n - 0=not in high impedance mode, 1=in high impedance mode - [1:1] - read-write - - - EN - enable\n - 0=not enabled, 1=enabled - [0:0] - read-write - - - - - BOD - brown-out detection control - 0x4 - 0x00000091 - - - VSEL - threshold select\n - 0000 - 0.473V\n - 0001 - 0.516V\n - 0010 - 0.559V\n - 0011 - 0.602V\n - 0100 - 0.645V\n - 0101 - 0.688V\n - 0110 - 0.731V\n - 0111 - 0.774V\n - 1000 - 0.817V\n - 1001 - 0.860V (default)\n - 1010 - 0.903V\n - 1011 - 0.946V\n - 1100 - 0.989V\n - 1101 - 1.032V\n - 1110 - 1.075V\n - 1111 - 1.118V - [7:4] - read-write - - - EN - enable\n - 0=not enabled, 1=enabled - [0:0] - read-write - - - - - CHIP_RESET - Chip reset control and status - 0x8 - 0x00000000 - - - PSM_RESTART_FLAG - This is set by psm_restart from the debugger.\n - Its purpose is to branch bootcode to a safe mode when the debugger has issued a psm_restart in order to recover from a boot lock-up.\n - In the safe mode the debugger can repair the boot code, clear this flag then reboot the processor. - [24:24] - read-write - oneToClear - - - HAD_PSM_RESTART - Last reset was from the debug port - [20:20] - read-only - - - HAD_RUN - Last reset was from the RUN pin - [16:16] - read-only - - - HAD_POR - Last reset was from the power-on reset or brown-out detection blocks - [8:8] - read-only - - - - - - - TBMAN - 1 - Testbench manager. Allows the programmer to know what platform their software is running on. - 0x4006C000 - 0x20 - - 0x0 - 0x1000 - registers - - - - PLATFORM - Indicates the type of platform in use - 0x0 - 0x00000005 - - - FPGA - Indicates the platform is an FPGA - [1:1] - read-only - - - ASIC - Indicates the platform is an ASIC - [0:0] - read-only - - - - - - - DMA - 1 - DMA with separate read and write masters - 0x50000000 - 0x20 - - 0x0 - 0x1000 - registers - - - DMA_IRQ_0 - 11 - - - DMA_IRQ_1 - 12 - - - - 12 - 0x40 - 0-11 - CH%s - Cluster CH%s, containing CH?_READ_ADDR,CH??_READ_ADDR, CH?_WRITE_ADDR,CH??_WRITE_ADDR, CH?_TRANS_COUNT,CH??_TRANS_COUNT, CH?_CTRL_TRIG,CH??_CTRL_TRIG, CH?_AL1_CTRL,CH??_AL1_CTRL, CH?_AL1_READ_ADDR,CH??_AL1_READ_ADDR, CH?_AL1_WRITE_ADDR,CH??_AL1_WRITE_ADDR, CH?_AL1_TRANS_COUNT_TRIG,CH??_AL1_TRANS_COUNT_TRIG, CH?_AL2_CTRL,CH??_AL2_CTRL, CH?_AL2_TRANS_COUNT,CH??_AL2_TRANS_COUNT, CH?_AL2_READ_ADDR,CH??_AL2_READ_ADDR, CH?_AL2_WRITE_ADDR_TRIG,CH??_AL2_WRITE_ADDR_TRIG, CH?_AL3_CTRL,CH??_AL3_CTRL, CH?_AL3_WRITE_ADDR,CH??_AL3_WRITE_ADDR, CH?_AL3_TRANS_COUNT,CH??_AL3_TRANS_COUNT, CH?_AL3_READ_ADDR_TRIG,CH??_AL3_READ_ADDR_TRIG - 0x0 - - CH_READ_ADDR - DMA Channel 0 Read Address pointer\n - This register updates automatically each time a read completes. The current value is the next address to be read by this channel. - 0x0 - read-write - 0x00000000 - - - CH_WRITE_ADDR - DMA Channel 0 Write Address pointer\n - This register updates automatically each time a write completes. The current value is the next address to be written by this channel. - 0x4 - read-write - 0x00000000 - - - CH_TRANS_COUNT - DMA Channel 0 Transfer Count\n - Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n - When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n - Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n - The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. - 0x8 - read-write - 0x00000000 - - - CH_CTRL_TRIG - DMA Channel 0 Control and Status - 0xC - 0x00000000 - - - AHB_ERROR - Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. - [31:31] - read-only - - - READ_ERROR - If 1, the channel received a read bus error. Write one to clear.\n - READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) - [30:30] - read-write - oneToClear - - - WRITE_ERROR - If 1, the channel received a write bus error. Write one to clear.\n - WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) - [29:29] - read-write - oneToClear - - - BUSY - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n - To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. - [24:24] - read-only - - - SNIFF_EN - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n - This allows checksum to be enabled or disabled on a per-control- block basis. - [23:23] - read-write - - - BSWAP - Apply byte-swap transformation to DMA data.\n - For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. - [22:22] - read-write - - - IRQ_QUIET - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n - This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. - [21:21] - read-write - - - TREQ_SEL - Select a Transfer Request signal.\n - The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n - 0x0 to 0x3a -> select DREQ n as TREQ - [20:15] - read-write - - TREQ_SEL - - PIO0_TX0 - Select PIO0's TX FIFO 0 as TREQ - 0 - - - PIO0_TX1 - Select PIO0's TX FIFO 1 as TREQ - 1 - - - PIO0_TX2 - Select PIO0's TX FIFO 2 as TREQ - 2 - - - PIO0_TX3 - Select PIO0's TX FIFO 3 as TREQ - 3 - - - PIO0_RX0 - Select PIO0's RX FIFO 0 as TREQ - 4 - - - PIO0_RX1 - Select PIO0's RX FIFO 1 as TREQ - 5 - - - PIO0_RX2 - Select PIO0's RX FIFO 2 as TREQ - 6 - - - PIO0_RX3 - Select PIO0's RX FIFO 3 as TREQ - 7 - - - PIO1_TX0 - Select PIO1's TX FIFO 0 as TREQ - 8 - - - PIO1_TX1 - Select PIO1's TX FIFO 1 as TREQ - 9 - - - PIO1_TX2 - Select PIO1's TX FIFO 2 as TREQ - 10 - - - PIO1_TX3 - Select PIO1's TX FIFO 3 as TREQ - 11 - - - PIO1_RX0 - Select PIO1's RX FIFO 0 as TREQ - 12 - - - PIO1_RX1 - Select PIO1's RX FIFO 1 as TREQ - 13 - - - PIO1_RX2 - Select PIO1's RX FIFO 2 as TREQ - 14 - - - PIO1_RX3 - Select PIO1's RX FIFO 3 as TREQ - 15 - - - SPI0_TX - Select SPI0's TX FIFO as TREQ - 16 - - - SPI0_RX - Select SPI0's RX FIFO as TREQ - 17 - - - SPI1_TX - Select SPI1's TX FIFO as TREQ - 18 - - - SPI1_RX - Select SPI1's RX FIFO as TREQ - 19 - - - UART0_TX - Select UART0's TX FIFO as TREQ - 20 - - - UART0_RX - Select UART0's RX FIFO as TREQ - 21 - - - UART1_TX - Select UART1's TX FIFO as TREQ - 22 - - - UART1_RX - Select UART1's RX FIFO as TREQ - 23 - - - PWM_WRAP0 - Select PWM Counter 0's Wrap Value as TREQ - 24 - - - PWM_WRAP1 - Select PWM Counter 1's Wrap Value as TREQ - 25 - - - PWM_WRAP2 - Select PWM Counter 2's Wrap Value as TREQ - 26 - - - PWM_WRAP3 - Select PWM Counter 3's Wrap Value as TREQ - 27 - - - PWM_WRAP4 - Select PWM Counter 4's Wrap Value as TREQ - 28 - - - PWM_WRAP5 - Select PWM Counter 5's Wrap Value as TREQ - 29 - - - PWM_WRAP6 - Select PWM Counter 6's Wrap Value as TREQ - 30 - - - PWM_WRAP7 - Select PWM Counter 7's Wrap Value as TREQ - 31 - - - I2C0_TX - Select I2C0's TX FIFO as TREQ - 32 - - - I2C0_RX - Select I2C0's RX FIFO as TREQ - 33 - - - I2C1_TX - Select I2C1's TX FIFO as TREQ - 34 - - - I2C1_RX - Select I2C1's RX FIFO as TREQ - 35 - - - ADC - Select the ADC as TREQ - 36 - - - XIP_STREAM - Select the XIP Streaming FIFO as TREQ - 37 - - - XIP_SSITX - Select the XIP SSI TX FIFO as TREQ - 38 - - - XIP_SSIRX - Select the XIP SSI RX FIFO as TREQ - 39 - - - TIMER0 - Select Timer 0 as TREQ - 59 - - - TIMER1 - Select Timer 1 as TREQ - 60 - - - TIMER2 - Select Timer 2 as TREQ (Optional) - 61 - - - TIMER3 - Select Timer 3 as TREQ (Optional) - 62 - - - PERMANENT - Permanent request, for unpaced transfers. - 63 - - - - - CHAIN_TO - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. \n Reset value is 0, which means for channels 1 and above the default will be to chain to channel 0 - set this field to avoid this behaviour. - [14:11] - read-write - - - RING_SEL - Select whether RING_SIZE applies to read or write addresses.\n - If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. - [10:10] - read-write - - - RING_SIZE - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n - Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. - [9:6] - read-write - - - RING_NONE - 0 - - - - - INCR_WRITE - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n - Generally this should be disabled for memory-to-peripheral transfers. - [5:5] - read-write - - - INCR_READ - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n - Generally this should be disabled for peripheral-to-memory transfers. - [4:4] - read-write - - - DATA_SIZE - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. - [3:2] - read-write - - - SIZE_BYTE - 0 - - - SIZE_HALFWORD - 1 - - - SIZE_WORD - 2 - - - - - HIGH_PRIORITY - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n - This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. - [1:1] - read-write - - - EN - DMA Channel Enable.\n - When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) - [0:0] - read-write - - - - - CH_AL1_CTRL - DMA Channel 0 Control and Status - 0x10 - 0x00000000 - - - AHB_ERROR - Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. - [31:31] - read-only - - - READ_ERROR - If 1, the channel received a read bus error. Write one to clear.\n - READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) - [30:30] - read-write - oneToClear + oneToClear WRITE_ERROR - If 1, the channel received a write bus error. Write one to clear.\n - WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) [29:29] read-write oneToClear BUSY - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n - To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. + + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. [24:24] read-only SNIFF_EN - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n - This allows checksum to be enabled or disabled on a per-control- block basis. + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis. [23:23] read-write BSWAP - Apply byte-swap transformation to DMA data.\n - For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. [22:22] read-write IRQ_QUIET - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n - This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. [21:21] read-write TREQ_SEL - Select a Transfer Request signal.\n - The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n - 0x0 to 0x3a -> select DREQ n as TREQ + Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ [20:15] read-write @@ -15473,15 +11609,16 @@ RING_SEL - Select whether RING_SIZE applies to read or write addresses.\n - If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. [10:10] read-write RING_SIZE - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n - Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. [9:6] read-write @@ -15493,15 +11630,17 @@ INCR_WRITE - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n - Generally this should be disabled for memory-to-peripheral transfers. + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers. [5:5] read-write INCR_READ - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n - Generally this should be disabled for peripheral-to-memory transfers. + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers. [4:4] read-write @@ -15527,15 +11666,16 @@ HIGH_PRIORITY - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n - This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. [1:1] read-write EN - DMA Channel Enable.\n - When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) [0:0] read-write @@ -15545,24 +11685,42 @@ CH_AL1_READ_ADDR Alias for channel 0 READ_ADDR register 0x14 - read-write - 0x00000000 + 0x00000000 + + + CH0_AL1_READ_ADDR + [31:0] + read-write + + CH_AL1_WRITE_ADDR Alias for channel 0 WRITE_ADDR register 0x18 - read-write - 0x00000000 + 0x00000000 + + + CH0_AL1_WRITE_ADDR + [31:0] + read-write + + CH_AL1_TRANS_COUNT_TRIG - Alias for channel 0 TRANS_COUNT register\n - This is a trigger register (0xc). Writing a nonzero value will\n - reload the channel counter and start the channel. + Alias for channel 0 TRANS_COUNT register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. 0x1C - read-write - 0x00000000 + 0x00000000 + + + CH0_AL1_TRANS_COUNT_TRIG + [31:0] + read-write + + CH_AL2_CTRL @@ -15578,53 +11736,56 @@ READ_ERROR - If 1, the channel received a read bus error. Write one to clear.\n - READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) [30:30] read-write oneToClear WRITE_ERROR - If 1, the channel received a write bus error. Write one to clear.\n - WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) [29:29] read-write oneToClear BUSY - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n - To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. + + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. [24:24] read-only SNIFF_EN - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n - This allows checksum to be enabled or disabled on a per-control- block basis. + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis. [23:23] read-write BSWAP - Apply byte-swap transformation to DMA data.\n - For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. [22:22] read-write IRQ_QUIET - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n - This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. [21:21] read-write TREQ_SEL - Select a Transfer Request signal.\n - The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n - 0x0 to 0x3a -> select DREQ n as TREQ + Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ [20:15] read-write @@ -15864,15 +12025,16 @@ RING_SEL - Select whether RING_SIZE applies to read or write addresses.\n - If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. [10:10] read-write RING_SIZE - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n - Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. [9:6] read-write @@ -15884,15 +12046,17 @@ INCR_WRITE - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n - Generally this should be disabled for memory-to-peripheral transfers. + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers. [5:5] read-write INCR_READ - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n - Generally this should be disabled for peripheral-to-memory transfers. + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers. [4:4] read-write @@ -15918,15 +12082,16 @@ HIGH_PRIORITY - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n - This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. [1:1] read-write EN - DMA Channel Enable.\n - When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) [0:0] read-write @@ -15936,24 +12101,42 @@ CH_AL2_TRANS_COUNT Alias for channel 0 TRANS_COUNT register 0x24 - read-write - 0x00000000 + 0x00000000 + + + CH0_AL2_TRANS_COUNT + [31:0] + read-write + + CH_AL2_READ_ADDR Alias for channel 0 READ_ADDR register 0x28 - read-write - 0x00000000 + 0x00000000 + + + CH0_AL2_READ_ADDR + [31:0] + read-write + + CH_AL2_WRITE_ADDR_TRIG - Alias for channel 0 WRITE_ADDR register\n - This is a trigger register (0xc). Writing a nonzero value will\n - reload the channel counter and start the channel. + Alias for channel 0 WRITE_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. 0x2C - read-write - 0x00000000 + 0x00000000 + + + CH0_AL2_WRITE_ADDR_TRIG + [31:0] + read-write + + CH_AL3_CTRL @@ -15969,53 +12152,56 @@ READ_ERROR - If 1, the channel received a read bus error. Write one to clear.\n - READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) [30:30] read-write oneToClear WRITE_ERROR - If 1, the channel received a write bus error. Write one to clear.\n - WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) [29:29] read-write oneToClear BUSY - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n - To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. + + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. [24:24] read-only SNIFF_EN - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n - This allows checksum to be enabled or disabled on a per-control- block basis. + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis. [23:23] read-write BSWAP - Apply byte-swap transformation to DMA data.\n - For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. [22:22] read-write IRQ_QUIET - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n - This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. [21:21] read-write TREQ_SEL - Select a Transfer Request signal.\n - The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n - 0x0 to 0x3a -> select DREQ n as TREQ + Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ [20:15] read-write @@ -16254,5975 +12440,10644 @@ read-write - RING_SEL - Select whether RING_SIZE applies to read or write addresses.\n - If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. - [10:10] + RING_SEL + Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [10:10] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [9:6] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH_AL3_WRITE_ADDR + Alias for channel 0 WRITE_ADDR register + 0x34 + 0x00000000 + + + CH0_AL3_WRITE_ADDR + [31:0] + read-write + + + + + CH_AL3_TRANS_COUNT + Alias for channel 0 TRANS_COUNT register + 0x38 + 0x00000000 + + + CH0_AL3_TRANS_COUNT + [31:0] + read-write + + + + + CH_AL3_READ_ADDR_TRIG + Alias for channel 0 READ_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x3C + 0x00000000 + + + CH0_AL3_READ_ADDR_TRIG + [31:0] + read-write + + + + + + INTR + Interrupt Status (raw) + 0x400 + 0x00000000 + + + INTR + Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR, INTS0 or INTS1. + + Channel interrupts can be routed to either of two system-level IRQs based on INTE0 and INTE1. + + This can be used vector different channel interrupts to different ISRs: this might be done to allow NVIC IRQ preemption for more time-critical channels, or to spread IRQ load across different cores. + + It is also valid to ignore this behaviour and just use INTE0/INTS0/IRQ 0. + [15:0] + read-write + oneToClear + + + + + INTE0 + Interrupt Enables for IRQ 0 + 0x404 + 0x00000000 + + + INTE0 + Set bit n to pass interrupts from channel n to DMA IRQ 0. + [15:0] + read-write + + + + + INTF0 + Force Interrupts + 0x408 + 0x00000000 + + + INTF0 + Write 1s to force the corresponding bits in INTE0. The interrupt remains asserted until INTF0 is cleared. + [15:0] + read-write + + + + + INTS0 + Interrupt Status for IRQ 0 + 0x40C + 0x00000000 + + + INTS0 + Indicates active channel interrupt requests which are currently causing IRQ 0 to be asserted. + Channel interrupts can be cleared by writing a bit mask here. + [15:0] + read-write + oneToClear + + + + + INTR1 + Interrupt Status (raw) + 0x410 + 0x00000000 + + + INTR1 + Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR, INTS0 or INTS1. + + Channel interrupts can be routed to either of two system-level IRQs based on INTE0 and INTE1. + + This can be used vector different channel interrupts to different ISRs: this might be done to allow NVIC IRQ preemption for more time-critical channels, or to spread IRQ load across different cores. + + It is also valid to ignore this behaviour and just use INTE0/INTS0/IRQ 0. + [15:0] + read-write + oneToClear + + + + + INTE1 + Interrupt Enables for IRQ 1 + 0x414 + 0x00000000 + + + INTE1 + Set bit n to pass interrupts from channel n to DMA IRQ 1. + [15:0] + read-write + + + + + INTF1 + Force Interrupts for IRQ 1 + 0x418 + 0x00000000 + + + INTF1 + Write 1s to force the corresponding bits in INTE0. The interrupt remains asserted until INTF0 is cleared. + [15:0] + read-write + + + + + INTS1 + Interrupt Status (masked) for IRQ 1 + 0x41C + 0x00000000 + + + INTS1 + Indicates active channel interrupt requests which are currently causing IRQ 1 to be asserted. + Channel interrupts can be cleared by writing a bit mask here. + [15:0] + read-write + oneToClear + + + + + TIMER0 + Pacing (X/Y) Fractional Timer + The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. + 0x420 + 0x00000000 + + + X + Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. + [31:16] + read-write + + + Y + Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. + [15:0] + read-write + + + + + TIMER1 + Pacing (X/Y) Fractional Timer + The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. + 0x424 + 0x00000000 + + + X + Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. + [31:16] + read-write + + + Y + Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. + [15:0] + read-write + + + + + TIMER2 + Pacing (X/Y) Fractional Timer + The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. + 0x428 + 0x00000000 + + + X + Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. + [31:16] + read-write + + + Y + Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. + [15:0] + read-write + + + + + TIMER3 + Pacing (X/Y) Fractional Timer + The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. + 0x42C + 0x00000000 + + + X + Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. + [31:16] + read-write + + + Y + Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. + [15:0] + read-write + + + + + MULTI_CHAN_TRIGGER + Trigger one or more channels simultaneously + 0x430 + 0x00000000 + + + MULTI_CHAN_TRIGGER + Each bit in this register corresponds to a DMA channel. Writing a 1 to the relevant bit is the same as writing to that channel's trigger register; the channel will start if it is currently enabled and not already busy. + [15:0] + write-only + + + + + SNIFF_CTRL + Sniffer Control + 0x434 + 0x00000000 + + + OUT_INV + If set, the result appears inverted (bitwise complement) when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus. + [11:11] + read-write + + + OUT_REV + If set, the result appears bit-reversed when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus. + [10:10] + read-write + + + BSWAP + Locally perform a byte reverse on the sniffed data, before feeding into checksum. + + Note that the sniff hardware is downstream of the DMA channel byteswap performed in the read master: if channel CTRL_BSWAP and SNIFF_CTRL_BSWAP are both enabled, their effects cancel from the sniffer's point of view. + [9:9] + read-write + + + CALC + [8:5] + read-write + + + CRC32 + Calculate a CRC-32 (IEEE802.3 polynomial) + 0 + + + CRC32R + Calculate a CRC-32 (IEEE802.3 polynomial) with bit reversed data + 1 + + + CRC16 + Calculate a CRC-16-CCITT + 2 + + + CRC16R + Calculate a CRC-16-CCITT with bit reversed data + 3 + + + EVEN + XOR reduction over all data. == 1 if the total 1 population count is odd. + 14 + + + SUM + Calculate a simple 32-bit checksum (addition with a 32 bit accumulator) + 15 + + + + + DMACH + DMA channel for Sniffer to observe + [4:1] + read-write + + + EN + Enable sniffer + [0:0] + read-write + + + + + SNIFF_DATA + Data accumulator for sniff hardware + 0x438 + 0x00000000 + + + SNIFF_DATA + Write an initial seed value here before starting a DMA transfer on the channel indicated by SNIFF_CTRL_DMACH. The hardware will update this register each time it observes a read from the indicated channel. Once the channel completes, the final result can be read from this register. + [31:0] + read-write + + + + + FIFO_LEVELS + Debug RAF, WAF, TDF levels + 0x440 + 0x00000000 + + + RAF_LVL + Current Read-Address-FIFO fill level + [23:16] + read-only + + + WAF_LVL + Current Write-Address-FIFO fill level + [15:8] + read-only + + + TDF_LVL + Current Transfer-Data-FIFO fill level + [7:0] + read-only + + + + + CHAN_ABORT + Abort an in-progress transfer sequence on one or more channels + 0x444 + 0x00000000 + + + CHAN_ABORT + Each bit corresponds to a channel. Writing a 1 aborts whatever transfer sequence is in progress on that channel. The bit will remain high until any in-flight transfers have been flushed through the address and data FIFOs. + + After writing, this register must be polled until it returns all-zero. Until this point, it is unsafe to restart the channel. + [15:0] + read-write + + + + + N_CHANNELS + The number of channels this DMA instance is equipped with. This DMA supports up to 16 hardware channels, but can be configured with as few as one, to minimise silicon area. + 0x448 + 0x00000000 + + + N_CHANNELS + [4:0] + read-only + + + + + CH0_DBG_CTDREQ + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x800 + 0x00000000 + + + CH0_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH0_DBG_TCR + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x804 + 0x00000000 + + + CH0_DBG_TCR + [31:0] + read-only + + + + + CH1_DBG_CTDREQ + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x840 + 0x00000000 + + + CH1_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH1_DBG_TCR + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x844 + 0x00000000 + + + CH1_DBG_TCR + [31:0] + read-only + + + + + CH2_DBG_CTDREQ + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x880 + 0x00000000 + + + CH2_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH2_DBG_TCR + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x884 + 0x00000000 + + + CH2_DBG_TCR + [31:0] + read-only + + + + + CH3_DBG_CTDREQ + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x8C0 + 0x00000000 + + + CH3_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH3_DBG_TCR + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x8C4 + 0x00000000 + + + CH3_DBG_TCR + [31:0] + read-only + + + + + CH4_DBG_CTDREQ + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x900 + 0x00000000 + + + CH4_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH4_DBG_TCR + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x904 + 0x00000000 + + + CH4_DBG_TCR + [31:0] + read-only + + + + + CH5_DBG_CTDREQ + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x940 + 0x00000000 + + + CH5_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH5_DBG_TCR + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x944 + 0x00000000 + + + CH5_DBG_TCR + [31:0] + read-only + + + + + CH6_DBG_CTDREQ + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x980 + 0x00000000 + + + CH6_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH6_DBG_TCR + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x984 + 0x00000000 + + + CH6_DBG_TCR + [31:0] + read-only + + + + + CH7_DBG_CTDREQ + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x9C0 + 0x00000000 + + + CH7_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH7_DBG_TCR + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x9C4 + 0x00000000 + + + CH7_DBG_TCR + [31:0] + read-only + + + + + CH8_DBG_CTDREQ + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0xA00 + 0x00000000 + + + CH8_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH8_DBG_TCR + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0xA04 + 0x00000000 + + + CH8_DBG_TCR + [31:0] + read-only + + + + + CH9_DBG_CTDREQ + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0xA40 + 0x00000000 + + + CH9_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH9_DBG_TCR + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0xA44 + 0x00000000 + + + CH9_DBG_TCR + [31:0] + read-only + + + + + CH10_DBG_CTDREQ + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0xA80 + 0x00000000 + + + CH10_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH10_DBG_TCR + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0xA84 + 0x00000000 + + + CH10_DBG_TCR + [31:0] + read-only + + + + + CH11_DBG_CTDREQ + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0xAC0 + 0x00000000 + + + CH11_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH11_DBG_TCR + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0xAC4 + 0x00000000 + + + CH11_DBG_TCR + [31:0] + read-only + + + + + + + TIMER + Controls time and alarms + time is a 64 bit value indicating the time in usec since power-on + timeh is the top 32 bits of time & timel is the bottom 32 bits + to change time write to timelw before timehw + to read time read from timelr before timehr + An alarm is set by setting alarm_enable and writing to the corresponding alarm register + When an alarm is pending, the corresponding alarm_running signal will be high + An alarm can be cancelled before it has finished by clearing the alarm_enable + When an alarm fires, the corresponding alarm_irq is set and alarm_running is cleared + To clear the interrupt write a 1 to the corresponding alarm_irq + 0x40054000 + + 0x0 + 0x44 + registers + + + TIMER_IRQ_0 + 0 + + + TIMER_IRQ_1 + 1 + + + TIMER_IRQ_2 + 2 + + + TIMER_IRQ_3 + 3 + + + + TIMEHW + Write to bits 63:32 of time + always write timelw before timehw + 0x0 + 0x00000000 + + + TIMEHW + [31:0] + write-only + + + + + TIMELW + Write to bits 31:0 of time + writes do not get copied to time until timehw is written + 0x4 + 0x00000000 + + + TIMELW + [31:0] + write-only + + + + + TIMEHR + Read from bits 63:32 of time + always read timelr before timehr + 0x8 + 0x00000000 + + + TIMEHR + [31:0] + read-only + + + + + TIMELR + Read from bits 31:0 of time + 0xC + 0x00000000 + + + TIMELR + [31:0] + read-only + modify + + + + + ALARM0 + Arm alarm 0, and configure the time it will fire. + Once armed, the alarm fires when TIMER_ALARM0 == TIMELR. + The alarm will disarm itself once it fires, and can + be disarmed early using the ARMED status register. + 0x10 + 0x00000000 + + + ALARM0 + [31:0] + read-write + + + + + ALARM1 + Arm alarm 1, and configure the time it will fire. + Once armed, the alarm fires when TIMER_ALARM1 == TIMELR. + The alarm will disarm itself once it fires, and can + be disarmed early using the ARMED status register. + 0x14 + 0x00000000 + + + ALARM1 + [31:0] + read-write + + + + + ALARM2 + Arm alarm 2, and configure the time it will fire. + Once armed, the alarm fires when TIMER_ALARM2 == TIMELR. + The alarm will disarm itself once it fires, and can + be disarmed early using the ARMED status register. + 0x18 + 0x00000000 + + + ALARM2 + [31:0] + read-write + + + + + ALARM3 + Arm alarm 3, and configure the time it will fire. + Once armed, the alarm fires when TIMER_ALARM3 == TIMELR. + The alarm will disarm itself once it fires, and can + be disarmed early using the ARMED status register. + 0x1C + 0x00000000 + + + ALARM3 + [31:0] + read-write + + + + + ARMED + Indicates the armed/disarmed status of each alarm. + A write to the corresponding ALARMx register arms the alarm. + Alarms automatically disarm upon firing, but writing ones here + will disarm immediately without waiting to fire. + 0x20 + 0x00000000 + + + ARMED + [3:0] + read-write + oneToClear + + + + + TIMERAWH + Raw read from bits 63:32 of time (no side effects) + 0x24 + 0x00000000 + + + TIMERAWH + [31:0] + read-only + + + + + TIMERAWL + Raw read from bits 31:0 of time (no side effects) + 0x28 + 0x00000000 + + + TIMERAWL + [31:0] + read-only + + + + + DBGPAUSE + Set bits high to enable pause when the corresponding debug ports are active + 0x2C + 0x00000007 + + + DBG1 + Pause when processor 1 is in debug mode + [2:2] + read-write + + + DBG0 + Pause when processor 0 is in debug mode + [1:1] + read-write + + + + + PAUSE + Set high to pause the timer + 0x30 + 0x00000000 + + + PAUSE + [0:0] + read-write + + + + + INTR + Raw Interrupts + 0x34 + 0x00000000 + + + ALARM_3 + [3:3] + read-write + oneToClear + + + ALARM_2 + [2:2] + read-write + oneToClear + + + ALARM_1 + [1:1] + read-write + oneToClear + + + ALARM_0 + [0:0] + read-write + oneToClear + + + + + INTE + Interrupt Enable + 0x38 + 0x00000000 + + + ALARM_3 + [3:3] + read-write + + + ALARM_2 + [2:2] + read-write + + + ALARM_1 + [1:1] + read-write + + + ALARM_0 + [0:0] + read-write + + + + + INTF + Interrupt Force + 0x3C + 0x00000000 + + + ALARM_3 + [3:3] + read-write + + + ALARM_2 + [2:2] + read-write + + + ALARM_1 + [1:1] + read-write + + + ALARM_0 + [0:0] + read-write + + + + + INTS + Interrupt status after masking & forcing + 0x40 + 0x00000000 + + + ALARM_3 + [3:3] + read-only + + + ALARM_2 + [2:2] + read-only + + + ALARM_1 + [1:1] + read-only + + + ALARM_0 + [0:0] + read-only + + + + + + + PWM + Simple PWM + 0x40050000 + + 0x0 + 0xB4 + registers + + + PWM_IRQ_WRAP + 4 + + + + 8 + 0x14 + 0-7 + CH%s + Cluster CH%s, containing CH*_CC, CH*_CSR, CH*_CTR, CH*_DIV, CH*_TOP + 0x0 + + CC + Counter compare values + 0xC + 0x00000000 + + + B + [31:16] read-write - RING_SIZE - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n - Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. - [9:6] + A + [15:0] read-write - - - RING_NONE - 0 - - + + + + CSR + Control and status register + 0x0 + 0x00000000 + - INCR_WRITE - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n - Generally this should be disabled for memory-to-peripheral transfers. - [5:5] - read-write + PH_ADV + Advance the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running + at less than full speed (div_int + div_frac / 16 > 1) + [7:7] + write-only - INCR_READ - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n - Generally this should be disabled for peripheral-to-memory transfers. - [4:4] - read-write + PH_RET + Retard the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running. + [6:6] + write-only - DATA_SIZE - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. - [3:2] + DIVMODE + [5:4] read-write - SIZE_BYTE + div + Free-running counting at rate dictated by fractional divider 0 - SIZE_HALFWORD + level + Fractional divider operation is gated by the PWM B pin. 1 - SIZE_WORD + rise + Counter advances with each rising edge of the PWM B pin. 2 + + fall + Counter advances with each falling edge of the PWM B pin. + 3 + - HIGH_PRIORITY - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n - This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + B_INV + Invert output B + [3:3] + read-write + + + A_INV + Invert output A + [2:2] + read-write + + + PH_CORRECT + 1: Enable phase-correct modulation. 0: Trailing-edge [1:1] read-write EN - DMA Channel Enable.\n - When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + Enable the PWM channel. [0:0] read-write - CH_AL3_WRITE_ADDR - Alias for channel 0 WRITE_ADDR register - 0x34 - read-write + CTR + Direct access to the PWM counter + 0x8 0x00000000 + + + CTR + [15:0] + read-write + + - CH_AL3_TRANS_COUNT - Alias for channel 0 TRANS_COUNT register - 0x38 - read-write - 0x00000000 + DIV + INT and FRAC form a fixed-point fractional number. + Counting rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. + 0x4 + 0x00000010 + + + INT + [11:4] + read-write + + + FRAC + [3:0] + read-write + + - CH_AL3_READ_ADDR_TRIG - Alias for channel 0 READ_ADDR register\n - This is a trigger register (0xc). Writing a nonzero value will\n - reload the channel counter and start the channel. - 0x3C - read-write - 0x00000000 + TOP + Counter wrap value + 0x10 + 0x0000FFFF + + + TOP + [15:0] + read-write + + - INTR - Interrupt Status (raw) - 0x400 + EN + This register aliases the CSR_EN bits for all channels. + Writing to this register allows multiple channels to be enabled + or disabled simultaneously, so they can run in perfect sync. + For each channel, there is only one physical EN register bit, + which can be accessed through here or CHx_CSR. + 0xA0 + 0x00000000 + + + CH7 + [7:7] + read-write + + + CH6 + [6:6] + read-write + + + CH5 + [5:5] + read-write + + + CH4 + [4:4] + read-write + + + CH3 + [3:3] + read-write + + + CH2 + [2:2] + read-write + + + CH1 + [1:1] + read-write + + + CH0 + [0:0] + read-write + + + + + INTR + Raw Interrupts + 0xA4 + 0x00000000 + + + CH7 + [7:7] + read-write + oneToClear + + + CH6 + [6:6] + read-write + oneToClear + + + CH5 + [5:5] + read-write + oneToClear + + + CH4 + [4:4] + read-write + oneToClear + + + CH3 + [3:3] + read-write + oneToClear + + + CH2 + [2:2] + read-write + oneToClear + + + CH1 + [1:1] + read-write + oneToClear + + + CH0 + [0:0] + read-write + oneToClear + + + + + INTE + Interrupt Enable + 0xA8 + 0x00000000 + + + CH7 + [7:7] + read-write + + + CH6 + [6:6] + read-write + + + CH5 + [5:5] + read-write + + + CH4 + [4:4] + read-write + + + CH3 + [3:3] + read-write + + + CH2 + [2:2] + read-write + + + CH1 + [1:1] + read-write + + + CH0 + [0:0] + read-write + + + + + INTF + Interrupt Force + 0xAC + 0x00000000 + + + CH7 + [7:7] + read-write + + + CH6 + [6:6] + read-write + + + CH5 + [5:5] + read-write + + + CH4 + [4:4] + read-write + + + CH3 + [3:3] + read-write + + + CH2 + [2:2] + read-write + + + CH1 + [1:1] + read-write + + + CH0 + [0:0] + read-write + + + + + INTS + Interrupt status after masking & forcing + 0xB0 + 0x00000000 + + + CH7 + [7:7] + read-only + + + CH6 + [6:6] + read-only + + + CH5 + [5:5] + read-only + + + CH4 + [4:4] + read-only + + + CH3 + [3:3] + read-only + + + CH2 + [2:2] + read-only + + + CH1 + [1:1] + read-only + + + CH0 + [0:0] + read-only + + + + + + + ADC + Control and data interface to SAR ADC + 0x4004C000 + + 0x0 + 0x24 + registers + + + ADC_IRQ_FIFO + 22 + + + + CS + ADC Control and Status + 0x0 + 0x00000000 + + + RROBIN + Round-robin sampling. 1 bit per channel. Set all bits to 0 to disable. + Otherwise, the ADC will cycle through each enabled channel in a round-robin fashion. + The first channel to be sampled will be the one currently indicated by AINSEL. + AINSEL will be updated after each conversion with the newly-selected channel. + [20:16] + read-write + + + AINSEL + Select analog mux input. Updated automatically in round-robin mode. + [14:12] + read-write + + + ERR_STICKY + Some past ADC conversion encountered an error. Write 1 to clear. + [10:10] + read-write + oneToClear + + + ERR + The most recent ADC conversion encountered an error; result is undefined or noisy. + [9:9] + read-only + + + READY + 1 if the ADC is ready to start a new conversion. Implies any previous conversion has completed. + 0 whilst conversion in progress. + [8:8] + read-only + + + START_MANY + Continuously perform conversions whilst this bit is 1. A new conversion will start immediately after the previous finishes. + [3:3] + read-write + + + START_ONCE + Start a single conversion. Self-clearing. Ignored if start_many is asserted. + [2:2] + write-only + + + TS_EN + Power on temperature sensor. 1 - enabled. 0 - disabled. + [1:1] + read-write + + + EN + Power on ADC and enable its clock. + 1 - enabled. 0 - disabled. + [0:0] + read-write + + + + + RESULT + Result of most recent ADC conversion + 0x4 + 0x00000000 + + + RESULT + [11:0] + read-only + + + + + FCS + FIFO control and status + 0x8 + 0x00000000 + + + THRESH + DREQ/IRQ asserted when level >= threshold + [27:24] + read-write + + + LEVEL + The number of conversion results currently waiting in the FIFO + [19:16] + read-only + + + OVER + 1 if the FIFO has been overflowed. Write 1 to clear. + [11:11] + read-write + oneToClear + + + UNDER + 1 if the FIFO has been underflowed. Write 1 to clear. + [10:10] + read-write + oneToClear + + + FULL + [9:9] + read-only + + + EMPTY + [8:8] + read-only + + + DREQ_EN + If 1: assert DMA requests when FIFO contains data + [3:3] + read-write + + + ERR + If 1: conversion error bit appears in the FIFO alongside the result + [2:2] + read-write + + + SHIFT + If 1: FIFO results are right-shifted to be one byte in size. Enables DMA to byte buffers. + [1:1] + read-write + + + EN + If 1: write result to the FIFO after each conversion. + [0:0] + read-write + + + + + FIFO + Conversion result FIFO + 0xC + 0x00000000 + + + ERR + 1 if this particular sample experienced a conversion error. Remains in the same location if the sample is shifted. + [15:15] + read-only + modify + + + VAL + [11:0] + read-only + modify + + + + + DIV + Clock divider. If non-zero, CS_START_MANY will start conversions + at regular intervals rather than back-to-back. + The divider is reset when either of these fields are written. + Total period is 1 + INT + FRAC / 256 + 0x10 + 0x00000000 + + + INT + Integer part of clock divisor. + [23:8] + read-write + + + FRAC + Fractional part of clock divisor. First-order delta-sigma. + [7:0] + read-write + + + + + INTR + Raw Interrupts + 0x14 + 0x00000000 + + + FIFO + Triggered when the sample FIFO reaches a certain level. + This level can be programmed via the FCS_THRESH field. + [0:0] + read-only + + + + + INTE + Interrupt Enable + 0x18 + 0x00000000 + + + FIFO + Triggered when the sample FIFO reaches a certain level. + This level can be programmed via the FCS_THRESH field. + [0:0] + read-write + + + + + INTF + Interrupt Force + 0x1C + 0x00000000 + + + FIFO + Triggered when the sample FIFO reaches a certain level. + This level can be programmed via the FCS_THRESH field. + [0:0] + read-write + + + + + INTS + Interrupt status after masking & forcing + 0x20 + 0x00000000 + + + FIFO + Triggered when the sample FIFO reaches a certain level. + This level can be programmed via the FCS_THRESH field. + [0:0] + read-only + + + + + + + I2C0 + DW_apb_i2c address block + + List of configuration constants for the Synopsys I2C hardware (you may see references to these in I2C register header; these are *fixed* values, set at hardware design time): + + IC_ULTRA_FAST_MODE ................ 0x0 + IC_UFM_TBUF_CNT_DEFAULT ........... 0x8 + IC_UFM_SCL_LOW_COUNT .............. 0x0008 + IC_UFM_SCL_HIGH_COUNT ............. 0x0006 + IC_TX_TL .......................... 0x0 + IC_TX_CMD_BLOCK ................... 0x1 + IC_HAS_DMA ........................ 0x1 + IC_HAS_ASYNC_FIFO ................. 0x0 + IC_SMBUS_ARP ...................... 0x0 + IC_FIRST_DATA_BYTE_STATUS ......... 0x1 + IC_INTR_IO ........................ 0x1 + IC_MASTER_MODE .................... 0x1 + IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1 + IC_INTR_POL ....................... 0x1 + IC_OPTIONAL_SAR ................... 0x0 + IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055 + IC_DEFAULT_SLAVE_ADDR ............. 0x055 + IC_DEFAULT_HS_SPKLEN .............. 0x1 + IC_FS_SCL_HIGH_COUNT .............. 0x0006 + IC_HS_SCL_LOW_COUNT ............... 0x0008 + IC_DEVICE_ID_VALUE ................ 0x0 + IC_10BITADDR_MASTER ............... 0x0 + IC_CLK_FREQ_OPTIMIZATION .......... 0x0 + IC_DEFAULT_FS_SPKLEN .............. 0x7 + IC_ADD_ENCODED_PARAMS ............. 0x0 + IC_DEFAULT_SDA_HOLD ............... 0x000001 + IC_DEFAULT_SDA_SETUP .............. 0x64 + IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0 + IC_CLOCK_PERIOD ................... 100 + IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1 + IC_RESTART_EN ..................... 0x1 + IC_TX_CMD_BLOCK_DEFAULT ........... 0x0 + IC_BUS_CLEAR_FEATURE .............. 0x0 + IC_CAP_LOADING .................... 100 + IC_FS_SCL_LOW_COUNT ............... 0x000d + APB_DATA_WIDTH .................... 32 + IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff + IC_SLV_DATA_NACK_ONLY ............. 0x1 + IC_10BITADDR_SLAVE ................ 0x0 + IC_CLK_TYPE ....................... 0x0 + IC_SMBUS_UDID_MSB ................. 0x0 + IC_SMBUS_SUSPEND_ALERT ............ 0x0 + IC_HS_SCL_HIGH_COUNT .............. 0x0006 + IC_SLV_RESTART_DET_EN ............. 0x1 + IC_SMBUS .......................... 0x0 + IC_OPTIONAL_SAR_DEFAULT ........... 0x0 + IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0 + IC_USE_COUNTS ..................... 0x0 + IC_RX_BUFFER_DEPTH ................ 16 + IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff + IC_RX_FULL_HLD_BUS_EN ............. 0x1 + IC_SLAVE_DISABLE .................. 0x1 + IC_RX_TL .......................... 0x0 + IC_DEVICE_ID ...................... 0x0 + IC_HC_COUNT_VALUES ................ 0x0 + I2C_DYNAMIC_TAR_UPDATE ............ 0 + IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff + IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff + IC_HS_MASTER_CODE ................. 0x1 + IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff + IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff + IC_SS_SCL_HIGH_COUNT .............. 0x0028 + IC_SS_SCL_LOW_COUNT ............... 0x002f + IC_MAX_SPEED_MODE ................. 0x2 + IC_STAT_FOR_CLK_STRETCH ........... 0x0 + IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0 + IC_DEFAULT_UFM_SPKLEN ............. 0x1 + IC_TX_BUFFER_DEPTH ................ 16 + 0x40044000 + + 0x0 + 0x100 + registers + + + I2C0_IRQ + 23 + + + + IC_CON + I2C Control Register. This register can be written only when the DW_apb_i2c is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. + + Read/Write Access: - bit 10 is read only. - bit 11 is read only - bit 16 is read only - bit 17 is read only - bits 18 and 19 are read only. + 0x0 + 0x00000065 + + + STOP_DET_IF_MASTER_ACTIVE + Master issues the STOP_DET interrupt irrespective of whether master is active or not + [10:10] + read-only + + + RX_FIFO_FULL_HLD_CTRL + This bit controls whether DW_apb_i2c should hold the bus when the Rx FIFO is physically full to its RX_BUFFER_DEPTH, as described in the IC_RX_FULL_HLD_BUS_EN parameter. + + Reset value: 0x0. + [9:9] + read-write + + + DISABLED + Overflow when RX_FIFO is full + 0 + + + ENABLED + Hold bus when RX_FIFO is full + 1 + + + + + TX_EMPTY_CTRL + This bit controls the generation of the TX_EMPTY interrupt, as described in the IC_RAW_INTR_STAT register. + + Reset value: 0x0. + [8:8] + read-write + + + DISABLED + Default behaviour of TX_EMPTY interrupt + 0 + + + ENABLED + Controlled generation of TX_EMPTY interrupt + 1 + + + + + STOP_DET_IFADDRESSED + In slave mode: - 1'b1: issues the STOP_DET interrupt only when it is addressed. - 1'b0: issues the STOP_DET irrespective of whether it's addressed or not. Reset value: 0x0 + + NOTE: During a general call address, this slave does not issue the STOP_DET interrupt if STOP_DET_IF_ADDRESSED = 1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR). + [7:7] + read-write + + + DISABLED + slave issues STOP_DET intr always + 0 + + + ENABLED + slave issues STOP_DET intr only if addressed + 1 + + + + + IC_SLAVE_DISABLE + This bit controls whether I2C has its slave disabled, which means once the presetn signal is applied, then this bit is set and the slave is disabled. + + If this bit is set (slave is disabled), DW_apb_i2c functions only as a master and does not perform any action that requires a slave. + + NOTE: Software should ensure that if this bit is written with 0, then bit 0 should also be written with a 0. + [6:6] + read-write + + + SLAVE_ENABLED + Slave mode is enabled + 0 + + + SLAVE_DISABLED + Slave mode is disabled + 1 + + + + + IC_RESTART_EN + Determines whether RESTART conditions may be sent when acting as a master. Some older slaves do not support handling RESTART conditions; however, RESTART conditions are used in several DW_apb_i2c operations. When RESTART is disabled, the master is prohibited from performing the following functions: - Sending a START BYTE - Performing any high-speed mode operation - High-speed mode operation - Performing direction changes in combined format mode - Performing a read operation with a 10-bit address By replacing RESTART condition followed by a STOP and a subsequent START condition, split operations are broken down into multiple DW_apb_i2c transfers. If the above operations are performed, it will result in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. + + Reset value: ENABLED + [5:5] + read-write + + + DISABLED + Master restart disabled + 0 + + + ENABLED + Master restart enabled + 1 + + + + + IC_10BITADDR_MASTER + Controls whether the DW_apb_i2c starts its transfers in 7- or 10-bit addressing mode when acting as a master. - 0: 7-bit addressing - 1: 10-bit addressing + [4:4] + read-write + + + ADDR_7BITS + Master 7Bit addressing mode + 0 + + + ADDR_10BITS + Master 10Bit addressing mode + 1 + + + + + IC_10BITADDR_SLAVE + When acting as a slave, this bit controls whether the DW_apb_i2c responds to 7- or 10-bit addresses. - 0: 7-bit addressing. The DW_apb_i2c ignores transactions that involve 10-bit addressing; for 7-bit addressing, only the lower 7 bits of the IC_SAR register are compared. - 1: 10-bit addressing. The DW_apb_i2c responds to only 10-bit addressing transfers that match the full 10 bits of the IC_SAR register. + [3:3] + read-write + + + ADDR_7BITS + Slave 7Bit addressing + 0 + + + ADDR_10BITS + Slave 10Bit addressing + 1 + + + + + SPEED + These bits control at which speed the DW_apb_i2c operates; its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode also, as it is used to capture correct value of spike filter as per the speed mode. + + This register should be programmed only with a value in the range of 1 to IC_MAX_SPEED_MODE; otherwise, hardware updates this register with the value of IC_MAX_SPEED_MODE. + + 1: standard mode (100 kbit/s) + + 2: fast mode (<=400 kbit/s) or fast mode plus (<=1000Kbit/s) + + 3: high speed mode (3.4 Mbit/s) + + Note: This field is not applicable when IC_ULTRA_FAST_MODE=1 + [2:1] + read-write + + + STANDARD + Standard Speed mode of operation + 1 + + + FAST + Fast or Fast Plus mode of operation + 2 + + + HIGH + High Speed mode of operation + 3 + + + + + MASTER_MODE + This bit controls whether the DW_apb_i2c master is enabled. + + NOTE: Software should ensure that if this bit is written with '1' then bit 6 should also be written with a '1'. + [0:0] + read-write + + + DISABLED + Master mode is disabled + 0 + + + ENABLED + Master mode is enabled + 1 + + + + + + + IC_TAR + I2C Target Address Register + + This register is 12 bits wide, and bits 31:12 are reserved. This register can be written to only when IC_ENABLE[0] is set to 0. + + Note: If the software or application is aware that the DW_apb_i2c is not using the TAR address for the pending commands in the Tx FIFO, then it is possible to update the TAR address even while the Tx FIFO has entries (IC_STATUS[2]= 0). - It is not necessary to perform any write to this register if DW_apb_i2c is enabled as an I2C slave only. + 0x4 + 0x00000055 + + + SPECIAL + This bit indicates whether software performs a Device-ID or General Call or START BYTE command. - 0: ignore bit 10 GC_OR_START and use IC_TAR normally - 1: perform special I2C command as specified in Device_ID or GC_OR_START bit Reset value: 0x0 + [11:11] + read-write + + + DISABLED + Disables programming of GENERAL_CALL or START_BYTE transmission + 0 + + + ENABLED + Enables programming of GENERAL_CALL or START_BYTE transmission + 1 + + + + + GC_OR_START + If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to 0, then this bit indicates whether a General Call or START byte command is to be performed by the DW_apb_i2c. - 0: General Call Address - after issuing a General Call, only writes may be performed. Attempting to issue a read command results in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. The DW_apb_i2c remains in General Call mode until the SPECIAL bit value (bit 11) is cleared. - 1: START BYTE Reset value: 0x0 + [10:10] + read-write + + + GENERAL_CALL + GENERAL_CALL byte transmission + 0 + + + START_BYTE + START byte transmission + 1 + + + + + IC_TAR + This is the target address for any master transaction. When transmitting a General Call, these bits are ignored. To generate a START BYTE, the CPU needs to write only once into these bits. + + If the IC_TAR and IC_SAR are the same, loopback exists but the FIFOs are shared between master and slave, so full loopback is not feasible. Only one direction loopback mode is supported (simplex), not duplex. A master cannot transmit to itself; it can transmit to only a slave. + [9:0] + read-write + + + + + IC_SAR + I2C Slave Address Register + 0x8 + 0x00000055 + + + IC_SAR + The IC_SAR holds the slave address when the I2C is operating as a slave. For 7-bit addressing, only IC_SAR[6:0] is used. + + This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. + + Note: The default values cannot be any of the reserved address locations: that is, 0x00 to 0x07, or 0x78 to 0x7f. The correct operation of the device is not guaranteed if you program the IC_SAR or IC_TAR to a reserved value. Refer to <<table_I2C_firstbyte_bit_defs>> for a complete list of these reserved values. + [9:0] + read-write + + + + + IC_DATA_CMD + I2C Rx/Tx Data Buffer and Command Register; this is the register the CPU writes to when filling the TX FIFO and the CPU reads from when retrieving bytes from RX FIFO. + + The size of the register changes as follows: + + Write: - 11 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=1 - 9 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=0 Read: - 12 bits when IC_FIRST_DATA_BYTE_STATUS = 1 - 8 bits when IC_FIRST_DATA_BYTE_STATUS = 0 Note: In order for the DW_apb_i2c to continue acknowledging reads, a read command should be written for every byte that is to be received; otherwise the DW_apb_i2c will stop acknowledging. + 0x10 + 0x00000000 + + + FIRST_DATA_BYTE + Indicates the first data byte received after the address phase for receive transfer in Master receiver or Slave receiver mode. + + Reset value : 0x0 + + NOTE: In case of APB_DATA_WIDTH=8, + + 1. The user has to perform two APB Reads to IC_DATA_CMD in order to get status on 11 bit. + + 2. In order to read the 11 bit, the user has to perform the first data byte read [7:0] (offset 0x10) and then perform the second read [15:8] (offset 0x11) in order to know the status of 11 bit (whether the data received in previous read is a first data byte or not). + + 3. The 11th bit is an optional read field, user can ignore 2nd byte read [15:8] (offset 0x11) if not interested in FIRST_DATA_BYTE status. + [11:11] + read-only + + + INACTIVE + Sequential data byte received + 0 + + + ACTIVE + Non sequential data byte received + 1 + + + + + RESTART + This bit controls whether a RESTART is issued before the byte is sent or received. + + 1 - If IC_RESTART_EN is 1, a RESTART is issued before the data is sent/received (according to the value of CMD), regardless of whether or not the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead. + + 0 - If IC_RESTART_EN is 1, a RESTART is issued only if the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead. + + Reset value: 0x0 + [10:10] + write-only + + + DISABLE + Don't Issue RESTART before this command + 0 + + + ENABLE + Issue RESTART before this command + 1 + + + + + STOP + This bit controls whether a STOP is issued after the byte is sent or received. + + - 1 - STOP is issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master immediately tries to start a new transfer by issuing a START and arbitrating for the bus. - 0 - STOP is not issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master continues the current transfer by sending/receiving data bytes according to the value of the CMD bit. If the Tx FIFO is empty, the master holds the SCL line low and stalls the bus until a new command is available in the Tx FIFO. Reset value: 0x0 + [9:9] + write-only + + + DISABLE + Don't Issue STOP after this command + 0 + + + ENABLE + Issue STOP after this command + 1 + + + + + CMD + This bit controls whether a read or a write is performed. This bit does not control the direction when the DW_apb_i2con acts as a slave. It controls only the direction when it acts as a master. + + When a command is entered in the TX FIFO, this bit distinguishes the write and read commands. In slave-receiver mode, this bit is a 'don't care' because writes to this register are not required. In slave-transmitter mode, a '0' indicates that the data in IC_DATA_CMD is to be transmitted. + + When programming this bit, you should remember the following: attempting to perform a read operation after a General Call command has been sent results in a TX_ABRT interrupt (bit 6 of the IC_RAW_INTR_STAT register), unless bit 11 (SPECIAL) in the IC_TAR register has been cleared. If a '1' is written to this bit after receiving a RD_REQ interrupt, then a TX_ABRT interrupt occurs. + + Reset value: 0x0 + [8:8] + write-only + + + WRITE + Master Write Command + 0 + + + READ + Master Read Command + 1 + + + + + DAT + This register contains the data to be transmitted or received on the I2C bus. If you are writing to this register and want to perform a read, bits 7:0 (DAT) are ignored by the DW_apb_i2c. However, when you read this register, these bits return the value of data received on the DW_apb_i2c interface. + + Reset value: 0x0 + [7:0] + read-write + + + + + IC_SS_SCL_HCNT + Standard Speed I2C Clock SCL High Count Register + 0x14 + 0x00000028 + + + IC_SS_SCL_HCNT + This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration'. + + This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. + + The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. + + NOTE: This register must not be programmed to a value higher than 65525, because DW_apb_i2c uses a 16-bit counter to flag an I2C bus idle condition when this counter reaches a value of IC_SS_SCL_HCNT + 10. + [15:0] + read-write + + + + + IC_SS_SCL_LCNT + Standard Speed I2C Clock SCL Low Count Register + 0x18 + 0x0000002F + + + IC_SS_SCL_LCNT + This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration' + + This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. + + The minimum valid value is 8; hardware prevents values less than this being written, and if attempted, results in 8 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of DW_apb_i2c. The lower byte must be programmed first, and then the upper byte is programmed. + [15:0] + read-write + + + + + IC_FS_SCL_HCNT + Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register + 0x1C + 0x00000006 + + + IC_FS_SCL_HCNT + This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for fast mode or fast mode plus. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'. + + This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. + + The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH == 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. + [15:0] + read-write + + + + + IC_FS_SCL_LCNT + Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register + 0x20 + 0x0000000D + + + IC_FS_SCL_LCNT + This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for fast speed. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'. + + This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard. + + This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. + + The minimum valid value is 8; hardware prevents values less than this being written, and if attempted results in 8 being set. For designs with APB_DATA_WIDTH = 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. If the value is less than 8 then the count value gets changed to 8. + [15:0] + read-write + + + + + IC_INTR_STAT + I2C Interrupt Status Register + + Each bit in this register has a corresponding mask bit in the IC_INTR_MASK register. These bits are cleared by reading the matching interrupt clear register. The unmasked raw versions of these bits are available in the IC_RAW_INTR_STAT register. + 0x2C + 0x00000000 + + + R_RESTART_DET + See IC_RAW_INTR_STAT for a detailed description of R_RESTART_DET bit. + + Reset value: 0x0 + [12:12] + read-only + + + INACTIVE + R_RESTART_DET interrupt is inactive + 0 + + + ACTIVE + R_RESTART_DET interrupt is active + 1 + + + + + R_GEN_CALL + See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL bit. + + Reset value: 0x0 + [11:11] + read-only + + + INACTIVE + R_GEN_CALL interrupt is inactive + 0 + + + ACTIVE + R_GEN_CALL interrupt is active + 1 + + + + + R_START_DET + See IC_RAW_INTR_STAT for a detailed description of R_START_DET bit. + + Reset value: 0x0 + [10:10] + read-only + + + INACTIVE + R_START_DET interrupt is inactive + 0 + + + ACTIVE + R_START_DET interrupt is active + 1 + + + + + R_STOP_DET + See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET bit. + + Reset value: 0x0 + [9:9] + read-only + + + INACTIVE + R_STOP_DET interrupt is inactive + 0 + + + ACTIVE + R_STOP_DET interrupt is active + 1 + + + + + R_ACTIVITY + See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY bit. + + Reset value: 0x0 + [8:8] + read-only + + + INACTIVE + R_ACTIVITY interrupt is inactive + 0 + + + ACTIVE + R_ACTIVITY interrupt is active + 1 + + + + + R_RX_DONE + See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE bit. + + Reset value: 0x0 + [7:7] + read-only + + + INACTIVE + R_RX_DONE interrupt is inactive + 0 + + + ACTIVE + R_RX_DONE interrupt is active + 1 + + + + + R_TX_ABRT + See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT bit. + + Reset value: 0x0 + [6:6] + read-only + + + INACTIVE + R_TX_ABRT interrupt is inactive + 0 + + + ACTIVE + R_TX_ABRT interrupt is active + 1 + + + + + R_RD_REQ + See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ bit. + + Reset value: 0x0 + [5:5] + read-only + + + INACTIVE + R_RD_REQ interrupt is inactive + 0 + + + ACTIVE + R_RD_REQ interrupt is active + 1 + + + + + R_TX_EMPTY + See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY bit. + + Reset value: 0x0 + [4:4] + read-only + + + INACTIVE + R_TX_EMPTY interrupt is inactive + 0 + + + ACTIVE + R_TX_EMPTY interrupt is active + 1 + + + + + R_TX_OVER + See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER bit. + + Reset value: 0x0 + [3:3] + read-only + + + INACTIVE + R_TX_OVER interrupt is inactive + 0 + + + ACTIVE + R_TX_OVER interrupt is active + 1 + + + + + R_RX_FULL + See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL bit. + + Reset value: 0x0 + [2:2] + read-only + + + INACTIVE + R_RX_FULL interrupt is inactive + 0 + + + ACTIVE + R_RX_FULL interrupt is active + 1 + + + + + R_RX_OVER + See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER bit. + + Reset value: 0x0 + [1:1] + read-only + + + INACTIVE + R_RX_OVER interrupt is inactive + 0 + + + ACTIVE + R_RX_OVER interrupt is active + 1 + + + + + R_RX_UNDER + See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER bit. + + Reset value: 0x0 + [0:0] + read-only + + + INACTIVE + RX_UNDER interrupt is inactive + 0 + + + ACTIVE + RX_UNDER interrupt is active + 1 + + + + + + + IC_INTR_MASK + I2C Interrupt Mask Register. + + These bits mask their corresponding interrupt status bits. This register is active low; a value of 0 masks the interrupt, whereas a value of 1 unmasks the interrupt. + 0x30 + 0x000008FF + + + M_RESTART_DET + This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register. + + Reset value: 0x0 + [12:12] + read-write + + + ENABLED + RESTART_DET interrupt is masked + 0 + + + DISABLED + RESTART_DET interrupt is unmasked + 1 + + + + + M_GEN_CALL + This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register. + + Reset value: 0x1 + [11:11] + read-write + + + ENABLED + GEN_CALL interrupt is masked + 0 + + + DISABLED + GEN_CALL interrupt is unmasked + 1 + + + + + M_START_DET + This bit masks the R_START_DET interrupt in IC_INTR_STAT register. + + Reset value: 0x0 + [10:10] + read-write + + + ENABLED + START_DET interrupt is masked + 0 + + + DISABLED + START_DET interrupt is unmasked + 1 + + + + + M_STOP_DET + This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register. + + Reset value: 0x0 + [9:9] + read-write + + + ENABLED + STOP_DET interrupt is masked + 0 + + + DISABLED + STOP_DET interrupt is unmasked + 1 + + + + + M_ACTIVITY + This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register. + + Reset value: 0x0 + [8:8] + read-write + + + ENABLED + ACTIVITY interrupt is masked + 0 + + + DISABLED + ACTIVITY interrupt is unmasked + 1 + + + + + M_RX_DONE + This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register. + + Reset value: 0x1 + [7:7] + read-write + + + ENABLED + RX_DONE interrupt is masked + 0 + + + DISABLED + RX_DONE interrupt is unmasked + 1 + + + + + M_TX_ABRT + This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register. + + Reset value: 0x1 + [6:6] + read-write + + + ENABLED + TX_ABORT interrupt is masked + 0 + + + DISABLED + TX_ABORT interrupt is unmasked + 1 + + + + + M_RD_REQ + This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register. + + Reset value: 0x1 + [5:5] + read-write + + + ENABLED + RD_REQ interrupt is masked + 0 + + + DISABLED + RD_REQ interrupt is unmasked + 1 + + + + + M_TX_EMPTY + This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register. + + Reset value: 0x1 + [4:4] + read-write + + + ENABLED + TX_EMPTY interrupt is masked + 0 + + + DISABLED + TX_EMPTY interrupt is unmasked + 1 + + + + + M_TX_OVER + This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register. + + Reset value: 0x1 + [3:3] + read-write + + + ENABLED + TX_OVER interrupt is masked + 0 + + + DISABLED + TX_OVER interrupt is unmasked + 1 + + + + + M_RX_FULL + This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register. + + Reset value: 0x1 + [2:2] + read-write + + + ENABLED + RX_FULL interrupt is masked + 0 + + + DISABLED + RX_FULL interrupt is unmasked + 1 + + + + + M_RX_OVER + This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register. + + Reset value: 0x1 + [1:1] + read-write + + + ENABLED + RX_OVER interrupt is masked + 0 + + + DISABLED + RX_OVER interrupt is unmasked + 1 + + + + + M_RX_UNDER + This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register. + + Reset value: 0x1 + [0:0] + read-write + + + ENABLED + RX_UNDER interrupt is masked + 0 + + + DISABLED + RX_UNDER interrupt is unmasked + 1 + + + + + + + IC_RAW_INTR_STAT + I2C Raw Interrupt Status Register + + Unlike the IC_INTR_STAT register, these bits are not masked so they always show the true status of the DW_apb_i2c. + 0x34 + 0x00000000 + + + RESTART_DET + Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in Slave mode and the slave is being addressed. Enabled only when IC_SLV_RESTART_DET_EN=1. + + Note: However, in high-speed mode or during a START BYTE transfer, the RESTART comes before the address field as per the I2C protocol. In this case, the slave is not the addressed slave when the RESTART is issued, therefore DW_apb_i2c does not generate the RESTART_DET interrupt. + + Reset value: 0x0 + [12:12] + read-only + + + INACTIVE + RESTART_DET interrupt is inactive + 0 + + + ACTIVE + RESTART_DET interrupt is active + 1 + + + + + GEN_CALL + Set only when a General Call address is received and it is acknowledged. It stays set until it is cleared either by disabling DW_apb_i2c or when the CPU reads bit 0 of the IC_CLR_GEN_CALL register. DW_apb_i2c stores the received data in the Rx buffer. + + Reset value: 0x0 + [11:11] + read-only + + + INACTIVE + GEN_CALL interrupt is inactive + 0 + + + ACTIVE + GEN_CALL interrupt is active + 1 + + + + + START_DET + Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode. + + Reset value: 0x0 + [10:10] + read-only + + + INACTIVE + START_DET interrupt is inactive + 0 + + + ACTIVE + START_DET interrupt is active + 1 + + + + + STOP_DET + Indicates whether a STOP condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode. + + In Slave Mode: - If IC_CON[7]=1'b1 (STOP_DET_IFADDRESSED), the STOP_DET interrupt will be issued only if slave is addressed. Note: During a general call address, this slave does not issue a STOP_DET interrupt if STOP_DET_IF_ADDRESSED=1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR). - If IC_CON[7]=1'b0 (STOP_DET_IFADDRESSED), the STOP_DET interrupt is issued irrespective of whether it is being addressed. In Master Mode: - If IC_CON[10]=1'b1 (STOP_DET_IF_MASTER_ACTIVE),the STOP_DET interrupt will be issued only if Master is active. - If IC_CON[10]=1'b0 (STOP_DET_IFADDRESSED),the STOP_DET interrupt will be issued irrespective of whether master is active or not. Reset value: 0x0 + [9:9] + read-only + + + INACTIVE + STOP_DET interrupt is inactive + 0 + + + ACTIVE + STOP_DET interrupt is active + 1 + + + + + ACTIVITY + This bit captures DW_apb_i2c activity and stays set until it is cleared. There are four ways to clear it: - Disabling the DW_apb_i2c - Reading the IC_CLR_ACTIVITY register - Reading the IC_CLR_INTR register - System reset Once this bit is set, it stays set unless one of the four methods is used to clear it. Even if the DW_apb_i2c module is idle, this bit remains set until cleared, indicating that there was activity on the bus. + + Reset value: 0x0 + [8:8] + read-only + + + INACTIVE + RAW_INTR_ACTIVITY interrupt is inactive + 0 + + + ACTIVE + RAW_INTR_ACTIVITY interrupt is active + 1 + + + + + RX_DONE + When the DW_apb_i2c is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte. This occurs on the last byte of the transmission, indicating that the transmission is done. + + Reset value: 0x0 + [7:7] + read-only + + + INACTIVE + RX_DONE interrupt is inactive + 0 + + + ACTIVE + RX_DONE interrupt is active + 1 + + + + + TX_ABRT + This bit indicates if DW_apb_i2c, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO. This situation can occur both as an I2C master or an I2C slave, and is referred to as a 'transmit abort'. When this bit is set to 1, the IC_TX_ABRT_SOURCE register indicates the reason why the transmit abort takes places. + + Note: The DW_apb_i2c flushes/resets/empties the TX_FIFO and RX_FIFO whenever there is a transmit abort caused by any of the events tracked by the IC_TX_ABRT_SOURCE register. The FIFOs remains in this flushed state until the register IC_CLR_TX_ABRT is read. Once this read is performed, the Tx FIFO is then ready to accept more data bytes from the APB interface. + + Reset value: 0x0 + [6:6] + read-only + + + INACTIVE + TX_ABRT interrupt is inactive + 0 + + + ACTIVE + TX_ABRT interrupt is active + 1 + + + + + RD_REQ + This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C master is attempting to read data from DW_apb_i2c. The DW_apb_i2c holds the I2C bus in a wait state (SCL=0) until this interrupt is serviced, which means that the slave has been addressed by a remote master that is asking for data to be transferred. The processor must respond to this interrupt and then write the requested data to the IC_DATA_CMD register. This bit is set to 0 just after the processor reads the IC_CLR_RD_REQ register. + + Reset value: 0x0 + [5:5] + read-only + + + INACTIVE + RD_REQ interrupt is inactive + 0 + + + ACTIVE + RD_REQ interrupt is active + 1 + + + + + TX_EMPTY + The behavior of the TX_EMPTY interrupt status differs based on the TX_EMPTY_CTRL selection in the IC_CON register. - When TX_EMPTY_CTRL = 0: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register. - When TX_EMPTY_CTRL = 1: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register and the transmission of the address/data from the internal shift register for the most recently popped command is completed. It is automatically cleared by hardware when the buffer level goes above the threshold. When IC_ENABLE[0] is set to 0, the TX FIFO is flushed and held in reset. There the TX FIFO looks like it has no data within it, so this bit is set to 1, provided there is activity in the master or slave state machines. When there is no longer any activity, then with ic_en=0, this bit is set to 0. + + Reset value: 0x0. + [4:4] + read-only + + + INACTIVE + TX_EMPTY interrupt is inactive + 0 + + + ACTIVE + TX_EMPTY interrupt is active + 1 + + + + + TX_OVER + Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register. When the module is disabled, this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. + + Reset value: 0x0 + [3:3] + read-only + + + INACTIVE + TX_OVER interrupt is inactive + 0 + + + ACTIVE + TX_OVER interrupt is active + 1 + + + + + RX_FULL + Set when the receive buffer reaches or goes above the RX_TL threshold in the IC_RX_TL register. It is automatically cleared by hardware when buffer level goes below the threshold. If the module is disabled (IC_ENABLE[0]=0), the RX FIFO is flushed and held in reset; therefore the RX FIFO is not full. So this bit is cleared once the IC_ENABLE bit 0 is programmed with a 0, regardless of the activity that continues. + + Reset value: 0x0 + [2:2] + read-only + + + INACTIVE + RX_FULL interrupt is inactive + 0 + + + ACTIVE + RX_FULL interrupt is active + 1 + + + + + RX_OVER + Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an additional byte is received from an external I2C device. The DW_apb_i2c acknowledges this, but any data bytes received after the FIFO is full are lost. If the module is disabled (IC_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. + + Note: If bit 9 of the IC_CON register (RX_FIFO_FULL_HLD_CTRL) is programmed to HIGH, then the RX_OVER interrupt never occurs, because the Rx FIFO never overflows. + + Reset value: 0x0 + [1:1] + read-only + + + INACTIVE + RX_OVER interrupt is inactive + 0 + + + ACTIVE + RX_OVER interrupt is active + 1 + + + + + RX_UNDER + Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register. If the module is disabled (IC_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. + + Reset value: 0x0 + [0:0] + read-only + + + INACTIVE + RX_UNDER interrupt is inactive + 0 + + + ACTIVE + RX_UNDER interrupt is active + 1 + + + + + + + IC_RX_TL + I2C Receive FIFO Threshold Register + 0x38 + 0x00000000 + + + RX_TL + Receive FIFO Threshold Level. + + Controls the level of entries (or above) that triggers the RX_FULL interrupt (bit 2 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that hardware does not allow this value to be set to a value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 1 entry, and a value of 255 sets the threshold for 256 entries. + [7:0] + read-write + + + + + IC_TX_TL + I2C Transmit FIFO Threshold Register + 0x3C + 0x00000000 + + + TX_TL + Transmit FIFO Threshold Level. + + Controls the level of entries (or below) that trigger the TX_EMPTY interrupt (bit 4 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that it may not be set to value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 0 entries, and a value of 255 sets the threshold for 255 entries. + [7:0] + read-write + + + + + IC_CLR_INTR + Clear Combined and Individual Interrupt Register + 0x40 + 0x00000000 + + + CLR_INTR + Read this register to clear the combined interrupt, all individual interrupts, and the IC_TX_ABRT_SOURCE register. This bit does not clear hardware clearable interrupts but software clearable interrupts. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE. + + Reset value: 0x0 + [0:0] + read-only + + + + + IC_CLR_RX_UNDER + Clear RX_UNDER Interrupt Register + 0x44 + 0x00000000 + + + CLR_RX_UNDER + Read this register to clear the RX_UNDER interrupt (bit 0) of the IC_RAW_INTR_STAT register. + + Reset value: 0x0 + [0:0] + read-only + + + + + IC_CLR_RX_OVER + Clear RX_OVER Interrupt Register + 0x48 + 0x00000000 + + + CLR_RX_OVER + Read this register to clear the RX_OVER interrupt (bit 1) of the IC_RAW_INTR_STAT register. + + Reset value: 0x0 + [0:0] + read-only + + + + + IC_CLR_TX_OVER + Clear TX_OVER Interrupt Register + 0x4C + 0x00000000 + + + CLR_TX_OVER + Read this register to clear the TX_OVER interrupt (bit 3) of the IC_RAW_INTR_STAT register. + + Reset value: 0x0 + [0:0] + read-only + + + + + IC_CLR_RD_REQ + Clear RD_REQ Interrupt Register + 0x50 0x00000000 - INTR - Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR, INTS0 or INTS1.\n\n - Channel interrupts can be routed to either of two system-level IRQs based on INTE0 and INTE1.\n\n - This can be used vector different channel interrupts to different ISRs: this might be done to allow NVIC IRQ preemption for more time-critical channels, or to spread IRQ load across different cores.\n\n - It is also valid to ignore this behaviour and just use INTE0/INTS0/IRQ 0. - [15:0] - read-write - oneToClear + CLR_RD_REQ + Read this register to clear the RD_REQ interrupt (bit 5) of the IC_RAW_INTR_STAT register. + + Reset value: 0x0 + [0:0] + read-only - INTE0 - Interrupt Enables for IRQ 0 - 0x404 + IC_CLR_TX_ABRT + Clear TX_ABRT Interrupt Register + 0x54 0x00000000 - INTE0 - Set bit n to pass interrupts from channel n to DMA IRQ 0. - [15:0] - read-write + CLR_TX_ABRT + Read this register to clear the TX_ABRT interrupt (bit 6) of the IC_RAW_INTR_STAT register, and the IC_TX_ABRT_SOURCE register. This also releases the TX FIFO from the flushed/reset state, allowing more writes to the TX FIFO. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE. + + Reset value: 0x0 + [0:0] + read-only - INTF0 - Force Interrupts - 0x408 + IC_CLR_RX_DONE + Clear RX_DONE Interrupt Register + 0x58 0x00000000 - INTF0 - Write 1s to force the corresponding bits in INTE0. The interrupt remains asserted until INTF0 is cleared. - [15:0] - read-write + CLR_RX_DONE + Read this register to clear the RX_DONE interrupt (bit 7) of the IC_RAW_INTR_STAT register. + + Reset value: 0x0 + [0:0] + read-only - INTS0 - Interrupt Status for IRQ 0 - 0x40C + IC_CLR_ACTIVITY + Clear ACTIVITY Interrupt Register + 0x5C 0x00000000 - INTS0 - Indicates active channel interrupt requests which are currently causing IRQ 0 to be asserted.\n - Channel interrupts can be cleared by writing a bit mask here. - [15:0] + CLR_ACTIVITY + Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore. If the I2C module is still active on the bus, the ACTIVITY interrupt bit continues to be set. It is automatically cleared by hardware if the module is disabled and if there is no further activity on the bus. The value read from this register to get status of the ACTIVITY interrupt (bit 8) of the IC_RAW_INTR_STAT register. + + Reset value: 0x0 + [0:0] + read-only + + + + + IC_CLR_STOP_DET + Clear STOP_DET Interrupt Register + 0x60 + 0x00000000 + + + CLR_STOP_DET + Read this register to clear the STOP_DET interrupt (bit 9) of the IC_RAW_INTR_STAT register. + + Reset value: 0x0 + [0:0] + read-only + + + + + IC_CLR_START_DET + Clear START_DET Interrupt Register + 0x64 + 0x00000000 + + + CLR_START_DET + Read this register to clear the START_DET interrupt (bit 10) of the IC_RAW_INTR_STAT register. + + Reset value: 0x0 + [0:0] + read-only + + + + + IC_CLR_GEN_CALL + Clear GEN_CALL Interrupt Register + 0x68 + 0x00000000 + + + CLR_GEN_CALL + Read this register to clear the GEN_CALL interrupt (bit 11) of IC_RAW_INTR_STAT register. + + Reset value: 0x0 + [0:0] + read-only + + + + + IC_ENABLE + I2C Enable Register + 0x6C + 0x00000000 + + + TX_CMD_BLOCK + In Master mode: - 1'b1: Blocks the transmission of data on I2C bus even if Tx FIFO has data to transmit. - 1'b0: The transmission of data starts on I2C bus automatically, as soon as the first data is available in the Tx FIFO. Note: To block the execution of Master commands, set the TX_CMD_BLOCK bit only when Tx FIFO is empty (IC_STATUS[2]==1) and Master is in Idle state (IC_STATUS[5] == 0). Any further commands put in the Tx FIFO are not executed until TX_CMD_BLOCK bit is unset. Reset value: IC_TX_CMD_BLOCK_DEFAULT + [2:2] read-write - oneToClear + + + NOT_BLOCKED + Tx Command execution not blocked + 0 + + + BLOCKED + Tx Command execution blocked + 1 + + + + + ABORT + When set, the controller initiates the transfer abort. - 0: ABORT not initiated or ABORT done - 1: ABORT operation in progress The software can abort the I2C transfer in master mode by setting this bit. The software can set this bit only when ENABLE is already set; otherwise, the controller ignores any write to ABORT bit. The software cannot clear the ABORT bit once set. In response to an ABORT, the controller issues a STOP and flushes the Tx FIFO after completing the current transfer, then sets the TX_ABORT interrupt after the abort operation. The ABORT bit is cleared automatically after the abort operation. + + For a detailed description on how to abort I2C transfers, refer to 'Aborting I2C Transfers'. + + Reset value: 0x0 + [1:1] + read-write + + + DISABLE + ABORT operation not in progress + 0 + + + ENABLED + ABORT operation in progress + 1 + + + + + ENABLE + Controls whether the DW_apb_i2c is enabled. - 0: Disables DW_apb_i2c (TX and RX FIFOs are held in an erased state) - 1: Enables DW_apb_i2c Software can disable DW_apb_i2c while it is active. However, it is important that care be taken to ensure that DW_apb_i2c is disabled properly. A recommended procedure is described in 'Disabling DW_apb_i2c'. + + When DW_apb_i2c is disabled, the following occurs: - The TX FIFO and RX FIFO get flushed. - Status bits in the IC_INTR_STAT register are still active until DW_apb_i2c goes into IDLE state. If the module is transmitting, it stops as well as deletes the contents of the transmit buffer after the current transfer is complete. If the module is receiving, the DW_apb_i2c stops the current transfer at the end of the current byte and does not acknowledge the transfer. + + In systems with asynchronous pclk and ic_clk when IC_CLK_TYPE parameter set to asynchronous (1), there is a two ic_clk delay when enabling or disabling the DW_apb_i2c. For a detailed description on how to disable DW_apb_i2c, refer to 'Disabling DW_apb_i2c' + + Reset value: 0x0 + [0:0] + read-write + + + DISABLED + I2C is disabled + 0 + + + ENABLED + I2C is enabled + 1 + + + + + + + IC_STATUS + I2C Status Register + + This is a read-only register used to indicate the current transfer status and FIFO status. The status register may be read at any time. None of the bits in this register request an interrupt. + + When the I2C is disabled by writing 0 in bit 0 of the IC_ENABLE register: - Bits 1 and 2 are set to 1 - Bits 3 and 10 are set to 0 When the master or slave state machines goes to idle and ic_en=0: - Bits 5 and 6 are set to 0 + 0x70 + 0x00000006 + + + SLV_ACTIVITY + Slave FSM Activity Status. When the Slave Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Slave FSM is in IDLE state so the Slave part of DW_apb_i2c is not Active - 1: Slave FSM is not in IDLE state so the Slave part of DW_apb_i2c is Active Reset value: 0x0 + [6:6] + read-only + + + IDLE + Slave is idle + 0 + + + ACTIVE + Slave not idle + 1 + + + + + MST_ACTIVITY + Master FSM Activity Status. When the Master Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Master FSM is in IDLE state so the Master part of DW_apb_i2c is not Active - 1: Master FSM is not in IDLE state so the Master part of DW_apb_i2c is Active Note: IC_STATUS[0]-that is, ACTIVITY bit-is the OR of SLV_ACTIVITY and MST_ACTIVITY bits. + + Reset value: 0x0 + [5:5] + read-only + + + IDLE + Master is idle + 0 + + + ACTIVE + Master not idle + 1 + + + + + RFF + Receive FIFO Completely Full. When the receive FIFO is completely full, this bit is set. When the receive FIFO contains one or more empty location, this bit is cleared. - 0: Receive FIFO is not full - 1: Receive FIFO is full Reset value: 0x0 + [4:4] + read-only + + + NOT_FULL + Rx FIFO not full + 0 + + + FULL + Rx FIFO is full + 1 + + + + + RFNE + Receive FIFO Not Empty. This bit is set when the receive FIFO contains one or more entries; it is cleared when the receive FIFO is empty. - 0: Receive FIFO is empty - 1: Receive FIFO is not empty Reset value: 0x0 + [3:3] + read-only + + + EMPTY + Rx FIFO is empty + 0 + + + NOT_EMPTY + Rx FIFO not empty + 1 + + + + + TFE + Transmit FIFO Completely Empty. When the transmit FIFO is completely empty, this bit is set. When it contains one or more valid entries, this bit is cleared. This bit field does not request an interrupt. - 0: Transmit FIFO is not empty - 1: Transmit FIFO is empty Reset value: 0x1 + [2:2] + read-only + + + NON_EMPTY + Tx FIFO not empty + 0 + + + EMPTY + Tx FIFO is empty + 1 + + + + + TFNF + Transmit FIFO Not Full. Set when the transmit FIFO contains one or more empty locations, and is cleared when the FIFO is full. - 0: Transmit FIFO is full - 1: Transmit FIFO is not full Reset value: 0x1 + [1:1] + read-only + + + FULL + Tx FIFO is full + 0 + + + NOT_FULL + Tx FIFO not full + 1 + + - - - - INTE1 - Interrupt Enables for IRQ 1 - 0x414 - 0x00000000 - - INTE1 - Set bit n to pass interrupts from channel n to DMA IRQ 1. - [15:0] - read-write + ACTIVITY + I2C Activity Status. Reset value: 0x0 + [0:0] + read-only + + + INACTIVE + I2C is idle + 0 + + + ACTIVE + I2C is active + 1 + + - INTF1 - Force Interrupts for IRQ 1 - 0x418 + IC_TXFLR + I2C Transmit FIFO Level Register This register contains the number of valid data entries in the transmit FIFO buffer. It is cleared whenever: - The I2C is disabled - There is a transmit abort - that is, TX_ABRT bit is set in the IC_RAW_INTR_STAT register - The slave bulk transmit mode is aborted The register increments whenever data is placed into the transmit FIFO and decrements when data is taken from the transmit FIFO. + 0x74 0x00000000 - INTF1 - Write 1s to force the corresponding bits in INTE0. The interrupt remains asserted until INTF0 is cleared. - [15:0] - read-write + TXFLR + Transmit FIFO Level. Contains the number of valid data entries in the transmit FIFO. + + Reset value: 0x0 + [4:0] + read-only - INTS1 - Interrupt Status (masked) for IRQ 1 - 0x41C + IC_RXFLR + I2C Receive FIFO Level Register This register contains the number of valid data entries in the receive FIFO buffer. It is cleared whenever: - The I2C is disabled - Whenever there is a transmit abort caused by any of the events tracked in IC_TX_ABRT_SOURCE The register increments whenever data is placed into the receive FIFO and decrements when data is taken from the receive FIFO. + 0x78 0x00000000 - INTS1 - Indicates active channel interrupt requests which are currently causing IRQ 1 to be asserted.\n - Channel interrupts can be cleared by writing a bit mask here. - [15:0] - read-write - oneToClear + RXFLR + Receive FIFO Level. Contains the number of valid data entries in the receive FIFO. + + Reset value: 0x0 + [4:0] + read-only - TIMER0 - Pacing (X/Y) Fractional Timer\n - The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. - 0x420 - 0x00000000 + IC_SDA_HOLD + I2C SDA Hold Time Length Register + + The bits [15:0] of this register are used to control the hold time of SDA during transmit in both slave and master mode (after SCL goes from HIGH to LOW). + + The bits [23:16] of this register are used to extend the SDA transition (if any) whenever SCL is HIGH in the receiver in either master or slave mode. + + Writes to this register succeed only when IC_ENABLE[0]=0. + + The values in this register are in units of ic_clk period. The value programmed in IC_SDA_TX_HOLD must be greater than the minimum hold time in each mode (one cycle in master mode, seven cycles in slave mode) for the value to be implemented. + + The programmed SDA hold time during transmit (IC_SDA_TX_HOLD) cannot exceed at any time the duration of the low part of scl. Therefore the programmed value cannot be larger than N_SCL_LOW-2, where N_SCL_LOW is the duration of the low part of the scl period measured in ic_clk cycles. + 0x7C + 0x00000001 - X - Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. - [31:16] + IC_SDA_RX_HOLD + Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a receiver. + + Reset value: IC_DEFAULT_SDA_HOLD[23:16]. + [23:16] read-write - Y - Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. + IC_SDA_TX_HOLD + Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a transmitter. + + Reset value: IC_DEFAULT_SDA_HOLD[15:0]. [15:0] read-write - TIMER1 - Pacing (X/Y) Fractional Timer\n - The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. - 0x424 + IC_TX_ABRT_SOURCE + I2C Transmit Abort Source Register + + This register has 32 bits that indicate the source of the TX_ABRT bit. Except for Bit 9, this register is cleared whenever the IC_CLR_TX_ABRT register or the IC_CLR_INTR register is read. To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; RESTART must be enabled (IC_CON[5]=1), the SPECIAL bit must be cleared (IC_TAR[11]), or the GC_OR_START bit must be cleared (IC_TAR[10]). + + Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, Bit 9 clears for one cycle and is then re-asserted. + 0x80 0x00000000 - X - Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. - [31:16] - read-write - - - Y - Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. - [15:0] - read-write + TX_FLUSH_CNT + This field indicates the number of Tx FIFO Data Commands which are flushed due to TX_ABRT interrupt. It is cleared whenever I2C is disabled. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter + [31:23] + read-only - - - - TIMER2 - Pacing (X/Y) Fractional Timer\n - The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. - 0x428 - 0x00000000 - - X - Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. - [31:16] - read-write + ABRT_USER_ABRT + This is a master-mode-only bit. Master has detected the transfer abort (IC_ENABLE[1]) + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter + [16:16] + read-only + + + ABRT_USER_ABRT_VOID + Transfer abort detected by master- scenario not present + 0 + + + ABRT_USER_ABRT_GENERATED + Transfer abort detected by master + 1 + + - Y - Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. - [15:0] - read-write + ABRT_SLVRD_INTX + 1: When the processor side responds to a slave mode request for data to be transmitted to a remote master and user writes a 1 in CMD (bit 8) of IC_DATA_CMD register. + + Reset value: 0x0 + + Role of DW_apb_i2c: Slave-Transmitter + [15:15] + read-only + + + ABRT_SLVRD_INTX_VOID + Slave trying to transmit to remote master in read mode- scenario not present + 0 + + + ABRT_SLVRD_INTX_GENERATED + Slave trying to transmit to remote master in read mode + 1 + + - - - - TIMER3 - Pacing (X/Y) Fractional Timer\n - The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. - 0x42C - 0x00000000 - - X - Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. - [31:16] - read-write + ABRT_SLV_ARBLOST + This field indicates that a Slave has lost the bus while transmitting data to a remote master. IC_TX_ABRT_SOURCE[12] is set at the same time. Note: Even though the slave never 'owns' the bus, something could go wrong on the bus. This is a fail safe check. For instance, during a data transmission at the low-to-high transition of SCL, if what is on the data bus is not what is supposed to be transmitted, then DW_apb_i2c no longer own the bus. + + Reset value: 0x0 + + Role of DW_apb_i2c: Slave-Transmitter + [14:14] + read-only + + + ABRT_SLV_ARBLOST_VOID + Slave lost arbitration to remote master- scenario not present + 0 + + + ABRT_SLV_ARBLOST_GENERATED + Slave lost arbitration to remote master + 1 + + - Y - Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. - [15:0] - read-write + ABRT_SLVFLUSH_TXFIFO + This field specifies that the Slave has received a read command and some data exists in the TX FIFO, so the slave issues a TX_ABRT interrupt to flush old data in TX FIFO. + + Reset value: 0x0 + + Role of DW_apb_i2c: Slave-Transmitter + [13:13] + read-only + + + ABRT_SLVFLUSH_TXFIFO_VOID + Slave flushes existing data in TX-FIFO upon getting read command- scenario not present + 0 + + + ABRT_SLVFLUSH_TXFIFO_GENERATED + Slave flushes existing data in TX-FIFO upon getting read command + 1 + + - - - - MULTI_CHAN_TRIGGER - Trigger one or more channels simultaneously - 0x430 - 0x00000000 - - MULTI_CHAN_TRIGGER - Each bit in this register corresponds to a DMA channel. Writing a 1 to the relevant bit is the same as writing to that channel's trigger register; the channel will start if it is currently enabled and not already busy. - [15:0] - read-write - clear + ARB_LOST + This field specifies that the Master has lost arbitration, or if IC_TX_ABRT_SOURCE[14] is also set, then the slave transmitter has lost arbitration. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter + [12:12] + read-only + + + ABRT_LOST_VOID + Master or Slave-Transmitter lost arbitration- scenario not present + 0 + + + ABRT_LOST_GENERATED + Master or Slave-Transmitter lost arbitration + 1 + + - - - - SNIFF_CTRL - Sniffer Control - 0x434 - 0x00000000 - - OUT_INV - If set, the result appears inverted (bitwise complement) when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus. + ABRT_MASTER_DIS + This field indicates that the User tries to initiate a Master operation with the Master mode disabled. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter or Master-Receiver [11:11] - read-write + read-only + + + ABRT_MASTER_DIS_VOID + User initiating master operation when MASTER disabled- scenario not present + 0 + + + ABRT_MASTER_DIS_GENERATED + User initiating master operation when MASTER disabled + 1 + + - OUT_REV - If set, the result appears bit-reversed when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus. + ABRT_10B_RD_NORSTRT + This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the master sends a read command in 10-bit addressing mode. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Receiver [10:10] - read-write + read-only + + + ABRT_10B_RD_VOID + Master not trying to read in 10Bit addressing mode when RESTART disabled + 0 + + + ABRT_10B_RD_GENERATED + Master trying to read in 10Bit addressing mode when RESTART disabled + 1 + + - BSWAP - Locally perform a byte reverse on the sniffed data, before feeding into checksum.\n\n - Note that the sniff hardware is downstream of the DMA channel byteswap performed in the read master: if channel CTRL_BSWAP and SNIFF_CTRL_BSWAP are both enabled, their effects cancel from the sniffer's point of view. + ABRT_SBYTE_NORSTRT + To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; restart must be enabled (IC_CON[5]=1), the SPECIAL bit must be cleared (IC_TAR[11]), or the GC_OR_START bit must be cleared (IC_TAR[10]). Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, bit 9 clears for one cycle and then gets reasserted. When this field is set to 1, the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to send a START Byte. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master [9:9] - read-write - - - CALC - [8:5] - read-write + read-only - CRC32 - Calculate a CRC-32 (IEEE802.3 polynomial) + ABRT_SBYTE_NORSTRT_VOID + User trying to send START byte when RESTART disabled- scenario not present 0 - CRC32R - Calculate a CRC-32 (IEEE802.3 polynomial) with bit reversed data + ABRT_SBYTE_NORSTRT_GENERATED + User trying to send START byte when RESTART disabled 1 + + + + ABRT_HS_NORSTRT + This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to use the master to transfer data in High Speed mode. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter or Master-Receiver + [8:8] + read-only + - CRC16 - Calculate a CRC-16-CCITT - 2 + ABRT_HS_NORSTRT_VOID + User trying to switch Master to HS mode when RESTART disabled- scenario not present + 0 - CRC16R - Calculate a CRC-16-CCITT with bit reversed data - 3 + ABRT_HS_NORSTRT_GENERATED + User trying to switch Master to HS mode when RESTART disabled + 1 + + + + ABRT_SBYTE_ACKDET + This field indicates that the Master has sent a START Byte and the START Byte was acknowledged (wrong behavior). + + Reset value: 0x0 + + Role of DW_apb_i2c: Master + [7:7] + read-only + - EVEN - XOR reduction over all data. == 1 if the total 1 population count is odd. - 14 + ABRT_SBYTE_ACKDET_VOID + ACK detected for START byte- scenario not present + 0 - SUM - Calculate a simple 32-bit checksum (addition with a 32 bit accumulator) - 15 + ABRT_SBYTE_ACKDET_GENERATED + ACK detected for START byte + 1 - DMACH - DMA channel for Sniffer to observe - [4:1] - read-write - - - EN - Enable sniffer - [0:0] - read-write - - - - - SNIFF_DATA - Data accumulator for sniff hardware\n - Write an initial seed value here before starting a DMA transfer on the channel indicated by SNIFF_CTRL_DMACH. The hardware will update this register each time it observes a read from the indicated channel. Once the channel completes, the final result can be read from this register. - 0x438 - read-write - 0x00000000 - - - FIFO_LEVELS - Debug RAF, WAF, TDF levels - 0x440 - 0x00000000 - - - RAF_LVL - Current Read-Address-FIFO fill level - [23:16] - read-only - - - WAF_LVL - Current Write-Address-FIFO fill level - [15:8] + ABRT_HS_ACKDET + This field indicates that the Master is in High Speed mode and the High Speed Master code was acknowledged (wrong behavior). + + Reset value: 0x0 + + Role of DW_apb_i2c: Master + [6:6] read-only + + + ABRT_HS_ACK_VOID + HS Master code ACKed in HS Mode- scenario not present + 0 + + + ABRT_HS_ACK_GENERATED + HS Master code ACKed in HS Mode + 1 + + - TDF_LVL - Current Transfer-Data-FIFO fill level - [7:0] + ABRT_GCALL_READ + This field indicates that DW_apb_i2c in the master mode has sent a General Call but the user programmed the byte following the General Call to be a read from the bus (IC_DATA_CMD[9] is set to 1). + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter + [5:5] read-only + + + ABRT_GCALL_READ_VOID + GCALL is followed by read from bus-scenario not present + 0 + + + ABRT_GCALL_READ_GENERATED + GCALL is followed by read from bus + 1 + + - - - - CHAN_ABORT - Abort an in-progress transfer sequence on one or more channels - 0x444 - 0x00000000 - - - CHAN_ABORT - Each bit corresponds to a channel. Writing a 1 aborts whatever transfer sequence is in progress on that channel. The bit will remain high until any in-flight transfers have been flushed through the address and data FIFOs.\n\n - After writing, this register must be polled until it returns all-zero. Until this point, it is unsafe to restart the channel. - [15:0] - read-write - clear - - - - - N_CHANNELS - The number of channels this DMA instance is equipped with. This DMA supports up to 16 hardware channels, but can be configured with as few as one, to minimise silicon area. - 0x448 - 0x00000000 - - N_CHANNELS - [4:0] + ABRT_GCALL_NOACK + This field indicates that DW_apb_i2c in master mode has sent a General Call and no slave on the bus acknowledged the General Call. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter + [4:4] read-only - - - - - CH0_DBG_CTDREQ - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - 0x800 - 0x00000000 - - - CH0_DBG_CTDREQ - [5:0] - read-write - oneToClear - - - - - CH0_DBG_TCR - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer - 0x804 - read-only - 0x00000000 - - - CH1_DBG_CTDREQ - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - 0x840 - 0x00000000 - - - CH1_DBG_CTDREQ - [5:0] - read-write - oneToClear - - - - - CH1_DBG_TCR - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer - 0x844 - read-only - 0x00000000 - - - CH2_DBG_CTDREQ - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - 0x880 - 0x00000000 - - - CH2_DBG_CTDREQ - [5:0] - read-write - oneToClear - - - - - CH2_DBG_TCR - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer - 0x884 - read-only - 0x00000000 - - - CH3_DBG_CTDREQ - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - 0x8C0 - 0x00000000 - - - CH3_DBG_CTDREQ - [5:0] - read-write - oneToClear - - - - - CH3_DBG_TCR - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer - 0x8C4 - read-only - 0x00000000 - - - CH4_DBG_CTDREQ - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - 0x900 - 0x00000000 - - - CH4_DBG_CTDREQ - [5:0] - read-write - oneToClear - - - - - CH4_DBG_TCR - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer - 0x904 - read-only - 0x00000000 - - - CH5_DBG_CTDREQ - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - 0x940 - 0x00000000 - + + + ABRT_GCALL_NOACK_VOID + GCALL not ACKed by any slave-scenario not present + 0 + + + ABRT_GCALL_NOACK_GENERATED + GCALL not ACKed by any slave + 1 + + + - CH5_DBG_CTDREQ - [5:0] - read-write - oneToClear + ABRT_TXDATA_NOACK + This field indicates the master-mode only bit. When the master receives an acknowledgement for the address, but when it sends data byte(s) following the address, it did not receive an acknowledge from the remote slave(s). + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter + [3:3] + read-only + + + ABRT_TXDATA_NOACK_VOID + Transmitted data non-ACKed by addressed slave-scenario not present + 0 + + + ABRT_TXDATA_NOACK_GENERATED + Transmitted data not ACKed by addressed slave + 1 + + - - - - CH5_DBG_TCR - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer - 0x944 - read-only - 0x00000000 - - - CH6_DBG_CTDREQ - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - 0x980 - 0x00000000 - - CH6_DBG_CTDREQ - [5:0] - read-write - oneToClear + ABRT_10ADDR2_NOACK + This field indicates that the Master is in 10-bit address mode and that the second address byte of the 10-bit address was not acknowledged by any slave. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter or Master-Receiver + [2:2] + read-only + + + INACTIVE + This abort is not generated + 0 + + + ACTIVE + Byte 2 of 10Bit Address not ACKed by any slave + 1 + + - - - - CH6_DBG_TCR - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer - 0x984 - read-only - 0x00000000 - - - CH7_DBG_CTDREQ - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - 0x9C0 - 0x00000000 - - CH7_DBG_CTDREQ - [5:0] - read-write - oneToClear + ABRT_10ADDR1_NOACK + This field indicates that the Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter or Master-Receiver + [1:1] + read-only + + + INACTIVE + This abort is not generated + 0 + + + ACTIVE + Byte 1 of 10Bit Address not ACKed by any slave + 1 + + - - - - CH7_DBG_TCR - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer - 0x9C4 - read-only - 0x00000000 - - - CH8_DBG_CTDREQ - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - 0xA00 - 0x00000000 - - CH8_DBG_CTDREQ - [5:0] - read-write - oneToClear + ABRT_7B_ADDR_NOACK + This field indicates that the Master is in 7-bit addressing mode and the address sent was not acknowledged by any slave. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter or Master-Receiver + [0:0] + read-only + + + INACTIVE + This abort is not generated + 0 + + + ACTIVE + This abort is generated because of NOACK for 7-bit address + 1 + + - CH8_DBG_TCR - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer - 0xA04 - read-only - 0x00000000 - - - CH9_DBG_CTDREQ - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - 0xA40 + IC_SLV_DATA_NACK_ONLY + Generate Slave Data NACK Register + + The register is used to generate a NACK for the data part of a transfer when DW_apb_i2c is acting as a slave-receiver. This register only exists when the IC_SLV_DATA_NACK_ONLY parameter is set to 1. When this parameter disabled, this register does not exist and writing to the register's address has no effect. + + A write can occur on this register if both of the following conditions are met: - DW_apb_i2c is disabled (IC_ENABLE[0] = 0) - Slave part is inactive (IC_STATUS[6] = 0) Note: The IC_STATUS[6] is a register read-back location for the internal slv_activity signal; the user should poll this before writing the ic_slv_data_nack_only bit. + 0x84 0x00000000 - CH9_DBG_CTDREQ - [5:0] + NACK + Generate NACK. This NACK generation only occurs when DW_apb_i2c is a slave-receiver. If this register is set to a value of 1, it can only generate a NACK after a data byte is received; hence, the data transfer is aborted and the data received is not pushed to the receive buffer. + + When the register is set to a value of 0, it generates NACK/ACK, depending on normal criteria. - 1: generate NACK after data byte received - 0: generate NACK/ACK normally Reset value: 0x0 + [0:0] read-write - oneToClear + + + DISABLED + Slave receiver generates NACK normally + 0 + + + ENABLED + Slave receiver generates NACK upon data reception only + 1 + + - CH9_DBG_TCR - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer - 0xA44 - read-only - 0x00000000 - - - CH10_DBG_CTDREQ - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - 0xA80 + IC_DMA_CR + DMA Control Register + + The register is used to enable the DMA Controller interface operation. There is a separate bit for transmit and receive. This can be programmed regardless of the state of IC_ENABLE. + 0x88 0x00000000 - CH10_DBG_CTDREQ - [5:0] + TDMAE + Transmit DMA Enable. This bit enables/disables the transmit FIFO DMA channel. Reset value: 0x0 + [1:1] read-write - oneToClear + + + DISABLED + transmit FIFO DMA channel disabled + 0 + + + ENABLED + Transmit FIFO DMA channel enabled + 1 + + - - - - CH10_DBG_TCR - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer - 0xA84 - read-only - 0x00000000 - - - CH11_DBG_CTDREQ - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. - 0xAC0 - 0x00000000 - - CH11_DBG_CTDREQ - [5:0] + RDMAE + Receive DMA Enable. This bit enables/disables the receive FIFO DMA channel. Reset value: 0x0 + [0:0] read-write - oneToClear + + + DISABLED + Receive FIFO DMA channel disabled + 0 + + + ENABLED + Receive FIFO DMA channel enabled + 1 + + - CH11_DBG_TCR - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer - 0xAC4 - read-only - 0x00000000 - - - - - USBCTRL_DPRAM - 1 - DPRAM layout for USB device. - 0x50100000 - 0x20 - - 0x0 - 0x100 - registers - - - - SETUP_PACKET_LOW - Bytes 0-3 of the SETUP packet from the host. - 0x0 + IC_DMA_TDLR + DMA Transmit Data Level Register + 0x8C 0x00000000 - - WVALUE - [31:16] - read-write - - - BREQUEST - [15:8] - read-write - - - BMREQUESTTYPE - [7:0] + + DMATDL + Transmit Data Level. This bit field controls the level at which a DMA request is made by the transmit logic. It is equal to the watermark level; that is, the dma_tx_req signal is generated when the number of valid data entries in the transmit FIFO is equal to or below this field value, and TDMAE = 1. + + Reset value: 0x0 + [3:0] read-write - SETUP_PACKET_HIGH - Bytes 4-7 of the setup packet from the host. - 0x4 + IC_DMA_RDLR + I2C Receive Data Level Register + 0x90 0x00000000 - WLENGTH - [31:16] - read-write - - - WINDEX - [15:0] + DMARDL + Receive Data Level. This bit field controls the level at which a DMA request is made by the receive logic. The watermark level = DMARDL+1; that is, dma_rx_req is generated when the number of valid data entries in the receive FIFO is equal to or more than this field value + 1, and RDMAE =1. For instance, when DMARDL is 0, then dma_rx_req is asserted when 1 or more data entries are present in the receive FIFO. + + Reset value: 0x0 + [3:0] read-write - 30 - 0x4 - 0-29 - EP_CONTROL%s - - - 0x8 - 0x00000000 + IC_SDA_SETUP + I2C SDA Setup Register + + This register controls the amount of time delay (in terms of number of ic_clk clock periods) introduced in the rising edge of SCL - relative to SDA changing - when DW_apb_i2c services a read request in a slave-transmitter operation. The relevant I2C requirement is tSU:DAT (note 4) as detailed in the I2C Bus Specification. This register must be programmed with a value equal to or greater than 2. + + Writes to this register succeed only when IC_ENABLE[0] = 0. + + Note: The length of setup time is calculated using [(IC_SDA_SETUP - 1) * (ic_clk_period)], so if the user requires 10 ic_clk periods of setup time, they should program a value of 11. The IC_SDA_SETUP register is only used by the DW_apb_i2c when operating as a slave transmitter. + 0x94 + 0x00000064 - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] + SDA_SETUP + SDA Setup. It is recommended that if the required delay is 1000ns, then for an ic_clk frequency of 10 MHz, IC_SDA_SETUP should be programmed to a value of 11. IC_SDA_SETUP must be programmed with a minimum value of 2. + [7:0] read-write + + + + IC_ACK_GENERAL_CALL + I2C ACK General Call Register + + The register controls whether DW_apb_i2c responds with a ACK or NACK when it receives an I2C General Call address. + + This register is applicable only when the DW_apb_i2c is in slave mode. + 0x98 + 0x00000001 + - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] + ACK_GEN_CALL + ACK General Call. When set to 1, DW_apb_i2c responds with a ACK (by asserting ic_data_oe) when it receives a General Call. Otherwise, DW_apb_i2c responds with a NACK (by negating ic_data_oe). + [0:0] read-write + + + DISABLED + Generate NACK for a General Call + 0 + + + ENABLED + Generate ACK for a General Call + 1 + + + + + + IC_ENABLE_STATUS + I2C Enable Status Register + + The register is used to report the DW_apb_i2c hardware status when the IC_ENABLE[0] register is set from 1 to 0; that is, when DW_apb_i2c is disabled. + + If IC_ENABLE[0] has been set to 1, bits 2:1 are forced to 0, and bit 0 is forced to 1. + + If IC_ENABLE[0] has been set to 0, bits 2:1 is only be valid as soon as bit 0 is read as '0'. + + Note: When IC_ENABLE[0] has been set to 0, a delay occurs for bit 0 to be read as 0 because disabling the DW_apb_i2c depends on I2C bus activities. + 0x9C + 0x00000000 + - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] - read-write + SLV_RX_DATA_LOST + Slave Received Data Lost. This bit indicates if a Slave-Receiver operation has been aborted with at least one data byte received from an I2C transfer due to the setting bit 0 of IC_ENABLE from 1 to 0. When read as 1, DW_apb_i2c is deemed to have been actively engaged in an aborted I2C transfer (with matching address) and the data phase of the I2C transfer has been entered, even though a data byte has been responded with a NACK. + + Note: If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE[0] has been set to 0, then this bit is also set to 1. + + When read as 0, DW_apb_i2c is deemed to have been disabled without being actively involved in the data phase of a Slave-Receiver transfer. + + Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0. + + Reset value: 0x0 + [2:2] + read-only + + + INACTIVE + Slave RX Data is not lost + 0 + + + ACTIVE + Slave RX Data is lost + 1 + + - ENDPOINT_TYPE - [27:26] - read-write + SLV_DISABLED_WHILE_BUSY + Slave Disabled While Busy (Transmit, Receive). This bit indicates if a potential or active Slave operation has been aborted due to the setting bit 0 of the IC_ENABLE register from 1 to 0. This bit is set when the CPU writes a 0 to the IC_ENABLE register while: + + (a) DW_apb_i2c is receiving the address byte of the Slave-Transmitter operation from a remote master; + + OR, + + (b) address and data bytes of the Slave-Receiver operation from a remote master. + + When read as 1, DW_apb_i2c is deemed to have forced a NACK during any part of an I2C transfer, irrespective of whether the I2C address matches the slave address set in DW_apb_i2c (IC_SAR register) OR if the transfer is completed before IC_ENABLE is set to 0 but has not taken effect. + + Note: If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE[0] has been set to 0, then this bit will also be set to 1. + + When read as 0, DW_apb_i2c is deemed to have been disabled when there is master activity, or when the I2C bus is idle. + + Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0. + + Reset value: 0x0 + [1:1] + read-only - Control + INACTIVE + Slave is disabled when it is idle 0 - Isochronous + ACTIVE + Slave is disabled when it is active 1 + + + + IC_EN + ic_en Status. This bit always reflects the value driven on the output port ic_en. - When read as 1, DW_apb_i2c is deemed to be in an enabled state. - When read as 0, DW_apb_i2c is deemed completely inactive. Note: The CPU can safely read this bit anytime. When this bit is read as 0, the CPU can safely read SLV_RX_DATA_LOST (bit 2) and SLV_DISABLED_WHILE_BUSY (bit 1). + + Reset value: 0x0 + [0:0] + read-only + - Bulk - 2 + DISABLED + I2C disabled + 0 - Interrupt - 3 + ENABLED + I2C enabled + 1 + + + + IC_FS_SPKLEN + I2C SS, FS or FM+ spike suppression limit + + This register is used to store the duration, measured in ic_clk cycles, of the longest spike that is filtered out by the spike suppression logic when the component is operating in SS, FS or FM+ modes. The relevant I2C requirement is tSP (table 4) as detailed in the I2C Bus Specification. This register must be programmed with a minimum value of 1. + 0xA0 + 0x00000007 + - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] + IC_FS_SPKLEN + This register must be set before any I2C bus transaction can take place to ensure stable operation. This register sets the duration, measured in ic_clk cycles, of the longest spike in the SCL or SDA lines that will be filtered out by the spike suppression logic. This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. The minimum valid value is 1; hardware prevents values less than this being written, and if attempted results in 1 being set. or more information, refer to 'Spike Suppression'. + [7:0] read-write + + + + IC_CLR_RESTART_DET + Clear RESTART_DET Interrupt Register + 0xA8 + 0x00000000 + - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] - read-write + CLR_RESTART_DET + Read this register to clear the RESTART_DET interrupt (bit 12) of IC_RAW_INTR_STAT register. + + Reset value: 0x0 + [0:0] + read-only + + + + IC_COMP_PARAM_1 + Component Parameter Register 1 + + Note This register is not implemented and therefore reads as 0. If it was implemented it would be a constant read-only register that contains encoded information about the component's parameter settings. Fields shown below are the settings for those parameters + 0xF4 + 0x00000000 + - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] - read-write + TX_BUFFER_DEPTH + TX Buffer Depth = 16 + [23:16] + read-only - HOST_POLL_INTERVAL - The interval the host controller should poll this endpoint. Only applicable for interrupt endpoints. Specified in ms - 1. For example: a value of 9 would poll the endpoint every 10ms. - 16 - 10 + RX_BUFFER_DEPTH + RX Buffer Depth = 16 + [15:8] + read-only + + + ADD_ENCODED_PARAMS + Encoded parameters not visible + [7:7] + read-only + + + HAS_DMA + DMA handshaking signals are enabled + [6:6] + read-only + + + INTR_IO + COMBINED Interrupt outputs + [5:5] + read-only + + + HC_COUNT_VALUES + Programmable count values for each mode. + [4:4] + read-only + + + MAX_SPEED_MODE + MAX SPEED MODE = FAST MODE + [3:2] + read-only + + + APB_DATA_WIDTH + APB data bus width is 32 bits + [1:0] + read-only + + + + + IC_COMP_VERSION + I2C Component Version Register + 0xF8 + 0x3230312A + + + IC_COMP_VERSION + [31:0] + read-only + + + + + IC_COMP_TYPE + I2C Component Type Register + 0xFC + 0x44570140 + + + IC_COMP_TYPE + Designware Component Type number = 0x44_57_01_40. This assigned unique hex value is constant and is derived from the two ASCII letters 'DW' followed by a 16-bit unsigned number. + [31:0] + read-only + + + + I2C1 + 0x40048000 + + I2C1_IRQ + 24 + + + + SPI0 + 0x4003C000 + + 0x0 + 0x1000 + registers + + + SPI0_IRQ + 18 + + - 32 - 0x4 - 0-31 - EP_BUFFER_CONTROL%s - - - 0x80 + SSPCR0 + Control register 0, SSPCR0 on page 3-4 + 0x0 0x00000000 - FULL_1 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [31:31] + SCR + Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: F SSPCLK CPSDVSR x (1+SCR) where CPSDVSR is an even value from 2-254, programmed through the SSPCPSR register and SCR is a value from 0-255. + [15:8] read-write - LAST_1 - Buffer 1 is the last buffer of the transfer. - [30:30] + SPH + SSPCLKOUT phase, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10. + [7:7] read-write - PID_1 - The data pid of buffer 1. - [29:29] + SPO + SSPCLKOUT polarity, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10. + [6:6] read-write - DOUBLE_BUFFER_ISO_OFFSET - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n - For a non Isochronous endpoint the offset is always 64 bytes. - [28:27] + FRF + Frame format. + [5:4] read-write + FRF - 128 + Motorola + Motorola SPI frame format 0 - 256 + Texas_Instruments + Texas Instruments synchronous serial frame format 1 - 512 + National_Semiconductor_Microwire + National Semiconductor Microwire frame format 2 - - 1024 - 3 - - AVAILABLE_1 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [26:26] + DSS + Data Size Select: 0000 Reserved, undefined operation. 0001 Reserved, undefined operation. 0010 Reserved, undefined operation. 0011 4-bit data. 0100 5-bit data. 0101 6-bit data. 0110 7-bit data. 0111 8-bit data. 1000 9-bit data. 1001 10-bit data. 1010 11-bit data. 1011 12-bit data. 1100 13-bit data. 1101 14-bit data. 1110 15-bit data. 1111 16-bit data. + [3:0] read-write + + + + SSPCR1 + Control register 1, SSPCR1 on page 3-5 + 0x4 + 0x00000000 + - LENGTH_1 - The length of the data in buffer 1. - [25:16] + SOD + Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line: 0 SSP can drive the SSPTXD output in slave mode. 1 SSP must not drive the SSPTXD output in slave mode. + [3:3] read-write - FULL_0 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. - [15:15] + MS + Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0: 0 Device configured as master, default. 1 Device configured as slave. + [2:2] read-write - LAST_0 - Buffer 0 is the last buffer of the transfer. - [14:14] + SSE + Synchronous serial port enable: 0 SSP operation disabled. 1 SSP operation enabled. + [1:1] read-write - PID_0 - The data pid of buffer 0. - [13:13] + LBM + Loop back mode: 0 Normal serial port operation enabled. 1 Output of transmit serial shifter is connected to input of receive serial shifter internally. + [0:0] read-write + + + + SSPDR + Data register, SSPDR on page 3-6 + 0x8 + 0x00000000 + - RESET - Reset the buffer selector to buffer 0. - [12:12] + DATA + Transmit/Receive FIFO: Read Receive FIFO. Write Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies. + [15:0] read-write + modify + + + + SSPSR + Status register, SSPSR on page 3-7 + 0xC + 0x00000003 + - STALL - Reply with a stall (valid for both buffers). - [11:11] - read-write + BSY + PrimeCell SSP busy flag, RO: 0 SSP is idle. 1 SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty. + [4:4] + read-only - AVAILABLE_0 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. - [10:10] - read-write + RFF + Receive FIFO full, RO: 0 Receive FIFO is not full. 1 Receive FIFO is full. + [3:3] + read-only - LENGTH_0 - The length of the data in buffer 0. - [9:0] - read-write + RNE + Receive FIFO not empty, RO: 0 Receive FIFO is empty. 1 Receive FIFO is not empty. + [2:2] + read-only + + + TNF + Transmit FIFO not full, RO: 0 Transmit FIFO is full. 1 Transmit FIFO is not full. + [1:1] + read-only + + + TFE + Transmit FIFO empty, RO: 0 Transmit FIFO is not empty. 1 Transmit FIFO is empty. + [0:0] + read-only - EPX_CONTROL - EPx Control (Host-mode only!) - 0x100 + SSPCPSR + Clock prescale register, SSPCPSR on page 3-8 + 0x10 0x00000000 - ENABLE - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. - [31:31] - read-write - - - DOUBLE_BUFFERED - This endpoint is double buffered. - [30:30] - read-write - - - INTERRUPT_PER_BUFF - Trigger an interrupt each time a buffer is done. - [29:29] - read-write - - - INTERRUPT_PER_DOUBLE_BUFF - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. - [28:28] + CPSDVSR + Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads. + [7:0] read-write + + + + SSPIMSC + Interrupt mask set or clear register, SSPIMSC on page 3-9 + 0x14 + 0x00000000 + - ENDPOINT_TYPE - [27:26] + TXIM + Transmit FIFO interrupt mask: 0 Transmit FIFO half empty or less condition interrupt is masked. 1 Transmit FIFO half empty or less condition interrupt is not masked. + [3:3] read-write - - - Control - 0 - - - Isochronous - 1 - - - Bulk - 2 - - - Interrupt - 3 - - - INTERRUPT_ON_STALL - Trigger an interrupt if a STALL is sent. Intended for debug only. - [17:17] + RXIM + Receive FIFO interrupt mask: 0 Receive FIFO half full or less condition interrupt is masked. 1 Receive FIFO half full or less condition interrupt is not masked. + [2:2] read-write - INTERRUPT_ON_NAK - Trigger an interrupt if a NAK is sent. Intended for debug only. - [16:16] + RTIM + Receive timeout interrupt mask: 0 Receive FIFO not empty and no read prior to timeout period interrupt is masked. 1 Receive FIFO not empty and no read prior to timeout period interrupt is not masked. + [1:1] read-write - BUFFER_ADDRESS - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. - [15:0] + RORIM + Receive overrun interrupt mask: 0 Receive FIFO written to while full condition interrupt is masked. 1 Receive FIFO written to while full condition interrupt is not masked. + [0:0] read-write - - - - USBCTRL_REGS - 1 - USB FS/LS controller device registers - 0x50110000 - 0x20 - - 0x0 - 0x1000 - registers - - - USBCTRL_IRQ - 5 - - - ADDR_ENDP - Device address and endpoint control - 0x0 - 0x00000000 + SSPRIS + Raw interrupt status register, SSPRIS on page 3-10 + 0x18 + 0x00000008 - ENDPOINT - Device endpoint to send data to. Only valid for HOST mode. - [19:16] - read-write + TXRIS + Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt + [3:3] + read-only + + + RXRIS + Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt + [2:2] + read-only + + + RTRIS + Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt + [1:1] + read-only - ADDRESS - In device mode, the address that the device should respond to. Set in response to a SET_ADDR setup packet from the host. In host mode set to the address of the device to communicate with. - [6:0] - read-write + RORRIS + Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt + [0:0] + read-only - 15 - 0x4 - 1-15 - HOST_ADDR_ENDP%s - Interrupt endpoints. Only valid in HOST mode. - 0x4 + SSPMIS + Masked interrupt status register, SSPMIS on page 3-11 + 0x1C 0x00000000 - INTEP_PREAMBLE - Interrupt EP requires preamble (is a low speed device on a full speed hub) - [26:26] - read-write + TXMIS + Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt + [3:3] + read-only - INTEP_DIR - Direction of the interrupt endpoint. In=0, Out=1 - [25:25] - read-write + RXMIS + Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt + [2:2] + read-only - ENDPOINT - Endpoint number of the interrupt endpoint - [19:16] - read-write + RTMIS + Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt + [1:1] + read-only - ADDRESS - Device address - [6:0] - read-write + RORMIS + Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt + [0:0] + read-only - MAIN_CTRL - Main control register - 0x40 + SSPICR + Interrupt clear register, SSPICR on page 3-11 + 0x20 0x00000000 - SIM_TIMING - Reduced timings for simulation - [31:31] + RTIC + Clears the SSPRTINTR interrupt + [1:1] read-write + oneToClear - HOST_NDEVICE - Device mode = 0, Host mode = 1 + RORIC + Clears the SSPRORINTR interrupt + [0:0] + read-write + oneToClear + + + + + SSPDMACR + DMA control register, SSPDMACR on page 3-12 + 0x24 + 0x00000000 + + + TXDMAE + Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. [1:1] read-write - CONTROLLER_EN - Enable controller + RXDMAE + Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled. [0:0] read-write - SOF_WR - Set the SOF (Start of Frame) frame number in the host controller. The SOF packet is sent every 1ms and the host will increment the frame number by 1 each time. - 0x44 - 0x00000000 + SSPPERIPHID0 + Peripheral identification registers, SSPPeriphID0-3 on page 3-13 + 0xFE0 + 0x00000022 - COUNT - [10:0] - write-only + PARTNUMBER0 + These bits read back as 0x22 + [7:0] + read-only - SOF_RD - Read the last SOF (Start of Frame) frame number seen. In device mode the last SOF received from the host. In host mode the last SOF sent by the host. - 0x48 - 0x00000000 + SSPPERIPHID1 + Peripheral identification registers, SSPPeriphID0-3 on page 3-13 + 0xFE4 + 0x00000010 - COUNT - [10:0] + DESIGNER0 + These bits read back as 0x1 + [7:4] + read-only + + + PARTNUMBER1 + These bits read back as 0x0 + [3:0] read-only - SIE_CTRL - SIE control register - 0x4C + SSPPERIPHID2 + Peripheral identification registers, SSPPeriphID0-3 on page 3-13 + 0xFE8 + 0x00000034 + + + REVISION + These bits return the peripheral revision + [7:4] + read-only + + + DESIGNER1 + These bits read back as 0x4 + [3:0] + read-only + + + + + SSPPERIPHID3 + Peripheral identification registers, SSPPeriphID0-3 on page 3-13 + 0xFEC 0x00000000 - EP0_INT_STALL - Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a STALL - [31:31] - read-write + CONFIGURATION + These bits read back as 0x00 + [7:0] + read-only + + + + SSPPCELLID0 + PrimeCell identification registers, SSPPCellID0-3 on page 3-16 + 0xFF0 + 0x0000000D + - EP0_DOUBLE_BUF - Device: EP0 single buffered = 0, double buffered = 1 - [30:30] - read-write + SSPPCELLID0 + These bits read back as 0x0D + [7:0] + read-only + + + + SSPPCELLID1 + PrimeCell identification registers, SSPPCellID0-3 on page 3-16 + 0xFF4 + 0x000000F0 + - EP0_INT_1BUF - Device: Set bit in BUFF_STATUS for every buffer completed on EP0 - [29:29] - read-write + SSPPCELLID1 + These bits read back as 0xF0 + [7:0] + read-only + + + + SSPPCELLID2 + PrimeCell identification registers, SSPPCellID0-3 on page 3-16 + 0xFF8 + 0x00000005 + - EP0_INT_2BUF - Device: Set bit in BUFF_STATUS for every 2 buffers completed on EP0 - [28:28] - read-write + SSPPCELLID2 + These bits read back as 0x05 + [7:0] + read-only + + + + SSPPCELLID3 + PrimeCell identification registers, SSPPCellID0-3 on page 3-16 + 0xFFC + 0x000000B1 + - EP0_INT_NAK - Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a NAK - [27:27] - read-write + SSPPCELLID3 + These bits read back as 0xB1 + [7:0] + read-only + + + + + + SPI1 + 0x40040000 + + SPI1_IRQ + 19 + + + + PIO0 + Programmable IO block + 0x50200000 + + 0x0 + 0x144 + registers + + + PIO0_IRQ_0 + 7 + + + PIO0_IRQ_1 + 8 + + + + CTRL + PIO control register + 0x0 + 0x00000000 + - DIRECT_EN - Direct bus drive enable - [26:26] - read-write + CLKDIV_RESTART + Restart a state machine's clock divider from an initial phase of 0. Clock dividers are free-running, so once started, their output (including fractional jitter) is completely determined by the integer/fractional divisor configured in SMx_CLKDIV. This means that, if multiple clock dividers with the same divisor are restarted simultaneously, by writing multiple 1 bits to this field, the execution clocks of those state machines will run in precise lockstep. + + Note that setting/clearing SM_ENABLE does not stop the clock divider from running, so once multiple state machines' clocks are synchronised, it is safe to disable/reenable a state machine, whilst keeping the clock dividers in sync. + + Note also that CLKDIV_RESTART can be written to whilst the state machine is running, and this is useful to resynchronise clock dividers after the divisors (SMx_CLKDIV) have been changed on-the-fly. + [11:8] + write-only - DIRECT_DP - Direct control of DP - [25:25] - read-write + SM_RESTART + Write 1 to instantly clear internal SM state which may be otherwise difficult to access and will affect future execution. + + Specifically, the following are cleared: input and output shift counters; the contents of the input shift register; the delay counter; the waiting-on-IRQ state; any stalled instruction written to SMx_INSTR or run by OUT/MOV EXEC; any pin write left asserted due to OUT_STICKY. + + The program counter, the contents of the output shift register and the X/Y scratch registers are not affected. + [7:4] + write-only - DIRECT_DM - Direct control of DM - [24:24] + SM_ENABLE + Enable/disable each of the four state machines by writing 1/0 to each of these four bits. When disabled, a state machine will cease executing instructions, except those written directly to SMx_INSTR by the system. Multiple bits can be set/cleared at once to run/halt multiple state machines simultaneously. + [3:0] read-write + + + + FSTAT + FIFO status register + 0x4 + 0x0F000F00 + - TRANSCEIVER_PD - Power down bus transceiver - [18:18] - read-write + TXEMPTY + State machine TX FIFO is empty + [27:24] + read-only - RPU_OPT - Device: Pull-up strength (0=1K2, 1=2k3) - [17:17] - read-write + TXFULL + State machine TX FIFO is full + [19:16] + read-only - PULLUP_EN - Device: Enable pull up resistor - [16:16] - read-write + RXEMPTY + State machine RX FIFO is empty + [11:8] + read-only - PULLDOWN_EN - Host: Enable pull down resistors - [15:15] - read-write + RXFULL + State machine RX FIFO is full + [3:0] + read-only + + + + FDEBUG + FIFO debug register + 0x8 + 0x00000000 + - RESET_BUS - Host: Reset bus - [13:13] + TXSTALL + State machine has stalled on empty TX FIFO during a blocking PULL, or an OUT with autopull enabled. Write 1 to clear. + [27:24] read-write - clear + oneToClear - RESUME - Device: Remote wakeup. Device can initiate its own resume after suspend. - [12:12] + TXOVER + TX FIFO overflow (i.e. write-on-full by the system) has occurred. Write 1 to clear. Note that write-on-full does not alter the state or contents of the FIFO in any way, but the data that the system attempted to write is dropped, so if this flag is set, your software has quite likely dropped some data on the floor. + [19:16] read-write - clear + oneToClear - VBUS_EN - Host: Enable VBUS - [11:11] + RXUNDER + RX FIFO underflow (i.e. read-on-empty by the system) has occurred. Write 1 to clear. Note that read-on-empty does not perturb the state of the FIFO in any way, but the data returned by reading from an empty FIFO is undefined, so this flag generally only becomes set due to some kind of software error. + [11:8] read-write + oneToClear - KEEP_ALIVE_EN - Host: Enable keep alive packet (for low speed bus) - [10:10] + RXSTALL + State machine has stalled on full RX FIFO during a blocking PUSH, or an IN with autopush enabled. This flag is also set when a nonblocking PUSH to a full FIFO took place, in which case the state machine has dropped data. Write 1 to clear. + [3:0] read-write + oneToClear + + + + FLEVEL + FIFO levels + 0xC + 0x00000000 + - SOF_EN - Host: Enable SOF generation (for full speed bus) - [9:9] - read-write + RX3 + [31:28] + read-only - SOF_SYNC - Host: Delay packet(s) until after SOF - [8:8] - read-write + TX3 + [27:24] + read-only - PREAMBLE_EN - Host: Preable enable for LS device on FS hub - [6:6] - read-write + RX2 + [23:20] + read-only - STOP_TRANS - Host: Stop transaction - [4:4] - read-write - clear + TX2 + [19:16] + read-only - RECEIVE_DATA - Host: Receive transaction (IN to host) - [3:3] - read-write + RX1 + [15:12] + read-only - SEND_DATA - Host: Send transaction (OUT from host) - [2:2] - read-write + TX1 + [11:8] + read-only - SEND_SETUP - Host: Send Setup packet - [1:1] - read-write + RX0 + [7:4] + read-only - START_TRANS - Host: Start transaction - [0:0] - read-write - clear + TX0 + [3:0] + read-only - SIE_STATUS - SIE status register - 0x50 + 4 + 0x4 + 0-3 + TXF%s + Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO. + 0x10 0x00000000 - DATA_SEQ_ERROR - Data Sequence Error.\n\n - The device can raise a sequence error in the following conditions:\n\n - * A SETUP packet is received followed by a DATA1 packet (data phase should always be DATA0) * An OUT packet is received from the host but doesn't match the data pid in the buffer control register read from DPSRAM\n\n - The host can raise a data sequence error in the following conditions:\n\n - * An IN packet from the device has the wrong data PID - [31:31] - read-write - oneToClear - - - ACK_REC - ACK received. Raised by both host and device. - [30:30] - read-write - oneToClear + TXF0 + [31:0] + write-only + + + + 4 + 0x4 + 0-3 + RXF%s + Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined. + 0x20 + 0x00000000 + - STALL_REC - Host: STALL received - [29:29] - read-write - oneToClear + RXF0 + [31:0] + read-only + modify + + + + IRQ + State machine IRQ flags register. Write 1 to clear. There are 8 state machine IRQ flags, which can be set, cleared, and waited on by the state machines. There's no fixed association between flags and state machines -- any state machine can use any flag. + + Any of the 8 flags can be used for timing synchronisation between state machines, using IRQ and WAIT instructions. The lower four of these flags are also routed out to system-level interrupt requests, alongside FIFO status interrupts -- see e.g. IRQ0_INTE. + 0x30 + 0x00000000 + - NAK_REC - Host: NAK received - [28:28] + IRQ + [7:0] read-write oneToClear + + + + IRQ_FORCE + Writing a 1 to each of these bits will forcibly assert the corresponding IRQ. Note this is different to the INTF register: writing here affects PIO internal state. INTF just asserts the processor-facing IRQ signal for testing ISRs, and is not visible to the state machines. + 0x34 + 0x00000000 + - RX_TIMEOUT - RX timeout is raised by both the host and device if an ACK is not received in the maximum time specified by the USB spec. - [27:27] - read-write - oneToClear + IRQ_FORCE + [7:0] + write-only + + + + INPUT_SYNC_BYPASS + There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic from metastabilities. This increases input delay, and for fast synchronous IO (e.g. SPI) these synchronizers may need to be bypassed. Each bit in this register corresponds to one GPIO. + 0 -> input is synchronized (default) + 1 -> synchronizer is bypassed + If in doubt, leave this register as all zeroes. + 0x38 + 0x00000000 + - RX_OVERFLOW - RX overflow is raised by the Serial RX engine if the incoming data is too fast. - [26:26] + INPUT_SYNC_BYPASS + [31:0] read-write - oneToClear - - BIT_STUFF_ERROR - Bit Stuff Error. Raised by the Serial RX engine. - [25:25] - read-write - oneToClear + + + + DBG_PADOUT + Read to sample the pad output values PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0. + 0x3C + 0x00000000 + + + DBG_PADOUT + [31:0] + read-only + + + + DBG_PADOE + Read to sample the pad output enables (direction) PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0. + 0x40 + 0x00000000 + - CRC_ERROR - CRC Error. Raised by the Serial RX engine. - [24:24] - read-write - oneToClear + DBG_PADOE + [31:0] + read-only + + + + DBG_CFGINFO + The PIO hardware has some free parameters that may vary between chip products. + These should be provided in the chip datasheet, but are also exposed here. + 0x44 + 0x00000000 + - BUS_RESET - Device: bus reset received - [19:19] - read-write - oneToClear + IMEM_SIZE + The size of the instruction memory, measured in units of one instruction + [21:16] + read-only - TRANS_COMPLETE - Transaction complete.\n\n - Raised by device if:\n\n - * An IN or OUT packet is sent with the `LAST_BUFF` bit set in the buffer control register\n\n - Raised by host if:\n\n - * A setup packet is sent when no data in or data out transaction follows * An IN packet is received and the `LAST_BUFF` bit is set in the buffer control register * An IN packet is received with zero length * An OUT packet is sent and the `LAST_BUFF` bit is set - [18:18] - read-write - oneToClear + SM_COUNT + The number of state machines this PIO instance is equipped with. + [11:8] + read-only - SETUP_REC - Device: Setup packet received - [17:17] - read-write - oneToClear + FIFO_DEPTH + The depth of the state machine TX/RX FIFOs, measured in words. + Joining fifos via SHIFTCTRL_FJOIN gives one FIFO with double + this depth. + [5:0] + read-only + + + + 32 + 0x4 + 0-31 + INSTR_MEM%s + Write-only access to instruction memory location %s + 0x48 + 0x00000000 + - CONNECTED - Device: connected - [16:16] - read-write - oneToClear + INSTR_MEM0 + [15:0] + write-only + + + + 4 + 0x18 + 0-3 + SM%s + Cluster SM%s, containing SM*_CLKDIV, SM*_EXECCTRL, SM*_SHIFTCTRL, SM*_ADDR, SM*_INSTR, SM*_PINCTRL + 0xC8 + + SM_CLKDIV + Clock divisor register for state machine 0 + Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) + 0x0 + 0x00010000 + + + INT + Effective frequency is sysclk/(int + frac/256). + Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0. + [31:16] + read-write + + + FRAC + Fractional part of clock divisor + [15:8] + read-write + + + + + SM_EXECCTRL + Execution/behavioural settings for state machine 0 + 0x4 + 0x0001F000 + + + EXEC_STALLED + If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes. + [31:31] + read-only + + + SIDE_EN + If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit. + [30:30] + read-write + + + SIDE_PINDIR + If 1, side-set data is asserted to pin directions, instead of pin values + [29:29] + read-write + + + JMP_PIN + The GPIO number to use as condition for JMP PIN. Unaffected by input mapping. + [28:24] + read-write + + + OUT_EN_SEL + Which data bit to use for inline OUT enable + [23:19] + read-write + + + INLINE_OUT_EN + If 1, use a bit of OUT data as an auxiliary write enable + When used in conjunction with OUT_STICKY, writes with an enable of 0 will + deassert the latest pin write. This can create useful masking/override behaviour + due to the priority ordering of state machine pin writes (SM0 < SM1 < ...) + [18:18] + read-write + + + OUT_STICKY + Continuously assert the most recent OUT/SET to the pins + [17:17] + read-write + + + WRAP_TOP + After reaching this address, execution is wrapped to wrap_bottom. + If the instruction is a jump, and the jump condition is true, the jump takes priority. + [16:12] + read-write + + + WRAP_BOTTOM + After reaching wrap_top, execution is wrapped to this address. + [11:7] + read-write + + + STATUS_SEL + Comparison used for the MOV x, STATUS instruction. + [4:4] + read-write + + + TXLEVEL + All-ones if TX FIFO level < N, otherwise all-zeroes + 0 + + + RXLEVEL + All-ones if RX FIFO level < N, otherwise all-zeroes + 1 + + + + + STATUS_N + Comparison level for the MOV x, STATUS instruction + [3:0] + read-write + + + + + SM_SHIFTCTRL + Control behaviour of the input/output shift registers for state machine 0 + 0x8 + 0x000C0000 + + + FJOIN_RX + When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep. + TX FIFO is disabled as a result (always reads as both full and empty). + FIFOs are flushed when this bit is changed. + [31:31] + read-write + + + FJOIN_TX + When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep. + RX FIFO is disabled as a result (always reads as both full and empty). + FIFOs are flushed when this bit is changed. + [30:30] + read-write + + + PULL_THRESH + Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place. + Write 0 for value of 32. + [29:25] + read-write + + + PUSH_THRESH + Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place. + Write 0 for value of 32. + [24:20] + read-write + + + OUT_SHIFTDIR + 1 = shift out of output shift register to right. 0 = to left. + [19:19] + read-write + + + IN_SHIFTDIR + 1 = shift input shift register to right (data enters from left). 0 = to left. + [18:18] + read-write + + + AUTOPULL + Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH. + [17:17] + read-write + + + AUTOPUSH + Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH. + [16:16] + read-write + + + + + SM_ADDR + Current instruction address of state machine 0 + 0xC + 0x00000000 + + + SM0_ADDR + [4:0] + read-only + + + + + SM_INSTR + Read to see the instruction currently addressed by state machine 0's program counter + Write to execute an instruction immediately (including jumps) and then resume execution. + 0x10 + 0x00000000 + + + SM0_INSTR + [15:0] + read-write + + + + + SM_PINCTRL + State machine pin control + 0x14 + 0x14000000 + + + SIDESET_COUNT + The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay). + [31:29] + read-write + + + SET_COUNT + The number of pins asserted by a SET. In the range 0 to 5 inclusive. + [28:26] + read-write + + + OUT_COUNT + The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive. + [25:20] + read-write + + + IN_BASE + The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number. + [19:15] + read-write + + + SIDESET_BASE + The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins. + [14:10] + read-write + + + SET_BASE + The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data. + [9:5] + read-write + + + OUT_BASE + The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data. + [4:0] + read-write + + + + + + INTR + Raw Interrupts + 0x128 + 0x00000000 + - RESUME - Host: Device has initiated a remote resume. Device: host has initiated a resume. + SM3 [11:11] - read-write - oneToClear + read-only - VBUS_OVER_CURR - VBUS over current detected + SM2 [10:10] read-only - SPEED - Host: device speed. Disconnected = 00, LS = 01, FS = 10 - [9:8] - read-write - oneToClear - - - SUSPENDED - Bus in suspended state. Valid for device and host. Host and device will go into suspend if neither Keep Alive / SOF frames are enabled. - [4:4] - read-write - oneToClear - - - LINE_STATE - USB bus line state - [3:2] + SM1 + [9:9] read-only - - LINE_STATE - - SE0 - SE0 - 0 - - - J - J - 1 - - - K - K - 2 - - - SE1 - SE1 - 3 - - - VBUS_DETECTED - Device: VBUS Detected - [0:0] + SM0 + [8:8] read-only - - - - INT_EP_CTRL - interrupt endpoint control register - 0x54 - 0x00000000 - - - INT_EP_ACTIVE - Host: Enable interrupt endpoint 1 -> 15 - [15:1] - read-write - - - - - BUFF_STATUS - Buffer status register. A bit set here indicates that a buffer has completed on the endpoint (if the buffer interrupt is enabled). It is possible for 2 buffers to be completed, so clearing the buffer status bit may instantly re set it on the next clock cycle. - 0x58 - 0x00000000 - - - EP15_OUT - [31:31] - read-write - oneToClear - - - EP15_IN - [30:30] - read-write - oneToClear - - - EP14_OUT - [29:29] - read-write - oneToClear - - - EP14_IN - [28:28] - read-write - oneToClear - - - EP13_OUT - [27:27] - read-write - oneToClear - - - EP13_IN - [26:26] - read-write - oneToClear - - - EP12_OUT - [25:25] - read-write - oneToClear - - - EP12_IN - [24:24] - read-write - oneToClear - - - EP11_OUT - [23:23] - read-write - oneToClear - - - EP11_IN - [22:22] - read-write - oneToClear - - - EP10_OUT - [21:21] - read-write - oneToClear - - - EP10_IN - [20:20] - read-write - oneToClear - - EP9_OUT - [19:19] - read-write - oneToClear - - - EP9_IN - [18:18] - read-write - oneToClear + SM3_TXNFULL + [7:7] + read-only - EP8_OUT - [17:17] - read-write - oneToClear + SM2_TXNFULL + [6:6] + read-only - EP8_IN - [16:16] - read-write - oneToClear + SM1_TXNFULL + [5:5] + read-only - EP7_OUT - [15:15] - read-write - oneToClear + SM0_TXNFULL + [4:4] + read-only - EP7_IN - [14:14] - read-write - oneToClear + SM3_RXNEMPTY + [3:3] + read-only - EP6_OUT - [13:13] - read-write - oneToClear + SM2_RXNEMPTY + [2:2] + read-only - EP6_IN - [12:12] - read-write - oneToClear + SM1_RXNEMPTY + [1:1] + read-only - EP5_OUT - [11:11] - read-write - oneToClear + SM0_RXNEMPTY + [0:0] + read-only + + + + 2 + 0xC + 0-1 + SM_IRQ%s + Cluster SM_IRQ%s, containing IRQ*_INTE, IRQ*_INTF, IRQ*_INTS + 0x12C + + IRQ_INTE + Interrupt Enable for irq0 + 0x0 + 0x00000000 + + + SM3 + [11:11] + read-write + + + SM2 + [10:10] + read-write + + + SM1 + [9:9] + read-write + + + SM0 + [8:8] + read-write + + + SM3_TXNFULL + [7:7] + read-write + + + SM2_TXNFULL + [6:6] + read-write + + + SM1_TXNFULL + [5:5] + read-write + + + SM0_TXNFULL + [4:4] + read-write + + + SM3_RXNEMPTY + [3:3] + read-write + + + SM2_RXNEMPTY + [2:2] + read-write + + + SM1_RXNEMPTY + [1:1] + read-write + + + SM0_RXNEMPTY + [0:0] + read-write + + + + + IRQ_INTF + Interrupt Force for irq0 + 0x4 + 0x00000000 + + + SM3 + [11:11] + read-write + + + SM2 + [10:10] + read-write + + + SM1 + [9:9] + read-write + + + SM0 + [8:8] + read-write + + + SM3_TXNFULL + [7:7] + read-write + + + SM2_TXNFULL + [6:6] + read-write + + + SM1_TXNFULL + [5:5] + read-write + + + SM0_TXNFULL + [4:4] + read-write + + + SM3_RXNEMPTY + [3:3] + read-write + + + SM2_RXNEMPTY + [2:2] + read-write + + + SM1_RXNEMPTY + [1:1] + read-write + + + SM0_RXNEMPTY + [0:0] + read-write + + + + + IRQ_INTS + Interrupt status after masking & forcing for irq0 + 0x8 + 0x00000000 + + + SM3 + [11:11] + read-only + + + SM2 + [10:10] + read-only + + + SM1 + [9:9] + read-only + + + SM0 + [8:8] + read-only + + + SM3_TXNFULL + [7:7] + read-only + + + SM2_TXNFULL + [6:6] + read-only + + + SM1_TXNFULL + [5:5] + read-only + + + SM0_TXNFULL + [4:4] + read-only + + + SM3_RXNEMPTY + [3:3] + read-only + + + SM2_RXNEMPTY + [2:2] + read-only + + + SM1_RXNEMPTY + [1:1] + read-only + + + SM0_RXNEMPTY + [0:0] + read-only + + + + + + + + PIO1 + 0x50300000 + + PIO1_IRQ_0 + 9 + + + PIO1_IRQ_1 + 10 + + + + BUSCTRL + Register block for busfabric control signals and performance counters + 0x40030000 + + 0x0 + 0x28 + registers + + + + BUS_PRIORITY + Set the priority of each master for bus arbitration. + 0x0 + 0x00000000 + - EP5_IN - [10:10] + DMA_W + 0 - low priority, 1 - high priority + [12:12] read-write - oneToClear - EP4_OUT - [9:9] + DMA_R + 0 - low priority, 1 - high priority + [8:8] read-write - oneToClear - EP4_IN - [8:8] + PROC1 + 0 - low priority, 1 - high priority + [4:4] read-write - oneToClear - EP3_OUT - [7:7] + PROC0 + 0 - low priority, 1 - high priority + [0:0] read-write - oneToClear + + + + BUS_PRIORITY_ACK + Bus priority acknowledge + 0x4 + 0x00000000 + - EP3_IN - [6:6] - read-write - oneToClear + BUS_PRIORITY_ACK + Goes to 1 once all arbiters have registered the new global priority levels. + Arbiters update their local priority when servicing a new nonsequential access. + In normal circumstances this will happen almost immediately. + [0:0] + read-only + + + + PERFCTR0 + Bus fabric performance counter 0 + 0x8 + 0x00000000 + - EP2_OUT - [5:5] + PERFCTR0 + Busfabric saturating performance counter 0 + Count some event signal from the busfabric arbiters. + Write any value to clear. Select an event to count using PERFSEL0 + [23:0] read-write oneToClear + + + + PERFSEL0 + Bus fabric performance event select for PERFCTR0 + 0xC + 0x0000001F + - EP2_IN - [4:4] + PERFSEL0 + Select an event for PERFCTR0. Count either contested accesses, or all accesses, on a downstream port of the main crossbar. + [4:0] read-write - oneToClear + + + apb_contested + 0 + + + apb + 1 + + + fastperi_contested + 2 + + + fastperi + 3 + + + sram5_contested + 4 + + + sram5 + 5 + + + sram4_contested + 6 + + + sram4 + 7 + + + sram3_contested + 8 + + + sram3 + 9 + + + sram2_contested + 10 + + + sram2 + 11 + + + sram1_contested + 12 + + + sram1 + 13 + + + sram0_contested + 14 + + + sram0 + 15 + + + xip_main_contested + 16 + + + xip_main + 17 + + + rom_contested + 18 + + + rom + 19 + + + + + + PERFCTR1 + Bus fabric performance counter 1 + 0x10 + 0x00000000 + - EP1_OUT - [3:3] + PERFCTR1 + Busfabric saturating performance counter 1 + Count some event signal from the busfabric arbiters. + Write any value to clear. Select an event to count using PERFSEL1 + [23:0] read-write oneToClear + + + + PERFSEL1 + Bus fabric performance event select for PERFCTR1 + 0x14 + 0x0000001F + - EP1_IN - [2:2] + PERFSEL1 + Select an event for PERFCTR1. Count either contested accesses, or all accesses, on a downstream port of the main crossbar. + [4:0] read-write - oneToClear + + + apb_contested + 0 + + + apb + 1 + + + fastperi_contested + 2 + + + fastperi + 3 + + + sram5_contested + 4 + + + sram5 + 5 + + + sram4_contested + 6 + + + sram4 + 7 + + + sram3_contested + 8 + + + sram3 + 9 + + + sram2_contested + 10 + + + sram2 + 11 + + + sram1_contested + 12 + + + sram1 + 13 + + + sram0_contested + 14 + + + sram0 + 15 + + + xip_main_contested + 16 + + + xip_main + 17 + + + rom_contested + 18 + + + rom + 19 + + + + + + PERFCTR2 + Bus fabric performance counter 2 + 0x18 + 0x00000000 + - EP0_OUT - [1:1] + PERFCTR2 + Busfabric saturating performance counter 2 + Count some event signal from the busfabric arbiters. + Write any value to clear. Select an event to count using PERFSEL2 + [23:0] read-write oneToClear + + + + PERFSEL2 + Bus fabric performance event select for PERFCTR2 + 0x1C + 0x0000001F + - EP0_IN - [0:0] + PERFSEL2 + Select an event for PERFCTR2. Count either contested accesses, or all accesses, on a downstream port of the main crossbar. + [4:0] read-write - oneToClear + + + apb_contested + 0 + + + apb + 1 + + + fastperi_contested + 2 + + + fastperi + 3 + + + sram5_contested + 4 + + + sram5 + 5 + + + sram4_contested + 6 + + + sram4 + 7 + + + sram3_contested + 8 + + + sram3 + 9 + + + sram2_contested + 10 + + + sram2 + 11 + + + sram1_contested + 12 + + + sram1 + 13 + + + sram0_contested + 14 + + + sram0 + 15 + + + xip_main_contested + 16 + + + xip_main + 17 + + + rom_contested + 18 + + + rom + 19 + + - BUFF_CPU_SHOULD_HANDLE - Which of the double buffers should be handled. Only valid if using an interrupt per buffer (i.e. not per 2 buffers). Not valid for host interrupt endpoint polling because they are only single buffered. - 0x5C + PERFCTR3 + Bus fabric performance counter 3 + 0x20 0x00000000 - EP15_OUT - [31:31] - read-only - - - EP15_IN - [30:30] - read-only - - - EP14_OUT - [29:29] - read-only - - - EP14_IN - [28:28] - read-only - - - EP13_OUT - [27:27] - read-only - - - EP13_IN - [26:26] - read-only - - - EP12_OUT - [25:25] - read-only - - - EP12_IN - [24:24] - read-only - - - EP11_OUT - [23:23] - read-only - - - EP11_IN - [22:22] - read-only - - - EP10_OUT - [21:21] - read-only - - - EP10_IN - [20:20] - read-only - - - EP9_OUT - [19:19] - read-only - - - EP9_IN - [18:18] - read-only - - - EP8_OUT - [17:17] - read-only - - - EP8_IN - [16:16] - read-only - - - EP7_OUT - [15:15] - read-only - - - EP7_IN - [14:14] - read-only - - - EP6_OUT - [13:13] - read-only - - - EP6_IN - [12:12] - read-only - - - EP5_OUT - [11:11] - read-only - - - EP5_IN - [10:10] - read-only - - - EP4_OUT - [9:9] - read-only - - - EP4_IN - [8:8] - read-only + PERFCTR3 + Busfabric saturating performance counter 3 + Count some event signal from the busfabric arbiters. + Write any value to clear. Select an event to count using PERFSEL3 + [23:0] + read-write + oneToClear + + + + PERFSEL3 + Bus fabric performance event select for PERFCTR3 + 0x24 + 0x0000001F + - EP3_OUT - [7:7] - read-only + PERFSEL3 + Select an event for PERFCTR3. Count either contested accesses, or all accesses, on a downstream port of the main crossbar. + [4:0] + read-write + + + apb_contested + 0 + + + apb + 1 + + + fastperi_contested + 2 + + + fastperi + 3 + + + sram5_contested + 4 + + + sram5 + 5 + + + sram4_contested + 6 + + + sram4 + 7 + + + sram3_contested + 8 + + + sram3 + 9 + + + sram2_contested + 10 + + + sram2 + 11 + + + sram1_contested + 12 + + + sram1 + 13 + + + sram0_contested + 14 + + + sram0 + 15 + + + xip_main_contested + 16 + + + xip_main + 17 + + + rom_contested + 18 + + + rom + 19 + + + + + + + + SIO + Single-cycle IO block + Provides core-local and inter-core hardware for the two processors, with single-cycle access. + 0xD0000000 + + 0x0 + 0x180 + registers + + + SIO_IRQ_PROC0 + 15 + + + SIO_IRQ_PROC1 + 16 + + + + CPUID + Processor core identifier + 0x0 + 0x00000000 + - EP3_IN - [6:6] + CPUID + Value is 0 when read from processor core 0, and 1 when read from processor core 1. + [31:0] read-only + + + + GPIO_IN + Input value for GPIO pins + 0x4 + 0x00000000 + - EP2_OUT - [5:5] + GPIO_IN + Input value for GPIO0...29 + [29:0] read-only + + + + GPIO_HI_IN + Input value for QSPI pins + 0x8 + 0x00000000 + - EP2_IN - [4:4] + GPIO_HI_IN + Input value on QSPI IO in order 0..5: SCLK, SSn, SD0, SD1, SD2, SD3 + [5:0] read-only + + + + GPIO_OUT + GPIO output value + 0x10 + 0x00000000 + - EP1_OUT - [3:3] - read-only + GPIO_OUT + Set output level (1/0 -> high/low) for GPIO0...29. + Reading back gives the last value written, NOT the input value from the pins. + If core 0 and core 1 both write to GPIO_OUT simultaneously (or to a SET/CLR/XOR alias), + the result is as though the write from core 0 took place first, + and the write from core 1 was then applied to that intermediate result. + [29:0] + read-write + + + + GPIO_OUT_SET + GPIO output value set + 0x14 + 0x00000000 + - EP1_IN - [2:2] - read-only + GPIO_OUT_SET + Perform an atomic bit-set on GPIO_OUT, i.e. `GPIO_OUT |= wdata` + [29:0] + write-only + + + + GPIO_OUT_CLR + GPIO output value clear + 0x18 + 0x00000000 + - EP0_OUT - [1:1] - read-only + GPIO_OUT_CLR + Perform an atomic bit-clear on GPIO_OUT, i.e. `GPIO_OUT &= ~wdata` + [29:0] + write-only + + + + GPIO_OUT_XOR + GPIO output value XOR + 0x1C + 0x00000000 + - EP0_IN - [0:0] - read-only + GPIO_OUT_XOR + Perform an atomic bitwise XOR on GPIO_OUT, i.e. `GPIO_OUT ^= wdata` + [29:0] + write-only - EP_ABORT - Device only: Can be set to ignore the buffer control register for this endpoint in case you would like to revoke a buffer. A NAK will be sent for every access to the endpoint until this bit is cleared. A corresponding bit in `EP_ABORT_DONE` is set when it is safe to modify the buffer control register. - 0x60 + GPIO_OE + GPIO output enable + 0x20 0x00000000 - EP15_OUT - [31:31] + GPIO_OE + Set output enable (1/0 -> output/input) for GPIO0...29. + Reading back gives the last value written. + If core 0 and core 1 both write to GPIO_OE simultaneously (or to a SET/CLR/XOR alias), + the result is as though the write from core 0 took place first, + and the write from core 1 was then applied to that intermediate result. + [29:0] read-write + + + + GPIO_OE_SET + GPIO output enable set + 0x24 + 0x00000000 + - EP15_IN - [30:30] - read-write + GPIO_OE_SET + Perform an atomic bit-set on GPIO_OE, i.e. `GPIO_OE |= wdata` + [29:0] + write-only + + + + GPIO_OE_CLR + GPIO output enable clear + 0x28 + 0x00000000 + - EP14_OUT - [29:29] - read-write + GPIO_OE_CLR + Perform an atomic bit-clear on GPIO_OE, i.e. `GPIO_OE &= ~wdata` + [29:0] + write-only + + + + GPIO_OE_XOR + GPIO output enable XOR + 0x2C + 0x00000000 + - EP14_IN - [28:28] - read-write + GPIO_OE_XOR + Perform an atomic bitwise XOR on GPIO_OE, i.e. `GPIO_OE ^= wdata` + [29:0] + write-only + + + + GPIO_HI_OUT + QSPI output value + 0x30 + 0x00000000 + - EP13_OUT - [27:27] + GPIO_HI_OUT + Set output level (1/0 -> high/low) for QSPI IO0...5. + Reading back gives the last value written, NOT the input value from the pins. + If core 0 and core 1 both write to GPIO_HI_OUT simultaneously (or to a SET/CLR/XOR alias), + the result is as though the write from core 0 took place first, + and the write from core 1 was then applied to that intermediate result. + [5:0] read-write + + + + GPIO_HI_OUT_SET + QSPI output value set + 0x34 + 0x00000000 + - EP13_IN - [26:26] - read-write + GPIO_HI_OUT_SET + Perform an atomic bit-set on GPIO_HI_OUT, i.e. `GPIO_HI_OUT |= wdata` + [5:0] + write-only + + + + GPIO_HI_OUT_CLR + QSPI output value clear + 0x38 + 0x00000000 + - EP12_OUT - [25:25] - read-write + GPIO_HI_OUT_CLR + Perform an atomic bit-clear on GPIO_HI_OUT, i.e. `GPIO_HI_OUT &= ~wdata` + [5:0] + write-only + + + + GPIO_HI_OUT_XOR + QSPI output value XOR + 0x3C + 0x00000000 + - EP12_IN - [24:24] - read-write + GPIO_HI_OUT_XOR + Perform an atomic bitwise XOR on GPIO_HI_OUT, i.e. `GPIO_HI_OUT ^= wdata` + [5:0] + write-only + + + + GPIO_HI_OE + QSPI output enable + 0x40 + 0x00000000 + - EP11_OUT - [23:23] + GPIO_HI_OE + Set output enable (1/0 -> output/input) for QSPI IO0...5. + Reading back gives the last value written. + If core 0 and core 1 both write to GPIO_HI_OE simultaneously (or to a SET/CLR/XOR alias), + the result is as though the write from core 0 took place first, + and the write from core 1 was then applied to that intermediate result. + [5:0] read-write + + + + GPIO_HI_OE_SET + QSPI output enable set + 0x44 + 0x00000000 + - EP11_IN - [22:22] - read-write + GPIO_HI_OE_SET + Perform an atomic bit-set on GPIO_HI_OE, i.e. `GPIO_HI_OE |= wdata` + [5:0] + write-only + + + + GPIO_HI_OE_CLR + QSPI output enable clear + 0x48 + 0x00000000 + - EP10_OUT - [21:21] - read-write + GPIO_HI_OE_CLR + Perform an atomic bit-clear on GPIO_HI_OE, i.e. `GPIO_HI_OE &= ~wdata` + [5:0] + write-only + + + + GPIO_HI_OE_XOR + QSPI output enable XOR + 0x4C + 0x00000000 + - EP10_IN - [20:20] - read-write + GPIO_HI_OE_XOR + Perform an atomic bitwise XOR on GPIO_HI_OE, i.e. `GPIO_HI_OE ^= wdata` + [5:0] + write-only + + + + FIFO_ST + Status register for inter-core FIFOs (mailboxes). + There is one FIFO in the core 0 -> core 1 direction, and one core 1 -> core 0. Both are 32 bits wide and 8 words deep. + Core 0 can see the read side of the 1->0 FIFO (RX), and the write side of 0->1 FIFO (TX). + Core 1 can see the read side of the 0->1 FIFO (RX), and the write side of 1->0 FIFO (TX). + The SIO IRQ for each core is the logical OR of the VLD, WOF and ROE fields of its FIFO_ST register. + 0x50 + 0x00000002 + - EP9_OUT - [19:19] + ROE + Sticky flag indicating the RX FIFO was read when empty. This read was ignored by the FIFO. + [3:3] read-write + oneToClear - EP9_IN - [18:18] + WOF + Sticky flag indicating the TX FIFO was written when full. This write was ignored by the FIFO. + [2:2] read-write + oneToClear - EP8_OUT - [17:17] - read-write + RDY + Value is 1 if this core's TX FIFO is not full (i.e. if FIFO_WR is ready for more data) + [1:1] + read-only - EP8_IN - [16:16] - read-write + VLD + Value is 1 if this core's RX FIFO is not empty (i.e. if FIFO_RD is valid) + [0:0] + read-only + + + + FIFO_WR + Write access to this core's TX FIFO + 0x54 + 0x00000000 + - EP7_OUT - [15:15] - read-write + FIFO_WR + [31:0] + write-only + + + + FIFO_RD + Read access to this core's RX FIFO + 0x58 + 0x00000000 + - EP7_IN - [14:14] - read-write + FIFO_RD + [31:0] + read-only + modify + + + + SPINLOCK_ST + Spinlock state + A bitmap containing the state of all 32 spinlocks (1=locked). + Mainly intended for debugging. + 0x5C + 0x00000000 + - EP6_OUT - [13:13] - read-write + SPINLOCK_ST + [31:0] + read-only + + + + DIV_UDIVIDEND + Divider unsigned dividend + Write to the DIVIDEND operand of the divider, i.e. the p in `p / q`. + Any operand write starts a new calculation. The results appear in QUOTIENT, REMAINDER. + UDIVIDEND/SDIVIDEND are aliases of the same internal register. The U alias starts an + unsigned calculation, and the S alias starts a signed calculation. + 0x60 + 0x00000000 + - EP6_IN - [12:12] + DIV_UDIVIDEND + [31:0] read-write + + + + DIV_UDIVISOR + Divider unsigned divisor + Write to the DIVISOR operand of the divider, i.e. the q in `p / q`. + Any operand write starts a new calculation. The results appear in QUOTIENT, REMAINDER. + UDIVISOR/SDIVISOR are aliases of the same internal register. The U alias starts an + unsigned calculation, and the S alias starts a signed calculation. + 0x64 + 0x00000000 + - EP5_OUT - [11:11] + DIV_UDIVISOR + [31:0] read-write + + + + DIV_SDIVIDEND + Divider signed dividend + The same as UDIVIDEND, but starts a signed calculation, rather than unsigned. + 0x68 + 0x00000000 + - EP5_IN - [10:10] + DIV_SDIVIDEND + [31:0] read-write + + + + DIV_SDIVISOR + Divider signed divisor + The same as UDIVISOR, but starts a signed calculation, rather than unsigned. + 0x6C + 0x00000000 + - EP4_OUT - [9:9] + DIV_SDIVISOR + [31:0] read-write + + + + DIV_QUOTIENT + Divider result quotient + The result of `DIVIDEND / DIVISOR` (division). Contents undefined while CSR_READY is low. + For signed calculations, QUOTIENT is negative when the signs of DIVIDEND and DIVISOR differ. + This register can be written to directly, for context save/restore purposes. This halts any + in-progress calculation and sets the CSR_READY and CSR_DIRTY flags. + Reading from QUOTIENT clears the CSR_DIRTY flag, so should read results in the order + REMAINDER, QUOTIENT if CSR_DIRTY is used. + 0x70 + 0x00000000 + - EP4_IN - [8:8] + DIV_QUOTIENT + [31:0] read-write + + + + DIV_REMAINDER + Divider result remainder + The result of `DIVIDEND % DIVISOR` (modulo). Contents undefined while CSR_READY is low. + For signed calculations, REMAINDER is negative only when DIVIDEND is negative. + This register can be written to directly, for context save/restore purposes. This halts any + in-progress calculation and sets the CSR_READY and CSR_DIRTY flags. + 0x74 + 0x00000000 + - EP3_OUT - [7:7] + DIV_REMAINDER + [31:0] read-write + + + + DIV_CSR + Control and status register for divider. + 0x78 + 0x00000001 + - EP3_IN - [6:6] - read-write + DIRTY + Changes to 1 when any register is written, and back to 0 when QUOTIENT is read. + Software can use this flag to make save/restore more efficient (skip if not DIRTY). + If the flag is used in this way, it's recommended to either read QUOTIENT only, + or REMAINDER and then QUOTIENT, to prevent data loss on context switch. + [1:1] + read-only - EP2_OUT - [5:5] - read-write + READY + Reads as 0 when a calculation is in progress, 1 otherwise. + Writing an operand (xDIVIDEND, xDIVISOR) will immediately start a new calculation, no + matter if one is already in progress. + Writing to a result register will immediately terminate any in-progress calculation + and set the READY and DIRTY flags. + [0:0] + read-only + + + + INTERP0_ACCUM0 + Read/write access to accumulator 0 + 0x80 + 0x00000000 + - EP2_IN - [4:4] + INTERP0_ACCUM0 + [31:0] read-write + + + + INTERP0_ACCUM1 + Read/write access to accumulator 1 + 0x84 + 0x00000000 + - EP1_OUT - [3:3] + INTERP0_ACCUM1 + [31:0] read-write + + + + INTERP0_BASE0 + Read/write access to BASE0 register. + 0x88 + 0x00000000 + - EP1_IN - [2:2] + INTERP0_BASE0 + [31:0] read-write + + + + INTERP0_BASE1 + Read/write access to BASE1 register. + 0x8C + 0x00000000 + - EP0_OUT - [1:1] + INTERP0_BASE1 + [31:0] read-write + + + + INTERP0_BASE2 + Read/write access to BASE2 register. + 0x90 + 0x00000000 + - EP0_IN - [0:0] + INTERP0_BASE2 + [31:0] read-write - EP_ABORT_DONE - Device only: Used in conjunction with `EP_ABORT`. Set once an endpoint is idle so the programmer knows it is safe to modify the buffer control register. - 0x64 + INTERP0_POP_LANE0 + Read LANE0 result, and simultaneously write lane results to both accumulators (POP). + 0x94 0x00000000 - EP15_OUT - [31:31] - read-write - oneToClear + INTERP0_POP_LANE0 + [31:0] + read-only + + + + INTERP0_POP_LANE1 + Read LANE1 result, and simultaneously write lane results to both accumulators (POP). + 0x98 + 0x00000000 + - EP15_IN - [30:30] - read-write - oneToClear + INTERP0_POP_LANE1 + [31:0] + read-only + + + + INTERP0_POP_FULL + Read FULL result, and simultaneously write lane results to both accumulators (POP). + 0x9C + 0x00000000 + - EP14_OUT - [29:29] - read-write - oneToClear + INTERP0_POP_FULL + [31:0] + read-only + + + + INTERP0_PEEK_LANE0 + Read LANE0 result, without altering any internal state (PEEK). + 0xA0 + 0x00000000 + - EP14_IN - [28:28] - read-write - oneToClear + INTERP0_PEEK_LANE0 + [31:0] + read-only + + + + INTERP0_PEEK_LANE1 + Read LANE1 result, without altering any internal state (PEEK). + 0xA4 + 0x00000000 + - EP13_OUT - [27:27] - read-write - oneToClear + INTERP0_PEEK_LANE1 + [31:0] + read-only + + + + INTERP0_PEEK_FULL + Read FULL result, without altering any internal state (PEEK). + 0xA8 + 0x00000000 + - EP13_IN - [26:26] - read-write - oneToClear + INTERP0_PEEK_FULL + [31:0] + read-only + + + + INTERP0_CTRL_LANE0 + Control register for lane 0 + 0xAC + 0x00000000 + - EP12_OUT + OVERF + Set if either OVERF0 or OVERF1 is set. [25:25] - read-write - oneToClear + read-only - EP12_IN + OVERF1 + Indicates if any masked-off MSBs in ACCUM1 are set. [24:24] - read-write - oneToClear + read-only - EP11_OUT + OVERF0 + Indicates if any masked-off MSBs in ACCUM0 are set. [23:23] - read-write - oneToClear - - - EP11_IN - [22:22] - read-write - oneToClear + read-only - EP10_OUT + BLEND + Only present on INTERP0 on each core. If BLEND mode is enabled: + - LANE1 result is a linear interpolation between BASE0 and BASE1, controlled + by the 8 LSBs of lane 1 shift and mask value (a fractional number between + 0 and 255/256ths) + - LANE0 result does not have BASE0 added (yields only the 8 LSBs of lane 1 shift+mask value) + - FULL result does not have lane 1 shift+mask value added (BASE2 + lane 0 shift+mask) + LANE1 SIGNED flag controls whether the interpolation is signed or unsigned. [21:21] read-write - oneToClear - - - EP10_IN - [20:20] - read-write - oneToClear - EP9_OUT - [19:19] + FORCE_MSB + ORed into bits 29:28 of the lane result presented to the processor on the bus. + No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence + of pointers into flash or SRAM. + [20:19] read-write - oneToClear - EP9_IN + ADD_RAW + If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result. [18:18] read-write - oneToClear - EP8_OUT + CROSS_RESULT + If 1, feed the opposite lane's result into this lane's accumulator on POP. [17:17] read-write - oneToClear - EP8_IN + CROSS_INPUT + If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. + Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass) [16:16] read-write - oneToClear - EP7_OUT + SIGNED + If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits + before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor. [15:15] read-write - oneToClear - - - EP7_IN - [14:14] - read-write - oneToClear - - - EP6_OUT - [13:13] - read-write - oneToClear - - - EP6_IN - [12:12] - read-write - oneToClear - - - EP5_OUT - [11:11] - read-write - oneToClear - EP5_IN - [10:10] + MASK_MSB + The most-significant bit allowed to pass by the mask (inclusive) + Setting MSB < LSB may cause chip to turn inside-out + [14:10] read-write - oneToClear - EP4_OUT - [9:9] + MASK_LSB + The least-significant bit allowed to pass by the mask (inclusive) + [9:5] read-write - oneToClear - EP4_IN - [8:8] + SHIFT + Logical right-shift applied to accumulator before masking + [4:0] read-write - oneToClear + + + + INTERP0_CTRL_LANE1 + Control register for lane 1 + 0xB0 + 0x00000000 + - EP3_OUT - [7:7] + FORCE_MSB + ORed into bits 29:28 of the lane result presented to the processor on the bus. + No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence + of pointers into flash or SRAM. + [20:19] read-write - oneToClear - EP3_IN - [6:6] + ADD_RAW + If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result. + [18:18] read-write - oneToClear - EP2_OUT - [5:5] + CROSS_RESULT + If 1, feed the opposite lane's result into this lane's accumulator on POP. + [17:17] read-write - oneToClear - EP2_IN - [4:4] + CROSS_INPUT + If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. + Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass) + [16:16] read-write - oneToClear - EP1_OUT - [3:3] + SIGNED + If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits + before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor. + [15:15] read-write - oneToClear - EP1_IN - [2:2] + MASK_MSB + The most-significant bit allowed to pass by the mask (inclusive) + Setting MSB < LSB may cause chip to turn inside-out + [14:10] read-write - oneToClear - EP0_OUT - [1:1] + MASK_LSB + The least-significant bit allowed to pass by the mask (inclusive) + [9:5] read-write - oneToClear - EP0_IN - [0:0] + SHIFT + Logical right-shift applied to accumulator before masking + [4:0] read-write - oneToClear - EP_STALL_ARM - Device: this bit must be set in conjunction with the `STALL` bit in the buffer control register to send a STALL on EP0. The device controller clears these bits when a SETUP packet is received because the USB spec requires that a STALL condition is cleared when a SETUP packet is received. - 0x68 + INTERP0_ACCUM0_ADD + Values written here are atomically added to ACCUM0 + Reading yields lane 0's raw shift and mask value (BASE0 not added). + 0xB4 0x00000000 - EP0_OUT - [1:1] - read-write - - - EP0_IN - [0:0] + INTERP0_ACCUM0_ADD + [23:0] read-write - NAK_POLL - Used by the host controller. Sets the wait time in microseconds before trying again if the device replies with a NAK. - 0x6C - 0x00100010 + INTERP0_ACCUM1_ADD + Values written here are atomically added to ACCUM1 + Reading yields lane 1's raw shift and mask value (BASE1 not added). + 0xB8 + 0x00000000 - DELAY_FS - NAK polling interval for a full speed device - [25:16] - read-write - - - DELAY_LS - NAK polling interval for a low speed device - [9:0] + INTERP0_ACCUM1_ADD + [23:0] read-write - EP_STATUS_STALL_NAK - Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` bits are set. For EP0 this comes from `SIE_CTRL`. For all other endpoints it comes from the endpoint control register. - 0x70 + INTERP0_BASE_1AND0 + On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously. + Each half is sign-extended to 32 bits if that lane's SIGNED flag is set. + 0xBC 0x00000000 - EP15_OUT - [31:31] - read-write - oneToClear + INTERP0_BASE_1AND0 + [31:0] + write-only + + + + INTERP1_ACCUM0 + Read/write access to accumulator 0 + 0xC0 + 0x00000000 + - EP15_IN - [30:30] + INTERP1_ACCUM0 + [31:0] read-write - oneToClear + + + + INTERP1_ACCUM1 + Read/write access to accumulator 1 + 0xC4 + 0x00000000 + - EP14_OUT - [29:29] + INTERP1_ACCUM1 + [31:0] read-write - oneToClear + + + + INTERP1_BASE0 + Read/write access to BASE0 register. + 0xC8 + 0x00000000 + - EP14_IN - [28:28] + INTERP1_BASE0 + [31:0] read-write - oneToClear + + + + INTERP1_BASE1 + Read/write access to BASE1 register. + 0xCC + 0x00000000 + - EP13_OUT - [27:27] + INTERP1_BASE1 + [31:0] read-write - oneToClear + + + + INTERP1_BASE2 + Read/write access to BASE2 register. + 0xD0 + 0x00000000 + - EP13_IN - [26:26] + INTERP1_BASE2 + [31:0] read-write - oneToClear + + + + INTERP1_POP_LANE0 + Read LANE0 result, and simultaneously write lane results to both accumulators (POP). + 0xD4 + 0x00000000 + - EP12_OUT - [25:25] - read-write - oneToClear + INTERP1_POP_LANE0 + [31:0] + read-only + + + + INTERP1_POP_LANE1 + Read LANE1 result, and simultaneously write lane results to both accumulators (POP). + 0xD8 + 0x00000000 + - EP12_IN - [24:24] - read-write - oneToClear + INTERP1_POP_LANE1 + [31:0] + read-only + + + + INTERP1_POP_FULL + Read FULL result, and simultaneously write lane results to both accumulators (POP). + 0xDC + 0x00000000 + - EP11_OUT - [23:23] - read-write - oneToClear + INTERP1_POP_FULL + [31:0] + read-only + + + + INTERP1_PEEK_LANE0 + Read LANE0 result, without altering any internal state (PEEK). + 0xE0 + 0x00000000 + - EP11_IN - [22:22] - read-write - oneToClear + INTERP1_PEEK_LANE0 + [31:0] + read-only + + + + INTERP1_PEEK_LANE1 + Read LANE1 result, without altering any internal state (PEEK). + 0xE4 + 0x00000000 + - EP10_OUT - [21:21] - read-write - oneToClear + INTERP1_PEEK_LANE1 + [31:0] + read-only + + + + INTERP1_PEEK_FULL + Read FULL result, without altering any internal state (PEEK). + 0xE8 + 0x00000000 + - EP10_IN - [20:20] - read-write - oneToClear + INTERP1_PEEK_FULL + [31:0] + read-only + + + + INTERP1_CTRL_LANE0 + Control register for lane 0 + 0xEC + 0x00000000 + - EP9_OUT - [19:19] - read-write - oneToClear + OVERF + Set if either OVERF0 or OVERF1 is set. + [25:25] + read-only - EP9_IN - [18:18] - read-write - oneToClear + OVERF1 + Indicates if any masked-off MSBs in ACCUM1 are set. + [24:24] + read-only - EP8_OUT - [17:17] - read-write - oneToClear + OVERF0 + Indicates if any masked-off MSBs in ACCUM0 are set. + [23:23] + read-only - EP8_IN - [16:16] + CLAMP + Only present on INTERP1 on each core. If CLAMP mode is enabled: + - LANE0 result is shifted and masked ACCUM0, clamped by a lower bound of + BASE0 and an upper bound of BASE1. + - Signedness of these comparisons is determined by LANE0_CTRL_SIGNED + [22:22] read-write - oneToClear - EP7_OUT - [15:15] + FORCE_MSB + ORed into bits 29:28 of the lane result presented to the processor on the bus. + No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence + of pointers into flash or SRAM. + [20:19] read-write - oneToClear - EP7_IN - [14:14] + ADD_RAW + If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result. + [18:18] read-write - oneToClear - EP6_OUT - [13:13] + CROSS_RESULT + If 1, feed the opposite lane's result into this lane's accumulator on POP. + [17:17] read-write - oneToClear - EP6_IN - [12:12] + CROSS_INPUT + If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. + Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass) + [16:16] read-write - oneToClear - EP5_OUT - [11:11] + SIGNED + If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits + before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor. + [15:15] read-write - oneToClear - EP5_IN - [10:10] + MASK_MSB + The most-significant bit allowed to pass by the mask (inclusive) + Setting MSB < LSB may cause chip to turn inside-out + [14:10] read-write - oneToClear - EP4_OUT - [9:9] + MASK_LSB + The least-significant bit allowed to pass by the mask (inclusive) + [9:5] read-write - oneToClear - EP4_IN - [8:8] + SHIFT + Logical right-shift applied to accumulator before masking + [4:0] read-write - oneToClear + + + + INTERP1_CTRL_LANE1 + Control register for lane 1 + 0xF0 + 0x00000000 + - EP3_OUT - [7:7] + FORCE_MSB + ORed into bits 29:28 of the lane result presented to the processor on the bus. + No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence + of pointers into flash or SRAM. + [20:19] read-write - oneToClear - EP3_IN - [6:6] + ADD_RAW + If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result. + [18:18] read-write - oneToClear - EP2_OUT - [5:5] + CROSS_RESULT + If 1, feed the opposite lane's result into this lane's accumulator on POP. + [17:17] read-write - oneToClear - EP2_IN - [4:4] + CROSS_INPUT + If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. + Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass) + [16:16] read-write - oneToClear - EP1_OUT - [3:3] + SIGNED + If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits + before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor. + [15:15] read-write - oneToClear - EP1_IN - [2:2] + MASK_MSB + The most-significant bit allowed to pass by the mask (inclusive) + Setting MSB < LSB may cause chip to turn inside-out + [14:10] read-write - oneToClear - EP0_OUT - [1:1] + MASK_LSB + The least-significant bit allowed to pass by the mask (inclusive) + [9:5] read-write - oneToClear - EP0_IN - [0:0] + SHIFT + Logical right-shift applied to accumulator before masking + [4:0] read-write - oneToClear - USB_MUXING - Where to connect the USB controller. Should be to_phy by default. - 0x74 + INTERP1_ACCUM0_ADD + Values written here are atomically added to ACCUM0 + Reading yields lane 0's raw shift and mask value (BASE0 not added). + 0xF4 0x00000000 - SOFTCON - [3:3] + INTERP1_ACCUM0_ADD + [23:0] read-write + + + + INTERP1_ACCUM1_ADD + Values written here are atomically added to ACCUM1 + Reading yields lane 1's raw shift and mask value (BASE1 not added). + 0xF8 + 0x00000000 + - TO_DIGITAL_PAD - [2:2] + INTERP1_ACCUM1_ADD + [23:0] read-write + + + + INTERP1_BASE_1AND0 + On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously. + Each half is sign-extended to 32 bits if that lane's SIGNED flag is set. + 0xFC + 0x00000000 + - TO_EXTPHY - [1:1] - read-write + INTERP1_BASE_1AND0 + [31:0] + write-only + + + + 32 + 0x4 + 0-31 + SPINLOCK%s + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x100 + 0x00000000 + - TO_PHY - [0:0] + SPINLOCK0 + [31:0] read-write + modify + + + + USBCTRL_REGS + USB FS/LS controller device registers + 0x50110000 + + 0x0 + 0x9C + registers + + + USBCTRL_IRQ + 5 + + - USB_PWR - Overrides for the power signals in the event that the VBUS signals are not hooked up to GPIO. Set the value of the override and then the override enable to switch over to the override value. - 0x78 + ADDR_ENDP + Device address and endpoint control + 0x0 0x00000000 - OVERCURR_DETECT_EN - [5:5] + ENDPOINT + Device endpoint to send data to. Only valid for HOST mode. + [19:16] read-write - OVERCURR_DETECT - [4:4] + ADDRESS + In device mode, the address that the device should respond to. Set in response to a SET_ADDR setup packet from the host. In host mode set to the address of the device to communicate with. + [6:0] read-write + + + + 15 + 0x4 + 1-15 + HOST_ADDR_ENDP%s + Interrupt endpoints. Only valid in HOST mode. + 0x4 + 0x00000000 + - VBUS_DETECT_OVERRIDE_EN - [3:3] + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] read-write - VBUS_DETECT - [2:2] + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] read-write - VBUS_EN_OVERRIDE_EN - [1:1] + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] read-write - VBUS_EN - [0:0] + ADDRESS + Device address + [6:0] read-write - USBPHY_DIRECT - This register allows for direct control of the USB phy. Use in conjunction with usbphy_direct_override register to enable each override bit. - 0x7C + MAIN_CTRL + Main control register + 0x40 0x00000000 - DM_OVV - DM over voltage - [22:22] - read-only - - - DP_OVV - DP over voltage - [21:21] - read-only - - - DM_OVCN - DM overcurrent - [20:20] - read-only - - - DP_OVCN - DP overcurrent - [19:19] - read-only - - - RX_DM - DPM pin state - [18:18] - read-only - - - RX_DP - DPP pin state - [17:17] - read-only + SIM_TIMING + Reduced timings for simulation + [31:31] + read-write - RX_DD - Differential RX - [16:16] - read-only + HOST_NDEVICE + Device mode = 0, Host mode = 1 + [1:1] + read-write - TX_DIFFMODE - TX_DIFFMODE=0: Single ended mode\n - TX_DIFFMODE=1: Differential drive mode (TX_DM, TX_DM_OE ignored) - [15:15] + CONTROLLER_EN + Enable controller + [0:0] read-write + + + + SOF_WR + Set the SOF (Start of Frame) frame number in the host controller. The SOF packet is sent every 1ms and the host will increment the frame number by 1 each time. + 0x44 + 0x00000000 + - TX_FSSLEW - TX_FSSLEW=0: Low speed slew rate\n - TX_FSSLEW=1: Full speed slew rate - [14:14] - read-write + COUNT + [10:0] + write-only + + + + SOF_RD + Read the last SOF (Start of Frame) frame number seen. In device mode the last SOF received from the host. In host mode the last SOF sent by the host. + 0x48 + 0x00000000 + - TX_PD - TX power down override (if override enable is set). 1 = powered down. - [13:13] - read-write + COUNT + [10:0] + read-only + + + + SIE_CTRL + SIE control register + 0x4C + 0x00000000 + - RX_PD - RX power down override (if override enable is set). 1 = powered down. - [12:12] + EP0_INT_STALL + Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a STALL + [31:31] read-write - TX_DM - Output data. TX_DIFFMODE=1, Ignored\n - TX_DIFFMODE=0, Drives DPM only. TX_DM_OE=1 to enable drive. DPM=TX_DM - [11:11] + EP0_DOUBLE_BUF + Device: EP0 single buffered = 0, double buffered = 1 + [30:30] read-write - TX_DP - Output data. If TX_DIFFMODE=1, Drives DPP/DPM diff pair. TX_DP_OE=1 to enable drive. DPP=TX_DP, DPM=~TX_DP\n - If TX_DIFFMODE=0, Drives DPP only. TX_DP_OE=1 to enable drive. DPP=TX_DP - [10:10] + EP0_INT_1BUF + Device: Set bit in BUFF_STATUS for every buffer completed on EP0 + [29:29] read-write - TX_DM_OE - Output enable. If TX_DIFFMODE=1, Ignored.\n - If TX_DIFFMODE=0, OE for DPM only. 0 - DPM in Hi-Z state; 1 - DPM driving - [9:9] + EP0_INT_2BUF + Device: Set bit in BUFF_STATUS for every 2 buffers completed on EP0 + [28:28] read-write - TX_DP_OE - Output enable. If TX_DIFFMODE=1, OE for DPP/DPM diff pair. 0 - DPP/DPM in Hi-Z state; 1 - DPP/DPM driving\n - If TX_DIFFMODE=0, OE for DPP only. 0 - DPP in Hi-Z state; 1 - DPP driving - [8:8] + EP0_INT_NAK + Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a NAK + [27:27] read-write - DM_PULLDN_EN - DM pull down enable - [6:6] + DIRECT_EN + Direct bus drive enable + [26:26] read-write - DM_PULLUP_EN - DM pull up enable - [5:5] + DIRECT_DP + Direct control of DP + [25:25] read-write - DM_PULLUP_HISEL - Enable the second DM pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2 - [4:4] + DIRECT_DM + Direct control of DM + [24:24] read-write - DP_PULLDN_EN - DP pull down enable - [2:2] + TRANSCEIVER_PD + Power down bus transceiver + [18:18] read-write - DP_PULLUP_EN - DP pull up enable - [1:1] + RPU_OPT + Device: Pull-up strength (0=1K2, 1=2k3) + [17:17] read-write - DP_PULLUP_HISEL - Enable the second DP pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2 - [0:0] + PULLUP_EN + Device: Enable pull up resistor + [16:16] read-write - - - - USBPHY_DIRECT_OVERRIDE - Override enable for each control in usbphy_direct - 0x80 - 0x00000000 - - TX_DIFFMODE_OVERRIDE_EN + PULLDOWN_EN + Host: Enable pull down resistors [15:15] read-write - DM_PULLUP_OVERRIDE_EN + RESET_BUS + Host: Reset bus + [13:13] + write-only + + + RESUME + Device: Remote wakeup. Device can initiate its own resume after suspend. [12:12] - read-write + write-only - TX_FSSLEW_OVERRIDE_EN + VBUS_EN + Host: Enable VBUS [11:11] read-write - TX_PD_OVERRIDE_EN + KEEP_ALIVE_EN + Host: Enable keep alive packet (for low speed bus) [10:10] read-write - RX_PD_OVERRIDE_EN + SOF_EN + Host: Enable SOF generation (for full speed bus) [9:9] read-write - TX_DM_OVERRIDE_EN + SOF_SYNC + Host: Delay packet(s) until after SOF [8:8] read-write - TX_DP_OVERRIDE_EN - [7:7] - read-write - - - TX_DM_OE_OVERRIDE_EN + PREAMBLE_EN + Host: Preable enable for LS device on FS hub [6:6] read-write - TX_DP_OE_OVERRIDE_EN - [5:5] - read-write - - - DM_PULLDN_EN_OVERRIDE_EN + STOP_TRANS + Host: Stop transaction [4:4] - read-write + write-only - DP_PULLDN_EN_OVERRIDE_EN + RECEIVE_DATA + Host: Receive transaction (IN to host) [3:3] read-write - DP_PULLUP_EN_OVERRIDE_EN + SEND_DATA + Host: Send transaction (OUT from host) [2:2] read-write - DM_PULLUP_HISEL_OVERRIDE_EN + SEND_SETUP + Host: Send Setup packet [1:1] read-write - DP_PULLUP_HISEL_OVERRIDE_EN + START_TRANS + Host: Start transaction [0:0] - read-write - - - - - USBPHY_TRIM - Used to adjust trim values of USB phy pull down resistors. - 0x84 - 0x00001F1F - - - DM_PULLDN_TRIM - Value to drive to USB PHY\n - DM pulldown resistor trim control\n - Experimental data suggests that the reset value will work, but this register allows adjustment if required - [12:8] - read-write - - - DP_PULLDN_TRIM - Value to drive to USB PHY\n - DP pulldown resistor trim control\n - Experimental data suggests that the reset value will work, but this register allows adjustment if required - [4:0] - read-write + write-only - INTR - Raw Interrupts - 0x8C + SIE_STATUS + SIE status register + 0x50 0x00000000 - EP_STALL_NAK - Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK. - [19:19] - read-only - - - ABORT_DONE - Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE. - [18:18] - read-only - - - DEV_SOF - Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD - [17:17] - read-only - - - SETUP_REQ - Device. Source: SIE_STATUS.SETUP_REC - [16:16] - read-only - - - DEV_RESUME_FROM_HOST - Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME - [15:15] - read-only - - - DEV_SUSPEND - Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED - [14:14] - read-only - - - DEV_CONN_DIS - Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED - [13:13] - read-only - - - BUS_RESET - Source: SIE_STATUS.BUS_RESET - [12:12] - read-only - - - VBUS_DETECT - Source: SIE_STATUS.VBUS_DETECTED - [11:11] - read-only - - - STALL - Source: SIE_STATUS.STALL_REC - [10:10] - read-only - - - ERROR_CRC - Source: SIE_STATUS.CRC_ERROR - [9:9] - read-only - - - ERROR_BIT_STUFF - Source: SIE_STATUS.BIT_STUFF_ERROR - [8:8] - read-only - - - ERROR_RX_OVERFLOW - Source: SIE_STATUS.RX_OVERFLOW - [7:7] - read-only - - - ERROR_RX_TIMEOUT - Source: SIE_STATUS.RX_TIMEOUT - [6:6] - read-only + DATA_SEQ_ERROR + Data Sequence Error. + + The device can raise a sequence error in the following conditions: + + * A SETUP packet is received followed by a DATA1 packet (data phase should always be DATA0) * An OUT packet is received from the host but doesn't match the data pid in the buffer control register read from DPSRAM + + The host can raise a data sequence error in the following conditions: + + * An IN packet from the device has the wrong data PID + [31:31] + read-write + oneToClear - ERROR_DATA_SEQ - Source: SIE_STATUS.DATA_SEQ_ERROR - [5:5] - read-only + ACK_REC + ACK received. Raised by both host and device. + [30:30] + read-write + oneToClear - BUFF_STATUS - Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS. - [4:4] - read-only + STALL_REC + Host: STALL received + [29:29] + read-write + oneToClear - TRANS_COMPLETE - Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit. - [3:3] - read-only + NAK_REC + Host: NAK received + [28:28] + read-write + oneToClear - HOST_SOF - Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD - [2:2] - read-only + RX_TIMEOUT + RX timeout is raised by both the host and device if an ACK is not received in the maximum time specified by the USB spec. + [27:27] + read-write + oneToClear - HOST_RESUME - Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME - [1:1] - read-only + RX_OVERFLOW + RX overflow is raised by the Serial RX engine if the incoming data is too fast. + [26:26] + read-write + oneToClear - HOST_CONN_DIS - Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED - [0:0] - read-only + BIT_STUFF_ERROR + Bit Stuff Error. Raised by the Serial RX engine. + [25:25] + read-write + oneToClear - - - - INTE - Interrupt Enable - 0x90 - 0x00000000 - - EP_STALL_NAK - Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK. + CRC_ERROR + CRC Error. Raised by the Serial RX engine. + [24:24] + read-write + oneToClear + + + BUS_RESET + Device: bus reset received [19:19] read-write + oneToClear - ABORT_DONE - Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE. + TRANS_COMPLETE + Transaction complete. + + Raised by device if: + + * An IN or OUT packet is sent with the `LAST_BUFF` bit set in the buffer control register + + Raised by host if: + + * A setup packet is sent when no data in or data out transaction follows * An IN packet is received and the `LAST_BUFF` bit is set in the buffer control register * An IN packet is received with zero length * An OUT packet is sent and the `LAST_BUFF` bit is set [18:18] read-write + oneToClear - DEV_SOF - Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD + SETUP_REC + Device: Setup packet received [17:17] read-write + oneToClear - SETUP_REQ - Device. Source: SIE_STATUS.SETUP_REC + CONNECTED + Device: connected [16:16] - read-write + read-only - DEV_RESUME_FROM_HOST - Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME - [15:15] + RESUME + Host: Device has initiated a remote resume. Device: host has initiated a resume. + [11:11] read-write + oneToClear - DEV_SUSPEND - Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED - [14:14] - read-write + VBUS_OVER_CURR + VBUS over current detected + [10:10] + read-only - DEV_CONN_DIS - Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED - [13:13] + SPEED + Host: device speed. Disconnected = 00, LS = 01, FS = 10 + [9:8] + read-only + + + SUSPENDED + Bus in suspended state. Valid for device and host. Host and device will go into suspend if neither Keep Alive / SOF frames are enabled. + [4:4] read-write + oneToClear - BUS_RESET - Source: SIE_STATUS.BUS_RESET - [12:12] + LINE_STATE + USB bus line state + [3:2] + read-only + + LINE_STATE + + SE0 + SE0 + 0 + + + J + J + 1 + + + K + K + 2 + + + SE1 + SE1 + 3 + + + + + VBUS_DETECTED + Device: VBUS Detected + [0:0] + read-only + + + + + INT_EP_CTRL + interrupt endpoint control register + 0x54 + 0x00000000 + + + INT_EP_ACTIVE + Host: Enable interrupt endpoint 1 => 15 + [15:1] read-write + + + + BUFF_STATUS + Buffer status register. A bit set here indicates that a buffer has completed on the endpoint (if the buffer interrupt is enabled). It is possible for 2 buffers to be completed, so clearing the buffer status bit may instantly re set it on the next clock cycle. + 0x58 + 0x00000000 + - VBUS_DETECT - Source: SIE_STATUS.VBUS_DETECTED - [11:11] + EP15_OUT + [31:31] read-write + oneToClear - STALL - Source: SIE_STATUS.STALL_REC - [10:10] + EP15_IN + [30:30] read-write + oneToClear - ERROR_CRC - Source: SIE_STATUS.CRC_ERROR - [9:9] + EP14_OUT + [29:29] read-write + oneToClear - ERROR_BIT_STUFF - Source: SIE_STATUS.BIT_STUFF_ERROR - [8:8] + EP14_IN + [28:28] read-write + oneToClear - ERROR_RX_OVERFLOW - Source: SIE_STATUS.RX_OVERFLOW - [7:7] + EP13_OUT + [27:27] read-write + oneToClear - ERROR_RX_TIMEOUT - Source: SIE_STATUS.RX_TIMEOUT - [6:6] + EP13_IN + [26:26] read-write + oneToClear - ERROR_DATA_SEQ - Source: SIE_STATUS.DATA_SEQ_ERROR - [5:5] + EP12_OUT + [25:25] read-write + oneToClear - BUFF_STATUS - Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS. - [4:4] + EP12_IN + [24:24] read-write + oneToClear - TRANS_COMPLETE - Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit. - [3:3] + EP11_OUT + [23:23] read-write + oneToClear - HOST_SOF - Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD - [2:2] + EP11_IN + [22:22] read-write + oneToClear - HOST_RESUME - Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME - [1:1] + EP10_OUT + [21:21] read-write + oneToClear - HOST_CONN_DIS - Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED - [0:0] + EP10_IN + [20:20] read-write + oneToClear - - - - INTF - Interrupt Force - 0x94 - 0x00000000 - - EP_STALL_NAK - Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK. + EP9_OUT [19:19] read-write + oneToClear - - ABORT_DONE - Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE. + + EP9_IN [18:18] read-write + oneToClear - DEV_SOF - Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD + EP8_OUT [17:17] read-write + oneToClear - SETUP_REQ - Device. Source: SIE_STATUS.SETUP_REC + EP8_IN [16:16] read-write + oneToClear - DEV_RESUME_FROM_HOST - Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME + EP7_OUT [15:15] read-write + oneToClear - DEV_SUSPEND - Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED + EP7_IN [14:14] read-write + oneToClear - DEV_CONN_DIS - Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED + EP6_OUT [13:13] read-write + oneToClear - BUS_RESET - Source: SIE_STATUS.BUS_RESET + EP6_IN [12:12] read-write + oneToClear - VBUS_DETECT - Source: SIE_STATUS.VBUS_DETECTED + EP5_OUT [11:11] read-write + oneToClear - STALL - Source: SIE_STATUS.STALL_REC + EP5_IN [10:10] read-write + oneToClear - ERROR_CRC - Source: SIE_STATUS.CRC_ERROR + EP4_OUT [9:9] read-write + oneToClear - ERROR_BIT_STUFF - Source: SIE_STATUS.BIT_STUFF_ERROR + EP4_IN [8:8] read-write + oneToClear - ERROR_RX_OVERFLOW - Source: SIE_STATUS.RX_OVERFLOW + EP3_OUT [7:7] read-write + oneToClear - ERROR_RX_TIMEOUT - Source: SIE_STATUS.RX_TIMEOUT + EP3_IN [6:6] read-write + oneToClear - ERROR_DATA_SEQ - Source: SIE_STATUS.DATA_SEQ_ERROR + EP2_OUT [5:5] read-write + oneToClear - BUFF_STATUS - Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS. + EP2_IN [4:4] read-write + oneToClear - TRANS_COMPLETE - Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit. + EP1_OUT [3:3] read-write + oneToClear - HOST_SOF - Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD + EP1_IN [2:2] read-write + oneToClear - HOST_RESUME - Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME + EP0_OUT [1:1] read-write + oneToClear - HOST_CONN_DIS - Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED + EP0_IN [0:0] read-write + oneToClear - INTS - Interrupt status after masking & forcing - 0x98 + BUFF_CPU_SHOULD_HANDLE + Which of the double buffers should be handled. Only valid if using an interrupt per buffer (i.e. not per 2 buffers). Not valid for host interrupt endpoint polling because they are only single buffered. + 0x5C 0x00000000 - EP_STALL_NAK - Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK. + EP15_OUT + [31:31] + read-only + + + EP15_IN + [30:30] + read-only + + + EP14_OUT + [29:29] + read-only + + + EP14_IN + [28:28] + read-only + + + EP13_OUT + [27:27] + read-only + + + EP13_IN + [26:26] + read-only + + + EP12_OUT + [25:25] + read-only + + + EP12_IN + [24:24] + read-only + + + EP11_OUT + [23:23] + read-only + + + EP11_IN + [22:22] + read-only + + + EP10_OUT + [21:21] + read-only + + + EP10_IN + [20:20] + read-only + + + EP9_OUT [19:19] read-only - ABORT_DONE - Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE. + EP9_IN [18:18] read-only - DEV_SOF - Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD + EP8_OUT [17:17] read-only - SETUP_REQ - Device. Source: SIE_STATUS.SETUP_REC + EP8_IN [16:16] read-only - DEV_RESUME_FROM_HOST - Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME + EP7_OUT [15:15] read-only - DEV_SUSPEND - Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED + EP7_IN [14:14] read-only - DEV_CONN_DIS - Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED + EP6_OUT [13:13] read-only - BUS_RESET - Source: SIE_STATUS.BUS_RESET + EP6_IN [12:12] read-only - VBUS_DETECT - Source: SIE_STATUS.VBUS_DETECTED + EP5_OUT [11:11] read-only - STALL - Source: SIE_STATUS.STALL_REC + EP5_IN [10:10] read-only - ERROR_CRC - Source: SIE_STATUS.CRC_ERROR + EP4_OUT [9:9] read-only - ERROR_BIT_STUFF - Source: SIE_STATUS.BIT_STUFF_ERROR + EP4_IN [8:8] read-only - ERROR_RX_OVERFLOW - Source: SIE_STATUS.RX_OVERFLOW + EP3_OUT [7:7] read-only - ERROR_RX_TIMEOUT - Source: SIE_STATUS.RX_TIMEOUT + EP3_IN [6:6] read-only - ERROR_DATA_SEQ - Source: SIE_STATUS.DATA_SEQ_ERROR + EP2_OUT [5:5] read-only - BUFF_STATUS - Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS. + EP2_IN [4:4] read-only - TRANS_COMPLETE - Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit. + EP1_OUT [3:3] read-only - HOST_SOF - Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD + EP1_IN [2:2] read-only - HOST_RESUME - Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME + EP0_OUT [1:1] read-only - HOST_CONN_DIS - Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED + EP0_IN [0:0] read-only - - - - PIO0 - 1 - Programmable IO block - 0x50200000 - 0x20 - - 0x0 - 0x1000 - registers - - - PIO0_IRQ_0 - 7 - - - PIO0_IRQ_1 - 8 - - - CTRL - PIO control register - 0x0 + EP_ABORT + Device only: Can be set to ignore the buffer control register for this endpoint in case you would like to revoke a buffer. A NAK will be sent for every access to the endpoint until this bit is cleared. A corresponding bit in `EP_ABORT_DONE` is set when it is safe to modify the buffer control register. + 0x60 0x00000000 - CLKDIV_RESTART - Restart a state machine's clock divider from an initial phase of 0. Clock dividers are free-running, so once started, their output (including fractional jitter) is completely determined by the integer/fractional divisor configured in SMx_CLKDIV. This means that, if multiple clock dividers with the same divisor are restarted simultaneously, by writing multiple 1 bits to this field, the execution clocks of those state machines will run in precise lockstep.\n\n - Note that setting/clearing SM_ENABLE does not stop the clock divider from running, so once multiple state machines' clocks are synchronised, it is safe to disable/reenable a state machine, whilst keeping the clock dividers in sync.\n\n - Note also that CLKDIV_RESTART can be written to whilst the state machine is running, and this is useful to resynchronise clock dividers after the divisors (SMx_CLKDIV) have been changed on-the-fly. - [11:8] + EP15_OUT + [31:31] + read-write + + + EP15_IN + [30:30] + read-write + + + EP14_OUT + [29:29] + read-write + + + EP14_IN + [28:28] + read-write + + + EP13_OUT + [27:27] + read-write + + + EP13_IN + [26:26] + read-write + + + EP12_OUT + [25:25] + read-write + + + EP12_IN + [24:24] read-write - clear - SM_RESTART - Write 1 to instantly clear internal SM state which may be otherwise difficult to access and will affect future execution.\n\n - Specifically, the following are cleared: input and output shift counters; the contents of the input shift register; the delay counter; the waiting-on-IRQ state; any stalled instruction written to SMx_INSTR or run by OUT/MOV EXEC; any pin write left asserted due to OUT_STICKY.\n\n - The program counter, the contents of the output shift register and the X/Y scratch registers are not affected. - [7:4] + EP11_OUT + [23:23] read-write - clear - SM_ENABLE - Enable/disable each of the four state machines by writing 1/0 to each of these four bits. When disabled, a state machine will cease executing instructions, except those written directly to SMx_INSTR by the system. Multiple bits can be set/cleared at once to run/halt multiple state machines simultaneously. - [3:0] + EP11_IN + [22:22] read-write - - - - FSTAT - FIFO status register - 0x4 - 0x0F000F00 - - TXEMPTY - State machine TX FIFO is empty - [27:24] - read-only + EP10_OUT + [21:21] + read-write - TXFULL - State machine TX FIFO is full - [19:16] - read-only + EP10_IN + [20:20] + read-write - RXEMPTY - State machine RX FIFO is empty - [11:8] - read-only + EP9_OUT + [19:19] + read-write - RXFULL - State machine RX FIFO is full - [3:0] - read-only + EP9_IN + [18:18] + read-write - - - - FDEBUG - FIFO debug register - 0x8 - 0x00000000 - - TXSTALL - State machine has stalled on empty TX FIFO during a blocking PULL, or an OUT with autopull enabled. Write 1 to clear. - [27:24] + EP8_OUT + [17:17] read-write - oneToClear - TXOVER - TX FIFO overflow (i.e. write-on-full by the system) has occurred. Write 1 to clear. Note that write-on-full does not alter the state or contents of the FIFO in any way, but the data that the system attempted to write is dropped, so if this flag is set, your software has quite likely dropped some data on the floor. - [19:16] + EP8_IN + [16:16] read-write - oneToClear - RXUNDER - RX FIFO underflow (i.e. read-on-empty by the system) has occurred. Write 1 to clear. Note that read-on-empty does not perturb the state of the FIFO in any way, but the data returned by reading from an empty FIFO is undefined, so this flag generally only becomes set due to some kind of software error. - [11:8] + EP7_OUT + [15:15] read-write - oneToClear - RXSTALL - State machine has stalled on full RX FIFO during a blocking PUSH, or an IN with autopush enabled. This flag is also set when a nonblocking PUSH to a full FIFO took place, in which case the state machine has dropped data. Write 1 to clear. - [3:0] + EP7_IN + [14:14] read-write - oneToClear - - - - FLEVEL - FIFO levels - 0xC - 0x00000000 - - RX3 - [31:28] - read-only + EP6_OUT + [13:13] + read-write - TX3 - [27:24] - read-only + EP6_IN + [12:12] + read-write - RX2 - [23:20] - read-only + EP5_OUT + [11:11] + read-write - TX2 - [19:16] - read-only + EP5_IN + [10:10] + read-write - RX1 - [15:12] - read-only + EP4_OUT + [9:9] + read-write - TX1 - [11:8] - read-only + EP4_IN + [8:8] + read-write - RX0 - [7:4] - read-only + EP3_OUT + [7:7] + read-write - TX0 - [3:0] - read-only + EP3_IN + [6:6] + read-write - - - - 4 - 0x4 - 0-3 - TXF%s - Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO. - 0x10 - write-only - 0x00000000 - - - 4 - 0x4 - 0-3 - RXF%s - Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined. - 0x20 - read-only - 0x00000000 - - - IRQ - State machine IRQ flags register. Write 1 to clear. There are 8 state machine IRQ flags, which can be set, cleared, and waited on by the state machines. There's no fixed association between flags and state machines -- any state machine can use any flag.\n\n - Any of the 8 flags can be used for timing synchronisation between state machines, using IRQ and WAIT instructions. The lower four of these flags are also routed out to system-level interrupt requests, alongside FIFO status interrupts -- see e.g. IRQ0_INTE. - 0x30 - 0x00000000 - - IRQ - [7:0] + EP2_OUT + [5:5] read-write - oneToClear - - - - IRQ_FORCE - Writing a 1 to each of these bits will forcibly assert the corresponding IRQ. Note this is different to the INTF register: writing here affects PIO internal state. INTF just asserts the processor-facing IRQ signal for testing ISRs, and is not visible to the state machines. - 0x34 - 0x00000000 - - IRQ_FORCE - [7:0] - write-only + EP2_IN + [4:4] + read-write - - - - INPUT_SYNC_BYPASS - There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic from metastabilities. This increases input delay, and for fast synchronous IO (e.g. SPI) these synchronizers may need to be bypassed. Each bit in this register corresponds to one GPIO.\n - 0 -> input is synchronized (default)\n - 1 -> synchronizer is bypassed\n - If in doubt, leave this register as all zeroes. - 0x38 - read-write - 0x00000000 - - - DBG_PADOUT - Read to sample the pad output values PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0. - 0x3C - read-only - 0x00000000 - - - DBG_PADOE - Read to sample the pad output enables (direction) PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0. - 0x40 - read-only - 0x00000000 - - - DBG_CFGINFO - The PIO hardware has some free parameters that may vary between chip products.\n - These should be provided in the chip datasheet, but are also exposed here. - 0x44 - 0x00000000 - - IMEM_SIZE - The size of the instruction memory, measured in units of one instruction - [21:16] - read-only + EP1_OUT + [3:3] + read-write - SM_COUNT - The number of state machines this PIO instance is equipped with. - [11:8] - read-only + EP1_IN + [2:2] + read-write - FIFO_DEPTH - The depth of the state machine TX/RX FIFOs, measured in words.\n - Joining fifos via SHIFTCTRL_FJOIN gives one FIFO with double\n - this depth. - [5:0] - read-only + EP0_OUT + [1:1] + read-write + + + EP0_IN + [0:0] + read-write - 32 - 0x4 - 0-31 - INSTR_MEM%s - Write-only access to instruction memory location %s - 0x48 + EP_ABORT_DONE + Device only: Used in conjunction with `EP_ABORT`. Set once an endpoint is idle so the programmer knows it is safe to modify the buffer control register. + 0x64 0x00000000 - INSTR_MEM0 - [15:0] - write-only + EP15_OUT + [31:31] + read-write + oneToClear + + + EP15_IN + [30:30] + read-write + oneToClear + + + EP14_OUT + [29:29] + read-write + oneToClear + + + EP14_IN + [28:28] + read-write + oneToClear - - - - 4 - 0x18 - 0-3 - SM%s - Cluster SM%s, containing SM*_CLKDIV, SM*_EXECCTRL, SM*_SHIFTCTRL, SM*_ADDR, SM*_INSTR, SM*_PINCTRL - 0xC8 - - SM_CLKDIV - Clock divisor register for state machine 0\n - Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) - 0x0 - 0x00010000 - - - INT - Effective frequency is sysclk/(int + frac/256).\n - Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0. - [31:16] - read-write - - - FRAC - Fractional part of clock divisor - [15:8] - read-write - - - - - SM_EXECCTRL - Execution/behavioural settings for state machine 0 - 0x4 - 0x0001F000 - - - EXEC_STALLED - If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes. - [31:31] - read-only - - - SIDE_EN - If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit. - [30:30] - read-write - - - SIDE_PINDIR - If 1, side-set data is asserted to pin directions, instead of pin values - [29:29] - read-write - - - JMP_PIN - The GPIO number to use as condition for JMP PIN. Unaffected by input mapping. - [28:24] - read-write - - - OUT_EN_SEL - Which data bit to use for inline OUT enable - [23:19] - read-write - - - INLINE_OUT_EN - If 1, use a bit of OUT data as an auxiliary write enable\n - When used in conjunction with OUT_STICKY, writes with an enable of 0 will\n - deassert the latest pin write. This can create useful masking/override behaviour\n - due to the priority ordering of state machine pin writes (SM0 < SM1 < ...) - [18:18] - read-write - - - OUT_STICKY - Continuously assert the most recent OUT/SET to the pins - [17:17] - read-write - - - WRAP_TOP - After reaching this address, execution is wrapped to wrap_bottom.\n - If the instruction is a jump, and the jump condition is true, the jump takes priority. - [16:12] - read-write - - - WRAP_BOTTOM - After reaching wrap_top, execution is wrapped to this address. - [11:7] - read-write - - - STATUS_SEL - Comparison used for the MOV x, STATUS instruction. - [4:4] - read-write - - - TXLEVEL - All-ones if TX FIFO level < N, otherwise all-zeroes - 0 - - - RXLEVEL - All-ones if RX FIFO level < N, otherwise all-zeroes - 1 - - - - - STATUS_N - Comparison level for the MOV x, STATUS instruction - [3:0] - read-write - - - - - SM_SHIFTCTRL - Control behaviour of the input/output shift registers for state machine 0 - 0x8 - 0x000C0000 - - - FJOIN_RX - When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep.\n - TX FIFO is disabled as a result (always reads as both full and empty).\n - FIFOs are flushed when this bit is changed. - [31:31] - read-write - - - FJOIN_TX - When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep.\n - RX FIFO is disabled as a result (always reads as both full and empty).\n - FIFOs are flushed when this bit is changed. - [30:30] - read-write - - - PULL_THRESH - Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place.\n - Write 0 for value of 32. - [29:25] - read-write - - - PUSH_THRESH - Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place.\n - Write 0 for value of 32. - [24:20] - read-write - - - OUT_SHIFTDIR - 1 = shift out of output shift register to right. 0 = to left. - [19:19] - read-write - - - IN_SHIFTDIR - 1 = shift input shift register to right (data enters from left). 0 = to left. - [18:18] - read-write - - - AUTOPULL - Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH. - [17:17] - read-write - - - AUTOPUSH - Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH. - [16:16] - read-write - - - - - SM_ADDR - Current instruction address of state machine 0 - 0xC - 0x00000000 - - - SM0_ADDR - [4:0] - read-only - - - - - SM_INSTR - Read to see the instruction currently addressed by state machine 0's program counter\n - Write to execute an instruction immediately (including jumps) and then resume execution. - 0x10 - 0x00000000 - - - SM0_INSTR - [15:0] - read-write - - - - - SM_PINCTRL - State machine pin control - 0x14 - 0x14000000 - - - SIDESET_COUNT - The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay). - [31:29] - read-write - - - SET_COUNT - The number of pins asserted by a SET. In the range 0 to 5 inclusive. - [28:26] - read-write - - - OUT_COUNT - The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive. - [25:20] - read-write - - - IN_BASE - The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number. - [19:15] - read-write - - - SIDESET_BASE - The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins. - [14:10] - read-write - - - SET_BASE - The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data. - [9:5] - read-write - - - OUT_BASE - The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data. - [4:0] - read-write - - - - + + EP13_OUT + [27:27] + read-write + oneToClear + + + EP13_IN + [26:26] + read-write + oneToClear + + + EP12_OUT + [25:25] + read-write + oneToClear + + + EP12_IN + [24:24] + read-write + oneToClear + + + EP11_OUT + [23:23] + read-write + oneToClear + + + EP11_IN + [22:22] + read-write + oneToClear + + + EP10_OUT + [21:21] + read-write + oneToClear + + + EP10_IN + [20:20] + read-write + oneToClear + + + EP9_OUT + [19:19] + read-write + oneToClear + + + EP9_IN + [18:18] + read-write + oneToClear + + + EP8_OUT + [17:17] + read-write + oneToClear + + + EP8_IN + [16:16] + read-write + oneToClear + + + EP7_OUT + [15:15] + read-write + oneToClear + + + EP7_IN + [14:14] + read-write + oneToClear + + + EP6_OUT + [13:13] + read-write + oneToClear + + + EP6_IN + [12:12] + read-write + oneToClear + + + EP5_OUT + [11:11] + read-write + oneToClear + + + EP5_IN + [10:10] + read-write + oneToClear + + + EP4_OUT + [9:9] + read-write + oneToClear + + + EP4_IN + [8:8] + read-write + oneToClear + + + EP3_OUT + [7:7] + read-write + oneToClear + + + EP3_IN + [6:6] + read-write + oneToClear + + + EP2_OUT + [5:5] + read-write + oneToClear + + + EP2_IN + [4:4] + read-write + oneToClear + + + EP1_OUT + [3:3] + read-write + oneToClear + + + EP1_IN + [2:2] + read-write + oneToClear + + + EP0_OUT + [1:1] + read-write + oneToClear + + + EP0_IN + [0:0] + read-write + oneToClear + + + - INTR - Raw Interrupts - 0x128 + EP_STALL_ARM + Device: this bit must be set in conjunction with the `STALL` bit in the buffer control register to send a STALL on EP0. The device controller clears these bits when a SETUP packet is received because the USB spec requires that a STALL condition is cleared when a SETUP packet is received. + 0x68 + 0x00000000 + + + EP0_OUT + [1:1] + read-write + + + EP0_IN + [0:0] + read-write + + + + + NAK_POLL + Used by the host controller. Sets the wait time in microseconds before trying again if the device replies with a NAK. + 0x6C + 0x00100010 + + + DELAY_FS + NAK polling interval for a full speed device + [25:16] + read-write + + + DELAY_LS + NAK polling interval for a low speed device + [9:0] + read-write + + + + + EP_STATUS_STALL_NAK + Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` bits are set. For EP0 this comes from `SIE_CTRL`. For all other endpoints it comes from the endpoint control register. + 0x70 0x00000000 - SM3 + EP15_OUT + [31:31] + read-write + oneToClear + + + EP15_IN + [30:30] + read-write + oneToClear + + + EP14_OUT + [29:29] + read-write + oneToClear + + + EP14_IN + [28:28] + read-write + oneToClear + + + EP13_OUT + [27:27] + read-write + oneToClear + + + EP13_IN + [26:26] + read-write + oneToClear + + + EP12_OUT + [25:25] + read-write + oneToClear + + + EP12_IN + [24:24] + read-write + oneToClear + + + EP11_OUT + [23:23] + read-write + oneToClear + + + EP11_IN + [22:22] + read-write + oneToClear + + + EP10_OUT + [21:21] + read-write + oneToClear + + + EP10_IN + [20:20] + read-write + oneToClear + + + EP9_OUT + [19:19] + read-write + oneToClear + + + EP9_IN + [18:18] + read-write + oneToClear + + + EP8_OUT + [17:17] + read-write + oneToClear + + + EP8_IN + [16:16] + read-write + oneToClear + + + EP7_OUT + [15:15] + read-write + oneToClear + + + EP7_IN + [14:14] + read-write + oneToClear + + + EP6_OUT + [13:13] + read-write + oneToClear + + + EP6_IN + [12:12] + read-write + oneToClear + + + EP5_OUT [11:11] - read-only + read-write + oneToClear - SM2 + EP5_IN [10:10] - read-only + read-write + oneToClear - SM1 + EP4_OUT [9:9] - read-only + read-write + oneToClear - SM0 + EP4_IN [8:8] - read-only + read-write + oneToClear - SM3_TXNFULL + EP3_OUT [7:7] - read-only + read-write + oneToClear - SM2_TXNFULL + EP3_IN [6:6] - read-only + read-write + oneToClear - SM1_TXNFULL + EP2_OUT [5:5] - read-only + read-write + oneToClear - SM0_TXNFULL + EP2_IN [4:4] - read-only + read-write + oneToClear - SM3_RXNEMPTY + EP1_OUT [3:3] - read-only + read-write + oneToClear - SM2_RXNEMPTY + EP1_IN + [2:2] + read-write + oneToClear + + + EP0_OUT + [1:1] + read-write + oneToClear + + + EP0_IN + [0:0] + read-write + oneToClear + + + + + USB_MUXING + Where to connect the USB controller. Should be to_phy by default. + 0x74 + 0x00000000 + + + SOFTCON + [3:3] + read-write + + + TO_DIGITAL_PAD + [2:2] + read-write + + + TO_EXTPHY + [1:1] + read-write + + + TO_PHY + [0:0] + read-write + + + + + USB_PWR + Overrides for the power signals in the event that the VBUS signals are not hooked up to GPIO. Set the value of the override and then the override enable so switch over to the override value. + 0x78 + 0x00000000 + + + OVERCURR_DETECT_EN + [5:5] + read-write + + + OVERCURR_DETECT + [4:4] + read-write + + + VBUS_DETECT_OVERRIDE_EN + [3:3] + read-write + + + VBUS_DETECT [2:2] + read-write + + + VBUS_EN_OVERRIDE_EN + [1:1] + read-write + + + VBUS_EN + [0:0] + read-write + + + + + USBPHY_DIRECT + Note that most functions are driven directly from usb_fsls controller. This register allows more detailed control/status from the USB PHY. Useful for debug but not expected to be used in normal operation + Use in conjunction with usbphy_direct_override register + 0x7C + 0x00000000 + + + DM_OVV + Status bit from USB PHY + [22:22] + read-only + + + DP_OVV + Status bit from USB PHY + [21:21] + read-only + + + DM_OVCN + Status bit from USB PHY + [20:20] + read-only + + + DP_OVCN + Status bit from USB PHY + [19:19] + read-only + + + RX_DM + Status bit from USB PHY + DPM pin state + [18:18] + read-only + + + RX_DP + Status bit from USB PHY + DPP pin state + [17:17] + read-only + + + RX_DD + Status bit from USB PHY + RX Diff data + [16:16] read-only - SM1_RXNEMPTY - [1:1] - read-only + TX_DIFFMODE + [15:15] + read-write + + + TX_FSSLEW + [14:14] + read-write + + + TX_PD + [13:13] + read-write + + + RX_PD + [12:12] + read-write + + + TX_DM + Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller + TX_SEMODE=0, Ignored + TX_SEMODE=1, Drives DPM only. TX_DM_OE=1 to enable drive. DPM=TX_DM + [11:11] + read-write - SM0_RXNEMPTY - [0:0] - read-only - - - - - 2 - 0xC - 0-1 - SM_IRQ%s - Cluster SM_IRQ%s, containing IRQ*_INTE, IRQ*_INTF, IRQ*_INTS - 0x12C - - IRQ_INTE - Interrupt Enable for irq0 - 0x0 - 0x00000000 - - - SM3 - [11:11] - read-write - - - SM2 - [10:10] - read-write - - - SM1 - [9:9] - read-write - - - SM0 - [8:8] - read-write - - - SM3_TXNFULL - [7:7] - read-write - - - SM2_TXNFULL - [6:6] - read-write - - - SM1_TXNFULL - [5:5] - read-write - - - SM0_TXNFULL - [4:4] - read-write - - - SM3_RXNEMPTY - [3:3] - read-write - - - SM2_RXNEMPTY - [2:2] - read-write - - - SM1_RXNEMPTY - [1:1] - read-write - - - SM0_RXNEMPTY - [0:0] - read-write - - - - - IRQ_INTF - Interrupt Force for irq0 - 0x4 - 0x00000000 - - - SM3 - [11:11] - read-write - - - SM2 - [10:10] - read-write - - - SM1 - [9:9] - read-write - - - SM0 - [8:8] - read-write - - - SM3_TXNFULL - [7:7] - read-write - - - SM2_TXNFULL - [6:6] - read-write - - - SM1_TXNFULL - [5:5] - read-write - - - SM0_TXNFULL - [4:4] - read-write - - - SM3_RXNEMPTY - [3:3] - read-write - - - SM2_RXNEMPTY - [2:2] - read-write - - - SM1_RXNEMPTY - [1:1] - read-write - - - SM0_RXNEMPTY - [0:0] - read-write - - - - - IRQ_INTS - Interrupt status after masking & forcing for irq0 - 0x8 - 0x00000000 - - - SM3 - [11:11] - read-only - - - SM2 - [10:10] - read-only - - - SM1 - [9:9] - read-only - - - SM0 - [8:8] - read-only - - - SM3_TXNFULL - [7:7] - read-only - - - SM2_TXNFULL - [6:6] - read-only - - - SM1_TXNFULL - [5:5] - read-only - - - SM0_TXNFULL - [4:4] - read-only - - - SM3_RXNEMPTY - [3:3] - read-only - - - SM2_RXNEMPTY - [2:2] - read-only - - - SM1_RXNEMPTY - [1:1] - read-only - - - SM0_RXNEMPTY - [0:0] - read-only - - - - - - - - PIO1 - 0x50300000 - - PIO1_IRQ_0 - 9 - - - PIO1_IRQ_1 - 10 - - - - SIO - 1 - Single-cycle IO block\n - Provides core-local and inter-core hardware for the two processors, with single-cycle access. - 0xD0000000 - 0x20 - - 0x0 - 0x200 - registers - - - SIO_IRQ_PROC0 - 15 - - - SIO_IRQ_PROC1 - 16 - - + TX_DP + Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller + TX_SEMODE=0, Drives DPP/DPM diff pair. TX_DP_OE=1 to enable drive. DPP=TX_DP, DPM=~TX_DP + TX_SEMODE=1, Drives DPP only. TX_DP_OE=1 to enable drive. DPP=TX_DP + [10:10] + read-write + + + TX_DM_OE + Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller + TX_SEMODE=0, Ignored. + TX_SEMODE=1, OE for DPM only. 0 - DPM in Hi-Z state; 1 - DPM driving + [9:9] + read-write + + + TX_DP_OE + Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller + TX_SEMODE=0, OE for DPP/DPM diff pair. 0 - DPP/DPM in Hi-Z state; 1 - DPP/DPM driving + TX_SEMODE=1, OE for DPP only. 0 - DPP in Hi-Z state; 1 - DPP driving + [8:8] + read-write + + + DM_PULLDN_EN + Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller + 1 - Enable Rpd on DPM + [6:6] + read-write + + + DM_PULLUP_EN + Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller + 1 - Enable Rpu on DPM + [5:5] + read-write + + + DM_PULLUP_HISEL + when dm_pullup_en is set high, this enables second resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2 + [4:4] + read-write + + + DP_PULLDN_EN + Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller + 1 - Enable Rpd on DPP + [2:2] + read-write + + + DP_PULLUP_EN + Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller + [1:1] + read-write + + + DP_PULLUP_HISEL + when dp_pullup_en is set high, this enables second resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2 + [0:0] + read-write + + + - CPUID - Processor core identifier\n - Value is 0 when read from processor core 0, and 1 when read from processor core 1. - 0x0 - read-only + USBPHY_DIRECT_OVERRIDE + 0x80 0x00000000 + + + TX_DIFFMODE_OVERRIDE_EN + [15:15] + read-write + + + DM_PULLUP_OVERRIDE_EN + [12:12] + read-write + + + TX_FSSLEW_OVERRIDE_EN + [11:11] + read-write + + + TX_PD_OVERRIDE_EN + [10:10] + read-write + + + RX_PD_OVERRIDE_EN + [9:9] + read-write + + + TX_DM_OVERRIDE_EN + Override default value or value driven from USB Controller to PHY + [8:8] + read-write + + + TX_DP_OVERRIDE_EN + Override default value or value driven from USB Controller to PHY + [7:7] + read-write + + + TX_DM_OE_OVERRIDE_EN + Override default value or value driven from USB Controller to PHY + [6:6] + read-write + + + TX_DP_OE_OVERRIDE_EN + Override default value or value driven from USB Controller to PHY + [5:5] + read-write + + + DM_PULLDN_EN_OVERRIDE_EN + Override default value or value driven from USB Controller to PHY + [4:4] + read-write + + + DP_PULLDN_EN_OVERRIDE_EN + Override default value or value driven from USB Controller to PHY + [3:3] + read-write + + + DP_PULLUP_EN_OVERRIDE_EN + Override default value or value driven from USB Controller to PHY + [2:2] + read-write + + + DM_PULLUP_HISEL_OVERRIDE_EN + [1:1] + read-write + + + DP_PULLUP_HISEL_OVERRIDE_EN + [0:0] + read-write + + - GPIO_IN - Input value for GPIO pins - 0x4 - 0x00000000 + USBPHY_TRIM + Note that most functions are driven directly from usb_fsls controller. This register allows more detailed control/status from the USB PHY. Useful for debug but not expected to be used in normal operation + 0x84 + 0x00001F1F - GPIO_IN - Input value for GPIO0...29 - [29:0] - read-only + DM_PULLDN_TRIM + Value to drive to USB PHY + DM pulldown resistor trim control + Experimental data suggests that the reset value will work, but this register allows adjustment if required + [12:8] + read-write + + + DP_PULLDN_TRIM + Value to drive to USB PHY + DP pulldown resistor trim control + Experimental data suggests that the reset value will work, but this register allows adjustment if required + [4:0] + read-write - GPIO_HI_IN - Input value for QSPI pins - 0x8 + INTR + Raw Interrupts + 0x8C 0x00000000 - GPIO_HI_IN - Input value on QSPI IO in order 0..5: SCLK, SSn, SD0, SD1, SD2, SD3 - [5:0] + EP_STALL_NAK + Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK. + [19:19] + read-only + + + ABORT_DONE + Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE. + [18:18] + read-only + + + DEV_SOF + Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD + [17:17] + read-only + + + SETUP_REQ + Device. Source: SIE_STATUS.SETUP_REC + [16:16] + read-only + + + DEV_RESUME_FROM_HOST + Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME_REMOTE + [15:15] + read-only + + + DEV_SUSPEND + Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED + [14:14] + read-only + + + DEV_CONN_DIS + Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED + [13:13] + read-only + + + BUS_RESET + Source: SIE_STATUS.BUS_RESET + [12:12] + read-only + + + VBUS_DETECT + Source: SIE_STATUS.VBUS_DETECT + [11:11] + read-only + + + STALL + Source: SIE_STATUS.STALL_REC + [10:10] + read-only + + + ERROR_CRC + Source: SIE_STATUS.CRC_ERROR + [9:9] + read-only + + + ERROR_BIT_STUFF + Source: SIE_STATUS.BIT_STUFF_ERROR + [8:8] + read-only + + + ERROR_RX_OVERFLOW + Source: SIE_STATUS.RX_OVERFLOW + [7:7] + read-only + + + ERROR_RX_TIMEOUT + Source: SIE_STATUS.RX_TIMEOUT + [6:6] + read-only + + + ERROR_DATA_SEQ + Source: SIE_STATUS.DATA_SEQ_ERROR + [5:5] + read-only + + + BUFF_STATUS + Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS. + [4:4] + read-only + + + TRANS_COMPLETE + Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit. + [3:3] + read-only + + + HOST_SOF + Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD + [2:2] + read-only + + + HOST_RESUME + Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME_REMOTE + [1:1] + read-only + + + HOST_CONN_DIS + Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED + [0:0] read-only - GPIO_OUT - GPIO output value - 0x10 + INTE + Interrupt Enable + 0x90 0x00000000 - GPIO_OUT - Set output level (1/0 -> high/low) for GPIO0...29.\n - Reading back gives the last value written, NOT the input value from the pins.\n - If core 0 and core 1 both write to GPIO_OUT simultaneously (or to a SET/CLR/XOR alias),\n - the result is as though the write from core 0 took place first,\n - and the write from core 1 was then applied to that intermediate result. - [29:0] + EP_STALL_NAK + Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK. + [19:19] read-write - - - - GPIO_OUT_SET - GPIO output value set - 0x14 - 0x00000000 - - GPIO_OUT_SET - Perform an atomic bit-set on GPIO_OUT, i.e. `GPIO_OUT |= wdata` - [29:0] - write-only + ABORT_DONE + Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE. + [18:18] + read-write - - - - GPIO_OUT_CLR - GPIO output value clear - 0x18 - 0x00000000 - - GPIO_OUT_CLR - Perform an atomic bit-clear on GPIO_OUT, i.e. `GPIO_OUT &= ~wdata` - [29:0] - write-only + DEV_SOF + Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD + [17:17] + read-write - - - - GPIO_OUT_XOR - GPIO output value XOR - 0x1C - 0x00000000 - - GPIO_OUT_XOR - Perform an atomic bitwise XOR on GPIO_OUT, i.e. `GPIO_OUT ^= wdata` - [29:0] - write-only + SETUP_REQ + Device. Source: SIE_STATUS.SETUP_REC + [16:16] + read-write - - - - GPIO_OE - GPIO output enable - 0x20 - 0x00000000 - - GPIO_OE - Set output enable (1/0 -> output/input) for GPIO0...29.\n - Reading back gives the last value written.\n - If core 0 and core 1 both write to GPIO_OE simultaneously (or to a SET/CLR/XOR alias),\n - the result is as though the write from core 0 took place first,\n - and the write from core 1 was then applied to that intermediate result. - [29:0] + DEV_RESUME_FROM_HOST + Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME_REMOTE + [15:15] read-write - - - - GPIO_OE_SET - GPIO output enable set - 0x24 - 0x00000000 - - GPIO_OE_SET - Perform an atomic bit-set on GPIO_OE, i.e. `GPIO_OE |= wdata` - [29:0] - write-only + DEV_SUSPEND + Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED + [14:14] + read-write - - - - GPIO_OE_CLR - GPIO output enable clear - 0x28 - 0x00000000 - - GPIO_OE_CLR - Perform an atomic bit-clear on GPIO_OE, i.e. `GPIO_OE &= ~wdata` - [29:0] - write-only + DEV_CONN_DIS + Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED + [13:13] + read-write - - - - GPIO_OE_XOR - GPIO output enable XOR - 0x2C - 0x00000000 - - GPIO_OE_XOR - Perform an atomic bitwise XOR on GPIO_OE, i.e. `GPIO_OE ^= wdata` - [29:0] - write-only + BUS_RESET + Source: SIE_STATUS.BUS_RESET + [12:12] + read-write - - - - GPIO_HI_OUT - QSPI output value - 0x30 - 0x00000000 - - GPIO_HI_OUT - Set output level (1/0 -> high/low) for QSPI IO0...5.\n - Reading back gives the last value written, NOT the input value from the pins.\n - If core 0 and core 1 both write to GPIO_HI_OUT simultaneously (or to a SET/CLR/XOR alias),\n - the result is as though the write from core 0 took place first,\n - and the write from core 1 was then applied to that intermediate result. - [5:0] + VBUS_DETECT + Source: SIE_STATUS.VBUS_DETECT + [11:11] read-write - - - - GPIO_HI_OUT_SET - QSPI output value set - 0x34 - 0x00000000 - - GPIO_HI_OUT_SET - Perform an atomic bit-set on GPIO_HI_OUT, i.e. `GPIO_HI_OUT |= wdata` - [5:0] - write-only + STALL + Source: SIE_STATUS.STALL_REC + [10:10] + read-write - - - - GPIO_HI_OUT_CLR - QSPI output value clear - 0x38 - 0x00000000 - - GPIO_HI_OUT_CLR - Perform an atomic bit-clear on GPIO_HI_OUT, i.e. `GPIO_HI_OUT &= ~wdata` - [5:0] - write-only + ERROR_CRC + Source: SIE_STATUS.CRC_ERROR + [9:9] + read-write - - - - GPIO_HI_OUT_XOR - QSPI output value XOR - 0x3C - 0x00000000 - - GPIO_HI_OUT_XOR - Perform an atomic bitwise XOR on GPIO_HI_OUT, i.e. `GPIO_HI_OUT ^= wdata` - [5:0] - write-only + ERROR_BIT_STUFF + Source: SIE_STATUS.BIT_STUFF_ERROR + [8:8] + read-write - - - - GPIO_HI_OE - QSPI output enable - 0x40 - 0x00000000 - - GPIO_HI_OE - Set output enable (1/0 -> output/input) for QSPI IO0...5.\n - Reading back gives the last value written.\n - If core 0 and core 1 both write to GPIO_HI_OE simultaneously (or to a SET/CLR/XOR alias),\n - the result is as though the write from core 0 took place first,\n - and the write from core 1 was then applied to that intermediate result. - [5:0] + ERROR_RX_OVERFLOW + Source: SIE_STATUS.RX_OVERFLOW + [7:7] read-write - - - - GPIO_HI_OE_SET - QSPI output enable set - 0x44 - 0x00000000 - - GPIO_HI_OE_SET - Perform an atomic bit-set on GPIO_HI_OE, i.e. `GPIO_HI_OE |= wdata` - [5:0] - write-only + ERROR_RX_TIMEOUT + Source: SIE_STATUS.RX_TIMEOUT + [6:6] + read-write - - - - GPIO_HI_OE_CLR - QSPI output enable clear - 0x48 - 0x00000000 - - GPIO_HI_OE_CLR - Perform an atomic bit-clear on GPIO_HI_OE, i.e. `GPIO_HI_OE &= ~wdata` - [5:0] - write-only + ERROR_DATA_SEQ + Source: SIE_STATUS.DATA_SEQ_ERROR + [5:5] + read-write - - - - GPIO_HI_OE_XOR - QSPI output enable XOR - 0x4C - 0x00000000 - - GPIO_HI_OE_XOR - Perform an atomic bitwise XOR on GPIO_HI_OE, i.e. `GPIO_HI_OE ^= wdata` - [5:0] - write-only + BUFF_STATUS + Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS. + [4:4] + read-write - - - - FIFO_ST - Status register for inter-core FIFOs (mailboxes).\n - There is one FIFO in the core 0 -> core 1 direction, and one core 1 -> core 0. Both are 32 bits wide and 8 words deep.\n - Core 0 can see the read side of the 1->0 FIFO (RX), and the write side of 0->1 FIFO (TX).\n - Core 1 can see the read side of the 0->1 FIFO (RX), and the write side of 1->0 FIFO (TX).\n - The SIO IRQ for each core is the logical OR of the VLD, WOF and ROE fields of its FIFO_ST register. - 0x50 - 0x00000002 - - - ROE - Sticky flag indicating the RX FIFO was read when empty. This read was ignored by the FIFO. + + TRANS_COMPLETE + Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit. [3:3] read-write - oneToClear - WOF - Sticky flag indicating the TX FIFO was written when full. This write was ignored by the FIFO. + HOST_SOF + Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD [2:2] read-write - oneToClear - RDY - Value is 1 if this core's TX FIFO is not full (i.e. if FIFO_WR is ready for more data) + HOST_RESUME + Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME_REMOTE [1:1] - read-only + read-write - VLD - Value is 1 if this core's RX FIFO is not empty (i.e. if FIFO_RD is valid) + HOST_CONN_DIS + Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED [0:0] - read-only + read-write - FIFO_WR - Write access to this core's TX FIFO - 0x54 - write-only - 0x00000000 - - - FIFO_RD - Read access to this core's RX FIFO - 0x58 - read-only - 0x00000000 - - - SPINLOCK_ST - Spinlock state\n - A bitmap containing the state of all 32 spinlocks (1=locked).\n - Mainly intended for debugging. - 0x5C - read-only - 0x00000000 - - - DIV_UDIVIDEND - Divider unsigned dividend\n - Write to the DIVIDEND operand of the divider, i.e. the p in `p / q`.\n - Any operand write starts a new calculation. The results appear in QUOTIENT, REMAINDER.\n - UDIVIDEND/SDIVIDEND are aliases of the same internal register. The U alias starts an\n - unsigned calculation, and the S alias starts a signed calculation. - 0x60 - read-write - 0x00000000 - - - DIV_UDIVISOR - Divider unsigned divisor\n - Write to the DIVISOR operand of the divider, i.e. the q in `p / q`.\n - Any operand write starts a new calculation. The results appear in QUOTIENT, REMAINDER.\n - UDIVISOR/SDIVISOR are aliases of the same internal register. The U alias starts an\n - unsigned calculation, and the S alias starts a signed calculation. - 0x64 - read-write - 0x00000000 - - - DIV_SDIVIDEND - Divider signed dividend\n - The same as UDIVIDEND, but starts a signed calculation, rather than unsigned. - 0x68 - read-write - 0x00000000 - - - DIV_SDIVISOR - Divider signed divisor\n - The same as UDIVISOR, but starts a signed calculation, rather than unsigned. - 0x6C - read-write - 0x00000000 - - - DIV_QUOTIENT - Divider result quotient\n - The result of `DIVIDEND / DIVISOR` (division). Contents undefined while CSR_READY is low.\n - For signed calculations, QUOTIENT is negative when the signs of DIVIDEND and DIVISOR differ.\n - This register can be written to directly, for context save/restore purposes. This halts any\n - in-progress calculation and sets the CSR_READY and CSR_DIRTY flags.\n - Reading from QUOTIENT clears the CSR_DIRTY flag, so should read results in the order\n - REMAINDER, QUOTIENT if CSR_DIRTY is used. - 0x70 - read-write - 0x00000000 - - - DIV_REMAINDER - Divider result remainder\n - The result of `DIVIDEND % DIVISOR` (modulo). Contents undefined while CSR_READY is low.\n - For signed calculations, REMAINDER is negative only when DIVIDEND is negative.\n - This register can be written to directly, for context save/restore purposes. This halts any\n - in-progress calculation and sets the CSR_READY and CSR_DIRTY flags. - 0x74 - read-write + INTF + Interrupt Force + 0x94 0x00000000 - - - DIV_CSR - Control and status register for divider. - 0x78 - 0x00000001 - DIRTY - Changes to 1 when any register is written, and back to 0 when QUOTIENT is read.\n - Software can use this flag to make save/restore more efficient (skip if not DIRTY).\n - If the flag is used in this way, it's recommended to either read QUOTIENT only,\n - or REMAINDER and then QUOTIENT, to prevent data loss on context switch. - [1:1] - read-only + EP_STALL_NAK + Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK. + [19:19] + read-write - READY - Reads as 0 when a calculation is in progress, 1 otherwise.\n - Writing an operand (xDIVIDEND, xDIVISOR) will immediately start a new calculation, no\n - matter if one is already in progress.\n - Writing to a result register will immediately terminate any in-progress calculation\n - and set the READY and DIRTY flags. - [0:0] - read-only + ABORT_DONE + Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE. + [18:18] + read-write - - - - INTERP0_ACCUM0 - Read/write access to accumulator 0 - 0x80 - read-write - 0x00000000 - - - INTERP0_ACCUM1 - Read/write access to accumulator 1 - 0x84 - read-write - 0x00000000 - - - INTERP0_BASE0 - Read/write access to BASE0 register. - 0x88 - read-write - 0x00000000 - - - INTERP0_BASE1 - Read/write access to BASE1 register. - 0x8C - read-write - 0x00000000 - - - INTERP0_BASE2 - Read/write access to BASE2 register. - 0x90 - read-write - 0x00000000 - - - INTERP0_POP_LANE0 - Read LANE0 result, and simultaneously write lane results to both accumulators (POP). - 0x94 - read-only - 0x00000000 - - - INTERP0_POP_LANE1 - Read LANE1 result, and simultaneously write lane results to both accumulators (POP). - 0x98 - read-only - 0x00000000 - - - INTERP0_POP_FULL - Read FULL result, and simultaneously write lane results to both accumulators (POP). - 0x9C - read-only - 0x00000000 - - - INTERP0_PEEK_LANE0 - Read LANE0 result, without altering any internal state (PEEK). - 0xA0 - read-only - 0x00000000 - - - INTERP0_PEEK_LANE1 - Read LANE1 result, without altering any internal state (PEEK). - 0xA4 - read-only - 0x00000000 - - - INTERP0_PEEK_FULL - Read FULL result, without altering any internal state (PEEK). - 0xA8 - read-only - 0x00000000 - - - INTERP0_CTRL_LANE0 - Control register for lane 0 - 0xAC - 0x00000000 - - OVERF - Set if either OVERF0 or OVERF1 is set. - [25:25] - read-only + DEV_SOF + Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD + [17:17] + read-write - OVERF1 - Indicates if any masked-off MSBs in ACCUM1 are set. - [24:24] - read-only + SETUP_REQ + Device. Source: SIE_STATUS.SETUP_REC + [16:16] + read-write - OVERF0 - Indicates if any masked-off MSBs in ACCUM0 are set. - [23:23] - read-only + DEV_RESUME_FROM_HOST + Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME_REMOTE + [15:15] + read-write - BLEND - Only present on INTERP0 on each core. If BLEND mode is enabled:\n - - LANE1 result is a linear interpolation between BASE0 and BASE1, controlled\n - by the 8 LSBs of lane 1 shift and mask value (a fractional number between\n - 0 and 255/256ths)\n - - LANE0 result does not have BASE0 added (yields only the 8 LSBs of lane 1 shift+mask value)\n - - FULL result does not have lane 1 shift+mask value added (BASE2 + lane 0 shift+mask)\n - LANE1 SIGNED flag controls whether the interpolation is signed or unsigned. - [21:21] + DEV_SUSPEND + Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED + [14:14] read-write - FORCE_MSB - ORed into bits 29:28 of the lane result presented to the processor on the bus.\n - No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence\n - of pointers into flash or SRAM. - [20:19] + DEV_CONN_DIS + Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED + [13:13] read-write - ADD_RAW - If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result. - [18:18] + BUS_RESET + Source: SIE_STATUS.BUS_RESET + [12:12] read-write - CROSS_RESULT - If 1, feed the opposite lane's result into this lane's accumulator on POP. - [17:17] + VBUS_DETECT + Source: SIE_STATUS.VBUS_DETECT + [11:11] read-write - CROSS_INPUT - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware.\n - Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass) - [16:16] + STALL + Source: SIE_STATUS.STALL_REC + [10:10] read-write - SIGNED - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits\n - before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor. - [15:15] + ERROR_CRC + Source: SIE_STATUS.CRC_ERROR + [9:9] read-write - MASK_MSB - The most-significant bit allowed to pass by the mask (inclusive)\n - Setting MSB < LSB may cause chip to turn inside-out - [14:10] + ERROR_BIT_STUFF + Source: SIE_STATUS.BIT_STUFF_ERROR + [8:8] + read-write + + + ERROR_RX_OVERFLOW + Source: SIE_STATUS.RX_OVERFLOW + [7:7] + read-write + + + ERROR_RX_TIMEOUT + Source: SIE_STATUS.RX_TIMEOUT + [6:6] + read-write + + + ERROR_DATA_SEQ + Source: SIE_STATUS.DATA_SEQ_ERROR + [5:5] + read-write + + + BUFF_STATUS + Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS. + [4:4] + read-write + + + TRANS_COMPLETE + Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit. + [3:3] + read-write + + + HOST_SOF + Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD + [2:2] read-write - MASK_LSB - The least-significant bit allowed to pass by the mask (inclusive) - [9:5] + HOST_RESUME + Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME_REMOTE + [1:1] read-write - SHIFT - Logical right-shift applied to accumulator before masking - [4:0] + HOST_CONN_DIS + Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED + [0:0] read-write - INTERP0_CTRL_LANE1 - Control register for lane 1 - 0xB0 + INTS + Interrupt status after masking & forcing + 0x98 0x00000000 - FORCE_MSB - ORed into bits 29:28 of the lane result presented to the processor on the bus.\n - No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence\n - of pointers into flash or SRAM. - [20:19] - read-write + EP_STALL_NAK + Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK. + [19:19] + read-only - ADD_RAW - If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result. + ABORT_DONE + Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE. [18:18] - read-write + read-only - CROSS_RESULT - If 1, feed the opposite lane's result into this lane's accumulator on POP. + DEV_SOF + Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD [17:17] - read-write + read-only - CROSS_INPUT - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware.\n - Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass) + SETUP_REQ + Device. Source: SIE_STATUS.SETUP_REC [16:16] - read-write + read-only - SIGNED - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits\n - before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor. + DEV_RESUME_FROM_HOST + Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME_REMOTE [15:15] - read-write + read-only - MASK_MSB - The most-significant bit allowed to pass by the mask (inclusive)\n - Setting MSB < LSB may cause chip to turn inside-out - [14:10] - read-write + DEV_SUSPEND + Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED + [14:14] + read-only - MASK_LSB - The least-significant bit allowed to pass by the mask (inclusive) - [9:5] - read-write + DEV_CONN_DIS + Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED + [13:13] + read-only - SHIFT - Logical right-shift applied to accumulator before masking - [4:0] - read-write + BUS_RESET + Source: SIE_STATUS.BUS_RESET + [12:12] + read-only - - - - INTERP0_ACCUM0_ADD - Values written here are atomically added to ACCUM0\n - Reading yields lane 0's raw shift and mask value (BASE0 not added). - 0xB4 - 0x00000000 - - INTERP0_ACCUM0_ADD - [23:0] - read-write + VBUS_DETECT + Source: SIE_STATUS.VBUS_DETECT + [11:11] + read-only - - - - INTERP0_ACCUM1_ADD - Values written here are atomically added to ACCUM1\n - Reading yields lane 1's raw shift and mask value (BASE1 not added). - 0xB8 - 0x00000000 - - INTERP0_ACCUM1_ADD - [23:0] - read-write + STALL + Source: SIE_STATUS.STALL_REC + [10:10] + read-only - - - - INTERP0_BASE_1AND0 - On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously.\n - Each half is sign-extended to 32 bits if that lane's SIGNED flag is set. - 0xBC - write-only - 0x00000000 - - - INTERP1_ACCUM0 - Read/write access to accumulator 0 - 0xC0 - read-write - 0x00000000 - - - INTERP1_ACCUM1 - Read/write access to accumulator 1 - 0xC4 - read-write - 0x00000000 - - - INTERP1_BASE0 - Read/write access to BASE0 register. - 0xC8 - read-write - 0x00000000 - - - INTERP1_BASE1 - Read/write access to BASE1 register. - 0xCC - read-write - 0x00000000 - - - INTERP1_BASE2 - Read/write access to BASE2 register. - 0xD0 - read-write - 0x00000000 - - - INTERP1_POP_LANE0 - Read LANE0 result, and simultaneously write lane results to both accumulators (POP). - 0xD4 - read-only - 0x00000000 - - - INTERP1_POP_LANE1 - Read LANE1 result, and simultaneously write lane results to both accumulators (POP). - 0xD8 - read-only - 0x00000000 - - - INTERP1_POP_FULL - Read FULL result, and simultaneously write lane results to both accumulators (POP). - 0xDC - read-only - 0x00000000 - - - INTERP1_PEEK_LANE0 - Read LANE0 result, without altering any internal state (PEEK). - 0xE0 - read-only - 0x00000000 - - - INTERP1_PEEK_LANE1 - Read LANE1 result, without altering any internal state (PEEK). - 0xE4 - read-only - 0x00000000 - - - INTERP1_PEEK_FULL - Read FULL result, without altering any internal state (PEEK). - 0xE8 - read-only - 0x00000000 - - - INTERP1_CTRL_LANE0 - Control register for lane 0 - 0xEC - 0x00000000 - - OVERF - Set if either OVERF0 or OVERF1 is set. - [25:25] + ERROR_CRC + Source: SIE_STATUS.CRC_ERROR + [9:9] read-only - OVERF1 - Indicates if any masked-off MSBs in ACCUM1 are set. - [24:24] + ERROR_BIT_STUFF + Source: SIE_STATUS.BIT_STUFF_ERROR + [8:8] read-only - OVERF0 - Indicates if any masked-off MSBs in ACCUM0 are set. - [23:23] + ERROR_RX_OVERFLOW + Source: SIE_STATUS.RX_OVERFLOW + [7:7] read-only - CLAMP - Only present on INTERP1 on each core. If CLAMP mode is enabled:\n - - LANE0 result is shifted and masked ACCUM0, clamped by a lower bound of\n - BASE0 and an upper bound of BASE1.\n - - Signedness of these comparisons is determined by LANE0_CTRL_SIGNED - [22:22] - read-write + ERROR_RX_TIMEOUT + Source: SIE_STATUS.RX_TIMEOUT + [6:6] + read-only - FORCE_MSB - ORed into bits 29:28 of the lane result presented to the processor on the bus.\n - No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence\n - of pointers into flash or SRAM. - [20:19] - read-write + ERROR_DATA_SEQ + Source: SIE_STATUS.DATA_SEQ_ERROR + [5:5] + read-only - ADD_RAW - If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result. - [18:18] - read-write + BUFF_STATUS + Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS. + [4:4] + read-only - CROSS_RESULT - If 1, feed the opposite lane's result into this lane's accumulator on POP. - [17:17] - read-write + TRANS_COMPLETE + Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit. + [3:3] + read-only + + + HOST_SOF + Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD + [2:2] + read-only + + + HOST_RESUME + Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME_REMOTE + [1:1] + read-only + + + HOST_CONN_DIS + Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED + [0:0] + read-only + + + + + + USBCTRL_DPRAM + DPRAM layout for USB device. + 0x50100000 + + 0x0 + 0x100 + registers + + + + SETUP_PACKET_LOW + Bytes 0-3 of the SETUP packet from the host. + 0x0 + 0x00000000 + - CROSS_INPUT - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware.\n - Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass) - [16:16] + WVALUE + [31:16] read-write - SIGNED - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits\n - before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor. - [15:15] + BREQUEST + [15:8] read-write - MASK_MSB - The most-significant bit allowed to pass by the mask (inclusive)\n - Setting MSB < LSB may cause chip to turn inside-out - [14:10] + BMREQUESTTYPE + [7:0] read-write + + + + SETUP_PACKET_HIGH + Bytes 4-7 of the setup packet from the host. + 0x4 + 0x00000000 + - MASK_LSB - The least-significant bit allowed to pass by the mask (inclusive) - [9:5] + WLENGTH + [31:16] read-write - SHIFT - Logical right-shift applied to accumulator before masking - [4:0] + WINDEX + [15:0] read-write - INTERP1_CTRL_LANE1 - Control register for lane 1 - 0xF0 + 30 + 0x4 + 0-29 + EP_CONTROL%s + - + 0x8 0x00000000 - FORCE_MSB - ORed into bits 29:28 of the lane result presented to the processor on the bus.\n - No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence\n - of pointers into flash or SRAM. - [20:19] - read-write - - - ADD_RAW - If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result. - [18:18] + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] read-write - CROSS_RESULT - If 1, feed the opposite lane's result into this lane's accumulator on POP. - [17:17] + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] read-write - CROSS_INPUT - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware.\n - Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass) - [16:16] + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] read-write - SIGNED - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits\n - before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor. - [15:15] + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] read-write - MASK_MSB - The most-significant bit allowed to pass by the mask (inclusive)\n - Setting MSB < LSB may cause chip to turn inside-out - [14:10] + ENDPOINT_TYPE + [27:26] read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + - MASK_LSB - The least-significant bit allowed to pass by the mask (inclusive) - [9:5] + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] read-write - SHIFT - Logical right-shift applied to accumulator before masking - [4:0] + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] read-write - - - - INTERP1_ACCUM0_ADD - Values written here are atomically added to ACCUM0\n - Reading yields lane 0's raw shift and mask value (BASE0 not added). - 0xF4 - 0x00000000 - - INTERP1_ACCUM0_ADD - [23:0] + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] read-write - - - - INTERP1_ACCUM1_ADD - Values written here are atomically added to ACCUM1\n - Reading yields lane 1's raw shift and mask value (BASE1 not added). - 0xF8 - 0x00000000 - - INTERP1_ACCUM1_ADD - [23:0] - read-write + HOST_POLL_INTERVAL + The interval the host controller should poll this endpoint. Only applicable for interrupt endpoints. Specified in ms - 1. For example: a value of 9 would poll the endpoint every 10ms. + 16 + 10 - - INTERP1_BASE_1AND0 - On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously.\n - Each half is sign-extended to 32 bits if that lane's SIGNED flag is set. - 0xFC - write-only - 0x00000000 - 32 0x4 0-31 - SPINLOCK%s - Reading from a spinlock address will:\n - - Return 0 if lock is already locked\n - - Otherwise return nonzero, and simultaneously claim the lock\n\n - Writing (any value) releases the lock.\n - If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n - The value returned on success is 0x1 << lock number. - 0x100 - read-write - 0x00000000 - - - - - PPB - 1 - 0xE0000000 - 0x20 - - 0x0 - 0x10000 - registers - - - - SYST_CSR - Use the SysTick Control and Status Register to enable the SysTick features. - 0xE010 + EP_BUFFER_CONTROL%s + - + 0x80 0x00000000 - COUNTFLAG - Returns 1 if timer counted to 0 since last time this was read. Clears on read by application or debugger. - [16:16] - read-only - - - CLKSOURCE - SysTick clock source. Always reads as one if SYST_CALIB reports NOREF.\n - Selects the SysTick timer clock source:\n - 0 = External reference clock.\n - 1 = Processor clock. - [2:2] + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] read-write - TICKINT - Enables SysTick exception request:\n - 0 = Counting down to zero does not assert the SysTick exception request.\n - 1 = Counting down to zero to asserts the SysTick exception request. - [1:1] + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] read-write - ENABLE - Enable SysTick counter:\n - 0 = Counter disabled.\n - 1 = Counter enabled. - [0:0] + PID_1 + The data pid of buffer 1. + [29:29] read-write - - - - SYST_RVR - Use the SysTick Reload Value Register to specify the start value to load into the current value register when the counter reaches 0. It can be any value between 0 and 0x00FFFFFF. A start value of 0 is possible, but has no effect because the SysTick interrupt and COUNTFLAG are activated when counting from 1 to 0. The reset value of this register is UNKNOWN.\n - To generate a multi-shot timer with a period of N processor clock cycles, use a RELOAD value of N-1. For example, if the SysTick interrupt is required every 100 clock pulses, set RELOAD to 99. - 0xE014 - 0x00000000 - - RELOAD - Value to load into the SysTick Current Value Register when the counter reaches 0. - [23:0] + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + - - - - SYST_CVR - Use the SysTick Current Value Register to find the current value in the register. The reset value of this register is UNKNOWN. - 0xE018 - 0x00000000 - - CURRENT - Reads return the current value of the SysTick counter. This register is write-clear. Writing to it with any value clears the register to 0. Clearing this register also clears the COUNTFLAG bit of the SysTick Control and Status Register. - [23:0] + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] read-write - - - - SYST_CALIB - Use the SysTick Calibration Value Register to enable software to scale to any required speed using divide and multiply. - 0xE01C - 0x00000000 - - - NOREF - If reads as 1, the Reference clock is not provided - the CLKSOURCE bit of the SysTick Control and Status register will be forced to 1 and cannot be cleared to 0. - [31:31] - read-only - - - SKEW - If reads as 1, the calibration value for 10ms is inexact (due to clock frequency). - [30:30] - read-only - - TENMS - An optional Reload value to be used for 10ms (100Hz) timing, subject to system clock skew errors. If the value reads as 0, the calibration value is not known. - [23:0] - read-only - - - - - NVIC_ISER - Use the Interrupt Set-Enable Register to enable interrupts and determine which interrupts are currently enabled.\n - If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC never activates the interrupt, regardless of its priority. - 0xE100 - 0x00000000 - - - SETENA - Interrupt set-enable bits.\n - Write:\n - 0 = No effect.\n - 1 = Enable interrupt.\n - Read:\n - 0 = Interrupt disabled.\n - 1 = Interrupt enabled. - [31:0] + LENGTH_1 + The length of the data in buffer 1. + [25:16] read-write - - - - NVIC_ICER - Use the Interrupt Clear-Enable Registers to disable interrupts and determine which interrupts are currently enabled. - 0xE180 - 0x00000000 - - CLRENA - Interrupt clear-enable bits.\n - Write:\n - 0 = No effect.\n - 1 = Disable interrupt.\n - Read:\n - 0 = Interrupt disabled.\n - 1 = Interrupt enabled. - [31:0] + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] read-write - - - - NVIC_ISPR - The NVIC_ISPR forces interrupts into the pending state, and shows which interrupts are pending. - 0xE200 - 0x00000000 - - SETPEND - Interrupt set-pending bits.\n - Write:\n - 0 = No effect.\n - 1 = Changes interrupt state to pending.\n - Read:\n - 0 = Interrupt is not pending.\n - 1 = Interrupt is pending.\n - Note: Writing 1 to the NVIC_ISPR bit corresponding to:\n - An interrupt that is pending has no effect.\n - A disabled interrupt sets the state of that interrupt to pending. - [31:0] + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] read-write - - - - NVIC_ICPR - Use the Interrupt Clear-Pending Register to clear pending interrupts and determine which interrupts are currently pending. - 0xE280 - 0x00000000 - - CLRPEND - Interrupt clear-pending bits.\n - Write:\n - 0 = No effect.\n - 1 = Removes pending state and interrupt.\n - Read:\n - 0 = Interrupt is not pending.\n - 1 = Interrupt is pending. - [31:0] + PID_0 + The data pid of buffer 0. + [13:13] read-write - - - - NVIC_IPR0 - Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.\n - Note: Writing 1 to an NVIC_ICPR bit does not affect the active state of the corresponding interrupt.\n - These registers are only word-accessible - 0xE400 - 0x00000000 - - IP_3 - Priority of interrupt 3 - [31:30] + RESET + Reset the buffer selector to buffer 0. + [12:12] read-write - IP_2 - Priority of interrupt 2 - [23:22] + STALL + Reply with a stall (valid for both buffers). + [11:11] read-write - IP_1 - Priority of interrupt 1 - [15:14] + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] read-write - IP_0 - Priority of interrupt 0 - [7:6] + LENGTH_0 + The length of the data in buffer 0. + [9:0] read-write - NVIC_IPR1 - Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. - 0xE404 + EPX_CONTROL + EPx Control (Host-mode only!) + 0x100 0x00000000 - IP_7 - Priority of interrupt 7 - [31:30] + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] read-write - IP_6 - Priority of interrupt 6 - [23:22] + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] read-write - IP_5 - Priority of interrupt 5 - [15:14] + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] read-write - IP_4 - Priority of interrupt 4 - [7:6] + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] read-write - - - - NVIC_IPR2 - Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. - 0xE408 - 0x00000000 - - IP_11 - Priority of interrupt 11 - [31:30] + ENDPOINT_TYPE + [27:26] read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + - IP_10 - Priority of interrupt 10 - [23:22] + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] read-write - IP_9 - Priority of interrupt 9 - [15:14] + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] read-write - IP_8 - Priority of interrupt 8 - [7:6] + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] read-write + + + + TBMAN + Testbench manager. Allows the programmer to know what platform their software is running on. + 0x4006C000 + + 0x0 + 0x4 + registers + + - NVIC_IPR3 - Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. - 0xE40C - 0x00000000 + PLATFORM + Indicates the type of platform in use + 0x0 + 0x00000005 - IP_15 - Priority of interrupt 15 - [31:30] - read-write + FPGA + Indicates the platform is an FPGA + [1:1] + read-only - IP_14 - Priority of interrupt 14 - [23:22] + ASIC + Indicates the platform is an ASIC + [0:0] + read-only + + + + + + + VREG_AND_CHIP_RESET + control and status for on-chip voltage regulator and chip level reset subsystem + 0x40064000 + + 0x0 + 0xC + registers + + + + VREG + Voltage regulator control and status + 0x0 + 0x000000B1 + + + ROK + regulation status + 0=not in regulation, 1=in regulation + [12:12] + read-only + + + VSEL + Output voltage select for on-chip voltage regulator. + [7:4] read-write + + VSEL + + Voltage0_80 + 0.80V + 5 + + + Voltage0_85 + 0.85V + 6 + + + Voltage0_90 + 0.90V + 7 + + + Voltage0_95 + 0.95V + 8 + + + Voltage1_00 + 1.00V + 9 + + + Voltage1_05 + 1.05V + 10 + + + Voltage1_10 + 1.10V (default) + 11 + + + Voltage1_15 + 1.15V + 12 + + + Voltage1_20 + 1.20V + 13 + + + Voltage1_25 + 1.25V + 14 + + + Voltage1_30 + 1.30V + 15 + + - IP_13 - Priority of interrupt 13 - [15:14] + HIZ + high impedance mode select + 0=not in high impedance mode, 1=in high impedance mode + [1:1] read-write - IP_12 - Priority of interrupt 12 - [7:6] + EN + enable + 0=not enabled, 1=enabled + [0:0] read-write - NVIC_IPR4 - Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. - 0xE410 - 0x00000000 + BOD + brown-out detection control + 0x4 + 0x00000091 - IP_19 - Priority of interrupt 19 - [31:30] - read-write - - - IP_18 - Priority of interrupt 18 - [23:22] - read-write - - - IP_17 - Priority of interrupt 17 - [15:14] + VSEL + threshold select + 0000 - 0.473V + 0001 - 0.516V + 0010 - 0.559V + 0011 - 0.602V + 0100 - 0.645V + 0101 - 0.688V + 0110 - 0.731V + 0111 - 0.774V + 1000 - 0.817V + 1001 - 0.860V (default) + 1010 - 0.903V + 1011 - 0.946V + 1100 - 0.989V + 1101 - 1.032V + 1110 - 1.075V + 1111 - 1.118V + [7:4] read-write - IP_16 - Priority of interrupt 16 - [7:6] + EN + enable + 0=not enabled, 1=enabled + [0:0] read-write - NVIC_IPR5 - Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. - 0xE414 + CHIP_RESET + Chip reset control and status + 0x8 0x00000000 - IP_23 - Priority of interrupt 23 - [31:30] + PSM_RESTART_FLAG + This is set by psm_restart from the debugger. + Its purpose is to branch bootcode to a safe mode when the debugger has issued a psm_restart in order to recover from a boot lock-up. + In the safe mode the debugger can repair the boot code, clear this flag then reboot the processor. + [24:24] read-write + oneToClear - IP_22 - Priority of interrupt 22 - [23:22] - read-write + HAD_PSM_RESTART + Last reset was from the debug port + [20:20] + read-only - IP_21 - Priority of interrupt 21 - [15:14] - read-write + HAD_RUN + Last reset was from the RUN pin + [16:16] + read-only - IP_20 - Priority of interrupt 20 - [7:6] - read-write + HAD_POR + Last reset was from the power-on reset or brown-out detection blocks + [8:8] + read-only + + + + RTC + Register block to control RTC + 0x4005C000 + + 0x0 + 0x30 + registers + + + RTC_IRQ + 25 + + - NVIC_IPR6 - Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. - 0xE418 + CLKDIV_M1 + Divider minus 1 for the 1 second counter. Safe to change the value when RTC is not enabled. + 0x0 0x00000000 - IP_27 - Priority of interrupt 27 - [31:30] + CLKDIV_M1 + [15:0] read-write + + + + SETUP_0 + RTC setup register 0 + 0x4 + 0x00000000 + - IP_26 - Priority of interrupt 26 - [23:22] + YEAR + Year + [23:12] read-write - IP_25 - Priority of interrupt 25 - [15:14] + MONTH + Month (1..12) + [11:8] read-write - IP_24 - Priority of interrupt 24 - [7:6] + DAY + Day of the month (1..31) + [4:0] read-write - NVIC_IPR7 - Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. - 0xE41C + SETUP_1 + RTC setup register 1 + 0x8 0x00000000 - IP_31 - Priority of interrupt 31 - [31:30] + DOTW + Day of the week: 1-Monday...0-Sunday ISO 8601 mod 7 + [26:24] read-write - IP_30 - Priority of interrupt 30 - [23:22] + HOUR + Hours + [20:16] read-write - IP_29 - Priority of interrupt 29 - [15:14] + MIN + Minutes + [13:8] read-write - IP_28 - Priority of interrupt 28 - [7:6] + SEC + Seconds + [5:0] read-write - CPUID - Read the CPU ID Base Register to determine: the ID number of the processor core, the version number of the processor core, the implementation details of the processor core. - 0xED00 - 0x410CC601 + CTRL + RTC Control and status + 0xC + 0x00000000 - IMPLEMENTER - Implementor code: 0x41 = ARM - [31:24] - read-only - - - VARIANT - Major revision number n in the rnpm revision status:\n - 0x0 = Revision 0. - [23:20] - read-only + FORCE_NOTLEAPYEAR + If set, leapyear is forced off. + Useful for years divisible by 100 but not by 400 + [8:8] + read-write - ARCHITECTURE - Constant that defines the architecture of the processor:\n - 0xC = ARMv6-M architecture. - [19:16] - read-only + LOAD + Load RTC + [4:4] + write-only - PARTNO - Number of processor within family: 0xC60 = Cortex-M0+ - [15:4] + RTC_ACTIVE + RTC enabled (running) + [1:1] read-only - REVISION - Minor revision number m in the rnpm revision status:\n - 0x1 = Patch 1. - [3:0] - read-only + RTC_ENABLE + Enable RTC + [0:0] + read-write - ICSR - Use the Interrupt Control State Register to set a pending Non-Maskable Interrupt (NMI), set or clear a pending PendSV, set or clear a pending SysTick, check for pending exceptions, check the vector number of the highest priority pended exception, check the vector number of the active exception. - 0xED04 + IRQ_SETUP_0 + Interrupt setup register 0 + 0x10 0x00000000 - NMIPENDSET - Setting this bit will activate an NMI. Since NMI is the highest priority exception, it will activate as soon as it is registered.\n - NMI set-pending bit.\n - Write:\n - 0 = No effect.\n - 1 = Changes NMI exception state to pending.\n - Read:\n - 0 = NMI exception is not pending.\n - 1 = NMI exception is pending.\n - Because NMI is the highest-priority exception, normally the processor enters the NMI\n - exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears\n - this bit to 0. This means a read of this bit by the NMI exception handler returns 1 only if the\n - NMI signal is reasserted while the processor is executing that handler. - [31:31] - read-write + MATCH_ACTIVE + [29:29] + read-only - PENDSVSET - PendSV set-pending bit.\n - Write:\n - 0 = No effect.\n - 1 = Changes PendSV exception state to pending.\n - Read:\n - 0 = PendSV exception is not pending.\n - 1 = PendSV exception is pending.\n - Writing 1 to this bit is the only way to set the PendSV exception state to pending. + MATCH_ENA + Global match enable. Don't change any other value while this one is enabled [28:28] read-write - PENDSVCLR - PendSV clear-pending bit.\n - Write:\n - 0 = No effect.\n - 1 = Removes the pending state from the PendSV exception. - [27:27] - read-write - - - PENDSTSET - SysTick exception set-pending bit.\n - Write:\n - 0 = No effect.\n - 1 = Changes SysTick exception state to pending.\n - Read:\n - 0 = SysTick exception is not pending.\n - 1 = SysTick exception is pending. + YEAR_ENA + Enable year matching [26:26] read-write - PENDSTCLR - SysTick exception clear-pending bit.\n - Write:\n - 0 = No effect.\n - 1 = Removes the pending state from the SysTick exception.\n - This bit is WO. On a register read its value is Unknown. + MONTH_ENA + Enable month matching [25:25] read-write - ISRPREEMPT - The system can only access this bit when the core is halted. It indicates that a pending interrupt is to be taken in the next running cycle. If C_MASKINTS is clear in the Debug Halting Control and Status Register, the interrupt is serviced. - [23:23] - read-only + DAY_ENA + Enable day matching + [24:24] + read-write - ISRPENDING - External interrupt pending flag - [22:22] - read-only + YEAR + Year + [23:12] + read-write - VECTPENDING - Indicates the exception number for the highest priority pending exception: 0 = no pending exceptions. Non zero = The pending state includes the effect of memory-mapped enable and mask registers. It does not include the PRIMASK special-purpose register qualifier. - [20:12] - read-only + MONTH + Month (1..12) + [11:8] + read-write - VECTACTIVE - Active exception number field. Reset clears the VECTACTIVE field. - [8:0] - read-only + DAY + Day of the month (1..31) + [4:0] + read-write - VTOR - The VTOR holds the vector table offset address. - 0xED08 + IRQ_SETUP_1 + Interrupt setup register 1 + 0x14 0x00000000 - TBLOFF - Bits [31:8] of the indicate the vector table offset address. - [31:8] + DOTW_ENA + Enable day of the week matching + [31:31] read-write - - - - AIRCR - Use the Application Interrupt and Reset Control Register to: determine data endianness, clear all active state information from debug halt mode, request a system reset. - 0xED0C - 0x00000000 - - VECTKEY - Register key:\n - Reads as Unknown\n - On writes, write 0x05FA to VECTKEY, otherwise the write is ignored. - [31:16] + HOUR_ENA + Enable hour matching + [30:30] read-write - ENDIANESS - Data endianness implemented:\n - 0 = Little-endian. - [15:15] - read-only + MIN_ENA + Enable minute matching + [29:29] + read-write - SYSRESETREQ - Writing 1 to this bit causes the SYSRESETREQ signal to the outer system to be asserted to request a reset. The intention is to force a large system reset of all major components except for debug. The C_HALT bit in the DHCSR is cleared as a result of the system reset requested. The debugger does not lose contact with the device. - [2:2] + SEC_ENA + Enable second matching + [28:28] read-write - VECTCLRACTIVE - Clears all active state information for fixed and configurable exceptions. This bit: is self-clearing, can only be set by the DAP when the core is halted. When set: clears all active exception status of the processor, forces a return to Thread mode, forces an IPSR of 0. A debugger must re-initialize the stack. - [1:1] + DOTW + Day of the week + [26:24] read-write - - - - SCR - System Control Register. Use the System Control Register for power-management functions: signal to the system when the processor can enter a low power state, control how the processor enters and exits low power states. - 0xED10 - 0x00000000 - - SEVONPEND - Send Event on Pending bit:\n - 0 = Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded.\n - 1 = Enabled events and all interrupts, including disabled interrupts, can wakeup the processor.\n - When an event or interrupt becomes pending, the event signal wakes up the processor from WFE. If the\n - processor is not waiting for an event, the event is registered and affects the next WFE.\n - The processor also wakes up on execution of an SEV instruction or an external event. - [4:4] + HOUR + Hours + [20:16] read-write - SLEEPDEEP - Controls whether the processor uses sleep or deep sleep as its low power mode:\n - 0 = Sleep.\n - 1 = Deep sleep. - [2:2] + MIN + Minutes + [13:8] read-write - SLEEPONEXIT - Indicates sleep-on-exit when returning from Handler mode to Thread mode:\n - 0 = Do not sleep when returning to Thread mode.\n - 1 = Enter sleep, or deep sleep, on return from an ISR to Thread mode.\n - Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application. - [1:1] + SEC + Seconds + [5:0] read-write - CCR - The Configuration and Control Register permanently enables stack alignment and causes unaligned accesses to result in a Hard Fault. - 0xED14 + RTC_1 + RTC register 1. + 0x18 0x00000000 - STKALIGN - Always reads as one, indicates 8-byte stack alignment on exception entry. On exception entry, the processor uses bit[9] of the stacked PSR to indicate the stack alignment. On return from the exception it uses this stacked bit to restore the correct stack alignment. - [9:9] + YEAR + Year + [23:12] read-only - UNALIGN_TRP - Always reads as one, indicates that all unaligned accesses generate a HardFault. - [3:3] + MONTH + Month (1..12) + [11:8] read-only - - - - SHPR2 - System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Use the System Handler Priority Register 2 to set the priority of SVCall. - 0xED1C - 0x00000000 - - - PRI_11 - Priority of system handler 11, SVCall - [31:30] - read-write - - - - - SHPR3 - System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Use the System Handler Priority Register 3 to set the priority of PendSV and SysTick. - 0xED20 - 0x00000000 - - - PRI_15 - Priority of system handler 15, SysTick - [31:30] - read-write - - PRI_14 - Priority of system handler 14, PendSV - [23:22] - read-write + DAY + Day of the month (1..31) + [4:0] + read-only - SHCSR - Use the System Handler Control and State Register to determine or clear the pending status of SVCall. - 0xED24 + RTC_0 + RTC register 0 + Read this before RTC 1! + 0x1C 0x00000000 - SVCALLPENDED - Reads as 1 if SVCall is Pending. Write 1 to set pending SVCall, write 0 to clear pending SVCall. - [15:15] - read-write + DOTW + Day of the week + [26:24] + read-only + modify - - - - MPU_TYPE - Read the MPU Type Register to determine if the processor implements an MPU, and how many regions the MPU supports. - 0xED90 - 0x00000800 - - IREGION - Instruction region. Reads as zero as ARMv6-M only supports a unified MPU. - [23:16] + HOUR + Hours + [20:16] read-only + modify - DREGION - Number of regions supported by the MPU. - [15:8] + MIN + Minutes + [13:8] read-only + modify - SEPARATE - Indicates support for separate instruction and data address maps. Reads as 0 as ARMv6-M only supports a unified MPU. - [0:0] + SEC + Seconds + [5:0] read-only + modify - MPU_CTRL - Use the MPU Control Register to enable and disable the MPU, and to control whether the default memory map is enabled as a background region for privileged accesses, and whether the MPU is enabled for HardFaults and NMIs. - 0xED94 + INTR + Raw Interrupts + 0x20 0x00000000 - PRIVDEFENA - Controls whether the default memory map is enabled as a background region for privileged accesses. This bit is ignored when ENABLE is clear.\n - 0 = If the MPU is enabled, disables use of the default memory map. Any memory access to a location not\n - covered by any enabled region causes a fault.\n - 1 = If the MPU is enabled, enables use of the default memory map as a background region for privileged software accesses.\n - When enabled, the background region acts as if it is region number -1. Any region that is defined and enabled has priority over this default map. - [2:2] - read-write - - - HFNMIENA - Controls the use of the MPU for HardFaults and NMIs. Setting this bit when ENABLE is clear results in UNPREDICTABLE behaviour.\n - When the MPU is enabled:\n - 0 = MPU is disabled during HardFault and NMI handlers, regardless of the value of the ENABLE bit.\n - 1 = the MPU is enabled during HardFault and NMI handlers. - [1:1] - read-write - - - ENABLE - Enables the MPU. If the MPU is disabled, privileged and unprivileged accesses use the default memory map.\n - 0 = MPU disabled.\n - 1 = MPU enabled. + RTC [0:0] - read-write + read-only - MPU_RNR - Use the MPU Region Number Register to select the region currently accessed by MPU_RBAR and MPU_RASR. - 0xED98 + INTE + Interrupt Enable + 0x24 0x00000000 - REGION - Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers.\n - The MPU supports 8 memory regions, so the permitted values of this field are 0-7. - [3:0] + RTC + [0:0] read-write - MPU_RBAR - Read the MPU Region Base Address Register to determine the base address of the region identified by MPU_RNR. Write to update the base address of said region or that of a specified region, with whose number MPU_RNR will also be updated. - 0xED9C + INTF + Interrupt Force + 0x28 0x00000000 - ADDR - Base address of the region. - [31:8] - read-write - - - VALID - On writes, indicates whether the write must update the base address of the region identified by the REGION field, updating the MPU_RNR to indicate this new region.\n - Write:\n - 0 = MPU_RNR not changed, and the processor:\n - Updates the base address for the region specified in the MPU_RNR.\n - Ignores the value of the REGION field.\n - 1 = The processor:\n - Updates the value of the MPU_RNR to the value of the REGION field.\n - Updates the base address for the region specified in the REGION field.\n - Always reads as zero. - [4:4] - read-write - - - REGION - On writes, specifies the number of the region whose base address to update provided VALID is set written as 1. On reads, returns bits [3:0] of MPU_RNR. - [3:0] + RTC + [0:0] read-write - MPU_RASR - Use the MPU Region Attribute and Size Register to define the size, access behaviour and memory type of the region identified by MPU_RNR, and enable that region. - 0xEDA0 + INTS + Interrupt status after masking & forcing + 0x2C 0x00000000 - ATTRS - The MPU Region Attribute field. Use to define the region attribute control.\n - 28 = XN: Instruction access disable bit:\n - 0 = Instruction fetches enabled.\n - 1 = Instruction fetches disabled.\n - 26:24 = AP: Access permission field\n - 18 = S: Shareable bit\n - 17 = C: Cacheable bit\n - 16 = B: Bufferable bit - [31:16] - read-write - - - SRD - Subregion Disable. For regions of 256 bytes or larger, each bit of this field controls whether one of the eight equal subregions is enabled. - [15:8] - read-write - - - SIZE - Indicates the region size. Region size in bytes = 2^(SIZE+1). The minimum permitted value is 7 (b00111) = 256Bytes - [5:1] - read-write - - - ENABLE - Enables the region. + RTC [0:0] - read-write + read-only