diff --git a/clang/include/clang/Basic/riscv_vector_xtheadv.td b/clang/include/clang/Basic/riscv_vector_xtheadv.td
index 520a2b3aeb648e..a152bea528d8cb 100644
--- a/clang/include/clang/Basic/riscv_vector_xtheadv.td
+++ b/clang/include/clang/Basic/riscv_vector_xtheadv.td
@@ -2137,6 +2137,36 @@ let HasMasked = false,
 let HasMasked = false, HasVL = false, IRName = "" in {
   let Name = "th_vreinterpret_v", MaskedPolicyScheme = NonePolicy,
       ManualCodegen = [{
+        if (ResultType->isIntOrIntVectorTy(1) ||
+            Ops[0]->getType()->isIntOrIntVectorTy(1)) {
+          assert(isa<ScalableVectorType>(ResultType) &&
+                 isa<ScalableVectorType>(Ops[0]->getType()));
+
+          LLVMContext &Context = CGM.getLLVMContext();
+          ScalableVectorType *Boolean64Ty =
+              ScalableVectorType::get(llvm::Type::getInt1Ty(Context), 64);
+
+          if (ResultType->isIntOrIntVectorTy(1)) {
+            // Casting from m1 vector integer -> vector boolean
+            // Ex: <vscale x 8 x i8>
+            //     --(bitcast)--------> <vscale x 64 x i1>
+            //     --(vector_extract)-> <vscale x  8 x i1>
+            llvm::Value *BitCast = Builder.CreateBitCast(Ops[0], Boolean64Ty);
+            return Builder.CreateExtractVector(ResultType, BitCast,
+                                               ConstantInt::get(Int64Ty, 0));
+          } else {
+            // Casting from vector boolean -> m1 vector integer
+            // Ex: <vscale x  1 x i1>
+            //       --(vector_insert)-> <vscale x 64 x i1>
+            //       --(bitcast)-------> <vscale x  8 x i8>
+            llvm::Value *Boolean64Val =
+              Builder.CreateInsertVector(Boolean64Ty,
+                                         llvm::PoisonValue::get(Boolean64Ty),
+                                         Ops[0],
+                                         ConstantInt::get(Int64Ty, 0));
+            return Builder.CreateBitCast(Boolean64Val, ResultType);
+          }
+        }
         // Just simple type cast
         return Builder.CreateBitCast(Ops[0], ResultType);
       }] in {
@@ -2148,6 +2178,36 @@ let HasMasked = false, HasVL = false, IRName = "" in {
     // Reinterpret between signed and unsigned types
     def th_vreinterpret_i_u : RVVBuiltin<"Uvv", "vUv", "csil", "v">;
     def th_vreinterpret_u_i : RVVBuiltin<"vUv", "Uvv", "csil", "Uv">;
+
+    // Reinterpret between different SEW under the same LMUL
+    foreach dst_sew = ["(FixedSEW:8)", "(FixedSEW:16)", "(FixedSEW:32)",
+                       "(FixedSEW:64)"] in {
+      def th_vreinterpret_i_ # dst_sew : RVVBuiltin<"v" # dst_sew # "v",
+                                                    dst_sew # "vv", "csil", dst_sew # "v">;
+      def th_vreinterpret_u_ # dst_sew : RVVBuiltin<"Uv" # dst_sew # "Uv",
+                                                    dst_sew # "UvUv", "csil", dst_sew # "Uv">;
+    }
+
+    // Reinterpret between LMUL=1 integer type and vector boolean type.
+    // NOTE: they are not defined in the spec, but they are useful as I have
+    // seen them in some RVV related open-source projects.
+    def th_vreintrepret_i_m1_b8 : RVVBuiltin<"Svm", "mSv", "c", "m">;
+    def th_vreintrepret_u_m1_b8 : RVVBuiltin<"USvm", "mUSv", "c", "m">;
+    def th_vreintrepret_i_b8_m1 : RVVBuiltin<"mSv", "Svm", "c", "Sv">;
+    def th_vreintrepret_u_b8_m1 : RVVBuiltin<"mUSv", "USvm", "c", "USv">;
+
+    foreach dst_sew = ["(FixedSEW:16)", "(FixedSEW:32)", "(FixedSEW:64)"] in {
+      // Reinterpret from LMUL=1 integer type to vector boolean type
+      def th_vreinterpret_i_m1_b # dst_sew:
+        RVVBuiltin<dst_sew # "Svm", "m" # dst_sew # "Sv", "c", "m">;
+      def th_vreinterpret_u_m1_b # dst_sew:
+        RVVBuiltin<dst_sew # "USvm", "m" # dst_sew # "USv", "c", "m">;
+      // Reinterpret from vector boolean type to LMUL=1 integer type
+      def th_vreinterpret_i_b # dst_sew # _m1:
+        RVVBuiltin<"m" # dst_sew # "Sv", dst_sew # "Svm", "c", dst_sew # "Sv">;
+      def th_vreinterpret_u_b # dst_sew # _m1:
+        RVVBuiltin<"m" # dst_sew # "USv", dst_sew # "USvm", "c", dst_sew # "USv">;
+    }
   }
 
   // Vector Initialization
diff --git a/clang/include/clang/Basic/riscv_vector_xtheadv_wrappers.td b/clang/include/clang/Basic/riscv_vector_xtheadv_wrappers.td
index a330c278a998be..93aaf4a4fb94eb 100644
--- a/clang/include/clang/Basic/riscv_vector_xtheadv_wrappers.td
+++ b/clang/include/clang/Basic/riscv_vector_xtheadv_wrappers.td
@@ -6307,5 +6307,192 @@ let HeaderCode = [{
 #define __riscv_vreinterpret_v_f64m2_u64m2(src) __riscv_th_vreinterpret_v_f64m2_u64m2(src)
 #define __riscv_vreinterpret_v_f64m4_u64m4(src) __riscv_th_vreinterpret_v_f64m4_u64m4(src)
 #define __riscv_vreinterpret_v_f64m8_u64m8(src) __riscv_th_vreinterpret_v_f64m8_u64m8(src)
+
+#define __riscv_vreinterpret_v_i8m1_i16m1(src) __riscv_th_vreinterpret_v_i8m1_i16m1(src)
+#define __riscv_vreinterpret_v_i8m2_i16m2(src) __riscv_th_vreinterpret_v_i8m2_i16m2(src)
+#define __riscv_vreinterpret_v_i8m4_i16m4(src) __riscv_th_vreinterpret_v_i8m4_i16m4(src)
+#define __riscv_vreinterpret_v_i8m8_i16m8(src) __riscv_th_vreinterpret_v_i8m8_i16m8(src)
+#define __riscv_vreinterpret_v_u8m1_u16m1(src) __riscv_th_vreinterpret_v_u8m1_u16m1(src)
+#define __riscv_vreinterpret_v_u8m2_u16m2(src) __riscv_th_vreinterpret_v_u8m2_u16m2(src)
+#define __riscv_vreinterpret_v_u8m4_u16m4(src) __riscv_th_vreinterpret_v_u8m4_u16m4(src)
+#define __riscv_vreinterpret_v_u8m8_u16m8(src) __riscv_th_vreinterpret_v_u8m8_u16m8(src)
+#define __riscv_vreinterpret_v_i8m1_i32m1(src) __riscv_th_vreinterpret_v_i8m1_i32m1(src)
+#define __riscv_vreinterpret_v_i8m2_i32m2(src) __riscv_th_vreinterpret_v_i8m2_i32m2(src)
+#define __riscv_vreinterpret_v_i8m4_i32m4(src) __riscv_th_vreinterpret_v_i8m4_i32m4(src)
+#define __riscv_vreinterpret_v_i8m8_i32m8(src) __riscv_th_vreinterpret_v_i8m8_i32m8(src)
+#define __riscv_vreinterpret_v_u8m1_u32m1(src) __riscv_th_vreinterpret_v_u8m1_u32m1(src)
+#define __riscv_vreinterpret_v_u8m2_u32m2(src) __riscv_th_vreinterpret_v_u8m2_u32m2(src)
+#define __riscv_vreinterpret_v_u8m4_u32m4(src) __riscv_th_vreinterpret_v_u8m4_u32m4(src)
+#define __riscv_vreinterpret_v_u8m8_u32m8(src) __riscv_th_vreinterpret_v_u8m8_u32m8(src)
+#define __riscv_vreinterpret_v_i8m1_i64m1(src) __riscv_th_vreinterpret_v_i8m1_i64m1(src)
+#define __riscv_vreinterpret_v_i8m2_i64m2(src) __riscv_th_vreinterpret_v_i8m2_i64m2(src)
+#define __riscv_vreinterpret_v_i8m4_i64m4(src) __riscv_th_vreinterpret_v_i8m4_i64m4(src)
+#define __riscv_vreinterpret_v_i8m8_i64m8(src) __riscv_th_vreinterpret_v_i8m8_i64m8(src)
+#define __riscv_vreinterpret_v_u8m1_u64m1(src) __riscv_th_vreinterpret_v_u8m1_u64m1(src)
+#define __riscv_vreinterpret_v_u8m2_u64m2(src) __riscv_th_vreinterpret_v_u8m2_u64m2(src)
+#define __riscv_vreinterpret_v_u8m4_u64m4(src) __riscv_th_vreinterpret_v_u8m4_u64m4(src)
+#define __riscv_vreinterpret_v_u8m8_u64m8(src) __riscv_th_vreinterpret_v_u8m8_u64m8(src)
+#define __riscv_vreinterpret_v_i16m1_i8m1(src) __riscv_th_vreinterpret_v_i16m1_i8m1(src)
+#define __riscv_vreinterpret_v_i16m2_i8m2(src) __riscv_th_vreinterpret_v_i16m2_i8m2(src)
+#define __riscv_vreinterpret_v_i16m4_i8m4(src) __riscv_th_vreinterpret_v_i16m4_i8m4(src)
+#define __riscv_vreinterpret_v_i16m8_i8m8(src) __riscv_th_vreinterpret_v_i16m8_i8m8(src)
+#define __riscv_vreinterpret_v_u16m1_u8m1(src) __riscv_th_vreinterpret_v_u16m1_u8m1(src)
+#define __riscv_vreinterpret_v_u16m2_u8m2(src) __riscv_th_vreinterpret_v_u16m2_u8m2(src)
+#define __riscv_vreinterpret_v_u16m4_u8m4(src) __riscv_th_vreinterpret_v_u16m4_u8m4(src)
+#define __riscv_vreinterpret_v_u16m8_u8m8(src) __riscv_th_vreinterpret_v_u16m8_u8m8(src)
+#define __riscv_vreinterpret_v_i16m1_i32m1(src) __riscv_th_vreinterpret_v_i16m1_i32m1(src)
+#define __riscv_vreinterpret_v_i16m2_i32m2(src) __riscv_th_vreinterpret_v_i16m2_i32m2(src)
+#define __riscv_vreinterpret_v_i16m4_i32m4(src) __riscv_th_vreinterpret_v_i16m4_i32m4(src)
+#define __riscv_vreinterpret_v_i16m8_i32m8(src) __riscv_th_vreinterpret_v_i16m8_i32m8(src)
+#define __riscv_vreinterpret_v_u16m1_u32m1(src) __riscv_th_vreinterpret_v_u16m1_u32m1(src)
+#define __riscv_vreinterpret_v_u16m2_u32m2(src) __riscv_th_vreinterpret_v_u16m2_u32m2(src)
+#define __riscv_vreinterpret_v_u16m4_u32m4(src) __riscv_th_vreinterpret_v_u16m4_u32m4(src)
+#define __riscv_vreinterpret_v_u16m8_u32m8(src) __riscv_th_vreinterpret_v_u16m8_u32m8(src)
+#define __riscv_vreinterpret_v_i16m1_i64m1(src) __riscv_th_vreinterpret_v_i16m1_i64m1(src)
+#define __riscv_vreinterpret_v_i16m2_i64m2(src) __riscv_th_vreinterpret_v_i16m2_i64m2(src)
+#define __riscv_vreinterpret_v_i16m4_i64m4(src) __riscv_th_vreinterpret_v_i16m4_i64m4(src)
+#define __riscv_vreinterpret_v_i16m8_i64m8(src) __riscv_th_vreinterpret_v_i16m8_i64m8(src)
+#define __riscv_vreinterpret_v_u16m1_u64m1(src) __riscv_th_vreinterpret_v_u16m1_u64m1(src)
+#define __riscv_vreinterpret_v_u16m2_u64m2(src) __riscv_th_vreinterpret_v_u16m2_u64m2(src)
+#define __riscv_vreinterpret_v_u16m4_u64m4(src) __riscv_th_vreinterpret_v_u16m4_u64m4(src)
+#define __riscv_vreinterpret_v_u16m8_u64m8(src) __riscv_th_vreinterpret_v_u16m8_u64m8(src)
+#define __riscv_vreinterpret_v_i32m1_i8m1(src) __riscv_th_vreinterpret_v_i32m1_i8m1(src)
+#define __riscv_vreinterpret_v_i32m2_i8m2(src) __riscv_th_vreinterpret_v_i32m2_i8m2(src)
+#define __riscv_vreinterpret_v_i32m4_i8m4(src) __riscv_th_vreinterpret_v_i32m4_i8m4(src)
+#define __riscv_vreinterpret_v_i32m8_i8m8(src) __riscv_th_vreinterpret_v_i32m8_i8m8(src)
+#define __riscv_vreinterpret_v_u32m1_u8m1(src) __riscv_th_vreinterpret_v_u32m1_u8m1(src)
+#define __riscv_vreinterpret_v_u32m2_u8m2(src) __riscv_th_vreinterpret_v_u32m2_u8m2(src)
+#define __riscv_vreinterpret_v_u32m4_u8m4(src) __riscv_th_vreinterpret_v_u32m4_u8m4(src)
+#define __riscv_vreinterpret_v_u32m8_u8m8(src) __riscv_th_vreinterpret_v_u32m8_u8m8(src)
+#define __riscv_vreinterpret_v_i32m1_i16m1(src) __riscv_th_vreinterpret_v_i32m1_i16m1(src)
+#define __riscv_vreinterpret_v_i32m2_i16m2(src) __riscv_th_vreinterpret_v_i32m2_i16m2(src)
+#define __riscv_vreinterpret_v_i32m4_i16m4(src) __riscv_th_vreinterpret_v_i32m4_i16m4(src)
+#define __riscv_vreinterpret_v_i32m8_i16m8(src) __riscv_th_vreinterpret_v_i32m8_i16m8(src)
+#define __riscv_vreinterpret_v_u32m1_u16m1(src) __riscv_th_vreinterpret_v_u32m1_u16m1(src)
+#define __riscv_vreinterpret_v_u32m2_u16m2(src) __riscv_th_vreinterpret_v_u32m2_u16m2(src)
+#define __riscv_vreinterpret_v_u32m4_u16m4(src) __riscv_th_vreinterpret_v_u32m4_u16m4(src)
+#define __riscv_vreinterpret_v_u32m8_u16m8(src) __riscv_th_vreinterpret_v_u32m8_u16m8(src)
+#define __riscv_vreinterpret_v_i32m1_i64m1(src) __riscv_th_vreinterpret_v_i32m1_i64m1(src)
+#define __riscv_vreinterpret_v_i32m2_i64m2(src) __riscv_th_vreinterpret_v_i32m2_i64m2(src)
+#define __riscv_vreinterpret_v_i32m4_i64m4(src) __riscv_th_vreinterpret_v_i32m4_i64m4(src)
+#define __riscv_vreinterpret_v_i32m8_i64m8(src) __riscv_th_vreinterpret_v_i32m8_i64m8(src)
+#define __riscv_vreinterpret_v_u32m1_u64m1(src) __riscv_th_vreinterpret_v_u32m1_u64m1(src)
+#define __riscv_vreinterpret_v_u32m2_u64m2(src) __riscv_th_vreinterpret_v_u32m2_u64m2(src)
+#define __riscv_vreinterpret_v_u32m4_u64m4(src) __riscv_th_vreinterpret_v_u32m4_u64m4(src)
+#define __riscv_vreinterpret_v_u32m8_u64m8(src) __riscv_th_vreinterpret_v_u32m8_u64m8(src)
+#define __riscv_vreinterpret_v_i64m1_i8m1(src) __riscv_th_vreinterpret_v_i64m1_i8m1(src)
+#define __riscv_vreinterpret_v_i64m2_i8m2(src) __riscv_th_vreinterpret_v_i64m2_i8m2(src)
+#define __riscv_vreinterpret_v_i64m4_i8m4(src) __riscv_th_vreinterpret_v_i64m4_i8m4(src)
+#define __riscv_vreinterpret_v_i64m8_i8m8(src) __riscv_th_vreinterpret_v_i64m8_i8m8(src)
+#define __riscv_vreinterpret_v_u64m1_u8m1(src) __riscv_th_vreinterpret_v_u64m1_u8m1(src)
+#define __riscv_vreinterpret_v_u64m2_u8m2(src) __riscv_th_vreinterpret_v_u64m2_u8m2(src)
+#define __riscv_vreinterpret_v_u64m4_u8m4(src) __riscv_th_vreinterpret_v_u64m4_u8m4(src)
+#define __riscv_vreinterpret_v_u64m8_u8m8(src) __riscv_th_vreinterpret_v_u64m8_u8m8(src)
+#define __riscv_vreinterpret_v_i64m1_i16m1(src) __riscv_th_vreinterpret_v_i64m1_i16m1(src)
+#define __riscv_vreinterpret_v_i64m2_i16m2(src) __riscv_th_vreinterpret_v_i64m2_i16m2(src)
+#define __riscv_vreinterpret_v_i64m4_i16m4(src) __riscv_th_vreinterpret_v_i64m4_i16m4(src)
+#define __riscv_vreinterpret_v_i64m8_i16m8(src) __riscv_th_vreinterpret_v_i64m8_i16m8(src)
+#define __riscv_vreinterpret_v_u64m1_u16m1(src) __riscv_th_vreinterpret_v_u64m1_u16m1(src)
+#define __riscv_vreinterpret_v_u64m2_u16m2(src) __riscv_th_vreinterpret_v_u64m2_u16m2(src)
+#define __riscv_vreinterpret_v_u64m4_u16m4(src) __riscv_th_vreinterpret_v_u64m4_u16m4(src)
+#define __riscv_vreinterpret_v_u64m8_u16m8(src) __riscv_th_vreinterpret_v_u64m8_u16m8(src)
+#define __riscv_vreinterpret_v_i64m1_i32m1(src) __riscv_th_vreinterpret_v_i64m1_i32m1(src)
+#define __riscv_vreinterpret_v_i64m2_i32m2(src) __riscv_th_vreinterpret_v_i64m2_i32m2(src)
+#define __riscv_vreinterpret_v_i64m4_i32m4(src) __riscv_th_vreinterpret_v_i64m4_i32m4(src)
+#define __riscv_vreinterpret_v_i64m8_i32m8(src) __riscv_th_vreinterpret_v_i64m8_i32m8(src)
+#define __riscv_vreinterpret_v_u64m1_u32m1(src) __riscv_th_vreinterpret_v_u64m1_u32m1(src)
+#define __riscv_vreinterpret_v_u64m2_u32m2(src) __riscv_th_vreinterpret_v_u64m2_u32m2(src)
+#define __riscv_vreinterpret_v_u64m4_u32m4(src) __riscv_th_vreinterpret_v_u64m4_u32m4(src)
+#define __riscv_vreinterpret_v_u64m8_u32m8(src) __riscv_th_vreinterpret_v_u64m8_u32m8(src)
+
+#define __riscv_vreinterpret_v_i8m1_b64(src) __riscv_th_vreinterpret_v_i8m1_b64(src)
+#define __riscv_vreinterpret_v_b64_i8m1(src) __riscv_th_vreinterpret_v_b64_i8m1(src)
+#define __riscv_vreinterpret_v_i8m1_b32(src) __riscv_th_vreinterpret_v_i8m1_b32(src)
+#define __riscv_vreinterpret_v_b32_i8m1(src) __riscv_th_vreinterpret_v_b32_i8m1(src)
+#define __riscv_vreinterpret_v_i8m1_b16(src) __riscv_th_vreinterpret_v_i8m1_b16(src)
+#define __riscv_vreinterpret_v_b16_i8m1(src) __riscv_th_vreinterpret_v_b16_i8m1(src)
+#define __riscv_vreinterpret_v_i8m1_b8(src) __riscv_th_vreinterpret_v_i8m1_b8(src)
+#define __riscv_vreinterpret_v_b8_i8m1(src) __riscv_th_vreinterpret_v_b8_i8m1(src)
+#define __riscv_vreinterpret_v_i8m1_b4(src) __riscv_th_vreinterpret_v_i8m1_b4(src)
+#define __riscv_vreinterpret_v_b4_i8m1(src) __riscv_th_vreinterpret_v_b4_i8m1(src)
+#define __riscv_vreinterpret_v_i8m1_b2(src) __riscv_th_vreinterpret_v_i8m1_b2(src)
+#define __riscv_vreinterpret_v_b2_i8m1(src) __riscv_th_vreinterpret_v_b2_i8m1(src)
+#define __riscv_vreinterpret_v_i8m1_b1(src) __riscv_th_vreinterpret_v_i8m1_b1(src)
+#define __riscv_vreinterpret_v_b1_i8m1(src) __riscv_th_vreinterpret_v_b1_i8m1(src)
+#define __riscv_vreinterpret_v_u8m1_b64(src) __riscv_th_vreinterpret_v_u8m1_b64(src)
+#define __riscv_vreinterpret_v_b64_u8m1(src) __riscv_th_vreinterpret_v_b64_u8m1(src)
+#define __riscv_vreinterpret_v_u8m1_b32(src) __riscv_th_vreinterpret_v_u8m1_b32(src)
+#define __riscv_vreinterpret_v_b32_u8m1(src) __riscv_th_vreinterpret_v_b32_u8m1(src)
+#define __riscv_vreinterpret_v_u8m1_b16(src) __riscv_th_vreinterpret_v_u8m1_b16(src)
+#define __riscv_vreinterpret_v_b16_u8m1(src) __riscv_th_vreinterpret_v_b16_u8m1(src)
+#define __riscv_vreinterpret_v_u8m1_b8(src) __riscv_th_vreinterpret_v_u8m1_b8(src)
+#define __riscv_vreinterpret_v_b8_u8m1(src) __riscv_th_vreinterpret_v_b8_u8m1(src)
+#define __riscv_vreinterpret_v_u8m1_b4(src) __riscv_th_vreinterpret_v_u8m1_b4(src)
+#define __riscv_vreinterpret_v_b4_u8m1(src) __riscv_th_vreinterpret_v_b4_u8m1(src)
+#define __riscv_vreinterpret_v_u8m1_b2(src) __riscv_th_vreinterpret_v_u8m1_b2(src)
+#define __riscv_vreinterpret_v_b2_u8m1(src) __riscv_th_vreinterpret_v_b2_u8m1(src)
+#define __riscv_vreinterpret_v_u8m1_b1(src) __riscv_th_vreinterpret_v_u8m1_b1(src)
+#define __riscv_vreinterpret_v_b1_u8m1(src) __riscv_th_vreinterpret_v_b1_u8m1(src)
+#define __riscv_vreinterpret_v_i16m1_b64(src) __riscv_th_vreinterpret_v_i16m1_b64(src)
+#define __riscv_vreinterpret_v_b64_i16m1(src) __riscv_th_vreinterpret_v_b64_i16m1(src)
+#define __riscv_vreinterpret_v_i16m1_b32(src) __riscv_th_vreinterpret_v_i16m1_b32(src)
+#define __riscv_vreinterpret_v_b32_i16m1(src) __riscv_th_vreinterpret_v_b32_i16m1(src)
+#define __riscv_vreinterpret_v_i16m1_b16(src) __riscv_th_vreinterpret_v_i16m1_b16(src)
+#define __riscv_vreinterpret_v_b16_i16m1(src) __riscv_th_vreinterpret_v_b16_i16m1(src)
+#define __riscv_vreinterpret_v_i16m1_b8(src) __riscv_th_vreinterpret_v_i16m1_b8(src)
+#define __riscv_vreinterpret_v_b8_i16m1(src) __riscv_th_vreinterpret_v_b8_i16m1(src)
+#define __riscv_vreinterpret_v_i16m1_b4(src) __riscv_th_vreinterpret_v_i16m1_b4(src)
+#define __riscv_vreinterpret_v_b4_i16m1(src) __riscv_th_vreinterpret_v_b4_i16m1(src)
+#define __riscv_vreinterpret_v_i16m1_b2(src) __riscv_th_vreinterpret_v_i16m1_b2(src)
+#define __riscv_vreinterpret_v_b2_i16m1(src) __riscv_th_vreinterpret_v_b2_i16m1(src)
+#define __riscv_vreinterpret_v_u16m1_b64(src) __riscv_th_vreinterpret_v_u16m1_b64(src)
+#define __riscv_vreinterpret_v_b64_u16m1(src) __riscv_th_vreinterpret_v_b64_u16m1(src)
+#define __riscv_vreinterpret_v_u16m1_b32(src) __riscv_th_vreinterpret_v_u16m1_b32(src)
+#define __riscv_vreinterpret_v_b32_u16m1(src) __riscv_th_vreinterpret_v_b32_u16m1(src)
+#define __riscv_vreinterpret_v_u16m1_b16(src) __riscv_th_vreinterpret_v_u16m1_b16(src)
+#define __riscv_vreinterpret_v_b16_u16m1(src) __riscv_th_vreinterpret_v_b16_u16m1(src)
+#define __riscv_vreinterpret_v_u16m1_b8(src) __riscv_th_vreinterpret_v_u16m1_b8(src)
+#define __riscv_vreinterpret_v_b8_u16m1(src) __riscv_th_vreinterpret_v_b8_u16m1(src)
+#define __riscv_vreinterpret_v_u16m1_b4(src) __riscv_th_vreinterpret_v_u16m1_b4(src)
+#define __riscv_vreinterpret_v_b4_u16m1(src) __riscv_th_vreinterpret_v_b4_u16m1(src)
+#define __riscv_vreinterpret_v_u16m1_b2(src) __riscv_th_vreinterpret_v_u16m1_b2(src)
+#define __riscv_vreinterpret_v_b2_u16m1(src) __riscv_th_vreinterpret_v_b2_u16m1(src)
+#define __riscv_vreinterpret_v_i32m1_b64(src) __riscv_th_vreinterpret_v_i32m1_b64(src)
+#define __riscv_vreinterpret_v_b64_i32m1(src) __riscv_th_vreinterpret_v_b64_i32m1(src)
+#define __riscv_vreinterpret_v_i32m1_b32(src) __riscv_th_vreinterpret_v_i32m1_b32(src)
+#define __riscv_vreinterpret_v_b32_i32m1(src) __riscv_th_vreinterpret_v_b32_i32m1(src)
+#define __riscv_vreinterpret_v_i32m1_b16(src) __riscv_th_vreinterpret_v_i32m1_b16(src)
+#define __riscv_vreinterpret_v_b16_i32m1(src) __riscv_th_vreinterpret_v_b16_i32m1(src)
+#define __riscv_vreinterpret_v_i32m1_b8(src) __riscv_th_vreinterpret_v_i32m1_b8(src)
+#define __riscv_vreinterpret_v_b8_i32m1(src) __riscv_th_vreinterpret_v_b8_i32m1(src)
+#define __riscv_vreinterpret_v_i32m1_b4(src) __riscv_th_vreinterpret_v_i32m1_b4(src)
+#define __riscv_vreinterpret_v_b4_i32m1(src) __riscv_th_vreinterpret_v_b4_i32m1(src)
+#define __riscv_vreinterpret_v_u32m1_b64(src) __riscv_th_vreinterpret_v_u32m1_b64(src)
+#define __riscv_vreinterpret_v_b64_u32m1(src) __riscv_th_vreinterpret_v_b64_u32m1(src)
+#define __riscv_vreinterpret_v_u32m1_b32(src) __riscv_th_vreinterpret_v_u32m1_b32(src)
+#define __riscv_vreinterpret_v_b32_u32m1(src) __riscv_th_vreinterpret_v_b32_u32m1(src)
+#define __riscv_vreinterpret_v_u32m1_b16(src) __riscv_th_vreinterpret_v_u32m1_b16(src)
+#define __riscv_vreinterpret_v_b16_u32m1(src) __riscv_th_vreinterpret_v_b16_u32m1(src)
+#define __riscv_vreinterpret_v_u32m1_b8(src) __riscv_th_vreinterpret_v_u32m1_b8(src)
+#define __riscv_vreinterpret_v_b8_u32m1(src) __riscv_th_vreinterpret_v_b8_u32m1(src)
+#define __riscv_vreinterpret_v_u32m1_b4(src) __riscv_th_vreinterpret_v_u32m1_b4(src)
+#define __riscv_vreinterpret_v_b4_u32m1(src) __riscv_th_vreinterpret_v_b4_u32m1(src)
+#define __riscv_vreinterpret_v_i64m1_b64(src) __riscv_th_vreinterpret_v_i64m1_b64(src)
+#define __riscv_vreinterpret_v_b64_i64m1(src) __riscv_th_vreinterpret_v_b64_i64m1(src)
+#define __riscv_vreinterpret_v_i64m1_b32(src) __riscv_th_vreinterpret_v_i64m1_b32(src)
+#define __riscv_vreinterpret_v_b32_i64m1(src) __riscv_th_vreinterpret_v_b32_i64m1(src)
+#define __riscv_vreinterpret_v_i64m1_b16(src) __riscv_th_vreinterpret_v_i64m1_b16(src)
+#define __riscv_vreinterpret_v_b16_i64m1(src) __riscv_th_vreinterpret_v_b16_i64m1(src)
+#define __riscv_vreinterpret_v_i64m1_b8(src) __riscv_th_vreinterpret_v_i64m1_b8(src)
+#define __riscv_vreinterpret_v_b8_i64m1(src) __riscv_th_vreinterpret_v_b8_i64m1(src)
+#define __riscv_vreinterpret_v_u64m1_b64(src) __riscv_th_vreinterpret_v_u64m1_b64(src)
+#define __riscv_vreinterpret_v_b64_u64m1(src) __riscv_th_vreinterpret_v_b64_u64m1(src)
+#define __riscv_vreinterpret_v_u64m1_b32(src) __riscv_th_vreinterpret_v_u64m1_b32(src)
+#define __riscv_vreinterpret_v_b32_u64m1(src) __riscv_th_vreinterpret_v_b32_u64m1(src)
+#define __riscv_vreinterpret_v_u64m1_b16(src) __riscv_th_vreinterpret_v_u64m1_b16(src)
+#define __riscv_vreinterpret_v_b16_u64m1(src) __riscv_th_vreinterpret_v_b16_u64m1(src)
+#define __riscv_vreinterpret_v_u64m1_b8(src) __riscv_th_vreinterpret_v_u64m1_b8(src)
+#define __riscv_vreinterpret_v_b8_u64m1(src) __riscv_th_vreinterpret_v_b8_u64m1(src)
+
 }] in
 def th_vector_misc_wrapper_macros: RVVHeader;
diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/misc/thead/vreinterpret_b.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/misc/thead/vreinterpret_b.c
new file mode 100644
index 00000000000000..0b7376bc823de4
--- /dev/null
+++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/misc/thead/vreinterpret_b.c
@@ -0,0 +1,975 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
+// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \
+// RUN:   -disable-O0-optnone -emit-llvm %s -o - | \
+// RUN:   opt -S -passes=mem2reg | \
+// RUN:   FileCheck --check-prefix=CHECK-RV64 %s
+
+#include <riscv_vector.h>
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vreinterpret_v_i8m1_b64
+// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i8> [[SRC]] to <vscale x 64 x i1>
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 1 x i1> @llvm.vector.extract.nxv1i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)
+// CHECK-RV64-NEXT:    ret <vscale x 1 x i1> [[TMP1]]
+//
+vbool64_t test_vreinterpret_v_i8m1_b64(vint8m1_t src) {
+  return __riscv_th_vreinterpret_v_i8m1_b64(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_b64_i8m1
+// CHECK-RV64-SAME: (<vscale x 1 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv1i1(<vscale x 64 x i1> poison, <vscale x 1 x i1> [[SRC]], i64 0)
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 8 x i8>
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP1]]
+//
+vint8m1_t test_vreinterpret_v_b64_i8m1(vbool64_t src) {
+  return __riscv_th_vreinterpret_v_b64_i8m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vreinterpret_v_i8m1_b32
+// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i8> [[SRC]] to <vscale x 64 x i1>
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)
+// CHECK-RV64-NEXT:    ret <vscale x 2 x i1> [[TMP1]]
+//
+vbool32_t test_vreinterpret_v_i8m1_b32(vint8m1_t src) {
+  return __riscv_th_vreinterpret_v_i8m1_b32(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_b32_i8m1
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv2i1(<vscale x 64 x i1> poison, <vscale x 2 x i1> [[SRC]], i64 0)
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 8 x i8>
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP1]]
+//
+vint8m1_t test_vreinterpret_v_b32_i8m1(vbool32_t src) {
+  return __riscv_th_vreinterpret_v_b32_i8m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vreinterpret_v_i8m1_b16
+// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i8> [[SRC]] to <vscale x 64 x i1>
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 4 x i1> @llvm.vector.extract.nxv4i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i1> [[TMP1]]
+//
+vbool16_t test_vreinterpret_v_i8m1_b16(vint8m1_t src) {
+  return __riscv_th_vreinterpret_v_i8m1_b16(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_b16_i8m1
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv4i1(<vscale x 64 x i1> poison, <vscale x 4 x i1> [[SRC]], i64 0)
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 8 x i8>
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP1]]
+//
+vint8m1_t test_vreinterpret_v_b16_i8m1(vbool16_t src) {
+  return __riscv_th_vreinterpret_v_b16_i8m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vreinterpret_v_i8m1_b8
+// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i8> [[SRC]] to <vscale x 64 x i1>
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 8 x i1> @llvm.vector.extract.nxv8i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i1> [[TMP1]]
+//
+vbool8_t test_vreinterpret_v_i8m1_b8(vint8m1_t src) {
+  return __riscv_th_vreinterpret_v_i8m1_b8(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_b8_i8m1
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv8i1(<vscale x 64 x i1> poison, <vscale x 8 x i1> [[SRC]], i64 0)
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 8 x i8>
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP1]]
+//
+vint8m1_t test_vreinterpret_v_b8_i8m1(vbool8_t src) {
+  return __riscv_th_vreinterpret_v_b8_i8m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vreinterpret_v_i8m1_b4
+// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i8> [[SRC]] to <vscale x 64 x i1>
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 16 x i1> @llvm.vector.extract.nxv16i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)
+// CHECK-RV64-NEXT:    ret <vscale x 16 x i1> [[TMP1]]
+//
+vbool4_t test_vreinterpret_v_i8m1_b4(vint8m1_t src) {
+  return __riscv_th_vreinterpret_v_i8m1_b4(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_b4_i8m1
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv16i1(<vscale x 64 x i1> poison, <vscale x 16 x i1> [[SRC]], i64 0)
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 8 x i8>
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP1]]
+//
+vint8m1_t test_vreinterpret_v_b4_i8m1(vbool4_t src) {
+  return __riscv_th_vreinterpret_v_b4_i8m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i1> @test_vreinterpret_v_i8m1_b2
+// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i8> [[SRC]] to <vscale x 64 x i1>
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 32 x i1> @llvm.vector.extract.nxv32i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)
+// CHECK-RV64-NEXT:    ret <vscale x 32 x i1> [[TMP1]]
+//
+vbool2_t test_vreinterpret_v_i8m1_b2(vint8m1_t src) {
+  return __riscv_th_vreinterpret_v_i8m1_b2(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_b2_i8m1
+// CHECK-RV64-SAME: (<vscale x 32 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv32i1(<vscale x 64 x i1> poison, <vscale x 32 x i1> [[SRC]], i64 0)
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 8 x i8>
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP1]]
+//
+vint8m1_t test_vreinterpret_v_b2_i8m1(vbool2_t src) {
+  return __riscv_th_vreinterpret_v_b2_i8m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i1> @test_vreinterpret_v_i8m1_b1
+// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i8> [[SRC]] to <vscale x 64 x i1>
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 64 x i1> @llvm.vector.extract.nxv64i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)
+// CHECK-RV64-NEXT:    ret <vscale x 64 x i1> [[TMP1]]
+//
+vbool1_t test_vreinterpret_v_i8m1_b1(vint8m1_t src) {
+  return __riscv_th_vreinterpret_v_i8m1_b1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_b1_i8m1
+// CHECK-RV64-SAME: (<vscale x 64 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv64i1(<vscale x 64 x i1> poison, <vscale x 64 x i1> [[SRC]], i64 0)
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 8 x i8>
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP1]]
+//
+vint8m1_t test_vreinterpret_v_b1_i8m1(vbool1_t src) {
+  return __riscv_th_vreinterpret_v_b1_i8m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vreinterpret_v_u8m1_b64
+// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i8> [[SRC]] to <vscale x 64 x i1>
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 1 x i1> @llvm.vector.extract.nxv1i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)
+// CHECK-RV64-NEXT:    ret <vscale x 1 x i1> [[TMP1]]
+//
+vbool64_t test_vreinterpret_v_u8m1_b64(vuint8m1_t src) {
+  return __riscv_th_vreinterpret_v_u8m1_b64(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_b64_u8m1
+// CHECK-RV64-SAME: (<vscale x 1 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv1i1(<vscale x 64 x i1> poison, <vscale x 1 x i1> [[SRC]], i64 0)
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 8 x i8>
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP1]]
+//
+vuint8m1_t test_vreinterpret_v_b64_u8m1(vbool64_t src) {
+  return __riscv_th_vreinterpret_v_b64_u8m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vreinterpret_v_u8m1_b32
+// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i8> [[SRC]] to <vscale x 64 x i1>
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)
+// CHECK-RV64-NEXT:    ret <vscale x 2 x i1> [[TMP1]]
+//
+vbool32_t test_vreinterpret_v_u8m1_b32(vuint8m1_t src) {
+  return __riscv_th_vreinterpret_v_u8m1_b32(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_b32_u8m1
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv2i1(<vscale x 64 x i1> poison, <vscale x 2 x i1> [[SRC]], i64 0)
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 8 x i8>
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP1]]
+//
+vuint8m1_t test_vreinterpret_v_b32_u8m1(vbool32_t src) {
+  return __riscv_th_vreinterpret_v_b32_u8m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vreinterpret_v_u8m1_b16
+// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i8> [[SRC]] to <vscale x 64 x i1>
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 4 x i1> @llvm.vector.extract.nxv4i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i1> [[TMP1]]
+//
+vbool16_t test_vreinterpret_v_u8m1_b16(vuint8m1_t src) {
+  return __riscv_th_vreinterpret_v_u8m1_b16(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_b16_u8m1
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv4i1(<vscale x 64 x i1> poison, <vscale x 4 x i1> [[SRC]], i64 0)
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 8 x i8>
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP1]]
+//
+vuint8m1_t test_vreinterpret_v_b16_u8m1(vbool16_t src) {
+  return __riscv_th_vreinterpret_v_b16_u8m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vreinterpret_v_u8m1_b8
+// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i8> [[SRC]] to <vscale x 64 x i1>
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 8 x i1> @llvm.vector.extract.nxv8i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i1> [[TMP1]]
+//
+vbool8_t test_vreinterpret_v_u8m1_b8(vuint8m1_t src) {
+  return __riscv_th_vreinterpret_v_u8m1_b8(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_b8_u8m1
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv8i1(<vscale x 64 x i1> poison, <vscale x 8 x i1> [[SRC]], i64 0)
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 8 x i8>
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP1]]
+//
+vuint8m1_t test_vreinterpret_v_b8_u8m1(vbool8_t src) {
+  return __riscv_th_vreinterpret_v_b8_u8m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vreinterpret_v_u8m1_b4
+// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i8> [[SRC]] to <vscale x 64 x i1>
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 16 x i1> @llvm.vector.extract.nxv16i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)
+// CHECK-RV64-NEXT:    ret <vscale x 16 x i1> [[TMP1]]
+//
+vbool4_t test_vreinterpret_v_u8m1_b4(vuint8m1_t src) {
+  return __riscv_th_vreinterpret_v_u8m1_b4(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_b4_u8m1
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv16i1(<vscale x 64 x i1> poison, <vscale x 16 x i1> [[SRC]], i64 0)
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 8 x i8>
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP1]]
+//
+vuint8m1_t test_vreinterpret_v_b4_u8m1(vbool4_t src) {
+  return __riscv_th_vreinterpret_v_b4_u8m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i1> @test_vreinterpret_v_u8m1_b2
+// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i8> [[SRC]] to <vscale x 64 x i1>
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 32 x i1> @llvm.vector.extract.nxv32i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)
+// CHECK-RV64-NEXT:    ret <vscale x 32 x i1> [[TMP1]]
+//
+vbool2_t test_vreinterpret_v_u8m1_b2(vuint8m1_t src) {
+  return __riscv_th_vreinterpret_v_u8m1_b2(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_b2_u8m1
+// CHECK-RV64-SAME: (<vscale x 32 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv32i1(<vscale x 64 x i1> poison, <vscale x 32 x i1> [[SRC]], i64 0)
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 8 x i8>
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP1]]
+//
+vuint8m1_t test_vreinterpret_v_b2_u8m1(vbool2_t src) {
+  return __riscv_th_vreinterpret_v_b2_u8m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i1> @test_vreinterpret_v_u8m1_b1
+// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i8> [[SRC]] to <vscale x 64 x i1>
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 64 x i1> @llvm.vector.extract.nxv64i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)
+// CHECK-RV64-NEXT:    ret <vscale x 64 x i1> [[TMP1]]
+//
+vbool1_t test_vreinterpret_v_u8m1_b1(vuint8m1_t src) {
+  return __riscv_th_vreinterpret_v_u8m1_b1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_b1_u8m1
+// CHECK-RV64-SAME: (<vscale x 64 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv64i1(<vscale x 64 x i1> poison, <vscale x 64 x i1> [[SRC]], i64 0)
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 8 x i8>
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP1]]
+//
+vuint8m1_t test_vreinterpret_v_b1_u8m1(vbool1_t src) {
+  return __riscv_th_vreinterpret_v_b1_u8m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vreinterpret_v_i16m1_b64
+// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC]] to <vscale x 64 x i1>
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 1 x i1> @llvm.vector.extract.nxv1i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)
+// CHECK-RV64-NEXT:    ret <vscale x 1 x i1> [[TMP1]]
+//
+vbool64_t test_vreinterpret_v_i16m1_b64(vint16m1_t src) {
+  return __riscv_th_vreinterpret_v_i16m1_b64(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_b64_i16m1
+// CHECK-RV64-SAME: (<vscale x 1 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv1i1(<vscale x 64 x i1> poison, <vscale x 1 x i1> [[SRC]], i64 0)
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 4 x i16>
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP1]]
+//
+vint16m1_t test_vreinterpret_v_b64_i16m1(vbool64_t src) {
+  return __riscv_th_vreinterpret_v_b64_i16m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vreinterpret_v_i16m1_b32
+// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC]] to <vscale x 64 x i1>
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)
+// CHECK-RV64-NEXT:    ret <vscale x 2 x i1> [[TMP1]]
+//
+vbool32_t test_vreinterpret_v_i16m1_b32(vint16m1_t src) {
+  return __riscv_th_vreinterpret_v_i16m1_b32(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_b32_i16m1
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv2i1(<vscale x 64 x i1> poison, <vscale x 2 x i1> [[SRC]], i64 0)
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 4 x i16>
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP1]]
+//
+vint16m1_t test_vreinterpret_v_b32_i16m1(vbool32_t src) {
+  return __riscv_th_vreinterpret_v_b32_i16m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vreinterpret_v_i16m1_b16
+// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC]] to <vscale x 64 x i1>
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 4 x i1> @llvm.vector.extract.nxv4i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i1> [[TMP1]]
+//
+vbool16_t test_vreinterpret_v_i16m1_b16(vint16m1_t src) {
+  return __riscv_th_vreinterpret_v_i16m1_b16(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_b16_i16m1
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv4i1(<vscale x 64 x i1> poison, <vscale x 4 x i1> [[SRC]], i64 0)
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 4 x i16>
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP1]]
+//
+vint16m1_t test_vreinterpret_v_b16_i16m1(vbool16_t src) {
+  return __riscv_th_vreinterpret_v_b16_i16m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vreinterpret_v_i16m1_b8
+// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC]] to <vscale x 64 x i1>
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 8 x i1> @llvm.vector.extract.nxv8i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i1> [[TMP1]]
+//
+vbool8_t test_vreinterpret_v_i16m1_b8(vint16m1_t src) {
+  return __riscv_th_vreinterpret_v_i16m1_b8(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_b8_i16m1
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv8i1(<vscale x 64 x i1> poison, <vscale x 8 x i1> [[SRC]], i64 0)
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 4 x i16>
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP1]]
+//
+vint16m1_t test_vreinterpret_v_b8_i16m1(vbool8_t src) {
+  return __riscv_th_vreinterpret_v_b8_i16m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vreinterpret_v_i16m1_b4
+// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC]] to <vscale x 64 x i1>
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 16 x i1> @llvm.vector.extract.nxv16i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)
+// CHECK-RV64-NEXT:    ret <vscale x 16 x i1> [[TMP1]]
+//
+vbool4_t test_vreinterpret_v_i16m1_b4(vint16m1_t src) {
+  return __riscv_th_vreinterpret_v_i16m1_b4(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_b4_i16m1
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv16i1(<vscale x 64 x i1> poison, <vscale x 16 x i1> [[SRC]], i64 0)
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 4 x i16>
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP1]]
+//
+vint16m1_t test_vreinterpret_v_b4_i16m1(vbool4_t src) {
+  return __riscv_th_vreinterpret_v_b4_i16m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i1> @test_vreinterpret_v_i16m1_b2
+// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC]] to <vscale x 64 x i1>
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 32 x i1> @llvm.vector.extract.nxv32i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)
+// CHECK-RV64-NEXT:    ret <vscale x 32 x i1> [[TMP1]]
+//
+vbool2_t test_vreinterpret_v_i16m1_b2(vint16m1_t src) {
+  return __riscv_th_vreinterpret_v_i16m1_b2(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_b2_i16m1
+// CHECK-RV64-SAME: (<vscale x 32 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv32i1(<vscale x 64 x i1> poison, <vscale x 32 x i1> [[SRC]], i64 0)
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 4 x i16>
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP1]]
+//
+vint16m1_t test_vreinterpret_v_b2_i16m1(vbool2_t src) {
+  return __riscv_th_vreinterpret_v_b2_i16m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vreinterpret_v_u16m1_b64
+// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC]] to <vscale x 64 x i1>
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 1 x i1> @llvm.vector.extract.nxv1i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)
+// CHECK-RV64-NEXT:    ret <vscale x 1 x i1> [[TMP1]]
+//
+vbool64_t test_vreinterpret_v_u16m1_b64(vuint16m1_t src) {
+  return __riscv_th_vreinterpret_v_u16m1_b64(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_b64_u16m1
+// CHECK-RV64-SAME: (<vscale x 1 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv1i1(<vscale x 64 x i1> poison, <vscale x 1 x i1> [[SRC]], i64 0)
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 4 x i16>
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP1]]
+//
+vuint16m1_t test_vreinterpret_v_b64_u16m1(vbool64_t src) {
+  return __riscv_th_vreinterpret_v_b64_u16m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vreinterpret_v_u16m1_b32
+// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC]] to <vscale x 64 x i1>
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)
+// CHECK-RV64-NEXT:    ret <vscale x 2 x i1> [[TMP1]]
+//
+vbool32_t test_vreinterpret_v_u16m1_b32(vuint16m1_t src) {
+  return __riscv_th_vreinterpret_v_u16m1_b32(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_b32_u16m1
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv2i1(<vscale x 64 x i1> poison, <vscale x 2 x i1> [[SRC]], i64 0)
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 4 x i16>
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP1]]
+//
+vuint16m1_t test_vreinterpret_v_b32_u16m1(vbool32_t src) {
+  return __riscv_th_vreinterpret_v_b32_u16m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vreinterpret_v_u16m1_b16
+// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC]] to <vscale x 64 x i1>
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 4 x i1> @llvm.vector.extract.nxv4i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i1> [[TMP1]]
+//
+vbool16_t test_vreinterpret_v_u16m1_b16(vuint16m1_t src) {
+  return __riscv_th_vreinterpret_v_u16m1_b16(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_b16_u16m1
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv4i1(<vscale x 64 x i1> poison, <vscale x 4 x i1> [[SRC]], i64 0)
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 4 x i16>
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP1]]
+//
+vuint16m1_t test_vreinterpret_v_b16_u16m1(vbool16_t src) {
+  return __riscv_th_vreinterpret_v_b16_u16m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vreinterpret_v_u16m1_b8
+// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC]] to <vscale x 64 x i1>
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 8 x i1> @llvm.vector.extract.nxv8i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i1> [[TMP1]]
+//
+vbool8_t test_vreinterpret_v_u16m1_b8(vuint16m1_t src) {
+  return __riscv_th_vreinterpret_v_u16m1_b8(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_b8_u16m1
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv8i1(<vscale x 64 x i1> poison, <vscale x 8 x i1> [[SRC]], i64 0)
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 4 x i16>
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP1]]
+//
+vuint16m1_t test_vreinterpret_v_b8_u16m1(vbool8_t src) {
+  return __riscv_th_vreinterpret_v_b8_u16m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vreinterpret_v_u16m1_b4
+// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC]] to <vscale x 64 x i1>
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 16 x i1> @llvm.vector.extract.nxv16i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)
+// CHECK-RV64-NEXT:    ret <vscale x 16 x i1> [[TMP1]]
+//
+vbool4_t test_vreinterpret_v_u16m1_b4(vuint16m1_t src) {
+  return __riscv_th_vreinterpret_v_u16m1_b4(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_b4_u16m1
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv16i1(<vscale x 64 x i1> poison, <vscale x 16 x i1> [[SRC]], i64 0)
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 4 x i16>
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP1]]
+//
+vuint16m1_t test_vreinterpret_v_b4_u16m1(vbool4_t src) {
+  return __riscv_th_vreinterpret_v_b4_u16m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i1> @test_vreinterpret_v_u16m1_b2
+// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC]] to <vscale x 64 x i1>
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 32 x i1> @llvm.vector.extract.nxv32i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)
+// CHECK-RV64-NEXT:    ret <vscale x 32 x i1> [[TMP1]]
+//
+vbool2_t test_vreinterpret_v_u16m1_b2(vuint16m1_t src) {
+  return __riscv_th_vreinterpret_v_u16m1_b2(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_b2_u16m1
+// CHECK-RV64-SAME: (<vscale x 32 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv32i1(<vscale x 64 x i1> poison, <vscale x 32 x i1> [[SRC]], i64 0)
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 4 x i16>
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP1]]
+//
+vuint16m1_t test_vreinterpret_v_b2_u16m1(vbool2_t src) {
+  return __riscv_th_vreinterpret_v_b2_u16m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vreinterpret_v_i32m1_b64
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i32> [[SRC]] to <vscale x 64 x i1>
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 1 x i1> @llvm.vector.extract.nxv1i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)
+// CHECK-RV64-NEXT:    ret <vscale x 1 x i1> [[TMP1]]
+//
+vbool64_t test_vreinterpret_v_i32m1_b64(vint32m1_t src) {
+  return __riscv_th_vreinterpret_v_i32m1_b64(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_b64_i32m1
+// CHECK-RV64-SAME: (<vscale x 1 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv1i1(<vscale x 64 x i1> poison, <vscale x 1 x i1> [[SRC]], i64 0)
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 2 x i32>
+// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP1]]
+//
+vint32m1_t test_vreinterpret_v_b64_i32m1(vbool64_t src) {
+  return __riscv_th_vreinterpret_v_b64_i32m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vreinterpret_v_i32m1_b32
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i32> [[SRC]] to <vscale x 64 x i1>
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)
+// CHECK-RV64-NEXT:    ret <vscale x 2 x i1> [[TMP1]]
+//
+vbool32_t test_vreinterpret_v_i32m1_b32(vint32m1_t src) {
+  return __riscv_th_vreinterpret_v_i32m1_b32(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_b32_i32m1
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv2i1(<vscale x 64 x i1> poison, <vscale x 2 x i1> [[SRC]], i64 0)
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 2 x i32>
+// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP1]]
+//
+vint32m1_t test_vreinterpret_v_b32_i32m1(vbool32_t src) {
+  return __riscv_th_vreinterpret_v_b32_i32m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vreinterpret_v_i32m1_b16
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i32> [[SRC]] to <vscale x 64 x i1>
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 4 x i1> @llvm.vector.extract.nxv4i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i1> [[TMP1]]
+//
+vbool16_t test_vreinterpret_v_i32m1_b16(vint32m1_t src) {
+  return __riscv_th_vreinterpret_v_i32m1_b16(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_b16_i32m1
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv4i1(<vscale x 64 x i1> poison, <vscale x 4 x i1> [[SRC]], i64 0)
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 2 x i32>
+// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP1]]
+//
+vint32m1_t test_vreinterpret_v_b16_i32m1(vbool16_t src) {
+  return __riscv_th_vreinterpret_v_b16_i32m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vreinterpret_v_i32m1_b8
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i32> [[SRC]] to <vscale x 64 x i1>
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 8 x i1> @llvm.vector.extract.nxv8i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i1> [[TMP1]]
+//
+vbool8_t test_vreinterpret_v_i32m1_b8(vint32m1_t src) {
+  return __riscv_th_vreinterpret_v_i32m1_b8(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_b8_i32m1
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv8i1(<vscale x 64 x i1> poison, <vscale x 8 x i1> [[SRC]], i64 0)
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 2 x i32>
+// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP1]]
+//
+vint32m1_t test_vreinterpret_v_b8_i32m1(vbool8_t src) {
+  return __riscv_th_vreinterpret_v_b8_i32m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vreinterpret_v_i32m1_b4
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i32> [[SRC]] to <vscale x 64 x i1>
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 16 x i1> @llvm.vector.extract.nxv16i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)
+// CHECK-RV64-NEXT:    ret <vscale x 16 x i1> [[TMP1]]
+//
+vbool4_t test_vreinterpret_v_i32m1_b4(vint32m1_t src) {
+  return __riscv_th_vreinterpret_v_i32m1_b4(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_b4_i32m1
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv16i1(<vscale x 64 x i1> poison, <vscale x 16 x i1> [[SRC]], i64 0)
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 2 x i32>
+// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP1]]
+//
+vint32m1_t test_vreinterpret_v_b4_i32m1(vbool4_t src) {
+  return __riscv_th_vreinterpret_v_b4_i32m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vreinterpret_v_u32m1_b64
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i32> [[SRC]] to <vscale x 64 x i1>
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 1 x i1> @llvm.vector.extract.nxv1i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)
+// CHECK-RV64-NEXT:    ret <vscale x 1 x i1> [[TMP1]]
+//
+vbool64_t test_vreinterpret_v_u32m1_b64(vuint32m1_t src) {
+  return __riscv_th_vreinterpret_v_u32m1_b64(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_b64_u32m1
+// CHECK-RV64-SAME: (<vscale x 1 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv1i1(<vscale x 64 x i1> poison, <vscale x 1 x i1> [[SRC]], i64 0)
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 2 x i32>
+// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP1]]
+//
+vuint32m1_t test_vreinterpret_v_b64_u32m1(vbool64_t src) {
+  return __riscv_th_vreinterpret_v_b64_u32m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vreinterpret_v_u32m1_b32
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i32> [[SRC]] to <vscale x 64 x i1>
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)
+// CHECK-RV64-NEXT:    ret <vscale x 2 x i1> [[TMP1]]
+//
+vbool32_t test_vreinterpret_v_u32m1_b32(vuint32m1_t src) {
+  return __riscv_th_vreinterpret_v_u32m1_b32(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_b32_u32m1
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv2i1(<vscale x 64 x i1> poison, <vscale x 2 x i1> [[SRC]], i64 0)
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 2 x i32>
+// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP1]]
+//
+vuint32m1_t test_vreinterpret_v_b32_u32m1(vbool32_t src) {
+  return __riscv_th_vreinterpret_v_b32_u32m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vreinterpret_v_u32m1_b16
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i32> [[SRC]] to <vscale x 64 x i1>
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 4 x i1> @llvm.vector.extract.nxv4i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i1> [[TMP1]]
+//
+vbool16_t test_vreinterpret_v_u32m1_b16(vuint32m1_t src) {
+  return __riscv_th_vreinterpret_v_u32m1_b16(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_b16_u32m1
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv4i1(<vscale x 64 x i1> poison, <vscale x 4 x i1> [[SRC]], i64 0)
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 2 x i32>
+// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP1]]
+//
+vuint32m1_t test_vreinterpret_v_b16_u32m1(vbool16_t src) {
+  return __riscv_th_vreinterpret_v_b16_u32m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vreinterpret_v_u32m1_b8
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i32> [[SRC]] to <vscale x 64 x i1>
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 8 x i1> @llvm.vector.extract.nxv8i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i1> [[TMP1]]
+//
+vbool8_t test_vreinterpret_v_u32m1_b8(vuint32m1_t src) {
+  return __riscv_th_vreinterpret_v_u32m1_b8(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_b8_u32m1
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv8i1(<vscale x 64 x i1> poison, <vscale x 8 x i1> [[SRC]], i64 0)
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 2 x i32>
+// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP1]]
+//
+vuint32m1_t test_vreinterpret_v_b8_u32m1(vbool8_t src) {
+  return __riscv_th_vreinterpret_v_b8_u32m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vreinterpret_v_u32m1_b4
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i32> [[SRC]] to <vscale x 64 x i1>
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 16 x i1> @llvm.vector.extract.nxv16i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)
+// CHECK-RV64-NEXT:    ret <vscale x 16 x i1> [[TMP1]]
+//
+vbool4_t test_vreinterpret_v_u32m1_b4(vuint32m1_t src) {
+  return __riscv_th_vreinterpret_v_u32m1_b4(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_b4_u32m1
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv16i1(<vscale x 64 x i1> poison, <vscale x 16 x i1> [[SRC]], i64 0)
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 2 x i32>
+// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP1]]
+//
+vuint32m1_t test_vreinterpret_v_b4_u32m1(vbool4_t src) {
+  return __riscv_th_vreinterpret_v_b4_u32m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vreinterpret_v_i64m1_b64
+// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i64> [[SRC]] to <vscale x 64 x i1>
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 1 x i1> @llvm.vector.extract.nxv1i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)
+// CHECK-RV64-NEXT:    ret <vscale x 1 x i1> [[TMP1]]
+//
+vbool64_t test_vreinterpret_v_i64m1_b64(vint64m1_t src) {
+  return __riscv_th_vreinterpret_v_i64m1_b64(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_b64_i64m1
+// CHECK-RV64-SAME: (<vscale x 1 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv1i1(<vscale x 64 x i1> poison, <vscale x 1 x i1> [[SRC]], i64 0)
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 1 x i64>
+// CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP1]]
+//
+vint64m1_t test_vreinterpret_v_b64_i64m1(vbool64_t src) {
+  return __riscv_th_vreinterpret_v_b64_i64m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vreinterpret_v_i64m1_b32
+// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i64> [[SRC]] to <vscale x 64 x i1>
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)
+// CHECK-RV64-NEXT:    ret <vscale x 2 x i1> [[TMP1]]
+//
+vbool32_t test_vreinterpret_v_i64m1_b32(vint64m1_t src) {
+  return __riscv_th_vreinterpret_v_i64m1_b32(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_b32_i64m1
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv2i1(<vscale x 64 x i1> poison, <vscale x 2 x i1> [[SRC]], i64 0)
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 1 x i64>
+// CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP1]]
+//
+vint64m1_t test_vreinterpret_v_b32_i64m1(vbool32_t src) {
+  return __riscv_th_vreinterpret_v_b32_i64m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vreinterpret_v_i64m1_b16
+// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i64> [[SRC]] to <vscale x 64 x i1>
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 4 x i1> @llvm.vector.extract.nxv4i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i1> [[TMP1]]
+//
+vbool16_t test_vreinterpret_v_i64m1_b16(vint64m1_t src) {
+  return __riscv_th_vreinterpret_v_i64m1_b16(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_b16_i64m1
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv4i1(<vscale x 64 x i1> poison, <vscale x 4 x i1> [[SRC]], i64 0)
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 1 x i64>
+// CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP1]]
+//
+vint64m1_t test_vreinterpret_v_b16_i64m1(vbool16_t src) {
+  return __riscv_th_vreinterpret_v_b16_i64m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vreinterpret_v_i64m1_b8
+// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i64> [[SRC]] to <vscale x 64 x i1>
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 8 x i1> @llvm.vector.extract.nxv8i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i1> [[TMP1]]
+//
+vbool8_t test_vreinterpret_v_i64m1_b8(vint64m1_t src) {
+  return __riscv_th_vreinterpret_v_i64m1_b8(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_b8_i64m1
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv8i1(<vscale x 64 x i1> poison, <vscale x 8 x i1> [[SRC]], i64 0)
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 1 x i64>
+// CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP1]]
+//
+vint64m1_t test_vreinterpret_v_b8_i64m1(vbool8_t src) {
+  return __riscv_th_vreinterpret_v_b8_i64m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vreinterpret_v_u64m1_b64
+// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i64> [[SRC]] to <vscale x 64 x i1>
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 1 x i1> @llvm.vector.extract.nxv1i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)
+// CHECK-RV64-NEXT:    ret <vscale x 1 x i1> [[TMP1]]
+//
+vbool64_t test_vreinterpret_v_u64m1_b64(vuint64m1_t src) {
+  return __riscv_th_vreinterpret_v_u64m1_b64(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_b64_u64m1
+// CHECK-RV64-SAME: (<vscale x 1 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv1i1(<vscale x 64 x i1> poison, <vscale x 1 x i1> [[SRC]], i64 0)
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 1 x i64>
+// CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP1]]
+//
+vuint64m1_t test_vreinterpret_v_b64_u64m1(vbool64_t src) {
+  return __riscv_th_vreinterpret_v_b64_u64m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vreinterpret_v_u64m1_b32
+// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i64> [[SRC]] to <vscale x 64 x i1>
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)
+// CHECK-RV64-NEXT:    ret <vscale x 2 x i1> [[TMP1]]
+//
+vbool32_t test_vreinterpret_v_u64m1_b32(vuint64m1_t src) {
+  return __riscv_th_vreinterpret_v_u64m1_b32(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_b32_u64m1
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv2i1(<vscale x 64 x i1> poison, <vscale x 2 x i1> [[SRC]], i64 0)
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 1 x i64>
+// CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP1]]
+//
+vuint64m1_t test_vreinterpret_v_b32_u64m1(vbool32_t src) {
+  return __riscv_th_vreinterpret_v_b32_u64m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vreinterpret_v_u64m1_b16
+// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i64> [[SRC]] to <vscale x 64 x i1>
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 4 x i1> @llvm.vector.extract.nxv4i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i1> [[TMP1]]
+//
+vbool16_t test_vreinterpret_v_u64m1_b16(vuint64m1_t src) {
+  return __riscv_th_vreinterpret_v_u64m1_b16(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_b16_u64m1
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv4i1(<vscale x 64 x i1> poison, <vscale x 4 x i1> [[SRC]], i64 0)
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 1 x i64>
+// CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP1]]
+//
+vuint64m1_t test_vreinterpret_v_b16_u64m1(vbool16_t src) {
+  return __riscv_th_vreinterpret_v_b16_u64m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vreinterpret_v_u64m1_b8
+// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i64> [[SRC]] to <vscale x 64 x i1>
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 8 x i1> @llvm.vector.extract.nxv8i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i1> [[TMP1]]
+//
+vbool8_t test_vreinterpret_v_u64m1_b8(vuint64m1_t src) {
+  return __riscv_th_vreinterpret_v_u64m1_b8(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_b8_u64m1
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv8i1(<vscale x 64 x i1> poison, <vscale x 8 x i1> [[SRC]], i64 0)
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 1 x i64>
+// CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP1]]
+//
+vuint64m1_t test_vreinterpret_v_b8_u64m1(vbool8_t src) {
+  return __riscv_th_vreinterpret_v_b8_u64m1(src);
+}
diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/misc/thead/vreinterpret_iuf.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/misc/thead/vreinterpret_iuf.c
index cbe8c36f73a773..3271dc864db310 100644
--- a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/misc/thead/vreinterpret_iuf.c
+++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/misc/thead/vreinterpret_iuf.c
@@ -6,10 +6,6 @@
 
 #include <riscv_vector.h>
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_i8m1_u8m1
-// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[SRC]]
 // CHECK-IR-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_i8m1_u8m1
 // CHECK-IR-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0:[0-9]+]] {
 // CHECK-IR-NEXT:  entry:
@@ -19,10 +15,6 @@ vuint8m1_t test_vreinterpret_v_i8m1_u8m1(vint8m1_t src) {
   return __riscv_th_vreinterpret_v_i8m1_u8m1(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vreinterpret_v_i8m2_u8m2
-// CHECK-RV64-SAME: (<vscale x 16 x i8> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 16 x i8> [[SRC]]
 // CHECK-IR-LABEL: define dso_local <vscale x 16 x i8> @test_vreinterpret_v_i8m2_u8m2
 // CHECK-IR-SAME: (<vscale x 16 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -32,10 +24,6 @@ vuint8m2_t test_vreinterpret_v_i8m2_u8m2(vint8m2_t src) {
   return __riscv_th_vreinterpret_v_i8m2_u8m2(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vreinterpret_v_i8m4_u8m4
-// CHECK-RV64-SAME: (<vscale x 32 x i8> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 32 x i8> [[SRC]]
 // CHECK-IR-LABEL: define dso_local <vscale x 32 x i8> @test_vreinterpret_v_i8m4_u8m4
 // CHECK-IR-SAME: (<vscale x 32 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -45,10 +33,6 @@ vuint8m4_t test_vreinterpret_v_i8m4_u8m4(vint8m4_t src) {
   return __riscv_th_vreinterpret_v_i8m4_u8m4(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vreinterpret_v_i8m8_u8m8
-// CHECK-RV64-SAME: (<vscale x 64 x i8> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 64 x i8> [[SRC]]
 // CHECK-IR-LABEL: define dso_local <vscale x 64 x i8> @test_vreinterpret_v_i8m8_u8m8
 // CHECK-IR-SAME: (<vscale x 64 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -58,10 +42,6 @@ vuint8m8_t test_vreinterpret_v_i8m8_u8m8(vint8m8_t src) {
   return __riscv_th_vreinterpret_v_i8m8_u8m8(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_u8m1_i8m1
-// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[SRC]]
 // CHECK-IR-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_u8m1_i8m1
 // CHECK-IR-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -71,10 +51,6 @@ vint8m1_t test_vreinterpret_v_u8m1_i8m1(vuint8m1_t src) {
   return __riscv_th_vreinterpret_v_u8m1_i8m1(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vreinterpret_v_u8m2_i8m2
-// CHECK-RV64-SAME: (<vscale x 16 x i8> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 16 x i8> [[SRC]]
 // CHECK-IR-LABEL: define dso_local <vscale x 16 x i8> @test_vreinterpret_v_u8m2_i8m2
 // CHECK-IR-SAME: (<vscale x 16 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -84,10 +60,6 @@ vint8m2_t test_vreinterpret_v_u8m2_i8m2(vuint8m2_t src) {
   return __riscv_th_vreinterpret_v_u8m2_i8m2(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vreinterpret_v_u8m4_i8m4
-// CHECK-RV64-SAME: (<vscale x 32 x i8> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 32 x i8> [[SRC]]
 // CHECK-IR-LABEL: define dso_local <vscale x 32 x i8> @test_vreinterpret_v_u8m4_i8m4
 // CHECK-IR-SAME: (<vscale x 32 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -97,10 +69,6 @@ vint8m4_t test_vreinterpret_v_u8m4_i8m4(vuint8m4_t src) {
   return __riscv_th_vreinterpret_v_u8m4_i8m4(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vreinterpret_v_u8m8_i8m8
-// CHECK-RV64-SAME: (<vscale x 64 x i8> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 64 x i8> [[SRC]]
 // CHECK-IR-LABEL: define dso_local <vscale x 64 x i8> @test_vreinterpret_v_u8m8_i8m8
 // CHECK-IR-SAME: (<vscale x 64 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -110,11 +78,6 @@ vint8m8_t test_vreinterpret_v_u8m8_i8m8(vuint8m8_t src) {
   return __riscv_th_vreinterpret_v_u8m8_i8m8(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vreinterpret_v_i16m1_f16m1
-// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC]] to <vscale x 4 x half>
-// CHECK-RV64-NEXT:    ret <vscale x 4 x half> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 4 x half> @test_vreinterpret_v_i16m1_f16m1
 // CHECK-IR-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -125,11 +88,6 @@ vfloat16m1_t test_vreinterpret_v_i16m1_f16m1(vint16m1_t src) {
   return __riscv_th_vreinterpret_v_i16m1_f16m1(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vreinterpret_v_i16m2_f16m2
-// CHECK-RV64-SAME: (<vscale x 8 x i16> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i16> [[SRC]] to <vscale x 8 x half>
-// CHECK-RV64-NEXT:    ret <vscale x 8 x half> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 8 x half> @test_vreinterpret_v_i16m2_f16m2
 // CHECK-IR-SAME: (<vscale x 8 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -140,11 +98,6 @@ vfloat16m2_t test_vreinterpret_v_i16m2_f16m2(vint16m2_t src) {
   return __riscv_th_vreinterpret_v_i16m2_f16m2(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vreinterpret_v_i16m4_f16m4
-// CHECK-RV64-SAME: (<vscale x 16 x i16> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i16> [[SRC]] to <vscale x 16 x half>
-// CHECK-RV64-NEXT:    ret <vscale x 16 x half> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 16 x half> @test_vreinterpret_v_i16m4_f16m4
 // CHECK-IR-SAME: (<vscale x 16 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -155,11 +108,6 @@ vfloat16m4_t test_vreinterpret_v_i16m4_f16m4(vint16m4_t src) {
   return __riscv_th_vreinterpret_v_i16m4_f16m4(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vreinterpret_v_i16m8_f16m8
-// CHECK-RV64-SAME: (<vscale x 32 x i16> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x i16> [[SRC]] to <vscale x 32 x half>
-// CHECK-RV64-NEXT:    ret <vscale x 32 x half> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 32 x half> @test_vreinterpret_v_i16m8_f16m8
 // CHECK-IR-SAME: (<vscale x 32 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -170,11 +118,6 @@ vfloat16m8_t test_vreinterpret_v_i16m8_f16m8(vint16m8_t src) {
   return __riscv_th_vreinterpret_v_i16m8_f16m8(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vreinterpret_v_u16m1_f16m1
-// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC]] to <vscale x 4 x half>
-// CHECK-RV64-NEXT:    ret <vscale x 4 x half> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 4 x half> @test_vreinterpret_v_u16m1_f16m1
 // CHECK-IR-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -185,11 +128,6 @@ vfloat16m1_t test_vreinterpret_v_u16m1_f16m1(vuint16m1_t src) {
   return __riscv_th_vreinterpret_v_u16m1_f16m1(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vreinterpret_v_u16m2_f16m2
-// CHECK-RV64-SAME: (<vscale x 8 x i16> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i16> [[SRC]] to <vscale x 8 x half>
-// CHECK-RV64-NEXT:    ret <vscale x 8 x half> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 8 x half> @test_vreinterpret_v_u16m2_f16m2
 // CHECK-IR-SAME: (<vscale x 8 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -200,11 +138,6 @@ vfloat16m2_t test_vreinterpret_v_u16m2_f16m2(vuint16m2_t src) {
   return __riscv_th_vreinterpret_v_u16m2_f16m2(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vreinterpret_v_u16m4_f16m4
-// CHECK-RV64-SAME: (<vscale x 16 x i16> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i16> [[SRC]] to <vscale x 16 x half>
-// CHECK-RV64-NEXT:    ret <vscale x 16 x half> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 16 x half> @test_vreinterpret_v_u16m4_f16m4
 // CHECK-IR-SAME: (<vscale x 16 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -215,11 +148,6 @@ vfloat16m4_t test_vreinterpret_v_u16m4_f16m4(vuint16m4_t src) {
   return __riscv_th_vreinterpret_v_u16m4_f16m4(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vreinterpret_v_u16m8_f16m8
-// CHECK-RV64-SAME: (<vscale x 32 x i16> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x i16> [[SRC]] to <vscale x 32 x half>
-// CHECK-RV64-NEXT:    ret <vscale x 32 x half> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 32 x half> @test_vreinterpret_v_u16m8_f16m8
 // CHECK-IR-SAME: (<vscale x 32 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -230,10 +158,6 @@ vfloat16m8_t test_vreinterpret_v_u16m8_f16m8(vuint16m8_t src) {
   return __riscv_th_vreinterpret_v_u16m8_f16m8(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_i16m1_u16m1
-// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[SRC]]
 // CHECK-IR-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_i16m1_u16m1
 // CHECK-IR-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -243,10 +167,6 @@ vuint16m1_t test_vreinterpret_v_i16m1_u16m1(vint16m1_t src) {
   return __riscv_th_vreinterpret_v_i16m1_u16m1(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vreinterpret_v_i16m2_u16m2
-// CHECK-RV64-SAME: (<vscale x 8 x i16> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[SRC]]
 // CHECK-IR-LABEL: define dso_local <vscale x 8 x i16> @test_vreinterpret_v_i16m2_u16m2
 // CHECK-IR-SAME: (<vscale x 8 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -256,10 +176,6 @@ vuint16m2_t test_vreinterpret_v_i16m2_u16m2(vint16m2_t src) {
   return __riscv_th_vreinterpret_v_i16m2_u16m2(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vreinterpret_v_i16m4_u16m4
-// CHECK-RV64-SAME: (<vscale x 16 x i16> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[SRC]]
 // CHECK-IR-LABEL: define dso_local <vscale x 16 x i16> @test_vreinterpret_v_i16m4_u16m4
 // CHECK-IR-SAME: (<vscale x 16 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -269,10 +185,6 @@ vuint16m4_t test_vreinterpret_v_i16m4_u16m4(vint16m4_t src) {
   return __riscv_th_vreinterpret_v_i16m4_u16m4(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vreinterpret_v_i16m8_u16m8
-// CHECK-RV64-SAME: (<vscale x 32 x i16> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[SRC]]
 // CHECK-IR-LABEL: define dso_local <vscale x 32 x i16> @test_vreinterpret_v_i16m8_u16m8
 // CHECK-IR-SAME: (<vscale x 32 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -282,10 +194,6 @@ vuint16m8_t test_vreinterpret_v_i16m8_u16m8(vint16m8_t src) {
   return __riscv_th_vreinterpret_v_i16m8_u16m8(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_u16m1_i16m1
-// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[SRC]]
 // CHECK-IR-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_u16m1_i16m1
 // CHECK-IR-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -295,10 +203,6 @@ vint16m1_t test_vreinterpret_v_u16m1_i16m1(vuint16m1_t src) {
   return __riscv_th_vreinterpret_v_u16m1_i16m1(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vreinterpret_v_u16m2_i16m2
-// CHECK-RV64-SAME: (<vscale x 8 x i16> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[SRC]]
 // CHECK-IR-LABEL: define dso_local <vscale x 8 x i16> @test_vreinterpret_v_u16m2_i16m2
 // CHECK-IR-SAME: (<vscale x 8 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -308,10 +212,6 @@ vint16m2_t test_vreinterpret_v_u16m2_i16m2(vuint16m2_t src) {
   return __riscv_th_vreinterpret_v_u16m2_i16m2(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vreinterpret_v_u16m4_i16m4
-// CHECK-RV64-SAME: (<vscale x 16 x i16> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[SRC]]
 // CHECK-IR-LABEL: define dso_local <vscale x 16 x i16> @test_vreinterpret_v_u16m4_i16m4
 // CHECK-IR-SAME: (<vscale x 16 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -321,10 +221,6 @@ vint16m4_t test_vreinterpret_v_u16m4_i16m4(vuint16m4_t src) {
   return __riscv_th_vreinterpret_v_u16m4_i16m4(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vreinterpret_v_u16m8_i16m8
-// CHECK-RV64-SAME: (<vscale x 32 x i16> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[SRC]]
 // CHECK-IR-LABEL: define dso_local <vscale x 32 x i16> @test_vreinterpret_v_u16m8_i16m8
 // CHECK-IR-SAME: (<vscale x 32 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -334,11 +230,6 @@ vint16m8_t test_vreinterpret_v_u16m8_i16m8(vuint16m8_t src) {
   return __riscv_th_vreinterpret_v_u16m8_i16m8(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_f16m1_i16m1
-// CHECK-RV64-SAME: (<vscale x 4 x half> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x half> [[SRC]] to <vscale x 4 x i16>
-// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_f16m1_i16m1
 // CHECK-IR-SAME: (<vscale x 4 x half> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -349,11 +240,6 @@ vint16m1_t test_vreinterpret_v_f16m1_i16m1(vfloat16m1_t src) {
   return __riscv_th_vreinterpret_v_f16m1_i16m1(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vreinterpret_v_f16m2_i16m2
-// CHECK-RV64-SAME: (<vscale x 8 x half> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x half> [[SRC]] to <vscale x 8 x i16>
-// CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 8 x i16> @test_vreinterpret_v_f16m2_i16m2
 // CHECK-IR-SAME: (<vscale x 8 x half> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -364,11 +250,6 @@ vint16m2_t test_vreinterpret_v_f16m2_i16m2(vfloat16m2_t src) {
   return __riscv_th_vreinterpret_v_f16m2_i16m2(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vreinterpret_v_f16m4_i16m4
-// CHECK-RV64-SAME: (<vscale x 16 x half> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x half> [[SRC]] to <vscale x 16 x i16>
-// CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 16 x i16> @test_vreinterpret_v_f16m4_i16m4
 // CHECK-IR-SAME: (<vscale x 16 x half> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -379,11 +260,6 @@ vint16m4_t test_vreinterpret_v_f16m4_i16m4(vfloat16m4_t src) {
   return __riscv_th_vreinterpret_v_f16m4_i16m4(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vreinterpret_v_f16m8_i16m8
-// CHECK-RV64-SAME: (<vscale x 32 x half> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x half> [[SRC]] to <vscale x 32 x i16>
-// CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 32 x i16> @test_vreinterpret_v_f16m8_i16m8
 // CHECK-IR-SAME: (<vscale x 32 x half> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -394,11 +270,6 @@ vint16m8_t test_vreinterpret_v_f16m8_i16m8(vfloat16m8_t src) {
   return __riscv_th_vreinterpret_v_f16m8_i16m8(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_f16m1_u16m1
-// CHECK-RV64-SAME: (<vscale x 4 x half> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x half> [[SRC]] to <vscale x 4 x i16>
-// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_f16m1_u16m1
 // CHECK-IR-SAME: (<vscale x 4 x half> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -409,11 +280,6 @@ vuint16m1_t test_vreinterpret_v_f16m1_u16m1(vfloat16m1_t src) {
   return __riscv_th_vreinterpret_v_f16m1_u16m1(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vreinterpret_v_f16m2_u16m2
-// CHECK-RV64-SAME: (<vscale x 8 x half> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x half> [[SRC]] to <vscale x 8 x i16>
-// CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 8 x i16> @test_vreinterpret_v_f16m2_u16m2
 // CHECK-IR-SAME: (<vscale x 8 x half> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -424,11 +290,6 @@ vuint16m2_t test_vreinterpret_v_f16m2_u16m2(vfloat16m2_t src) {
   return __riscv_th_vreinterpret_v_f16m2_u16m2(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vreinterpret_v_f16m4_u16m4
-// CHECK-RV64-SAME: (<vscale x 16 x half> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x half> [[SRC]] to <vscale x 16 x i16>
-// CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 16 x i16> @test_vreinterpret_v_f16m4_u16m4
 // CHECK-IR-SAME: (<vscale x 16 x half> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -439,11 +300,6 @@ vuint16m4_t test_vreinterpret_v_f16m4_u16m4(vfloat16m4_t src) {
   return __riscv_th_vreinterpret_v_f16m4_u16m4(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vreinterpret_v_f16m8_u16m8
-// CHECK-RV64-SAME: (<vscale x 32 x half> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x half> [[SRC]] to <vscale x 32 x i16>
-// CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 32 x i16> @test_vreinterpret_v_f16m8_u16m8
 // CHECK-IR-SAME: (<vscale x 32 x half> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -454,11 +310,6 @@ vuint16m8_t test_vreinterpret_v_f16m8_u16m8(vfloat16m8_t src) {
   return __riscv_th_vreinterpret_v_f16m8_u16m8(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vreinterpret_v_i32m1_f32m1
-// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i32> [[SRC]] to <vscale x 2 x float>
-// CHECK-RV64-NEXT:    ret <vscale x 2 x float> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 2 x float> @test_vreinterpret_v_i32m1_f32m1
 // CHECK-IR-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -469,11 +320,6 @@ vfloat32m1_t test_vreinterpret_v_i32m1_f32m1(vint32m1_t src) {
   return __riscv_th_vreinterpret_v_i32m1_f32m1(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vreinterpret_v_i32m2_f32m2
-// CHECK-RV64-SAME: (<vscale x 4 x i32> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i32> [[SRC]] to <vscale x 4 x float>
-// CHECK-RV64-NEXT:    ret <vscale x 4 x float> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 4 x float> @test_vreinterpret_v_i32m2_f32m2
 // CHECK-IR-SAME: (<vscale x 4 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -484,11 +330,6 @@ vfloat32m2_t test_vreinterpret_v_i32m2_f32m2(vint32m2_t src) {
   return __riscv_th_vreinterpret_v_i32m2_f32m2(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vreinterpret_v_i32m4_f32m4
-// CHECK-RV64-SAME: (<vscale x 8 x i32> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i32> [[SRC]] to <vscale x 8 x float>
-// CHECK-RV64-NEXT:    ret <vscale x 8 x float> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 8 x float> @test_vreinterpret_v_i32m4_f32m4
 // CHECK-IR-SAME: (<vscale x 8 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -499,11 +340,6 @@ vfloat32m4_t test_vreinterpret_v_i32m4_f32m4(vint32m4_t src) {
   return __riscv_th_vreinterpret_v_i32m4_f32m4(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vreinterpret_v_i32m8_f32m8
-// CHECK-RV64-SAME: (<vscale x 16 x i32> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i32> [[SRC]] to <vscale x 16 x float>
-// CHECK-RV64-NEXT:    ret <vscale x 16 x float> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 16 x float> @test_vreinterpret_v_i32m8_f32m8
 // CHECK-IR-SAME: (<vscale x 16 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -514,11 +350,6 @@ vfloat32m8_t test_vreinterpret_v_i32m8_f32m8(vint32m8_t src) {
   return __riscv_th_vreinterpret_v_i32m8_f32m8(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vreinterpret_v_u32m1_f32m1
-// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i32> [[SRC]] to <vscale x 2 x float>
-// CHECK-RV64-NEXT:    ret <vscale x 2 x float> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 2 x float> @test_vreinterpret_v_u32m1_f32m1
 // CHECK-IR-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -529,11 +360,6 @@ vfloat32m1_t test_vreinterpret_v_u32m1_f32m1(vuint32m1_t src) {
   return __riscv_th_vreinterpret_v_u32m1_f32m1(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vreinterpret_v_u32m2_f32m2
-// CHECK-RV64-SAME: (<vscale x 4 x i32> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i32> [[SRC]] to <vscale x 4 x float>
-// CHECK-RV64-NEXT:    ret <vscale x 4 x float> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 4 x float> @test_vreinterpret_v_u32m2_f32m2
 // CHECK-IR-SAME: (<vscale x 4 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -544,11 +370,6 @@ vfloat32m2_t test_vreinterpret_v_u32m2_f32m2(vuint32m2_t src) {
   return __riscv_th_vreinterpret_v_u32m2_f32m2(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vreinterpret_v_u32m4_f32m4
-// CHECK-RV64-SAME: (<vscale x 8 x i32> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i32> [[SRC]] to <vscale x 8 x float>
-// CHECK-RV64-NEXT:    ret <vscale x 8 x float> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 8 x float> @test_vreinterpret_v_u32m4_f32m4
 // CHECK-IR-SAME: (<vscale x 8 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -559,11 +380,6 @@ vfloat32m4_t test_vreinterpret_v_u32m4_f32m4(vuint32m4_t src) {
   return __riscv_th_vreinterpret_v_u32m4_f32m4(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vreinterpret_v_u32m8_f32m8
-// CHECK-RV64-SAME: (<vscale x 16 x i32> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i32> [[SRC]] to <vscale x 16 x float>
-// CHECK-RV64-NEXT:    ret <vscale x 16 x float> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 16 x float> @test_vreinterpret_v_u32m8_f32m8
 // CHECK-IR-SAME: (<vscale x 16 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -574,10 +390,6 @@ vfloat32m8_t test_vreinterpret_v_u32m8_f32m8(vuint32m8_t src) {
   return __riscv_th_vreinterpret_v_u32m8_f32m8(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_i32m1_u32m1
-// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[SRC]]
 // CHECK-IR-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_i32m1_u32m1
 // CHECK-IR-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -587,10 +399,6 @@ vuint32m1_t test_vreinterpret_v_i32m1_u32m1(vint32m1_t src) {
   return __riscv_th_vreinterpret_v_i32m1_u32m1(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vreinterpret_v_i32m2_u32m2
-// CHECK-RV64-SAME: (<vscale x 4 x i32> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[SRC]]
 // CHECK-IR-LABEL: define dso_local <vscale x 4 x i32> @test_vreinterpret_v_i32m2_u32m2
 // CHECK-IR-SAME: (<vscale x 4 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -600,10 +408,6 @@ vuint32m2_t test_vreinterpret_v_i32m2_u32m2(vint32m2_t src) {
   return __riscv_th_vreinterpret_v_i32m2_u32m2(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vreinterpret_v_i32m4_u32m4
-// CHECK-RV64-SAME: (<vscale x 8 x i32> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[SRC]]
 // CHECK-IR-LABEL: define dso_local <vscale x 8 x i32> @test_vreinterpret_v_i32m4_u32m4
 // CHECK-IR-SAME: (<vscale x 8 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -613,10 +417,6 @@ vuint32m4_t test_vreinterpret_v_i32m4_u32m4(vint32m4_t src) {
   return __riscv_th_vreinterpret_v_i32m4_u32m4(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vreinterpret_v_i32m8_u32m8
-// CHECK-RV64-SAME: (<vscale x 16 x i32> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[SRC]]
 // CHECK-IR-LABEL: define dso_local <vscale x 16 x i32> @test_vreinterpret_v_i32m8_u32m8
 // CHECK-IR-SAME: (<vscale x 16 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -626,10 +426,6 @@ vuint32m8_t test_vreinterpret_v_i32m8_u32m8(vint32m8_t src) {
   return __riscv_th_vreinterpret_v_i32m8_u32m8(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_u32m1_i32m1
-// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[SRC]]
 // CHECK-IR-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_u32m1_i32m1
 // CHECK-IR-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -639,10 +435,6 @@ vint32m1_t test_vreinterpret_v_u32m1_i32m1(vuint32m1_t src) {
   return __riscv_th_vreinterpret_v_u32m1_i32m1(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vreinterpret_v_u32m2_i32m2
-// CHECK-RV64-SAME: (<vscale x 4 x i32> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[SRC]]
 // CHECK-IR-LABEL: define dso_local <vscale x 4 x i32> @test_vreinterpret_v_u32m2_i32m2
 // CHECK-IR-SAME: (<vscale x 4 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -652,10 +444,6 @@ vint32m2_t test_vreinterpret_v_u32m2_i32m2(vuint32m2_t src) {
   return __riscv_th_vreinterpret_v_u32m2_i32m2(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vreinterpret_v_u32m4_i32m4
-// CHECK-RV64-SAME: (<vscale x 8 x i32> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[SRC]]
 // CHECK-IR-LABEL: define dso_local <vscale x 8 x i32> @test_vreinterpret_v_u32m4_i32m4
 // CHECK-IR-SAME: (<vscale x 8 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -665,10 +453,6 @@ vint32m4_t test_vreinterpret_v_u32m4_i32m4(vuint32m4_t src) {
   return __riscv_th_vreinterpret_v_u32m4_i32m4(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vreinterpret_v_u32m8_i32m8
-// CHECK-RV64-SAME: (<vscale x 16 x i32> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[SRC]]
 // CHECK-IR-LABEL: define dso_local <vscale x 16 x i32> @test_vreinterpret_v_u32m8_i32m8
 // CHECK-IR-SAME: (<vscale x 16 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -678,11 +462,6 @@ vint32m8_t test_vreinterpret_v_u32m8_i32m8(vuint32m8_t src) {
   return __riscv_th_vreinterpret_v_u32m8_i32m8(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_f32m1_i32m1
-// CHECK-RV64-SAME: (<vscale x 2 x float> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x float> [[SRC]] to <vscale x 2 x i32>
-// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_f32m1_i32m1
 // CHECK-IR-SAME: (<vscale x 2 x float> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -693,11 +472,6 @@ vint32m1_t test_vreinterpret_v_f32m1_i32m1(vfloat32m1_t src) {
   return __riscv_th_vreinterpret_v_f32m1_i32m1(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vreinterpret_v_f32m2_i32m2
-// CHECK-RV64-SAME: (<vscale x 4 x float> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x float> [[SRC]] to <vscale x 4 x i32>
-// CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 4 x i32> @test_vreinterpret_v_f32m2_i32m2
 // CHECK-IR-SAME: (<vscale x 4 x float> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -708,11 +482,6 @@ vint32m2_t test_vreinterpret_v_f32m2_i32m2(vfloat32m2_t src) {
   return __riscv_th_vreinterpret_v_f32m2_i32m2(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vreinterpret_v_f32m4_i32m4
-// CHECK-RV64-SAME: (<vscale x 8 x float> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x float> [[SRC]] to <vscale x 8 x i32>
-// CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 8 x i32> @test_vreinterpret_v_f32m4_i32m4
 // CHECK-IR-SAME: (<vscale x 8 x float> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -723,11 +492,6 @@ vint32m4_t test_vreinterpret_v_f32m4_i32m4(vfloat32m4_t src) {
   return __riscv_th_vreinterpret_v_f32m4_i32m4(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vreinterpret_v_f32m8_i32m8
-// CHECK-RV64-SAME: (<vscale x 16 x float> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x float> [[SRC]] to <vscale x 16 x i32>
-// CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 16 x i32> @test_vreinterpret_v_f32m8_i32m8
 // CHECK-IR-SAME: (<vscale x 16 x float> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -738,11 +502,6 @@ vint32m8_t test_vreinterpret_v_f32m8_i32m8(vfloat32m8_t src) {
   return __riscv_th_vreinterpret_v_f32m8_i32m8(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_f32m1_u32m1
-// CHECK-RV64-SAME: (<vscale x 2 x float> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x float> [[SRC]] to <vscale x 2 x i32>
-// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_f32m1_u32m1
 // CHECK-IR-SAME: (<vscale x 2 x float> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -753,11 +512,6 @@ vuint32m1_t test_vreinterpret_v_f32m1_u32m1(vfloat32m1_t src) {
   return __riscv_th_vreinterpret_v_f32m1_u32m1(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vreinterpret_v_f32m2_u32m2
-// CHECK-RV64-SAME: (<vscale x 4 x float> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x float> [[SRC]] to <vscale x 4 x i32>
-// CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 4 x i32> @test_vreinterpret_v_f32m2_u32m2
 // CHECK-IR-SAME: (<vscale x 4 x float> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -768,11 +522,6 @@ vuint32m2_t test_vreinterpret_v_f32m2_u32m2(vfloat32m2_t src) {
   return __riscv_th_vreinterpret_v_f32m2_u32m2(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vreinterpret_v_f32m4_u32m4
-// CHECK-RV64-SAME: (<vscale x 8 x float> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x float> [[SRC]] to <vscale x 8 x i32>
-// CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 8 x i32> @test_vreinterpret_v_f32m4_u32m4
 // CHECK-IR-SAME: (<vscale x 8 x float> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -783,11 +532,6 @@ vuint32m4_t test_vreinterpret_v_f32m4_u32m4(vfloat32m4_t src) {
   return __riscv_th_vreinterpret_v_f32m4_u32m4(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vreinterpret_v_f32m8_u32m8
-// CHECK-RV64-SAME: (<vscale x 16 x float> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x float> [[SRC]] to <vscale x 16 x i32>
-// CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 16 x i32> @test_vreinterpret_v_f32m8_u32m8
 // CHECK-IR-SAME: (<vscale x 16 x float> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -798,11 +542,6 @@ vuint32m8_t test_vreinterpret_v_f32m8_u32m8(vfloat32m8_t src) {
   return __riscv_th_vreinterpret_v_f32m8_u32m8(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vreinterpret_v_i64m1_f64m1
-// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i64> [[SRC]] to <vscale x 1 x double>
-// CHECK-RV64-NEXT:    ret <vscale x 1 x double> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 1 x double> @test_vreinterpret_v_i64m1_f64m1
 // CHECK-IR-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -813,11 +552,6 @@ vfloat64m1_t test_vreinterpret_v_i64m1_f64m1(vint64m1_t src) {
   return __riscv_th_vreinterpret_v_i64m1_f64m1(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vreinterpret_v_i64m2_f64m2
-// CHECK-RV64-SAME: (<vscale x 2 x i64> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i64> [[SRC]] to <vscale x 2 x double>
-// CHECK-RV64-NEXT:    ret <vscale x 2 x double> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 2 x double> @test_vreinterpret_v_i64m2_f64m2
 // CHECK-IR-SAME: (<vscale x 2 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -828,11 +562,6 @@ vfloat64m2_t test_vreinterpret_v_i64m2_f64m2(vint64m2_t src) {
   return __riscv_th_vreinterpret_v_i64m2_f64m2(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vreinterpret_v_i64m4_f64m4
-// CHECK-RV64-SAME: (<vscale x 4 x i64> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i64> [[SRC]] to <vscale x 4 x double>
-// CHECK-RV64-NEXT:    ret <vscale x 4 x double> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 4 x double> @test_vreinterpret_v_i64m4_f64m4
 // CHECK-IR-SAME: (<vscale x 4 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -843,11 +572,6 @@ vfloat64m4_t test_vreinterpret_v_i64m4_f64m4(vint64m4_t src) {
   return __riscv_th_vreinterpret_v_i64m4_f64m4(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vreinterpret_v_i64m8_f64m8
-// CHECK-RV64-SAME: (<vscale x 8 x i64> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i64> [[SRC]] to <vscale x 8 x double>
-// CHECK-RV64-NEXT:    ret <vscale x 8 x double> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 8 x double> @test_vreinterpret_v_i64m8_f64m8
 // CHECK-IR-SAME: (<vscale x 8 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -858,11 +582,6 @@ vfloat64m8_t test_vreinterpret_v_i64m8_f64m8(vint64m8_t src) {
   return __riscv_th_vreinterpret_v_i64m8_f64m8(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vreinterpret_v_u64m1_f64m1
-// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i64> [[SRC]] to <vscale x 1 x double>
-// CHECK-RV64-NEXT:    ret <vscale x 1 x double> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 1 x double> @test_vreinterpret_v_u64m1_f64m1
 // CHECK-IR-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -873,11 +592,6 @@ vfloat64m1_t test_vreinterpret_v_u64m1_f64m1(vuint64m1_t src) {
   return __riscv_th_vreinterpret_v_u64m1_f64m1(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vreinterpret_v_u64m2_f64m2
-// CHECK-RV64-SAME: (<vscale x 2 x i64> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i64> [[SRC]] to <vscale x 2 x double>
-// CHECK-RV64-NEXT:    ret <vscale x 2 x double> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 2 x double> @test_vreinterpret_v_u64m2_f64m2
 // CHECK-IR-SAME: (<vscale x 2 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -888,11 +602,6 @@ vfloat64m2_t test_vreinterpret_v_u64m2_f64m2(vuint64m2_t src) {
   return __riscv_th_vreinterpret_v_u64m2_f64m2(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vreinterpret_v_u64m4_f64m4
-// CHECK-RV64-SAME: (<vscale x 4 x i64> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i64> [[SRC]] to <vscale x 4 x double>
-// CHECK-RV64-NEXT:    ret <vscale x 4 x double> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 4 x double> @test_vreinterpret_v_u64m4_f64m4
 // CHECK-IR-SAME: (<vscale x 4 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -903,11 +612,6 @@ vfloat64m4_t test_vreinterpret_v_u64m4_f64m4(vuint64m4_t src) {
   return __riscv_th_vreinterpret_v_u64m4_f64m4(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vreinterpret_v_u64m8_f64m8
-// CHECK-RV64-SAME: (<vscale x 8 x i64> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i64> [[SRC]] to <vscale x 8 x double>
-// CHECK-RV64-NEXT:    ret <vscale x 8 x double> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 8 x double> @test_vreinterpret_v_u64m8_f64m8
 // CHECK-IR-SAME: (<vscale x 8 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -918,10 +622,6 @@ vfloat64m8_t test_vreinterpret_v_u64m8_f64m8(vuint64m8_t src) {
   return __riscv_th_vreinterpret_v_u64m8_f64m8(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_i64m1_u64m1
-// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[SRC]]
 // CHECK-IR-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_i64m1_u64m1
 // CHECK-IR-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -931,10 +631,6 @@ vuint64m1_t test_vreinterpret_v_i64m1_u64m1(vint64m1_t src) {
   return __riscv_th_vreinterpret_v_i64m1_u64m1(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vreinterpret_v_i64m2_u64m2
-// CHECK-RV64-SAME: (<vscale x 2 x i64> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[SRC]]
 // CHECK-IR-LABEL: define dso_local <vscale x 2 x i64> @test_vreinterpret_v_i64m2_u64m2
 // CHECK-IR-SAME: (<vscale x 2 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -944,10 +640,6 @@ vuint64m2_t test_vreinterpret_v_i64m2_u64m2(vint64m2_t src) {
   return __riscv_th_vreinterpret_v_i64m2_u64m2(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vreinterpret_v_i64m4_u64m4
-// CHECK-RV64-SAME: (<vscale x 4 x i64> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[SRC]]
 // CHECK-IR-LABEL: define dso_local <vscale x 4 x i64> @test_vreinterpret_v_i64m4_u64m4
 // CHECK-IR-SAME: (<vscale x 4 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -957,10 +649,6 @@ vuint64m4_t test_vreinterpret_v_i64m4_u64m4(vint64m4_t src) {
   return __riscv_th_vreinterpret_v_i64m4_u64m4(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vreinterpret_v_i64m8_u64m8
-// CHECK-RV64-SAME: (<vscale x 8 x i64> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[SRC]]
 // CHECK-IR-LABEL: define dso_local <vscale x 8 x i64> @test_vreinterpret_v_i64m8_u64m8
 // CHECK-IR-SAME: (<vscale x 8 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -970,10 +658,6 @@ vuint64m8_t test_vreinterpret_v_i64m8_u64m8(vint64m8_t src) {
   return __riscv_th_vreinterpret_v_i64m8_u64m8(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_u64m1_i64m1
-// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[SRC]]
 // CHECK-IR-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_u64m1_i64m1
 // CHECK-IR-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -983,10 +667,6 @@ vint64m1_t test_vreinterpret_v_u64m1_i64m1(vuint64m1_t src) {
   return __riscv_th_vreinterpret_v_u64m1_i64m1(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vreinterpret_v_u64m2_i64m2
-// CHECK-RV64-SAME: (<vscale x 2 x i64> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[SRC]]
 // CHECK-IR-LABEL: define dso_local <vscale x 2 x i64> @test_vreinterpret_v_u64m2_i64m2
 // CHECK-IR-SAME: (<vscale x 2 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -996,10 +676,6 @@ vint64m2_t test_vreinterpret_v_u64m2_i64m2(vuint64m2_t src) {
   return __riscv_th_vreinterpret_v_u64m2_i64m2(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vreinterpret_v_u64m4_i64m4
-// CHECK-RV64-SAME: (<vscale x 4 x i64> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[SRC]]
 // CHECK-IR-LABEL: define dso_local <vscale x 4 x i64> @test_vreinterpret_v_u64m4_i64m4
 // CHECK-IR-SAME: (<vscale x 4 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -1009,10 +685,6 @@ vint64m4_t test_vreinterpret_v_u64m4_i64m4(vuint64m4_t src) {
   return __riscv_th_vreinterpret_v_u64m4_i64m4(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vreinterpret_v_u64m8_i64m8
-// CHECK-RV64-SAME: (<vscale x 8 x i64> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[SRC]]
 // CHECK-IR-LABEL: define dso_local <vscale x 8 x i64> @test_vreinterpret_v_u64m8_i64m8
 // CHECK-IR-SAME: (<vscale x 8 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -1022,11 +694,6 @@ vint64m8_t test_vreinterpret_v_u64m8_i64m8(vuint64m8_t src) {
   return __riscv_th_vreinterpret_v_u64m8_i64m8(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_f64m1_i64m1
-// CHECK-RV64-SAME: (<vscale x 1 x double> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x double> [[SRC]] to <vscale x 1 x i64>
-// CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_f64m1_i64m1
 // CHECK-IR-SAME: (<vscale x 1 x double> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -1037,11 +704,6 @@ vint64m1_t test_vreinterpret_v_f64m1_i64m1(vfloat64m1_t src) {
   return __riscv_th_vreinterpret_v_f64m1_i64m1(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vreinterpret_v_f64m2_i64m2
-// CHECK-RV64-SAME: (<vscale x 2 x double> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x double> [[SRC]] to <vscale x 2 x i64>
-// CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 2 x i64> @test_vreinterpret_v_f64m2_i64m2
 // CHECK-IR-SAME: (<vscale x 2 x double> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -1052,11 +714,6 @@ vint64m2_t test_vreinterpret_v_f64m2_i64m2(vfloat64m2_t src) {
   return __riscv_th_vreinterpret_v_f64m2_i64m2(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vreinterpret_v_f64m4_i64m4
-// CHECK-RV64-SAME: (<vscale x 4 x double> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x double> [[SRC]] to <vscale x 4 x i64>
-// CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 4 x i64> @test_vreinterpret_v_f64m4_i64m4
 // CHECK-IR-SAME: (<vscale x 4 x double> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -1067,11 +724,6 @@ vint64m4_t test_vreinterpret_v_f64m4_i64m4(vfloat64m4_t src) {
   return __riscv_th_vreinterpret_v_f64m4_i64m4(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vreinterpret_v_f64m8_i64m8
-// CHECK-RV64-SAME: (<vscale x 8 x double> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x double> [[SRC]] to <vscale x 8 x i64>
-// CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 8 x i64> @test_vreinterpret_v_f64m8_i64m8
 // CHECK-IR-SAME: (<vscale x 8 x double> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -1082,11 +734,6 @@ vint64m8_t test_vreinterpret_v_f64m8_i64m8(vfloat64m8_t src) {
   return __riscv_th_vreinterpret_v_f64m8_i64m8(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_f64m1_u64m1
-// CHECK-RV64-SAME: (<vscale x 1 x double> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x double> [[SRC]] to <vscale x 1 x i64>
-// CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_f64m1_u64m1
 // CHECK-IR-SAME: (<vscale x 1 x double> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -1097,11 +744,6 @@ vuint64m1_t test_vreinterpret_v_f64m1_u64m1(vfloat64m1_t src) {
   return __riscv_th_vreinterpret_v_f64m1_u64m1(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vreinterpret_v_f64m2_u64m2
-// CHECK-RV64-SAME: (<vscale x 2 x double> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x double> [[SRC]] to <vscale x 2 x i64>
-// CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 2 x i64> @test_vreinterpret_v_f64m2_u64m2
 // CHECK-IR-SAME: (<vscale x 2 x double> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -1112,11 +754,6 @@ vuint64m2_t test_vreinterpret_v_f64m2_u64m2(vfloat64m2_t src) {
   return __riscv_th_vreinterpret_v_f64m2_u64m2(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vreinterpret_v_f64m4_u64m4
-// CHECK-RV64-SAME: (<vscale x 4 x double> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x double> [[SRC]] to <vscale x 4 x i64>
-// CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 4 x i64> @test_vreinterpret_v_f64m4_u64m4
 // CHECK-IR-SAME: (<vscale x 4 x double> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -1127,11 +764,6 @@ vuint64m4_t test_vreinterpret_v_f64m4_u64m4(vfloat64m4_t src) {
   return __riscv_th_vreinterpret_v_f64m4_u64m4(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vreinterpret_v_f64m8_u64m8
-// CHECK-RV64-SAME: (<vscale x 8 x double> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x double> [[SRC]] to <vscale x 8 x i64>
-// CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 8 x i64> @test_vreinterpret_v_f64m8_u64m8
 // CHECK-IR-SAME: (<vscale x 8 x double> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/misc/thead/vreinterpret_sew.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/misc/thead/vreinterpret_sew.c
new file mode 100644
index 00000000000000..ff11c6a79c9da8
--- /dev/null
+++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/misc/thead/vreinterpret_sew.c
@@ -0,0 +1,967 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
+// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \
+// RUN:   -disable-O0-optnone -emit-llvm %s -o - | \
+// RUN:   opt -S -passes=mem2reg | \
+// RUN:   FileCheck --check-prefix=CHECK-IR %s
+
+#include <riscv_vector.h>
+
+// CHECK-IR-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_i8m1_i16m1
+// CHECK-IR-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i8> [[SRC]] to <vscale x 4 x i16>
+// CHECK-IR-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
+//
+vint16m1_t test_vreinterpret_v_i8m1_i16m1(vint8m1_t src) {
+  return __riscv_th_vreinterpret_v_i8m1_i16m1(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 8 x i16> @test_vreinterpret_v_i8m2_i16m2
+// CHECK-IR-SAME: (<vscale x 16 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i8> [[SRC]] to <vscale x 8 x i16>
+// CHECK-IR-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
+//
+vint16m2_t test_vreinterpret_v_i8m2_i16m2(vint8m2_t src) {
+  return __riscv_th_vreinterpret_v_i8m2_i16m2(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 16 x i16> @test_vreinterpret_v_i8m4_i16m4
+// CHECK-IR-SAME: (<vscale x 32 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x i8> [[SRC]] to <vscale x 16 x i16>
+// CHECK-IR-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
+//
+vint16m4_t test_vreinterpret_v_i8m4_i16m4(vint8m4_t src) {
+  return __riscv_th_vreinterpret_v_i8m4_i16m4(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 32 x i16> @test_vreinterpret_v_i8m8_i16m8
+// CHECK-IR-SAME: (<vscale x 64 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 64 x i8> [[SRC]] to <vscale x 32 x i16>
+// CHECK-IR-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
+//
+vint16m8_t test_vreinterpret_v_i8m8_i16m8(vint8m8_t src) {
+  return __riscv_th_vreinterpret_v_i8m8_i16m8(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_u8m1_u16m1
+// CHECK-IR-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i8> [[SRC]] to <vscale x 4 x i16>
+// CHECK-IR-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
+//
+vuint16m1_t test_vreinterpret_v_u8m1_u16m1(vuint8m1_t src) {
+  return __riscv_th_vreinterpret_v_u8m1_u16m1(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 8 x i16> @test_vreinterpret_v_u8m2_u16m2
+// CHECK-IR-SAME: (<vscale x 16 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i8> [[SRC]] to <vscale x 8 x i16>
+// CHECK-IR-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
+//
+vuint16m2_t test_vreinterpret_v_u8m2_u16m2(vuint8m2_t src) {
+  return __riscv_th_vreinterpret_v_u8m2_u16m2(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 16 x i16> @test_vreinterpret_v_u8m4_u16m4
+// CHECK-IR-SAME: (<vscale x 32 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x i8> [[SRC]] to <vscale x 16 x i16>
+// CHECK-IR-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
+//
+vuint16m4_t test_vreinterpret_v_u8m4_u16m4(vuint8m4_t src) {
+  return __riscv_th_vreinterpret_v_u8m4_u16m4(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 32 x i16> @test_vreinterpret_v_u8m8_u16m8
+// CHECK-IR-SAME: (<vscale x 64 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 64 x i8> [[SRC]] to <vscale x 32 x i16>
+// CHECK-IR-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
+//
+vuint16m8_t test_vreinterpret_v_u8m8_u16m8(vuint8m8_t src) {
+  return __riscv_th_vreinterpret_v_u8m8_u16m8(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_i8m1_i32m1
+// CHECK-IR-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i8> [[SRC]] to <vscale x 2 x i32>
+// CHECK-IR-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+vint32m1_t test_vreinterpret_v_i8m1_i32m1(vint8m1_t src) {
+  return __riscv_th_vreinterpret_v_i8m1_i32m1(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 4 x i32> @test_vreinterpret_v_i8m2_i32m2
+// CHECK-IR-SAME: (<vscale x 16 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i8> [[SRC]] to <vscale x 4 x i32>
+// CHECK-IR-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
+//
+vint32m2_t test_vreinterpret_v_i8m2_i32m2(vint8m2_t src) {
+  return __riscv_th_vreinterpret_v_i8m2_i32m2(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 8 x i32> @test_vreinterpret_v_i8m4_i32m4
+// CHECK-IR-SAME: (<vscale x 32 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x i8> [[SRC]] to <vscale x 8 x i32>
+// CHECK-IR-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
+//
+vint32m4_t test_vreinterpret_v_i8m4_i32m4(vint8m4_t src) {
+  return __riscv_th_vreinterpret_v_i8m4_i32m4(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 16 x i32> @test_vreinterpret_v_i8m8_i32m8
+// CHECK-IR-SAME: (<vscale x 64 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 64 x i8> [[SRC]] to <vscale x 16 x i32>
+// CHECK-IR-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
+//
+vint32m8_t test_vreinterpret_v_i8m8_i32m8(vint8m8_t src) {
+  return __riscv_th_vreinterpret_v_i8m8_i32m8(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_u8m1_u32m1
+// CHECK-IR-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i8> [[SRC]] to <vscale x 2 x i32>
+// CHECK-IR-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+vuint32m1_t test_vreinterpret_v_u8m1_u32m1(vuint8m1_t src) {
+  return __riscv_th_vreinterpret_v_u8m1_u32m1(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 4 x i32> @test_vreinterpret_v_u8m2_u32m2
+// CHECK-IR-SAME: (<vscale x 16 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i8> [[SRC]] to <vscale x 4 x i32>
+// CHECK-IR-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
+//
+vuint32m2_t test_vreinterpret_v_u8m2_u32m2(vuint8m2_t src) {
+  return __riscv_th_vreinterpret_v_u8m2_u32m2(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 8 x i32> @test_vreinterpret_v_u8m4_u32m4
+// CHECK-IR-SAME: (<vscale x 32 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x i8> [[SRC]] to <vscale x 8 x i32>
+// CHECK-IR-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
+//
+vuint32m4_t test_vreinterpret_v_u8m4_u32m4(vuint8m4_t src) {
+  return __riscv_th_vreinterpret_v_u8m4_u32m4(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 16 x i32> @test_vreinterpret_v_u8m8_u32m8
+// CHECK-IR-SAME: (<vscale x 64 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 64 x i8> [[SRC]] to <vscale x 16 x i32>
+// CHECK-IR-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
+//
+vuint32m8_t test_vreinterpret_v_u8m8_u32m8(vuint8m8_t src) {
+  return __riscv_th_vreinterpret_v_u8m8_u32m8(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_i8m1_i64m1
+// CHECK-IR-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i8> [[SRC]] to <vscale x 1 x i64>
+// CHECK-IR-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
+//
+vint64m1_t test_vreinterpret_v_i8m1_i64m1(vint8m1_t src) {
+  return __riscv_th_vreinterpret_v_i8m1_i64m1(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 2 x i64> @test_vreinterpret_v_i8m2_i64m2
+// CHECK-IR-SAME: (<vscale x 16 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i8> [[SRC]] to <vscale x 2 x i64>
+// CHECK-IR-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
+//
+vint64m2_t test_vreinterpret_v_i8m2_i64m2(vint8m2_t src) {
+  return __riscv_th_vreinterpret_v_i8m2_i64m2(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 4 x i64> @test_vreinterpret_v_i8m4_i64m4
+// CHECK-IR-SAME: (<vscale x 32 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x i8> [[SRC]] to <vscale x 4 x i64>
+// CHECK-IR-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
+//
+vint64m4_t test_vreinterpret_v_i8m4_i64m4(vint8m4_t src) {
+  return __riscv_th_vreinterpret_v_i8m4_i64m4(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 8 x i64> @test_vreinterpret_v_i8m8_i64m8
+// CHECK-IR-SAME: (<vscale x 64 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 64 x i8> [[SRC]] to <vscale x 8 x i64>
+// CHECK-IR-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
+//
+vint64m8_t test_vreinterpret_v_i8m8_i64m8(vint8m8_t src) {
+  return __riscv_th_vreinterpret_v_i8m8_i64m8(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_u8m1_u64m1
+// CHECK-IR-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i8> [[SRC]] to <vscale x 1 x i64>
+// CHECK-IR-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
+//
+vuint64m1_t test_vreinterpret_v_u8m1_u64m1(vuint8m1_t src) {
+  return __riscv_th_vreinterpret_v_u8m1_u64m1(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 2 x i64> @test_vreinterpret_v_u8m2_u64m2
+// CHECK-IR-SAME: (<vscale x 16 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i8> [[SRC]] to <vscale x 2 x i64>
+// CHECK-IR-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
+//
+vuint64m2_t test_vreinterpret_v_u8m2_u64m2(vuint8m2_t src) {
+  return __riscv_th_vreinterpret_v_u8m2_u64m2(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 4 x i64> @test_vreinterpret_v_u8m4_u64m4
+// CHECK-IR-SAME: (<vscale x 32 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x i8> [[SRC]] to <vscale x 4 x i64>
+// CHECK-IR-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
+//
+vuint64m4_t test_vreinterpret_v_u8m4_u64m4(vuint8m4_t src) {
+  return __riscv_th_vreinterpret_v_u8m4_u64m4(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 8 x i64> @test_vreinterpret_v_u8m8_u64m8
+// CHECK-IR-SAME: (<vscale x 64 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 64 x i8> [[SRC]] to <vscale x 8 x i64>
+// CHECK-IR-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
+//
+vuint64m8_t test_vreinterpret_v_u8m8_u64m8(vuint8m8_t src) {
+  return __riscv_th_vreinterpret_v_u8m8_u64m8(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_i16m1_i8m1
+// CHECK-IR-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC]] to <vscale x 8 x i8>
+// CHECK-IR-NEXT:    ret <vscale x 8 x i8> [[TMP0]]
+//
+vint8m1_t test_vreinterpret_v_i16m1_i8m1(vint16m1_t src) {
+  return __riscv_th_vreinterpret_v_i16m1_i8m1(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 16 x i8> @test_vreinterpret_v_i16m2_i8m2
+// CHECK-IR-SAME: (<vscale x 8 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i16> [[SRC]] to <vscale x 16 x i8>
+// CHECK-IR-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
+//
+vint8m2_t test_vreinterpret_v_i16m2_i8m2(vint16m2_t src) {
+  return __riscv_th_vreinterpret_v_i16m2_i8m2(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 32 x i8> @test_vreinterpret_v_i16m4_i8m4
+// CHECK-IR-SAME: (<vscale x 16 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i16> [[SRC]] to <vscale x 32 x i8>
+// CHECK-IR-NEXT:    ret <vscale x 32 x i8> [[TMP0]]
+//
+vint8m4_t test_vreinterpret_v_i16m4_i8m4(vint16m4_t src) {
+  return __riscv_th_vreinterpret_v_i16m4_i8m4(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 64 x i8> @test_vreinterpret_v_i16m8_i8m8
+// CHECK-IR-SAME: (<vscale x 32 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x i16> [[SRC]] to <vscale x 64 x i8>
+// CHECK-IR-NEXT:    ret <vscale x 64 x i8> [[TMP0]]
+//
+vint8m8_t test_vreinterpret_v_i16m8_i8m8(vint16m8_t src) {
+  return __riscv_th_vreinterpret_v_i16m8_i8m8(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_u16m1_u8m1
+// CHECK-IR-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC]] to <vscale x 8 x i8>
+// CHECK-IR-NEXT:    ret <vscale x 8 x i8> [[TMP0]]
+//
+vuint8m1_t test_vreinterpret_v_u16m1_u8m1(vuint16m1_t src) {
+  return __riscv_th_vreinterpret_v_u16m1_u8m1(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 16 x i8> @test_vreinterpret_v_u16m2_u8m2
+// CHECK-IR-SAME: (<vscale x 8 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i16> [[SRC]] to <vscale x 16 x i8>
+// CHECK-IR-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
+//
+vuint8m2_t test_vreinterpret_v_u16m2_u8m2(vuint16m2_t src) {
+  return __riscv_th_vreinterpret_v_u16m2_u8m2(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 32 x i8> @test_vreinterpret_v_u16m4_u8m4
+// CHECK-IR-SAME: (<vscale x 16 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i16> [[SRC]] to <vscale x 32 x i8>
+// CHECK-IR-NEXT:    ret <vscale x 32 x i8> [[TMP0]]
+//
+vuint8m4_t test_vreinterpret_v_u16m4_u8m4(vuint16m4_t src) {
+  return __riscv_th_vreinterpret_v_u16m4_u8m4(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 64 x i8> @test_vreinterpret_v_u16m8_u8m8
+// CHECK-IR-SAME: (<vscale x 32 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x i16> [[SRC]] to <vscale x 64 x i8>
+// CHECK-IR-NEXT:    ret <vscale x 64 x i8> [[TMP0]]
+//
+vuint8m8_t test_vreinterpret_v_u16m8_u8m8(vuint16m8_t src) {
+  return __riscv_th_vreinterpret_v_u16m8_u8m8(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_i16m1_i32m1
+// CHECK-IR-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC]] to <vscale x 2 x i32>
+// CHECK-IR-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+vint32m1_t test_vreinterpret_v_i16m1_i32m1(vint16m1_t src) {
+  return __riscv_th_vreinterpret_v_i16m1_i32m1(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 4 x i32> @test_vreinterpret_v_i16m2_i32m2
+// CHECK-IR-SAME: (<vscale x 8 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i16> [[SRC]] to <vscale x 4 x i32>
+// CHECK-IR-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
+//
+vint32m2_t test_vreinterpret_v_i16m2_i32m2(vint16m2_t src) {
+  return __riscv_th_vreinterpret_v_i16m2_i32m2(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 8 x i32> @test_vreinterpret_v_i16m4_i32m4
+// CHECK-IR-SAME: (<vscale x 16 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i16> [[SRC]] to <vscale x 8 x i32>
+// CHECK-IR-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
+//
+vint32m4_t test_vreinterpret_v_i16m4_i32m4(vint16m4_t src) {
+  return __riscv_th_vreinterpret_v_i16m4_i32m4(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 16 x i32> @test_vreinterpret_v_i16m8_i32m8
+// CHECK-IR-SAME: (<vscale x 32 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x i16> [[SRC]] to <vscale x 16 x i32>
+// CHECK-IR-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
+//
+vint32m8_t test_vreinterpret_v_i16m8_i32m8(vint16m8_t src) {
+  return __riscv_th_vreinterpret_v_i16m8_i32m8(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_u16m1_u32m1
+// CHECK-IR-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC]] to <vscale x 2 x i32>
+// CHECK-IR-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+vuint32m1_t test_vreinterpret_v_u16m1_u32m1(vuint16m1_t src) {
+  return __riscv_th_vreinterpret_v_u16m1_u32m1(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 4 x i32> @test_vreinterpret_v_u16m2_u32m2
+// CHECK-IR-SAME: (<vscale x 8 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i16> [[SRC]] to <vscale x 4 x i32>
+// CHECK-IR-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
+//
+vuint32m2_t test_vreinterpret_v_u16m2_u32m2(vuint16m2_t src) {
+  return __riscv_th_vreinterpret_v_u16m2_u32m2(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 8 x i32> @test_vreinterpret_v_u16m4_u32m4
+// CHECK-IR-SAME: (<vscale x 16 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i16> [[SRC]] to <vscale x 8 x i32>
+// CHECK-IR-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
+//
+vuint32m4_t test_vreinterpret_v_u16m4_u32m4(vuint16m4_t src) {
+  return __riscv_th_vreinterpret_v_u16m4_u32m4(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 16 x i32> @test_vreinterpret_v_u16m8_u32m8
+// CHECK-IR-SAME: (<vscale x 32 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x i16> [[SRC]] to <vscale x 16 x i32>
+// CHECK-IR-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
+//
+vuint32m8_t test_vreinterpret_v_u16m8_u32m8(vuint16m8_t src) {
+  return __riscv_th_vreinterpret_v_u16m8_u32m8(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_i16m1_i64m1
+// CHECK-IR-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC]] to <vscale x 1 x i64>
+// CHECK-IR-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
+//
+vint64m1_t test_vreinterpret_v_i16m1_i64m1(vint16m1_t src) {
+  return __riscv_th_vreinterpret_v_i16m1_i64m1(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 2 x i64> @test_vreinterpret_v_i16m2_i64m2
+// CHECK-IR-SAME: (<vscale x 8 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i16> [[SRC]] to <vscale x 2 x i64>
+// CHECK-IR-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
+//
+vint64m2_t test_vreinterpret_v_i16m2_i64m2(vint16m2_t src) {
+  return __riscv_th_vreinterpret_v_i16m2_i64m2(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 4 x i64> @test_vreinterpret_v_i16m4_i64m4
+// CHECK-IR-SAME: (<vscale x 16 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i16> [[SRC]] to <vscale x 4 x i64>
+// CHECK-IR-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
+//
+vint64m4_t test_vreinterpret_v_i16m4_i64m4(vint16m4_t src) {
+  return __riscv_th_vreinterpret_v_i16m4_i64m4(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 8 x i64> @test_vreinterpret_v_i16m8_i64m8
+// CHECK-IR-SAME: (<vscale x 32 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x i16> [[SRC]] to <vscale x 8 x i64>
+// CHECK-IR-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
+//
+vint64m8_t test_vreinterpret_v_i16m8_i64m8(vint16m8_t src) {
+  return __riscv_th_vreinterpret_v_i16m8_i64m8(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_u16m1_u64m1
+// CHECK-IR-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC]] to <vscale x 1 x i64>
+// CHECK-IR-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
+//
+vuint64m1_t test_vreinterpret_v_u16m1_u64m1(vuint16m1_t src) {
+  return __riscv_th_vreinterpret_v_u16m1_u64m1(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 2 x i64> @test_vreinterpret_v_u16m2_u64m2
+// CHECK-IR-SAME: (<vscale x 8 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i16> [[SRC]] to <vscale x 2 x i64>
+// CHECK-IR-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
+//
+vuint64m2_t test_vreinterpret_v_u16m2_u64m2(vuint16m2_t src) {
+  return __riscv_th_vreinterpret_v_u16m2_u64m2(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 4 x i64> @test_vreinterpret_v_u16m4_u64m4
+// CHECK-IR-SAME: (<vscale x 16 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i16> [[SRC]] to <vscale x 4 x i64>
+// CHECK-IR-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
+//
+vuint64m4_t test_vreinterpret_v_u16m4_u64m4(vuint16m4_t src) {
+  return __riscv_th_vreinterpret_v_u16m4_u64m4(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 8 x i64> @test_vreinterpret_v_u16m8_u64m8
+// CHECK-IR-SAME: (<vscale x 32 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x i16> [[SRC]] to <vscale x 8 x i64>
+// CHECK-IR-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
+//
+vuint64m8_t test_vreinterpret_v_u16m8_u64m8(vuint16m8_t src) {
+  return __riscv_th_vreinterpret_v_u16m8_u64m8(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_i32m1_i8m1
+// CHECK-IR-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i32> [[SRC]] to <vscale x 8 x i8>
+// CHECK-IR-NEXT:    ret <vscale x 8 x i8> [[TMP0]]
+//
+vint8m1_t test_vreinterpret_v_i32m1_i8m1(vint32m1_t src) {
+  return __riscv_th_vreinterpret_v_i32m1_i8m1(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 16 x i8> @test_vreinterpret_v_i32m2_i8m2
+// CHECK-IR-SAME: (<vscale x 4 x i32> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i32> [[SRC]] to <vscale x 16 x i8>
+// CHECK-IR-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
+//
+vint8m2_t test_vreinterpret_v_i32m2_i8m2(vint32m2_t src) {
+  return __riscv_th_vreinterpret_v_i32m2_i8m2(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 32 x i8> @test_vreinterpret_v_i32m4_i8m4
+// CHECK-IR-SAME: (<vscale x 8 x i32> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i32> [[SRC]] to <vscale x 32 x i8>
+// CHECK-IR-NEXT:    ret <vscale x 32 x i8> [[TMP0]]
+//
+vint8m4_t test_vreinterpret_v_i32m4_i8m4(vint32m4_t src) {
+  return __riscv_th_vreinterpret_v_i32m4_i8m4(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 64 x i8> @test_vreinterpret_v_i32m8_i8m8
+// CHECK-IR-SAME: (<vscale x 16 x i32> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i32> [[SRC]] to <vscale x 64 x i8>
+// CHECK-IR-NEXT:    ret <vscale x 64 x i8> [[TMP0]]
+//
+vint8m8_t test_vreinterpret_v_i32m8_i8m8(vint32m8_t src) {
+  return __riscv_th_vreinterpret_v_i32m8_i8m8(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_u32m1_u8m1
+// CHECK-IR-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i32> [[SRC]] to <vscale x 8 x i8>
+// CHECK-IR-NEXT:    ret <vscale x 8 x i8> [[TMP0]]
+//
+vuint8m1_t test_vreinterpret_v_u32m1_u8m1(vuint32m1_t src) {
+  return __riscv_th_vreinterpret_v_u32m1_u8m1(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 16 x i8> @test_vreinterpret_v_u32m2_u8m2
+// CHECK-IR-SAME: (<vscale x 4 x i32> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i32> [[SRC]] to <vscale x 16 x i8>
+// CHECK-IR-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
+//
+vuint8m2_t test_vreinterpret_v_u32m2_u8m2(vuint32m2_t src) {
+  return __riscv_th_vreinterpret_v_u32m2_u8m2(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 32 x i8> @test_vreinterpret_v_u32m4_u8m4
+// CHECK-IR-SAME: (<vscale x 8 x i32> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i32> [[SRC]] to <vscale x 32 x i8>
+// CHECK-IR-NEXT:    ret <vscale x 32 x i8> [[TMP0]]
+//
+vuint8m4_t test_vreinterpret_v_u32m4_u8m4(vuint32m4_t src) {
+  return __riscv_th_vreinterpret_v_u32m4_u8m4(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 64 x i8> @test_vreinterpret_v_u32m8_u8m8
+// CHECK-IR-SAME: (<vscale x 16 x i32> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i32> [[SRC]] to <vscale x 64 x i8>
+// CHECK-IR-NEXT:    ret <vscale x 64 x i8> [[TMP0]]
+//
+vuint8m8_t test_vreinterpret_v_u32m8_u8m8(vuint32m8_t src) {
+  return __riscv_th_vreinterpret_v_u32m8_u8m8(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_i32m1_i16m1
+// CHECK-IR-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i32> [[SRC]] to <vscale x 4 x i16>
+// CHECK-IR-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
+//
+vint16m1_t test_vreinterpret_v_i32m1_i16m1(vint32m1_t src) {
+  return __riscv_th_vreinterpret_v_i32m1_i16m1(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 8 x i16> @test_vreinterpret_v_i32m2_i16m2
+// CHECK-IR-SAME: (<vscale x 4 x i32> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i32> [[SRC]] to <vscale x 8 x i16>
+// CHECK-IR-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
+//
+vint16m2_t test_vreinterpret_v_i32m2_i16m2(vint32m2_t src) {
+  return __riscv_th_vreinterpret_v_i32m2_i16m2(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 16 x i16> @test_vreinterpret_v_i32m4_i16m4
+// CHECK-IR-SAME: (<vscale x 8 x i32> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i32> [[SRC]] to <vscale x 16 x i16>
+// CHECK-IR-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
+//
+vint16m4_t test_vreinterpret_v_i32m4_i16m4(vint32m4_t src) {
+  return __riscv_th_vreinterpret_v_i32m4_i16m4(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 32 x i16> @test_vreinterpret_v_i32m8_i16m8
+// CHECK-IR-SAME: (<vscale x 16 x i32> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i32> [[SRC]] to <vscale x 32 x i16>
+// CHECK-IR-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
+//
+vint16m8_t test_vreinterpret_v_i32m8_i16m8(vint32m8_t src) {
+  return __riscv_th_vreinterpret_v_i32m8_i16m8(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_u32m1_u16m1
+// CHECK-IR-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i32> [[SRC]] to <vscale x 4 x i16>
+// CHECK-IR-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
+//
+vuint16m1_t test_vreinterpret_v_u32m1_u16m1(vuint32m1_t src) {
+  return __riscv_th_vreinterpret_v_u32m1_u16m1(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 8 x i16> @test_vreinterpret_v_u32m2_u16m2
+// CHECK-IR-SAME: (<vscale x 4 x i32> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i32> [[SRC]] to <vscale x 8 x i16>
+// CHECK-IR-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
+//
+vuint16m2_t test_vreinterpret_v_u32m2_u16m2(vuint32m2_t src) {
+  return __riscv_th_vreinterpret_v_u32m2_u16m2(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 16 x i16> @test_vreinterpret_v_u32m4_u16m4
+// CHECK-IR-SAME: (<vscale x 8 x i32> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i32> [[SRC]] to <vscale x 16 x i16>
+// CHECK-IR-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
+//
+vuint16m4_t test_vreinterpret_v_u32m4_u16m4(vuint32m4_t src) {
+  return __riscv_th_vreinterpret_v_u32m4_u16m4(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 32 x i16> @test_vreinterpret_v_u32m8_u16m8
+// CHECK-IR-SAME: (<vscale x 16 x i32> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i32> [[SRC]] to <vscale x 32 x i16>
+// CHECK-IR-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
+//
+vuint16m8_t test_vreinterpret_v_u32m8_u16m8(vuint32m8_t src) {
+  return __riscv_th_vreinterpret_v_u32m8_u16m8(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_i32m1_i64m1
+// CHECK-IR-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i32> [[SRC]] to <vscale x 1 x i64>
+// CHECK-IR-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
+//
+vint64m1_t test_vreinterpret_v_i32m1_i64m1(vint32m1_t src) {
+  return __riscv_th_vreinterpret_v_i32m1_i64m1(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 2 x i64> @test_vreinterpret_v_i32m2_i64m2
+// CHECK-IR-SAME: (<vscale x 4 x i32> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i32> [[SRC]] to <vscale x 2 x i64>
+// CHECK-IR-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
+//
+vint64m2_t test_vreinterpret_v_i32m2_i64m2(vint32m2_t src) {
+  return __riscv_th_vreinterpret_v_i32m2_i64m2(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 4 x i64> @test_vreinterpret_v_i32m4_i64m4
+// CHECK-IR-SAME: (<vscale x 8 x i32> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i32> [[SRC]] to <vscale x 4 x i64>
+// CHECK-IR-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
+//
+vint64m4_t test_vreinterpret_v_i32m4_i64m4(vint32m4_t src) {
+  return __riscv_th_vreinterpret_v_i32m4_i64m4(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 8 x i64> @test_vreinterpret_v_i32m8_i64m8
+// CHECK-IR-SAME: (<vscale x 16 x i32> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i32> [[SRC]] to <vscale x 8 x i64>
+// CHECK-IR-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
+//
+vint64m8_t test_vreinterpret_v_i32m8_i64m8(vint32m8_t src) {
+  return __riscv_th_vreinterpret_v_i32m8_i64m8(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_u32m1_u64m1
+// CHECK-IR-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i32> [[SRC]] to <vscale x 1 x i64>
+// CHECK-IR-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
+//
+vuint64m1_t test_vreinterpret_v_u32m1_u64m1(vuint32m1_t src) {
+  return __riscv_th_vreinterpret_v_u32m1_u64m1(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 2 x i64> @test_vreinterpret_v_u32m2_u64m2
+// CHECK-IR-SAME: (<vscale x 4 x i32> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i32> [[SRC]] to <vscale x 2 x i64>
+// CHECK-IR-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
+//
+vuint64m2_t test_vreinterpret_v_u32m2_u64m2(vuint32m2_t src) {
+  return __riscv_th_vreinterpret_v_u32m2_u64m2(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 4 x i64> @test_vreinterpret_v_u32m4_u64m4
+// CHECK-IR-SAME: (<vscale x 8 x i32> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i32> [[SRC]] to <vscale x 4 x i64>
+// CHECK-IR-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
+//
+vuint64m4_t test_vreinterpret_v_u32m4_u64m4(vuint32m4_t src) {
+  return __riscv_th_vreinterpret_v_u32m4_u64m4(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 8 x i64> @test_vreinterpret_v_u32m8_u64m8
+// CHECK-IR-SAME: (<vscale x 16 x i32> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i32> [[SRC]] to <vscale x 8 x i64>
+// CHECK-IR-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
+//
+vuint64m8_t test_vreinterpret_v_u32m8_u64m8(vuint32m8_t src) {
+  return __riscv_th_vreinterpret_v_u32m8_u64m8(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_i64m1_i8m1
+// CHECK-IR-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i64> [[SRC]] to <vscale x 8 x i8>
+// CHECK-IR-NEXT:    ret <vscale x 8 x i8> [[TMP0]]
+//
+vint8m1_t test_vreinterpret_v_i64m1_i8m1(vint64m1_t src) {
+  return __riscv_th_vreinterpret_v_i64m1_i8m1(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 16 x i8> @test_vreinterpret_v_i64m2_i8m2
+// CHECK-IR-SAME: (<vscale x 2 x i64> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i64> [[SRC]] to <vscale x 16 x i8>
+// CHECK-IR-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
+//
+vint8m2_t test_vreinterpret_v_i64m2_i8m2(vint64m2_t src) {
+  return __riscv_th_vreinterpret_v_i64m2_i8m2(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 32 x i8> @test_vreinterpret_v_i64m4_i8m4
+// CHECK-IR-SAME: (<vscale x 4 x i64> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i64> [[SRC]] to <vscale x 32 x i8>
+// CHECK-IR-NEXT:    ret <vscale x 32 x i8> [[TMP0]]
+//
+vint8m4_t test_vreinterpret_v_i64m4_i8m4(vint64m4_t src) {
+  return __riscv_th_vreinterpret_v_i64m4_i8m4(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 64 x i8> @test_vreinterpret_v_i64m8_i8m8
+// CHECK-IR-SAME: (<vscale x 8 x i64> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i64> [[SRC]] to <vscale x 64 x i8>
+// CHECK-IR-NEXT:    ret <vscale x 64 x i8> [[TMP0]]
+//
+vint8m8_t test_vreinterpret_v_i64m8_i8m8(vint64m8_t src) {
+  return __riscv_th_vreinterpret_v_i64m8_i8m8(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_u64m1_u8m1
+// CHECK-IR-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i64> [[SRC]] to <vscale x 8 x i8>
+// CHECK-IR-NEXT:    ret <vscale x 8 x i8> [[TMP0]]
+//
+vuint8m1_t test_vreinterpret_v_u64m1_u8m1(vuint64m1_t src) {
+  return __riscv_th_vreinterpret_v_u64m1_u8m1(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 16 x i8> @test_vreinterpret_v_u64m2_u8m2
+// CHECK-IR-SAME: (<vscale x 2 x i64> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i64> [[SRC]] to <vscale x 16 x i8>
+// CHECK-IR-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
+//
+vuint8m2_t test_vreinterpret_v_u64m2_u8m2(vuint64m2_t src) {
+  return __riscv_th_vreinterpret_v_u64m2_u8m2(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 32 x i8> @test_vreinterpret_v_u64m4_u8m4
+// CHECK-IR-SAME: (<vscale x 4 x i64> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i64> [[SRC]] to <vscale x 32 x i8>
+// CHECK-IR-NEXT:    ret <vscale x 32 x i8> [[TMP0]]
+//
+vuint8m4_t test_vreinterpret_v_u64m4_u8m4(vuint64m4_t src) {
+  return __riscv_th_vreinterpret_v_u64m4_u8m4(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 64 x i8> @test_vreinterpret_v_u64m8_u8m8
+// CHECK-IR-SAME: (<vscale x 8 x i64> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i64> [[SRC]] to <vscale x 64 x i8>
+// CHECK-IR-NEXT:    ret <vscale x 64 x i8> [[TMP0]]
+//
+vuint8m8_t test_vreinterpret_v_u64m8_u8m8(vuint64m8_t src) {
+  return __riscv_th_vreinterpret_v_u64m8_u8m8(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_i64m1_i16m1
+// CHECK-IR-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i64> [[SRC]] to <vscale x 4 x i16>
+// CHECK-IR-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
+//
+vint16m1_t test_vreinterpret_v_i64m1_i16m1(vint64m1_t src) {
+  return __riscv_th_vreinterpret_v_i64m1_i16m1(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 8 x i16> @test_vreinterpret_v_i64m2_i16m2
+// CHECK-IR-SAME: (<vscale x 2 x i64> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i64> [[SRC]] to <vscale x 8 x i16>
+// CHECK-IR-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
+//
+vint16m2_t test_vreinterpret_v_i64m2_i16m2(vint64m2_t src) {
+  return __riscv_th_vreinterpret_v_i64m2_i16m2(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 16 x i16> @test_vreinterpret_v_i64m4_i16m4
+// CHECK-IR-SAME: (<vscale x 4 x i64> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i64> [[SRC]] to <vscale x 16 x i16>
+// CHECK-IR-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
+//
+vint16m4_t test_vreinterpret_v_i64m4_i16m4(vint64m4_t src) {
+  return __riscv_th_vreinterpret_v_i64m4_i16m4(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 32 x i16> @test_vreinterpret_v_i64m8_i16m8
+// CHECK-IR-SAME: (<vscale x 8 x i64> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i64> [[SRC]] to <vscale x 32 x i16>
+// CHECK-IR-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
+//
+vint16m8_t test_vreinterpret_v_i64m8_i16m8(vint64m8_t src) {
+  return __riscv_th_vreinterpret_v_i64m8_i16m8(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_u64m1_u16m1
+// CHECK-IR-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i64> [[SRC]] to <vscale x 4 x i16>
+// CHECK-IR-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
+//
+vuint16m1_t test_vreinterpret_v_u64m1_u16m1(vuint64m1_t src) {
+  return __riscv_th_vreinterpret_v_u64m1_u16m1(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 8 x i16> @test_vreinterpret_v_u64m2_u16m2
+// CHECK-IR-SAME: (<vscale x 2 x i64> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i64> [[SRC]] to <vscale x 8 x i16>
+// CHECK-IR-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
+//
+vuint16m2_t test_vreinterpret_v_u64m2_u16m2(vuint64m2_t src) {
+  return __riscv_th_vreinterpret_v_u64m2_u16m2(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 16 x i16> @test_vreinterpret_v_u64m4_u16m4
+// CHECK-IR-SAME: (<vscale x 4 x i64> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i64> [[SRC]] to <vscale x 16 x i16>
+// CHECK-IR-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
+//
+vuint16m4_t test_vreinterpret_v_u64m4_u16m4(vuint64m4_t src) {
+  return __riscv_th_vreinterpret_v_u64m4_u16m4(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 32 x i16> @test_vreinterpret_v_u64m8_u16m8
+// CHECK-IR-SAME: (<vscale x 8 x i64> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i64> [[SRC]] to <vscale x 32 x i16>
+// CHECK-IR-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
+//
+vuint16m8_t test_vreinterpret_v_u64m8_u16m8(vuint64m8_t src) {
+  return __riscv_th_vreinterpret_v_u64m8_u16m8(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_i64m1_i32m1
+// CHECK-IR-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i64> [[SRC]] to <vscale x 2 x i32>
+// CHECK-IR-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+vint32m1_t test_vreinterpret_v_i64m1_i32m1(vint64m1_t src) {
+  return __riscv_th_vreinterpret_v_i64m1_i32m1(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 4 x i32> @test_vreinterpret_v_i64m2_i32m2
+// CHECK-IR-SAME: (<vscale x 2 x i64> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i64> [[SRC]] to <vscale x 4 x i32>
+// CHECK-IR-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
+//
+vint32m2_t test_vreinterpret_v_i64m2_i32m2(vint64m2_t src) {
+  return __riscv_th_vreinterpret_v_i64m2_i32m2(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 8 x i32> @test_vreinterpret_v_i64m4_i32m4
+// CHECK-IR-SAME: (<vscale x 4 x i64> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i64> [[SRC]] to <vscale x 8 x i32>
+// CHECK-IR-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
+//
+vint32m4_t test_vreinterpret_v_i64m4_i32m4(vint64m4_t src) {
+  return __riscv_th_vreinterpret_v_i64m4_i32m4(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 16 x i32> @test_vreinterpret_v_i64m8_i32m8
+// CHECK-IR-SAME: (<vscale x 8 x i64> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i64> [[SRC]] to <vscale x 16 x i32>
+// CHECK-IR-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
+//
+vint32m8_t test_vreinterpret_v_i64m8_i32m8(vint64m8_t src) {
+  return __riscv_th_vreinterpret_v_i64m8_i32m8(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_u64m1_u32m1
+// CHECK-IR-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i64> [[SRC]] to <vscale x 2 x i32>
+// CHECK-IR-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+vuint32m1_t test_vreinterpret_v_u64m1_u32m1(vuint64m1_t src) {
+  return __riscv_th_vreinterpret_v_u64m1_u32m1(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 4 x i32> @test_vreinterpret_v_u64m2_u32m2
+// CHECK-IR-SAME: (<vscale x 2 x i64> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i64> [[SRC]] to <vscale x 4 x i32>
+// CHECK-IR-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
+//
+vuint32m2_t test_vreinterpret_v_u64m2_u32m2(vuint64m2_t src) {
+  return __riscv_th_vreinterpret_v_u64m2_u32m2(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 8 x i32> @test_vreinterpret_v_u64m4_u32m4
+// CHECK-IR-SAME: (<vscale x 4 x i64> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i64> [[SRC]] to <vscale x 8 x i32>
+// CHECK-IR-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
+//
+vuint32m4_t test_vreinterpret_v_u64m4_u32m4(vuint64m4_t src) {
+  return __riscv_th_vreinterpret_v_u64m4_u32m4(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 16 x i32> @test_vreinterpret_v_u64m8_u32m8
+// CHECK-IR-SAME: (<vscale x 8 x i64> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i64> [[SRC]] to <vscale x 16 x i32>
+// CHECK-IR-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
+//
+vuint32m8_t test_vreinterpret_v_u64m8_u32m8(vuint64m8_t src) {
+  return __riscv_th_vreinterpret_v_u64m8_u32m8(src);
+}
diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/misc/wrappers/vreinterpret_b.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/misc/wrappers/vreinterpret_b.c
new file mode 100644
index 00000000000000..52931d4873debb
--- /dev/null
+++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/misc/wrappers/vreinterpret_b.c
@@ -0,0 +1,975 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
+// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \
+// RUN:   -disable-O0-optnone -emit-llvm %s -o - | \
+// RUN:   opt -S -passes=mem2reg | \
+// RUN:   FileCheck --check-prefix=CHECK-RV64 %s
+
+#include <riscv_vector.h>
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vreinterpret_v_i8m1_b64
+// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i8> [[SRC]] to <vscale x 64 x i1>
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 1 x i1> @llvm.vector.extract.nxv1i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)
+// CHECK-RV64-NEXT:    ret <vscale x 1 x i1> [[TMP1]]
+//
+vbool64_t test_vreinterpret_v_i8m1_b64(vint8m1_t src) {
+  return __riscv_vreinterpret_v_i8m1_b64(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_b64_i8m1
+// CHECK-RV64-SAME: (<vscale x 1 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv1i1(<vscale x 64 x i1> poison, <vscale x 1 x i1> [[SRC]], i64 0)
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 8 x i8>
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP1]]
+//
+vint8m1_t test_vreinterpret_v_b64_i8m1(vbool64_t src) {
+  return __riscv_vreinterpret_v_b64_i8m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vreinterpret_v_i8m1_b32
+// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i8> [[SRC]] to <vscale x 64 x i1>
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)
+// CHECK-RV64-NEXT:    ret <vscale x 2 x i1> [[TMP1]]
+//
+vbool32_t test_vreinterpret_v_i8m1_b32(vint8m1_t src) {
+  return __riscv_vreinterpret_v_i8m1_b32(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_b32_i8m1
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv2i1(<vscale x 64 x i1> poison, <vscale x 2 x i1> [[SRC]], i64 0)
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 8 x i8>
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP1]]
+//
+vint8m1_t test_vreinterpret_v_b32_i8m1(vbool32_t src) {
+  return __riscv_vreinterpret_v_b32_i8m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vreinterpret_v_i8m1_b16
+// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i8> [[SRC]] to <vscale x 64 x i1>
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 4 x i1> @llvm.vector.extract.nxv4i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i1> [[TMP1]]
+//
+vbool16_t test_vreinterpret_v_i8m1_b16(vint8m1_t src) {
+  return __riscv_vreinterpret_v_i8m1_b16(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_b16_i8m1
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv4i1(<vscale x 64 x i1> poison, <vscale x 4 x i1> [[SRC]], i64 0)
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 8 x i8>
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP1]]
+//
+vint8m1_t test_vreinterpret_v_b16_i8m1(vbool16_t src) {
+  return __riscv_vreinterpret_v_b16_i8m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vreinterpret_v_i8m1_b8
+// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i8> [[SRC]] to <vscale x 64 x i1>
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 8 x i1> @llvm.vector.extract.nxv8i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i1> [[TMP1]]
+//
+vbool8_t test_vreinterpret_v_i8m1_b8(vint8m1_t src) {
+  return __riscv_vreinterpret_v_i8m1_b8(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_b8_i8m1
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv8i1(<vscale x 64 x i1> poison, <vscale x 8 x i1> [[SRC]], i64 0)
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 8 x i8>
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP1]]
+//
+vint8m1_t test_vreinterpret_v_b8_i8m1(vbool8_t src) {
+  return __riscv_vreinterpret_v_b8_i8m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vreinterpret_v_i8m1_b4
+// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i8> [[SRC]] to <vscale x 64 x i1>
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 16 x i1> @llvm.vector.extract.nxv16i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)
+// CHECK-RV64-NEXT:    ret <vscale x 16 x i1> [[TMP1]]
+//
+vbool4_t test_vreinterpret_v_i8m1_b4(vint8m1_t src) {
+  return __riscv_vreinterpret_v_i8m1_b4(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_b4_i8m1
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv16i1(<vscale x 64 x i1> poison, <vscale x 16 x i1> [[SRC]], i64 0)
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 8 x i8>
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP1]]
+//
+vint8m1_t test_vreinterpret_v_b4_i8m1(vbool4_t src) {
+  return __riscv_vreinterpret_v_b4_i8m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i1> @test_vreinterpret_v_i8m1_b2
+// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i8> [[SRC]] to <vscale x 64 x i1>
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 32 x i1> @llvm.vector.extract.nxv32i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)
+// CHECK-RV64-NEXT:    ret <vscale x 32 x i1> [[TMP1]]
+//
+vbool2_t test_vreinterpret_v_i8m1_b2(vint8m1_t src) {
+  return __riscv_vreinterpret_v_i8m1_b2(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_b2_i8m1
+// CHECK-RV64-SAME: (<vscale x 32 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv32i1(<vscale x 64 x i1> poison, <vscale x 32 x i1> [[SRC]], i64 0)
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 8 x i8>
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP1]]
+//
+vint8m1_t test_vreinterpret_v_b2_i8m1(vbool2_t src) {
+  return __riscv_vreinterpret_v_b2_i8m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i1> @test_vreinterpret_v_i8m1_b1
+// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i8> [[SRC]] to <vscale x 64 x i1>
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 64 x i1> @llvm.vector.extract.nxv64i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)
+// CHECK-RV64-NEXT:    ret <vscale x 64 x i1> [[TMP1]]
+//
+vbool1_t test_vreinterpret_v_i8m1_b1(vint8m1_t src) {
+  return __riscv_vreinterpret_v_i8m1_b1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_b1_i8m1
+// CHECK-RV64-SAME: (<vscale x 64 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv64i1(<vscale x 64 x i1> poison, <vscale x 64 x i1> [[SRC]], i64 0)
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 8 x i8>
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP1]]
+//
+vint8m1_t test_vreinterpret_v_b1_i8m1(vbool1_t src) {
+  return __riscv_vreinterpret_v_b1_i8m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vreinterpret_v_u8m1_b64
+// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i8> [[SRC]] to <vscale x 64 x i1>
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 1 x i1> @llvm.vector.extract.nxv1i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)
+// CHECK-RV64-NEXT:    ret <vscale x 1 x i1> [[TMP1]]
+//
+vbool64_t test_vreinterpret_v_u8m1_b64(vuint8m1_t src) {
+  return __riscv_vreinterpret_v_u8m1_b64(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_b64_u8m1
+// CHECK-RV64-SAME: (<vscale x 1 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv1i1(<vscale x 64 x i1> poison, <vscale x 1 x i1> [[SRC]], i64 0)
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 8 x i8>
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP1]]
+//
+vuint8m1_t test_vreinterpret_v_b64_u8m1(vbool64_t src) {
+  return __riscv_vreinterpret_v_b64_u8m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vreinterpret_v_u8m1_b32
+// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i8> [[SRC]] to <vscale x 64 x i1>
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)
+// CHECK-RV64-NEXT:    ret <vscale x 2 x i1> [[TMP1]]
+//
+vbool32_t test_vreinterpret_v_u8m1_b32(vuint8m1_t src) {
+  return __riscv_vreinterpret_v_u8m1_b32(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_b32_u8m1
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv2i1(<vscale x 64 x i1> poison, <vscale x 2 x i1> [[SRC]], i64 0)
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 8 x i8>
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP1]]
+//
+vuint8m1_t test_vreinterpret_v_b32_u8m1(vbool32_t src) {
+  return __riscv_vreinterpret_v_b32_u8m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vreinterpret_v_u8m1_b16
+// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i8> [[SRC]] to <vscale x 64 x i1>
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 4 x i1> @llvm.vector.extract.nxv4i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i1> [[TMP1]]
+//
+vbool16_t test_vreinterpret_v_u8m1_b16(vuint8m1_t src) {
+  return __riscv_vreinterpret_v_u8m1_b16(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_b16_u8m1
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv4i1(<vscale x 64 x i1> poison, <vscale x 4 x i1> [[SRC]], i64 0)
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 8 x i8>
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP1]]
+//
+vuint8m1_t test_vreinterpret_v_b16_u8m1(vbool16_t src) {
+  return __riscv_vreinterpret_v_b16_u8m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vreinterpret_v_u8m1_b8
+// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i8> [[SRC]] to <vscale x 64 x i1>
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 8 x i1> @llvm.vector.extract.nxv8i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i1> [[TMP1]]
+//
+vbool8_t test_vreinterpret_v_u8m1_b8(vuint8m1_t src) {
+  return __riscv_vreinterpret_v_u8m1_b8(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_b8_u8m1
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv8i1(<vscale x 64 x i1> poison, <vscale x 8 x i1> [[SRC]], i64 0)
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 8 x i8>
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP1]]
+//
+vuint8m1_t test_vreinterpret_v_b8_u8m1(vbool8_t src) {
+  return __riscv_vreinterpret_v_b8_u8m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vreinterpret_v_u8m1_b4
+// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i8> [[SRC]] to <vscale x 64 x i1>
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 16 x i1> @llvm.vector.extract.nxv16i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)
+// CHECK-RV64-NEXT:    ret <vscale x 16 x i1> [[TMP1]]
+//
+vbool4_t test_vreinterpret_v_u8m1_b4(vuint8m1_t src) {
+  return __riscv_vreinterpret_v_u8m1_b4(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_b4_u8m1
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv16i1(<vscale x 64 x i1> poison, <vscale x 16 x i1> [[SRC]], i64 0)
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 8 x i8>
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP1]]
+//
+vuint8m1_t test_vreinterpret_v_b4_u8m1(vbool4_t src) {
+  return __riscv_vreinterpret_v_b4_u8m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i1> @test_vreinterpret_v_u8m1_b2
+// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i8> [[SRC]] to <vscale x 64 x i1>
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 32 x i1> @llvm.vector.extract.nxv32i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)
+// CHECK-RV64-NEXT:    ret <vscale x 32 x i1> [[TMP1]]
+//
+vbool2_t test_vreinterpret_v_u8m1_b2(vuint8m1_t src) {
+  return __riscv_vreinterpret_v_u8m1_b2(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_b2_u8m1
+// CHECK-RV64-SAME: (<vscale x 32 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv32i1(<vscale x 64 x i1> poison, <vscale x 32 x i1> [[SRC]], i64 0)
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 8 x i8>
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP1]]
+//
+vuint8m1_t test_vreinterpret_v_b2_u8m1(vbool2_t src) {
+  return __riscv_vreinterpret_v_b2_u8m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i1> @test_vreinterpret_v_u8m1_b1
+// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i8> [[SRC]] to <vscale x 64 x i1>
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 64 x i1> @llvm.vector.extract.nxv64i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)
+// CHECK-RV64-NEXT:    ret <vscale x 64 x i1> [[TMP1]]
+//
+vbool1_t test_vreinterpret_v_u8m1_b1(vuint8m1_t src) {
+  return __riscv_vreinterpret_v_u8m1_b1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_b1_u8m1
+// CHECK-RV64-SAME: (<vscale x 64 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv64i1(<vscale x 64 x i1> poison, <vscale x 64 x i1> [[SRC]], i64 0)
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 8 x i8>
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP1]]
+//
+vuint8m1_t test_vreinterpret_v_b1_u8m1(vbool1_t src) {
+  return __riscv_vreinterpret_v_b1_u8m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vreinterpret_v_i16m1_b64
+// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC]] to <vscale x 64 x i1>
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 1 x i1> @llvm.vector.extract.nxv1i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)
+// CHECK-RV64-NEXT:    ret <vscale x 1 x i1> [[TMP1]]
+//
+vbool64_t test_vreinterpret_v_i16m1_b64(vint16m1_t src) {
+  return __riscv_vreinterpret_v_i16m1_b64(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_b64_i16m1
+// CHECK-RV64-SAME: (<vscale x 1 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv1i1(<vscale x 64 x i1> poison, <vscale x 1 x i1> [[SRC]], i64 0)
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 4 x i16>
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP1]]
+//
+vint16m1_t test_vreinterpret_v_b64_i16m1(vbool64_t src) {
+  return __riscv_vreinterpret_v_b64_i16m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vreinterpret_v_i16m1_b32
+// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC]] to <vscale x 64 x i1>
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)
+// CHECK-RV64-NEXT:    ret <vscale x 2 x i1> [[TMP1]]
+//
+vbool32_t test_vreinterpret_v_i16m1_b32(vint16m1_t src) {
+  return __riscv_vreinterpret_v_i16m1_b32(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_b32_i16m1
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv2i1(<vscale x 64 x i1> poison, <vscale x 2 x i1> [[SRC]], i64 0)
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 4 x i16>
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP1]]
+//
+vint16m1_t test_vreinterpret_v_b32_i16m1(vbool32_t src) {
+  return __riscv_vreinterpret_v_b32_i16m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vreinterpret_v_i16m1_b16
+// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC]] to <vscale x 64 x i1>
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 4 x i1> @llvm.vector.extract.nxv4i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i1> [[TMP1]]
+//
+vbool16_t test_vreinterpret_v_i16m1_b16(vint16m1_t src) {
+  return __riscv_vreinterpret_v_i16m1_b16(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_b16_i16m1
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv4i1(<vscale x 64 x i1> poison, <vscale x 4 x i1> [[SRC]], i64 0)
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 4 x i16>
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP1]]
+//
+vint16m1_t test_vreinterpret_v_b16_i16m1(vbool16_t src) {
+  return __riscv_vreinterpret_v_b16_i16m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vreinterpret_v_i16m1_b8
+// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC]] to <vscale x 64 x i1>
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 8 x i1> @llvm.vector.extract.nxv8i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i1> [[TMP1]]
+//
+vbool8_t test_vreinterpret_v_i16m1_b8(vint16m1_t src) {
+  return __riscv_vreinterpret_v_i16m1_b8(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_b8_i16m1
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv8i1(<vscale x 64 x i1> poison, <vscale x 8 x i1> [[SRC]], i64 0)
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 4 x i16>
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP1]]
+//
+vint16m1_t test_vreinterpret_v_b8_i16m1(vbool8_t src) {
+  return __riscv_vreinterpret_v_b8_i16m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vreinterpret_v_i16m1_b4
+// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC]] to <vscale x 64 x i1>
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 16 x i1> @llvm.vector.extract.nxv16i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)
+// CHECK-RV64-NEXT:    ret <vscale x 16 x i1> [[TMP1]]
+//
+vbool4_t test_vreinterpret_v_i16m1_b4(vint16m1_t src) {
+  return __riscv_vreinterpret_v_i16m1_b4(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_b4_i16m1
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv16i1(<vscale x 64 x i1> poison, <vscale x 16 x i1> [[SRC]], i64 0)
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 4 x i16>
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP1]]
+//
+vint16m1_t test_vreinterpret_v_b4_i16m1(vbool4_t src) {
+  return __riscv_vreinterpret_v_b4_i16m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i1> @test_vreinterpret_v_i16m1_b2
+// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC]] to <vscale x 64 x i1>
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 32 x i1> @llvm.vector.extract.nxv32i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)
+// CHECK-RV64-NEXT:    ret <vscale x 32 x i1> [[TMP1]]
+//
+vbool2_t test_vreinterpret_v_i16m1_b2(vint16m1_t src) {
+  return __riscv_vreinterpret_v_i16m1_b2(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_b2_i16m1
+// CHECK-RV64-SAME: (<vscale x 32 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv32i1(<vscale x 64 x i1> poison, <vscale x 32 x i1> [[SRC]], i64 0)
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 4 x i16>
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP1]]
+//
+vint16m1_t test_vreinterpret_v_b2_i16m1(vbool2_t src) {
+  return __riscv_vreinterpret_v_b2_i16m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vreinterpret_v_u16m1_b64
+// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC]] to <vscale x 64 x i1>
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 1 x i1> @llvm.vector.extract.nxv1i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)
+// CHECK-RV64-NEXT:    ret <vscale x 1 x i1> [[TMP1]]
+//
+vbool64_t test_vreinterpret_v_u16m1_b64(vuint16m1_t src) {
+  return __riscv_vreinterpret_v_u16m1_b64(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_b64_u16m1
+// CHECK-RV64-SAME: (<vscale x 1 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv1i1(<vscale x 64 x i1> poison, <vscale x 1 x i1> [[SRC]], i64 0)
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 4 x i16>
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP1]]
+//
+vuint16m1_t test_vreinterpret_v_b64_u16m1(vbool64_t src) {
+  return __riscv_vreinterpret_v_b64_u16m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vreinterpret_v_u16m1_b32
+// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC]] to <vscale x 64 x i1>
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)
+// CHECK-RV64-NEXT:    ret <vscale x 2 x i1> [[TMP1]]
+//
+vbool32_t test_vreinterpret_v_u16m1_b32(vuint16m1_t src) {
+  return __riscv_vreinterpret_v_u16m1_b32(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_b32_u16m1
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv2i1(<vscale x 64 x i1> poison, <vscale x 2 x i1> [[SRC]], i64 0)
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 4 x i16>
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP1]]
+//
+vuint16m1_t test_vreinterpret_v_b32_u16m1(vbool32_t src) {
+  return __riscv_vreinterpret_v_b32_u16m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vreinterpret_v_u16m1_b16
+// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC]] to <vscale x 64 x i1>
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 4 x i1> @llvm.vector.extract.nxv4i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i1> [[TMP1]]
+//
+vbool16_t test_vreinterpret_v_u16m1_b16(vuint16m1_t src) {
+  return __riscv_vreinterpret_v_u16m1_b16(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_b16_u16m1
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv4i1(<vscale x 64 x i1> poison, <vscale x 4 x i1> [[SRC]], i64 0)
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 4 x i16>
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP1]]
+//
+vuint16m1_t test_vreinterpret_v_b16_u16m1(vbool16_t src) {
+  return __riscv_vreinterpret_v_b16_u16m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vreinterpret_v_u16m1_b8
+// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC]] to <vscale x 64 x i1>
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 8 x i1> @llvm.vector.extract.nxv8i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i1> [[TMP1]]
+//
+vbool8_t test_vreinterpret_v_u16m1_b8(vuint16m1_t src) {
+  return __riscv_vreinterpret_v_u16m1_b8(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_b8_u16m1
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv8i1(<vscale x 64 x i1> poison, <vscale x 8 x i1> [[SRC]], i64 0)
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 4 x i16>
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP1]]
+//
+vuint16m1_t test_vreinterpret_v_b8_u16m1(vbool8_t src) {
+  return __riscv_vreinterpret_v_b8_u16m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vreinterpret_v_u16m1_b4
+// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC]] to <vscale x 64 x i1>
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 16 x i1> @llvm.vector.extract.nxv16i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)
+// CHECK-RV64-NEXT:    ret <vscale x 16 x i1> [[TMP1]]
+//
+vbool4_t test_vreinterpret_v_u16m1_b4(vuint16m1_t src) {
+  return __riscv_vreinterpret_v_u16m1_b4(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_b4_u16m1
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv16i1(<vscale x 64 x i1> poison, <vscale x 16 x i1> [[SRC]], i64 0)
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 4 x i16>
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP1]]
+//
+vuint16m1_t test_vreinterpret_v_b4_u16m1(vbool4_t src) {
+  return __riscv_vreinterpret_v_b4_u16m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i1> @test_vreinterpret_v_u16m1_b2
+// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC]] to <vscale x 64 x i1>
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 32 x i1> @llvm.vector.extract.nxv32i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)
+// CHECK-RV64-NEXT:    ret <vscale x 32 x i1> [[TMP1]]
+//
+vbool2_t test_vreinterpret_v_u16m1_b2(vuint16m1_t src) {
+  return __riscv_vreinterpret_v_u16m1_b2(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_b2_u16m1
+// CHECK-RV64-SAME: (<vscale x 32 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv32i1(<vscale x 64 x i1> poison, <vscale x 32 x i1> [[SRC]], i64 0)
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 4 x i16>
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP1]]
+//
+vuint16m1_t test_vreinterpret_v_b2_u16m1(vbool2_t src) {
+  return __riscv_vreinterpret_v_b2_u16m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vreinterpret_v_i32m1_b64
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i32> [[SRC]] to <vscale x 64 x i1>
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 1 x i1> @llvm.vector.extract.nxv1i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)
+// CHECK-RV64-NEXT:    ret <vscale x 1 x i1> [[TMP1]]
+//
+vbool64_t test_vreinterpret_v_i32m1_b64(vint32m1_t src) {
+  return __riscv_vreinterpret_v_i32m1_b64(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_b64_i32m1
+// CHECK-RV64-SAME: (<vscale x 1 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv1i1(<vscale x 64 x i1> poison, <vscale x 1 x i1> [[SRC]], i64 0)
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 2 x i32>
+// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP1]]
+//
+vint32m1_t test_vreinterpret_v_b64_i32m1(vbool64_t src) {
+  return __riscv_vreinterpret_v_b64_i32m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vreinterpret_v_i32m1_b32
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i32> [[SRC]] to <vscale x 64 x i1>
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)
+// CHECK-RV64-NEXT:    ret <vscale x 2 x i1> [[TMP1]]
+//
+vbool32_t test_vreinterpret_v_i32m1_b32(vint32m1_t src) {
+  return __riscv_vreinterpret_v_i32m1_b32(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_b32_i32m1
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv2i1(<vscale x 64 x i1> poison, <vscale x 2 x i1> [[SRC]], i64 0)
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 2 x i32>
+// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP1]]
+//
+vint32m1_t test_vreinterpret_v_b32_i32m1(vbool32_t src) {
+  return __riscv_vreinterpret_v_b32_i32m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vreinterpret_v_i32m1_b16
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i32> [[SRC]] to <vscale x 64 x i1>
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 4 x i1> @llvm.vector.extract.nxv4i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i1> [[TMP1]]
+//
+vbool16_t test_vreinterpret_v_i32m1_b16(vint32m1_t src) {
+  return __riscv_vreinterpret_v_i32m1_b16(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_b16_i32m1
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv4i1(<vscale x 64 x i1> poison, <vscale x 4 x i1> [[SRC]], i64 0)
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 2 x i32>
+// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP1]]
+//
+vint32m1_t test_vreinterpret_v_b16_i32m1(vbool16_t src) {
+  return __riscv_vreinterpret_v_b16_i32m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vreinterpret_v_i32m1_b8
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i32> [[SRC]] to <vscale x 64 x i1>
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 8 x i1> @llvm.vector.extract.nxv8i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i1> [[TMP1]]
+//
+vbool8_t test_vreinterpret_v_i32m1_b8(vint32m1_t src) {
+  return __riscv_vreinterpret_v_i32m1_b8(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_b8_i32m1
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv8i1(<vscale x 64 x i1> poison, <vscale x 8 x i1> [[SRC]], i64 0)
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 2 x i32>
+// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP1]]
+//
+vint32m1_t test_vreinterpret_v_b8_i32m1(vbool8_t src) {
+  return __riscv_vreinterpret_v_b8_i32m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vreinterpret_v_i32m1_b4
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i32> [[SRC]] to <vscale x 64 x i1>
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 16 x i1> @llvm.vector.extract.nxv16i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)
+// CHECK-RV64-NEXT:    ret <vscale x 16 x i1> [[TMP1]]
+//
+vbool4_t test_vreinterpret_v_i32m1_b4(vint32m1_t src) {
+  return __riscv_vreinterpret_v_i32m1_b4(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_b4_i32m1
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv16i1(<vscale x 64 x i1> poison, <vscale x 16 x i1> [[SRC]], i64 0)
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 2 x i32>
+// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP1]]
+//
+vint32m1_t test_vreinterpret_v_b4_i32m1(vbool4_t src) {
+  return __riscv_vreinterpret_v_b4_i32m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vreinterpret_v_u32m1_b64
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i32> [[SRC]] to <vscale x 64 x i1>
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 1 x i1> @llvm.vector.extract.nxv1i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)
+// CHECK-RV64-NEXT:    ret <vscale x 1 x i1> [[TMP1]]
+//
+vbool64_t test_vreinterpret_v_u32m1_b64(vuint32m1_t src) {
+  return __riscv_vreinterpret_v_u32m1_b64(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_b64_u32m1
+// CHECK-RV64-SAME: (<vscale x 1 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv1i1(<vscale x 64 x i1> poison, <vscale x 1 x i1> [[SRC]], i64 0)
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 2 x i32>
+// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP1]]
+//
+vuint32m1_t test_vreinterpret_v_b64_u32m1(vbool64_t src) {
+  return __riscv_vreinterpret_v_b64_u32m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vreinterpret_v_u32m1_b32
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i32> [[SRC]] to <vscale x 64 x i1>
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)
+// CHECK-RV64-NEXT:    ret <vscale x 2 x i1> [[TMP1]]
+//
+vbool32_t test_vreinterpret_v_u32m1_b32(vuint32m1_t src) {
+  return __riscv_vreinterpret_v_u32m1_b32(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_b32_u32m1
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv2i1(<vscale x 64 x i1> poison, <vscale x 2 x i1> [[SRC]], i64 0)
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 2 x i32>
+// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP1]]
+//
+vuint32m1_t test_vreinterpret_v_b32_u32m1(vbool32_t src) {
+  return __riscv_vreinterpret_v_b32_u32m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vreinterpret_v_u32m1_b16
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i32> [[SRC]] to <vscale x 64 x i1>
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 4 x i1> @llvm.vector.extract.nxv4i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i1> [[TMP1]]
+//
+vbool16_t test_vreinterpret_v_u32m1_b16(vuint32m1_t src) {
+  return __riscv_vreinterpret_v_u32m1_b16(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_b16_u32m1
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv4i1(<vscale x 64 x i1> poison, <vscale x 4 x i1> [[SRC]], i64 0)
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 2 x i32>
+// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP1]]
+//
+vuint32m1_t test_vreinterpret_v_b16_u32m1(vbool16_t src) {
+  return __riscv_vreinterpret_v_b16_u32m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vreinterpret_v_u32m1_b8
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i32> [[SRC]] to <vscale x 64 x i1>
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 8 x i1> @llvm.vector.extract.nxv8i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i1> [[TMP1]]
+//
+vbool8_t test_vreinterpret_v_u32m1_b8(vuint32m1_t src) {
+  return __riscv_vreinterpret_v_u32m1_b8(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_b8_u32m1
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv8i1(<vscale x 64 x i1> poison, <vscale x 8 x i1> [[SRC]], i64 0)
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 2 x i32>
+// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP1]]
+//
+vuint32m1_t test_vreinterpret_v_b8_u32m1(vbool8_t src) {
+  return __riscv_vreinterpret_v_b8_u32m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vreinterpret_v_u32m1_b4
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i32> [[SRC]] to <vscale x 64 x i1>
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 16 x i1> @llvm.vector.extract.nxv16i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)
+// CHECK-RV64-NEXT:    ret <vscale x 16 x i1> [[TMP1]]
+//
+vbool4_t test_vreinterpret_v_u32m1_b4(vuint32m1_t src) {
+  return __riscv_vreinterpret_v_u32m1_b4(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_b4_u32m1
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv16i1(<vscale x 64 x i1> poison, <vscale x 16 x i1> [[SRC]], i64 0)
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 2 x i32>
+// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP1]]
+//
+vuint32m1_t test_vreinterpret_v_b4_u32m1(vbool4_t src) {
+  return __riscv_vreinterpret_v_b4_u32m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vreinterpret_v_i64m1_b64
+// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i64> [[SRC]] to <vscale x 64 x i1>
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 1 x i1> @llvm.vector.extract.nxv1i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)
+// CHECK-RV64-NEXT:    ret <vscale x 1 x i1> [[TMP1]]
+//
+vbool64_t test_vreinterpret_v_i64m1_b64(vint64m1_t src) {
+  return __riscv_vreinterpret_v_i64m1_b64(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_b64_i64m1
+// CHECK-RV64-SAME: (<vscale x 1 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv1i1(<vscale x 64 x i1> poison, <vscale x 1 x i1> [[SRC]], i64 0)
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 1 x i64>
+// CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP1]]
+//
+vint64m1_t test_vreinterpret_v_b64_i64m1(vbool64_t src) {
+  return __riscv_vreinterpret_v_b64_i64m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vreinterpret_v_i64m1_b32
+// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i64> [[SRC]] to <vscale x 64 x i1>
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)
+// CHECK-RV64-NEXT:    ret <vscale x 2 x i1> [[TMP1]]
+//
+vbool32_t test_vreinterpret_v_i64m1_b32(vint64m1_t src) {
+  return __riscv_vreinterpret_v_i64m1_b32(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_b32_i64m1
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv2i1(<vscale x 64 x i1> poison, <vscale x 2 x i1> [[SRC]], i64 0)
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 1 x i64>
+// CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP1]]
+//
+vint64m1_t test_vreinterpret_v_b32_i64m1(vbool32_t src) {
+  return __riscv_vreinterpret_v_b32_i64m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vreinterpret_v_i64m1_b16
+// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i64> [[SRC]] to <vscale x 64 x i1>
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 4 x i1> @llvm.vector.extract.nxv4i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i1> [[TMP1]]
+//
+vbool16_t test_vreinterpret_v_i64m1_b16(vint64m1_t src) {
+  return __riscv_vreinterpret_v_i64m1_b16(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_b16_i64m1
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv4i1(<vscale x 64 x i1> poison, <vscale x 4 x i1> [[SRC]], i64 0)
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 1 x i64>
+// CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP1]]
+//
+vint64m1_t test_vreinterpret_v_b16_i64m1(vbool16_t src) {
+  return __riscv_vreinterpret_v_b16_i64m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vreinterpret_v_i64m1_b8
+// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i64> [[SRC]] to <vscale x 64 x i1>
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 8 x i1> @llvm.vector.extract.nxv8i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i1> [[TMP1]]
+//
+vbool8_t test_vreinterpret_v_i64m1_b8(vint64m1_t src) {
+  return __riscv_vreinterpret_v_i64m1_b8(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_b8_i64m1
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv8i1(<vscale x 64 x i1> poison, <vscale x 8 x i1> [[SRC]], i64 0)
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 1 x i64>
+// CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP1]]
+//
+vint64m1_t test_vreinterpret_v_b8_i64m1(vbool8_t src) {
+  return __riscv_vreinterpret_v_b8_i64m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vreinterpret_v_u64m1_b64
+// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i64> [[SRC]] to <vscale x 64 x i1>
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 1 x i1> @llvm.vector.extract.nxv1i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)
+// CHECK-RV64-NEXT:    ret <vscale x 1 x i1> [[TMP1]]
+//
+vbool64_t test_vreinterpret_v_u64m1_b64(vuint64m1_t src) {
+  return __riscv_vreinterpret_v_u64m1_b64(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_b64_u64m1
+// CHECK-RV64-SAME: (<vscale x 1 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv1i1(<vscale x 64 x i1> poison, <vscale x 1 x i1> [[SRC]], i64 0)
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 1 x i64>
+// CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP1]]
+//
+vuint64m1_t test_vreinterpret_v_b64_u64m1(vbool64_t src) {
+  return __riscv_vreinterpret_v_b64_u64m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vreinterpret_v_u64m1_b32
+// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i64> [[SRC]] to <vscale x 64 x i1>
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)
+// CHECK-RV64-NEXT:    ret <vscale x 2 x i1> [[TMP1]]
+//
+vbool32_t test_vreinterpret_v_u64m1_b32(vuint64m1_t src) {
+  return __riscv_vreinterpret_v_u64m1_b32(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_b32_u64m1
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv2i1(<vscale x 64 x i1> poison, <vscale x 2 x i1> [[SRC]], i64 0)
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 1 x i64>
+// CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP1]]
+//
+vuint64m1_t test_vreinterpret_v_b32_u64m1(vbool32_t src) {
+  return __riscv_vreinterpret_v_b32_u64m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vreinterpret_v_u64m1_b16
+// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i64> [[SRC]] to <vscale x 64 x i1>
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 4 x i1> @llvm.vector.extract.nxv4i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i1> [[TMP1]]
+//
+vbool16_t test_vreinterpret_v_u64m1_b16(vuint64m1_t src) {
+  return __riscv_vreinterpret_v_u64m1_b16(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_b16_u64m1
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv4i1(<vscale x 64 x i1> poison, <vscale x 4 x i1> [[SRC]], i64 0)
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 1 x i64>
+// CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP1]]
+//
+vuint64m1_t test_vreinterpret_v_b16_u64m1(vbool16_t src) {
+  return __riscv_vreinterpret_v_b16_u64m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vreinterpret_v_u64m1_b8
+// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i64> [[SRC]] to <vscale x 64 x i1>
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 8 x i1> @llvm.vector.extract.nxv8i1.nxv64i1(<vscale x 64 x i1> [[TMP0]], i64 0)
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i1> [[TMP1]]
+//
+vbool8_t test_vreinterpret_v_u64m1_b8(vuint64m1_t src) {
+  return __riscv_vreinterpret_v_u64m1_b8(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_b8_u64m1
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.vector.insert.nxv64i1.nxv8i1(<vscale x 64 x i1> poison, <vscale x 8 x i1> [[SRC]], i64 0)
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 64 x i1> [[TMP0]] to <vscale x 1 x i64>
+// CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP1]]
+//
+vuint64m1_t test_vreinterpret_v_b8_u64m1(vbool8_t src) {
+  return __riscv_vreinterpret_v_b8_u64m1(src);
+}
diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/misc/wrappers/vreinterpret_iuf.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/misc/wrappers/vreinterpret_iuf.c
index 8fb6e6b32ccfa9..b5884c5cbc441e 100644
--- a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/misc/wrappers/vreinterpret_iuf.c
+++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/misc/wrappers/vreinterpret_iuf.c
@@ -6,10 +6,6 @@
 
 #include <riscv_vector.h>
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_i8m1_u8m1
-// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[SRC]]
 // CHECK-IR-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_i8m1_u8m1
 // CHECK-IR-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0:[0-9]+]] {
 // CHECK-IR-NEXT:  entry:
@@ -19,10 +15,6 @@ vuint8m1_t test_vreinterpret_v_i8m1_u8m1(vint8m1_t src) {
   return __riscv_vreinterpret_v_i8m1_u8m1(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vreinterpret_v_i8m2_u8m2
-// CHECK-RV64-SAME: (<vscale x 16 x i8> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 16 x i8> [[SRC]]
 // CHECK-IR-LABEL: define dso_local <vscale x 16 x i8> @test_vreinterpret_v_i8m2_u8m2
 // CHECK-IR-SAME: (<vscale x 16 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -32,10 +24,6 @@ vuint8m2_t test_vreinterpret_v_i8m2_u8m2(vint8m2_t src) {
   return __riscv_vreinterpret_v_i8m2_u8m2(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vreinterpret_v_i8m4_u8m4
-// CHECK-RV64-SAME: (<vscale x 32 x i8> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 32 x i8> [[SRC]]
 // CHECK-IR-LABEL: define dso_local <vscale x 32 x i8> @test_vreinterpret_v_i8m4_u8m4
 // CHECK-IR-SAME: (<vscale x 32 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -45,10 +33,6 @@ vuint8m4_t test_vreinterpret_v_i8m4_u8m4(vint8m4_t src) {
   return __riscv_vreinterpret_v_i8m4_u8m4(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vreinterpret_v_i8m8_u8m8
-// CHECK-RV64-SAME: (<vscale x 64 x i8> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 64 x i8> [[SRC]]
 // CHECK-IR-LABEL: define dso_local <vscale x 64 x i8> @test_vreinterpret_v_i8m8_u8m8
 // CHECK-IR-SAME: (<vscale x 64 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -58,10 +42,6 @@ vuint8m8_t test_vreinterpret_v_i8m8_u8m8(vint8m8_t src) {
   return __riscv_vreinterpret_v_i8m8_u8m8(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_u8m1_i8m1
-// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[SRC]]
 // CHECK-IR-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_u8m1_i8m1
 // CHECK-IR-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -71,10 +51,6 @@ vint8m1_t test_vreinterpret_v_u8m1_i8m1(vuint8m1_t src) {
   return __riscv_vreinterpret_v_u8m1_i8m1(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vreinterpret_v_u8m2_i8m2
-// CHECK-RV64-SAME: (<vscale x 16 x i8> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 16 x i8> [[SRC]]
 // CHECK-IR-LABEL: define dso_local <vscale x 16 x i8> @test_vreinterpret_v_u8m2_i8m2
 // CHECK-IR-SAME: (<vscale x 16 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -84,10 +60,6 @@ vint8m2_t test_vreinterpret_v_u8m2_i8m2(vuint8m2_t src) {
   return __riscv_vreinterpret_v_u8m2_i8m2(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vreinterpret_v_u8m4_i8m4
-// CHECK-RV64-SAME: (<vscale x 32 x i8> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 32 x i8> [[SRC]]
 // CHECK-IR-LABEL: define dso_local <vscale x 32 x i8> @test_vreinterpret_v_u8m4_i8m4
 // CHECK-IR-SAME: (<vscale x 32 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -97,10 +69,6 @@ vint8m4_t test_vreinterpret_v_u8m4_i8m4(vuint8m4_t src) {
   return __riscv_vreinterpret_v_u8m4_i8m4(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vreinterpret_v_u8m8_i8m8
-// CHECK-RV64-SAME: (<vscale x 64 x i8> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 64 x i8> [[SRC]]
 // CHECK-IR-LABEL: define dso_local <vscale x 64 x i8> @test_vreinterpret_v_u8m8_i8m8
 // CHECK-IR-SAME: (<vscale x 64 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -110,11 +78,6 @@ vint8m8_t test_vreinterpret_v_u8m8_i8m8(vuint8m8_t src) {
   return __riscv_vreinterpret_v_u8m8_i8m8(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vreinterpret_v_i16m1_f16m1
-// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC]] to <vscale x 4 x half>
-// CHECK-RV64-NEXT:    ret <vscale x 4 x half> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 4 x half> @test_vreinterpret_v_i16m1_f16m1
 // CHECK-IR-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -125,11 +88,6 @@ vfloat16m1_t test_vreinterpret_v_i16m1_f16m1(vint16m1_t src) {
   return __riscv_vreinterpret_v_i16m1_f16m1(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vreinterpret_v_i16m2_f16m2
-// CHECK-RV64-SAME: (<vscale x 8 x i16> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i16> [[SRC]] to <vscale x 8 x half>
-// CHECK-RV64-NEXT:    ret <vscale x 8 x half> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 8 x half> @test_vreinterpret_v_i16m2_f16m2
 // CHECK-IR-SAME: (<vscale x 8 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -140,11 +98,6 @@ vfloat16m2_t test_vreinterpret_v_i16m2_f16m2(vint16m2_t src) {
   return __riscv_vreinterpret_v_i16m2_f16m2(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vreinterpret_v_i16m4_f16m4
-// CHECK-RV64-SAME: (<vscale x 16 x i16> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i16> [[SRC]] to <vscale x 16 x half>
-// CHECK-RV64-NEXT:    ret <vscale x 16 x half> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 16 x half> @test_vreinterpret_v_i16m4_f16m4
 // CHECK-IR-SAME: (<vscale x 16 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -155,11 +108,6 @@ vfloat16m4_t test_vreinterpret_v_i16m4_f16m4(vint16m4_t src) {
   return __riscv_vreinterpret_v_i16m4_f16m4(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vreinterpret_v_i16m8_f16m8
-// CHECK-RV64-SAME: (<vscale x 32 x i16> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x i16> [[SRC]] to <vscale x 32 x half>
-// CHECK-RV64-NEXT:    ret <vscale x 32 x half> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 32 x half> @test_vreinterpret_v_i16m8_f16m8
 // CHECK-IR-SAME: (<vscale x 32 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -170,11 +118,6 @@ vfloat16m8_t test_vreinterpret_v_i16m8_f16m8(vint16m8_t src) {
   return __riscv_vreinterpret_v_i16m8_f16m8(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vreinterpret_v_u16m1_f16m1
-// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC]] to <vscale x 4 x half>
-// CHECK-RV64-NEXT:    ret <vscale x 4 x half> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 4 x half> @test_vreinterpret_v_u16m1_f16m1
 // CHECK-IR-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -185,11 +128,6 @@ vfloat16m1_t test_vreinterpret_v_u16m1_f16m1(vuint16m1_t src) {
   return __riscv_vreinterpret_v_u16m1_f16m1(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vreinterpret_v_u16m2_f16m2
-// CHECK-RV64-SAME: (<vscale x 8 x i16> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i16> [[SRC]] to <vscale x 8 x half>
-// CHECK-RV64-NEXT:    ret <vscale x 8 x half> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 8 x half> @test_vreinterpret_v_u16m2_f16m2
 // CHECK-IR-SAME: (<vscale x 8 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -200,11 +138,6 @@ vfloat16m2_t test_vreinterpret_v_u16m2_f16m2(vuint16m2_t src) {
   return __riscv_vreinterpret_v_u16m2_f16m2(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vreinterpret_v_u16m4_f16m4
-// CHECK-RV64-SAME: (<vscale x 16 x i16> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i16> [[SRC]] to <vscale x 16 x half>
-// CHECK-RV64-NEXT:    ret <vscale x 16 x half> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 16 x half> @test_vreinterpret_v_u16m4_f16m4
 // CHECK-IR-SAME: (<vscale x 16 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -215,11 +148,6 @@ vfloat16m4_t test_vreinterpret_v_u16m4_f16m4(vuint16m4_t src) {
   return __riscv_vreinterpret_v_u16m4_f16m4(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vreinterpret_v_u16m8_f16m8
-// CHECK-RV64-SAME: (<vscale x 32 x i16> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x i16> [[SRC]] to <vscale x 32 x half>
-// CHECK-RV64-NEXT:    ret <vscale x 32 x half> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 32 x half> @test_vreinterpret_v_u16m8_f16m8
 // CHECK-IR-SAME: (<vscale x 32 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -230,10 +158,6 @@ vfloat16m8_t test_vreinterpret_v_u16m8_f16m8(vuint16m8_t src) {
   return __riscv_vreinterpret_v_u16m8_f16m8(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_i16m1_u16m1
-// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[SRC]]
 // CHECK-IR-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_i16m1_u16m1
 // CHECK-IR-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -243,10 +167,6 @@ vuint16m1_t test_vreinterpret_v_i16m1_u16m1(vint16m1_t src) {
   return __riscv_vreinterpret_v_i16m1_u16m1(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vreinterpret_v_i16m2_u16m2
-// CHECK-RV64-SAME: (<vscale x 8 x i16> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[SRC]]
 // CHECK-IR-LABEL: define dso_local <vscale x 8 x i16> @test_vreinterpret_v_i16m2_u16m2
 // CHECK-IR-SAME: (<vscale x 8 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -256,10 +176,6 @@ vuint16m2_t test_vreinterpret_v_i16m2_u16m2(vint16m2_t src) {
   return __riscv_vreinterpret_v_i16m2_u16m2(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vreinterpret_v_i16m4_u16m4
-// CHECK-RV64-SAME: (<vscale x 16 x i16> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[SRC]]
 // CHECK-IR-LABEL: define dso_local <vscale x 16 x i16> @test_vreinterpret_v_i16m4_u16m4
 // CHECK-IR-SAME: (<vscale x 16 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -269,10 +185,6 @@ vuint16m4_t test_vreinterpret_v_i16m4_u16m4(vint16m4_t src) {
   return __riscv_vreinterpret_v_i16m4_u16m4(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vreinterpret_v_i16m8_u16m8
-// CHECK-RV64-SAME: (<vscale x 32 x i16> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[SRC]]
 // CHECK-IR-LABEL: define dso_local <vscale x 32 x i16> @test_vreinterpret_v_i16m8_u16m8
 // CHECK-IR-SAME: (<vscale x 32 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -282,10 +194,6 @@ vuint16m8_t test_vreinterpret_v_i16m8_u16m8(vint16m8_t src) {
   return __riscv_vreinterpret_v_i16m8_u16m8(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_u16m1_i16m1
-// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[SRC]]
 // CHECK-IR-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_u16m1_i16m1
 // CHECK-IR-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -295,10 +203,6 @@ vint16m1_t test_vreinterpret_v_u16m1_i16m1(vuint16m1_t src) {
   return __riscv_vreinterpret_v_u16m1_i16m1(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vreinterpret_v_u16m2_i16m2
-// CHECK-RV64-SAME: (<vscale x 8 x i16> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[SRC]]
 // CHECK-IR-LABEL: define dso_local <vscale x 8 x i16> @test_vreinterpret_v_u16m2_i16m2
 // CHECK-IR-SAME: (<vscale x 8 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -308,10 +212,6 @@ vint16m2_t test_vreinterpret_v_u16m2_i16m2(vuint16m2_t src) {
   return __riscv_vreinterpret_v_u16m2_i16m2(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vreinterpret_v_u16m4_i16m4
-// CHECK-RV64-SAME: (<vscale x 16 x i16> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[SRC]]
 // CHECK-IR-LABEL: define dso_local <vscale x 16 x i16> @test_vreinterpret_v_u16m4_i16m4
 // CHECK-IR-SAME: (<vscale x 16 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -321,10 +221,6 @@ vint16m4_t test_vreinterpret_v_u16m4_i16m4(vuint16m4_t src) {
   return __riscv_vreinterpret_v_u16m4_i16m4(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vreinterpret_v_u16m8_i16m8
-// CHECK-RV64-SAME: (<vscale x 32 x i16> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[SRC]]
 // CHECK-IR-LABEL: define dso_local <vscale x 32 x i16> @test_vreinterpret_v_u16m8_i16m8
 // CHECK-IR-SAME: (<vscale x 32 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -334,11 +230,6 @@ vint16m8_t test_vreinterpret_v_u16m8_i16m8(vuint16m8_t src) {
   return __riscv_vreinterpret_v_u16m8_i16m8(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_f16m1_i16m1
-// CHECK-RV64-SAME: (<vscale x 4 x half> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x half> [[SRC]] to <vscale x 4 x i16>
-// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_f16m1_i16m1
 // CHECK-IR-SAME: (<vscale x 4 x half> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -349,11 +240,6 @@ vint16m1_t test_vreinterpret_v_f16m1_i16m1(vfloat16m1_t src) {
   return __riscv_vreinterpret_v_f16m1_i16m1(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vreinterpret_v_f16m2_i16m2
-// CHECK-RV64-SAME: (<vscale x 8 x half> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x half> [[SRC]] to <vscale x 8 x i16>
-// CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 8 x i16> @test_vreinterpret_v_f16m2_i16m2
 // CHECK-IR-SAME: (<vscale x 8 x half> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -364,11 +250,6 @@ vint16m2_t test_vreinterpret_v_f16m2_i16m2(vfloat16m2_t src) {
   return __riscv_vreinterpret_v_f16m2_i16m2(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vreinterpret_v_f16m4_i16m4
-// CHECK-RV64-SAME: (<vscale x 16 x half> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x half> [[SRC]] to <vscale x 16 x i16>
-// CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 16 x i16> @test_vreinterpret_v_f16m4_i16m4
 // CHECK-IR-SAME: (<vscale x 16 x half> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -379,11 +260,6 @@ vint16m4_t test_vreinterpret_v_f16m4_i16m4(vfloat16m4_t src) {
   return __riscv_vreinterpret_v_f16m4_i16m4(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vreinterpret_v_f16m8_i16m8
-// CHECK-RV64-SAME: (<vscale x 32 x half> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x half> [[SRC]] to <vscale x 32 x i16>
-// CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 32 x i16> @test_vreinterpret_v_f16m8_i16m8
 // CHECK-IR-SAME: (<vscale x 32 x half> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -394,11 +270,6 @@ vint16m8_t test_vreinterpret_v_f16m8_i16m8(vfloat16m8_t src) {
   return __riscv_vreinterpret_v_f16m8_i16m8(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_f16m1_u16m1
-// CHECK-RV64-SAME: (<vscale x 4 x half> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x half> [[SRC]] to <vscale x 4 x i16>
-// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_f16m1_u16m1
 // CHECK-IR-SAME: (<vscale x 4 x half> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -409,11 +280,6 @@ vuint16m1_t test_vreinterpret_v_f16m1_u16m1(vfloat16m1_t src) {
   return __riscv_vreinterpret_v_f16m1_u16m1(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vreinterpret_v_f16m2_u16m2
-// CHECK-RV64-SAME: (<vscale x 8 x half> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x half> [[SRC]] to <vscale x 8 x i16>
-// CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 8 x i16> @test_vreinterpret_v_f16m2_u16m2
 // CHECK-IR-SAME: (<vscale x 8 x half> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -424,11 +290,6 @@ vuint16m2_t test_vreinterpret_v_f16m2_u16m2(vfloat16m2_t src) {
   return __riscv_vreinterpret_v_f16m2_u16m2(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vreinterpret_v_f16m4_u16m4
-// CHECK-RV64-SAME: (<vscale x 16 x half> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x half> [[SRC]] to <vscale x 16 x i16>
-// CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 16 x i16> @test_vreinterpret_v_f16m4_u16m4
 // CHECK-IR-SAME: (<vscale x 16 x half> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -439,11 +300,6 @@ vuint16m4_t test_vreinterpret_v_f16m4_u16m4(vfloat16m4_t src) {
   return __riscv_vreinterpret_v_f16m4_u16m4(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vreinterpret_v_f16m8_u16m8
-// CHECK-RV64-SAME: (<vscale x 32 x half> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x half> [[SRC]] to <vscale x 32 x i16>
-// CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 32 x i16> @test_vreinterpret_v_f16m8_u16m8
 // CHECK-IR-SAME: (<vscale x 32 x half> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -454,11 +310,6 @@ vuint16m8_t test_vreinterpret_v_f16m8_u16m8(vfloat16m8_t src) {
   return __riscv_vreinterpret_v_f16m8_u16m8(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vreinterpret_v_i32m1_f32m1
-// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i32> [[SRC]] to <vscale x 2 x float>
-// CHECK-RV64-NEXT:    ret <vscale x 2 x float> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 2 x float> @test_vreinterpret_v_i32m1_f32m1
 // CHECK-IR-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -469,11 +320,6 @@ vfloat32m1_t test_vreinterpret_v_i32m1_f32m1(vint32m1_t src) {
   return __riscv_vreinterpret_v_i32m1_f32m1(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vreinterpret_v_i32m2_f32m2
-// CHECK-RV64-SAME: (<vscale x 4 x i32> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i32> [[SRC]] to <vscale x 4 x float>
-// CHECK-RV64-NEXT:    ret <vscale x 4 x float> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 4 x float> @test_vreinterpret_v_i32m2_f32m2
 // CHECK-IR-SAME: (<vscale x 4 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -484,11 +330,6 @@ vfloat32m2_t test_vreinterpret_v_i32m2_f32m2(vint32m2_t src) {
   return __riscv_vreinterpret_v_i32m2_f32m2(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vreinterpret_v_i32m4_f32m4
-// CHECK-RV64-SAME: (<vscale x 8 x i32> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i32> [[SRC]] to <vscale x 8 x float>
-// CHECK-RV64-NEXT:    ret <vscale x 8 x float> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 8 x float> @test_vreinterpret_v_i32m4_f32m4
 // CHECK-IR-SAME: (<vscale x 8 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -499,11 +340,6 @@ vfloat32m4_t test_vreinterpret_v_i32m4_f32m4(vint32m4_t src) {
   return __riscv_vreinterpret_v_i32m4_f32m4(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vreinterpret_v_i32m8_f32m8
-// CHECK-RV64-SAME: (<vscale x 16 x i32> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i32> [[SRC]] to <vscale x 16 x float>
-// CHECK-RV64-NEXT:    ret <vscale x 16 x float> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 16 x float> @test_vreinterpret_v_i32m8_f32m8
 // CHECK-IR-SAME: (<vscale x 16 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -514,11 +350,6 @@ vfloat32m8_t test_vreinterpret_v_i32m8_f32m8(vint32m8_t src) {
   return __riscv_vreinterpret_v_i32m8_f32m8(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vreinterpret_v_u32m1_f32m1
-// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i32> [[SRC]] to <vscale x 2 x float>
-// CHECK-RV64-NEXT:    ret <vscale x 2 x float> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 2 x float> @test_vreinterpret_v_u32m1_f32m1
 // CHECK-IR-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -529,11 +360,6 @@ vfloat32m1_t test_vreinterpret_v_u32m1_f32m1(vuint32m1_t src) {
   return __riscv_vreinterpret_v_u32m1_f32m1(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vreinterpret_v_u32m2_f32m2
-// CHECK-RV64-SAME: (<vscale x 4 x i32> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i32> [[SRC]] to <vscale x 4 x float>
-// CHECK-RV64-NEXT:    ret <vscale x 4 x float> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 4 x float> @test_vreinterpret_v_u32m2_f32m2
 // CHECK-IR-SAME: (<vscale x 4 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -544,11 +370,6 @@ vfloat32m2_t test_vreinterpret_v_u32m2_f32m2(vuint32m2_t src) {
   return __riscv_vreinterpret_v_u32m2_f32m2(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vreinterpret_v_u32m4_f32m4
-// CHECK-RV64-SAME: (<vscale x 8 x i32> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i32> [[SRC]] to <vscale x 8 x float>
-// CHECK-RV64-NEXT:    ret <vscale x 8 x float> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 8 x float> @test_vreinterpret_v_u32m4_f32m4
 // CHECK-IR-SAME: (<vscale x 8 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -559,11 +380,6 @@ vfloat32m4_t test_vreinterpret_v_u32m4_f32m4(vuint32m4_t src) {
   return __riscv_vreinterpret_v_u32m4_f32m4(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vreinterpret_v_u32m8_f32m8
-// CHECK-RV64-SAME: (<vscale x 16 x i32> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i32> [[SRC]] to <vscale x 16 x float>
-// CHECK-RV64-NEXT:    ret <vscale x 16 x float> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 16 x float> @test_vreinterpret_v_u32m8_f32m8
 // CHECK-IR-SAME: (<vscale x 16 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -574,10 +390,6 @@ vfloat32m8_t test_vreinterpret_v_u32m8_f32m8(vuint32m8_t src) {
   return __riscv_vreinterpret_v_u32m8_f32m8(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_i32m1_u32m1
-// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[SRC]]
 // CHECK-IR-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_i32m1_u32m1
 // CHECK-IR-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -587,10 +399,6 @@ vuint32m1_t test_vreinterpret_v_i32m1_u32m1(vint32m1_t src) {
   return __riscv_vreinterpret_v_i32m1_u32m1(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vreinterpret_v_i32m2_u32m2
-// CHECK-RV64-SAME: (<vscale x 4 x i32> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[SRC]]
 // CHECK-IR-LABEL: define dso_local <vscale x 4 x i32> @test_vreinterpret_v_i32m2_u32m2
 // CHECK-IR-SAME: (<vscale x 4 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -600,10 +408,6 @@ vuint32m2_t test_vreinterpret_v_i32m2_u32m2(vint32m2_t src) {
   return __riscv_vreinterpret_v_i32m2_u32m2(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vreinterpret_v_i32m4_u32m4
-// CHECK-RV64-SAME: (<vscale x 8 x i32> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[SRC]]
 // CHECK-IR-LABEL: define dso_local <vscale x 8 x i32> @test_vreinterpret_v_i32m4_u32m4
 // CHECK-IR-SAME: (<vscale x 8 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -613,10 +417,6 @@ vuint32m4_t test_vreinterpret_v_i32m4_u32m4(vint32m4_t src) {
   return __riscv_vreinterpret_v_i32m4_u32m4(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vreinterpret_v_i32m8_u32m8
-// CHECK-RV64-SAME: (<vscale x 16 x i32> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[SRC]]
 // CHECK-IR-LABEL: define dso_local <vscale x 16 x i32> @test_vreinterpret_v_i32m8_u32m8
 // CHECK-IR-SAME: (<vscale x 16 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -626,10 +426,6 @@ vuint32m8_t test_vreinterpret_v_i32m8_u32m8(vint32m8_t src) {
   return __riscv_vreinterpret_v_i32m8_u32m8(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_u32m1_i32m1
-// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[SRC]]
 // CHECK-IR-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_u32m1_i32m1
 // CHECK-IR-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -639,10 +435,6 @@ vint32m1_t test_vreinterpret_v_u32m1_i32m1(vuint32m1_t src) {
   return __riscv_vreinterpret_v_u32m1_i32m1(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vreinterpret_v_u32m2_i32m2
-// CHECK-RV64-SAME: (<vscale x 4 x i32> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[SRC]]
 // CHECK-IR-LABEL: define dso_local <vscale x 4 x i32> @test_vreinterpret_v_u32m2_i32m2
 // CHECK-IR-SAME: (<vscale x 4 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -652,10 +444,6 @@ vint32m2_t test_vreinterpret_v_u32m2_i32m2(vuint32m2_t src) {
   return __riscv_vreinterpret_v_u32m2_i32m2(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vreinterpret_v_u32m4_i32m4
-// CHECK-RV64-SAME: (<vscale x 8 x i32> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[SRC]]
 // CHECK-IR-LABEL: define dso_local <vscale x 8 x i32> @test_vreinterpret_v_u32m4_i32m4
 // CHECK-IR-SAME: (<vscale x 8 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -665,10 +453,6 @@ vint32m4_t test_vreinterpret_v_u32m4_i32m4(vuint32m4_t src) {
   return __riscv_vreinterpret_v_u32m4_i32m4(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vreinterpret_v_u32m8_i32m8
-// CHECK-RV64-SAME: (<vscale x 16 x i32> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[SRC]]
 // CHECK-IR-LABEL: define dso_local <vscale x 16 x i32> @test_vreinterpret_v_u32m8_i32m8
 // CHECK-IR-SAME: (<vscale x 16 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -678,11 +462,6 @@ vint32m8_t test_vreinterpret_v_u32m8_i32m8(vuint32m8_t src) {
   return __riscv_vreinterpret_v_u32m8_i32m8(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_f32m1_i32m1
-// CHECK-RV64-SAME: (<vscale x 2 x float> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x float> [[SRC]] to <vscale x 2 x i32>
-// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_f32m1_i32m1
 // CHECK-IR-SAME: (<vscale x 2 x float> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -693,11 +472,6 @@ vint32m1_t test_vreinterpret_v_f32m1_i32m1(vfloat32m1_t src) {
   return __riscv_vreinterpret_v_f32m1_i32m1(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vreinterpret_v_f32m2_i32m2
-// CHECK-RV64-SAME: (<vscale x 4 x float> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x float> [[SRC]] to <vscale x 4 x i32>
-// CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 4 x i32> @test_vreinterpret_v_f32m2_i32m2
 // CHECK-IR-SAME: (<vscale x 4 x float> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -708,11 +482,6 @@ vint32m2_t test_vreinterpret_v_f32m2_i32m2(vfloat32m2_t src) {
   return __riscv_vreinterpret_v_f32m2_i32m2(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vreinterpret_v_f32m4_i32m4
-// CHECK-RV64-SAME: (<vscale x 8 x float> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x float> [[SRC]] to <vscale x 8 x i32>
-// CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 8 x i32> @test_vreinterpret_v_f32m4_i32m4
 // CHECK-IR-SAME: (<vscale x 8 x float> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -723,11 +492,6 @@ vint32m4_t test_vreinterpret_v_f32m4_i32m4(vfloat32m4_t src) {
   return __riscv_vreinterpret_v_f32m4_i32m4(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vreinterpret_v_f32m8_i32m8
-// CHECK-RV64-SAME: (<vscale x 16 x float> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x float> [[SRC]] to <vscale x 16 x i32>
-// CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 16 x i32> @test_vreinterpret_v_f32m8_i32m8
 // CHECK-IR-SAME: (<vscale x 16 x float> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -738,11 +502,6 @@ vint32m8_t test_vreinterpret_v_f32m8_i32m8(vfloat32m8_t src) {
   return __riscv_vreinterpret_v_f32m8_i32m8(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_f32m1_u32m1
-// CHECK-RV64-SAME: (<vscale x 2 x float> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x float> [[SRC]] to <vscale x 2 x i32>
-// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_f32m1_u32m1
 // CHECK-IR-SAME: (<vscale x 2 x float> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -753,11 +512,6 @@ vuint32m1_t test_vreinterpret_v_f32m1_u32m1(vfloat32m1_t src) {
   return __riscv_vreinterpret_v_f32m1_u32m1(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vreinterpret_v_f32m2_u32m2
-// CHECK-RV64-SAME: (<vscale x 4 x float> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x float> [[SRC]] to <vscale x 4 x i32>
-// CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 4 x i32> @test_vreinterpret_v_f32m2_u32m2
 // CHECK-IR-SAME: (<vscale x 4 x float> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -768,11 +522,6 @@ vuint32m2_t test_vreinterpret_v_f32m2_u32m2(vfloat32m2_t src) {
   return __riscv_vreinterpret_v_f32m2_u32m2(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vreinterpret_v_f32m4_u32m4
-// CHECK-RV64-SAME: (<vscale x 8 x float> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x float> [[SRC]] to <vscale x 8 x i32>
-// CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 8 x i32> @test_vreinterpret_v_f32m4_u32m4
 // CHECK-IR-SAME: (<vscale x 8 x float> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -783,11 +532,6 @@ vuint32m4_t test_vreinterpret_v_f32m4_u32m4(vfloat32m4_t src) {
   return __riscv_vreinterpret_v_f32m4_u32m4(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vreinterpret_v_f32m8_u32m8
-// CHECK-RV64-SAME: (<vscale x 16 x float> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x float> [[SRC]] to <vscale x 16 x i32>
-// CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 16 x i32> @test_vreinterpret_v_f32m8_u32m8
 // CHECK-IR-SAME: (<vscale x 16 x float> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -798,11 +542,6 @@ vuint32m8_t test_vreinterpret_v_f32m8_u32m8(vfloat32m8_t src) {
   return __riscv_vreinterpret_v_f32m8_u32m8(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vreinterpret_v_i64m1_f64m1
-// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i64> [[SRC]] to <vscale x 1 x double>
-// CHECK-RV64-NEXT:    ret <vscale x 1 x double> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 1 x double> @test_vreinterpret_v_i64m1_f64m1
 // CHECK-IR-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -813,11 +552,6 @@ vfloat64m1_t test_vreinterpret_v_i64m1_f64m1(vint64m1_t src) {
   return __riscv_vreinterpret_v_i64m1_f64m1(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vreinterpret_v_i64m2_f64m2
-// CHECK-RV64-SAME: (<vscale x 2 x i64> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i64> [[SRC]] to <vscale x 2 x double>
-// CHECK-RV64-NEXT:    ret <vscale x 2 x double> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 2 x double> @test_vreinterpret_v_i64m2_f64m2
 // CHECK-IR-SAME: (<vscale x 2 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -828,11 +562,6 @@ vfloat64m2_t test_vreinterpret_v_i64m2_f64m2(vint64m2_t src) {
   return __riscv_vreinterpret_v_i64m2_f64m2(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vreinterpret_v_i64m4_f64m4
-// CHECK-RV64-SAME: (<vscale x 4 x i64> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i64> [[SRC]] to <vscale x 4 x double>
-// CHECK-RV64-NEXT:    ret <vscale x 4 x double> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 4 x double> @test_vreinterpret_v_i64m4_f64m4
 // CHECK-IR-SAME: (<vscale x 4 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -843,11 +572,6 @@ vfloat64m4_t test_vreinterpret_v_i64m4_f64m4(vint64m4_t src) {
   return __riscv_vreinterpret_v_i64m4_f64m4(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vreinterpret_v_i64m8_f64m8
-// CHECK-RV64-SAME: (<vscale x 8 x i64> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i64> [[SRC]] to <vscale x 8 x double>
-// CHECK-RV64-NEXT:    ret <vscale x 8 x double> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 8 x double> @test_vreinterpret_v_i64m8_f64m8
 // CHECK-IR-SAME: (<vscale x 8 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -858,11 +582,6 @@ vfloat64m8_t test_vreinterpret_v_i64m8_f64m8(vint64m8_t src) {
   return __riscv_vreinterpret_v_i64m8_f64m8(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vreinterpret_v_u64m1_f64m1
-// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i64> [[SRC]] to <vscale x 1 x double>
-// CHECK-RV64-NEXT:    ret <vscale x 1 x double> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 1 x double> @test_vreinterpret_v_u64m1_f64m1
 // CHECK-IR-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -873,11 +592,6 @@ vfloat64m1_t test_vreinterpret_v_u64m1_f64m1(vuint64m1_t src) {
   return __riscv_vreinterpret_v_u64m1_f64m1(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vreinterpret_v_u64m2_f64m2
-// CHECK-RV64-SAME: (<vscale x 2 x i64> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i64> [[SRC]] to <vscale x 2 x double>
-// CHECK-RV64-NEXT:    ret <vscale x 2 x double> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 2 x double> @test_vreinterpret_v_u64m2_f64m2
 // CHECK-IR-SAME: (<vscale x 2 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -888,11 +602,6 @@ vfloat64m2_t test_vreinterpret_v_u64m2_f64m2(vuint64m2_t src) {
   return __riscv_vreinterpret_v_u64m2_f64m2(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vreinterpret_v_u64m4_f64m4
-// CHECK-RV64-SAME: (<vscale x 4 x i64> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i64> [[SRC]] to <vscale x 4 x double>
-// CHECK-RV64-NEXT:    ret <vscale x 4 x double> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 4 x double> @test_vreinterpret_v_u64m4_f64m4
 // CHECK-IR-SAME: (<vscale x 4 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -903,11 +612,6 @@ vfloat64m4_t test_vreinterpret_v_u64m4_f64m4(vuint64m4_t src) {
   return __riscv_vreinterpret_v_u64m4_f64m4(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vreinterpret_v_u64m8_f64m8
-// CHECK-RV64-SAME: (<vscale x 8 x i64> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i64> [[SRC]] to <vscale x 8 x double>
-// CHECK-RV64-NEXT:    ret <vscale x 8 x double> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 8 x double> @test_vreinterpret_v_u64m8_f64m8
 // CHECK-IR-SAME: (<vscale x 8 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -918,10 +622,6 @@ vfloat64m8_t test_vreinterpret_v_u64m8_f64m8(vuint64m8_t src) {
   return __riscv_vreinterpret_v_u64m8_f64m8(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_i64m1_u64m1
-// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[SRC]]
 // CHECK-IR-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_i64m1_u64m1
 // CHECK-IR-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -931,10 +631,6 @@ vuint64m1_t test_vreinterpret_v_i64m1_u64m1(vint64m1_t src) {
   return __riscv_vreinterpret_v_i64m1_u64m1(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vreinterpret_v_i64m2_u64m2
-// CHECK-RV64-SAME: (<vscale x 2 x i64> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[SRC]]
 // CHECK-IR-LABEL: define dso_local <vscale x 2 x i64> @test_vreinterpret_v_i64m2_u64m2
 // CHECK-IR-SAME: (<vscale x 2 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -944,10 +640,6 @@ vuint64m2_t test_vreinterpret_v_i64m2_u64m2(vint64m2_t src) {
   return __riscv_vreinterpret_v_i64m2_u64m2(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vreinterpret_v_i64m4_u64m4
-// CHECK-RV64-SAME: (<vscale x 4 x i64> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[SRC]]
 // CHECK-IR-LABEL: define dso_local <vscale x 4 x i64> @test_vreinterpret_v_i64m4_u64m4
 // CHECK-IR-SAME: (<vscale x 4 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -957,10 +649,6 @@ vuint64m4_t test_vreinterpret_v_i64m4_u64m4(vint64m4_t src) {
   return __riscv_vreinterpret_v_i64m4_u64m4(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vreinterpret_v_i64m8_u64m8
-// CHECK-RV64-SAME: (<vscale x 8 x i64> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[SRC]]
 // CHECK-IR-LABEL: define dso_local <vscale x 8 x i64> @test_vreinterpret_v_i64m8_u64m8
 // CHECK-IR-SAME: (<vscale x 8 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -970,10 +658,6 @@ vuint64m8_t test_vreinterpret_v_i64m8_u64m8(vint64m8_t src) {
   return __riscv_vreinterpret_v_i64m8_u64m8(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_u64m1_i64m1
-// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[SRC]]
 // CHECK-IR-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_u64m1_i64m1
 // CHECK-IR-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -983,10 +667,6 @@ vint64m1_t test_vreinterpret_v_u64m1_i64m1(vuint64m1_t src) {
   return __riscv_vreinterpret_v_u64m1_i64m1(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vreinterpret_v_u64m2_i64m2
-// CHECK-RV64-SAME: (<vscale x 2 x i64> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[SRC]]
 // CHECK-IR-LABEL: define dso_local <vscale x 2 x i64> @test_vreinterpret_v_u64m2_i64m2
 // CHECK-IR-SAME: (<vscale x 2 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -996,10 +676,6 @@ vint64m2_t test_vreinterpret_v_u64m2_i64m2(vuint64m2_t src) {
   return __riscv_vreinterpret_v_u64m2_i64m2(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vreinterpret_v_u64m4_i64m4
-// CHECK-RV64-SAME: (<vscale x 4 x i64> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[SRC]]
 // CHECK-IR-LABEL: define dso_local <vscale x 4 x i64> @test_vreinterpret_v_u64m4_i64m4
 // CHECK-IR-SAME: (<vscale x 4 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -1009,10 +685,6 @@ vint64m4_t test_vreinterpret_v_u64m4_i64m4(vuint64m4_t src) {
   return __riscv_vreinterpret_v_u64m4_i64m4(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vreinterpret_v_u64m8_i64m8
-// CHECK-RV64-SAME: (<vscale x 8 x i64> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[SRC]]
 // CHECK-IR-LABEL: define dso_local <vscale x 8 x i64> @test_vreinterpret_v_u64m8_i64m8
 // CHECK-IR-SAME: (<vscale x 8 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -1022,11 +694,6 @@ vint64m8_t test_vreinterpret_v_u64m8_i64m8(vuint64m8_t src) {
   return __riscv_vreinterpret_v_u64m8_i64m8(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_f64m1_i64m1
-// CHECK-RV64-SAME: (<vscale x 1 x double> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x double> [[SRC]] to <vscale x 1 x i64>
-// CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_f64m1_i64m1
 // CHECK-IR-SAME: (<vscale x 1 x double> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -1037,11 +704,6 @@ vint64m1_t test_vreinterpret_v_f64m1_i64m1(vfloat64m1_t src) {
   return __riscv_vreinterpret_v_f64m1_i64m1(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vreinterpret_v_f64m2_i64m2
-// CHECK-RV64-SAME: (<vscale x 2 x double> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x double> [[SRC]] to <vscale x 2 x i64>
-// CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 2 x i64> @test_vreinterpret_v_f64m2_i64m2
 // CHECK-IR-SAME: (<vscale x 2 x double> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -1052,11 +714,6 @@ vint64m2_t test_vreinterpret_v_f64m2_i64m2(vfloat64m2_t src) {
   return __riscv_vreinterpret_v_f64m2_i64m2(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vreinterpret_v_f64m4_i64m4
-// CHECK-RV64-SAME: (<vscale x 4 x double> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x double> [[SRC]] to <vscale x 4 x i64>
-// CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 4 x i64> @test_vreinterpret_v_f64m4_i64m4
 // CHECK-IR-SAME: (<vscale x 4 x double> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -1067,11 +724,6 @@ vint64m4_t test_vreinterpret_v_f64m4_i64m4(vfloat64m4_t src) {
   return __riscv_vreinterpret_v_f64m4_i64m4(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vreinterpret_v_f64m8_i64m8
-// CHECK-RV64-SAME: (<vscale x 8 x double> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x double> [[SRC]] to <vscale x 8 x i64>
-// CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 8 x i64> @test_vreinterpret_v_f64m8_i64m8
 // CHECK-IR-SAME: (<vscale x 8 x double> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -1082,11 +734,6 @@ vint64m8_t test_vreinterpret_v_f64m8_i64m8(vfloat64m8_t src) {
   return __riscv_vreinterpret_v_f64m8_i64m8(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_f64m1_u64m1
-// CHECK-RV64-SAME: (<vscale x 1 x double> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x double> [[SRC]] to <vscale x 1 x i64>
-// CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_f64m1_u64m1
 // CHECK-IR-SAME: (<vscale x 1 x double> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -1097,11 +744,6 @@ vuint64m1_t test_vreinterpret_v_f64m1_u64m1(vfloat64m1_t src) {
   return __riscv_vreinterpret_v_f64m1_u64m1(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vreinterpret_v_f64m2_u64m2
-// CHECK-RV64-SAME: (<vscale x 2 x double> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x double> [[SRC]] to <vscale x 2 x i64>
-// CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 2 x i64> @test_vreinterpret_v_f64m2_u64m2
 // CHECK-IR-SAME: (<vscale x 2 x double> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -1112,11 +754,6 @@ vuint64m2_t test_vreinterpret_v_f64m2_u64m2(vfloat64m2_t src) {
   return __riscv_vreinterpret_v_f64m2_u64m2(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vreinterpret_v_f64m4_u64m4
-// CHECK-RV64-SAME: (<vscale x 4 x double> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x double> [[SRC]] to <vscale x 4 x i64>
-// CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 4 x i64> @test_vreinterpret_v_f64m4_u64m4
 // CHECK-IR-SAME: (<vscale x 4 x double> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
@@ -1127,11 +764,6 @@ vuint64m4_t test_vreinterpret_v_f64m4_u64m4(vfloat64m4_t src) {
   return __riscv_vreinterpret_v_f64m4_u64m4(src);
 }
 
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vreinterpret_v_f64m8_u64m8
-// CHECK-RV64-SAME: (<vscale x 8 x double> [[SRC:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x double> [[SRC]] to <vscale x 8 x i64>
-// CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
 // CHECK-IR-LABEL: define dso_local <vscale x 8 x i64> @test_vreinterpret_v_f64m8_u64m8
 // CHECK-IR-SAME: (<vscale x 8 x double> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-IR-NEXT:  entry:
diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/misc/wrappers/vreinterpret_sew.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/misc/wrappers/vreinterpret_sew.c
new file mode 100644
index 00000000000000..a959a439c70c1c
--- /dev/null
+++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/misc/wrappers/vreinterpret_sew.c
@@ -0,0 +1,967 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
+// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \
+// RUN:   -disable-O0-optnone -emit-llvm %s -o - | \
+// RUN:   opt -S -passes=mem2reg | \
+// RUN:   FileCheck --check-prefix=CHECK-IR %s
+
+#include <riscv_vector.h>
+
+// CHECK-IR-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_i8m1_i16m1
+// CHECK-IR-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i8> [[SRC]] to <vscale x 4 x i16>
+// CHECK-IR-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
+//
+vint16m1_t test_vreinterpret_v_i8m1_i16m1(vint8m1_t src) {
+  return __riscv_vreinterpret_v_i8m1_i16m1(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 8 x i16> @test_vreinterpret_v_i8m2_i16m2
+// CHECK-IR-SAME: (<vscale x 16 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i8> [[SRC]] to <vscale x 8 x i16>
+// CHECK-IR-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
+//
+vint16m2_t test_vreinterpret_v_i8m2_i16m2(vint8m2_t src) {
+  return __riscv_vreinterpret_v_i8m2_i16m2(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 16 x i16> @test_vreinterpret_v_i8m4_i16m4
+// CHECK-IR-SAME: (<vscale x 32 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x i8> [[SRC]] to <vscale x 16 x i16>
+// CHECK-IR-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
+//
+vint16m4_t test_vreinterpret_v_i8m4_i16m4(vint8m4_t src) {
+  return __riscv_vreinterpret_v_i8m4_i16m4(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 32 x i16> @test_vreinterpret_v_i8m8_i16m8
+// CHECK-IR-SAME: (<vscale x 64 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 64 x i8> [[SRC]] to <vscale x 32 x i16>
+// CHECK-IR-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
+//
+vint16m8_t test_vreinterpret_v_i8m8_i16m8(vint8m8_t src) {
+  return __riscv_vreinterpret_v_i8m8_i16m8(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_u8m1_u16m1
+// CHECK-IR-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i8> [[SRC]] to <vscale x 4 x i16>
+// CHECK-IR-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
+//
+vuint16m1_t test_vreinterpret_v_u8m1_u16m1(vuint8m1_t src) {
+  return __riscv_vreinterpret_v_u8m1_u16m1(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 8 x i16> @test_vreinterpret_v_u8m2_u16m2
+// CHECK-IR-SAME: (<vscale x 16 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i8> [[SRC]] to <vscale x 8 x i16>
+// CHECK-IR-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
+//
+vuint16m2_t test_vreinterpret_v_u8m2_u16m2(vuint8m2_t src) {
+  return __riscv_vreinterpret_v_u8m2_u16m2(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 16 x i16> @test_vreinterpret_v_u8m4_u16m4
+// CHECK-IR-SAME: (<vscale x 32 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x i8> [[SRC]] to <vscale x 16 x i16>
+// CHECK-IR-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
+//
+vuint16m4_t test_vreinterpret_v_u8m4_u16m4(vuint8m4_t src) {
+  return __riscv_vreinterpret_v_u8m4_u16m4(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 32 x i16> @test_vreinterpret_v_u8m8_u16m8
+// CHECK-IR-SAME: (<vscale x 64 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 64 x i8> [[SRC]] to <vscale x 32 x i16>
+// CHECK-IR-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
+//
+vuint16m8_t test_vreinterpret_v_u8m8_u16m8(vuint8m8_t src) {
+  return __riscv_vreinterpret_v_u8m8_u16m8(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_i8m1_i32m1
+// CHECK-IR-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i8> [[SRC]] to <vscale x 2 x i32>
+// CHECK-IR-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+vint32m1_t test_vreinterpret_v_i8m1_i32m1(vint8m1_t src) {
+  return __riscv_vreinterpret_v_i8m1_i32m1(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 4 x i32> @test_vreinterpret_v_i8m2_i32m2
+// CHECK-IR-SAME: (<vscale x 16 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i8> [[SRC]] to <vscale x 4 x i32>
+// CHECK-IR-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
+//
+vint32m2_t test_vreinterpret_v_i8m2_i32m2(vint8m2_t src) {
+  return __riscv_vreinterpret_v_i8m2_i32m2(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 8 x i32> @test_vreinterpret_v_i8m4_i32m4
+// CHECK-IR-SAME: (<vscale x 32 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x i8> [[SRC]] to <vscale x 8 x i32>
+// CHECK-IR-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
+//
+vint32m4_t test_vreinterpret_v_i8m4_i32m4(vint8m4_t src) {
+  return __riscv_vreinterpret_v_i8m4_i32m4(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 16 x i32> @test_vreinterpret_v_i8m8_i32m8
+// CHECK-IR-SAME: (<vscale x 64 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 64 x i8> [[SRC]] to <vscale x 16 x i32>
+// CHECK-IR-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
+//
+vint32m8_t test_vreinterpret_v_i8m8_i32m8(vint8m8_t src) {
+  return __riscv_vreinterpret_v_i8m8_i32m8(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_u8m1_u32m1
+// CHECK-IR-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i8> [[SRC]] to <vscale x 2 x i32>
+// CHECK-IR-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+vuint32m1_t test_vreinterpret_v_u8m1_u32m1(vuint8m1_t src) {
+  return __riscv_vreinterpret_v_u8m1_u32m1(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 4 x i32> @test_vreinterpret_v_u8m2_u32m2
+// CHECK-IR-SAME: (<vscale x 16 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i8> [[SRC]] to <vscale x 4 x i32>
+// CHECK-IR-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
+//
+vuint32m2_t test_vreinterpret_v_u8m2_u32m2(vuint8m2_t src) {
+  return __riscv_vreinterpret_v_u8m2_u32m2(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 8 x i32> @test_vreinterpret_v_u8m4_u32m4
+// CHECK-IR-SAME: (<vscale x 32 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x i8> [[SRC]] to <vscale x 8 x i32>
+// CHECK-IR-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
+//
+vuint32m4_t test_vreinterpret_v_u8m4_u32m4(vuint8m4_t src) {
+  return __riscv_vreinterpret_v_u8m4_u32m4(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 16 x i32> @test_vreinterpret_v_u8m8_u32m8
+// CHECK-IR-SAME: (<vscale x 64 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 64 x i8> [[SRC]] to <vscale x 16 x i32>
+// CHECK-IR-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
+//
+vuint32m8_t test_vreinterpret_v_u8m8_u32m8(vuint8m8_t src) {
+  return __riscv_vreinterpret_v_u8m8_u32m8(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_i8m1_i64m1
+// CHECK-IR-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i8> [[SRC]] to <vscale x 1 x i64>
+// CHECK-IR-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
+//
+vint64m1_t test_vreinterpret_v_i8m1_i64m1(vint8m1_t src) {
+  return __riscv_vreinterpret_v_i8m1_i64m1(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 2 x i64> @test_vreinterpret_v_i8m2_i64m2
+// CHECK-IR-SAME: (<vscale x 16 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i8> [[SRC]] to <vscale x 2 x i64>
+// CHECK-IR-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
+//
+vint64m2_t test_vreinterpret_v_i8m2_i64m2(vint8m2_t src) {
+  return __riscv_vreinterpret_v_i8m2_i64m2(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 4 x i64> @test_vreinterpret_v_i8m4_i64m4
+// CHECK-IR-SAME: (<vscale x 32 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x i8> [[SRC]] to <vscale x 4 x i64>
+// CHECK-IR-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
+//
+vint64m4_t test_vreinterpret_v_i8m4_i64m4(vint8m4_t src) {
+  return __riscv_vreinterpret_v_i8m4_i64m4(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 8 x i64> @test_vreinterpret_v_i8m8_i64m8
+// CHECK-IR-SAME: (<vscale x 64 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 64 x i8> [[SRC]] to <vscale x 8 x i64>
+// CHECK-IR-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
+//
+vint64m8_t test_vreinterpret_v_i8m8_i64m8(vint8m8_t src) {
+  return __riscv_vreinterpret_v_i8m8_i64m8(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_u8m1_u64m1
+// CHECK-IR-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i8> [[SRC]] to <vscale x 1 x i64>
+// CHECK-IR-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
+//
+vuint64m1_t test_vreinterpret_v_u8m1_u64m1(vuint8m1_t src) {
+  return __riscv_vreinterpret_v_u8m1_u64m1(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 2 x i64> @test_vreinterpret_v_u8m2_u64m2
+// CHECK-IR-SAME: (<vscale x 16 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i8> [[SRC]] to <vscale x 2 x i64>
+// CHECK-IR-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
+//
+vuint64m2_t test_vreinterpret_v_u8m2_u64m2(vuint8m2_t src) {
+  return __riscv_vreinterpret_v_u8m2_u64m2(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 4 x i64> @test_vreinterpret_v_u8m4_u64m4
+// CHECK-IR-SAME: (<vscale x 32 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x i8> [[SRC]] to <vscale x 4 x i64>
+// CHECK-IR-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
+//
+vuint64m4_t test_vreinterpret_v_u8m4_u64m4(vuint8m4_t src) {
+  return __riscv_vreinterpret_v_u8m4_u64m4(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 8 x i64> @test_vreinterpret_v_u8m8_u64m8
+// CHECK-IR-SAME: (<vscale x 64 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 64 x i8> [[SRC]] to <vscale x 8 x i64>
+// CHECK-IR-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
+//
+vuint64m8_t test_vreinterpret_v_u8m8_u64m8(vuint8m8_t src) {
+  return __riscv_vreinterpret_v_u8m8_u64m8(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_i16m1_i8m1
+// CHECK-IR-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC]] to <vscale x 8 x i8>
+// CHECK-IR-NEXT:    ret <vscale x 8 x i8> [[TMP0]]
+//
+vint8m1_t test_vreinterpret_v_i16m1_i8m1(vint16m1_t src) {
+  return __riscv_vreinterpret_v_i16m1_i8m1(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 16 x i8> @test_vreinterpret_v_i16m2_i8m2
+// CHECK-IR-SAME: (<vscale x 8 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i16> [[SRC]] to <vscale x 16 x i8>
+// CHECK-IR-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
+//
+vint8m2_t test_vreinterpret_v_i16m2_i8m2(vint16m2_t src) {
+  return __riscv_vreinterpret_v_i16m2_i8m2(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 32 x i8> @test_vreinterpret_v_i16m4_i8m4
+// CHECK-IR-SAME: (<vscale x 16 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i16> [[SRC]] to <vscale x 32 x i8>
+// CHECK-IR-NEXT:    ret <vscale x 32 x i8> [[TMP0]]
+//
+vint8m4_t test_vreinterpret_v_i16m4_i8m4(vint16m4_t src) {
+  return __riscv_vreinterpret_v_i16m4_i8m4(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 64 x i8> @test_vreinterpret_v_i16m8_i8m8
+// CHECK-IR-SAME: (<vscale x 32 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x i16> [[SRC]] to <vscale x 64 x i8>
+// CHECK-IR-NEXT:    ret <vscale x 64 x i8> [[TMP0]]
+//
+vint8m8_t test_vreinterpret_v_i16m8_i8m8(vint16m8_t src) {
+  return __riscv_vreinterpret_v_i16m8_i8m8(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_u16m1_u8m1
+// CHECK-IR-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC]] to <vscale x 8 x i8>
+// CHECK-IR-NEXT:    ret <vscale x 8 x i8> [[TMP0]]
+//
+vuint8m1_t test_vreinterpret_v_u16m1_u8m1(vuint16m1_t src) {
+  return __riscv_vreinterpret_v_u16m1_u8m1(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 16 x i8> @test_vreinterpret_v_u16m2_u8m2
+// CHECK-IR-SAME: (<vscale x 8 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i16> [[SRC]] to <vscale x 16 x i8>
+// CHECK-IR-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
+//
+vuint8m2_t test_vreinterpret_v_u16m2_u8m2(vuint16m2_t src) {
+  return __riscv_vreinterpret_v_u16m2_u8m2(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 32 x i8> @test_vreinterpret_v_u16m4_u8m4
+// CHECK-IR-SAME: (<vscale x 16 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i16> [[SRC]] to <vscale x 32 x i8>
+// CHECK-IR-NEXT:    ret <vscale x 32 x i8> [[TMP0]]
+//
+vuint8m4_t test_vreinterpret_v_u16m4_u8m4(vuint16m4_t src) {
+  return __riscv_vreinterpret_v_u16m4_u8m4(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 64 x i8> @test_vreinterpret_v_u16m8_u8m8
+// CHECK-IR-SAME: (<vscale x 32 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x i16> [[SRC]] to <vscale x 64 x i8>
+// CHECK-IR-NEXT:    ret <vscale x 64 x i8> [[TMP0]]
+//
+vuint8m8_t test_vreinterpret_v_u16m8_u8m8(vuint16m8_t src) {
+  return __riscv_vreinterpret_v_u16m8_u8m8(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_i16m1_i32m1
+// CHECK-IR-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC]] to <vscale x 2 x i32>
+// CHECK-IR-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+vint32m1_t test_vreinterpret_v_i16m1_i32m1(vint16m1_t src) {
+  return __riscv_vreinterpret_v_i16m1_i32m1(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 4 x i32> @test_vreinterpret_v_i16m2_i32m2
+// CHECK-IR-SAME: (<vscale x 8 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i16> [[SRC]] to <vscale x 4 x i32>
+// CHECK-IR-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
+//
+vint32m2_t test_vreinterpret_v_i16m2_i32m2(vint16m2_t src) {
+  return __riscv_vreinterpret_v_i16m2_i32m2(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 8 x i32> @test_vreinterpret_v_i16m4_i32m4
+// CHECK-IR-SAME: (<vscale x 16 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i16> [[SRC]] to <vscale x 8 x i32>
+// CHECK-IR-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
+//
+vint32m4_t test_vreinterpret_v_i16m4_i32m4(vint16m4_t src) {
+  return __riscv_vreinterpret_v_i16m4_i32m4(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 16 x i32> @test_vreinterpret_v_i16m8_i32m8
+// CHECK-IR-SAME: (<vscale x 32 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x i16> [[SRC]] to <vscale x 16 x i32>
+// CHECK-IR-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
+//
+vint32m8_t test_vreinterpret_v_i16m8_i32m8(vint16m8_t src) {
+  return __riscv_vreinterpret_v_i16m8_i32m8(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_u16m1_u32m1
+// CHECK-IR-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC]] to <vscale x 2 x i32>
+// CHECK-IR-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+vuint32m1_t test_vreinterpret_v_u16m1_u32m1(vuint16m1_t src) {
+  return __riscv_vreinterpret_v_u16m1_u32m1(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 4 x i32> @test_vreinterpret_v_u16m2_u32m2
+// CHECK-IR-SAME: (<vscale x 8 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i16> [[SRC]] to <vscale x 4 x i32>
+// CHECK-IR-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
+//
+vuint32m2_t test_vreinterpret_v_u16m2_u32m2(vuint16m2_t src) {
+  return __riscv_vreinterpret_v_u16m2_u32m2(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 8 x i32> @test_vreinterpret_v_u16m4_u32m4
+// CHECK-IR-SAME: (<vscale x 16 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i16> [[SRC]] to <vscale x 8 x i32>
+// CHECK-IR-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
+//
+vuint32m4_t test_vreinterpret_v_u16m4_u32m4(vuint16m4_t src) {
+  return __riscv_vreinterpret_v_u16m4_u32m4(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 16 x i32> @test_vreinterpret_v_u16m8_u32m8
+// CHECK-IR-SAME: (<vscale x 32 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x i16> [[SRC]] to <vscale x 16 x i32>
+// CHECK-IR-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
+//
+vuint32m8_t test_vreinterpret_v_u16m8_u32m8(vuint16m8_t src) {
+  return __riscv_vreinterpret_v_u16m8_u32m8(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_i16m1_i64m1
+// CHECK-IR-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC]] to <vscale x 1 x i64>
+// CHECK-IR-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
+//
+vint64m1_t test_vreinterpret_v_i16m1_i64m1(vint16m1_t src) {
+  return __riscv_vreinterpret_v_i16m1_i64m1(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 2 x i64> @test_vreinterpret_v_i16m2_i64m2
+// CHECK-IR-SAME: (<vscale x 8 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i16> [[SRC]] to <vscale x 2 x i64>
+// CHECK-IR-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
+//
+vint64m2_t test_vreinterpret_v_i16m2_i64m2(vint16m2_t src) {
+  return __riscv_vreinterpret_v_i16m2_i64m2(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 4 x i64> @test_vreinterpret_v_i16m4_i64m4
+// CHECK-IR-SAME: (<vscale x 16 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i16> [[SRC]] to <vscale x 4 x i64>
+// CHECK-IR-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
+//
+vint64m4_t test_vreinterpret_v_i16m4_i64m4(vint16m4_t src) {
+  return __riscv_vreinterpret_v_i16m4_i64m4(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 8 x i64> @test_vreinterpret_v_i16m8_i64m8
+// CHECK-IR-SAME: (<vscale x 32 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x i16> [[SRC]] to <vscale x 8 x i64>
+// CHECK-IR-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
+//
+vint64m8_t test_vreinterpret_v_i16m8_i64m8(vint16m8_t src) {
+  return __riscv_vreinterpret_v_i16m8_i64m8(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_u16m1_u64m1
+// CHECK-IR-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC]] to <vscale x 1 x i64>
+// CHECK-IR-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
+//
+vuint64m1_t test_vreinterpret_v_u16m1_u64m1(vuint16m1_t src) {
+  return __riscv_vreinterpret_v_u16m1_u64m1(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 2 x i64> @test_vreinterpret_v_u16m2_u64m2
+// CHECK-IR-SAME: (<vscale x 8 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i16> [[SRC]] to <vscale x 2 x i64>
+// CHECK-IR-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
+//
+vuint64m2_t test_vreinterpret_v_u16m2_u64m2(vuint16m2_t src) {
+  return __riscv_vreinterpret_v_u16m2_u64m2(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 4 x i64> @test_vreinterpret_v_u16m4_u64m4
+// CHECK-IR-SAME: (<vscale x 16 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i16> [[SRC]] to <vscale x 4 x i64>
+// CHECK-IR-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
+//
+vuint64m4_t test_vreinterpret_v_u16m4_u64m4(vuint16m4_t src) {
+  return __riscv_vreinterpret_v_u16m4_u64m4(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 8 x i64> @test_vreinterpret_v_u16m8_u64m8
+// CHECK-IR-SAME: (<vscale x 32 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x i16> [[SRC]] to <vscale x 8 x i64>
+// CHECK-IR-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
+//
+vuint64m8_t test_vreinterpret_v_u16m8_u64m8(vuint16m8_t src) {
+  return __riscv_vreinterpret_v_u16m8_u64m8(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_i32m1_i8m1
+// CHECK-IR-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i32> [[SRC]] to <vscale x 8 x i8>
+// CHECK-IR-NEXT:    ret <vscale x 8 x i8> [[TMP0]]
+//
+vint8m1_t test_vreinterpret_v_i32m1_i8m1(vint32m1_t src) {
+  return __riscv_vreinterpret_v_i32m1_i8m1(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 16 x i8> @test_vreinterpret_v_i32m2_i8m2
+// CHECK-IR-SAME: (<vscale x 4 x i32> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i32> [[SRC]] to <vscale x 16 x i8>
+// CHECK-IR-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
+//
+vint8m2_t test_vreinterpret_v_i32m2_i8m2(vint32m2_t src) {
+  return __riscv_vreinterpret_v_i32m2_i8m2(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 32 x i8> @test_vreinterpret_v_i32m4_i8m4
+// CHECK-IR-SAME: (<vscale x 8 x i32> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i32> [[SRC]] to <vscale x 32 x i8>
+// CHECK-IR-NEXT:    ret <vscale x 32 x i8> [[TMP0]]
+//
+vint8m4_t test_vreinterpret_v_i32m4_i8m4(vint32m4_t src) {
+  return __riscv_vreinterpret_v_i32m4_i8m4(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 64 x i8> @test_vreinterpret_v_i32m8_i8m8
+// CHECK-IR-SAME: (<vscale x 16 x i32> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i32> [[SRC]] to <vscale x 64 x i8>
+// CHECK-IR-NEXT:    ret <vscale x 64 x i8> [[TMP0]]
+//
+vint8m8_t test_vreinterpret_v_i32m8_i8m8(vint32m8_t src) {
+  return __riscv_vreinterpret_v_i32m8_i8m8(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_u32m1_u8m1
+// CHECK-IR-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i32> [[SRC]] to <vscale x 8 x i8>
+// CHECK-IR-NEXT:    ret <vscale x 8 x i8> [[TMP0]]
+//
+vuint8m1_t test_vreinterpret_v_u32m1_u8m1(vuint32m1_t src) {
+  return __riscv_vreinterpret_v_u32m1_u8m1(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 16 x i8> @test_vreinterpret_v_u32m2_u8m2
+// CHECK-IR-SAME: (<vscale x 4 x i32> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i32> [[SRC]] to <vscale x 16 x i8>
+// CHECK-IR-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
+//
+vuint8m2_t test_vreinterpret_v_u32m2_u8m2(vuint32m2_t src) {
+  return __riscv_vreinterpret_v_u32m2_u8m2(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 32 x i8> @test_vreinterpret_v_u32m4_u8m4
+// CHECK-IR-SAME: (<vscale x 8 x i32> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i32> [[SRC]] to <vscale x 32 x i8>
+// CHECK-IR-NEXT:    ret <vscale x 32 x i8> [[TMP0]]
+//
+vuint8m4_t test_vreinterpret_v_u32m4_u8m4(vuint32m4_t src) {
+  return __riscv_vreinterpret_v_u32m4_u8m4(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 64 x i8> @test_vreinterpret_v_u32m8_u8m8
+// CHECK-IR-SAME: (<vscale x 16 x i32> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i32> [[SRC]] to <vscale x 64 x i8>
+// CHECK-IR-NEXT:    ret <vscale x 64 x i8> [[TMP0]]
+//
+vuint8m8_t test_vreinterpret_v_u32m8_u8m8(vuint32m8_t src) {
+  return __riscv_vreinterpret_v_u32m8_u8m8(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_i32m1_i16m1
+// CHECK-IR-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i32> [[SRC]] to <vscale x 4 x i16>
+// CHECK-IR-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
+//
+vint16m1_t test_vreinterpret_v_i32m1_i16m1(vint32m1_t src) {
+  return __riscv_vreinterpret_v_i32m1_i16m1(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 8 x i16> @test_vreinterpret_v_i32m2_i16m2
+// CHECK-IR-SAME: (<vscale x 4 x i32> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i32> [[SRC]] to <vscale x 8 x i16>
+// CHECK-IR-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
+//
+vint16m2_t test_vreinterpret_v_i32m2_i16m2(vint32m2_t src) {
+  return __riscv_vreinterpret_v_i32m2_i16m2(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 16 x i16> @test_vreinterpret_v_i32m4_i16m4
+// CHECK-IR-SAME: (<vscale x 8 x i32> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i32> [[SRC]] to <vscale x 16 x i16>
+// CHECK-IR-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
+//
+vint16m4_t test_vreinterpret_v_i32m4_i16m4(vint32m4_t src) {
+  return __riscv_vreinterpret_v_i32m4_i16m4(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 32 x i16> @test_vreinterpret_v_i32m8_i16m8
+// CHECK-IR-SAME: (<vscale x 16 x i32> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i32> [[SRC]] to <vscale x 32 x i16>
+// CHECK-IR-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
+//
+vint16m8_t test_vreinterpret_v_i32m8_i16m8(vint32m8_t src) {
+  return __riscv_vreinterpret_v_i32m8_i16m8(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_u32m1_u16m1
+// CHECK-IR-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i32> [[SRC]] to <vscale x 4 x i16>
+// CHECK-IR-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
+//
+vuint16m1_t test_vreinterpret_v_u32m1_u16m1(vuint32m1_t src) {
+  return __riscv_vreinterpret_v_u32m1_u16m1(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 8 x i16> @test_vreinterpret_v_u32m2_u16m2
+// CHECK-IR-SAME: (<vscale x 4 x i32> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i32> [[SRC]] to <vscale x 8 x i16>
+// CHECK-IR-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
+//
+vuint16m2_t test_vreinterpret_v_u32m2_u16m2(vuint32m2_t src) {
+  return __riscv_vreinterpret_v_u32m2_u16m2(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 16 x i16> @test_vreinterpret_v_u32m4_u16m4
+// CHECK-IR-SAME: (<vscale x 8 x i32> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i32> [[SRC]] to <vscale x 16 x i16>
+// CHECK-IR-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
+//
+vuint16m4_t test_vreinterpret_v_u32m4_u16m4(vuint32m4_t src) {
+  return __riscv_vreinterpret_v_u32m4_u16m4(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 32 x i16> @test_vreinterpret_v_u32m8_u16m8
+// CHECK-IR-SAME: (<vscale x 16 x i32> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i32> [[SRC]] to <vscale x 32 x i16>
+// CHECK-IR-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
+//
+vuint16m8_t test_vreinterpret_v_u32m8_u16m8(vuint32m8_t src) {
+  return __riscv_vreinterpret_v_u32m8_u16m8(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_i32m1_i64m1
+// CHECK-IR-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i32> [[SRC]] to <vscale x 1 x i64>
+// CHECK-IR-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
+//
+vint64m1_t test_vreinterpret_v_i32m1_i64m1(vint32m1_t src) {
+  return __riscv_vreinterpret_v_i32m1_i64m1(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 2 x i64> @test_vreinterpret_v_i32m2_i64m2
+// CHECK-IR-SAME: (<vscale x 4 x i32> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i32> [[SRC]] to <vscale x 2 x i64>
+// CHECK-IR-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
+//
+vint64m2_t test_vreinterpret_v_i32m2_i64m2(vint32m2_t src) {
+  return __riscv_vreinterpret_v_i32m2_i64m2(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 4 x i64> @test_vreinterpret_v_i32m4_i64m4
+// CHECK-IR-SAME: (<vscale x 8 x i32> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i32> [[SRC]] to <vscale x 4 x i64>
+// CHECK-IR-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
+//
+vint64m4_t test_vreinterpret_v_i32m4_i64m4(vint32m4_t src) {
+  return __riscv_vreinterpret_v_i32m4_i64m4(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 8 x i64> @test_vreinterpret_v_i32m8_i64m8
+// CHECK-IR-SAME: (<vscale x 16 x i32> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i32> [[SRC]] to <vscale x 8 x i64>
+// CHECK-IR-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
+//
+vint64m8_t test_vreinterpret_v_i32m8_i64m8(vint32m8_t src) {
+  return __riscv_vreinterpret_v_i32m8_i64m8(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_u32m1_u64m1
+// CHECK-IR-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i32> [[SRC]] to <vscale x 1 x i64>
+// CHECK-IR-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
+//
+vuint64m1_t test_vreinterpret_v_u32m1_u64m1(vuint32m1_t src) {
+  return __riscv_vreinterpret_v_u32m1_u64m1(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 2 x i64> @test_vreinterpret_v_u32m2_u64m2
+// CHECK-IR-SAME: (<vscale x 4 x i32> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i32> [[SRC]] to <vscale x 2 x i64>
+// CHECK-IR-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
+//
+vuint64m2_t test_vreinterpret_v_u32m2_u64m2(vuint32m2_t src) {
+  return __riscv_vreinterpret_v_u32m2_u64m2(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 4 x i64> @test_vreinterpret_v_u32m4_u64m4
+// CHECK-IR-SAME: (<vscale x 8 x i32> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i32> [[SRC]] to <vscale x 4 x i64>
+// CHECK-IR-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
+//
+vuint64m4_t test_vreinterpret_v_u32m4_u64m4(vuint32m4_t src) {
+  return __riscv_vreinterpret_v_u32m4_u64m4(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 8 x i64> @test_vreinterpret_v_u32m8_u64m8
+// CHECK-IR-SAME: (<vscale x 16 x i32> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i32> [[SRC]] to <vscale x 8 x i64>
+// CHECK-IR-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
+//
+vuint64m8_t test_vreinterpret_v_u32m8_u64m8(vuint32m8_t src) {
+  return __riscv_vreinterpret_v_u32m8_u64m8(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_i64m1_i8m1
+// CHECK-IR-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i64> [[SRC]] to <vscale x 8 x i8>
+// CHECK-IR-NEXT:    ret <vscale x 8 x i8> [[TMP0]]
+//
+vint8m1_t test_vreinterpret_v_i64m1_i8m1(vint64m1_t src) {
+  return __riscv_vreinterpret_v_i64m1_i8m1(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 16 x i8> @test_vreinterpret_v_i64m2_i8m2
+// CHECK-IR-SAME: (<vscale x 2 x i64> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i64> [[SRC]] to <vscale x 16 x i8>
+// CHECK-IR-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
+//
+vint8m2_t test_vreinterpret_v_i64m2_i8m2(vint64m2_t src) {
+  return __riscv_vreinterpret_v_i64m2_i8m2(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 32 x i8> @test_vreinterpret_v_i64m4_i8m4
+// CHECK-IR-SAME: (<vscale x 4 x i64> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i64> [[SRC]] to <vscale x 32 x i8>
+// CHECK-IR-NEXT:    ret <vscale x 32 x i8> [[TMP0]]
+//
+vint8m4_t test_vreinterpret_v_i64m4_i8m4(vint64m4_t src) {
+  return __riscv_vreinterpret_v_i64m4_i8m4(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 64 x i8> @test_vreinterpret_v_i64m8_i8m8
+// CHECK-IR-SAME: (<vscale x 8 x i64> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i64> [[SRC]] to <vscale x 64 x i8>
+// CHECK-IR-NEXT:    ret <vscale x 64 x i8> [[TMP0]]
+//
+vint8m8_t test_vreinterpret_v_i64m8_i8m8(vint64m8_t src) {
+  return __riscv_vreinterpret_v_i64m8_i8m8(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_u64m1_u8m1
+// CHECK-IR-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i64> [[SRC]] to <vscale x 8 x i8>
+// CHECK-IR-NEXT:    ret <vscale x 8 x i8> [[TMP0]]
+//
+vuint8m1_t test_vreinterpret_v_u64m1_u8m1(vuint64m1_t src) {
+  return __riscv_vreinterpret_v_u64m1_u8m1(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 16 x i8> @test_vreinterpret_v_u64m2_u8m2
+// CHECK-IR-SAME: (<vscale x 2 x i64> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i64> [[SRC]] to <vscale x 16 x i8>
+// CHECK-IR-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
+//
+vuint8m2_t test_vreinterpret_v_u64m2_u8m2(vuint64m2_t src) {
+  return __riscv_vreinterpret_v_u64m2_u8m2(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 32 x i8> @test_vreinterpret_v_u64m4_u8m4
+// CHECK-IR-SAME: (<vscale x 4 x i64> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i64> [[SRC]] to <vscale x 32 x i8>
+// CHECK-IR-NEXT:    ret <vscale x 32 x i8> [[TMP0]]
+//
+vuint8m4_t test_vreinterpret_v_u64m4_u8m4(vuint64m4_t src) {
+  return __riscv_vreinterpret_v_u64m4_u8m4(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 64 x i8> @test_vreinterpret_v_u64m8_u8m8
+// CHECK-IR-SAME: (<vscale x 8 x i64> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i64> [[SRC]] to <vscale x 64 x i8>
+// CHECK-IR-NEXT:    ret <vscale x 64 x i8> [[TMP0]]
+//
+vuint8m8_t test_vreinterpret_v_u64m8_u8m8(vuint64m8_t src) {
+  return __riscv_vreinterpret_v_u64m8_u8m8(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_i64m1_i16m1
+// CHECK-IR-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i64> [[SRC]] to <vscale x 4 x i16>
+// CHECK-IR-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
+//
+vint16m1_t test_vreinterpret_v_i64m1_i16m1(vint64m1_t src) {
+  return __riscv_vreinterpret_v_i64m1_i16m1(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 8 x i16> @test_vreinterpret_v_i64m2_i16m2
+// CHECK-IR-SAME: (<vscale x 2 x i64> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i64> [[SRC]] to <vscale x 8 x i16>
+// CHECK-IR-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
+//
+vint16m2_t test_vreinterpret_v_i64m2_i16m2(vint64m2_t src) {
+  return __riscv_vreinterpret_v_i64m2_i16m2(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 16 x i16> @test_vreinterpret_v_i64m4_i16m4
+// CHECK-IR-SAME: (<vscale x 4 x i64> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i64> [[SRC]] to <vscale x 16 x i16>
+// CHECK-IR-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
+//
+vint16m4_t test_vreinterpret_v_i64m4_i16m4(vint64m4_t src) {
+  return __riscv_vreinterpret_v_i64m4_i16m4(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 32 x i16> @test_vreinterpret_v_i64m8_i16m8
+// CHECK-IR-SAME: (<vscale x 8 x i64> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i64> [[SRC]] to <vscale x 32 x i16>
+// CHECK-IR-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
+//
+vint16m8_t test_vreinterpret_v_i64m8_i16m8(vint64m8_t src) {
+  return __riscv_vreinterpret_v_i64m8_i16m8(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_u64m1_u16m1
+// CHECK-IR-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i64> [[SRC]] to <vscale x 4 x i16>
+// CHECK-IR-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
+//
+vuint16m1_t test_vreinterpret_v_u64m1_u16m1(vuint64m1_t src) {
+  return __riscv_vreinterpret_v_u64m1_u16m1(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 8 x i16> @test_vreinterpret_v_u64m2_u16m2
+// CHECK-IR-SAME: (<vscale x 2 x i64> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i64> [[SRC]] to <vscale x 8 x i16>
+// CHECK-IR-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
+//
+vuint16m2_t test_vreinterpret_v_u64m2_u16m2(vuint64m2_t src) {
+  return __riscv_vreinterpret_v_u64m2_u16m2(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 16 x i16> @test_vreinterpret_v_u64m4_u16m4
+// CHECK-IR-SAME: (<vscale x 4 x i64> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i64> [[SRC]] to <vscale x 16 x i16>
+// CHECK-IR-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
+//
+vuint16m4_t test_vreinterpret_v_u64m4_u16m4(vuint64m4_t src) {
+  return __riscv_vreinterpret_v_u64m4_u16m4(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 32 x i16> @test_vreinterpret_v_u64m8_u16m8
+// CHECK-IR-SAME: (<vscale x 8 x i64> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i64> [[SRC]] to <vscale x 32 x i16>
+// CHECK-IR-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
+//
+vuint16m8_t test_vreinterpret_v_u64m8_u16m8(vuint64m8_t src) {
+  return __riscv_vreinterpret_v_u64m8_u16m8(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_i64m1_i32m1
+// CHECK-IR-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i64> [[SRC]] to <vscale x 2 x i32>
+// CHECK-IR-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+vint32m1_t test_vreinterpret_v_i64m1_i32m1(vint64m1_t src) {
+  return __riscv_vreinterpret_v_i64m1_i32m1(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 4 x i32> @test_vreinterpret_v_i64m2_i32m2
+// CHECK-IR-SAME: (<vscale x 2 x i64> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i64> [[SRC]] to <vscale x 4 x i32>
+// CHECK-IR-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
+//
+vint32m2_t test_vreinterpret_v_i64m2_i32m2(vint64m2_t src) {
+  return __riscv_vreinterpret_v_i64m2_i32m2(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 8 x i32> @test_vreinterpret_v_i64m4_i32m4
+// CHECK-IR-SAME: (<vscale x 4 x i64> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i64> [[SRC]] to <vscale x 8 x i32>
+// CHECK-IR-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
+//
+vint32m4_t test_vreinterpret_v_i64m4_i32m4(vint64m4_t src) {
+  return __riscv_vreinterpret_v_i64m4_i32m4(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 16 x i32> @test_vreinterpret_v_i64m8_i32m8
+// CHECK-IR-SAME: (<vscale x 8 x i64> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i64> [[SRC]] to <vscale x 16 x i32>
+// CHECK-IR-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
+//
+vint32m8_t test_vreinterpret_v_i64m8_i32m8(vint64m8_t src) {
+  return __riscv_vreinterpret_v_i64m8_i32m8(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_u64m1_u32m1
+// CHECK-IR-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i64> [[SRC]] to <vscale x 2 x i32>
+// CHECK-IR-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+vuint32m1_t test_vreinterpret_v_u64m1_u32m1(vuint64m1_t src) {
+  return __riscv_vreinterpret_v_u64m1_u32m1(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 4 x i32> @test_vreinterpret_v_u64m2_u32m2
+// CHECK-IR-SAME: (<vscale x 2 x i64> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i64> [[SRC]] to <vscale x 4 x i32>
+// CHECK-IR-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
+//
+vuint32m2_t test_vreinterpret_v_u64m2_u32m2(vuint64m2_t src) {
+  return __riscv_vreinterpret_v_u64m2_u32m2(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 8 x i32> @test_vreinterpret_v_u64m4_u32m4
+// CHECK-IR-SAME: (<vscale x 4 x i64> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i64> [[SRC]] to <vscale x 8 x i32>
+// CHECK-IR-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
+//
+vuint32m4_t test_vreinterpret_v_u64m4_u32m4(vuint64m4_t src) {
+  return __riscv_vreinterpret_v_u64m4_u32m4(src);
+}
+
+// CHECK-IR-LABEL: define dso_local <vscale x 16 x i32> @test_vreinterpret_v_u64m8_u32m8
+// CHECK-IR-SAME: (<vscale x 8 x i64> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-IR-NEXT:  entry:
+// CHECK-IR-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i64> [[SRC]] to <vscale x 16 x i32>
+// CHECK-IR-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
+//
+vuint32m8_t test_vreinterpret_v_u64m8_u32m8(vuint64m8_t src) {
+  return __riscv_vreinterpret_v_u64m8_u32m8(src);
+}