From 3032c7b145442c274945da1c9402fb8a53e8a923 Mon Sep 17 00:00:00 2001 From: imkiva Date: Wed, 22 May 2024 14:18:47 +0800 Subject: [PATCH] [Clang][XTHeadVector] Implement wrappers for 14.16-14.18 --- .../Basic/riscv_vector_xtheadv_wrappers.td | 240 +++++ .../vector-floating-conv/wrappers/vfcvt.c | 968 ++++++++++++++++++ .../vector-floating-conv/wrappers/vfncvt.c | 728 +++++++++++++ .../vector-floating-conv/wrappers/vfwcvt_f.c | 488 +++++++++ .../vector-floating-conv/wrappers/vfwcvt_x.c | 248 +++++ 5 files changed, 2672 insertions(+) create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/vector-floating-conv/wrappers/vfcvt.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/vector-floating-conv/wrappers/vfncvt.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/vector-floating-conv/wrappers/vfwcvt_f.c create mode 100644 clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/vector-floating-conv/wrappers/vfwcvt_x.c diff --git a/clang/include/clang/Basic/riscv_vector_xtheadv_wrappers.td b/clang/include/clang/Basic/riscv_vector_xtheadv_wrappers.td index 322ff40ba290cf..12fa5d58532246 100644 --- a/clang/include/clang/Basic/riscv_vector_xtheadv_wrappers.td +++ b/clang/include/clang/Basic/riscv_vector_xtheadv_wrappers.td @@ -4632,6 +4632,246 @@ let HeaderCode = #define __riscv_vmfge_vv_f64m8_b8_m(mask, op1, op2, vl) __riscv_th_vmfge_vv_f64m8_b8_m(mask, op1, op2, vl) #define __riscv_vmfge_vf_f64m8_b8_m(mask, op1, op2, vl) __riscv_th_vmfge_vf_f64m8_b8_m(mask, op1, op2, vl) +#define __riscv_vfcvt_x_f_v_i16m1(src, vl) __riscv_th_vfcvt_x_f_v_i16m1(src, vl) +#define __riscv_vfcvt_x_f_v_i16m2(src, vl) __riscv_th_vfcvt_x_f_v_i16m2(src, vl) +#define __riscv_vfcvt_x_f_v_i16m4(src, vl) __riscv_th_vfcvt_x_f_v_i16m4(src, vl) +#define __riscv_vfcvt_x_f_v_i16m8(src, vl) __riscv_th_vfcvt_x_f_v_i16m8(src, vl) +#define __riscv_vfcvt_xu_f_v_u16m1(src, vl) __riscv_th_vfcvt_xu_f_v_u16m1(src, vl) +#define __riscv_vfcvt_xu_f_v_u16m2(src, vl) __riscv_th_vfcvt_xu_f_v_u16m2(src, vl) +#define __riscv_vfcvt_xu_f_v_u16m4(src, vl) __riscv_th_vfcvt_xu_f_v_u16m4(src, vl) +#define __riscv_vfcvt_xu_f_v_u16m8(src, vl) __riscv_th_vfcvt_xu_f_v_u16m8(src, vl) +#define __riscv_vfcvt_f_x_v_f16m1(src, vl) __riscv_th_vfcvt_f_x_v_f16m1(src, vl) +#define __riscv_vfcvt_f_x_v_f16m2(src, vl) __riscv_th_vfcvt_f_x_v_f16m2(src, vl) +#define __riscv_vfcvt_f_x_v_f16m4(src, vl) __riscv_th_vfcvt_f_x_v_f16m4(src, vl) +#define __riscv_vfcvt_f_x_v_f16m8(src, vl) __riscv_th_vfcvt_f_x_v_f16m8(src, vl) +#define __riscv_vfcvt_f_xu_v_f16m1(src, vl) __riscv_th_vfcvt_f_xu_v_f16m1(src, vl) +#define __riscv_vfcvt_f_xu_v_f16m2(src, vl) __riscv_th_vfcvt_f_xu_v_f16m2(src, vl) +#define __riscv_vfcvt_f_xu_v_f16m4(src, vl) __riscv_th_vfcvt_f_xu_v_f16m4(src, vl) +#define __riscv_vfcvt_f_xu_v_f16m8(src, vl) __riscv_th_vfcvt_f_xu_v_f16m8(src, vl) +#define __riscv_vfcvt_x_f_v_i32m1(src, vl) __riscv_th_vfcvt_x_f_v_i32m1(src, vl) +#define __riscv_vfcvt_x_f_v_i32m2(src, vl) __riscv_th_vfcvt_x_f_v_i32m2(src, vl) +#define __riscv_vfcvt_x_f_v_i32m4(src, vl) __riscv_th_vfcvt_x_f_v_i32m4(src, vl) +#define __riscv_vfcvt_x_f_v_i32m8(src, vl) __riscv_th_vfcvt_x_f_v_i32m8(src, vl) +#define __riscv_vfcvt_xu_f_v_u32m1(src, vl) __riscv_th_vfcvt_xu_f_v_u32m1(src, vl) +#define __riscv_vfcvt_xu_f_v_u32m2(src, vl) __riscv_th_vfcvt_xu_f_v_u32m2(src, vl) +#define __riscv_vfcvt_xu_f_v_u32m4(src, vl) __riscv_th_vfcvt_xu_f_v_u32m4(src, vl) +#define __riscv_vfcvt_xu_f_v_u32m8(src, vl) __riscv_th_vfcvt_xu_f_v_u32m8(src, vl) +#define __riscv_vfcvt_f_x_v_f32m1(src, vl) __riscv_th_vfcvt_f_x_v_f32m1(src, vl) +#define __riscv_vfcvt_f_x_v_f32m2(src, vl) __riscv_th_vfcvt_f_x_v_f32m2(src, vl) +#define __riscv_vfcvt_f_x_v_f32m4(src, vl) __riscv_th_vfcvt_f_x_v_f32m4(src, vl) +#define __riscv_vfcvt_f_x_v_f32m8(src, vl) __riscv_th_vfcvt_f_x_v_f32m8(src, vl) +#define __riscv_vfcvt_f_xu_v_f32m1(src, vl) __riscv_th_vfcvt_f_xu_v_f32m1(src, vl) +#define __riscv_vfcvt_f_xu_v_f32m2(src, vl) __riscv_th_vfcvt_f_xu_v_f32m2(src, vl) +#define __riscv_vfcvt_f_xu_v_f32m4(src, vl) __riscv_th_vfcvt_f_xu_v_f32m4(src, vl) +#define __riscv_vfcvt_f_xu_v_f32m8(src, vl) __riscv_th_vfcvt_f_xu_v_f32m8(src, vl) +#define __riscv_vfcvt_x_f_v_i64m1(src, vl) __riscv_th_vfcvt_x_f_v_i64m1(src, vl) +#define __riscv_vfcvt_x_f_v_i64m2(src, vl) __riscv_th_vfcvt_x_f_v_i64m2(src, vl) +#define __riscv_vfcvt_x_f_v_i64m4(src, vl) __riscv_th_vfcvt_x_f_v_i64m4(src, vl) +#define __riscv_vfcvt_x_f_v_i64m8(src, vl) __riscv_th_vfcvt_x_f_v_i64m8(src, vl) +#define __riscv_vfcvt_xu_f_v_u64m1(src, vl) __riscv_th_vfcvt_xu_f_v_u64m1(src, vl) +#define __riscv_vfcvt_xu_f_v_u64m2(src, vl) __riscv_th_vfcvt_xu_f_v_u64m2(src, vl) +#define __riscv_vfcvt_xu_f_v_u64m4(src, vl) __riscv_th_vfcvt_xu_f_v_u64m4(src, vl) +#define __riscv_vfcvt_xu_f_v_u64m8(src, vl) __riscv_th_vfcvt_xu_f_v_u64m8(src, vl) +#define __riscv_vfcvt_f_x_v_f64m1(src, vl) __riscv_th_vfcvt_f_x_v_f64m1(src, vl) +#define __riscv_vfcvt_f_x_v_f64m2(src, vl) __riscv_th_vfcvt_f_x_v_f64m2(src, vl) +#define __riscv_vfcvt_f_x_v_f64m4(src, vl) __riscv_th_vfcvt_f_x_v_f64m4(src, vl) +#define __riscv_vfcvt_f_x_v_f64m8(src, vl) __riscv_th_vfcvt_f_x_v_f64m8(src, vl) +#define __riscv_vfcvt_f_xu_v_f64m1(src, vl) __riscv_th_vfcvt_f_xu_v_f64m1(src, vl) +#define __riscv_vfcvt_f_xu_v_f64m2(src, vl) __riscv_th_vfcvt_f_xu_v_f64m2(src, vl) +#define __riscv_vfcvt_f_xu_v_f64m4(src, vl) __riscv_th_vfcvt_f_xu_v_f64m4(src, vl) +#define __riscv_vfcvt_f_xu_v_f64m8(src, vl) __riscv_th_vfcvt_f_xu_v_f64m8(src, vl) +#define __riscv_vfcvt_x_f_v_i16m1_m(mask, src, vl) __riscv_th_vfcvt_x_f_v_i16m1_m(mask, src, vl) +#define __riscv_vfcvt_x_f_v_i16m2_m(mask, src, vl) __riscv_th_vfcvt_x_f_v_i16m2_m(mask, src, vl) +#define __riscv_vfcvt_x_f_v_i16m4_m(mask, src, vl) __riscv_th_vfcvt_x_f_v_i16m4_m(mask, src, vl) +#define __riscv_vfcvt_x_f_v_i16m8_m(mask, src, vl) __riscv_th_vfcvt_x_f_v_i16m8_m(mask, src, vl) +#define __riscv_vfcvt_xu_f_v_u16m1_m(mask, src, vl) __riscv_th_vfcvt_xu_f_v_u16m1_m(mask, src, vl) +#define __riscv_vfcvt_xu_f_v_u16m2_m(mask, src, vl) __riscv_th_vfcvt_xu_f_v_u16m2_m(mask, src, vl) +#define __riscv_vfcvt_xu_f_v_u16m4_m(mask, src, vl) __riscv_th_vfcvt_xu_f_v_u16m4_m(mask, src, vl) +#define __riscv_vfcvt_xu_f_v_u16m8_m(mask, src, vl) __riscv_th_vfcvt_xu_f_v_u16m8_m(mask, src, vl) +#define __riscv_vfcvt_f_x_v_f16m1_m(mask, src, vl) __riscv_th_vfcvt_f_x_v_f16m1_m(mask, src, vl) +#define __riscv_vfcvt_f_x_v_f16m2_m(mask, src, vl) __riscv_th_vfcvt_f_x_v_f16m2_m(mask, src, vl) +#define __riscv_vfcvt_f_x_v_f16m4_m(mask, src, vl) __riscv_th_vfcvt_f_x_v_f16m4_m(mask, src, vl) +#define __riscv_vfcvt_f_x_v_f16m8_m(mask, src, vl) __riscv_th_vfcvt_f_x_v_f16m8_m(mask, src, vl) +#define __riscv_vfcvt_f_xu_v_f16m1_m(mask, src, vl) __riscv_th_vfcvt_f_xu_v_f16m1_m(mask, src, vl) +#define __riscv_vfcvt_f_xu_v_f16m2_m(mask, src, vl) __riscv_th_vfcvt_f_xu_v_f16m2_m(mask, src, vl) +#define __riscv_vfcvt_f_xu_v_f16m4_m(mask, src, vl) __riscv_th_vfcvt_f_xu_v_f16m4_m(mask, src, vl) +#define __riscv_vfcvt_f_xu_v_f16m8_m(mask, src, vl) __riscv_th_vfcvt_f_xu_v_f16m8_m(mask, src, vl) +#define __riscv_vfcvt_x_f_v_i32m1_m(mask, src, vl) __riscv_th_vfcvt_x_f_v_i32m1_m(mask, src, vl) +#define __riscv_vfcvt_x_f_v_i32m2_m(mask, src, vl) __riscv_th_vfcvt_x_f_v_i32m2_m(mask, src, vl) +#define __riscv_vfcvt_x_f_v_i32m4_m(mask, src, vl) __riscv_th_vfcvt_x_f_v_i32m4_m(mask, src, vl) +#define __riscv_vfcvt_x_f_v_i32m8_m(mask, src, vl) __riscv_th_vfcvt_x_f_v_i32m8_m(mask, src, vl) +#define __riscv_vfcvt_xu_f_v_u32m1_m(mask, src, vl) __riscv_th_vfcvt_xu_f_v_u32m1_m(mask, src, vl) +#define __riscv_vfcvt_xu_f_v_u32m2_m(mask, src, vl) __riscv_th_vfcvt_xu_f_v_u32m2_m(mask, src, vl) +#define __riscv_vfcvt_xu_f_v_u32m4_m(mask, src, vl) __riscv_th_vfcvt_xu_f_v_u32m4_m(mask, src, vl) +#define __riscv_vfcvt_xu_f_v_u32m8_m(mask, src, vl) __riscv_th_vfcvt_xu_f_v_u32m8_m(mask, src, vl) +#define __riscv_vfcvt_f_x_v_f32m1_m(mask, src, vl) __riscv_th_vfcvt_f_x_v_f32m1_m(mask, src, vl) +#define __riscv_vfcvt_f_x_v_f32m2_m(mask, src, vl) __riscv_th_vfcvt_f_x_v_f32m2_m(mask, src, vl) +#define __riscv_vfcvt_f_x_v_f32m4_m(mask, src, vl) __riscv_th_vfcvt_f_x_v_f32m4_m(mask, src, vl) +#define __riscv_vfcvt_f_x_v_f32m8_m(mask, src, vl) __riscv_th_vfcvt_f_x_v_f32m8_m(mask, src, vl) +#define __riscv_vfcvt_f_xu_v_f32m1_m(mask, src, vl) __riscv_th_vfcvt_f_xu_v_f32m1_m(mask, src, vl) +#define __riscv_vfcvt_f_xu_v_f32m2_m(mask, src, vl) __riscv_th_vfcvt_f_xu_v_f32m2_m(mask, src, vl) +#define __riscv_vfcvt_f_xu_v_f32m4_m(mask, src, vl) __riscv_th_vfcvt_f_xu_v_f32m4_m(mask, src, vl) +#define __riscv_vfcvt_f_xu_v_f32m8_m(mask, src, vl) __riscv_th_vfcvt_f_xu_v_f32m8_m(mask, src, vl) +#define __riscv_vfcvt_x_f_v_i64m1_m(mask, src, vl) __riscv_th_vfcvt_x_f_v_i64m1_m(mask, src, vl) +#define __riscv_vfcvt_x_f_v_i64m2_m(mask, src, vl) __riscv_th_vfcvt_x_f_v_i64m2_m(mask, src, vl) +#define __riscv_vfcvt_x_f_v_i64m4_m(mask, src, vl) __riscv_th_vfcvt_x_f_v_i64m4_m(mask, src, vl) +#define __riscv_vfcvt_x_f_v_i64m8_m(mask, src, vl) __riscv_th_vfcvt_x_f_v_i64m8_m(mask, src, vl) +#define __riscv_vfcvt_xu_f_v_u64m1_m(mask, src, vl) __riscv_th_vfcvt_xu_f_v_u64m1_m(mask, src, vl) +#define __riscv_vfcvt_xu_f_v_u64m2_m(mask, src, vl) __riscv_th_vfcvt_xu_f_v_u64m2_m(mask, src, vl) +#define __riscv_vfcvt_xu_f_v_u64m4_m(mask, src, vl) __riscv_th_vfcvt_xu_f_v_u64m4_m(mask, src, vl) +#define __riscv_vfcvt_xu_f_v_u64m8_m(mask, src, vl) __riscv_th_vfcvt_xu_f_v_u64m8_m(mask, src, vl) +#define __riscv_vfcvt_f_x_v_f64m1_m(mask, src, vl) __riscv_th_vfcvt_f_x_v_f64m1_m(mask, src, vl) +#define __riscv_vfcvt_f_x_v_f64m2_m(mask, src, vl) __riscv_th_vfcvt_f_x_v_f64m2_m(mask, src, vl) +#define __riscv_vfcvt_f_x_v_f64m4_m(mask, src, vl) __riscv_th_vfcvt_f_x_v_f64m4_m(mask, src, vl) +#define __riscv_vfcvt_f_x_v_f64m8_m(mask, src, vl) __riscv_th_vfcvt_f_x_v_f64m8_m(mask, src, vl) +#define __riscv_vfcvt_f_xu_v_f64m1_m(mask, src, vl) __riscv_th_vfcvt_f_xu_v_f64m1_m(mask, src, vl) +#define __riscv_vfcvt_f_xu_v_f64m2_m(mask, src, vl) __riscv_th_vfcvt_f_xu_v_f64m2_m(mask, src, vl) +#define __riscv_vfcvt_f_xu_v_f64m4_m(mask, src, vl) __riscv_th_vfcvt_f_xu_v_f64m4_m(mask, src, vl) +#define __riscv_vfcvt_f_xu_v_f64m8_m(mask, src, vl) __riscv_th_vfcvt_f_xu_v_f64m8_m(mask, src, vl) +#define __riscv_vfncvt_x_f_w_i8m1(src, vl) __riscv_th_vfncvt_x_f_w_i8m1(src, vl) +#define __riscv_vfncvt_x_f_w_i8m2(src, vl) __riscv_th_vfncvt_x_f_w_i8m2(src, vl) +#define __riscv_vfncvt_x_f_w_i8m4(src, vl) __riscv_th_vfncvt_x_f_w_i8m4(src, vl) +#define __riscv_vfncvt_xu_f_w_u8m1(src, vl) __riscv_th_vfncvt_xu_f_w_u8m1(src, vl) +#define __riscv_vfncvt_xu_f_w_u8m2(src, vl) __riscv_th_vfncvt_xu_f_w_u8m2(src, vl) +#define __riscv_vfncvt_xu_f_w_u8m4(src, vl) __riscv_th_vfncvt_xu_f_w_u8m4(src, vl) +#define __riscv_vfncvt_x_f_w_i16m1(src, vl) __riscv_th_vfncvt_x_f_w_i16m1(src, vl) +#define __riscv_vfncvt_x_f_w_i16m2(src, vl) __riscv_th_vfncvt_x_f_w_i16m2(src, vl) +#define __riscv_vfncvt_x_f_w_i16m4(src, vl) __riscv_th_vfncvt_x_f_w_i16m4(src, vl) +#define __riscv_vfncvt_xu_f_w_u16m1(src, vl) __riscv_th_vfncvt_xu_f_w_u16m1(src, vl) +#define __riscv_vfncvt_xu_f_w_u16m2(src, vl) __riscv_th_vfncvt_xu_f_w_u16m2(src, vl) +#define __riscv_vfncvt_xu_f_w_u16m4(src, vl) __riscv_th_vfncvt_xu_f_w_u16m4(src, vl) +#define __riscv_vfncvt_f_x_w_f16m1(src, vl) __riscv_th_vfncvt_f_x_w_f16m1(src, vl) +#define __riscv_vfncvt_f_x_w_f16m2(src, vl) __riscv_th_vfncvt_f_x_w_f16m2(src, vl) +#define __riscv_vfncvt_f_x_w_f16m4(src, vl) __riscv_th_vfncvt_f_x_w_f16m4(src, vl) +#define __riscv_vfncvt_f_xu_w_f16m1(src, vl) __riscv_th_vfncvt_f_xu_w_f16m1(src, vl) +#define __riscv_vfncvt_f_xu_w_f16m2(src, vl) __riscv_th_vfncvt_f_xu_w_f16m2(src, vl) +#define __riscv_vfncvt_f_xu_w_f16m4(src, vl) __riscv_th_vfncvt_f_xu_w_f16m4(src, vl) +#define __riscv_vfncvt_f_f_w_f16m1(src, vl) __riscv_th_vfncvt_f_f_w_f16m1(src, vl) +#define __riscv_vfncvt_f_f_w_f16m2(src, vl) __riscv_th_vfncvt_f_f_w_f16m2(src, vl) +#define __riscv_vfncvt_f_f_w_f16m4(src, vl) __riscv_th_vfncvt_f_f_w_f16m4(src, vl) +#define __riscv_vfncvt_x_f_w_i32m1(src, vl) __riscv_th_vfncvt_x_f_w_i32m1(src, vl) +#define __riscv_vfncvt_x_f_w_i32m2(src, vl) __riscv_th_vfncvt_x_f_w_i32m2(src, vl) +#define __riscv_vfncvt_x_f_w_i32m4(src, vl) __riscv_th_vfncvt_x_f_w_i32m4(src, vl) +#define __riscv_vfncvt_xu_f_w_u32m1(src, vl) __riscv_th_vfncvt_xu_f_w_u32m1(src, vl) +#define __riscv_vfncvt_xu_f_w_u32m2(src, vl) __riscv_th_vfncvt_xu_f_w_u32m2(src, vl) +#define __riscv_vfncvt_xu_f_w_u32m4(src, vl) __riscv_th_vfncvt_xu_f_w_u32m4(src, vl) +#define __riscv_vfncvt_f_x_w_f32m1(src, vl) __riscv_th_vfncvt_f_x_w_f32m1(src, vl) +#define __riscv_vfncvt_f_x_w_f32m2(src, vl) __riscv_th_vfncvt_f_x_w_f32m2(src, vl) +#define __riscv_vfncvt_f_x_w_f32m4(src, vl) __riscv_th_vfncvt_f_x_w_f32m4(src, vl) +#define __riscv_vfncvt_f_xu_w_f32m1(src, vl) __riscv_th_vfncvt_f_xu_w_f32m1(src, vl) +#define __riscv_vfncvt_f_xu_w_f32m2(src, vl) __riscv_th_vfncvt_f_xu_w_f32m2(src, vl) +#define __riscv_vfncvt_f_xu_w_f32m4(src, vl) __riscv_th_vfncvt_f_xu_w_f32m4(src, vl) +#define __riscv_vfncvt_f_f_w_f32m1(src, vl) __riscv_th_vfncvt_f_f_w_f32m1(src, vl) +#define __riscv_vfncvt_f_f_w_f32m2(src, vl) __riscv_th_vfncvt_f_f_w_f32m2(src, vl) +#define __riscv_vfncvt_f_f_w_f32m4(src, vl) __riscv_th_vfncvt_f_f_w_f32m4(src, vl) +#define __riscv_vfncvt_x_f_w_i8m1_m(mask, src, vl) __riscv_th_vfncvt_x_f_w_i8m1_m(mask, src, vl) +#define __riscv_vfncvt_x_f_w_i8m2_m(mask, src, vl) __riscv_th_vfncvt_x_f_w_i8m2_m(mask, src, vl) +#define __riscv_vfncvt_x_f_w_i8m4_m(mask, src, vl) __riscv_th_vfncvt_x_f_w_i8m4_m(mask, src, vl) +#define __riscv_vfncvt_xu_f_w_u8m1_m(mask, src, vl) __riscv_th_vfncvt_xu_f_w_u8m1_m(mask, src, vl) +#define __riscv_vfncvt_xu_f_w_u8m2_m(mask, src, vl) __riscv_th_vfncvt_xu_f_w_u8m2_m(mask, src, vl) +#define __riscv_vfncvt_xu_f_w_u8m4_m(mask, src, vl) __riscv_th_vfncvt_xu_f_w_u8m4_m(mask, src, vl) +#define __riscv_vfncvt_x_f_w_i16m1_m(mask, src, vl) __riscv_th_vfncvt_x_f_w_i16m1_m(mask, src, vl) +#define __riscv_vfncvt_x_f_w_i16m2_m(mask, src, vl) __riscv_th_vfncvt_x_f_w_i16m2_m(mask, src, vl) +#define __riscv_vfncvt_x_f_w_i16m4_m(mask, src, vl) __riscv_th_vfncvt_x_f_w_i16m4_m(mask, src, vl) +#define __riscv_vfncvt_xu_f_w_u16m1_m(mask, src, vl) __riscv_th_vfncvt_xu_f_w_u16m1_m(mask, src, vl) +#define __riscv_vfncvt_xu_f_w_u16m2_m(mask, src, vl) __riscv_th_vfncvt_xu_f_w_u16m2_m(mask, src, vl) +#define __riscv_vfncvt_xu_f_w_u16m4_m(mask, src, vl) __riscv_th_vfncvt_xu_f_w_u16m4_m(mask, src, vl) +#define __riscv_vfncvt_f_x_w_f16m1_m(mask, src, vl) __riscv_th_vfncvt_f_x_w_f16m1_m(mask, src, vl) +#define __riscv_vfncvt_f_x_w_f16m2_m(mask, src, vl) __riscv_th_vfncvt_f_x_w_f16m2_m(mask, src, vl) +#define __riscv_vfncvt_f_x_w_f16m4_m(mask, src, vl) __riscv_th_vfncvt_f_x_w_f16m4_m(mask, src, vl) +#define __riscv_vfncvt_f_xu_w_f16m1_m(mask, src, vl) __riscv_th_vfncvt_f_xu_w_f16m1_m(mask, src, vl) +#define __riscv_vfncvt_f_xu_w_f16m2_m(mask, src, vl) __riscv_th_vfncvt_f_xu_w_f16m2_m(mask, src, vl) +#define __riscv_vfncvt_f_xu_w_f16m4_m(mask, src, vl) __riscv_th_vfncvt_f_xu_w_f16m4_m(mask, src, vl) +#define __riscv_vfncvt_f_f_w_f16m1_m(mask, src, vl) __riscv_th_vfncvt_f_f_w_f16m1_m(mask, src, vl) +#define __riscv_vfncvt_f_f_w_f16m2_m(mask, src, vl) __riscv_th_vfncvt_f_f_w_f16m2_m(mask, src, vl) +#define __riscv_vfncvt_f_f_w_f16m4_m(mask, src, vl) __riscv_th_vfncvt_f_f_w_f16m4_m(mask, src, vl) +#define __riscv_vfncvt_x_f_w_i32m1_m(mask, src, vl) __riscv_th_vfncvt_x_f_w_i32m1_m(mask, src, vl) +#define __riscv_vfncvt_x_f_w_i32m2_m(mask, src, vl) __riscv_th_vfncvt_x_f_w_i32m2_m(mask, src, vl) +#define __riscv_vfncvt_x_f_w_i32m4_m(mask, src, vl) __riscv_th_vfncvt_x_f_w_i32m4_m(mask, src, vl) +#define __riscv_vfncvt_xu_f_w_u32m1_m(mask, src, vl) __riscv_th_vfncvt_xu_f_w_u32m1_m(mask, src, vl) +#define __riscv_vfncvt_xu_f_w_u32m2_m(mask, src, vl) __riscv_th_vfncvt_xu_f_w_u32m2_m(mask, src, vl) +#define __riscv_vfncvt_xu_f_w_u32m4_m(mask, src, vl) __riscv_th_vfncvt_xu_f_w_u32m4_m(mask, src, vl) +#define __riscv_vfncvt_f_x_w_f32m1_m(mask, src, vl) __riscv_th_vfncvt_f_x_w_f32m1_m(mask, src, vl) +#define __riscv_vfncvt_f_x_w_f32m2_m(mask, src, vl) __riscv_th_vfncvt_f_x_w_f32m2_m(mask, src, vl) +#define __riscv_vfncvt_f_x_w_f32m4_m(mask, src, vl) __riscv_th_vfncvt_f_x_w_f32m4_m(mask, src, vl) +#define __riscv_vfncvt_f_xu_w_f32m1_m(mask, src, vl) __riscv_th_vfncvt_f_xu_w_f32m1_m(mask, src, vl) +#define __riscv_vfncvt_f_xu_w_f32m2_m(mask, src, vl) __riscv_th_vfncvt_f_xu_w_f32m2_m(mask, src, vl) +#define __riscv_vfncvt_f_xu_w_f32m4_m(mask, src, vl) __riscv_th_vfncvt_f_xu_w_f32m4_m(mask, src, vl) +#define __riscv_vfncvt_f_f_w_f32m1_m(mask, src, vl) __riscv_th_vfncvt_f_f_w_f32m1_m(mask, src, vl) +#define __riscv_vfncvt_f_f_w_f32m2_m(mask, src, vl) __riscv_th_vfncvt_f_f_w_f32m2_m(mask, src, vl) +#define __riscv_vfncvt_f_f_w_f32m4_m(mask, src, vl) __riscv_th_vfncvt_f_f_w_f32m4_m(mask, src, vl) +#define __riscv_vfwcvt_f_x_v_f16m2(src, vl) __riscv_th_vfwcvt_f_x_v_f16m2(src, vl) +#define __riscv_vfwcvt_f_x_v_f16m4(src, vl) __riscv_th_vfwcvt_f_x_v_f16m4(src, vl) +#define __riscv_vfwcvt_f_x_v_f16m8(src, vl) __riscv_th_vfwcvt_f_x_v_f16m8(src, vl) +#define __riscv_vfwcvt_f_xu_v_f16m2(src, vl) __riscv_th_vfwcvt_f_xu_v_f16m2(src, vl) +#define __riscv_vfwcvt_f_xu_v_f16m4(src, vl) __riscv_th_vfwcvt_f_xu_v_f16m4(src, vl) +#define __riscv_vfwcvt_f_xu_v_f16m8(src, vl) __riscv_th_vfwcvt_f_xu_v_f16m8(src, vl) +#define __riscv_vfwcvt_f_x_v_f32m2(src, vl) __riscv_th_vfwcvt_f_x_v_f32m2(src, vl) +#define __riscv_vfwcvt_f_x_v_f32m4(src, vl) __riscv_th_vfwcvt_f_x_v_f32m4(src, vl) +#define __riscv_vfwcvt_f_x_v_f32m8(src, vl) __riscv_th_vfwcvt_f_x_v_f32m8(src, vl) +#define __riscv_vfwcvt_f_xu_v_f32m2(src, vl) __riscv_th_vfwcvt_f_xu_v_f32m2(src, vl) +#define __riscv_vfwcvt_f_xu_v_f32m4(src, vl) __riscv_th_vfwcvt_f_xu_v_f32m4(src, vl) +#define __riscv_vfwcvt_f_xu_v_f32m8(src, vl) __riscv_th_vfwcvt_f_xu_v_f32m8(src, vl) +#define __riscv_vfwcvt_f_f_v_f32m2(src, vl) __riscv_th_vfwcvt_f_f_v_f32m2(src, vl) +#define __riscv_vfwcvt_f_f_v_f32m4(src, vl) __riscv_th_vfwcvt_f_f_v_f32m4(src, vl) +#define __riscv_vfwcvt_f_f_v_f32m8(src, vl) __riscv_th_vfwcvt_f_f_v_f32m8(src, vl) +#define __riscv_vfwcvt_f_x_v_f64m2(src, vl) __riscv_th_vfwcvt_f_x_v_f64m2(src, vl) +#define __riscv_vfwcvt_f_x_v_f64m4(src, vl) __riscv_th_vfwcvt_f_x_v_f64m4(src, vl) +#define __riscv_vfwcvt_f_x_v_f64m8(src, vl) __riscv_th_vfwcvt_f_x_v_f64m8(src, vl) +#define __riscv_vfwcvt_f_xu_v_f64m2(src, vl) __riscv_th_vfwcvt_f_xu_v_f64m2(src, vl) +#define __riscv_vfwcvt_f_xu_v_f64m4(src, vl) __riscv_th_vfwcvt_f_xu_v_f64m4(src, vl) +#define __riscv_vfwcvt_f_xu_v_f64m8(src, vl) __riscv_th_vfwcvt_f_xu_v_f64m8(src, vl) +#define __riscv_vfwcvt_f_f_v_f64m2(src, vl) __riscv_th_vfwcvt_f_f_v_f64m2(src, vl) +#define __riscv_vfwcvt_f_f_v_f64m4(src, vl) __riscv_th_vfwcvt_f_f_v_f64m4(src, vl) +#define __riscv_vfwcvt_f_f_v_f64m8(src, vl) __riscv_th_vfwcvt_f_f_v_f64m8(src, vl) +#define __riscv_vfwcvt_f_x_v_f16m2_m(mask, src, vl) __riscv_th_vfwcvt_f_x_v_f16m2_m(mask, src, vl) +#define __riscv_vfwcvt_f_x_v_f16m4_m(mask, src, vl) __riscv_th_vfwcvt_f_x_v_f16m4_m(mask, src, vl) +#define __riscv_vfwcvt_f_x_v_f16m8_m(mask, src, vl) __riscv_th_vfwcvt_f_x_v_f16m8_m(mask, src, vl) +#define __riscv_vfwcvt_f_xu_v_f16m2_m(mask, src, vl) __riscv_th_vfwcvt_f_xu_v_f16m2_m(mask, src, vl) +#define __riscv_vfwcvt_f_xu_v_f16m4_m(mask, src, vl) __riscv_th_vfwcvt_f_xu_v_f16m4_m(mask, src, vl) +#define __riscv_vfwcvt_f_xu_v_f16m8_m(mask, src, vl) __riscv_th_vfwcvt_f_xu_v_f16m8_m(mask, src, vl) +#define __riscv_vfwcvt_f_x_v_f32m2_m(mask, src, vl) __riscv_th_vfwcvt_f_x_v_f32m2_m(mask, src, vl) +#define __riscv_vfwcvt_f_x_v_f32m4_m(mask, src, vl) __riscv_th_vfwcvt_f_x_v_f32m4_m(mask, src, vl) +#define __riscv_vfwcvt_f_x_v_f32m8_m(mask, src, vl) __riscv_th_vfwcvt_f_x_v_f32m8_m(mask, src, vl) +#define __riscv_vfwcvt_f_xu_v_f32m2_m(mask, src, vl) __riscv_th_vfwcvt_f_xu_v_f32m2_m(mask, src, vl) +#define __riscv_vfwcvt_f_xu_v_f32m4_m(mask, src, vl) __riscv_th_vfwcvt_f_xu_v_f32m4_m(mask, src, vl) +#define __riscv_vfwcvt_f_xu_v_f32m8_m(mask, src, vl) __riscv_th_vfwcvt_f_xu_v_f32m8_m(mask, src, vl) +#define __riscv_vfwcvt_f_f_v_f32m2_m(mask, src, vl) __riscv_th_vfwcvt_f_f_v_f32m2_m(mask, src, vl) +#define __riscv_vfwcvt_f_f_v_f32m4_m(mask, src, vl) __riscv_th_vfwcvt_f_f_v_f32m4_m(mask, src, vl) +#define __riscv_vfwcvt_f_f_v_f32m8_m(mask, src, vl) __riscv_th_vfwcvt_f_f_v_f32m8_m(mask, src, vl) +#define __riscv_vfwcvt_f_x_v_f64m2_m(mask, src, vl) __riscv_th_vfwcvt_f_x_v_f64m2_m(mask, src, vl) +#define __riscv_vfwcvt_f_x_v_f64m4_m(mask, src, vl) __riscv_th_vfwcvt_f_x_v_f64m4_m(mask, src, vl) +#define __riscv_vfwcvt_f_x_v_f64m8_m(mask, src, vl) __riscv_th_vfwcvt_f_x_v_f64m8_m(mask, src, vl) +#define __riscv_vfwcvt_f_xu_v_f64m2_m(mask, src, vl) __riscv_th_vfwcvt_f_xu_v_f64m2_m(mask, src, vl) +#define __riscv_vfwcvt_f_xu_v_f64m4_m(mask, src, vl) __riscv_th_vfwcvt_f_xu_v_f64m4_m(mask, src, vl) +#define __riscv_vfwcvt_f_xu_v_f64m8_m(mask, src, vl) __riscv_th_vfwcvt_f_xu_v_f64m8_m(mask, src, vl) +#define __riscv_vfwcvt_f_f_v_f64m2_m(mask, src, vl) __riscv_th_vfwcvt_f_f_v_f64m2_m(mask, src, vl) +#define __riscv_vfwcvt_f_f_v_f64m4_m(mask, src, vl) __riscv_th_vfwcvt_f_f_v_f64m4_m(mask, src, vl) +#define __riscv_vfwcvt_f_f_v_f64m8_m(mask, src, vl) __riscv_th_vfwcvt_f_f_v_f64m8_m(mask, src, vl) +#define __riscv_vfwcvt_x_f_v_i32m2(src, vl) __riscv_th_vfwcvt_x_f_v_i32m2(src, vl) +#define __riscv_vfwcvt_x_f_v_i32m4(src, vl) __riscv_th_vfwcvt_x_f_v_i32m4(src, vl) +#define __riscv_vfwcvt_x_f_v_i32m8(src, vl) __riscv_th_vfwcvt_x_f_v_i32m8(src, vl) +#define __riscv_vfwcvt_xu_f_v_u32m2(src, vl) __riscv_th_vfwcvt_xu_f_v_u32m2(src, vl) +#define __riscv_vfwcvt_xu_f_v_u32m4(src, vl) __riscv_th_vfwcvt_xu_f_v_u32m4(src, vl) +#define __riscv_vfwcvt_xu_f_v_u32m8(src, vl) __riscv_th_vfwcvt_xu_f_v_u32m8(src, vl) +#define __riscv_vfwcvt_x_f_v_i64m2(src, vl) __riscv_th_vfwcvt_x_f_v_i64m2(src, vl) +#define __riscv_vfwcvt_x_f_v_i64m4(src, vl) __riscv_th_vfwcvt_x_f_v_i64m4(src, vl) +#define __riscv_vfwcvt_x_f_v_i64m8(src, vl) __riscv_th_vfwcvt_x_f_v_i64m8(src, vl) +#define __riscv_vfwcvt_xu_f_v_u64m2(src, vl) __riscv_th_vfwcvt_xu_f_v_u64m2(src, vl) +#define __riscv_vfwcvt_xu_f_v_u64m4(src, vl) __riscv_th_vfwcvt_xu_f_v_u64m4(src, vl) +#define __riscv_vfwcvt_xu_f_v_u64m8(src, vl) __riscv_th_vfwcvt_xu_f_v_u64m8(src, vl) +#define __riscv_vfwcvt_x_f_v_i32m2_m(mask, src, vl) __riscv_th_vfwcvt_x_f_v_i32m2_m(mask, src, vl) +#define __riscv_vfwcvt_x_f_v_i32m4_m(mask, src, vl) __riscv_th_vfwcvt_x_f_v_i32m4_m(mask, src, vl) +#define __riscv_vfwcvt_x_f_v_i32m8_m(mask, src, vl) __riscv_th_vfwcvt_x_f_v_i32m8_m(mask, src, vl) +#define __riscv_vfwcvt_xu_f_v_u32m2_m(mask, src, vl) __riscv_th_vfwcvt_xu_f_v_u32m2_m(mask, src, vl) +#define __riscv_vfwcvt_xu_f_v_u32m4_m(mask, src, vl) __riscv_th_vfwcvt_xu_f_v_u32m4_m(mask, src, vl) +#define __riscv_vfwcvt_xu_f_v_u32m8_m(mask, src, vl) __riscv_th_vfwcvt_xu_f_v_u32m8_m(mask, src, vl) +#define __riscv_vfwcvt_x_f_v_i64m2_m(mask, src, vl) __riscv_th_vfwcvt_x_f_v_i64m2_m(mask, src, vl) +#define __riscv_vfwcvt_x_f_v_i64m4_m(mask, src, vl) __riscv_th_vfwcvt_x_f_v_i64m4_m(mask, src, vl) +#define __riscv_vfwcvt_x_f_v_i64m8_m(mask, src, vl) __riscv_th_vfwcvt_x_f_v_i64m8_m(mask, src, vl) +#define __riscv_vfwcvt_xu_f_v_u64m2_m(mask, src, vl) __riscv_th_vfwcvt_xu_f_v_u64m2_m(mask, src, vl) +#define __riscv_vfwcvt_xu_f_v_u64m4_m(mask, src, vl) __riscv_th_vfwcvt_xu_f_v_u64m4_m(mask, src, vl) +#define __riscv_vfwcvt_xu_f_v_u64m8_m(mask, src, vl) __riscv_th_vfwcvt_xu_f_v_u64m8_m(mask, src, vl) }] in def th_vector_floating_point_operations_wrapper_macros: RVVHeader; diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/vector-floating-conv/wrappers/vfcvt.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/vector-floating-conv/wrappers/vfcvt.c new file mode 100644 index 00000000000000..3bc21b8087584c --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/vector-floating-conv/wrappers/vfcvt.c @@ -0,0 +1,968 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -target-feature +d -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_x_f_v_i16m1 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.x.f.v.nxv4i16.nxv4f16.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m1_t test_vfcvt_x_f_v_i16m1(vfloat16m1_t src, size_t vl) { + return __riscv_vfcvt_x_f_v_i16m1(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_x_f_v_i16m2 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.x.f.v.nxv8i16.nxv8f16.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m2_t test_vfcvt_x_f_v_i16m2(vfloat16m2_t src, size_t vl) { + return __riscv_vfcvt_x_f_v_i16m2(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_x_f_v_i16m4 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.x.f.v.nxv16i16.nxv16f16.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m4_t test_vfcvt_x_f_v_i16m4(vfloat16m4_t src, size_t vl) { + return __riscv_vfcvt_x_f_v_i16m4(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_x_f_v_i16m8 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.x.f.v.nxv32i16.nxv32f16.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m8_t test_vfcvt_x_f_v_i16m8(vfloat16m8_t src, size_t vl) { + return __riscv_vfcvt_x_f_v_i16m8(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_xu_f_v_u16m1 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.xu.f.v.nxv4i16.nxv4f16.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m1_t test_vfcvt_xu_f_v_u16m1(vfloat16m1_t src, size_t vl) { + return __riscv_vfcvt_xu_f_v_u16m1(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_xu_f_v_u16m2 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.xu.f.v.nxv8i16.nxv8f16.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m2_t test_vfcvt_xu_f_v_u16m2(vfloat16m2_t src, size_t vl) { + return __riscv_vfcvt_xu_f_v_u16m2(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_xu_f_v_u16m4 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.xu.f.v.nxv16i16.nxv16f16.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m4_t test_vfcvt_xu_f_v_u16m4(vfloat16m4_t src, size_t vl) { + return __riscv_vfcvt_xu_f_v_u16m4(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_xu_f_v_u16m8 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.xu.f.v.nxv32i16.nxv32f16.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m8_t test_vfcvt_xu_f_v_u16m8(vfloat16m8_t src, size_t vl) { + return __riscv_vfcvt_xu_f_v_u16m8(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_f_x_v_f16m1 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.f.x.v.nxv4f16.nxv4i16.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat16m1_t test_vfcvt_f_x_v_f16m1(vint16m1_t src, size_t vl) { + return __riscv_vfcvt_f_x_v_f16m1(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_f_x_v_f16m2 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.f.x.v.nxv8f16.nxv8i16.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat16m2_t test_vfcvt_f_x_v_f16m2(vint16m2_t src, size_t vl) { + return __riscv_vfcvt_f_x_v_f16m2(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_f_x_v_f16m4 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.f.x.v.nxv16f16.nxv16i16.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat16m4_t test_vfcvt_f_x_v_f16m4(vint16m4_t src, size_t vl) { + return __riscv_vfcvt_f_x_v_f16m4(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_f_x_v_f16m8 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.f.x.v.nxv32f16.nxv32i16.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat16m8_t test_vfcvt_f_x_v_f16m8(vint16m8_t src, size_t vl) { + return __riscv_vfcvt_f_x_v_f16m8(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_f_xu_v_f16m1 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.f.xu.v.nxv4f16.nxv4i16.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat16m1_t test_vfcvt_f_xu_v_f16m1(vuint16m1_t src, size_t vl) { + return __riscv_vfcvt_f_xu_v_f16m1(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_f_xu_v_f16m2 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.f.xu.v.nxv8f16.nxv8i16.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat16m2_t test_vfcvt_f_xu_v_f16m2(vuint16m2_t src, size_t vl) { + return __riscv_vfcvt_f_xu_v_f16m2(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_f_xu_v_f16m4 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.f.xu.v.nxv16f16.nxv16i16.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat16m4_t test_vfcvt_f_xu_v_f16m4(vuint16m4_t src, size_t vl) { + return __riscv_vfcvt_f_xu_v_f16m4(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_f_xu_v_f16m8 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.f.xu.v.nxv32f16.nxv32i16.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat16m8_t test_vfcvt_f_xu_v_f16m8(vuint16m8_t src, size_t vl) { + return __riscv_vfcvt_f_xu_v_f16m8(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_x_f_v_i32m1 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.x.f.v.nxv2i32.nxv2f32.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m1_t test_vfcvt_x_f_v_i32m1(vfloat32m1_t src, size_t vl) { + return __riscv_vfcvt_x_f_v_i32m1(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_x_f_v_i32m2 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.x.f.v.nxv4i32.nxv4f32.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m2_t test_vfcvt_x_f_v_i32m2(vfloat32m2_t src, size_t vl) { + return __riscv_vfcvt_x_f_v_i32m2(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_x_f_v_i32m4 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.x.f.v.nxv8i32.nxv8f32.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m4_t test_vfcvt_x_f_v_i32m4(vfloat32m4_t src, size_t vl) { + return __riscv_vfcvt_x_f_v_i32m4(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_x_f_v_i32m8 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.x.f.v.nxv16i32.nxv16f32.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m8_t test_vfcvt_x_f_v_i32m8(vfloat32m8_t src, size_t vl) { + return __riscv_vfcvt_x_f_v_i32m8(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_xu_f_v_u32m1 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.xu.f.v.nxv2i32.nxv2f32.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m1_t test_vfcvt_xu_f_v_u32m1(vfloat32m1_t src, size_t vl) { + return __riscv_vfcvt_xu_f_v_u32m1(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_xu_f_v_u32m2 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.xu.f.v.nxv4i32.nxv4f32.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m2_t test_vfcvt_xu_f_v_u32m2(vfloat32m2_t src, size_t vl) { + return __riscv_vfcvt_xu_f_v_u32m2(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_xu_f_v_u32m4 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.xu.f.v.nxv8i32.nxv8f32.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m4_t test_vfcvt_xu_f_v_u32m4(vfloat32m4_t src, size_t vl) { + return __riscv_vfcvt_xu_f_v_u32m4(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_xu_f_v_u32m8 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.xu.f.v.nxv16i32.nxv16f32.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m8_t test_vfcvt_xu_f_v_u32m8(vfloat32m8_t src, size_t vl) { + return __riscv_vfcvt_xu_f_v_u32m8(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_f_x_v_f32m1 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.f.x.v.nxv2f32.nxv2i32.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m1_t test_vfcvt_f_x_v_f32m1(vint32m1_t src, size_t vl) { + return __riscv_vfcvt_f_x_v_f32m1(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_f_x_v_f32m2 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.f.x.v.nxv4f32.nxv4i32.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m2_t test_vfcvt_f_x_v_f32m2(vint32m2_t src, size_t vl) { + return __riscv_vfcvt_f_x_v_f32m2(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_f_x_v_f32m4 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.f.x.v.nxv8f32.nxv8i32.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m4_t test_vfcvt_f_x_v_f32m4(vint32m4_t src, size_t vl) { + return __riscv_vfcvt_f_x_v_f32m4(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_f_x_v_f32m8 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.f.x.v.nxv16f32.nxv16i32.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m8_t test_vfcvt_f_x_v_f32m8(vint32m8_t src, size_t vl) { + return __riscv_vfcvt_f_x_v_f32m8(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_f_xu_v_f32m1 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.f.xu.v.nxv2f32.nxv2i32.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m1_t test_vfcvt_f_xu_v_f32m1(vuint32m1_t src, size_t vl) { + return __riscv_vfcvt_f_xu_v_f32m1(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_f_xu_v_f32m2 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.f.xu.v.nxv4f32.nxv4i32.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m2_t test_vfcvt_f_xu_v_f32m2(vuint32m2_t src, size_t vl) { + return __riscv_vfcvt_f_xu_v_f32m2(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_f_xu_v_f32m4 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.f.xu.v.nxv8f32.nxv8i32.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m4_t test_vfcvt_f_xu_v_f32m4(vuint32m4_t src, size_t vl) { + return __riscv_vfcvt_f_xu_v_f32m4(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_f_xu_v_f32m8 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.f.xu.v.nxv16f32.nxv16i32.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m8_t test_vfcvt_f_xu_v_f32m8(vuint32m8_t src, size_t vl) { + return __riscv_vfcvt_f_xu_v_f32m8(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_x_f_v_i64m1 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.x.f.v.nxv1i64.nxv1f64.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint64m1_t test_vfcvt_x_f_v_i64m1(vfloat64m1_t src, size_t vl) { + return __riscv_vfcvt_x_f_v_i64m1(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_x_f_v_i64m2 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.x.f.v.nxv2i64.nxv2f64.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint64m2_t test_vfcvt_x_f_v_i64m2(vfloat64m2_t src, size_t vl) { + return __riscv_vfcvt_x_f_v_i64m2(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_x_f_v_i64m4 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.x.f.v.nxv4i64.nxv4f64.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint64m4_t test_vfcvt_x_f_v_i64m4(vfloat64m4_t src, size_t vl) { + return __riscv_vfcvt_x_f_v_i64m4(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_x_f_v_i64m8 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.x.f.v.nxv8i64.nxv8f64.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint64m8_t test_vfcvt_x_f_v_i64m8(vfloat64m8_t src, size_t vl) { + return __riscv_vfcvt_x_f_v_i64m8(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_xu_f_v_u64m1 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.xu.f.v.nxv1i64.nxv1f64.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m1_t test_vfcvt_xu_f_v_u64m1(vfloat64m1_t src, size_t vl) { + return __riscv_vfcvt_xu_f_v_u64m1(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_xu_f_v_u64m2 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.xu.f.v.nxv2i64.nxv2f64.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m2_t test_vfcvt_xu_f_v_u64m2(vfloat64m2_t src, size_t vl) { + return __riscv_vfcvt_xu_f_v_u64m2(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_xu_f_v_u64m4 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.xu.f.v.nxv4i64.nxv4f64.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m4_t test_vfcvt_xu_f_v_u64m4(vfloat64m4_t src, size_t vl) { + return __riscv_vfcvt_xu_f_v_u64m4(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_xu_f_v_u64m8 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.xu.f.v.nxv8i64.nxv8f64.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m8_t test_vfcvt_xu_f_v_u64m8(vfloat64m8_t src, size_t vl) { + return __riscv_vfcvt_xu_f_v_u64m8(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_f_x_v_f64m1 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.f.x.v.nxv1f64.nxv1i64.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat64m1_t test_vfcvt_f_x_v_f64m1(vint64m1_t src, size_t vl) { + return __riscv_vfcvt_f_x_v_f64m1(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_f_x_v_f64m2 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.f.x.v.nxv2f64.nxv2i64.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat64m2_t test_vfcvt_f_x_v_f64m2(vint64m2_t src, size_t vl) { + return __riscv_vfcvt_f_x_v_f64m2(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_f_x_v_f64m4 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.f.x.v.nxv4f64.nxv4i64.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat64m4_t test_vfcvt_f_x_v_f64m4(vint64m4_t src, size_t vl) { + return __riscv_vfcvt_f_x_v_f64m4(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_f_x_v_f64m8 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.f.x.v.nxv8f64.nxv8i64.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat64m8_t test_vfcvt_f_x_v_f64m8(vint64m8_t src, size_t vl) { + return __riscv_vfcvt_f_x_v_f64m8(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_f_xu_v_f64m1 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.f.xu.v.nxv1f64.nxv1i64.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat64m1_t test_vfcvt_f_xu_v_f64m1(vuint64m1_t src, size_t vl) { + return __riscv_vfcvt_f_xu_v_f64m1(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_f_xu_v_f64m2 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.f.xu.v.nxv2f64.nxv2i64.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat64m2_t test_vfcvt_f_xu_v_f64m2(vuint64m2_t src, size_t vl) { + return __riscv_vfcvt_f_xu_v_f64m2(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_f_xu_v_f64m4 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.f.xu.v.nxv4f64.nxv4i64.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat64m4_t test_vfcvt_f_xu_v_f64m4(vuint64m4_t src, size_t vl) { + return __riscv_vfcvt_f_xu_v_f64m4(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_f_xu_v_f64m8 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.f.xu.v.nxv8f64.nxv8i64.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat64m8_t test_vfcvt_f_xu_v_f64m8(vuint64m8_t src, size_t vl) { + return __riscv_vfcvt_f_xu_v_f64m8(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_x_f_v_i16m1_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.x.f.v.mask.nxv4i16.nxv4f16.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m1_t test_vfcvt_x_f_v_i16m1_m(vbool16_t mask, vfloat16m1_t src, size_t vl) { + return __riscv_vfcvt_x_f_v_i16m1_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_x_f_v_i16m2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.x.f.v.mask.nxv8i16.nxv8f16.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m2_t test_vfcvt_x_f_v_i16m2_m(vbool8_t mask, vfloat16m2_t src, size_t vl) { + return __riscv_vfcvt_x_f_v_i16m2_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_x_f_v_i16m4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.x.f.v.mask.nxv16i16.nxv16f16.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m4_t test_vfcvt_x_f_v_i16m4_m(vbool4_t mask, vfloat16m4_t src, size_t vl) { + return __riscv_vfcvt_x_f_v_i16m4_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_x_f_v_i16m8_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.x.f.v.mask.nxv32i16.nxv32f16.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m8_t test_vfcvt_x_f_v_i16m8_m(vbool2_t mask, vfloat16m8_t src, size_t vl) { + return __riscv_vfcvt_x_f_v_i16m8_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_xu_f_v_u16m1_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.xu.f.v.mask.nxv4i16.nxv4f16.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m1_t test_vfcvt_xu_f_v_u16m1_m(vbool16_t mask, vfloat16m1_t src, size_t vl) { + return __riscv_vfcvt_xu_f_v_u16m1_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_xu_f_v_u16m2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.xu.f.v.mask.nxv8i16.nxv8f16.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m2_t test_vfcvt_xu_f_v_u16m2_m(vbool8_t mask, vfloat16m2_t src, size_t vl) { + return __riscv_vfcvt_xu_f_v_u16m2_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_xu_f_v_u16m4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.xu.f.v.mask.nxv16i16.nxv16f16.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m4_t test_vfcvt_xu_f_v_u16m4_m(vbool4_t mask, vfloat16m4_t src, size_t vl) { + return __riscv_vfcvt_xu_f_v_u16m4_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_xu_f_v_u16m8_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.xu.f.v.mask.nxv32i16.nxv32f16.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m8_t test_vfcvt_xu_f_v_u16m8_m(vbool2_t mask, vfloat16m8_t src, size_t vl) { + return __riscv_vfcvt_xu_f_v_u16m8_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_f_x_v_f16m1_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.f.x.v.mask.nxv4f16.nxv4i16.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat16m1_t test_vfcvt_f_x_v_f16m1_m(vbool16_t mask, vint16m1_t src, size_t vl) { + return __riscv_vfcvt_f_x_v_f16m1_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_f_x_v_f16m2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.f.x.v.mask.nxv8f16.nxv8i16.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat16m2_t test_vfcvt_f_x_v_f16m2_m(vbool8_t mask, vint16m2_t src, size_t vl) { + return __riscv_vfcvt_f_x_v_f16m2_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_f_x_v_f16m4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.f.x.v.mask.nxv16f16.nxv16i16.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat16m4_t test_vfcvt_f_x_v_f16m4_m(vbool4_t mask, vint16m4_t src, size_t vl) { + return __riscv_vfcvt_f_x_v_f16m4_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_f_x_v_f16m8_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.f.x.v.mask.nxv32f16.nxv32i16.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat16m8_t test_vfcvt_f_x_v_f16m8_m(vbool2_t mask, vint16m8_t src, size_t vl) { + return __riscv_vfcvt_f_x_v_f16m8_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_f_xu_v_f16m1_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.f.xu.v.mask.nxv4f16.nxv4i16.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat16m1_t test_vfcvt_f_xu_v_f16m1_m(vbool16_t mask, vuint16m1_t src, size_t vl) { + return __riscv_vfcvt_f_xu_v_f16m1_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_f_xu_v_f16m2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.f.xu.v.mask.nxv8f16.nxv8i16.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat16m2_t test_vfcvt_f_xu_v_f16m2_m(vbool8_t mask, vuint16m2_t src, size_t vl) { + return __riscv_vfcvt_f_xu_v_f16m2_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_f_xu_v_f16m4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.f.xu.v.mask.nxv16f16.nxv16i16.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat16m4_t test_vfcvt_f_xu_v_f16m4_m(vbool4_t mask, vuint16m4_t src, size_t vl) { + return __riscv_vfcvt_f_xu_v_f16m4_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_f_xu_v_f16m8_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.f.xu.v.mask.nxv32f16.nxv32i16.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat16m8_t test_vfcvt_f_xu_v_f16m8_m(vbool2_t mask, vuint16m8_t src, size_t vl) { + return __riscv_vfcvt_f_xu_v_f16m8_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_x_f_v_i32m1_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.x.f.v.mask.nxv2i32.nxv2f32.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m1_t test_vfcvt_x_f_v_i32m1_m(vbool32_t mask, vfloat32m1_t src, size_t vl) { + return __riscv_vfcvt_x_f_v_i32m1_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_x_f_v_i32m2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.x.f.v.mask.nxv4i32.nxv4f32.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m2_t test_vfcvt_x_f_v_i32m2_m(vbool16_t mask, vfloat32m2_t src, size_t vl) { + return __riscv_vfcvt_x_f_v_i32m2_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_x_f_v_i32m4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.x.f.v.mask.nxv8i32.nxv8f32.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m4_t test_vfcvt_x_f_v_i32m4_m(vbool8_t mask, vfloat32m4_t src, size_t vl) { + return __riscv_vfcvt_x_f_v_i32m4_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_x_f_v_i32m8_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.x.f.v.mask.nxv16i32.nxv16f32.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m8_t test_vfcvt_x_f_v_i32m8_m(vbool4_t mask, vfloat32m8_t src, size_t vl) { + return __riscv_vfcvt_x_f_v_i32m8_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_xu_f_v_u32m1_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.xu.f.v.mask.nxv2i32.nxv2f32.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m1_t test_vfcvt_xu_f_v_u32m1_m(vbool32_t mask, vfloat32m1_t src, size_t vl) { + return __riscv_vfcvt_xu_f_v_u32m1_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_xu_f_v_u32m2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.xu.f.v.mask.nxv4i32.nxv4f32.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m2_t test_vfcvt_xu_f_v_u32m2_m(vbool16_t mask, vfloat32m2_t src, size_t vl) { + return __riscv_vfcvt_xu_f_v_u32m2_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_xu_f_v_u32m4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.xu.f.v.mask.nxv8i32.nxv8f32.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m4_t test_vfcvt_xu_f_v_u32m4_m(vbool8_t mask, vfloat32m4_t src, size_t vl) { + return __riscv_vfcvt_xu_f_v_u32m4_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_xu_f_v_u32m8_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.xu.f.v.mask.nxv16i32.nxv16f32.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m8_t test_vfcvt_xu_f_v_u32m8_m(vbool4_t mask, vfloat32m8_t src, size_t vl) { + return __riscv_vfcvt_xu_f_v_u32m8_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_f_x_v_f32m1_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.f.x.v.mask.nxv2f32.nxv2i32.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m1_t test_vfcvt_f_x_v_f32m1_m(vbool32_t mask, vint32m1_t src, size_t vl) { + return __riscv_vfcvt_f_x_v_f32m1_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_f_x_v_f32m2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.f.x.v.mask.nxv4f32.nxv4i32.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m2_t test_vfcvt_f_x_v_f32m2_m(vbool16_t mask, vint32m2_t src, size_t vl) { + return __riscv_vfcvt_f_x_v_f32m2_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_f_x_v_f32m4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.f.x.v.mask.nxv8f32.nxv8i32.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m4_t test_vfcvt_f_x_v_f32m4_m(vbool8_t mask, vint32m4_t src, size_t vl) { + return __riscv_vfcvt_f_x_v_f32m4_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_f_x_v_f32m8_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.f.x.v.mask.nxv16f32.nxv16i32.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m8_t test_vfcvt_f_x_v_f32m8_m(vbool4_t mask, vint32m8_t src, size_t vl) { + return __riscv_vfcvt_f_x_v_f32m8_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_f_xu_v_f32m1_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.f.xu.v.mask.nxv2f32.nxv2i32.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m1_t test_vfcvt_f_xu_v_f32m1_m(vbool32_t mask, vuint32m1_t src, size_t vl) { + return __riscv_vfcvt_f_xu_v_f32m1_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_f_xu_v_f32m2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.f.xu.v.mask.nxv4f32.nxv4i32.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m2_t test_vfcvt_f_xu_v_f32m2_m(vbool16_t mask, vuint32m2_t src, size_t vl) { + return __riscv_vfcvt_f_xu_v_f32m2_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_f_xu_v_f32m4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.f.xu.v.mask.nxv8f32.nxv8i32.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m4_t test_vfcvt_f_xu_v_f32m4_m(vbool8_t mask, vuint32m4_t src, size_t vl) { + return __riscv_vfcvt_f_xu_v_f32m4_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_f_xu_v_f32m8_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.f.xu.v.mask.nxv16f32.nxv16i32.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m8_t test_vfcvt_f_xu_v_f32m8_m(vbool4_t mask, vuint32m8_t src, size_t vl) { + return __riscv_vfcvt_f_xu_v_f32m8_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_x_f_v_i64m1_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.x.f.v.mask.nxv1i64.nxv1f64.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint64m1_t test_vfcvt_x_f_v_i64m1_m(vbool64_t mask, vfloat64m1_t src, size_t vl) { + return __riscv_vfcvt_x_f_v_i64m1_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_x_f_v_i64m2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.x.f.v.mask.nxv2i64.nxv2f64.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint64m2_t test_vfcvt_x_f_v_i64m2_m(vbool32_t mask, vfloat64m2_t src, size_t vl) { + return __riscv_vfcvt_x_f_v_i64m2_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_x_f_v_i64m4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.x.f.v.mask.nxv4i64.nxv4f64.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint64m4_t test_vfcvt_x_f_v_i64m4_m(vbool16_t mask, vfloat64m4_t src, size_t vl) { + return __riscv_vfcvt_x_f_v_i64m4_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_x_f_v_i64m8_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.x.f.v.mask.nxv8i64.nxv8f64.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint64m8_t test_vfcvt_x_f_v_i64m8_m(vbool8_t mask, vfloat64m8_t src, size_t vl) { + return __riscv_vfcvt_x_f_v_i64m8_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_xu_f_v_u64m1_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.xu.f.v.mask.nxv1i64.nxv1f64.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m1_t test_vfcvt_xu_f_v_u64m1_m(vbool64_t mask, vfloat64m1_t src, size_t vl) { + return __riscv_vfcvt_xu_f_v_u64m1_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_xu_f_v_u64m2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.xu.f.v.mask.nxv2i64.nxv2f64.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m2_t test_vfcvt_xu_f_v_u64m2_m(vbool32_t mask, vfloat64m2_t src, size_t vl) { + return __riscv_vfcvt_xu_f_v_u64m2_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_xu_f_v_u64m4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.xu.f.v.mask.nxv4i64.nxv4f64.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m4_t test_vfcvt_xu_f_v_u64m4_m(vbool16_t mask, vfloat64m4_t src, size_t vl) { + return __riscv_vfcvt_xu_f_v_u64m4_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_xu_f_v_u64m8_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.xu.f.v.mask.nxv8i64.nxv8f64.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m8_t test_vfcvt_xu_f_v_u64m8_m(vbool8_t mask, vfloat64m8_t src, size_t vl) { + return __riscv_vfcvt_xu_f_v_u64m8_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_f_x_v_f64m1_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.f.x.v.mask.nxv1f64.nxv1i64.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat64m1_t test_vfcvt_f_x_v_f64m1_m(vbool64_t mask, vint64m1_t src, size_t vl) { + return __riscv_vfcvt_f_x_v_f64m1_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_f_x_v_f64m2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.f.x.v.mask.nxv2f64.nxv2i64.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat64m2_t test_vfcvt_f_x_v_f64m2_m(vbool32_t mask, vint64m2_t src, size_t vl) { + return __riscv_vfcvt_f_x_v_f64m2_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_f_x_v_f64m4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.f.x.v.mask.nxv4f64.nxv4i64.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat64m4_t test_vfcvt_f_x_v_f64m4_m(vbool16_t mask, vint64m4_t src, size_t vl) { + return __riscv_vfcvt_f_x_v_f64m4_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_f_x_v_f64m8_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.f.x.v.mask.nxv8f64.nxv8i64.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat64m8_t test_vfcvt_f_x_v_f64m8_m(vbool8_t mask, vint64m8_t src, size_t vl) { + return __riscv_vfcvt_f_x_v_f64m8_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_f_xu_v_f64m1_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.f.xu.v.mask.nxv1f64.nxv1i64.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat64m1_t test_vfcvt_f_xu_v_f64m1_m(vbool64_t mask, vuint64m1_t src, size_t vl) { + return __riscv_vfcvt_f_xu_v_f64m1_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_f_xu_v_f64m2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.f.xu.v.mask.nxv2f64.nxv2i64.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat64m2_t test_vfcvt_f_xu_v_f64m2_m(vbool32_t mask, vuint64m2_t src, size_t vl) { + return __riscv_vfcvt_f_xu_v_f64m2_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_f_xu_v_f64m4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.f.xu.v.mask.nxv4f64.nxv4i64.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat64m4_t test_vfcvt_f_xu_v_f64m4_m(vbool16_t mask, vuint64m4_t src, size_t vl) { + return __riscv_vfcvt_f_xu_v_f64m4_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfcvt_f_xu_v_f64m8_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfcvt.f.xu.v.mask.nxv8f64.nxv8i64.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat64m8_t test_vfcvt_f_xu_v_f64m8_m(vbool8_t mask, vuint64m8_t src, size_t vl) { + return __riscv_vfcvt_f_xu_v_f64m8_m(mask, src, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/vector-floating-conv/wrappers/vfncvt.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/vector-floating-conv/wrappers/vfncvt.c new file mode 100644 index 00000000000000..f437d8f8a47fc9 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/vector-floating-conv/wrappers/vfncvt.c @@ -0,0 +1,728 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -target-feature +d -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_vfncvt_x_f_w_i8m1 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfncvt.x.f.w.nxv8i8.nxv8f16.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m1_t test_vfncvt_x_f_w_i8m1(vfloat16m2_t src, size_t vl) { + return __riscv_vfncvt_x_f_w_i8m1(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfncvt_x_f_w_i8m2 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfncvt.x.f.w.nxv16i8.nxv16f16.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m2_t test_vfncvt_x_f_w_i8m2(vfloat16m4_t src, size_t vl) { + return __riscv_vfncvt_x_f_w_i8m2(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfncvt_x_f_w_i8m4 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfncvt.x.f.w.nxv32i8.nxv32f16.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m4_t test_vfncvt_x_f_w_i8m4(vfloat16m8_t src, size_t vl) { + return __riscv_vfncvt_x_f_w_i8m4(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfncvt_xu_f_w_u8m1 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfncvt.xu.f.w.nxv8i8.nxv8f16.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m1_t test_vfncvt_xu_f_w_u8m1(vfloat16m2_t src, size_t vl) { + return __riscv_vfncvt_xu_f_w_u8m1(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfncvt_xu_f_w_u8m2 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfncvt.xu.f.w.nxv16i8.nxv16f16.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m2_t test_vfncvt_xu_f_w_u8m2(vfloat16m4_t src, size_t vl) { + return __riscv_vfncvt_xu_f_w_u8m2(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfncvt_xu_f_w_u8m4 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfncvt.xu.f.w.nxv32i8.nxv32f16.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m4_t test_vfncvt_xu_f_w_u8m4(vfloat16m8_t src, size_t vl) { + return __riscv_vfncvt_xu_f_w_u8m4(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfncvt_x_f_w_i16m1 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfncvt.x.f.w.nxv4i16.nxv4f32.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m1_t test_vfncvt_x_f_w_i16m1(vfloat32m2_t src, size_t vl) { + return __riscv_vfncvt_x_f_w_i16m1(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfncvt_x_f_w_i16m2 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfncvt.x.f.w.nxv8i16.nxv8f32.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m2_t test_vfncvt_x_f_w_i16m2(vfloat32m4_t src, size_t vl) { + return __riscv_vfncvt_x_f_w_i16m2(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfncvt_x_f_w_i16m4 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfncvt.x.f.w.nxv16i16.nxv16f32.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m4_t test_vfncvt_x_f_w_i16m4(vfloat32m8_t src, size_t vl) { + return __riscv_vfncvt_x_f_w_i16m4(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfncvt_xu_f_w_u16m1 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfncvt.xu.f.w.nxv4i16.nxv4f32.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m1_t test_vfncvt_xu_f_w_u16m1(vfloat32m2_t src, size_t vl) { + return __riscv_vfncvt_xu_f_w_u16m1(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfncvt_xu_f_w_u16m2 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfncvt.xu.f.w.nxv8i16.nxv8f32.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m2_t test_vfncvt_xu_f_w_u16m2(vfloat32m4_t src, size_t vl) { + return __riscv_vfncvt_xu_f_w_u16m2(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfncvt_xu_f_w_u16m4 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfncvt.xu.f.w.nxv16i16.nxv16f32.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m4_t test_vfncvt_xu_f_w_u16m4(vfloat32m8_t src, size_t vl) { + return __riscv_vfncvt_xu_f_w_u16m4(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfncvt_f_x_w_f16m1 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfncvt.f.x.w.nxv4f16.nxv4i32.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat16m1_t test_vfncvt_f_x_w_f16m1(vint32m2_t src, size_t vl) { + return __riscv_vfncvt_f_x_w_f16m1(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfncvt_f_x_w_f16m2 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfncvt.f.x.w.nxv8f16.nxv8i32.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat16m2_t test_vfncvt_f_x_w_f16m2(vint32m4_t src, size_t vl) { + return __riscv_vfncvt_f_x_w_f16m2(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfncvt_f_x_w_f16m4 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfncvt.f.x.w.nxv16f16.nxv16i32.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat16m4_t test_vfncvt_f_x_w_f16m4(vint32m8_t src, size_t vl) { + return __riscv_vfncvt_f_x_w_f16m4(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfncvt_f_xu_w_f16m1 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfncvt.f.xu.w.nxv4f16.nxv4i32.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat16m1_t test_vfncvt_f_xu_w_f16m1(vuint32m2_t src, size_t vl) { + return __riscv_vfncvt_f_xu_w_f16m1(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfncvt_f_xu_w_f16m2 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfncvt.f.xu.w.nxv8f16.nxv8i32.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat16m2_t test_vfncvt_f_xu_w_f16m2(vuint32m4_t src, size_t vl) { + return __riscv_vfncvt_f_xu_w_f16m2(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfncvt_f_xu_w_f16m4 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfncvt.f.xu.w.nxv16f16.nxv16i32.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat16m4_t test_vfncvt_f_xu_w_f16m4(vuint32m8_t src, size_t vl) { + return __riscv_vfncvt_f_xu_w_f16m4(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfncvt_f_f_w_f16m1 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfncvt.f.f.w.nxv4f16.nxv4f32.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat16m1_t test_vfncvt_f_f_w_f16m1(vfloat32m2_t src, size_t vl) { + return __riscv_vfncvt_f_f_w_f16m1(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfncvt_f_f_w_f16m2 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfncvt.f.f.w.nxv8f16.nxv8f32.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat16m2_t test_vfncvt_f_f_w_f16m2(vfloat32m4_t src, size_t vl) { + return __riscv_vfncvt_f_f_w_f16m2(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfncvt_f_f_w_f16m4 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfncvt.f.f.w.nxv16f16.nxv16f32.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat16m4_t test_vfncvt_f_f_w_f16m4(vfloat32m8_t src, size_t vl) { + return __riscv_vfncvt_f_f_w_f16m4(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfncvt_x_f_w_i32m1 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfncvt.x.f.w.nxv2i32.nxv2f64.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m1_t test_vfncvt_x_f_w_i32m1(vfloat64m2_t src, size_t vl) { + return __riscv_vfncvt_x_f_w_i32m1(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfncvt_x_f_w_i32m2 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfncvt.x.f.w.nxv4i32.nxv4f64.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m2_t test_vfncvt_x_f_w_i32m2(vfloat64m4_t src, size_t vl) { + return __riscv_vfncvt_x_f_w_i32m2(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfncvt_x_f_w_i32m4 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfncvt.x.f.w.nxv8i32.nxv8f64.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m4_t test_vfncvt_x_f_w_i32m4(vfloat64m8_t src, size_t vl) { + return __riscv_vfncvt_x_f_w_i32m4(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfncvt_xu_f_w_u32m1 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfncvt.xu.f.w.nxv2i32.nxv2f64.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m1_t test_vfncvt_xu_f_w_u32m1(vfloat64m2_t src, size_t vl) { + return __riscv_vfncvt_xu_f_w_u32m1(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfncvt_xu_f_w_u32m2 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfncvt.xu.f.w.nxv4i32.nxv4f64.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m2_t test_vfncvt_xu_f_w_u32m2(vfloat64m4_t src, size_t vl) { + return __riscv_vfncvt_xu_f_w_u32m2(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfncvt_xu_f_w_u32m4 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfncvt.xu.f.w.nxv8i32.nxv8f64.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m4_t test_vfncvt_xu_f_w_u32m4(vfloat64m8_t src, size_t vl) { + return __riscv_vfncvt_xu_f_w_u32m4(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfncvt_f_x_w_f32m1 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfncvt.f.x.w.nxv2f32.nxv2i64.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m1_t test_vfncvt_f_x_w_f32m1(vint64m2_t src, size_t vl) { + return __riscv_vfncvt_f_x_w_f32m1(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfncvt_f_x_w_f32m2 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfncvt.f.x.w.nxv4f32.nxv4i64.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m2_t test_vfncvt_f_x_w_f32m2(vint64m4_t src, size_t vl) { + return __riscv_vfncvt_f_x_w_f32m2(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfncvt_f_x_w_f32m4 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfncvt.f.x.w.nxv8f32.nxv8i64.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m4_t test_vfncvt_f_x_w_f32m4(vint64m8_t src, size_t vl) { + return __riscv_vfncvt_f_x_w_f32m4(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfncvt_f_xu_w_f32m1 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfncvt.f.xu.w.nxv2f32.nxv2i64.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m1_t test_vfncvt_f_xu_w_f32m1(vuint64m2_t src, size_t vl) { + return __riscv_vfncvt_f_xu_w_f32m1(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfncvt_f_xu_w_f32m2 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfncvt.f.xu.w.nxv4f32.nxv4i64.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m2_t test_vfncvt_f_xu_w_f32m2(vuint64m4_t src, size_t vl) { + return __riscv_vfncvt_f_xu_w_f32m2(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfncvt_f_xu_w_f32m4 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfncvt.f.xu.w.nxv8f32.nxv8i64.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m4_t test_vfncvt_f_xu_w_f32m4(vuint64m8_t src, size_t vl) { + return __riscv_vfncvt_f_xu_w_f32m4(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfncvt_f_f_w_f32m1 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfncvt.f.f.w.nxv2f32.nxv2f64.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m1_t test_vfncvt_f_f_w_f32m1(vfloat64m2_t src, size_t vl) { + return __riscv_vfncvt_f_f_w_f32m1(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfncvt_f_f_w_f32m2 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfncvt.f.f.w.nxv4f32.nxv4f64.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m2_t test_vfncvt_f_f_w_f32m2(vfloat64m4_t src, size_t vl) { + return __riscv_vfncvt_f_f_w_f32m2(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfncvt_f_f_w_f32m4 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfncvt.f.f.w.nxv8f32.nxv8f64.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m4_t test_vfncvt_f_f_w_f32m4(vfloat64m8_t src, size_t vl) { + return __riscv_vfncvt_f_f_w_f32m4(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfncvt_x_f_w_i8m1_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfncvt.x.f.w.mask.nxv8i8.nxv8f16.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m1_t test_vfncvt_x_f_w_i8m1_m(vbool8_t mask, vfloat16m2_t src, size_t vl) { + return __riscv_vfncvt_x_f_w_i8m1_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfncvt_x_f_w_i8m2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfncvt.x.f.w.mask.nxv16i8.nxv16f16.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m2_t test_vfncvt_x_f_w_i8m2_m(vbool4_t mask, vfloat16m4_t src, size_t vl) { + return __riscv_vfncvt_x_f_w_i8m2_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfncvt_x_f_w_i8m4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfncvt.x.f.w.mask.nxv32i8.nxv32f16.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m4_t test_vfncvt_x_f_w_i8m4_m(vbool2_t mask, vfloat16m8_t src, size_t vl) { + return __riscv_vfncvt_x_f_w_i8m4_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfncvt_xu_f_w_u8m1_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfncvt.xu.f.w.mask.nxv8i8.nxv8f16.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m1_t test_vfncvt_xu_f_w_u8m1_m(vbool8_t mask, vfloat16m2_t src, size_t vl) { + return __riscv_vfncvt_xu_f_w_u8m1_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfncvt_xu_f_w_u8m2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfncvt.xu.f.w.mask.nxv16i8.nxv16f16.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m2_t test_vfncvt_xu_f_w_u8m2_m(vbool4_t mask, vfloat16m4_t src, size_t vl) { + return __riscv_vfncvt_xu_f_w_u8m2_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfncvt_xu_f_w_u8m4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfncvt.xu.f.w.mask.nxv32i8.nxv32f16.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m4_t test_vfncvt_xu_f_w_u8m4_m(vbool2_t mask, vfloat16m8_t src, size_t vl) { + return __riscv_vfncvt_xu_f_w_u8m4_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfncvt_x_f_w_i16m1_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfncvt.x.f.w.mask.nxv4i16.nxv4f32.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m1_t test_vfncvt_x_f_w_i16m1_m(vbool16_t mask, vfloat32m2_t src, size_t vl) { + return __riscv_vfncvt_x_f_w_i16m1_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfncvt_x_f_w_i16m2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfncvt.x.f.w.mask.nxv8i16.nxv8f32.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m2_t test_vfncvt_x_f_w_i16m2_m(vbool8_t mask, vfloat32m4_t src, size_t vl) { + return __riscv_vfncvt_x_f_w_i16m2_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfncvt_x_f_w_i16m4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfncvt.x.f.w.mask.nxv16i16.nxv16f32.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m4_t test_vfncvt_x_f_w_i16m4_m(vbool4_t mask, vfloat32m8_t src, size_t vl) { + return __riscv_vfncvt_x_f_w_i16m4_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfncvt_xu_f_w_u16m1_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfncvt.xu.f.w.mask.nxv4i16.nxv4f32.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m1_t test_vfncvt_xu_f_w_u16m1_m(vbool16_t mask, vfloat32m2_t src, size_t vl) { + return __riscv_vfncvt_xu_f_w_u16m1_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfncvt_xu_f_w_u16m2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfncvt.xu.f.w.mask.nxv8i16.nxv8f32.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m2_t test_vfncvt_xu_f_w_u16m2_m(vbool8_t mask, vfloat32m4_t src, size_t vl) { + return __riscv_vfncvt_xu_f_w_u16m2_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfncvt_xu_f_w_u16m4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfncvt.xu.f.w.mask.nxv16i16.nxv16f32.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m4_t test_vfncvt_xu_f_w_u16m4_m(vbool4_t mask, vfloat32m8_t src, size_t vl) { + return __riscv_vfncvt_xu_f_w_u16m4_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfncvt_f_x_w_f16m1_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfncvt.f.x.w.mask.nxv4f16.nxv4i32.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat16m1_t test_vfncvt_f_x_w_f16m1_m(vbool16_t mask, vint32m2_t src, size_t vl) { + return __riscv_vfncvt_f_x_w_f16m1_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfncvt_f_x_w_f16m2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfncvt.f.x.w.mask.nxv8f16.nxv8i32.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat16m2_t test_vfncvt_f_x_w_f16m2_m(vbool8_t mask, vint32m4_t src, size_t vl) { + return __riscv_vfncvt_f_x_w_f16m2_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfncvt_f_x_w_f16m4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfncvt.f.x.w.mask.nxv16f16.nxv16i32.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat16m4_t test_vfncvt_f_x_w_f16m4_m(vbool4_t mask, vint32m8_t src, size_t vl) { + return __riscv_vfncvt_f_x_w_f16m4_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfncvt_f_xu_w_f16m1_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfncvt.f.xu.w.mask.nxv4f16.nxv4i32.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat16m1_t test_vfncvt_f_xu_w_f16m1_m(vbool16_t mask, vuint32m2_t src, size_t vl) { + return __riscv_vfncvt_f_xu_w_f16m1_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfncvt_f_xu_w_f16m2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfncvt.f.xu.w.mask.nxv8f16.nxv8i32.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat16m2_t test_vfncvt_f_xu_w_f16m2_m(vbool8_t mask, vuint32m4_t src, size_t vl) { + return __riscv_vfncvt_f_xu_w_f16m2_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfncvt_f_xu_w_f16m4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfncvt.f.xu.w.mask.nxv16f16.nxv16i32.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat16m4_t test_vfncvt_f_xu_w_f16m4_m(vbool4_t mask, vuint32m8_t src, size_t vl) { + return __riscv_vfncvt_f_xu_w_f16m4_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfncvt_f_f_w_f16m1_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfncvt.f.f.w.mask.nxv4f16.nxv4f32.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat16m1_t test_vfncvt_f_f_w_f16m1_m(vbool16_t mask, vfloat32m2_t src, size_t vl) { + return __riscv_vfncvt_f_f_w_f16m1_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfncvt_f_f_w_f16m2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfncvt.f.f.w.mask.nxv8f16.nxv8f32.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat16m2_t test_vfncvt_f_f_w_f16m2_m(vbool8_t mask, vfloat32m4_t src, size_t vl) { + return __riscv_vfncvt_f_f_w_f16m2_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfncvt_f_f_w_f16m4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfncvt.f.f.w.mask.nxv16f16.nxv16f32.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat16m4_t test_vfncvt_f_f_w_f16m4_m(vbool4_t mask, vfloat32m8_t src, size_t vl) { + return __riscv_vfncvt_f_f_w_f16m4_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfncvt_x_f_w_i32m1_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfncvt.x.f.w.mask.nxv2i32.nxv2f64.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m1_t test_vfncvt_x_f_w_i32m1_m(vbool32_t mask, vfloat64m2_t src, size_t vl) { + return __riscv_vfncvt_x_f_w_i32m1_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfncvt_x_f_w_i32m2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfncvt.x.f.w.mask.nxv4i32.nxv4f64.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m2_t test_vfncvt_x_f_w_i32m2_m(vbool16_t mask, vfloat64m4_t src, size_t vl) { + return __riscv_vfncvt_x_f_w_i32m2_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfncvt_x_f_w_i32m4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfncvt.x.f.w.mask.nxv8i32.nxv8f64.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m4_t test_vfncvt_x_f_w_i32m4_m(vbool8_t mask, vfloat64m8_t src, size_t vl) { + return __riscv_vfncvt_x_f_w_i32m4_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfncvt_xu_f_w_u32m1_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfncvt.xu.f.w.mask.nxv2i32.nxv2f64.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m1_t test_vfncvt_xu_f_w_u32m1_m(vbool32_t mask, vfloat64m2_t src, size_t vl) { + return __riscv_vfncvt_xu_f_w_u32m1_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfncvt_xu_f_w_u32m2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfncvt.xu.f.w.mask.nxv4i32.nxv4f64.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m2_t test_vfncvt_xu_f_w_u32m2_m(vbool16_t mask, vfloat64m4_t src, size_t vl) { + return __riscv_vfncvt_xu_f_w_u32m2_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfncvt_xu_f_w_u32m4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfncvt.xu.f.w.mask.nxv8i32.nxv8f64.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m4_t test_vfncvt_xu_f_w_u32m4_m(vbool8_t mask, vfloat64m8_t src, size_t vl) { + return __riscv_vfncvt_xu_f_w_u32m4_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfncvt_f_x_w_f32m1_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfncvt.f.x.w.mask.nxv2f32.nxv2i64.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m1_t test_vfncvt_f_x_w_f32m1_m(vbool32_t mask, vint64m2_t src, size_t vl) { + return __riscv_vfncvt_f_x_w_f32m1_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfncvt_f_x_w_f32m2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfncvt.f.x.w.mask.nxv4f32.nxv4i64.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m2_t test_vfncvt_f_x_w_f32m2_m(vbool16_t mask, vint64m4_t src, size_t vl) { + return __riscv_vfncvt_f_x_w_f32m2_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfncvt_f_x_w_f32m4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfncvt.f.x.w.mask.nxv8f32.nxv8i64.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m4_t test_vfncvt_f_x_w_f32m4_m(vbool8_t mask, vint64m8_t src, size_t vl) { + return __riscv_vfncvt_f_x_w_f32m4_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfncvt_f_xu_w_f32m1_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfncvt.f.xu.w.mask.nxv2f32.nxv2i64.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m1_t test_vfncvt_f_xu_w_f32m1_m(vbool32_t mask, vuint64m2_t src, size_t vl) { + return __riscv_vfncvt_f_xu_w_f32m1_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfncvt_f_xu_w_f32m2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfncvt.f.xu.w.mask.nxv4f32.nxv4i64.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m2_t test_vfncvt_f_xu_w_f32m2_m(vbool16_t mask, vuint64m4_t src, size_t vl) { + return __riscv_vfncvt_f_xu_w_f32m2_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfncvt_f_xu_w_f32m4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfncvt.f.xu.w.mask.nxv8f32.nxv8i64.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m4_t test_vfncvt_f_xu_w_f32m4_m(vbool8_t mask, vuint64m8_t src, size_t vl) { + return __riscv_vfncvt_f_xu_w_f32m4_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfncvt_f_f_w_f32m1_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfncvt.f.f.w.mask.nxv2f32.nxv2f64.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m1_t test_vfncvt_f_f_w_f32m1_m(vbool32_t mask, vfloat64m2_t src, size_t vl) { + return __riscv_vfncvt_f_f_w_f32m1_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfncvt_f_f_w_f32m2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfncvt.f.f.w.mask.nxv4f32.nxv4f64.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m2_t test_vfncvt_f_f_w_f32m2_m(vbool16_t mask, vfloat64m4_t src, size_t vl) { + return __riscv_vfncvt_f_f_w_f32m2_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfncvt_f_f_w_f32m4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfncvt.f.f.w.mask.nxv8f32.nxv8f64.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m4_t test_vfncvt_f_f_w_f32m4_m(vbool8_t mask, vfloat64m8_t src, size_t vl) { + return __riscv_vfncvt_f_f_w_f32m4_m(mask, src, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/vector-floating-conv/wrappers/vfwcvt_f.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/vector-floating-conv/wrappers/vfwcvt_f.c new file mode 100644 index 00000000000000..59394d5ae10150 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/vector-floating-conv/wrappers/vfwcvt_f.c @@ -0,0 +1,488 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -target-feature +d -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_vfwcvt_f_x_v_f16m2 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfwcvt.f.x.v.nxv8f16.nxv8i8.i64( poison, [[SRC]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat16m2_t test_vfwcvt_f_x_v_f16m2(vint8m1_t src, size_t vl) { + return __riscv_vfwcvt_f_x_v_f16m2(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfwcvt_f_x_v_f16m4 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfwcvt.f.x.v.nxv16f16.nxv16i8.i64( poison, [[SRC]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat16m4_t test_vfwcvt_f_x_v_f16m4(vint8m2_t src, size_t vl) { + return __riscv_vfwcvt_f_x_v_f16m4(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfwcvt_f_x_v_f16m8 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfwcvt.f.x.v.nxv32f16.nxv32i8.i64( poison, [[SRC]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat16m8_t test_vfwcvt_f_x_v_f16m8(vint8m4_t src, size_t vl) { + return __riscv_vfwcvt_f_x_v_f16m8(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfwcvt_f_xu_v_f16m2 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfwcvt.f.xu.v.nxv8f16.nxv8i8.i64( poison, [[SRC]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat16m2_t test_vfwcvt_f_xu_v_f16m2(vuint8m1_t src, size_t vl) { + return __riscv_vfwcvt_f_xu_v_f16m2(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfwcvt_f_xu_v_f16m4 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfwcvt.f.xu.v.nxv16f16.nxv16i8.i64( poison, [[SRC]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat16m4_t test_vfwcvt_f_xu_v_f16m4(vuint8m2_t src, size_t vl) { + return __riscv_vfwcvt_f_xu_v_f16m4(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfwcvt_f_xu_v_f16m8 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfwcvt.f.xu.v.nxv32f16.nxv32i8.i64( poison, [[SRC]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat16m8_t test_vfwcvt_f_xu_v_f16m8(vuint8m4_t src, size_t vl) { + return __riscv_vfwcvt_f_xu_v_f16m8(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfwcvt_f_x_v_f32m2 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfwcvt.f.x.v.nxv4f32.nxv4i16.i64( poison, [[SRC]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m2_t test_vfwcvt_f_x_v_f32m2(vint16m1_t src, size_t vl) { + return __riscv_vfwcvt_f_x_v_f32m2(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfwcvt_f_x_v_f32m4 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfwcvt.f.x.v.nxv8f32.nxv8i16.i64( poison, [[SRC]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m4_t test_vfwcvt_f_x_v_f32m4(vint16m2_t src, size_t vl) { + return __riscv_vfwcvt_f_x_v_f32m4(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfwcvt_f_x_v_f32m8 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfwcvt.f.x.v.nxv16f32.nxv16i16.i64( poison, [[SRC]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m8_t test_vfwcvt_f_x_v_f32m8(vint16m4_t src, size_t vl) { + return __riscv_vfwcvt_f_x_v_f32m8(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfwcvt_f_xu_v_f32m2 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfwcvt.f.xu.v.nxv4f32.nxv4i16.i64( poison, [[SRC]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m2_t test_vfwcvt_f_xu_v_f32m2(vuint16m1_t src, size_t vl) { + return __riscv_vfwcvt_f_xu_v_f32m2(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfwcvt_f_xu_v_f32m4 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfwcvt.f.xu.v.nxv8f32.nxv8i16.i64( poison, [[SRC]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m4_t test_vfwcvt_f_xu_v_f32m4(vuint16m2_t src, size_t vl) { + return __riscv_vfwcvt_f_xu_v_f32m4(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfwcvt_f_xu_v_f32m8 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfwcvt.f.xu.v.nxv16f32.nxv16i16.i64( poison, [[SRC]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m8_t test_vfwcvt_f_xu_v_f32m8(vuint16m4_t src, size_t vl) { + return __riscv_vfwcvt_f_xu_v_f32m8(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfwcvt_f_f_v_f32m2 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfwcvt.f.f.v.nxv4f32.nxv4f16.i64( poison, [[SRC]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m2_t test_vfwcvt_f_f_v_f32m2(vfloat16m1_t src, size_t vl) { + return __riscv_vfwcvt_f_f_v_f32m2(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfwcvt_f_f_v_f32m4 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfwcvt.f.f.v.nxv8f32.nxv8f16.i64( poison, [[SRC]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m4_t test_vfwcvt_f_f_v_f32m4(vfloat16m2_t src, size_t vl) { + return __riscv_vfwcvt_f_f_v_f32m4(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfwcvt_f_f_v_f32m8 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfwcvt.f.f.v.nxv16f32.nxv16f16.i64( poison, [[SRC]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m8_t test_vfwcvt_f_f_v_f32m8(vfloat16m4_t src, size_t vl) { + return __riscv_vfwcvt_f_f_v_f32m8(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfwcvt_f_x_v_f64m2 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfwcvt.f.x.v.nxv2f64.nxv2i32.i64( poison, [[SRC]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat64m2_t test_vfwcvt_f_x_v_f64m2(vint32m1_t src, size_t vl) { + return __riscv_vfwcvt_f_x_v_f64m2(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfwcvt_f_x_v_f64m4 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfwcvt.f.x.v.nxv4f64.nxv4i32.i64( poison, [[SRC]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat64m4_t test_vfwcvt_f_x_v_f64m4(vint32m2_t src, size_t vl) { + return __riscv_vfwcvt_f_x_v_f64m4(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfwcvt_f_x_v_f64m8 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfwcvt.f.x.v.nxv8f64.nxv8i32.i64( poison, [[SRC]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat64m8_t test_vfwcvt_f_x_v_f64m8(vint32m4_t src, size_t vl) { + return __riscv_vfwcvt_f_x_v_f64m8(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfwcvt_f_xu_v_f64m2 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfwcvt.f.xu.v.nxv2f64.nxv2i32.i64( poison, [[SRC]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat64m2_t test_vfwcvt_f_xu_v_f64m2(vuint32m1_t src, size_t vl) { + return __riscv_vfwcvt_f_xu_v_f64m2(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfwcvt_f_xu_v_f64m4 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfwcvt.f.xu.v.nxv4f64.nxv4i32.i64( poison, [[SRC]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat64m4_t test_vfwcvt_f_xu_v_f64m4(vuint32m2_t src, size_t vl) { + return __riscv_vfwcvt_f_xu_v_f64m4(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfwcvt_f_xu_v_f64m8 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfwcvt.f.xu.v.nxv8f64.nxv8i32.i64( poison, [[SRC]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat64m8_t test_vfwcvt_f_xu_v_f64m8(vuint32m4_t src, size_t vl) { + return __riscv_vfwcvt_f_xu_v_f64m8(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfwcvt_f_f_v_f64m2 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfwcvt.f.f.v.nxv2f64.nxv2f32.i64( poison, [[SRC]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat64m2_t test_vfwcvt_f_f_v_f64m2(vfloat32m1_t src, size_t vl) { + return __riscv_vfwcvt_f_f_v_f64m2(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfwcvt_f_f_v_f64m4 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfwcvt.f.f.v.nxv4f64.nxv4f32.i64( poison, [[SRC]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat64m4_t test_vfwcvt_f_f_v_f64m4(vfloat32m2_t src, size_t vl) { + return __riscv_vfwcvt_f_f_v_f64m4(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfwcvt_f_f_v_f64m8 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfwcvt.f.f.v.nxv8f64.nxv8f32.i64( poison, [[SRC]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat64m8_t test_vfwcvt_f_f_v_f64m8(vfloat32m4_t src, size_t vl) { + return __riscv_vfwcvt_f_f_v_f64m8(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfwcvt_f_x_v_f16m2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfwcvt.f.x.v.mask.nxv8f16.nxv8i8.i64( poison, [[SRC]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat16m2_t test_vfwcvt_f_x_v_f16m2_m(vbool8_t mask, vint8m1_t src, size_t vl) { + return __riscv_vfwcvt_f_x_v_f16m2_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfwcvt_f_x_v_f16m4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfwcvt.f.x.v.mask.nxv16f16.nxv16i8.i64( poison, [[SRC]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat16m4_t test_vfwcvt_f_x_v_f16m4_m(vbool4_t mask, vint8m2_t src, size_t vl) { + return __riscv_vfwcvt_f_x_v_f16m4_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfwcvt_f_x_v_f16m8_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfwcvt.f.x.v.mask.nxv32f16.nxv32i8.i64( poison, [[SRC]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat16m8_t test_vfwcvt_f_x_v_f16m8_m(vbool2_t mask, vint8m4_t src, size_t vl) { + return __riscv_vfwcvt_f_x_v_f16m8_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfwcvt_f_xu_v_f16m2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfwcvt.f.xu.v.mask.nxv8f16.nxv8i8.i64( poison, [[SRC]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat16m2_t test_vfwcvt_f_xu_v_f16m2_m(vbool8_t mask, vuint8m1_t src, size_t vl) { + return __riscv_vfwcvt_f_xu_v_f16m2_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfwcvt_f_xu_v_f16m4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfwcvt.f.xu.v.mask.nxv16f16.nxv16i8.i64( poison, [[SRC]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat16m4_t test_vfwcvt_f_xu_v_f16m4_m(vbool4_t mask, vuint8m2_t src, size_t vl) { + return __riscv_vfwcvt_f_xu_v_f16m4_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfwcvt_f_xu_v_f16m8_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfwcvt.f.xu.v.mask.nxv32f16.nxv32i8.i64( poison, [[SRC]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat16m8_t test_vfwcvt_f_xu_v_f16m8_m(vbool2_t mask, vuint8m4_t src, size_t vl) { + return __riscv_vfwcvt_f_xu_v_f16m8_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfwcvt_f_x_v_f32m2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfwcvt.f.x.v.mask.nxv4f32.nxv4i16.i64( poison, [[SRC]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m2_t test_vfwcvt_f_x_v_f32m2_m(vbool16_t mask, vint16m1_t src, size_t vl) { + return __riscv_vfwcvt_f_x_v_f32m2_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfwcvt_f_x_v_f32m4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfwcvt.f.x.v.mask.nxv8f32.nxv8i16.i64( poison, [[SRC]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m4_t test_vfwcvt_f_x_v_f32m4_m(vbool8_t mask, vint16m2_t src, size_t vl) { + return __riscv_vfwcvt_f_x_v_f32m4_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfwcvt_f_x_v_f32m8_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfwcvt.f.x.v.mask.nxv16f32.nxv16i16.i64( poison, [[SRC]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m8_t test_vfwcvt_f_x_v_f32m8_m(vbool4_t mask, vint16m4_t src, size_t vl) { + return __riscv_vfwcvt_f_x_v_f32m8_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfwcvt_f_xu_v_f32m2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfwcvt.f.xu.v.mask.nxv4f32.nxv4i16.i64( poison, [[SRC]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m2_t test_vfwcvt_f_xu_v_f32m2_m(vbool16_t mask, vuint16m1_t src, size_t vl) { + return __riscv_vfwcvt_f_xu_v_f32m2_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfwcvt_f_xu_v_f32m4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfwcvt.f.xu.v.mask.nxv8f32.nxv8i16.i64( poison, [[SRC]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m4_t test_vfwcvt_f_xu_v_f32m4_m(vbool8_t mask, vuint16m2_t src, size_t vl) { + return __riscv_vfwcvt_f_xu_v_f32m4_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfwcvt_f_xu_v_f32m8_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfwcvt.f.xu.v.mask.nxv16f32.nxv16i16.i64( poison, [[SRC]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m8_t test_vfwcvt_f_xu_v_f32m8_m(vbool4_t mask, vuint16m4_t src, size_t vl) { + return __riscv_vfwcvt_f_xu_v_f32m8_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfwcvt_f_f_v_f32m2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfwcvt.f.f.v.mask.nxv4f32.nxv4f16.i64( poison, [[SRC]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m2_t test_vfwcvt_f_f_v_f32m2_m(vbool16_t mask, vfloat16m1_t src, size_t vl) { + return __riscv_vfwcvt_f_f_v_f32m2_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfwcvt_f_f_v_f32m4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfwcvt.f.f.v.mask.nxv8f32.nxv8f16.i64( poison, [[SRC]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m4_t test_vfwcvt_f_f_v_f32m4_m(vbool8_t mask, vfloat16m2_t src, size_t vl) { + return __riscv_vfwcvt_f_f_v_f32m4_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfwcvt_f_f_v_f32m8_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfwcvt.f.f.v.mask.nxv16f32.nxv16f16.i64( poison, [[SRC]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m8_t test_vfwcvt_f_f_v_f32m8_m(vbool4_t mask, vfloat16m4_t src, size_t vl) { + return __riscv_vfwcvt_f_f_v_f32m8_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfwcvt_f_x_v_f64m2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfwcvt.f.x.v.mask.nxv2f64.nxv2i32.i64( poison, [[SRC]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat64m2_t test_vfwcvt_f_x_v_f64m2_m(vbool32_t mask, vint32m1_t src, size_t vl) { + return __riscv_vfwcvt_f_x_v_f64m2_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfwcvt_f_x_v_f64m4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfwcvt.f.x.v.mask.nxv4f64.nxv4i32.i64( poison, [[SRC]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat64m4_t test_vfwcvt_f_x_v_f64m4_m(vbool16_t mask, vint32m2_t src, size_t vl) { + return __riscv_vfwcvt_f_x_v_f64m4_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfwcvt_f_x_v_f64m8_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfwcvt.f.x.v.mask.nxv8f64.nxv8i32.i64( poison, [[SRC]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat64m8_t test_vfwcvt_f_x_v_f64m8_m(vbool8_t mask, vint32m4_t src, size_t vl) { + return __riscv_vfwcvt_f_x_v_f64m8_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfwcvt_f_xu_v_f64m2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfwcvt.f.xu.v.mask.nxv2f64.nxv2i32.i64( poison, [[SRC]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat64m2_t test_vfwcvt_f_xu_v_f64m2_m(vbool32_t mask, vuint32m1_t src, size_t vl) { + return __riscv_vfwcvt_f_xu_v_f64m2_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfwcvt_f_xu_v_f64m4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfwcvt.f.xu.v.mask.nxv4f64.nxv4i32.i64( poison, [[SRC]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat64m4_t test_vfwcvt_f_xu_v_f64m4_m(vbool16_t mask, vuint32m2_t src, size_t vl) { + return __riscv_vfwcvt_f_xu_v_f64m4_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfwcvt_f_xu_v_f64m8_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfwcvt.f.xu.v.mask.nxv8f64.nxv8i32.i64( poison, [[SRC]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat64m8_t test_vfwcvt_f_xu_v_f64m8_m(vbool8_t mask, vuint32m4_t src, size_t vl) { + return __riscv_vfwcvt_f_xu_v_f64m8_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfwcvt_f_f_v_f64m2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfwcvt.f.f.v.mask.nxv2f64.nxv2f32.i64( poison, [[SRC]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat64m2_t test_vfwcvt_f_f_v_f64m2_m(vbool32_t mask, vfloat32m1_t src, size_t vl) { + return __riscv_vfwcvt_f_f_v_f64m2_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfwcvt_f_f_v_f64m4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfwcvt.f.f.v.mask.nxv4f64.nxv4f32.i64( poison, [[SRC]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat64m4_t test_vfwcvt_f_f_v_f64m4_m(vbool16_t mask, vfloat32m2_t src, size_t vl) { + return __riscv_vfwcvt_f_f_v_f64m4_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfwcvt_f_f_v_f64m8_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfwcvt.f.f.v.mask.nxv8f64.nxv8f32.i64( poison, [[SRC]], [[MASK]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat64m8_t test_vfwcvt_f_f_v_f64m8_m(vbool8_t mask, vfloat32m4_t src, size_t vl) { + return __riscv_vfwcvt_f_f_v_f64m8_m(mask, src, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/vector-floating-conv/wrappers/vfwcvt_x.c b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/vector-floating-conv/wrappers/vfwcvt_x.c new file mode 100644 index 00000000000000..0d6b1f29ea7be7 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/vector-floating-conv/wrappers/vfwcvt_x.c @@ -0,0 +1,248 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \ +// RUN: -target-feature +d -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_vfwcvt_x_f_v_i32m2 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfwcvt.x.f.v.nxv4i32.nxv4f16.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m2_t test_vfwcvt_x_f_v_i32m2(vfloat16m1_t src, size_t vl) { + return __riscv_vfwcvt_x_f_v_i32m2(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfwcvt_x_f_v_i32m4 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfwcvt.x.f.v.nxv8i32.nxv8f16.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m4_t test_vfwcvt_x_f_v_i32m4(vfloat16m2_t src, size_t vl) { + return __riscv_vfwcvt_x_f_v_i32m4(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfwcvt_x_f_v_i32m8 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfwcvt.x.f.v.nxv16i32.nxv16f16.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m8_t test_vfwcvt_x_f_v_i32m8(vfloat16m4_t src, size_t vl) { + return __riscv_vfwcvt_x_f_v_i32m8(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfwcvt_xu_f_v_u32m2 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfwcvt.xu.f.v.nxv4i32.nxv4f16.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m2_t test_vfwcvt_xu_f_v_u32m2(vfloat16m1_t src, size_t vl) { + return __riscv_vfwcvt_xu_f_v_u32m2(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfwcvt_xu_f_v_u32m4 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfwcvt.xu.f.v.nxv8i32.nxv8f16.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m4_t test_vfwcvt_xu_f_v_u32m4(vfloat16m2_t src, size_t vl) { + return __riscv_vfwcvt_xu_f_v_u32m4(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfwcvt_xu_f_v_u32m8 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfwcvt.xu.f.v.nxv16i32.nxv16f16.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m8_t test_vfwcvt_xu_f_v_u32m8(vfloat16m4_t src, size_t vl) { + return __riscv_vfwcvt_xu_f_v_u32m8(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfwcvt_x_f_v_i64m2 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfwcvt.x.f.v.nxv2i64.nxv2f32.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint64m2_t test_vfwcvt_x_f_v_i64m2(vfloat32m1_t src, size_t vl) { + return __riscv_vfwcvt_x_f_v_i64m2(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfwcvt_x_f_v_i64m4 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfwcvt.x.f.v.nxv4i64.nxv4f32.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint64m4_t test_vfwcvt_x_f_v_i64m4(vfloat32m2_t src, size_t vl) { + return __riscv_vfwcvt_x_f_v_i64m4(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfwcvt_x_f_v_i64m8 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfwcvt.x.f.v.nxv8i64.nxv8f32.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint64m8_t test_vfwcvt_x_f_v_i64m8(vfloat32m4_t src, size_t vl) { + return __riscv_vfwcvt_x_f_v_i64m8(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfwcvt_xu_f_v_u64m2 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfwcvt.xu.f.v.nxv2i64.nxv2f32.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m2_t test_vfwcvt_xu_f_v_u64m2(vfloat32m1_t src, size_t vl) { + return __riscv_vfwcvt_xu_f_v_u64m2(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfwcvt_xu_f_v_u64m4 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfwcvt.xu.f.v.nxv4i64.nxv4f32.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m4_t test_vfwcvt_xu_f_v_u64m4(vfloat32m2_t src, size_t vl) { + return __riscv_vfwcvt_xu_f_v_u64m4(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfwcvt_xu_f_v_u64m8 +// CHECK-RV64-SAME: ( [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfwcvt.xu.f.v.nxv8i64.nxv8f32.i64( poison, [[SRC]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m8_t test_vfwcvt_xu_f_v_u64m8(vfloat32m4_t src, size_t vl) { + return __riscv_vfwcvt_xu_f_v_u64m8(src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfwcvt_x_f_v_i32m2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfwcvt.x.f.v.mask.nxv4i32.nxv4f16.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m2_t test_vfwcvt_x_f_v_i32m2_m(vbool16_t mask, vfloat16m1_t src, size_t vl) { + return __riscv_vfwcvt_x_f_v_i32m2_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfwcvt_x_f_v_i32m4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfwcvt.x.f.v.mask.nxv8i32.nxv8f16.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m4_t test_vfwcvt_x_f_v_i32m4_m(vbool8_t mask, vfloat16m2_t src, size_t vl) { + return __riscv_vfwcvt_x_f_v_i32m4_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfwcvt_x_f_v_i32m8_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfwcvt.x.f.v.mask.nxv16i32.nxv16f16.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m8_t test_vfwcvt_x_f_v_i32m8_m(vbool4_t mask, vfloat16m4_t src, size_t vl) { + return __riscv_vfwcvt_x_f_v_i32m8_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfwcvt_xu_f_v_u32m2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfwcvt.xu.f.v.mask.nxv4i32.nxv4f16.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m2_t test_vfwcvt_xu_f_v_u32m2_m(vbool16_t mask, vfloat16m1_t src, size_t vl) { + return __riscv_vfwcvt_xu_f_v_u32m2_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfwcvt_xu_f_v_u32m4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfwcvt.xu.f.v.mask.nxv8i32.nxv8f16.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m4_t test_vfwcvt_xu_f_v_u32m4_m(vbool8_t mask, vfloat16m2_t src, size_t vl) { + return __riscv_vfwcvt_xu_f_v_u32m4_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfwcvt_xu_f_v_u32m8_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfwcvt.xu.f.v.mask.nxv16i32.nxv16f16.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m8_t test_vfwcvt_xu_f_v_u32m8_m(vbool4_t mask, vfloat16m4_t src, size_t vl) { + return __riscv_vfwcvt_xu_f_v_u32m8_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfwcvt_x_f_v_i64m2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfwcvt.x.f.v.mask.nxv2i64.nxv2f32.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint64m2_t test_vfwcvt_x_f_v_i64m2_m(vbool32_t mask, vfloat32m1_t src, size_t vl) { + return __riscv_vfwcvt_x_f_v_i64m2_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfwcvt_x_f_v_i64m4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfwcvt.x.f.v.mask.nxv4i64.nxv4f32.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint64m4_t test_vfwcvt_x_f_v_i64m4_m(vbool16_t mask, vfloat32m2_t src, size_t vl) { + return __riscv_vfwcvt_x_f_v_i64m4_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfwcvt_x_f_v_i64m8_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfwcvt.x.f.v.mask.nxv8i64.nxv8f32.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint64m8_t test_vfwcvt_x_f_v_i64m8_m(vbool8_t mask, vfloat32m4_t src, size_t vl) { + return __riscv_vfwcvt_x_f_v_i64m8_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfwcvt_xu_f_v_u64m2_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfwcvt.xu.f.v.mask.nxv2i64.nxv2f32.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m2_t test_vfwcvt_xu_f_v_u64m2_m(vbool32_t mask, vfloat32m1_t src, size_t vl) { + return __riscv_vfwcvt_xu_f_v_u64m2_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfwcvt_xu_f_v_u64m4_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfwcvt.xu.f.v.mask.nxv4i64.nxv4f32.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m4_t test_vfwcvt_xu_f_v_u64m4_m(vbool16_t mask, vfloat32m2_t src, size_t vl) { + return __riscv_vfwcvt_xu_f_v_u64m4_m(mask, src, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vfwcvt_xu_f_v_u64m8_m +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.th.vfwcvt.xu.f.v.mask.nxv8i64.nxv8f32.i64( poison, [[SRC]], [[MASK]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m8_t test_vfwcvt_xu_f_v_u64m8_m(vbool8_t mask, vfloat32m4_t src, size_t vl) { + return __riscv_vfwcvt_xu_f_v_u64m8_m(mask, src, vl); +}