From 46ecdfa5d8bcb238b2d3c299e58369128dbefb6d Mon Sep 17 00:00:00 2001
From: Kiva <imkiva@islovely.icu>
Date: Thu, 11 Apr 2024 09:23:19 +0800
Subject: [PATCH] [LLVM][XTHeadVector] Implement 16.1
 `vmand{n}/vmnand/vmxor/vmor{n}/vmnor/vmxnor` (#95)

* [LLVM][XTHeadVector] Implement 16.1 `vmand/vmnand/vmandn/vmxor/vmor/vmnor/vmorn/vmxnor`

* [LLVM][XTHeadVector] Test 16.1 `vmand/vmnand/vmandn/vmxor/vmor/vmnor/vmorn/vmxnor`

* [LLVM][XTHeadVector] Implement 16.1 `vmclr/vmset`

* [LLVM][XTHeadVector] Test 16.1 `vmclr/vmset`
---
 .../include/llvm/IR/IntrinsicsRISCVXTHeadV.td |  13 ++
 .../Target/RISCV/RISCVExpandPseudoInsts.cpp   |  12 ++
 .../RISCV/RISCVInstrInfoXTHeadVPseudos.td     |  87 +++++++++++-
 llvm/test/CodeGen/RISCV/rvv0p71/vmand.ll      | 129 +++++++++++++++++
 llvm/test/CodeGen/RISCV/rvv0p71/vmandn.ll     | 130 ++++++++++++++++++
 llvm/test/CodeGen/RISCV/rvv0p71/vmclr.ll      |  81 +++++++++++
 llvm/test/CodeGen/RISCV/rvv0p71/vmnand.ll     | 129 +++++++++++++++++
 llvm/test/CodeGen/RISCV/rvv0p71/vmnor.ll      | 129 +++++++++++++++++
 llvm/test/CodeGen/RISCV/rvv0p71/vmor.ll       | 129 +++++++++++++++++
 llvm/test/CodeGen/RISCV/rvv0p71/vmorn.ll      | 129 +++++++++++++++++
 llvm/test/CodeGen/RISCV/rvv0p71/vmset.ll      |  81 +++++++++++
 llvm/test/CodeGen/RISCV/rvv0p71/vmxnor.ll     | 129 +++++++++++++++++
 llvm/test/CodeGen/RISCV/rvv0p71/vmxor.ll      | 129 +++++++++++++++++
 13 files changed, 1306 insertions(+), 1 deletion(-)
 create mode 100644 llvm/test/CodeGen/RISCV/rvv0p71/vmand.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv0p71/vmandn.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv0p71/vmclr.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv0p71/vmnand.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv0p71/vmnor.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv0p71/vmor.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv0p71/vmorn.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv0p71/vmset.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv0p71/vmxnor.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv0p71/vmxor.ll

diff --git a/llvm/include/llvm/IR/IntrinsicsRISCVXTHeadV.td b/llvm/include/llvm/IR/IntrinsicsRISCVXTHeadV.td
index 8bc3e2858d5061..5b71bc71e26df3 100644
--- a/llvm/include/llvm/IR/IntrinsicsRISCVXTHeadV.td
+++ b/llvm/include/llvm/IR/IntrinsicsRISCVXTHeadV.td
@@ -897,4 +897,17 @@ let TargetPrefix = "riscv" in {
   defm th_vfmul : XVBinaryAAXRoundingMode;
   defm th_vfdiv : XVBinaryAAXRoundingMode;
   defm th_vfrdiv : XVBinaryAAXRoundingMode;
+
+  // 16.1. Vector Mask-Register Logical Operations
+  def int_riscv_th_vmand: RISCVBinaryAAAUnMasked;
+  def int_riscv_th_vmnand: RISCVBinaryAAAUnMasked;
+  def int_riscv_th_vmandnot: RISCVBinaryAAAUnMasked;
+  def int_riscv_th_vmxor: RISCVBinaryAAAUnMasked;
+  def int_riscv_th_vmor: RISCVBinaryAAAUnMasked;
+  def int_riscv_th_vmnor: RISCVBinaryAAAUnMasked;
+  def int_riscv_th_vmornot: RISCVBinaryAAAUnMasked;
+  def int_riscv_th_vmxnor: RISCVBinaryAAAUnMasked;
+  def int_riscv_th_vmclr : RISCVNullaryIntrinsic;
+  def int_riscv_th_vmset : RISCVNullaryIntrinsic;
+
 } // TargetPrefix = "riscv"
diff --git a/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp b/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
index 90bdb55e6e2d63..e8c1658281cdb9 100644
--- a/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
@@ -146,6 +146,18 @@ bool RISCVExpandPseudo::expandMI(MachineBasicBlock &MBB,
   case RISCV::PseudoVMSET_M_B64:
     // vmset.m vd => vmxnor.mm vd, vd, vd
     return expandVMSET_VMCLR(MBB, MBBI, RISCV::VMXNOR_MM);
+  case RISCV::PseudoTH_VMCLR_M_B8:
+  case RISCV::PseudoTH_VMCLR_M_B16:
+  case RISCV::PseudoTH_VMCLR_M_B32:
+  case RISCV::PseudoTH_VMCLR_M_B64:
+      // th.vmclr.m vd => th.vmxor.mm vd, vd, vd
+      return expandVMSET_VMCLR(MBB, MBBI, RISCV::TH_VMXOR_MM);
+  case RISCV::PseudoTH_VMSET_M_B8:
+  case RISCV::PseudoTH_VMSET_M_B16:
+  case RISCV::PseudoTH_VMSET_M_B32:
+  case RISCV::PseudoTH_VMSET_M_B64:
+      // th.vmset.m vd => th.vmxnor.mm vd, vd, vd
+      return expandVMSET_VMCLR(MBB, MBBI, RISCV::TH_VMXNOR_MM);
   }
 
   return false;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXTHeadVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXTHeadVPseudos.td
index 5cb3c9b6468ebe..7c7c9ac7289883 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXTHeadVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXTHeadVPseudos.td
@@ -124,6 +124,17 @@ defset list<VTypeInfoToWide> AllWidenableFloatXVectors = {
   def : VTypeInfoToWide<VF32M4, VF64M8>;
 }
 
+// Redefine `AllMasks` from RISCVInstrInfoVPseudos.td to remove fractionally-grouped register groups.
+// TODO: riscv-v-intrinsics.pdf declares there are functions accepting vbool<16,32,64>_t, but they need
+//  to be connected to MF2, MF4, MF8, which are not supported by the 'V' extension 0.7.1.
+defset list<MTypeInfo> AllXMasks = {
+  // vbool<n>_t, <n> = SEW/LMUL, we assume SEW=8 and corresponding LMUL.
+  def : MTypeInfo<vbool8_t, V_M1, "B8">;
+  def : MTypeInfo<vbool4_t, V_M2, "B16">;
+  def : MTypeInfo<vbool2_t, V_M4, "B32">;
+  def : MTypeInfo<vbool1_t, V_M8, "B64">;
+}
+
 class GetXVTypePredicates<VTypeInfo vti> {
   // TODO: distinguish different types (like F16, F32, F64, AnyF)? Is it needed?
   list<Predicate> Predicates = !cond(!eq(vti.Scalar, f16) : [HasVendorXTHeadV],
@@ -1666,6 +1677,19 @@ class XVPseudoBinaryMaskNoPolicy<VReg RetClass,
   let HasSEWOp = 1;
 }
 
+multiclass XVPseudoNullaryPseudoM <string BaseInst> {
+  foreach mti = AllXMasks in {
+    defvar mx = mti.LMul.MX;
+    defvar WriteVMALUV_MX = !cast<SchedWrite>("WriteVMALUV_" # mx);
+    defvar ReadVMALUV_MX = !cast<SchedRead>("ReadVMALUV_" # mx);
+
+    let VLMul = mti.LMul.value in {
+      def "_M_" # mti.BX : VPseudoNullaryPseudoM<BaseInst # "_MM">,
+        Sched<[WriteVMALUV_MX, ReadVMALUV_MX, ReadVMALUV_MX]>;
+    }
+  }
+}
+
 class XVPseudoUnaryNoMask<DAGOperand RetClass, DAGOperand OpClass,
                           string Constraint = ""> :
       Pseudo<(outs RetClass:$rd),
@@ -2480,6 +2504,19 @@ multiclass XVPseudoVFRDIV_VF_RM {
   }
 }
 
+multiclass XVPseudoVALU_MM {
+  foreach m = MxListXTHeadV in {
+    defvar mx = m.MX;
+    defvar WriteVMALUV_MX = !cast<SchedWrite>("WriteVMALUV_" # mx);
+    defvar ReadVMALUV_MX = !cast<SchedRead>("ReadVMALUV_" # mx);
+
+    let VLMul = m.value in {
+      def "_MM_" # mx : VPseudoBinaryNoMask<VR, VR, VR, "">,
+                          Sched<[WriteVMALUV_MX, ReadVMALUV_MX, ReadVMALUV_MX]>;
+    }
+  }
+}
+
 //===----------------------------------------------------------------------===//
 // Helpers to define the intrinsic patterns for the XTHeadVector extension.
 //===----------------------------------------------------------------------===//
@@ -2943,6 +2980,21 @@ multiclass XVPatBinaryM_VI<string intrinsic, string instruction,
                        vti.RegClass, simm5>;
 }
 
+multiclass XVPatBinaryM_MM<string intrinsic, string instruction> {
+  foreach mti = AllXMasks in
+    def : VPatBinaryM<intrinsic, instruction # "_MM_" # mti.LMul.MX,
+                      mti.Mask, mti.Mask, mti.Mask,
+                      mti.Log2SEW, VR, VR>;
+}
+
+multiclass XVPatNullaryM<string intrinsic, string inst> {
+  foreach mti = AllXMasks in
+    def : Pat<(mti.Mask (!cast<Intrinsic>(intrinsic)
+                        VLOpFrag)),
+                        (!cast<Instruction>(inst#"_M_"#mti.BX)
+                        GPR:$vl, mti.Log2SEW)>;
+}
+
 multiclass XVPatCompare_VI<string intrinsic, string inst,
                           ImmLeaf ImmType> {
   foreach vti = AllIntegerXVectors in {
@@ -3818,7 +3870,7 @@ let Predicates = [HasVendorXTHeadV], mayRaiseFPException = true,
 } // Predicates = [HasVendorXTHeadV]
 
 let Predicates = [HasVendorXTHeadV] in {
-  defm : XVPatBinaryV_VV_VX_RM<"int_riscv_th_vfmul", "PseudoTH_VFMUL", 
+  defm : XVPatBinaryV_VV_VX_RM<"int_riscv_th_vfmul", "PseudoTH_VFMUL",
                                AllFloatXVectors>;
   defm : XVPatBinaryV_VV_VX_RM<"int_riscv_th_vfdiv", "PseudoTH_VFDIV",
                                AllFloatXVectors, isSEWAware=1>;
@@ -3826,4 +3878,37 @@ let Predicates = [HasVendorXTHeadV] in {
                             AllFloatXVectors, isSEWAware=1>;
 } // Predicates = [HasVendorXTHeadV]
 
+//===----------------------------------------------------------------------===//
+// 16.1. Vector Mask-Register Logical Operations
+//===----------------------------------------------------------------------===//
+
+defm PseudoTH_VMAND: XVPseudoVALU_MM;
+defm PseudoTH_VMNAND: XVPseudoVALU_MM;
+defm PseudoTH_VMANDN: XVPseudoVALU_MM;
+defm PseudoTH_VMXOR: XVPseudoVALU_MM;
+defm PseudoTH_VMOR: XVPseudoVALU_MM;
+defm PseudoTH_VMNOR: XVPseudoVALU_MM;
+defm PseudoTH_VMORN: XVPseudoVALU_MM;
+defm PseudoTH_VMXNOR: XVPseudoVALU_MM;
+
+// Pseudo instructions, processed by the RISCVExpandPseudoInsts pass.
+defm PseudoTH_VMCLR : XVPseudoNullaryPseudoM<"TH_VMXOR">;
+defm PseudoTH_VMSET : XVPseudoNullaryPseudoM<"TH_VMXNOR">;
+
+// Patterns
+let Predicates = [HasVendorXTHeadV] in {
+  defm : XVPatBinaryM_MM<"int_riscv_th_vmand", "PseudoTH_VMAND">;
+  defm : XVPatBinaryM_MM<"int_riscv_th_vmnand", "PseudoTH_VMNAND">;
+  defm : XVPatBinaryM_MM<"int_riscv_th_vmandnot", "PseudoTH_VMANDN">;
+  defm : XVPatBinaryM_MM<"int_riscv_th_vmxor", "PseudoTH_VMXOR">;
+  defm : XVPatBinaryM_MM<"int_riscv_th_vmor", "PseudoTH_VMOR">;
+  defm : XVPatBinaryM_MM<"int_riscv_th_vmnor", "PseudoTH_VMNOR">;
+  defm : XVPatBinaryM_MM<"int_riscv_th_vmornot", "PseudoTH_VMORN">;
+  defm : XVPatBinaryM_MM<"int_riscv_th_vmxnor", "PseudoTH_VMXNOR">;
+
+  // pseudo instructions
+  defm : XVPatNullaryM<"int_riscv_th_vmclr", "PseudoTH_VMCLR">;
+  defm : XVPatNullaryM<"int_riscv_th_vmset", "PseudoTH_VMSET">;
+}
+
 include "RISCVInstrInfoXTHeadVVLPatterns.td"
diff --git a/llvm/test/CodeGen/RISCV/rvv0p71/vmand.ll b/llvm/test/CodeGen/RISCV/rvv0p71/vmand.ll
new file mode 100644
index 00000000000000..a9dab078a2b3f6
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv0p71/vmand.ll
@@ -0,0 +1,129 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+xtheadvector \
+; RUN:   -verify-machineinstrs | FileCheck %s
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+xtheadvector \
+; RUN:   -verify-machineinstrs | FileCheck %s
+
+declare <vscale x 8 x i1> @llvm.riscv.th.vmand.nxv8i1(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i1>,
+  iXLen);
+
+define <vscale x 8 x i1> @intrinsic_vmand_mm_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, iXLen %2) nounwind {
+; CHECK-LABEL: intrinsic_vmand_mm_nxv8i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    csrr a1, vl
+; CHECK-NEXT:    csrr a2, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a1, a2
+; CHECK-NEXT:    csrr a1, vl
+; CHECK-NEXT:    csrr a2, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a1, a2
+; CHECK-NEXT:    th.vsetvli zero, a0, e8, m1, d1
+; CHECK-NEXT:    th.vmand.mm v0, v0, v8
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 8 x i1> @llvm.riscv.th.vmand.nxv8i1(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i1> %1,
+    iXLen %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.th.vmand.nxv16i1(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i1>,
+  iXLen);
+
+define <vscale x 16 x i1> @intrinsic_vmand_mm_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, iXLen %2) nounwind {
+; CHECK-LABEL: intrinsic_vmand_mm_nxv16i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    csrr a1, vl
+; CHECK-NEXT:    csrr a2, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a1, a2
+; CHECK-NEXT:    csrr a1, vl
+; CHECK-NEXT:    csrr a2, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a1, a2
+; CHECK-NEXT:    th.vsetvli zero, a0, e8, m2, d1
+; CHECK-NEXT:    th.vmand.mm v0, v0, v8
+; CHECK-NEXT:    csrr a0, vl
+; CHECK-NEXT:    csrr a1, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a0, a1
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 16 x i1> @llvm.riscv.th.vmand.nxv16i1(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i1> %1,
+    iXLen %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.th.vmand.nxv32i1(
+  <vscale x 32 x i1>,
+  <vscale x 32 x i1>,
+  iXLen);
+
+define <vscale x 32 x i1> @intrinsic_vmand_mm_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, iXLen %2) nounwind {
+; CHECK-LABEL: intrinsic_vmand_mm_nxv32i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    csrr a1, vl
+; CHECK-NEXT:    csrr a2, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a1, a2
+; CHECK-NEXT:    csrr a1, vl
+; CHECK-NEXT:    csrr a2, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a1, a2
+; CHECK-NEXT:    th.vsetvli zero, a0, e8, m4, d1
+; CHECK-NEXT:    th.vmand.mm v0, v0, v8
+; CHECK-NEXT:    csrr a0, vl
+; CHECK-NEXT:    csrr a1, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a0, a1
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 32 x i1> @llvm.riscv.th.vmand.nxv32i1(
+    <vscale x 32 x i1> %0,
+    <vscale x 32 x i1> %1,
+    iXLen %2)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 64 x i1> @llvm.riscv.th.vmand.nxv64i1(
+  <vscale x 64 x i1>,
+  <vscale x 64 x i1>,
+  iXLen);
+
+define <vscale x 64 x i1> @intrinsic_vmand_mm_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, iXLen %2) nounwind {
+; CHECK-LABEL: intrinsic_vmand_mm_nxv64i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    csrr a1, vl
+; CHECK-NEXT:    csrr a2, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a1, a2
+; CHECK-NEXT:    csrr a1, vl
+; CHECK-NEXT:    csrr a2, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a1, a2
+; CHECK-NEXT:    th.vsetvli zero, a0, e8, m8, d1
+; CHECK-NEXT:    th.vmand.mm v0, v0, v8
+; CHECK-NEXT:    csrr a0, vl
+; CHECK-NEXT:    csrr a1, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a0, a1
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 64 x i1> @llvm.riscv.th.vmand.nxv64i1(
+    <vscale x 64 x i1> %0,
+    <vscale x 64 x i1> %1,
+    iXLen %2)
+
+  ret <vscale x 64 x i1> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv0p71/vmandn.ll b/llvm/test/CodeGen/RISCV/rvv0p71/vmandn.ll
new file mode 100644
index 00000000000000..b765f74ee32066
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv0p71/vmandn.ll
@@ -0,0 +1,130 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+xtheadvector \
+; RUN:   -verify-machineinstrs | FileCheck %s
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+xtheadvector \
+; RUN:   -verify-machineinstrs | FileCheck %s
+
+declare <vscale x 8 x i1> @llvm.riscv.th.vmandnot.nxv8i1(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i1>,
+  iXLen);
+
+define <vscale x 8 x i1> @intrinsic_vmandn_mm_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, iXLen %2) nounwind {
+; CHECK-LABEL: intrinsic_vmandn_mm_nxv8i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    csrr a1, vl
+; CHECK-NEXT:    csrr a2, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a1, a2
+; CHECK-NEXT:    csrr a1, vl
+; CHECK-NEXT:    csrr a2, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a1, a2
+; CHECK-NEXT:    th.vsetvli zero, a0, e8, m1, d1
+; CHECK-NEXT:    th.vmandnot.mm v0, v0, v8
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 8 x i1> @llvm.riscv.th.vmandnot.nxv8i1(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i1> %1,
+    iXLen %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.th.vmandnot.nxv16i1(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i1>,
+  iXLen);
+
+define <vscale x 16 x i1> @intrinsic_vmandn_mm_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, iXLen %2) nounwind {
+; CHECK-LABEL: intrinsic_vmandn_mm_nxv16i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    csrr a1, vl
+; CHECK-NEXT:    csrr a2, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a1, a2
+; CHECK-NEXT:    csrr a1, vl
+; CHECK-NEXT:    csrr a2, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a1, a2
+; CHECK-NEXT:    th.vsetvli zero, a0, e8, m2, d1
+; CHECK-NEXT:    th.vmandnot.mm v0, v0, v8
+; CHECK-NEXT:    csrr a0, vl
+; CHECK-NEXT:    csrr a1, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a0, a1
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 16 x i1> @llvm.riscv.th.vmandnot.nxv16i1(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i1> %1,
+    iXLen %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.th.vmandnot.nxv32i1(
+  <vscale x 32 x i1>,
+  <vscale x 32 x i1>,
+  iXLen);
+
+define <vscale x 32 x i1> @intrinsic_vmandn_mm_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, iXLen %2) nounwind {
+; CHECK-LABEL: intrinsic_vmandn_mm_nxv32i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    csrr a1, vl
+; CHECK-NEXT:    csrr a2, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a1, a2
+; CHECK-NEXT:    csrr a1, vl
+; CHECK-NEXT:    csrr a2, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a1, a2
+; CHECK-NEXT:    th.vsetvli zero, a0, e8, m4, d1
+; CHECK-NEXT:    th.vmandnot.mm v0, v0, v8
+; CHECK-NEXT:    csrr a0, vl
+; CHECK-NEXT:    csrr a1, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a0, a1
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 32 x i1> @llvm.riscv.th.vmandnot.nxv32i1(
+    <vscale x 32 x i1> %0,
+    <vscale x 32 x i1> %1,
+    iXLen %2)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 64 x i1> @llvm.riscv.th.vmandnot.nxv64i1(
+  <vscale x 64 x i1>,
+  <vscale x 64 x i1>,
+  iXLen);
+
+define <vscale x 64 x i1> @intrinsic_vmandn_mm_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, iXLen %2) nounwind {
+; CHECK-LABEL: intrinsic_vmandn_mm_nxv64i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    csrr a1, vl
+; CHECK-NEXT:    csrr a2, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a1, a2
+; CHECK-NEXT:    csrr a1, vl
+; CHECK-NEXT:    csrr a2, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a1, a2
+; CHECK-NEXT:    th.vsetvli zero, a0, e8, m8, d1
+; CHECK-NEXT:    th.vmandnot.mm v0, v0, v8
+; CHECK-NEXT:    csrr a0, vl
+; CHECK-NEXT:    csrr a1, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a0, a1
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 64 x i1> @llvm.riscv.th.vmandnot.nxv64i1(
+    <vscale x 64 x i1> %0,
+    <vscale x 64 x i1> %1,
+    iXLen %2)
+
+  ret <vscale x 64 x i1> %a
+}
+
diff --git a/llvm/test/CodeGen/RISCV/rvv0p71/vmclr.ll b/llvm/test/CodeGen/RISCV/rvv0p71/vmclr.ll
new file mode 100644
index 00000000000000..94d9c421524de5
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv0p71/vmclr.ll
@@ -0,0 +1,81 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+xtheadvector \
+; RUN:   -verify-machineinstrs | FileCheck %s
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+xtheadvector \
+; RUN:   -verify-machineinstrs | FileCheck %s
+
+declare <vscale x 8 x i1> @llvm.riscv.th.vmclr.nxv8i1(
+  iXLen);
+
+define <vscale x 8 x i1> @intrinsic_vmclr_m_pseudo_nxv8i1(iXLen %0) nounwind {
+; CHECK-LABEL: intrinsic_vmclr_m_pseudo_nxv8i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    th.vsetvli zero, a0, e8, m1, d1
+; CHECK-NEXT:    th.vmclr.m v0
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 8 x i1> @llvm.riscv.th.vmclr.nxv8i1(
+    iXLen %0)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.th.vmclr.nxv16i1(
+  iXLen);
+
+define <vscale x 16 x i1> @intrinsic_vmclr_m_pseudo_nxv16i1(iXLen %0) nounwind {
+; CHECK-LABEL: intrinsic_vmclr_m_pseudo_nxv16i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    th.vsetvli zero, a0, e8, m2, d1
+; CHECK-NEXT:    th.vmclr.m v0
+; CHECK-NEXT:    csrr a0, vl
+; CHECK-NEXT:    csrr a1, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a0, a1
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 16 x i1> @llvm.riscv.th.vmclr.nxv16i1(
+    iXLen %0)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.th.vmclr.nxv32i1(
+  iXLen);
+
+define <vscale x 32 x i1> @intrinsic_vmclr_m_pseudo_nxv32i1(iXLen %0) nounwind {
+; CHECK-LABEL: intrinsic_vmclr_m_pseudo_nxv32i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    th.vsetvli zero, a0, e8, m4, d1
+; CHECK-NEXT:    th.vmclr.m v0
+; CHECK-NEXT:    csrr a0, vl
+; CHECK-NEXT:    csrr a1, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a0, a1
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 32 x i1> @llvm.riscv.th.vmclr.nxv32i1(
+    iXLen %0)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 64 x i1> @llvm.riscv.th.vmclr.nxv64i1(
+  iXLen);
+
+define <vscale x 64 x i1> @intrinsic_vmclr_m_pseudo_nxv64i1(iXLen %0) nounwind {
+; CHECK-LABEL: intrinsic_vmclr_m_pseudo_nxv64i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    th.vsetvli zero, a0, e8, m8, d1
+; CHECK-NEXT:    th.vmclr.m v0
+; CHECK-NEXT:    csrr a0, vl
+; CHECK-NEXT:    csrr a1, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a0, a1
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 64 x i1> @llvm.riscv.th.vmclr.nxv64i1(
+    iXLen %0)
+
+  ret <vscale x 64 x i1> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv0p71/vmnand.ll b/llvm/test/CodeGen/RISCV/rvv0p71/vmnand.ll
new file mode 100644
index 00000000000000..6dedd8b4675495
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv0p71/vmnand.ll
@@ -0,0 +1,129 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+xtheadvector \
+; RUN:   -verify-machineinstrs | FileCheck %s
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+xtheadvector \
+; RUN:   -verify-machineinstrs | FileCheck %s
+
+declare <vscale x 8 x i1> @llvm.riscv.th.vmnand.nxv8i1(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i1>,
+  iXLen);
+
+define <vscale x 8 x i1> @intrinsic_vmnand_mm_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, iXLen %2) nounwind {
+; CHECK-LABEL: intrinsic_vmnand_mm_nxv8i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    csrr a1, vl
+; CHECK-NEXT:    csrr a2, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a1, a2
+; CHECK-NEXT:    csrr a1, vl
+; CHECK-NEXT:    csrr a2, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a1, a2
+; CHECK-NEXT:    th.vsetvli zero, a0, e8, m1, d1
+; CHECK-NEXT:    th.vmnand.mm v0, v0, v8
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 8 x i1> @llvm.riscv.th.vmnand.nxv8i1(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i1> %1,
+    iXLen %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.th.vmnand.nxv16i1(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i1>,
+  iXLen);
+
+define <vscale x 16 x i1> @intrinsic_vmnand_mm_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, iXLen %2) nounwind {
+; CHECK-LABEL: intrinsic_vmnand_mm_nxv16i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    csrr a1, vl
+; CHECK-NEXT:    csrr a2, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a1, a2
+; CHECK-NEXT:    csrr a1, vl
+; CHECK-NEXT:    csrr a2, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a1, a2
+; CHECK-NEXT:    th.vsetvli zero, a0, e8, m2, d1
+; CHECK-NEXT:    th.vmnand.mm v0, v0, v8
+; CHECK-NEXT:    csrr a0, vl
+; CHECK-NEXT:    csrr a1, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a0, a1
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 16 x i1> @llvm.riscv.th.vmnand.nxv16i1(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i1> %1,
+    iXLen %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.th.vmnand.nxv32i1(
+  <vscale x 32 x i1>,
+  <vscale x 32 x i1>,
+  iXLen);
+
+define <vscale x 32 x i1> @intrinsic_vmnand_mm_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, iXLen %2) nounwind {
+; CHECK-LABEL: intrinsic_vmnand_mm_nxv32i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    csrr a1, vl
+; CHECK-NEXT:    csrr a2, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a1, a2
+; CHECK-NEXT:    csrr a1, vl
+; CHECK-NEXT:    csrr a2, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a1, a2
+; CHECK-NEXT:    th.vsetvli zero, a0, e8, m4, d1
+; CHECK-NEXT:    th.vmnand.mm v0, v0, v8
+; CHECK-NEXT:    csrr a0, vl
+; CHECK-NEXT:    csrr a1, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a0, a1
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 32 x i1> @llvm.riscv.th.vmnand.nxv32i1(
+    <vscale x 32 x i1> %0,
+    <vscale x 32 x i1> %1,
+    iXLen %2)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 64 x i1> @llvm.riscv.th.vmnand.nxv64i1(
+  <vscale x 64 x i1>,
+  <vscale x 64 x i1>,
+  iXLen);
+
+define <vscale x 64 x i1> @intrinsic_vmnand_mm_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, iXLen %2) nounwind {
+; CHECK-LABEL: intrinsic_vmnand_mm_nxv64i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    csrr a1, vl
+; CHECK-NEXT:    csrr a2, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a1, a2
+; CHECK-NEXT:    csrr a1, vl
+; CHECK-NEXT:    csrr a2, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a1, a2
+; CHECK-NEXT:    th.vsetvli zero, a0, e8, m8, d1
+; CHECK-NEXT:    th.vmnand.mm v0, v0, v8
+; CHECK-NEXT:    csrr a0, vl
+; CHECK-NEXT:    csrr a1, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a0, a1
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 64 x i1> @llvm.riscv.th.vmnand.nxv64i1(
+    <vscale x 64 x i1> %0,
+    <vscale x 64 x i1> %1,
+    iXLen %2)
+
+  ret <vscale x 64 x i1> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv0p71/vmnor.ll b/llvm/test/CodeGen/RISCV/rvv0p71/vmnor.ll
new file mode 100644
index 00000000000000..c0f8f261f8c58a
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv0p71/vmnor.ll
@@ -0,0 +1,129 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+xtheadvector \
+; RUN:   -verify-machineinstrs | FileCheck %s
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+xtheadvector \
+; RUN:   -verify-machineinstrs | FileCheck %s
+
+declare <vscale x 8 x i1> @llvm.riscv.th.vmnor.nxv8i1(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i1>,
+  iXLen);
+
+define <vscale x 8 x i1> @intrinsic_vmnor_mm_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, iXLen %2) nounwind {
+; CHECK-LABEL: intrinsic_vmnor_mm_nxv8i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    csrr a1, vl
+; CHECK-NEXT:    csrr a2, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a1, a2
+; CHECK-NEXT:    csrr a1, vl
+; CHECK-NEXT:    csrr a2, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a1, a2
+; CHECK-NEXT:    th.vsetvli zero, a0, e8, m1, d1
+; CHECK-NEXT:    th.vmnor.mm v0, v0, v8
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 8 x i1> @llvm.riscv.th.vmnor.nxv8i1(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i1> %1,
+    iXLen %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.th.vmnor.nxv16i1(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i1>,
+  iXLen);
+
+define <vscale x 16 x i1> @intrinsic_vmnor_mm_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, iXLen %2) nounwind {
+; CHECK-LABEL: intrinsic_vmnor_mm_nxv16i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    csrr a1, vl
+; CHECK-NEXT:    csrr a2, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a1, a2
+; CHECK-NEXT:    csrr a1, vl
+; CHECK-NEXT:    csrr a2, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a1, a2
+; CHECK-NEXT:    th.vsetvli zero, a0, e8, m2, d1
+; CHECK-NEXT:    th.vmnor.mm v0, v0, v8
+; CHECK-NEXT:    csrr a0, vl
+; CHECK-NEXT:    csrr a1, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a0, a1
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 16 x i1> @llvm.riscv.th.vmnor.nxv16i1(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i1> %1,
+    iXLen %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.th.vmnor.nxv32i1(
+  <vscale x 32 x i1>,
+  <vscale x 32 x i1>,
+  iXLen);
+
+define <vscale x 32 x i1> @intrinsic_vmnor_mm_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, iXLen %2) nounwind {
+; CHECK-LABEL: intrinsic_vmnor_mm_nxv32i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    csrr a1, vl
+; CHECK-NEXT:    csrr a2, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a1, a2
+; CHECK-NEXT:    csrr a1, vl
+; CHECK-NEXT:    csrr a2, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a1, a2
+; CHECK-NEXT:    th.vsetvli zero, a0, e8, m4, d1
+; CHECK-NEXT:    th.vmnor.mm v0, v0, v8
+; CHECK-NEXT:    csrr a0, vl
+; CHECK-NEXT:    csrr a1, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a0, a1
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 32 x i1> @llvm.riscv.th.vmnor.nxv32i1(
+    <vscale x 32 x i1> %0,
+    <vscale x 32 x i1> %1,
+    iXLen %2)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 64 x i1> @llvm.riscv.th.vmnor.nxv64i1(
+  <vscale x 64 x i1>,
+  <vscale x 64 x i1>,
+  iXLen);
+
+define <vscale x 64 x i1> @intrinsic_vmnor_mm_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, iXLen %2) nounwind {
+; CHECK-LABEL: intrinsic_vmnor_mm_nxv64i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    csrr a1, vl
+; CHECK-NEXT:    csrr a2, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a1, a2
+; CHECK-NEXT:    csrr a1, vl
+; CHECK-NEXT:    csrr a2, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a1, a2
+; CHECK-NEXT:    th.vsetvli zero, a0, e8, m8, d1
+; CHECK-NEXT:    th.vmnor.mm v0, v0, v8
+; CHECK-NEXT:    csrr a0, vl
+; CHECK-NEXT:    csrr a1, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a0, a1
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 64 x i1> @llvm.riscv.th.vmnor.nxv64i1(
+    <vscale x 64 x i1> %0,
+    <vscale x 64 x i1> %1,
+    iXLen %2)
+
+  ret <vscale x 64 x i1> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv0p71/vmor.ll b/llvm/test/CodeGen/RISCV/rvv0p71/vmor.ll
new file mode 100644
index 00000000000000..07942bab453801
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv0p71/vmor.ll
@@ -0,0 +1,129 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+xtheadvector \
+; RUN:   -verify-machineinstrs | FileCheck %s
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+xtheadvector \
+; RUN:   -verify-machineinstrs | FileCheck %s
+
+declare <vscale x 8 x i1> @llvm.riscv.th.vmor.nxv8i1(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i1>,
+  iXLen);
+
+define <vscale x 8 x i1> @intrinsic_vmor_mm_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, iXLen %2) nounwind {
+; CHECK-LABEL: intrinsic_vmor_mm_nxv8i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    csrr a1, vl
+; CHECK-NEXT:    csrr a2, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a1, a2
+; CHECK-NEXT:    csrr a1, vl
+; CHECK-NEXT:    csrr a2, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a1, a2
+; CHECK-NEXT:    th.vsetvli zero, a0, e8, m1, d1
+; CHECK-NEXT:    th.vmor.mm v0, v0, v8
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 8 x i1> @llvm.riscv.th.vmor.nxv8i1(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i1> %1,
+    iXLen %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.th.vmor.nxv16i1(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i1>,
+  iXLen);
+
+define <vscale x 16 x i1> @intrinsic_vmor_mm_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, iXLen %2) nounwind {
+; CHECK-LABEL: intrinsic_vmor_mm_nxv16i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    csrr a1, vl
+; CHECK-NEXT:    csrr a2, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a1, a2
+; CHECK-NEXT:    csrr a1, vl
+; CHECK-NEXT:    csrr a2, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a1, a2
+; CHECK-NEXT:    th.vsetvli zero, a0, e8, m2, d1
+; CHECK-NEXT:    th.vmor.mm v0, v0, v8
+; CHECK-NEXT:    csrr a0, vl
+; CHECK-NEXT:    csrr a1, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a0, a1
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 16 x i1> @llvm.riscv.th.vmor.nxv16i1(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i1> %1,
+    iXLen %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.th.vmor.nxv32i1(
+  <vscale x 32 x i1>,
+  <vscale x 32 x i1>,
+  iXLen);
+
+define <vscale x 32 x i1> @intrinsic_vmor_mm_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, iXLen %2) nounwind {
+; CHECK-LABEL: intrinsic_vmor_mm_nxv32i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    csrr a1, vl
+; CHECK-NEXT:    csrr a2, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a1, a2
+; CHECK-NEXT:    csrr a1, vl
+; CHECK-NEXT:    csrr a2, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a1, a2
+; CHECK-NEXT:    th.vsetvli zero, a0, e8, m4, d1
+; CHECK-NEXT:    th.vmor.mm v0, v0, v8
+; CHECK-NEXT:    csrr a0, vl
+; CHECK-NEXT:    csrr a1, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a0, a1
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 32 x i1> @llvm.riscv.th.vmor.nxv32i1(
+    <vscale x 32 x i1> %0,
+    <vscale x 32 x i1> %1,
+    iXLen %2)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 64 x i1> @llvm.riscv.th.vmor.nxv64i1(
+  <vscale x 64 x i1>,
+  <vscale x 64 x i1>,
+  iXLen);
+
+define <vscale x 64 x i1> @intrinsic_vmor_mm_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, iXLen %2) nounwind {
+; CHECK-LABEL: intrinsic_vmor_mm_nxv64i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    csrr a1, vl
+; CHECK-NEXT:    csrr a2, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a1, a2
+; CHECK-NEXT:    csrr a1, vl
+; CHECK-NEXT:    csrr a2, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a1, a2
+; CHECK-NEXT:    th.vsetvli zero, a0, e8, m8, d1
+; CHECK-NEXT:    th.vmor.mm v0, v0, v8
+; CHECK-NEXT:    csrr a0, vl
+; CHECK-NEXT:    csrr a1, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a0, a1
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 64 x i1> @llvm.riscv.th.vmor.nxv64i1(
+    <vscale x 64 x i1> %0,
+    <vscale x 64 x i1> %1,
+    iXLen %2)
+
+  ret <vscale x 64 x i1> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv0p71/vmorn.ll b/llvm/test/CodeGen/RISCV/rvv0p71/vmorn.ll
new file mode 100644
index 00000000000000..ba4e9ae9a36742
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv0p71/vmorn.ll
@@ -0,0 +1,129 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+xtheadvector \
+; RUN:   -verify-machineinstrs | FileCheck %s
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+xtheadvector \
+; RUN:   -verify-machineinstrs | FileCheck %s
+
+declare <vscale x 8 x i1> @llvm.riscv.th.vmornot.nxv8i1(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i1>,
+  iXLen);
+
+define <vscale x 8 x i1> @intrinsic_vmornot_mm_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, iXLen %2) nounwind {
+; CHECK-LABEL: intrinsic_vmornot_mm_nxv8i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    csrr a1, vl
+; CHECK-NEXT:    csrr a2, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a1, a2
+; CHECK-NEXT:    csrr a1, vl
+; CHECK-NEXT:    csrr a2, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a1, a2
+; CHECK-NEXT:    th.vsetvli zero, a0, e8, m1, d1
+; CHECK-NEXT:    th.vmornot.mm v0, v0, v8
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 8 x i1> @llvm.riscv.th.vmornot.nxv8i1(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i1> %1,
+    iXLen %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.th.vmornot.nxv16i1(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i1>,
+  iXLen);
+
+define <vscale x 16 x i1> @intrinsic_vmornot_mm_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, iXLen %2) nounwind {
+; CHECK-LABEL: intrinsic_vmornot_mm_nxv16i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    csrr a1, vl
+; CHECK-NEXT:    csrr a2, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a1, a2
+; CHECK-NEXT:    csrr a1, vl
+; CHECK-NEXT:    csrr a2, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a1, a2
+; CHECK-NEXT:    th.vsetvli zero, a0, e8, m2, d1
+; CHECK-NEXT:    th.vmornot.mm v0, v0, v8
+; CHECK-NEXT:    csrr a0, vl
+; CHECK-NEXT:    csrr a1, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a0, a1
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 16 x i1> @llvm.riscv.th.vmornot.nxv16i1(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i1> %1,
+    iXLen %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.th.vmornot.nxv32i1(
+  <vscale x 32 x i1>,
+  <vscale x 32 x i1>,
+  iXLen);
+
+define <vscale x 32 x i1> @intrinsic_vmornot_mm_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, iXLen %2) nounwind {
+; CHECK-LABEL: intrinsic_vmornot_mm_nxv32i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    csrr a1, vl
+; CHECK-NEXT:    csrr a2, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a1, a2
+; CHECK-NEXT:    csrr a1, vl
+; CHECK-NEXT:    csrr a2, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a1, a2
+; CHECK-NEXT:    th.vsetvli zero, a0, e8, m4, d1
+; CHECK-NEXT:    th.vmornot.mm v0, v0, v8
+; CHECK-NEXT:    csrr a0, vl
+; CHECK-NEXT:    csrr a1, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a0, a1
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 32 x i1> @llvm.riscv.th.vmornot.nxv32i1(
+    <vscale x 32 x i1> %0,
+    <vscale x 32 x i1> %1,
+    iXLen %2)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 64 x i1> @llvm.riscv.th.vmornot.nxv64i1(
+  <vscale x 64 x i1>,
+  <vscale x 64 x i1>,
+  iXLen);
+
+define <vscale x 64 x i1> @intrinsic_vmornot_mm_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, iXLen %2) nounwind {
+; CHECK-LABEL: intrinsic_vmornot_mm_nxv64i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    csrr a1, vl
+; CHECK-NEXT:    csrr a2, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a1, a2
+; CHECK-NEXT:    csrr a1, vl
+; CHECK-NEXT:    csrr a2, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a1, a2
+; CHECK-NEXT:    th.vsetvli zero, a0, e8, m8, d1
+; CHECK-NEXT:    th.vmornot.mm v0, v0, v8
+; CHECK-NEXT:    csrr a0, vl
+; CHECK-NEXT:    csrr a1, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a0, a1
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 64 x i1> @llvm.riscv.th.vmornot.nxv64i1(
+    <vscale x 64 x i1> %0,
+    <vscale x 64 x i1> %1,
+    iXLen %2)
+
+  ret <vscale x 64 x i1> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv0p71/vmset.ll b/llvm/test/CodeGen/RISCV/rvv0p71/vmset.ll
new file mode 100644
index 00000000000000..b856177afdef26
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv0p71/vmset.ll
@@ -0,0 +1,81 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+xtheadvector \
+; RUN:   -verify-machineinstrs | FileCheck %s
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+xtheadvector \
+; RUN:   -verify-machineinstrs | FileCheck %s
+
+declare <vscale x 8 x i1> @llvm.riscv.th.vmset.nxv8i1(
+  iXLen);
+
+define <vscale x 8 x i1> @intrinsic_vmset_m_pseudo_nxv8i1(iXLen %0) nounwind {
+; CHECK-LABEL: intrinsic_vmset_m_pseudo_nxv8i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    th.vsetvli zero, a0, e8, m1, d1
+; CHECK-NEXT:    th.vmset.m v0
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 8 x i1> @llvm.riscv.th.vmset.nxv8i1(
+    iXLen %0)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.th.vmset.nxv16i1(
+  iXLen);
+
+define <vscale x 16 x i1> @intrinsic_vmset_m_pseudo_nxv16i1(iXLen %0) nounwind {
+; CHECK-LABEL: intrinsic_vmset_m_pseudo_nxv16i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    th.vsetvli zero, a0, e8, m2, d1
+; CHECK-NEXT:    th.vmset.m v0
+; CHECK-NEXT:    csrr a0, vl
+; CHECK-NEXT:    csrr a1, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a0, a1
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 16 x i1> @llvm.riscv.th.vmset.nxv16i1(
+    iXLen %0)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.th.vmset.nxv32i1(
+  iXLen);
+
+define <vscale x 32 x i1> @intrinsic_vmset_m_pseudo_nxv32i1(iXLen %0) nounwind {
+; CHECK-LABEL: intrinsic_vmset_m_pseudo_nxv32i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    th.vsetvli zero, a0, e8, m4, d1
+; CHECK-NEXT:    th.vmset.m v0
+; CHECK-NEXT:    csrr a0, vl
+; CHECK-NEXT:    csrr a1, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a0, a1
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 32 x i1> @llvm.riscv.th.vmset.nxv32i1(
+    iXLen %0)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 64 x i1> @llvm.riscv.th.vmset.nxv64i1(
+  iXLen);
+
+define <vscale x 64 x i1> @intrinsic_vmset_m_pseudo_nxv64i1(iXLen %0) nounwind {
+; CHECK-LABEL: intrinsic_vmset_m_pseudo_nxv64i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    th.vsetvli zero, a0, e8, m8, d1
+; CHECK-NEXT:    th.vmset.m v0
+; CHECK-NEXT:    csrr a0, vl
+; CHECK-NEXT:    csrr a1, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a0, a1
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 64 x i1> @llvm.riscv.th.vmset.nxv64i1(
+    iXLen %0)
+
+  ret <vscale x 64 x i1> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv0p71/vmxnor.ll b/llvm/test/CodeGen/RISCV/rvv0p71/vmxnor.ll
new file mode 100644
index 00000000000000..dc37f497a1dea6
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv0p71/vmxnor.ll
@@ -0,0 +1,129 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+xtheadvector \
+; RUN:   -verify-machineinstrs | FileCheck %s
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+xtheadvector \
+; RUN:   -verify-machineinstrs | FileCheck %s
+
+declare <vscale x 8 x i1> @llvm.riscv.th.vmxnor.nxv8i1(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i1>,
+  iXLen);
+
+define <vscale x 8 x i1> @intrinsic_vmxnor_mm_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, iXLen %2) nounwind {
+; CHECK-LABEL: intrinsic_vmxnor_mm_nxv8i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    csrr a1, vl
+; CHECK-NEXT:    csrr a2, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a1, a2
+; CHECK-NEXT:    csrr a1, vl
+; CHECK-NEXT:    csrr a2, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a1, a2
+; CHECK-NEXT:    th.vsetvli zero, a0, e8, m1, d1
+; CHECK-NEXT:    th.vmxnor.mm v0, v0, v8
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 8 x i1> @llvm.riscv.th.vmxnor.nxv8i1(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i1> %1,
+    iXLen %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.th.vmxnor.nxv16i1(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i1>,
+  iXLen);
+
+define <vscale x 16 x i1> @intrinsic_vmxnor_mm_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, iXLen %2) nounwind {
+; CHECK-LABEL: intrinsic_vmxnor_mm_nxv16i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    csrr a1, vl
+; CHECK-NEXT:    csrr a2, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a1, a2
+; CHECK-NEXT:    csrr a1, vl
+; CHECK-NEXT:    csrr a2, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a1, a2
+; CHECK-NEXT:    th.vsetvli zero, a0, e8, m2, d1
+; CHECK-NEXT:    th.vmxnor.mm v0, v0, v8
+; CHECK-NEXT:    csrr a0, vl
+; CHECK-NEXT:    csrr a1, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a0, a1
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 16 x i1> @llvm.riscv.th.vmxnor.nxv16i1(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i1> %1,
+    iXLen %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.th.vmxnor.nxv32i1(
+  <vscale x 32 x i1>,
+  <vscale x 32 x i1>,
+  iXLen);
+
+define <vscale x 32 x i1> @intrinsic_vmxnor_mm_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, iXLen %2) nounwind {
+; CHECK-LABEL: intrinsic_vmxnor_mm_nxv32i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    csrr a1, vl
+; CHECK-NEXT:    csrr a2, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a1, a2
+; CHECK-NEXT:    csrr a1, vl
+; CHECK-NEXT:    csrr a2, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a1, a2
+; CHECK-NEXT:    th.vsetvli zero, a0, e8, m4, d1
+; CHECK-NEXT:    th.vmxnor.mm v0, v0, v8
+; CHECK-NEXT:    csrr a0, vl
+; CHECK-NEXT:    csrr a1, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a0, a1
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 32 x i1> @llvm.riscv.th.vmxnor.nxv32i1(
+    <vscale x 32 x i1> %0,
+    <vscale x 32 x i1> %1,
+    iXLen %2)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 64 x i1> @llvm.riscv.th.vmxnor.nxv64i1(
+  <vscale x 64 x i1>,
+  <vscale x 64 x i1>,
+  iXLen);
+
+define <vscale x 64 x i1> @intrinsic_vmxnor_mm_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, iXLen %2) nounwind {
+; CHECK-LABEL: intrinsic_vmxnor_mm_nxv64i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    csrr a1, vl
+; CHECK-NEXT:    csrr a2, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a1, a2
+; CHECK-NEXT:    csrr a1, vl
+; CHECK-NEXT:    csrr a2, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a1, a2
+; CHECK-NEXT:    th.vsetvli zero, a0, e8, m8, d1
+; CHECK-NEXT:    th.vmxnor.mm v0, v0, v8
+; CHECK-NEXT:    csrr a0, vl
+; CHECK-NEXT:    csrr a1, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a0, a1
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 64 x i1> @llvm.riscv.th.vmxnor.nxv64i1(
+    <vscale x 64 x i1> %0,
+    <vscale x 64 x i1> %1,
+    iXLen %2)
+
+  ret <vscale x 64 x i1> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv0p71/vmxor.ll b/llvm/test/CodeGen/RISCV/rvv0p71/vmxor.ll
new file mode 100644
index 00000000000000..f3c59dba5122a4
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv0p71/vmxor.ll
@@ -0,0 +1,129 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+xtheadvector \
+; RUN:   -verify-machineinstrs | FileCheck %s
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+xtheadvector \
+; RUN:   -verify-machineinstrs | FileCheck %s
+
+declare <vscale x 8 x i1> @llvm.riscv.th.vmxor.nxv8i1(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i1>,
+  iXLen);
+
+define <vscale x 8 x i1> @intrinsic_vmxor_mm_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, iXLen %2) nounwind {
+; CHECK-LABEL: intrinsic_vmxor_mm_nxv8i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    csrr a1, vl
+; CHECK-NEXT:    csrr a2, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a1, a2
+; CHECK-NEXT:    csrr a1, vl
+; CHECK-NEXT:    csrr a2, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a1, a2
+; CHECK-NEXT:    th.vsetvli zero, a0, e8, m1, d1
+; CHECK-NEXT:    th.vmxor.mm v0, v0, v8
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 8 x i1> @llvm.riscv.th.vmxor.nxv8i1(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i1> %1,
+    iXLen %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.th.vmxor.nxv16i1(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i1>,
+  iXLen);
+
+define <vscale x 16 x i1> @intrinsic_vmxor_mm_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, iXLen %2) nounwind {
+; CHECK-LABEL: intrinsic_vmxor_mm_nxv16i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    csrr a1, vl
+; CHECK-NEXT:    csrr a2, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a1, a2
+; CHECK-NEXT:    csrr a1, vl
+; CHECK-NEXT:    csrr a2, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a1, a2
+; CHECK-NEXT:    th.vsetvli zero, a0, e8, m2, d1
+; CHECK-NEXT:    th.vmxor.mm v0, v0, v8
+; CHECK-NEXT:    csrr a0, vl
+; CHECK-NEXT:    csrr a1, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a0, a1
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 16 x i1> @llvm.riscv.th.vmxor.nxv16i1(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i1> %1,
+    iXLen %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.th.vmxor.nxv32i1(
+  <vscale x 32 x i1>,
+  <vscale x 32 x i1>,
+  iXLen);
+
+define <vscale x 32 x i1> @intrinsic_vmxor_mm_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, iXLen %2) nounwind {
+; CHECK-LABEL: intrinsic_vmxor_mm_nxv32i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    csrr a1, vl
+; CHECK-NEXT:    csrr a2, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a1, a2
+; CHECK-NEXT:    csrr a1, vl
+; CHECK-NEXT:    csrr a2, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a1, a2
+; CHECK-NEXT:    th.vsetvli zero, a0, e8, m4, d1
+; CHECK-NEXT:    th.vmxor.mm v0, v0, v8
+; CHECK-NEXT:    csrr a0, vl
+; CHECK-NEXT:    csrr a1, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a0, a1
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 32 x i1> @llvm.riscv.th.vmxor.nxv32i1(
+    <vscale x 32 x i1> %0,
+    <vscale x 32 x i1> %1,
+    iXLen %2)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 64 x i1> @llvm.riscv.th.vmxor.nxv64i1(
+  <vscale x 64 x i1>,
+  <vscale x 64 x i1>,
+  iXLen);
+
+define <vscale x 64 x i1> @intrinsic_vmxor_mm_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, iXLen %2) nounwind {
+; CHECK-LABEL: intrinsic_vmxor_mm_nxv64i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    csrr a1, vl
+; CHECK-NEXT:    csrr a2, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a1, a2
+; CHECK-NEXT:    csrr a1, vl
+; CHECK-NEXT:    csrr a2, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a1, a2
+; CHECK-NEXT:    th.vsetvli zero, a0, e8, m8, d1
+; CHECK-NEXT:    th.vmxor.mm v0, v0, v8
+; CHECK-NEXT:    csrr a0, vl
+; CHECK-NEXT:    csrr a1, vtype
+; CHECK-NEXT:    th.vsetvli zero, zero, e8, m1, d1
+; CHECK-NEXT:    th.vsetvl zero, a0, a1
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 64 x i1> @llvm.riscv.th.vmxor.nxv64i1(
+    <vscale x 64 x i1> %0,
+    <vscale x 64 x i1> %1,
+    iXLen %2)
+
+  ret <vscale x 64 x i1> %a
+}