From 658bbbfdc9797d815671f2ed94dabbe7445cc1f6 Mon Sep 17 00:00:00 2001
From: Sven Wu <sven.wu@amd.com>
Date: Tue, 21 May 2024 14:28:40 +0800
Subject: [PATCH] PFM/D/01-som: Update som tutorial to 2024.1

---
 .../Design_Tutorials/01-Edge-KV260/README.md  |   4 +-
 .../01-Edge-KV260/ref_files/Makefile          |   4 +-
 .../01-Edge-KV260/ref_files/description.json  |   6 +-
 .../ref_files/step1_vivado/system_step1.tcl   |  17 +-
 .../ref_files/step2_pfm/Makefile              |  25 +--
 .../ref_files/step2_pfm/platform_creation.py  |   6 +-
 .../ref_files/step3_validate/Makefile         |  45 +++--
 .../ref_files/step3_validate/makefile_vadd    | 167 ++++++++++++++++++
 .../Design_Tutorials/01-Edge-KV260/step1.md   |   4 +-
 .../Design_Tutorials/01-Edge-KV260/step2.md   |  26 +--
 .../Design_Tutorials/01-Edge-KV260/step3.md   |  28 +--
 11 files changed, 245 insertions(+), 87 deletions(-)
 create mode 100644 Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/ref_files/step3_validate/makefile_vadd

diff --git a/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/README.md b/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/README.md
index 899b60c32..2a9410f7b 100644
--- a/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/README.md
+++ b/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/README.md
@@ -8,7 +8,7 @@
 
 # Vitis Custom Embedded Platform Creation Example on KV260
 
-***Version: Vitis 2023.2***
+***Version: Vitis 2024.1***
 
 The [AMD Kria™ KV260 Vision AI Starter Kit](https://www.xilinx.com/products/som/kria/kv260-vision-starter-kit.html) is the development platform for Kria K26 SOM. The KV260 is built for advanced vision application development without requiring complex hardware design knowledge. It is based on the AMD UltraScale+™ MPSoC technology similar to ZCU104 evaluation board. In this example, you will extend the [ZCU104 custom embedded platform creation example](../02-Edge-AI-ZCU104/README.md) to KV260 Vision AI Starter Kit.
 
@@ -81,6 +81,6 @@ The platform creation steps are introduced in the following pages. Each page des
 - [Vitis-AI GitHub Repository](https://github.com/Xilinx/Vitis-AI)
 
 
-<p class="sphinxhide" align="center"><sub>Copyright © 2020–2023 Advanced Micro Devices, Inc</sub></p>
+<p class="sphinxhide" align="center"><sub>Copyright © 2020–2024 Advanced Micro Devices, Inc</sub></p>
 
 <p class="sphinxhide" align="center"><sup><a href="https://www.amd.com/en/corporate/copyright">Terms and Conditions</a></sup></p>
diff --git a/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/ref_files/Makefile b/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/ref_files/Makefile
index c2411e303..bc6186340 100644
--- a/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/ref_files/Makefile
+++ b/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/ref_files/Makefile
@@ -24,7 +24,7 @@ ifeq ($(wildcard $(COMMON_IMAGE_ZYNQMP)/Image),)
 endif
 	
 all: step1 step2 step3 
-
+build_platform: step1 step2
 step1:
 	$(MAKE) -C step1_vivado all
 
@@ -41,4 +41,4 @@ clean:
 	$(MAKE) -C step3_validate clean
 ultraclean:clean
 	$(MAKE) -C step2_pfm ultraclean
-	$(MAKE) -C step3_validate ultraclean
\ No newline at end of file
+	$(MAKE) -C step3_validate ultraclean
diff --git a/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/ref_files/description.json b/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/ref_files/description.json
index c5ee8e73b..ea0c6e9ce 100644
--- a/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/ref_files/description.json
+++ b/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/ref_files/description.json
@@ -11,10 +11,10 @@
         "disable": "true",
         "tasks": {
             "build": {
-                "pre_exec": "./env_setup_zynqmp.sh"
+                "pre_exec": "./env_setup_zynqmp_notoolchain.sh"
             },
             "board": {
-                "pre_exec": "./env_setup_zynqmp.sh"
+                "pre_exec": "./env_setup_zynqmp_notoolchain.sh"
             }
          },
         "jobs": [
@@ -30,7 +30,7 @@
         ],
         "custom_build_target":
         {
-            "all": "all"
+            "all": "build_platform"
         }
     }
 }
diff --git a/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/ref_files/step1_vivado/system_step1.tcl b/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/ref_files/step1_vivado/system_step1.tcl
index 39e0f77b6..ec52de0cd 100644
--- a/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/ref_files/step1_vivado/system_step1.tcl
+++ b/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/ref_files/step1_vivado/system_step1.tcl
@@ -2,6 +2,7 @@
 #Copyright (C) 2023, Advanced Micro Devices, Inc. All rights reserved.
 #SPDX-License-Identifier: MIT
 #*/
+
 ################################################################
 # This is a generated script based on design: system
 #
@@ -23,7 +24,7 @@ set script_folder [_tcl::get_script_folder]
 ################################################################
 # Check if script is running in correct Vivado version.
 ################################################################
-set scripts_vivado_version 2023.2
+set scripts_vivado_version 2024.1
 set current_vivado_version [version -short]
 
 if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
@@ -54,8 +55,6 @@ set list_projs [get_projects -quiet]
 if { $list_projs eq "" } {
    create_project project_1 myproj -part xck26-sfvc784-2LV-c
    set_property board_part xilinx.com:kv260_som:part0:1.4 [current_project]
-   set_property board_connections {som240_1_connector xilinx.com:kv260_carrier:som240_1_connector:1.3} [current_project]
-   set_property platform.extensible true [current_project]
 }
 
 
@@ -1063,12 +1062,12 @@ MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0
     CONFIG.PSU__PRESET_APPLIED {1} \
     CONFIG.PSU__PROTECTION__DDR_SEGMENTS {NONE} \
     CONFIG.PSU__PROTECTION__ENABLE {0} \
-    CONFIG.PSU__PROTECTION__FPD_SEGMENTS {SA:0xFD1A0000; SIZE:1280; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware |  SA:0xFD000000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\
-subsystemId:PMU Firmware |  SA:0xFD010000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware |  SA:0xFD020000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU\
-Firmware |  SA:0xFD030000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware |  SA:0xFD040000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware\
-|  SA:0xFD050000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware |  SA:0xFD610000; SIZE:512; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware\
-|  SA:0xFD5D0000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD1A0000 ; SIZE:1280; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem}\
-\
+    CONFIG.PSU__PROTECTION__FPD_SEGMENTS {SA:0xFD1A0000; SIZE:1280; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware  |   SA:0xFD000000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\
+subsystemId:PMU Firmware  |   SA:0xFD010000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware  |   SA:0xFD020000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\
+subsystemId:PMU Firmware  |   SA:0xFD030000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware  |   SA:0xFD040000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\
+subsystemId:PMU Firmware  |   SA:0xFD050000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware  |   SA:0xFD610000; SIZE:512; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\
+subsystemId:PMU Firmware  |   SA:0xFD5D0000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware  |  SA:0xFD1A0000 ; SIZE:1280; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write;\
+subsystemId:Secure Subsystem} \
     CONFIG.PSU__PROTECTION__LPD_SEGMENTS {SA:0xFF980000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFF5E0000; SIZE:2560; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\
 subsystemId:PMU Firmware| SA:0xFFCC0000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFF180000; SIZE:768; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU\
 Firmware| SA:0xFF410000; SIZE:640; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFFA70000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware|\
diff --git a/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/ref_files/step2_pfm/Makefile b/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/ref_files/step2_pfm/Makefile
index 4e0049f85..5a6112a7e 100644
--- a/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/ref_files/step2_pfm/Makefile
+++ b/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/ref_files/step2_pfm/Makefile
@@ -5,7 +5,7 @@
 
 ROOT_DIR=$(realpath $(dir $(lastword $(MAKEFILE_LIST))))
 PLATFORM_NAME=kv260_custom
-PLATFORM_NAME_FSBL=kv260_custom_fsbl
+
 XSA_NAME=kv260_hardware_platform
 VERSION=2024.1
 COMMON_IMAGE_ZYNQMP ?=${PLATFORM_REPO_PATHS}/sw/zynqmp/xilinx-zynqmp-common-v$(VERSION)/
@@ -13,7 +13,11 @@ DT_PLAT_NAME=mydeivice
 DT_PATH=$(ROOT_DIR)/$(DT_PLAT_NAME)/psu_cortexa53_0/device_tree_domain/bsp
 DTB =$(ROOT_DIR)/$(DT_PLAT_NAME)/psu_cortexa53_0/device_tree_domain/bsp/system.dtb
 
-SYSROOT=sysroot
+DEVICE_TREE_REPO ?=
+
+#ifndef DEVICE_TREE_REPO
+DEVICE_TREE_REPO=https://github.com/Xilinx/device-tree-xlnx.git
+#endif
 
 
 .PHONY: help 
@@ -23,7 +27,7 @@ help:
 	@echo "make all COMMON_IMAGE_ZYNQMP=<path/to/common_image/>  	## Generate platform with pre-built software components"
 	
 
-all: check-common-image dtb dtbo pfm sysroot
+all: check-common-image dtb dtbo pfm 
 
 #target : check  whether the common image is ready 
 check-common-image:
@@ -50,22 +54,11 @@ pfm:
 	@echo "INFO: Creating  Platform $(PLATFORM_NAME)"
 	mkdir -p tmp && export XILINX_VITIS_DATA_DIR="./tmp" && vitis -s platform_creation.py --platform_name $(PLATFORM_NAME) --xsa_path ../step1_vivado/build/vivado/$(XSA_NAME).xsa --boot $(COMMON_IMAGE_ZYNQMP) --dtb $(DTB)
 	@echo "INFO: Checking created platforms:" && find . -name "*.xpfm"
-#install SDK tool
-sysroot: $(SYSROOT)
-
-$(SYSROOT): $(COMMON_IMAGE_ZYNQMP)/sdk.sh
-	mkdir -p $(SYSROOT) && sh $(COMMON_IMAGE_ZYNQMP)/sdk.sh -d  $(SYSROOT)/ -y
-
 
  
-#install SDK tool
-sysroot: $(SYSROOT)
-
-$(SYSROOT): $(COMMON_IMAGE_ZYNQMP)/sdk.sh
-	mkdir -p $(SYSROOT) && sh $(COMMON_IMAGE_ZYNQMP)/sdk.sh -d  $(SYSROOT)/ -y
 
 clean:
-	$(RM) -r IDE.log $(PLATFORM_NAME) $(PLATFORM_NAME_FSBL) device-tree-xlnx  mydevice dt_output dtg dtbo_output
+	rm -rf IDE.log $(PLATFORM_NAME) $(DT_PLAT_NAME) dt_output dtbo_output
 
 ultraclean: clean
-	$(RM) -r   sysroot
+	rm -rf   device-tree-xlnx tmp logs
diff --git a/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/ref_files/step2_pfm/platform_creation.py b/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/ref_files/step2_pfm/platform_creation.py
index b76fd7b2d..e82f39c1d 100644
--- a/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/ref_files/step2_pfm/platform_creation.py
+++ b/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/ref_files/step2_pfm/platform_creation.py
@@ -22,12 +22,12 @@
 print('args',args)
 client = vitis.create_client()
 client.set_workspace(path=os.getcwd())
-platform = client.create_platform_component(name = platform_name, hw =xsa_path, os = "linux",cpu = "psu_cortexa53" )
-platform = client.get_platform_component(name=platform_name)
+platform = client.create_platform_component(name = platform_name, hw_design =xsa_path, os = "linux",cpu = "psu_cortexa53" )
+platform = client.get_component(name=platform_name)
 domain = platform.get_domain(name="linux_psu_cortexa53")
 status = domain.update_name(new_name="xrt")
 status = domain.generate_bif() 
-status = domain.add_boot_dir(path=boot)
+status = domain.set_boot_dir(path=boot)
 status = domain.set_dtb(path=dtb)
 
 status = platform.build()
diff --git a/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/ref_files/step3_validate/Makefile b/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/ref_files/step3_validate/Makefile
index b56ee221a..a2eb44590 100644
--- a/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/ref_files/step3_validate/Makefile
+++ b/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/ref_files/step3_validate/Makefile
@@ -6,11 +6,11 @@
 ROOT_DIR=$(realpath $(dir $(lastword $(MAKEFILE_LIST))))
 PLATFORM_NAME=kv260_custom
 PLATFORM= $(ROOT_DIR)/../step2_pfm/$(PLATFORM_NAME)/export/$(PLATFORM_NAME)/$(PLATFORM_NAME).xpfm
-SW_COMP = $(ROOT_DIR)/../step2_pfm/sw_comp/
-SYSROOTDIR=$(ROOT_DIR)/../step2_pfm/sysroot/
+
 VERSION=2024.1
 COMMON_IMAGE_ZYNQMP ?=${PLATFORM_REPO_PATHS}/sw/zynqmp/xilinx-zynqmp-common-v$(VERSION)/
-PL_EXAMPLE_PATH = Vitis_Accel_Examples/cpp_kernels/simple_vadd/
+SYSROOT := $(COMMON_IMAGE_ZYNQMP)/sysroots/cortexa72-cortexa53-xilinx-linux
+VADD_WORK=$(ROOT_DIR)/vadd_work
 
 .PHONY: help  
 
@@ -23,30 +23,28 @@ all: getplatforminfo vadd_hw_package
 
 getplatforminfo:
 	$(MAKE) -C platforminfo/ all
-
-
-Vitis_Accel_Examples:
-	git clone https://github.com/Xilinx/Vitis_Accel_Examples.git
-
-# Quick command for generating vadd hw xclbin
-vadd_hw: Vitis_Accel_Examples
-	$(MAKE) -C $(PL_EXAMPLE_PATH) all TARGET=hw PLATFORM=$(PLATFORM) HOST_ARCH=aarch64 DEV_ARCH=zynquplus EDGE_COMMON_SW=$(COMMON_IMAGE_ZYNQMP) SYSROOT=$(SYSROOTDIR)/sysroots/cortexa72-cortexa53-xilinx-linux
+cpVaddCode:
+	mkdir -p vadd_work
+	cp $(XILINX_VITIS)/examples/vadd/* vadd_work
+	cp makefile_vadd vadd_work/Makefile
+
+# vadd_hw is a place-holder for manual build and test on hardware
+$(VADD_WORK)/simple_vadd: vadd_hw
+vadd_hw: cpVaddCode $(PLATFORM)
+	$(MAKE) -C $(VADD_WORK) sd_card TARGET=hw PLATFORM=$(PLATFORM) DEV_ARCH=versal HOST_ARCH=aarch64 EDGE_COMMON_SW=$(COMMON_IMAGE_ZYNQMP) SYSROOT=$(SYSROOT)/
 # vadd_hw generates the files for running on hardware. User needs to pick the files required by KV260, rename thr file and transfer them to the board
 # Do not use the generated sd_card.img
-$(PL_EXAMPLE_PATH)/simple_vadd:   Vitis_Accel_Examples $(PLATFORM)  
-	$(MAKE) -C $(PL_EXAMPLE_PATH) all TARGET=hw PLATFORM=$(PLATFORM) DEV_ARCH=zynquplus HOST_ARCH=aarch64 EDGE_COMMON_SW=$(COMMON_IMAGE_ZYNQMP) SYSROOT=$(SYSROOTDIR)/sysroots/cortexa72-cortexa53-xilinx-linux
 
+$(VADD_WORK)/shell.json:
+	cd $(VADD_WORK) && printf '{\n  "shell_type" : "XRT_FLAT",\n  "num_slots": "1"\n}' > shell.json
 
-$(PL_EXAMPLE_PATH)/shell.json:
-	cd $(PL_EXAMPLE_PATH) && printf '{\n  "shell_type" : "XRT_FLAT",\n  "num_slots": "1"\n}' > shell.json
-
-vadd_hw_package: $(PL_EXAMPLE_PATH)/simple_vadd  $(PL_EXAMPLE_PATH)/shell.json
+vadd_hw_package: $(VADD_WORK)/simple_vadd  $(VADD_WORK)/shell.json
 	@echo "INFO: Packaging Completed"
 	mkdir -p vadd
 	cp ../step2_pfm/dtbo_output/pl.dtbo vadd/
-	cp $(PL_EXAMPLE_PATH)/shell.json vadd/
-	cp $(PL_EXAMPLE_PATH)/build_dir.hw.$(PLATFORM_NAME)/krnl_vadd.link.xclbin vadd/krnl_vadd.bin
-	cp $(PL_EXAMPLE_PATH)/simple_vadd vadd/
+	cp $(VADD_WORK)/shell.json vadd/
+	cp $(VADD_WORK)/build_dir.hw/krnl_vadd.link.xclbin vadd/krnl_vadd.bin
+	cp $(VADD_WORK)/simple_vadd vadd/
 	@echo "Please  copy vadd to /lib/firmware/xilinx/ on target board"
 	@echo "then use xmutil to load hardware."
 	@echo "xmutil unloadapp"
@@ -54,13 +52,14 @@ vadd_hw_package: $(PL_EXAMPLE_PATH)/simple_vadd  $(PL_EXAMPLE_PATH)/shell.json
 	@echo "Go to /lib/firmware/xilinx/vadd directory and run application"
 	@echo "$ ./simple_vadd ./krnl_vadd.bin"
 
-
+getplatforminfo:
+	$(MAKE) -C platforminfo/ all
 
 
 clean:
-	-$(MAKE) -C $(PL_EXAMPLE_PATH) clean
+	-$(MAKE) -C $(VADD_WORK) clean
 	-$(MAKE) -C platforminfo/ clean
 	rm -rf vadd/
 
 ultraclean:clean
-	rm -rf Vitis_Accel_Examples
+	rm -rf $(VADD_WORK)
diff --git a/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/ref_files/step3_validate/makefile_vadd b/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/ref_files/step3_validate/makefile_vadd
new file mode 100644
index 000000000..8203d6bcf
--- /dev/null
+++ b/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/ref_files/step3_validate/makefile_vadd
@@ -0,0 +1,167 @@
+#/*
+#Copyright (C) 2023, Advanced Micro Devices, Inc. All rights reserved.
+#SPDX-License-Identifier: MIT
+#*/
+
+
+############################## Setting up Project Variables ##############################
+TARGET := hw
+SYSROOT := $(EDGE_COMMON_SW)/sysroots/cortexa72-cortexa53-xilinx-linux
+SD_IMAGE_FILE := $(EDGE_COMMON_SW)/Image
+VPP_LDFLAGS :=
+
+
+TEMP_DIR := ./_x.$(TARGET)
+BUILD_DIR := ./build_dir.$(TARGET)
+
+LINK_OUTPUT := $(BUILD_DIR)/krnl_vadd.link.xclbin
+
+EMU_PS := QEMU
+ifeq ($(TARGET), sw_emu)
+EMU_PS := X86
+endif
+
+# SoC variables
+RUN_APP_SCRIPT = run_vadd.sh
+PACKAGE_OUT = ./package.$(TARGET)
+
+LAUNCH_EMULATOR = $(PACKAGE_OUT)/launch_$(TARGET).sh
+RESULT_STRING = TEST PASSED
+
+VPP_PFLAGS := 
+CMD_ARGS = $(BUILD_DIR)/krnl_vadd.xclbin
+SD_CARD := $(PACKAGE_OUT)
+
+
+ifeq ($(EMU_PS), X86)
+CXXFLAGS += -I$(XILINX_XRT)/include -I$(XILINX_VIVADO)/include -Wall -O0 -g -std=c++1y
+LDFLAGS += -L$(XILINX_XRT)/lib -pthread -lOpenCL
+else
+CXXFLAGS += -I$(SYSROOT)/usr/include/xrt -I$(XILINX_VIVADO)/include -Wall -O0 -g -std=c++1y
+LDFLAGS += -L$(SYSROOT)/usr/lib -pthread -lxilinxopencl
+endif
+
+ifeq ($(TARGET),$(filter $(TARGET),sw_emu))
+VPP_PFLAGS+= --package.emu_ps qemu
+endif
+
+#Check for EMU_PS
+ifeq ($(TARGET), $(filter $(TARGET),hw_emu hw))
+ifeq ($(EMU_PS), X86)
+$(error For hw_emu and hw, the design has to run on QEMU. Thus, please give EMU_PS=QEMU for these targets.)
+endif
+endif
+
+########################## Checking if PLATFORM in allowlist #######################
+PLATFORM_BLOCKLIST += nodma 
+############################## Setting up Host Variables ##############################
+#Include Required Host Source Files
+HOST_SRCS += vadd.cpp 
+# Host compiler global settings
+CXXFLAGS += -fmessage-length=0
+LDFLAGS += -lrt -lstdc++ 
+ifneq ($(EMU_PS), X86)
+LDFLAGS += --sysroot=$(SYSROOT)
+endif
+############################## Setting up Kernel Variables ##############################
+# Kernel compiler global settings
+VPP_FLAGS += --save-temps 
+
+
+EXECUTABLE = ./simple_vadd
+EMCONFIG_DIR = $(TEMP_DIR)
+
+############################## Setting Targets ##############################
+.PHONY: all clean cleanall docs emconfig
+ifeq ($(EMU_PS), X86)
+all:   $(EXECUTABLE) $(LINK_OUTPUT) emconfig
+else
+all:    $(EXECUTABLE) $(LINK_OUTPUT) sd_card
+endif
+
+.PHONY: host
+host: $(EXECUTABLE)
+
+.PHONY: build
+build:  $(LINK_OUTPUT)
+
+.PHONY: xclbin
+xclbin: build
+
+
+############################## Setting Rules for Binary Containers (Building Kernels) ##############################
+$(TEMP_DIR)/krnl_vadd.xo: krnl_vadd.cpp
+	mkdir -p $(TEMP_DIR)
+	v++ -c $(VPP_FLAGS) -t $(TARGET) --platform $(PLATFORM) -k krnl_vadd --temp_dir $(TEMP_DIR)  -I'$(<D)' -o'$@' '$<'
+
+$(LINK_OUTPUT): $(TEMP_DIR)/krnl_vadd.xo
+	mkdir -p $(BUILD_DIR)
+	v++ -l $(VPP_FLAGS) $(VPP_LDFLAGS) -t $(TARGET) --platform $(PLATFORM) --temp_dir $(TEMP_DIR) -o'$(LINK_OUTPUT)' $(+)
+
+ifeq ($(EMU_PS), X86)
+	v++ -p $(LINK_OUTPUT) $(VPP_FLAGS) -t $(TARGET) --platform $(PLATFORM) -o $(BUILD_DIR)/krnl_vadd.xclbin
+endif
+############################## Preparing sdcard ##############################
+.PHONY: sd_card
+sd_card:  emconfig $(SD_CARD)
+
+$(SD_CARD): $(EXECUTABLE) $(LINK_OUTPUT)
+	v++ -p $(VPP_PFLAGS) $(LINK_OUTPUT) $(VPP_FLAGS) -t $(TARGET) --platform $(PLATFORM) --package.out_dir $(PACKAGE_OUT) --package.rootfs $(EDGE_COMMON_SW)/rootfs.ext4 --package.sd_file $(SD_IMAGE_FILE)  --package.sd_file ../$(RUN_APP_SCRIPT) --package.sd_file $(EXECUTABLE) --package.sd_file $(EMCONFIG_DIR)/emconfig.json -o $(BUILD_DIR)/krnl_vadd.xclbin
+
+
+############################## Setting Rules for Host (Building Host Executable) ##############################
+$(EXECUTABLE): $(HOST_SRCS)
+ifeq ($(EMU_PS), X86)
+	$(CXX) -o $@ $^ $(CXXFLAGS) $(LDFLAGS)
+else
+	$(XILINX_VITIS)/gnu/aarch64/lin/aarch64-linux/bin/aarch64-linux-gnu-g++ -o $@ $^ $(CXXFLAGS) $(LDFLAGS)
+endif
+
+emconfig:$(EMCONFIG_DIR)/emconfig.json
+$(EMCONFIG_DIR)/emconfig.json:
+	emconfigutil --platform $(PLATFORM) --od $(EMCONFIG_DIR)
+
+############################## Setting Essential Checks and Running Rules ##############################
+run: all
+ifeq ($(TARGET),$(filter $(TARGET),sw_emu hw_emu))
+ifeq ($(EMU_PS), X86)
+	cp -rf $(EMCONFIG_DIR)/emconfig.json .
+	XCL_EMULATION_MODE=$(TARGET) $(EXECUTABLE) $(CMD_ARGS)
+else
+	bash -c '$(LAUNCH_EMULATOR) -run-app $(RUN_APP_SCRIPT) | tee run_app.log; exit $${PIPESTATUS[0]}'
+endif
+else
+	$(ECHO) "Please copy the content of sd_card folder and data to an SD Card and run on the board"
+endif
+
+.PHONY: test
+test: $(EXECUTABLE)
+ifeq ($(TARGET),$(filter $(TARGET),sw_emu hw_emu))
+ifeq ($(EMU_PS), X86)
+	XCL_EMULATION_MODE=$(TARGET) $(EXECUTABLE) $(CMD_ARGS)
+else
+	bash -c '$(LAUNCH_EMULATOR) -run-app $(RUN_APP_SCRIPT) | tee run_app.log; exit $${PIPESTATUS[0]}'
+endif
+else
+	$(ECHO) "Please copy the content of sd_card folder and data to an SD Card and run on the board"
+endif
+
+check_edge_sw:
+ifndef EDGE_COMMON_SW
+	$(error EDGE_COMMON_SW variable is not set, please download and use the pre-built image from https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/embedded-platforms.html)
+endif
+
+############################## Cleaning Rules ##############################
+# Cleaning stuff
+clean:
+	-$(RMDIR) $(EXECUTABLE) *.xclbin/{*sw_emu*,*hw_emu*} 
+	-$(RMDIR) profile_* TempConfig system_estimate.xtxt *.rpt *.csv 
+	-$(RMDIR) src/*.ll *v++* .Xil emconfig.json dltmp* xmltmp* *.log *.jou *.wcfg *.wdb
+
+cleanall: clean
+	-$(RMDIR) build_dir* sd_card*
+	-$(RMDIR) package.*
+	-$(RMDIR) _x* *xclbin.run_summary qemu-memory-_* emulation _vimage pl* start_simulation.sh *.xclbin
+
+
+
diff --git a/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/step1.md b/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/step1.md
index 486e75ced..0054fa668 100644
--- a/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/step1.md
+++ b/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/step1.md
@@ -1,6 +1,6 @@
 <table class="sphinxhide" width="100%">
  <tr width="100%">
-    <td align="center"><img src="https://raw.githubusercontent.com/Xilinx/Image-Collateral/main/xilinx-logo.png" width="30%"/><h1>2023.2 Vitis™ Platform Creation Tutorials</h1>
+    <td align="center"><img src="https://raw.githubusercontent.com/Xilinx/Image-Collateral/main/xilinx-logo.png" width="30%"/><h1>2024.1 Vitis™ Platform Creation Tutorials</h1>
     <a href="https://www.xilinx.com/products/design-tools/vitis.html">See Vitis™ Development Environment on xilinx.com</br></a>
     </td>
  </tr>
@@ -302,6 +302,6 @@ For simple designs, interrupt signals can be sourced by processor's **pl_ps_irq*
 
 Now you finish the Hardware platform creation flow, then you should go to the [Step 2: Vitis Platform Creation](./step2.md)
 
-<p class="sphinxhide" align="center"><sub>Copyright © 2020–2023 Advanced Micro Devices, Inc</sub></p>
+<p class="sphinxhide" align="center"><sub>Copyright © 2020–2024 Advanced Micro Devices, Inc</sub></p>
 
 <p class="sphinxhide" align="center"><sup><a href="https://www.amd.com/en/corporate/copyright">Terms and Conditions</a></sup></p>
diff --git a/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/step2.md b/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/step2.md
index 966cac031..719c74c46 100644
--- a/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/step2.md
+++ b/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/step2.md
@@ -1,6 +1,6 @@
 <table class="sphinxhide" width="100%">
  <tr width="100%">
-    <td align="center"><img src="https://raw.githubusercontent.com/Xilinx/Image-Collateral/main/xilinx-logo.png" width="30%"/><h1>2023.2 Vitis™ Platform Creation Tutorials</h1>
+    <td align="center"><img src="https://raw.githubusercontent.com/Xilinx/Image-Collateral/main/xilinx-logo.png" width="30%"/><h1>2024.1 Vitis™ Platform Creation Tutorials</h1>
     <a href="https://www.xilinx.com/products/design-tools/vitis.html">See Vitis™ Development Environment on xilinx.com</br></a>
     </td>
  </tr>
@@ -18,7 +18,7 @@ In this step, you will create a Vitis platform running a Linux operation system.
    cd WorkSpace
    tree -L 1     # to see the directory hierarchy
    ├── kv260_hardware_platform
-   └── xilinx-zynqmp-common-v2023.2.tar.gz
+   └── xilinx-zynqmp-common-v2024.1.tar.gz
    ```
 
 2. Extract the common image.
@@ -26,14 +26,14 @@ In this step, you will create a Vitis platform running a Linux operation system.
 
    ```bash
    cd WorkSpace
-   tar xvf ../xilinx-zynqmp-common-v2023.2.tar.gz -C .
+   tar xvf ../xilinx-zynqmp-common-v2024.1.tar.gz -C .
    ```
 
-   You can see **xilinx-zynqmp-common-v2023.2** folder which contains the components located in **WrokSpace** folder.
+   You can see **xilinx-zynqmp-common-v2024.1** folder which contains the components located in **WrokSpace** folder.
 
    ```bash
    tree -L 2
-   ├── xilinx-zynqmp-common-v2023.2
+   ├── xilinx-zynqmp-common-v2024.1
    │   ├── bl31.elf
    │   ├── boot.scr
    │   ├── Image
@@ -55,7 +55,7 @@ If you need to do system customization, take the following steps as reference. F
 
 <summary><strong>Click for Detailed Steps</strong></summary>  
 
-1. Check the [AMD Kria™ K26 SOM wiki](https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/1641152513/Kria+K26+SOM), and download the BSP package from the following link: <https://www.xilinx.com/member/forms/download/xef.html?filename=xilinx-k26-starterkit-v2023.2-final.bsp>
+1. Check the [AMD Kria™ K26 SOM wiki](https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/1641152513/Kria+K26+SOM), and download the BSP package from the following link: <https://www.xilinx.com/member/forms/download/xef.html?filename=xilinx-k26-starterkit-v2024.1-final.bsp>
 
    Save it to **WorkSpace** directory.
 
@@ -71,14 +71,14 @@ If you need to do system customization, take the following steps as reference. F
 3. Update the PetaLinux eSDK to enable the recipes needed by the Starter Kit SOM BSP.
 
     ```bash
-    petalinux-upgrade -u 'http://petalinux.xilinx.com/sswreleases/rel-v2023/sdkupdate/' -p 'aarch64'
+    petalinux-upgrade -u 'http://petalinux.xilinx.com/sswreleases/rel-v2004/sdkupdate/' -p 'aarch64'
     ```
 
 4. Create PetaLinux with the Starter Kit SOM BSP, and the XSA export from step 1.
 
     ```bash
-    petalinux-create --type project -s xilinx-kv260-starterkit-v2023.2-final.bsp
-    cd xilinx-kv260-starterkit-2023.2
+    petalinux-create --type project -s xilinx-kv260-starterkit-v2024.1-final.bsp
+    cd xilinx-kv260-starterkit-2024.1
     petalinux-config --get-hw-description=<vivado_design_dir> --silent  
     ```
 
@@ -122,7 +122,7 @@ If you need to do system customization, take the following steps as reference. F
    cd WrokSpace
    xsct
    createdts -hw kv260_hardware_platform/kv260_hardware_platform.xsa -zocl -out . \
-   -platform-name mydevice -git-branch xlnx_rel_v2023.2 -overlay -compile
+   -platform-name mydevice -git-branch xlnx_rel_v2024.1 -overlay -compile
    ```
 
    The `createdts` command has the following input values. Specify them as you need.
@@ -173,7 +173,7 @@ If you need to do system customization, take the following steps as reference. F
 
 1. Install sysroot.
 
-   - Go to `<WorkSpace/xilinx-zynqmp-common-v2023.2>` directory.
+   - Go to `<WorkSpace/xilinx-zynqmp-common-v2024.1>` directory.
    - Type `./sdk.sh -d <Install Target Dir>` to install PetaLinux SDK. Use the `-d` option to provide a full pathname to the output directory. For example: `./sdk.sh -d .`. **.** means the current directory. 
    >**NOTE:** The environment variable **LD_LIBRARY_PATH** must not be set when running this command.
 
@@ -203,7 +203,7 @@ If you need to do system customization, take the following steps as reference. F
 
      >**Note:** The filenames in `<>` are placeholders in the bif file. Vitis will replace the placeholders with the relative path to platform during platform packaging. V++ packager, which runs when building the final application#, would expand it further to the full path during image packaging. Filename placeholders point to the files in boot components directory. The filenames in boot directory need to match with placeholders in BIF file. `<bitstream>` is a reserved keyword. V++ packager will replace it with the final system bit file.
 
-   - **Pre-Built Image Directory**: Browse to **xilinx-zynqmp-common-v2023.2** and click **OK**.
+   - **Pre-Built Image Directory**: Browse to **xilinx-zynqmp-common-v2024.1** and click **OK**.
 
    - **DTB File**: Browse to **mydevice/psu_cortexa53_0/device_tree_domain/bsp** and select system.dtb, then click **OK**.
       >Note: If the directory you specified for Pre-build image directory already contains DTB file, this DTB field will be automatically updated. 
@@ -236,6 +236,6 @@ If you need to do system customization, take the following steps as reference. F
 
 Next, try to [build applications on this platform and test them.](./step3.md)
 
-<p class="sphinxhide" align="center"><sub>Copyright © 2020–2023 Advanced Micro Devices, Inc</sub></p>
+<p class="sphinxhide" align="center"><sub>Copyright © 2020–2024 Advanced Micro Devices, Inc</sub></p>
 
 <p class="sphinxhide" align="center"><sup><a href="https://www.amd.com/en/corporate/copyright">Terms and Conditions</a></sup></p>
diff --git a/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/step3.md b/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/step3.md
index 1536b4051..42b3cf8a4 100644
--- a/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/step3.md
+++ b/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/step3.md
@@ -1,6 +1,6 @@
 <table class="sphinxhide" width="100%">
  <tr width="100%">
-    <td align="center"><img src="https://raw.githubusercontent.com/Xilinx/Image-Collateral/main/xilinx-logo.png" width="30%"/><h1>2023.2 Vitis™ Platform Creation Tutorials</h1>
+    <td align="center"><img src="https://raw.githubusercontent.com/Xilinx/Image-Collateral/main/xilinx-logo.png" width="30%"/><h1>2024.1 Vitis™ Platform Creation Tutorials</h1>
     <a href="https://www.xilinx.com/products/design-tools/vitis.html">See Vitis™ Development Environment on xilinx.com</br></a>
     </td>
  </tr>
@@ -194,17 +194,17 @@ Vector addition is the simplest acceleration PL kernel. Vitis Unified IDE can cr
     If the application required files are loaded successfully, the following log is expected:
 
     ```bash
-    Nov  8 06:20:28 xilinx-kv260-starterkit-20232 kernel: OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga-full/firmware-name
-    Nov  8 06:20:28 xilinx-kv260-starterkit-20232 kernel: OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga-full/pid
-    Nov  8 06:20:28 xilinx-kv260-starterkit-20232 kernel: OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga-full/resets
-    Nov  8 06:20:28 xilinx-kv260-starterkit-20232 kernel: OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga-full/uid
-    Nov  8 06:20:28 xilinx-kv260-starterkit-20232 kernel: OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/afi0
-    Nov  8 06:20:28 xilinx-kv260-starterkit-20232 kernel: OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/clocking0
-    Nov  8 06:20:28 xilinx-kv260-starterkit-20232 kernel: OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/clocking1
-    Nov  8 06:20:28 xilinx-kv260-starterkit-20232 kernel: OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/axi_intc_0
-    Nov  8 06:20:28 xilinx-kv260-starterkit-20232 kernel: OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/misc_clk_0
-    Nov  8 06:20:28 xilinx-kv260-starterkit-20232 kernel: irq-xilinx: mismatch in kind-of-intr param
-    Nov  8 06:20:28 xilinx-kv260-starterkit-20232 kernel: zocl-drm axi:zyxclmm_drm: error -ENXIO: IRQ index 32 not found
+    Nov  8 06:20:28 xilinx-kv260-starterkit-20241 kernel: OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga-full/firmware-name
+    Nov  8 06:20:28 xilinx-kv260-starterkit-20241 kernel: OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga-full/pid
+    Nov  8 06:20:28 xilinx-kv260-starterkit-20241 kernel: OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga-full/resets
+    Nov  8 06:20:28 xilinx-kv260-starterkit-20241 kernel: OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga-full/uid
+    Nov  8 06:20:28 xilinx-kv260-starterkit-20241 kernel: OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/afi0
+    Nov  8 06:20:28 xilinx-kv260-starterkit-20241 kernel: OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/clocking0
+    Nov  8 06:20:28 xilinx-kv260-starterkit-20241 kernel: OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/clocking1
+    Nov  8 06:20:28 xilinx-kv260-starterkit-20241 kernel: OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/axi_intc_0
+    Nov  8 06:20:28 xilinx-kv260-starterkit-20241 kernel: OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/misc_clk_0
+    Nov  8 06:20:28 xilinx-kv260-starterkit-20241 kernel: irq-xilinx: mismatch in kind-of-intr param
+    Nov  8 06:20:28 xilinx-kv260-starterkit-20241 kernel: zocl-drm axi:zyxclmm_drm: error -ENXIO: IRQ index 32 not found
     vadd: loaded to slot 0
     ```
 
@@ -220,7 +220,7 @@ Vector addition is the simplest acceleration PL kernel. Vitis Unified IDE can cr
    - It should show program prints.
 
    ```
-    xilinx-k26-starterkit-20232:~$ ./vadd_host binary_container_1.bin
+    xilinx-k26-starterkit-20241:~$ ./vadd_host binary_container_1.bin
     INFO: Reading binary_container_1.bin
     Loading: 'binary_container_1.bin'
     TEST PASSED
@@ -247,6 +247,6 @@ The command line flow has slight differences comparing to Vitis IDE flow.
 
 If user need to do iteration for your project, you could go through the [Iteration Guidelines](./Iteration_guideline.md) to do iterations.
 
-<p class="sphinxhide" align="center"><sub>Copyright © 2020–2023 Advanced Micro Devices, Inc</sub></p>
+<p class="sphinxhide" align="center"><sub>Copyright © 2020–2024 Advanced Micro Devices, Inc</sub></p>
 
 <p class="sphinxhide" align="center"><sup><a href="https://www.amd.com/en/corporate/copyright">Terms and Conditions</a></sup></p>