diff --git a/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/README.md b/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/README.md index 47164c5dc1..002b7a072c 100644 --- a/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/README.md +++ b/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/README.md @@ -8,13 +8,13 @@ # Vitis Custom Embedded Platform Creation Example on KV260 -***Version: Vitis 2023.1*** +***Version: Vitis 2023.2*** The [AMD Kria™ KV260 Vision AI Starter Kit](https://www.xilinx.com/products/som/kria/kv260-vision-starter-kit.html) is the development platform for Kria K26 SOM. The KV260 is built for advanced vision application development without requiring complex hardware design knowledge. It is based on the AMD UltraScale+™ MPSoC technology similar to ZCU104 evaluation board. In this example, you will extend the [ZCU104 custom embedded platform creation example](../02-Edge-AI-ZCU104/) to KV260 Vision AI Starter Kit. To highlight the differences between KV260 and ZCU104, this example will simplify the descriptions of general steps that are shared between all MPSoC platforms, but add more KV260 specific contents. If you have question in some steps, cross reference [ZCU104 custom embedded platform creation example](../02-Edge-AI-ZCU104/), or ask questions in Github Issues page. -For your reference, this example total system structure is similar to the following figure. +For your reference, The structure of this example system is shown in the following figure.. ![missing image](./images/structure.svg) @@ -77,7 +77,7 @@ The platform creation steps are introduced in the following pages. Each page des - [Setting up the Vitis environment](https://www.xilinx.com/html_docs/xilinx2021_1/vitis_doc/settingupvitisenvironment.html) - [Installing Xilinx Runtime](https://www.xilinx.com/html_docs/xilinx2021_1/vitis_doc/pjr1542153622642.html) - Platform Examples - - [zcu102](https://github.com/Xilinx/Vitis_Embedded_Platform_Source/tree/2023.1/Xilinx_Official_Platforms/xilinx_zcu102_base) and [zcu104](https://github.com/Xilinx/Vitis_Embedded_Platform_Source/tree/2023.1/Xilinx_Official_Platforms/xilinx_zcu104_base) base platform source code in [Vitis Embedded Platform Source Github Repository](https://github.com/Xilinx/Vitis_Embedded_Platform_Source) + - [zcu102](https://github.com/Xilinx/Vitis_Embedded_Platform_Source/tree/2023.2/Xilinx_Official_Platforms/xilinx_zcu102_base) and [zcu104](https://github.com/Xilinx/Vitis_Embedded_Platform_Source/tree/2023.2/Xilinx_Official_Platforms/xilinx_zcu104_base) base platform source code in [Vitis Embedded Platform Source Github Repository](https://github.com/Xilinx/Vitis_Embedded_Platform_Source) - [Xilinx Run Time (XRT)](https://xilinx.github.io/XRT/master/html/index.html) - [Vitis-AI GitHub Repository](https://github.com/Xilinx/Vitis-AI) diff --git a/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/images/add_hardware_function.png b/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/images/add_hardware_function.png deleted file mode 100644 index afb328777e..0000000000 Binary files a/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/images/add_hardware_function.png and /dev/null differ diff --git a/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/images/add_opencv_lib.png b/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/images/add_opencv_lib.png deleted file mode 100644 index 1b3ccc6a9e..0000000000 Binary files a/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/images/add_opencv_lib.png and /dev/null differ diff --git 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a/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/images/vivado_platform_connection.png and /dev/null differ diff --git a/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/images/vivado_project_summary.png b/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/images/vivado_project_summary.png deleted file mode 100644 index aa5a937cc7..0000000000 Binary files a/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/images/vivado_project_summary.png and /dev/null differ diff --git a/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/ref_files/description.json b/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/ref_files/description.json index ebfcd6806d..c5ee8e73ba 100644 --- a/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/ref_files/description.json +++ b/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/ref_files/description.json @@ -26,7 +26,7 @@ } ], "targets": [ - + "vitis_hw_build" ], "custom_build_target": { diff --git a/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/ref_files/step1_vivado/system_step1.tcl b/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/ref_files/step1_vivado/system_step1.tcl index 7c4ab85936..490c70e6dd 100644 --- a/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/ref_files/step1_vivado/system_step1.tcl +++ b/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/ref_files/step1_vivado/system_step1.tcl @@ -1,7 +1,4 @@ -#/* -#Copyright (C) 2023, Advanced Micro Devices, Inc. All rights reserved. -#SPDX-License-Identifier: X11 -#*/ + ################################################################ # This is a generated script based on design: system # @@ -23,12 +20,18 @@ set script_folder [_tcl::get_script_folder] ################################################################ # Check if script is running in correct Vivado version. ################################################################ -set scripts_vivado_version 2023.1 +set scripts_vivado_version 2023.2 set current_vivado_version [version -short] if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { puts "" - catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} + if { [string compare $scripts_vivado_version $current_vivado_version] > 0 } { + catch {common::send_gid_msg -ssname BD::TCL -id 2042 -severity "ERROR" " This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Sourcing the script failed since it was created with a future version of Vivado."} + + } else { + catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} + + } return 1 } @@ -202,6 +205,21 @@ proc create_root_design { parentCell } { # Create instance: zynq_ultra_ps_e_0, and set properties set zynq_ultra_ps_e_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.5 zynq_ultra_ps_e_0 ] set_property -dict [list \ + CONFIG.CAN0_BOARD_INTERFACE {custom} \ + CONFIG.CAN1_BOARD_INTERFACE {custom} \ + CONFIG.CSU_BOARD_INTERFACE {custom} \ + CONFIG.DP_BOARD_INTERFACE {custom} \ + CONFIG.GEM0_BOARD_INTERFACE {custom} \ + CONFIG.GEM1_BOARD_INTERFACE {custom} \ + CONFIG.GEM2_BOARD_INTERFACE {custom} \ + CONFIG.GEM3_BOARD_INTERFACE {custom} \ + CONFIG.GPIO_BOARD_INTERFACE {custom} \ + CONFIG.IIC0_BOARD_INTERFACE {custom} \ + CONFIG.IIC1_BOARD_INTERFACE {custom} \ + CONFIG.NAND_BOARD_INTERFACE {custom} \ + CONFIG.PCIE_BOARD_INTERFACE {custom} \ + CONFIG.PJTAG_BOARD_INTERFACE {custom} \ + CONFIG.PMU_BOARD_INTERFACE {custom} \ CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS18} \ CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS18} \ CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS18} \ @@ -209,156 +227,291 @@ proc create_root_design { parentCell } { CONFIG.PSU_DDR_RAM_HIGHADDR {0xFFFFFFFF} \ CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET {0x800000000} \ CONFIG.PSU_DDR_RAM_LOWADDR_OFFSET {0x80000000} \ + CONFIG.PSU_IMPORT_BOARD_PRESET {} \ CONFIG.PSU_MIO_0_DRIVE_STRENGTH {4} \ + CONFIG.PSU_MIO_0_PULLUPDOWN {pullup} \ CONFIG.PSU_MIO_0_SLEW {slow} \ CONFIG.PSU_MIO_10_DRIVE_STRENGTH {4} \ + CONFIG.PSU_MIO_10_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_10_PULLUPDOWN {pullup} \ CONFIG.PSU_MIO_10_SLEW {slow} \ CONFIG.PSU_MIO_11_DRIVE_STRENGTH {4} \ + CONFIG.PSU_MIO_11_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_11_PULLUPDOWN {pullup} \ CONFIG.PSU_MIO_11_SLEW {slow} \ CONFIG.PSU_MIO_12_DRIVE_STRENGTH {4} \ CONFIG.PSU_MIO_12_INPUT_TYPE {cmos} \ CONFIG.PSU_MIO_12_POLARITY {Default} \ + CONFIG.PSU_MIO_12_PULLUPDOWN {pullup} \ CONFIG.PSU_MIO_12_SLEW {slow} \ CONFIG.PSU_MIO_13_DRIVE_STRENGTH {4} \ + CONFIG.PSU_MIO_13_INPUT_TYPE {cmos} \ CONFIG.PSU_MIO_13_POLARITY {Default} \ + CONFIG.PSU_MIO_13_PULLUPDOWN {pullup} \ CONFIG.PSU_MIO_13_SLEW {slow} \ CONFIG.PSU_MIO_14_DRIVE_STRENGTH {4} \ + CONFIG.PSU_MIO_14_INPUT_TYPE {cmos} \ CONFIG.PSU_MIO_14_POLARITY {Default} \ + CONFIG.PSU_MIO_14_PULLUPDOWN {pullup} \ CONFIG.PSU_MIO_14_SLEW {slow} \ CONFIG.PSU_MIO_15_DRIVE_STRENGTH {4} \ + CONFIG.PSU_MIO_15_INPUT_TYPE {cmos} \ CONFIG.PSU_MIO_15_POLARITY {Default} \ + CONFIG.PSU_MIO_15_PULLUPDOWN {pullup} \ CONFIG.PSU_MIO_15_SLEW {slow} \ CONFIG.PSU_MIO_16_DRIVE_STRENGTH {4} \ + CONFIG.PSU_MIO_16_INPUT_TYPE {cmos} \ CONFIG.PSU_MIO_16_POLARITY {Default} \ + CONFIG.PSU_MIO_16_PULLUPDOWN {pullup} \ CONFIG.PSU_MIO_16_SLEW {slow} \ CONFIG.PSU_MIO_17_DRIVE_STRENGTH {4} \ + CONFIG.PSU_MIO_17_INPUT_TYPE {cmos} \ CONFIG.PSU_MIO_17_POLARITY {Default} \ + CONFIG.PSU_MIO_17_PULLUPDOWN {pullup} \ CONFIG.PSU_MIO_17_SLEW {slow} \ CONFIG.PSU_MIO_18_DRIVE_STRENGTH {4} \ + CONFIG.PSU_MIO_18_INPUT_TYPE {cmos} \ CONFIG.PSU_MIO_18_POLARITY {Default} \ + CONFIG.PSU_MIO_18_PULLUPDOWN {pullup} \ CONFIG.PSU_MIO_18_SLEW {slow} \ CONFIG.PSU_MIO_19_DRIVE_STRENGTH {4} \ + CONFIG.PSU_MIO_19_INPUT_TYPE {cmos} \ CONFIG.PSU_MIO_19_POLARITY {Default} \ + CONFIG.PSU_MIO_19_PULLUPDOWN {pullup} \ CONFIG.PSU_MIO_19_SLEW {slow} \ CONFIG.PSU_MIO_1_DRIVE_STRENGTH {4} \ + CONFIG.PSU_MIO_1_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_1_PULLUPDOWN {pullup} \ CONFIG.PSU_MIO_1_SLEW {slow} \ CONFIG.PSU_MIO_20_DRIVE_STRENGTH {4} \ + CONFIG.PSU_MIO_20_INPUT_TYPE {cmos} \ CONFIG.PSU_MIO_20_POLARITY {Default} \ + CONFIG.PSU_MIO_20_PULLUPDOWN {pullup} \ CONFIG.PSU_MIO_20_SLEW {slow} \ CONFIG.PSU_MIO_21_DRIVE_STRENGTH {4} \ + CONFIG.PSU_MIO_21_INPUT_TYPE {cmos} \ CONFIG.PSU_MIO_21_POLARITY {Default} \ + CONFIG.PSU_MIO_21_PULLUPDOWN {pullup} \ CONFIG.PSU_MIO_21_SLEW {slow} \ CONFIG.PSU_MIO_22_DRIVE_STRENGTH {4} \ + CONFIG.PSU_MIO_22_INPUT_TYPE {cmos} \ CONFIG.PSU_MIO_22_POLARITY {Default} \ + CONFIG.PSU_MIO_22_PULLUPDOWN {pullup} \ CONFIG.PSU_MIO_22_SLEW {slow} \ CONFIG.PSU_MIO_23_DRIVE_STRENGTH {4} \ + CONFIG.PSU_MIO_23_INPUT_TYPE {cmos} \ CONFIG.PSU_MIO_23_POLARITY {Default} \ + CONFIG.PSU_MIO_23_PULLUPDOWN {pullup} \ CONFIG.PSU_MIO_23_SLEW {slow} \ CONFIG.PSU_MIO_24_DRIVE_STRENGTH {4} \ + CONFIG.PSU_MIO_24_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_24_PULLUPDOWN {pullup} \ CONFIG.PSU_MIO_24_SLEW {slow} \ CONFIG.PSU_MIO_25_DRIVE_STRENGTH {4} \ + CONFIG.PSU_MIO_25_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_25_PULLUPDOWN {pullup} \ CONFIG.PSU_MIO_25_SLEW {slow} \ + CONFIG.PSU_MIO_26_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_26_PULLUPDOWN {pullup} \ CONFIG.PSU_MIO_27_DRIVE_STRENGTH {4} \ + CONFIG.PSU_MIO_27_PULLUPDOWN {pullup} \ CONFIG.PSU_MIO_27_SLEW {slow} \ + CONFIG.PSU_MIO_28_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_28_PULLUPDOWN {pullup} \ CONFIG.PSU_MIO_29_DRIVE_STRENGTH {4} \ + CONFIG.PSU_MIO_29_PULLUPDOWN {pullup} \ CONFIG.PSU_MIO_29_SLEW {slow} \ CONFIG.PSU_MIO_2_DRIVE_STRENGTH {4} \ + CONFIG.PSU_MIO_2_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_2_PULLUPDOWN {pullup} \ CONFIG.PSU_MIO_2_SLEW {slow} \ + CONFIG.PSU_MIO_30_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_30_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_31_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_31_PULLUPDOWN {pullup} \ CONFIG.PSU_MIO_32_DRIVE_STRENGTH {4} \ + CONFIG.PSU_MIO_32_INPUT_TYPE {cmos} \ CONFIG.PSU_MIO_32_POLARITY {Default} \ + CONFIG.PSU_MIO_32_PULLUPDOWN {pullup} \ CONFIG.PSU_MIO_32_SLEW {slow} \ CONFIG.PSU_MIO_33_DRIVE_STRENGTH {4} \ + CONFIG.PSU_MIO_33_INPUT_TYPE {cmos} \ CONFIG.PSU_MIO_33_POLARITY {Default} \ + CONFIG.PSU_MIO_33_PULLUPDOWN {pullup} \ CONFIG.PSU_MIO_33_SLEW {slow} \ CONFIG.PSU_MIO_34_DRIVE_STRENGTH {4} \ + CONFIG.PSU_MIO_34_INPUT_TYPE {cmos} \ CONFIG.PSU_MIO_34_POLARITY {Default} \ + CONFIG.PSU_MIO_34_PULLUPDOWN {pullup} \ CONFIG.PSU_MIO_34_SLEW {slow} \ CONFIG.PSU_MIO_35_DRIVE_STRENGTH {4} \ + CONFIG.PSU_MIO_35_PULLUPDOWN {pullup} \ CONFIG.PSU_MIO_35_SLEW {slow} \ CONFIG.PSU_MIO_36_DRIVE_STRENGTH {4} \ + CONFIG.PSU_MIO_36_PULLUPDOWN {pullup} \ CONFIG.PSU_MIO_36_SLEW {slow} \ + CONFIG.PSU_MIO_37_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_37_PULLUPDOWN {pullup} \ CONFIG.PSU_MIO_38_DRIVE_STRENGTH {4} \ + CONFIG.PSU_MIO_38_INPUT_TYPE {cmos} \ CONFIG.PSU_MIO_38_POLARITY {Default} \ + CONFIG.PSU_MIO_38_PULLUPDOWN {pullup} \ CONFIG.PSU_MIO_38_SLEW {slow} \ CONFIG.PSU_MIO_39_DRIVE_STRENGTH {4} \ + CONFIG.PSU_MIO_39_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_39_PULLUPDOWN {pullup} \ CONFIG.PSU_MIO_39_SLEW {slow} \ CONFIG.PSU_MIO_3_DRIVE_STRENGTH {4} \ + CONFIG.PSU_MIO_3_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_3_PULLUPDOWN {pullup} \ CONFIG.PSU_MIO_3_SLEW {slow} \ CONFIG.PSU_MIO_40_DRIVE_STRENGTH {4} \ + CONFIG.PSU_MIO_40_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_40_PULLUPDOWN {pullup} \ CONFIG.PSU_MIO_40_SLEW {slow} \ CONFIG.PSU_MIO_41_DRIVE_STRENGTH {4} \ + CONFIG.PSU_MIO_41_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_41_PULLUPDOWN {pullup} \ CONFIG.PSU_MIO_41_SLEW {slow} \ CONFIG.PSU_MIO_42_DRIVE_STRENGTH {4} \ + CONFIG.PSU_MIO_42_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_42_PULLUPDOWN {pullup} \ CONFIG.PSU_MIO_42_SLEW {slow} \ CONFIG.PSU_MIO_43_DRIVE_STRENGTH {4} \ + CONFIG.PSU_MIO_43_PULLUPDOWN {pullup} \ CONFIG.PSU_MIO_43_SLEW {slow} \ CONFIG.PSU_MIO_44_DRIVE_STRENGTH {4} \ + CONFIG.PSU_MIO_44_INPUT_TYPE {cmos} \ CONFIG.PSU_MIO_44_POLARITY {Default} \ + CONFIG.PSU_MIO_44_PULLUPDOWN {pullup} \ CONFIG.PSU_MIO_44_SLEW {slow} \ + CONFIG.PSU_MIO_45_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_45_PULLUPDOWN {pullup} \ CONFIG.PSU_MIO_46_DRIVE_STRENGTH {4} \ + CONFIG.PSU_MIO_46_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_46_PULLUPDOWN {pullup} \ CONFIG.PSU_MIO_46_SLEW {slow} \ CONFIG.PSU_MIO_47_DRIVE_STRENGTH {4} \ + CONFIG.PSU_MIO_47_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_47_PULLUPDOWN {pullup} \ CONFIG.PSU_MIO_47_SLEW {slow} \ CONFIG.PSU_MIO_48_DRIVE_STRENGTH {4} \ + CONFIG.PSU_MIO_48_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_48_PULLUPDOWN {pullup} \ CONFIG.PSU_MIO_48_SLEW {slow} \ CONFIG.PSU_MIO_49_DRIVE_STRENGTH {4} \ + CONFIG.PSU_MIO_49_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_49_PULLUPDOWN {pullup} \ CONFIG.PSU_MIO_49_SLEW {slow} \ CONFIG.PSU_MIO_4_DRIVE_STRENGTH {4} \ CONFIG.PSU_MIO_4_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_4_PULLUPDOWN {pullup} \ CONFIG.PSU_MIO_4_SLEW {slow} \ CONFIG.PSU_MIO_50_DRIVE_STRENGTH {4} \ + CONFIG.PSU_MIO_50_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_50_PULLUPDOWN {pullup} \ CONFIG.PSU_MIO_50_SLEW {slow} \ CONFIG.PSU_MIO_51_DRIVE_STRENGTH {4} \ + CONFIG.PSU_MIO_51_PULLUPDOWN {pullup} \ CONFIG.PSU_MIO_51_SLEW {slow} \ + CONFIG.PSU_MIO_52_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_52_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_53_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_53_PULLUPDOWN {pullup} \ CONFIG.PSU_MIO_54_DRIVE_STRENGTH {4} \ + CONFIG.PSU_MIO_54_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_54_PULLUPDOWN {pullup} \ CONFIG.PSU_MIO_54_SLEW {slow} \ + CONFIG.PSU_MIO_55_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_55_PULLUPDOWN {pullup} \ CONFIG.PSU_MIO_56_DRIVE_STRENGTH {4} \ + CONFIG.PSU_MIO_56_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_56_PULLUPDOWN {pullup} \ CONFIG.PSU_MIO_56_SLEW {slow} \ CONFIG.PSU_MIO_57_DRIVE_STRENGTH {4} \ + CONFIG.PSU_MIO_57_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_57_PULLUPDOWN {pullup} \ CONFIG.PSU_MIO_57_SLEW {slow} \ CONFIG.PSU_MIO_58_DRIVE_STRENGTH {4} \ + CONFIG.PSU_MIO_58_PULLUPDOWN {pullup} \ CONFIG.PSU_MIO_58_SLEW {slow} \ CONFIG.PSU_MIO_59_DRIVE_STRENGTH {4} \ + CONFIG.PSU_MIO_59_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_59_PULLUPDOWN {pullup} \ CONFIG.PSU_MIO_59_SLEW {slow} \ CONFIG.PSU_MIO_5_DRIVE_STRENGTH {4} \ + CONFIG.PSU_MIO_5_PULLUPDOWN {pullup} \ CONFIG.PSU_MIO_5_SLEW {slow} \ CONFIG.PSU_MIO_60_DRIVE_STRENGTH {4} \ + CONFIG.PSU_MIO_60_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_60_PULLUPDOWN {pullup} \ CONFIG.PSU_MIO_60_SLEW {slow} \ CONFIG.PSU_MIO_61_DRIVE_STRENGTH {4} \ + CONFIG.PSU_MIO_61_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_61_PULLUPDOWN {pullup} \ CONFIG.PSU_MIO_61_SLEW {slow} \ CONFIG.PSU_MIO_62_DRIVE_STRENGTH {4} \ + CONFIG.PSU_MIO_62_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_62_PULLUPDOWN {pullup} \ CONFIG.PSU_MIO_62_SLEW {slow} \ CONFIG.PSU_MIO_63_DRIVE_STRENGTH {4} \ + CONFIG.PSU_MIO_63_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_63_PULLUPDOWN {pullup} \ CONFIG.PSU_MIO_63_SLEW {slow} \ CONFIG.PSU_MIO_64_DRIVE_STRENGTH {4} \ + CONFIG.PSU_MIO_64_PULLUPDOWN {pullup} \ CONFIG.PSU_MIO_64_SLEW {slow} \ CONFIG.PSU_MIO_65_DRIVE_STRENGTH {4} \ + CONFIG.PSU_MIO_65_PULLUPDOWN {pullup} \ CONFIG.PSU_MIO_65_SLEW {slow} \ CONFIG.PSU_MIO_66_DRIVE_STRENGTH {4} \ + CONFIG.PSU_MIO_66_PULLUPDOWN {pullup} \ CONFIG.PSU_MIO_66_SLEW {slow} \ CONFIG.PSU_MIO_67_DRIVE_STRENGTH {4} \ + CONFIG.PSU_MIO_67_PULLUPDOWN {pullup} \ CONFIG.PSU_MIO_67_SLEW {slow} \ CONFIG.PSU_MIO_68_DRIVE_STRENGTH {4} \ + CONFIG.PSU_MIO_68_PULLUPDOWN {pullup} \ CONFIG.PSU_MIO_68_SLEW {slow} \ CONFIG.PSU_MIO_69_DRIVE_STRENGTH {4} \ + CONFIG.PSU_MIO_69_PULLUPDOWN {pullup} \ CONFIG.PSU_MIO_69_SLEW {slow} \ CONFIG.PSU_MIO_6_DRIVE_STRENGTH {4} \ + CONFIG.PSU_MIO_6_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_6_PULLUPDOWN {pullup} \ CONFIG.PSU_MIO_6_SLEW {slow} \ + CONFIG.PSU_MIO_70_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_70_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_71_INPUT_TYPE {cmos} \ CONFIG.PSU_MIO_71_PULLUPDOWN {disable} \ + CONFIG.PSU_MIO_72_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_72_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_73_INPUT_TYPE {cmos} \ CONFIG.PSU_MIO_73_PULLUPDOWN {disable} \ + CONFIG.PSU_MIO_74_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_74_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_75_INPUT_TYPE {cmos} \ CONFIG.PSU_MIO_75_PULLUPDOWN {disable} \ CONFIG.PSU_MIO_76_DRIVE_STRENGTH {4} \ + CONFIG.PSU_MIO_76_PULLUPDOWN {pullup} \ CONFIG.PSU_MIO_76_SLEW {slow} \ CONFIG.PSU_MIO_77_DRIVE_STRENGTH {4} \ + CONFIG.PSU_MIO_77_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_77_PULLUPDOWN {pullup} \ CONFIG.PSU_MIO_77_SLEW {slow} \ CONFIG.PSU_MIO_7_DRIVE_STRENGTH {4} \ CONFIG.PSU_MIO_7_INPUT_TYPE {cmos} \ CONFIG.PSU_MIO_7_POLARITY {Default} \ + CONFIG.PSU_MIO_7_PULLUPDOWN {pullup} \ CONFIG.PSU_MIO_7_SLEW {slow} \ CONFIG.PSU_MIO_8_DRIVE_STRENGTH {4} \ + CONFIG.PSU_MIO_8_INPUT_TYPE {cmos} \ CONFIG.PSU_MIO_8_POLARITY {Default} \ + CONFIG.PSU_MIO_8_PULLUPDOWN {pullup} \ CONFIG.PSU_MIO_8_SLEW {slow} \ CONFIG.PSU_MIO_9_DRIVE_STRENGTH {4} \ + CONFIG.PSU_MIO_9_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_9_PULLUPDOWN {pullup} \ CONFIG.PSU_MIO_9_SLEW {slow} \ CONFIG.PSU_MIO_TREE_PERIPHERALS {Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#SPI 1#GPIO0 MIO#GPIO0 MIO#SPI 1#SPI 1#SPI 1#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0\ MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#I2C 1#I2C 1#PMU GPI 0#DPAUX#DPAUX#DPAUX#DPAUX#PMU GPI 5#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#PMU GPO 3#UART 1#UART 1#GPIO1 MIO#SD\ @@ -366,20 +519,72 @@ MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 3#Gem 3#MDIO 3#MDIO 3} \ CONFIG.PSU_MIO_TREE_SIGNALS {sclk_out#miso_mo1#mo2#mo3#mosi_mi0#n_ss_out#sclk_out#gpio0[7]#gpio0[8]#n_ss_out[0]#miso#mosi#gpio0[12]#gpio0[13]#gpio0[14]#gpio0[15]#gpio0[16]#gpio0[17]#gpio0[18]#gpio0[19]#gpio0[20]#gpio0[21]#gpio0[22]#gpio0[23]#scl_out#sda_out#gpi[0]#dp_aux_data_out#dp_hot_plug_detect#dp_aux_data_oe#dp_aux_data_in#gpi[5]#gpio1[32]#gpio1[33]#gpio1[34]#gpo[3]#txd#rxd#gpio1[38]#sdio1_data_out[4]#sdio1_data_out[5]#sdio1_data_out[6]#sdio1_data_out[7]#sdio1_bus_pow#gpio1[44]#sdio1_cd_n#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#rgmii_tx_clk#rgmii_txd[0]#rgmii_txd[1]#rgmii_txd[2]#rgmii_txd[3]#rgmii_tx_ctl#rgmii_rx_clk#rgmii_rxd[0]#rgmii_rxd[1]#rgmii_rxd[2]#rgmii_rxd[3]#rgmii_rx_ctl#gem3_mdc#gem3_mdio_out}\ \ + CONFIG.PSU_PERIPHERAL_BOARD_PRESET {} \ + CONFIG.PSU_SD0_INTERNAL_BUS_WIDTH {8} \ CONFIG.PSU_SD1_INTERNAL_BUS_WIDTH {8} \ + CONFIG.PSU_SMC_CYCLE_T0 {NA} \ + CONFIG.PSU_SMC_CYCLE_T1 {NA} \ + CONFIG.PSU_SMC_CYCLE_T2 {NA} \ + CONFIG.PSU_SMC_CYCLE_T3 {NA} \ + CONFIG.PSU_SMC_CYCLE_T4 {NA} \ + CONFIG.PSU_SMC_CYCLE_T5 {NA} \ + CONFIG.PSU_SMC_CYCLE_T6 {NA} \ CONFIG.PSU_USB3__DUAL_CLOCK_ENABLE {1} \ + CONFIG.PSU_VALUE_SILVERSION {3} \ + CONFIG.PSU__ACPU0__POWER__ON {1} \ + CONFIG.PSU__ACPU1__POWER__ON {1} \ + CONFIG.PSU__ACPU2__POWER__ON {1} \ + CONFIG.PSU__ACPU3__POWER__ON {1} \ + CONFIG.PSU__ACTUAL__IP {1} \ CONFIG.PSU__ACT_DDR_FREQ_MHZ {1066.656006} \ + CONFIG.PSU__AUX_REF_CLK__FREQMHZ {33.333} \ + CONFIG.PSU__CAN0_LOOP_CAN1__ENABLE {0} \ + CONFIG.PSU__CAN0__PERIPHERAL__ENABLE {0} \ CONFIG.PSU__CAN1__PERIPHERAL__ENABLE {0} \ CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ {1333.333008} \ CONFIG.PSU__CRF_APB__ACPU_CTRL__FREQMHZ {1333.333} \ CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL {APLL} \ CONFIG.PSU__CRF_APB__ACPU__FRAC_ENABLED {1} \ + CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__ACT_FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__AFI0_REF__ENABLE {0} \ + CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__ACT_FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__AFI1_REF__ENABLE {0} \ + CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__ACT_FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__AFI2_REF__ENABLE {0} \ + CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__ACT_FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__AFI3_REF__ENABLE {0} \ + CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__ACT_FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__AFI4_REF__ENABLE {0} \ + CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__ACT_FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__AFI5_REF__ENABLE {0} \ CONFIG.PSU__CRF_APB__APLL_CTRL__FRACFREQ {1333.333} \ CONFIG.PSU__CRF_APB__APLL_CTRL__SRCSEL {PSS_REF_CLK} \ CONFIG.PSU__CRF_APB__APLL_FRAC_CFG__ENABLED {1} \ + CONFIG.PSU__CRF_APB__APM_CTRL__ACT_FREQMHZ {1} \ + CONFIG.PSU__CRF_APB__APM_CTRL__DIVISOR0 {1} \ + CONFIG.PSU__CRF_APB__APM_CTRL__FREQMHZ {1} \ CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ {249.997498} \ CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__FREQMHZ {250} \ CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__ACT_FREQMHZ {250} \ CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__FREQMHZ {250} \ CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL {IOPLL} \ CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ {249.997498} \ @@ -391,13 +596,17 @@ MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ {444.444336} \ CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__FREQMHZ {600} \ CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL {APLL} \ + CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACFREQ {27.138} \ CONFIG.PSU__CRF_APB__DPLL_CTRL__SRCSEL {PSS_REF_CLK} \ CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ {24.242182} \ + CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__FREQMHZ {25} \ CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {RPLL} \ CONFIG.PSU__CRF_APB__DP_AUDIO__FRAC_ENABLED {0} \ CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ {26.666401} \ + CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__FREQMHZ {27} \ CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {RPLL} \ CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ {299.997009} \ + CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__FREQMHZ {300} \ CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL {VPLL} \ CONFIG.PSU__CRF_APB__DP_VIDEO__FRAC_ENABLED {0} \ CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ {533.328003} \ @@ -406,33 +615,75 @@ MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 CONFIG.PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ {499.994995} \ CONFIG.PSU__CRF_APB__GPU_REF_CTRL__FREQMHZ {600} \ CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__ACT_FREQMHZ {-1} \ + CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__DIVISOR0 {-1} \ + CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__FREQMHZ {-1} \ + CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__SRCSEL {NA} \ + CONFIG.PSU__CRF_APB__GTGREF0__ENABLE {NA} \ + CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__ACT_FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__SATA_REF_CTRL__ACT_FREQMHZ {250} \ CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ {99.999001} \ CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__FREQMHZ {100} \ CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL {IOPLL} \ CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ {533.328003} \ CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__FREQMHZ {533.33} \ CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACFREQ {27.138} \ CONFIG.PSU__CRF_APB__VPLL_CTRL__SRCSEL {PSS_REF_CLK} \ CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ {499.994995} \ CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__FREQMHZ {500} \ CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__ACT_FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__AFI6__ENABLE {0} \ CONFIG.PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ {49.999500} \ + CONFIG.PSU__CRL_APB__AMS_REF_CTRL__FREQMHZ {50} \ + CONFIG.PSU__CRL_APB__AMS_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__ACT_FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__ACT_FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__FREQMHZ {100} \ CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL {IOPLL} \ CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ {533.328003} \ CONFIG.PSU__CRL_APB__CPU_R5_CTRL__FREQMHZ {533.333} \ CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL {RPLL} \ + CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__ACT_FREQMHZ {180} \ + CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__SRCSEL {SysOsc} \ CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ {249.997498} \ CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__FREQMHZ {250} \ CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__ACT_FREQMHZ {1000} \ + CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__DIVISOR0 {6} \ + CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__FREQMHZ {1000} \ + CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__SRCSEL {RPLL} \ CONFIG.PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ {1499.984985} \ + CONFIG.PSU__CRL_APB__DLL_REF_CTRL__FREQMHZ {1500} \ + CONFIG.PSU__CRL_APB__DLL_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__ACT_FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__ACT_FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__ACT_FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__SRCSEL {IOPLL} \ CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__ACT_FREQMHZ {124.998749} \ CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__FREQMHZ {125} \ CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL {IOPLL} \ CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__ACT_FREQMHZ {249.997498} \ + CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__FREQMHZ {250} \ CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__ACT_FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL {IOPLL} \ CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ {99.999001} \ CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__FREQMHZ {100} \ CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACFREQ {27.138} \ CONFIG.PSU__CRL_APB__IOPLL_CTRL__SRCSEL {PSS_REF_CLK} \ CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ {249.997498} \ CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__FREQMHZ {250} \ @@ -443,6 +694,13 @@ MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ {499.994995} \ CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__FREQMHZ {500} \ CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__NAND_REF_CTRL__ACT_FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__NAND_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__NAND_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__ACT_FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__SRCSEL {IOPLL} \ CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ {187.498123} \ CONFIG.PSU__CRL_APB__PCAP_CTRL__FREQMHZ {200} \ CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL {IOPLL} \ @@ -452,29 +710,60 @@ MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 CONFIG.PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ {99.999001} \ CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ {100} \ CONFIG.PSU__CRL_APB__PL1_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__PL2_REF_CTRL__ACT_FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__PL3_REF_CTRL__ACT_FREQMHZ {100} \ CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__ACT_FREQMHZ {124.998749} \ CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__FREQMHZ {125} \ CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACFREQ {27.138} \ CONFIG.PSU__CRL_APB__RPLL_CTRL__SRCSEL {PSS_REF_CLK} \ + CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__ACT_FREQMHZ {200} \ + CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__FREQMHZ {200} \ + CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__SRCSEL {RPLL} \ CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ {187.498123} \ CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__FREQMHZ {200} \ CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__ACT_FREQMHZ {214} \ + CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__FREQMHZ {200} \ + CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__SRCSEL {RPLL} \ CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__ACT_FREQMHZ {187.498123} \ + CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__FREQMHZ {200} \ CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__SRCSEL {IOPLL} \ CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ {99.999001} \ CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__FREQMHZ {100} \ CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__UART0_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__UART0_REF_CTRL__SRCSEL {IOPLL} \ CONFIG.PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ {99.999001} \ CONFIG.PSU__CRL_APB__UART1_REF_CTRL__FREQMHZ {100} \ CONFIG.PSU__CRL_APB__UART1_REF_CTRL__SRCSEL {IOPLL} \ CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ {249.997498} \ CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ {250} \ CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__ACT_FREQMHZ {250} \ + CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__SRCSEL {IOPLL} \ CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ {19.999800} \ CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ {20} \ CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL {IOPLL} \ CONFIG.PSU__CRL_APB__USB3__ENABLE {1} \ CONFIG.PSU__CSUPMU__PERIPHERAL__VALID {1} \ + CONFIG.PSU__CSU__CSU_TAMPER_0__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_10__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_11__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_12__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_1__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_2__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_3__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_4__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_5__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_6__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_7__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_8__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_9__ENABLE {0} \ + CONFIG.PSU__CSU__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__DDRC__AL {0} \ CONFIG.PSU__DDRC__BG_ADDR_COUNT {1} \ CONFIG.PSU__DDRC__BRC_MAPPING {ROW_BANK_COL} \ CONFIG.PSU__DDRC__BUS_WIDTH {64 Bit} \ @@ -485,19 +774,30 @@ MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING {0} \ CONFIG.PSU__DDRC__DDR4_CAL_MODE_ENABLE {0} \ CONFIG.PSU__DDRC__DDR4_CRC_CONTROL {0} \ + CONFIG.PSU__DDRC__DDR4_MAXPWR_SAVING_EN {0} \ CONFIG.PSU__DDRC__DDR4_T_REF_MODE {0} \ CONFIG.PSU__DDRC__DDR4_T_REF_RANGE {Normal (0-85)} \ CONFIG.PSU__DDRC__DEVICE_CAPACITY {8192 MBits} \ CONFIG.PSU__DDRC__DM_DBI {DM_NO_DBI} \ CONFIG.PSU__DDRC__DRAM_WIDTH {16 Bits} \ CONFIG.PSU__DDRC__ECC {Disabled} \ + CONFIG.PSU__DDRC__ECC_SCRUB {0} \ + CONFIG.PSU__DDRC__ENABLE {1} \ + CONFIG.PSU__DDRC__ENABLE_2T_TIMING {0} \ + CONFIG.PSU__DDRC__ENABLE_DP_SWITCH {0} \ + CONFIG.PSU__DDRC__EN_2ND_CLK {0} \ CONFIG.PSU__DDRC__FGRM {1X} \ + CONFIG.PSU__DDRC__FREQ_MHZ {1} \ + CONFIG.PSU__DDRC__LPDDR3_DUALRANK_SDP {0} \ CONFIG.PSU__DDRC__LP_ASR {manual normal} \ CONFIG.PSU__DDRC__MEMORY_TYPE {DDR 4} \ CONFIG.PSU__DDRC__PARITY_ENABLE {0} \ CONFIG.PSU__DDRC__PER_BANK_REFRESH {0} \ CONFIG.PSU__DDRC__PHY_DBI_MODE {0} \ + CONFIG.PSU__DDRC__PLL_BYPASS {0} \ + CONFIG.PSU__DDRC__PWR_DOWN_EN {0} \ CONFIG.PSU__DDRC__RANK_ADDR_COUNT {0} \ + CONFIG.PSU__DDRC__RD_DQS_CENTER {0} \ CONFIG.PSU__DDRC__ROW_ADDR_COUNT {16} \ CONFIG.PSU__DDRC__SELF_REF_ABORT {0} \ CONFIG.PSU__DDRC__SPEED_BIN {DDR4_2400R} \ @@ -510,9 +810,21 @@ MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 CONFIG.PSU__DDRC__T_RC {47.06} \ CONFIG.PSU__DDRC__T_RCD {16} \ CONFIG.PSU__DDRC__T_RP {16} \ + CONFIG.PSU__DDRC__VIDEO_BUFFER_SIZE {0} \ CONFIG.PSU__DDRC__VREF {1} \ CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE {1} \ + CONFIG.PSU__DDR_QOS_ENABLE {0} \ + CONFIG.PSU__DDR_QOS_HP0_RDQOS {} \ + CONFIG.PSU__DDR_QOS_HP0_WRQOS {} \ + CONFIG.PSU__DDR_QOS_HP1_RDQOS {} \ + CONFIG.PSU__DDR_QOS_HP1_WRQOS {} \ + CONFIG.PSU__DDR_QOS_HP2_RDQOS {} \ + CONFIG.PSU__DDR_QOS_HP2_WRQOS {} \ + CONFIG.PSU__DDR_QOS_HP3_RDQOS {} \ + CONFIG.PSU__DDR_QOS_HP3_WRQOS {} \ + CONFIG.PSU__DDR_SW_REFRESH_ENABLED {1} \ CONFIG.PSU__DDR__INTERFACE__FREQMHZ {600.000} \ + CONFIG.PSU__DEVICE_TYPE {EV} \ CONFIG.PSU__DISPLAYPORT__LANE0__ENABLE {1} \ CONFIG.PSU__DISPLAYPORT__LANE0__IO {GT Lane1} \ CONFIG.PSU__DISPLAYPORT__LANE1__ENABLE {1} \ @@ -524,6 +836,10 @@ MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 CONFIG.PSU__DP__LANE_SEL {Dual Lower} \ CONFIG.PSU__DP__REF_CLK_FREQ {27} \ CONFIG.PSU__DP__REF_CLK_SEL {Ref Clk0} \ + CONFIG.PSU__ENABLE__DDR__REFRESH__SIGNALS {0} \ + CONFIG.PSU__ENET0__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__ENET1__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__ENET2__PERIPHERAL__ENABLE {0} \ CONFIG.PSU__ENET3__FIFO__ENABLE {0} \ CONFIG.PSU__ENET3__GRP_MDIO__ENABLE {1} \ CONFIG.PSU__ENET3__GRP_MDIO__IO {MIO 76 .. 77} \ @@ -531,20 +847,68 @@ MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 CONFIG.PSU__ENET3__PERIPHERAL__IO {MIO 64 .. 75} \ CONFIG.PSU__ENET3__PTP__ENABLE {0} \ CONFIG.PSU__ENET3__TSU__ENABLE {0} \ + CONFIG.PSU__EN_AXI_STATUS_PORTS {0} \ + CONFIG.PSU__EN_EMIO_TRACE {0} \ + CONFIG.PSU__EP__IP {0} \ + CONFIG.PSU__EXPAND__CORESIGHT {0} \ + CONFIG.PSU__EXPAND__FPD_SLAVES {0} \ + CONFIG.PSU__EXPAND__GIC {0} \ + CONFIG.PSU__EXPAND__LOWER_LPS_SLAVES {0} \ + CONFIG.PSU__EXPAND__UPPER_LPS_SLAVES {0} \ CONFIG.PSU__FPD_SLCR__WDT1__ACT_FREQMHZ {99.999001} \ CONFIG.PSU__FPGA_PL0_ENABLE {1} \ CONFIG.PSU__FPGA_PL1_ENABLE {1} \ + CONFIG.PSU__FPGA_PL2_ENABLE {0} \ + CONFIG.PSU__FPGA_PL3_ENABLE {0} \ + CONFIG.PSU__FP__POWER__ON {1} \ + CONFIG.PSU__FTM__CTI_IN_0 {0} \ + CONFIG.PSU__FTM__CTI_IN_1 {0} \ + CONFIG.PSU__FTM__CTI_IN_2 {0} \ + CONFIG.PSU__FTM__CTI_IN_3 {0} \ + CONFIG.PSU__FTM__CTI_OUT_0 {0} \ + CONFIG.PSU__FTM__CTI_OUT_1 {0} \ + CONFIG.PSU__FTM__CTI_OUT_2 {0} \ + CONFIG.PSU__FTM__CTI_OUT_3 {0} \ + CONFIG.PSU__FTM__GPI {0} \ + CONFIG.PSU__FTM__GPO {0} \ CONFIG.PSU__GEM3_COHERENCY {0} \ CONFIG.PSU__GEM3_ROUTE_THROUGH_FPD {0} \ CONFIG.PSU__GEM__TSU__ENABLE {0} \ + CONFIG.PSU__GEN_IPI_0__MASTER {APU} \ + CONFIG.PSU__GEN_IPI_10__MASTER {NONE} \ + CONFIG.PSU__GEN_IPI_1__MASTER {RPU0} \ + CONFIG.PSU__GEN_IPI_2__MASTER {RPU1} \ + CONFIG.PSU__GEN_IPI_3__MASTER {PMU} \ + CONFIG.PSU__GEN_IPI_4__MASTER {PMU} \ + CONFIG.PSU__GEN_IPI_5__MASTER {PMU} \ + CONFIG.PSU__GEN_IPI_6__MASTER {PMU} \ + CONFIG.PSU__GEN_IPI_7__MASTER {NONE} \ + CONFIG.PSU__GEN_IPI_8__MASTER {NONE} \ + CONFIG.PSU__GEN_IPI_9__MASTER {NONE} \ CONFIG.PSU__GPIO0_MIO__IO {MIO 0 .. 25} \ CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {1} \ CONFIG.PSU__GPIO1_MIO__IO {MIO 26 .. 51} \ CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__GPIO2_MIO__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__GPIO_EMIO_WIDTH {1} \ + CONFIG.PSU__GPIO_EMIO__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__GPIO_EMIO__WIDTH {[94:0]} \ + CONFIG.PSU__GPU_PP0__POWER__ON {1} \ + CONFIG.PSU__GPU_PP1__POWER__ON {1} \ + CONFIG.PSU__GT_REF_CLK__FREQMHZ {33.333} \ CONFIG.PSU__GT__LINK_SPEED {HBR} \ CONFIG.PSU__GT__PRE_EMPH_LVL_4 {0} \ CONFIG.PSU__GT__VLT_SWNG_LVL_4 {0} \ + CONFIG.PSU__HPM0_FPD__NUM_READ_THREADS {4} \ + CONFIG.PSU__HPM0_FPD__NUM_WRITE_THREADS {4} \ + CONFIG.PSU__HPM0_LPD__NUM_READ_THREADS {4} \ + CONFIG.PSU__HPM0_LPD__NUM_WRITE_THREADS {4} \ + CONFIG.PSU__HPM1_FPD__NUM_READ_THREADS {4} \ + CONFIG.PSU__HPM1_FPD__NUM_WRITE_THREADS {4} \ + CONFIG.PSU__I2C0_LOOP_I2C1__ENABLE {0} \ + CONFIG.PSU__I2C0__GRP_INT__ENABLE {0} \ CONFIG.PSU__I2C0__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__I2C1__GRP_INT__ENABLE {0} \ CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} \ CONFIG.PSU__I2C1__PERIPHERAL__IO {MIO 24 .. 25} \ CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC0_SEL {APB} \ @@ -556,11 +920,121 @@ MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 CONFIG.PSU__IOU_SLCR__TTC2__ACT_FREQMHZ {100.000000} \ CONFIG.PSU__IOU_SLCR__TTC3__ACT_FREQMHZ {100.000000} \ CONFIG.PSU__IOU_SLCR__WDT0__ACT_FREQMHZ {99.999001} \ + CONFIG.PSU__IRQ_P2F_ADMA_CHAN__INT {0} \ + CONFIG.PSU__IRQ_P2F_AIB_AXI__INT {0} \ + CONFIG.PSU__IRQ_P2F_AMS__INT {0} \ + CONFIG.PSU__IRQ_P2F_APM_FPD__INT {0} \ + CONFIG.PSU__IRQ_P2F_APU_COMM__INT {0} \ + CONFIG.PSU__IRQ_P2F_APU_CPUMNT__INT {0} \ + CONFIG.PSU__IRQ_P2F_APU_CTI__INT {0} \ + CONFIG.PSU__IRQ_P2F_APU_EXTERR__INT {0} \ + CONFIG.PSU__IRQ_P2F_APU_IPI__INT {0} \ + CONFIG.PSU__IRQ_P2F_APU_L2ERR__INT {0} \ + CONFIG.PSU__IRQ_P2F_APU_PMU__INT {0} \ + CONFIG.PSU__IRQ_P2F_APU_REGS__INT {0} \ + CONFIG.PSU__IRQ_P2F_ATB_LPD__INT {0} \ + CONFIG.PSU__IRQ_P2F_CLKMON__INT {0} \ + CONFIG.PSU__IRQ_P2F_CSUPMU_WDT__INT {0} \ + CONFIG.PSU__IRQ_P2F_DDR_SS__INT {0} \ + CONFIG.PSU__IRQ_P2F_DPDMA__INT {0} \ + CONFIG.PSU__IRQ_P2F_DPORT__INT {0} \ + CONFIG.PSU__IRQ_P2F_EFUSE__INT {0} \ + CONFIG.PSU__IRQ_P2F_ENT3_WAKEUP__INT {0} \ + CONFIG.PSU__IRQ_P2F_ENT3__INT {0} \ + CONFIG.PSU__IRQ_P2F_FPD_APB__INT {0} \ + CONFIG.PSU__IRQ_P2F_FPD_ATB_ERR__INT {0} \ + CONFIG.PSU__IRQ_P2F_FP_WDT__INT {0} \ + CONFIG.PSU__IRQ_P2F_GDMA_CHAN__INT {0} \ + CONFIG.PSU__IRQ_P2F_GPIO__INT {0} \ + CONFIG.PSU__IRQ_P2F_GPU__INT {0} \ + CONFIG.PSU__IRQ_P2F_I2C1__INT {0} \ + CONFIG.PSU__IRQ_P2F_LPD_APB__INT {0} \ + CONFIG.PSU__IRQ_P2F_LPD_APM__INT {0} \ + CONFIG.PSU__IRQ_P2F_LP_WDT__INT {0} \ + CONFIG.PSU__IRQ_P2F_OCM_ERR__INT {0} \ + CONFIG.PSU__IRQ_P2F_PCIE_DMA__INT {0} \ + CONFIG.PSU__IRQ_P2F_PCIE_LEGACY__INT {0} \ + CONFIG.PSU__IRQ_P2F_PCIE_MSC__INT {0} \ + CONFIG.PSU__IRQ_P2F_PCIE_MSI__INT {0} \ + CONFIG.PSU__IRQ_P2F_PL_IPI__INT {0} \ + CONFIG.PSU__IRQ_P2F_QSPI__INT {0} \ + CONFIG.PSU__IRQ_P2F_R5_CORE0_ECC_ERR__INT {0} \ + CONFIG.PSU__IRQ_P2F_R5_CORE1_ECC_ERR__INT {0} \ + CONFIG.PSU__IRQ_P2F_RPU_IPI__INT {0} \ + CONFIG.PSU__IRQ_P2F_RPU_PERMON__INT {0} \ + CONFIG.PSU__IRQ_P2F_RTC_ALARM__INT {0} \ + CONFIG.PSU__IRQ_P2F_RTC_SECONDS__INT {0} \ + CONFIG.PSU__IRQ_P2F_SATA__INT {0} \ + CONFIG.PSU__IRQ_P2F_SDIO1_WAKE__INT {0} \ + CONFIG.PSU__IRQ_P2F_SDIO1__INT {0} \ + CONFIG.PSU__IRQ_P2F_SPI1__INT {0} \ + CONFIG.PSU__IRQ_P2F_TTC0__INT0 {0} \ + CONFIG.PSU__IRQ_P2F_TTC0__INT1 {0} \ + CONFIG.PSU__IRQ_P2F_TTC0__INT2 {0} \ + CONFIG.PSU__IRQ_P2F_TTC1__INT0 {0} \ + CONFIG.PSU__IRQ_P2F_TTC1__INT1 {0} \ + CONFIG.PSU__IRQ_P2F_TTC1__INT2 {0} \ + CONFIG.PSU__IRQ_P2F_TTC2__INT0 {0} \ + CONFIG.PSU__IRQ_P2F_TTC2__INT1 {0} \ + CONFIG.PSU__IRQ_P2F_TTC2__INT2 {0} \ + CONFIG.PSU__IRQ_P2F_TTC3__INT0 {0} \ + CONFIG.PSU__IRQ_P2F_TTC3__INT1 {0} \ + CONFIG.PSU__IRQ_P2F_TTC3__INT2 {0} \ + CONFIG.PSU__IRQ_P2F_UART1__INT {0} \ + CONFIG.PSU__IRQ_P2F_USB3_ENDPOINT__INT0 {0} \ + CONFIG.PSU__IRQ_P2F_USB3_ENDPOINT__INT1 {0} \ + CONFIG.PSU__IRQ_P2F_USB3_OTG__INT0 {0} \ + CONFIG.PSU__IRQ_P2F_USB3_OTG__INT1 {0} \ + CONFIG.PSU__IRQ_P2F_USB3_PMU_WAKEUP__INT {0} \ + CONFIG.PSU__IRQ_P2F_XMPU_FPD__INT {0} \ + CONFIG.PSU__IRQ_P2F_XMPU_LPD__INT {0} \ + CONFIG.PSU__IRQ_P2F__INTF_FPD_SMMU__INT {0} \ + CONFIG.PSU__IRQ_P2F__INTF_PPD_CCI__INT {0} \ + CONFIG.PSU__L2_BANK0__POWER__ON {1} \ + CONFIG.PSU__LPDMA0_COHERENCY {0} \ + CONFIG.PSU__LPDMA1_COHERENCY {0} \ + CONFIG.PSU__LPDMA2_COHERENCY {0} \ + CONFIG.PSU__LPDMA3_COHERENCY {0} \ + CONFIG.PSU__LPDMA4_COHERENCY {0} \ + CONFIG.PSU__LPDMA5_COHERENCY {0} \ + CONFIG.PSU__LPDMA6_COHERENCY {0} \ + CONFIG.PSU__LPDMA7_COHERENCY {0} \ + CONFIG.PSU__LPD_SLCR__CSUPMU_WDT_CLK_SEL__SELECT {APB} \ CONFIG.PSU__LPD_SLCR__CSUPMU__ACT_FREQMHZ {100.000000} \ CONFIG.PSU__MAXIGP2__DATA_WIDTH {32} \ + CONFIG.PSU__M_AXI_GP0_SUPPORTS_NARROW_BURST {1} \ + CONFIG.PSU__M_AXI_GP1_SUPPORTS_NARROW_BURST {1} \ + CONFIG.PSU__M_AXI_GP2_SUPPORTS_NARROW_BURST {1} \ + CONFIG.PSU__NAND__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__NAND__READY_BUSY__ENABLE {0} \ + CONFIG.PSU__NUM_FABRIC_RESETS {1} \ + CONFIG.PSU__OCM_BANK0__POWER__ON {1} \ + CONFIG.PSU__OCM_BANK1__POWER__ON {1} \ + CONFIG.PSU__OCM_BANK2__POWER__ON {1} \ + CONFIG.PSU__OCM_BANK3__POWER__ON {1} \ + CONFIG.PSU__OVERRIDE_HPX_QOS {0} \ CONFIG.PSU__OVERRIDE__BASIC_CLOCK {0} \ + CONFIG.PSU__PCIE__ACS_VIOLAION {0} \ + CONFIG.PSU__PCIE__AER_CAPABILITY {0} \ + CONFIG.PSU__PCIE__CLASS_CODE_BASE {} \ + CONFIG.PSU__PCIE__CLASS_CODE_INTERFACE {} \ + CONFIG.PSU__PCIE__CLASS_CODE_SUB {} \ + CONFIG.PSU__PCIE__DEVICE_ID {} \ + CONFIG.PSU__PCIE__INTX_GENERATION {0} \ + CONFIG.PSU__PCIE__MSIX_CAPABILITY {0} \ + CONFIG.PSU__PCIE__MSI_CAPABILITY {0} \ + CONFIG.PSU__PCIE__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__PCIE__PERIPHERAL__ENDPOINT_ENABLE {1} \ + CONFIG.PSU__PCIE__PERIPHERAL__ROOTPORT_ENABLE {0} \ + CONFIG.PSU__PCIE__RESET__POLARITY {Active Low} \ + CONFIG.PSU__PCIE__REVISION_ID {} \ + CONFIG.PSU__PCIE__SUBSYSTEM_ID {} \ + CONFIG.PSU__PCIE__SUBSYSTEM_VENDOR_ID {} \ + CONFIG.PSU__PCIE__VENDOR_ID {} \ + CONFIG.PSU__PJTAG__PERIPHERAL__ENABLE {0} \ CONFIG.PSU__PL_CLK0_BUF {TRUE} \ CONFIG.PSU__PL_CLK1_BUF {TRUE} \ + CONFIG.PSU__PL__POWER__ON {1} \ CONFIG.PSU__PMU_COHERENCY {0} \ CONFIG.PSU__PMU__AIBACK__ENABLE {0} \ CONFIG.PSU__PMU__EMIO_GPI__ENABLE {0} \ @@ -584,11 +1058,32 @@ MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 CONFIG.PSU__PMU__PERIPHERAL__ENABLE {1} \ CONFIG.PSU__PMU__PLERROR__ENABLE {0} \ CONFIG.PSU__PRESET_APPLIED {1} \ + CONFIG.PSU__PROTECTION__DDR_SEGMENTS {NONE} \ + CONFIG.PSU__PROTECTION__ENABLE {0} \ + CONFIG.PSU__PROTECTION__FPD_SEGMENTS {SA:0xFD1A0000; SIZE:1280; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD000000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\ +subsystemId:PMU Firmware | SA:0xFD010000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD020000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU\ +Firmware | SA:0xFD030000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD040000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware\ +| SA:0xFD050000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD610000; SIZE:512; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware\ +| SA:0xFD5D0000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD1A0000 ; SIZE:1280; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem}\ +\ + CONFIG.PSU__PROTECTION__LPD_SEGMENTS {SA:0xFF980000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFF5E0000; SIZE:2560; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\ +subsystemId:PMU Firmware| SA:0xFFCC0000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFF180000; SIZE:768; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU\ +Firmware| SA:0xFF410000; SIZE:640; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFFA70000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware|\ +SA:0xFF9A0000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware|SA:0xFF5E0000 ; SIZE:2560; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem|SA:0xFFCC0000\ +; SIZE:64; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem|SA:0xFF180000 ; SIZE:768; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem|SA:0xFF9A0000\ +; SIZE:64; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem} \ CONFIG.PSU__PROTECTION__MASTERS {USB1:NonSecure;0|USB0:NonSecure;1|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;0|S_AXI_HPC0_FPD:NA;0|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;0|S_AXI_HP1_FPD:NA;0|S_AXI_HP0_FPD:NA;0|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;1|SD0:NonSecure;0|SATA1:NonSecure;0|SATA0:NonSecure;0|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;1|PMU:NA;1|PCIe:NonSecure;0|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;1|GEM2:NonSecure;0|GEM1:NonSecure;0|GEM0:NonSecure;0|FDMA:NonSecure;1|DP:NonSecure;1|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1}\ \ + CONFIG.PSU__PROTECTION__MASTERS_TZ {GEM0:NonSecure|SD1:NonSecure|GEM2:NonSecure|GEM1:NonSecure|GEM3:NonSecure|PCIe:NonSecure|DP:NonSecure|NAND:NonSecure|GPU:NonSecure|USB1:NonSecure|USB0:NonSecure|LDMA:NonSecure|FDMA:NonSecure|QSPI:NonSecure|SD0:NonSecure}\ +\ + CONFIG.PSU__PROTECTION__OCM_SEGMENTS {NONE} \ + CONFIG.PSU__PROTECTION__PRESUBSYSTEMS {NONE} \ CONFIG.PSU__PROTECTION__SLAVES {LPD;USB3_1_XHCI;FE300000;FE3FFFFF;0|LPD;USB3_1;FF9E0000;FF9EFFFF;0|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;1|LPD;USB3_0;FF9D0000;FF9DFFFF;1|LPD;UART1;FF010000;FF01FFFF;1|LPD;UART0;FF000000;FF00FFFF;0|LPD;TTC3;FF140000;FF14FFFF;1|LPD;TTC2;FF130000;FF13FFFF;1|LPD;TTC1;FF120000;FF12FFFF;1|LPD;TTC0;FF110000;FF11FFFF;1|FPD;SWDT1;FD4D0000;FD4DFFFF;1|LPD;SWDT0;FF150000;FF15FFFF;1|LPD;SPI1;FF050000;FF05FFFF;1|LPD;SPI0;FF040000;FF04FFFF;0|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;0|FPD;SATA;FD0C0000;FD0CFFFF;0|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;1|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;0|FPD;PCIE_LOW;E0000000;EFFFFFFF;0|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;0|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;0|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;0|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;0|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;0|FPD;GPU;FD4B0000;FD4BFFFF;1|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;1|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;0|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display\ Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;87FFFFFFF;1|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;1|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;0|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9010000;F907FFFF;1}\ \ + CONFIG.PSU__PROTECTION__SUBSYSTEMS {PMU Firmware:PMU|Secure Subsystem:} \ + CONFIG.PSU__PSS_ALT_REF_CLK__ENABLE {0} \ + CONFIG.PSU__PSS_ALT_REF_CLK__FREQMHZ {33.333} \ CONFIG.PSU__PSS_REF_CLK__FREQMHZ {33.333} \ CONFIG.PSU__QSPI_COHERENCY {0} \ CONFIG.PSU__QSPI_ROUTE_THROUGH_FPD {0} \ @@ -597,6 +1092,18 @@ Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD05000 CONFIG.PSU__QSPI__PERIPHERAL__ENABLE {1} \ CONFIG.PSU__QSPI__PERIPHERAL__IO {MIO 0 .. 5} \ CONFIG.PSU__QSPI__PERIPHERAL__MODE {Single} \ + CONFIG.PSU__REPORT__DBGLOG {0} \ + CONFIG.PSU__RPU_COHERENCY {0} \ + CONFIG.PSU__RPU__POWER__ON {1} \ + CONFIG.PSU__SATA__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__SD0__CLK_100_SDR_OTAP_DLY {0x3} \ + CONFIG.PSU__SD0__CLK_200_SDR_OTAP_DLY {0x3} \ + CONFIG.PSU__SD0__CLK_50_DDR_ITAP_DLY {0x3D} \ + CONFIG.PSU__SD0__CLK_50_DDR_OTAP_DLY {0x4} \ + CONFIG.PSU__SD0__CLK_50_SDR_ITAP_DLY {0x15} \ + CONFIG.PSU__SD0__CLK_50_SDR_OTAP_DLY {0x5} \ + CONFIG.PSU__SD0__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__SD0__RESET__ENABLE {0} \ CONFIG.PSU__SD1_COHERENCY {0} \ CONFIG.PSU__SD1_ROUTE_THROUGH_FPD {0} \ CONFIG.PSU__SD1__CLK_100_SDR_OTAP_DLY {0x3} \ @@ -614,6 +1121,8 @@ Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD05000 CONFIG.PSU__SD1__PERIPHERAL__ENABLE {1} \ CONFIG.PSU__SD1__PERIPHERAL__IO {MIO 39 .. 51} \ CONFIG.PSU__SD1__SLOT_TYPE {SD 3.0} \ + CONFIG.PSU__SPI0_LOOP_SPI1__ENABLE {0} \ + CONFIG.PSU__SPI0__PERIPHERAL__ENABLE {0} \ CONFIG.PSU__SPI1__GRP_SS0__IO {MIO 9} \ CONFIG.PSU__SPI1__GRP_SS1__ENABLE {0} \ CONFIG.PSU__SPI1__GRP_SS2__ENABLE {0} \ @@ -621,23 +1130,39 @@ Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD05000 CONFIG.PSU__SPI1__PERIPHERAL__IO {MIO 6 .. 11} \ CONFIG.PSU__SWDT0__CLOCK__ENABLE {0} \ CONFIG.PSU__SWDT0__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__SWDT0__PERIPHERAL__IO {NA} \ CONFIG.PSU__SWDT0__RESET__ENABLE {0} \ CONFIG.PSU__SWDT1__CLOCK__ENABLE {0} \ CONFIG.PSU__SWDT1__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__SWDT1__PERIPHERAL__IO {NA} \ CONFIG.PSU__SWDT1__RESET__ENABLE {0} \ + CONFIG.PSU__TCM0A__POWER__ON {1} \ + CONFIG.PSU__TCM0B__POWER__ON {1} \ + CONFIG.PSU__TCM1A__POWER__ON {1} \ + CONFIG.PSU__TCM1B__POWER__ON {1} \ + CONFIG.PSU__TESTSCAN__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__TRACE__INTERNAL_WIDTH {32} \ + CONFIG.PSU__TRACE__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__TRISTATE__INVERTED {1} \ CONFIG.PSU__TSU__BUFG_PORT_PAIR {0} \ CONFIG.PSU__TTC0__CLOCK__ENABLE {0} \ CONFIG.PSU__TTC0__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__TTC0__PERIPHERAL__IO {NA} \ CONFIG.PSU__TTC0__WAVEOUT__ENABLE {0} \ CONFIG.PSU__TTC1__CLOCK__ENABLE {0} \ CONFIG.PSU__TTC1__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__TTC1__PERIPHERAL__IO {NA} \ CONFIG.PSU__TTC1__WAVEOUT__ENABLE {0} \ CONFIG.PSU__TTC2__CLOCK__ENABLE {0} \ CONFIG.PSU__TTC2__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__TTC2__PERIPHERAL__IO {NA} \ CONFIG.PSU__TTC2__WAVEOUT__ENABLE {0} \ CONFIG.PSU__TTC3__CLOCK__ENABLE {0} \ CONFIG.PSU__TTC3__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__TTC3__PERIPHERAL__IO {NA} \ CONFIG.PSU__TTC3__WAVEOUT__ENABLE {0} \ + CONFIG.PSU__UART0_LOOP_UART1__ENABLE {0} \ + CONFIG.PSU__UART0__PERIPHERAL__ENABLE {0} \ CONFIG.PSU__UART1__BAUD_RATE {115200} \ CONFIG.PSU__UART1__MODEM__ENABLE {0} \ CONFIG.PSU__UART1__PERIPHERAL__ENABLE {1} \ @@ -647,22 +1172,85 @@ Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD05000 CONFIG.PSU__USB0__PERIPHERAL__IO {MIO 52 .. 63} \ CONFIG.PSU__USB0__REF_CLK_FREQ {26} \ CONFIG.PSU__USB0__REF_CLK_SEL {Ref Clk1} \ + CONFIG.PSU__USB1__PERIPHERAL__ENABLE {0} \ CONFIG.PSU__USB2_0__EMIO__ENABLE {0} \ CONFIG.PSU__USB3_0__EMIO__ENABLE {0} \ CONFIG.PSU__USB3_0__PERIPHERAL__ENABLE {1} \ CONFIG.PSU__USB3_0__PERIPHERAL__IO {GT Lane2} \ CONFIG.PSU__USB__RESET__MODE {Boot Pin} \ CONFIG.PSU__USB__RESET__POLARITY {Active Low} \ + CONFIG.PSU__USE__ADMA {0} \ + CONFIG.PSU__USE__APU_LEGACY_INTERRUPT {0} \ + CONFIG.PSU__USE__AUDIO {0} \ + CONFIG.PSU__USE__CLK {0} \ + CONFIG.PSU__USE__CLK0 {0} \ + CONFIG.PSU__USE__CLK1 {0} \ + CONFIG.PSU__USE__CLK2 {0} \ + CONFIG.PSU__USE__CLK3 {0} \ + CONFIG.PSU__USE__CROSS_TRIGGER {0} \ + CONFIG.PSU__USE__DDR_INTF_REQUESTED {0} \ + CONFIG.PSU__USE__DEBUG__TEST {0} \ + CONFIG.PSU__USE__EVENT_RPU {0} \ + CONFIG.PSU__USE__FABRIC__RST {1} \ + CONFIG.PSU__USE__FTM {0} \ + CONFIG.PSU__USE__GDMA {0} \ + CONFIG.PSU__USE__IRQ {0} \ CONFIG.PSU__USE__IRQ0 {1} \ + CONFIG.PSU__USE__IRQ1 {0} \ CONFIG.PSU__USE__M_AXI_GP0 {0} \ CONFIG.PSU__USE__M_AXI_GP1 {0} \ CONFIG.PSU__USE__M_AXI_GP2 {1} \ + CONFIG.PSU__USE__PROC_EVENT_BUS {0} \ + CONFIG.PSU__USE__RPU_LEGACY_INTERRUPT {0} \ + CONFIG.PSU__USE__RST0 {0} \ + CONFIG.PSU__USE__RST1 {0} \ + CONFIG.PSU__USE__RST2 {0} \ + CONFIG.PSU__USE__RST3 {0} \ + CONFIG.PSU__USE__RTC {0} \ + CONFIG.PSU__USE__STM {0} \ + CONFIG.PSU__USE__S_AXI_ACE {0} \ + CONFIG.PSU__USE__S_AXI_ACP {0} \ + CONFIG.PSU__USE__S_AXI_GP0 {0} \ + CONFIG.PSU__USE__S_AXI_GP1 {0} \ + CONFIG.PSU__USE__S_AXI_GP2 {0} \ + CONFIG.PSU__USE__S_AXI_GP3 {0} \ + CONFIG.PSU__USE__S_AXI_GP4 {0} \ + CONFIG.PSU__USE__S_AXI_GP5 {0} \ + CONFIG.PSU__USE__S_AXI_GP6 {0} \ + CONFIG.PSU__USE__USB3_0_HUB {0} \ + CONFIG.PSU__USE__USB3_1_HUB {0} \ + CONFIG.PSU__USE__VIDEO {0} \ + CONFIG.PSU__VIDEO_REF_CLK__ENABLE {0} \ + CONFIG.PSU__VIDEO_REF_CLK__FREQMHZ {33.333} \ + CONFIG.QSPI_BOARD_INTERFACE {custom} \ + CONFIG.SATA_BOARD_INTERFACE {custom} \ + CONFIG.SD0_BOARD_INTERFACE {custom} \ + CONFIG.SD1_BOARD_INTERFACE {custom} \ + CONFIG.SPI0_BOARD_INTERFACE {custom} \ + CONFIG.SPI1_BOARD_INTERFACE {custom} \ + CONFIG.SUBPRESET1 {Custom} \ + CONFIG.SUBPRESET2 {Custom} \ + CONFIG.SWDT0_BOARD_INTERFACE {custom} \ + CONFIG.SWDT1_BOARD_INTERFACE {custom} \ + CONFIG.TRACE_BOARD_INTERFACE {custom} \ + CONFIG.TTC0_BOARD_INTERFACE {custom} \ + CONFIG.TTC1_BOARD_INTERFACE {custom} \ + CONFIG.TTC2_BOARD_INTERFACE {custom} \ + CONFIG.TTC3_BOARD_INTERFACE {custom} \ + CONFIG.UART0_BOARD_INTERFACE {custom} \ + CONFIG.UART1_BOARD_INTERFACE {custom} \ + CONFIG.USB0_BOARD_INTERFACE {custom} \ + CONFIG.USB1_BOARD_INTERFACE {custom} \ ] $zynq_ultra_ps_e_0 + set_property SELECTED_SIM_MODEL tlm $zynq_ultra_ps_e_0 + # Create instance: clk_wiz_0, and set properties set clk_wiz_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_wiz_0 ] set_property -dict [list \ + CONFIG.CLKOUT1_JITTER {115.833} \ + CONFIG.CLKOUT1_PHASE_ERROR {87.181} \ CONFIG.CLKOUT2_JITTER {102.087} \ CONFIG.CLKOUT2_PHASE_ERROR {87.181} \ CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {200.000} \ @@ -705,10 +1293,10 @@ Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD05000 # Create port connections connect_bd_net -net axi_intc_0_irq [get_bd_pins axi_intc_0/irq] [get_bd_pins zynq_ultra_ps_e_0/pl_ps_irq0] connect_bd_net -net clk_wiz_0_clk_out1 [get_bd_pins clk_wiz_0/clk_out1] [get_bd_pins proc_sys_reset_1/slowest_sync_clk] - connect_bd_net -net clk_wiz_0_clk_out2 [get_bd_pins clk_wiz_0/clk_out2] [get_bd_pins proc_sys_reset_2/slowest_sync_clk] [get_bd_pins ps8_0_axi_periph/ACLK] [get_bd_pins zynq_ultra_ps_e_0/maxihpm0_lpd_aclk] [get_bd_pins ps8_0_axi_periph/S00_ACLK] [get_bd_pins axi_intc_0/s_axi_aclk] [get_bd_pins ps8_0_axi_periph/M00_ACLK] + connect_bd_net -net clk_wiz_0_clk_out2 [get_bd_pins clk_wiz_0/clk_out2] [get_bd_pins axi_intc_0/s_axi_aclk] [get_bd_pins proc_sys_reset_2/slowest_sync_clk] [get_bd_pins ps8_0_axi_periph/ACLK] [get_bd_pins ps8_0_axi_periph/S00_ACLK] [get_bd_pins ps8_0_axi_periph/M00_ACLK] [get_bd_pins zynq_ultra_ps_e_0/maxihpm0_lpd_aclk] connect_bd_net -net clk_wiz_0_clk_out3 [get_bd_pins clk_wiz_0/clk_out3] [get_bd_pins proc_sys_reset_3/slowest_sync_clk] - connect_bd_net -net clk_wiz_0_locked [get_bd_pins clk_wiz_0/locked] [get_bd_pins proc_sys_reset_2/dcm_locked] [get_bd_pins proc_sys_reset_1/dcm_locked] [get_bd_pins proc_sys_reset_3/dcm_locked] - connect_bd_net -net proc_sys_reset_2_peripheral_aresetn [get_bd_pins proc_sys_reset_2/peripheral_aresetn] [get_bd_pins ps8_0_axi_periph/S00_ARESETN] [get_bd_pins axi_intc_0/s_axi_aresetn] [get_bd_pins ps8_0_axi_periph/M00_ARESETN] [get_bd_pins ps8_0_axi_periph/ARESETN] + connect_bd_net -net clk_wiz_0_locked [get_bd_pins clk_wiz_0/locked] [get_bd_pins proc_sys_reset_1/dcm_locked] [get_bd_pins proc_sys_reset_2/dcm_locked] [get_bd_pins proc_sys_reset_3/dcm_locked] + connect_bd_net -net proc_sys_reset_2_peripheral_aresetn [get_bd_pins proc_sys_reset_2/peripheral_aresetn] [get_bd_pins axi_intc_0/s_axi_aresetn] [get_bd_pins ps8_0_axi_periph/ARESETN] [get_bd_pins ps8_0_axi_periph/S00_ARESETN] [get_bd_pins ps8_0_axi_periph/M00_ARESETN] connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins zynq_ultra_ps_e_0/pl_clk0] [get_bd_pins clk_wiz_0/clk_in1] connect_bd_net -net zynq_ultra_ps_e_0_pl_resetn0 [get_bd_pins zynq_ultra_ps_e_0/pl_resetn0] [get_bd_pins clk_wiz_0/resetn] [get_bd_pins proc_sys_reset_1/ext_reset_in] [get_bd_pins proc_sys_reset_2/ext_reset_in] [get_bd_pins proc_sys_reset_3/ext_reset_in] @@ -720,13 +1308,13 @@ Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD05000 current_bd_instance $oldCurInst # Create PFM attributes + set_property PFM_NAME {xilinx:kv260:kv260_hardware_Platform:0.0} [get_files [current_bd_design].bd] set_property PFM.AXI_PORT {M_AXI_HPM0_FPD {memport "M_AXI_GP" sptag "" memory "" is_range "false"} M_AXI_HPM1_FPD {memport "M_AXI_GP" sptag "" memory "" is_range "false"} S_AXI_HPC0_FPD {memport "S_AXI_HP" sptag "HP2" memory "" is_range "false"} S_AXI_HPC1_FPD {memport "S_AXI_HP" sptag "HP3" memory "" is_range "false"} S_AXI_HP0_FPD {memport "S_AXI_HP" sptag "HPC0" memory "" is_range "false"} S_AXI_HP1_FPD {memport "S_AXI_HP" sptag "HPC1" memory "" is_range "false"} S_AXI_HP2_FPD {memport "S_AXI_HP" sptag "HP0" memory "" is_range "false"} S_AXI_HP3_FPD {memport "S_AXI_HP" sptag "HP1" memory "" is_range "false"}} [get_bd_cells /zynq_ultra_ps_e_0] set_property PFM.CLOCK {clk_out1 {id "0" is_default "false" proc_sys_reset "/proc_sys_reset_1" status "fixed" freq_hz "100000000"} clk_out2 {id "1" is_default "true" proc_sys_reset "/proc_sys_reset_2" status "fixed" freq_hz "200000000"} clk_out3 {id "2" is_default "false" proc_sys_reset "/proc_sys_reset_3" status "fixed" freq_hz "400000000"}} [get_bd_cells /clk_wiz_0] set_property PFM.IRQ {intr { id 0 range 32 }} [get_bd_cells /axi_intc_0] set_property PFM.AXI_PORT {M01_AXI {memport "M_AXI_GP" sptag "" memory "" is_range "false"} M02_AXI {memport "M_AXI_GP" sptag "" memory "" is_range "false"} M03_AXI {memport "M_AXI_GP" sptag "" memory "" is_range "false"} M04_AXI {memport "M_AXI_GP" sptag "" memory "" is_range "false"} M05_AXI {memport "M_AXI_GP" sptag "" memory "" is_range "false"} M06_AXI {memport "M_AXI_GP" sptag "" memory "" is_range "false"} M07_AXI {memport "M_AXI_GP" sptag "" memory "" is_range "false"}} [get_bd_cells /ps8_0_axi_periph] - validate_bd_design save_bd_design } # End of create_root_design() @@ -739,3 +1327,5 @@ Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD05000 create_root_design "" +common::send_gid_msg -ssname BD::TCL -id 2053 -severity "WARNING" "This Tcl script was generated from a block design that has not been validated. It is possible that design <$design_name> may result in errors during validation." + diff --git a/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/ref_files/step2_pfm/Makefile b/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/ref_files/step2_pfm/Makefile index 40bb9d3faf..189012530b 100644 --- a/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/ref_files/step2_pfm/Makefile +++ b/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/ref_files/step2_pfm/Makefile @@ -11,10 +11,10 @@ VERSION=2023.2 COMMON_IMAGE_ZYNQMP ?=${PLATFORM_REPO_PATHS}/sw/zynqmp/xilinx-zynqmp-common-v$(VERSION)/ DT_PLAT_NAME=mydeivice DT_PATH=$(ROOT_DIR)/$(DT_PLAT_NAME)/psu_cortexa53_0/device_tree_domain/bsp -BOOT=boot -SD_DIR=sd_dir +DTB =$(ROOT_DIR)/$(DT_PLAT_NAME)/psu_cortexa53_0/device_tree_domain/bsp/system.dtb + SYSROOT=sysroot -SW_COMP=sw_comp + .PHONY: help @@ -23,7 +23,7 @@ help: @echo "make all COMMON_IMAGE_ZYNQMP= ## Generate platform with pre-built software components" -all: check-common-image sw_comps dtb dtbo pfm_fsbl pfm sysroot +all: check-common-image dtb dtbo pfm sysroot #target : check whether the common image is ready check-common-image: @@ -33,41 +33,31 @@ ifeq ($(wildcard $(COMMON_IMAGE_ZYNQMP)/Image),) @echo "exit ....." && exit 1 endif -#target :software components -#copy software components to local directory -sw_comps:$(COMMON_IMAGE_ZYNQMP)/Image - @echo "create folder to store sw components and copy software components to local directory ./boot and ./sd_dir" - mkdir -p $(SW_COMP) && mkdir -p $(BOOT) && mkdir -p $(SD_DIR) - cp $(COMMON_IMAGE_ZYNQMP)/u-boot.elf $(BOOT)/ - cp $(COMMON_IMAGE_ZYNQMP)/bl31.elf $(BOOT)/ - cp $(COMMON_IMAGE_ZYNQMP)/boot.scr $(SD_DIR)/ - cp $(COMMON_IMAGE_ZYNQMP)/Image $(SW_COMP)/ - cp $(COMMON_IMAGE_ZYNQMP)/rootfs.ext4 $(SW_COMP)/ dtb: @echo "execute createdts to generate dtb file" xsct -eval " createdts -hw ../step1_vivado/build/vivado/$(XSA_NAME).xsa -zocl -platform-name $(DT_PLAT_NAME) -out . -git-branch xlnx_rel_v2023.1 -overlay -compile" - cp $(DT_PATH)/system.dtb $(BOOT)/ - cp $(DT_PATH)/system.dtb $(SD_DIR)/ dtbo:$(DT_PATH)/pl.dtsi dtc -@ -O dtb -o $(DT_PATH)/pl.dtbo $(DT_PATH)/pl.dtsi mkdir -p dtbo_output && cp $(DT_PATH)/pl.dtbo dtbo_output/ -pfm_fsbl: - @echo "INFO: Creating simple Platform $(PLATFORM_NAME_FSBL) to get FSBL and PMU" -#FSBL option is to convince XSCT to create a simple platform to get FSBL and PMU. - xsct xsct_create_pfm.tcl $(PLATFORM_NAME_FSBL) $(XSA_NAME) ../step1_vivado/build/vivado fsbl - @echo "INFO: Checking created platforms:" && find . -name "*.xpfm" #create platfrom pfm: - cp $(PLATFORM_NAME_FSBL)/zynqmp_fsbl/fsbl_a53.elf $(BOOT)/fsbl.elf - cp $(PLATFORM_NAME_FSBL)/zynqmp_pmufw/pmufw.elf $(BOOT)/ - @echo "INFO: Creating Final Platform $(PLATFORM_NAME)" - xsct xsct_create_pfm.tcl $(PLATFORM_NAME) $(XSA_NAME) ../step1_vivado/build/vivado + + @echo "INFO: Creating Platform $(PLATFORM_NAME)" + mkdir tmp -p && set %XILINX_VITIS_DATA_DIR%="tmp/" + vitis -s platform_creation.py --platform_name $(PLATFORM_NAME) --xsa_path ../step1_vivado/build/vivado/$(XSA_NAME).xsa --boot $(COMMON_IMAGE_ZYNQMP) --dtb $(DTB) @echo "INFO: Checking created platforms:" && find . -name "*.xpfm" +#install SDK tool +sysroot: $(SYSROOT) + +$(SYSROOT): $(COMMON_IMAGE_ZYNQMP)/sdk.sh + mkdir -p $(SYSROOT) && sh $(COMMON_IMAGE_ZYNQMP)/sdk.sh -d $(SYSROOT)/ -y + + #install SDK tool sysroot: $(SYSROOT) @@ -76,7 +66,7 @@ $(SYSROOT): $(COMMON_IMAGE_ZYNQMP)/sdk.sh mkdir -p $(SYSROOT) && sh $(COMMON_IMAGE_ZYNQMP)/sdk.sh -d $(SYSROOT)/ -y clean: - $(RM) -r IDE.log $(PLATFORM_NAME) $(PLATFORM_NAME_FSBL) device-tree-xlnx mydevice dt_output dtg boot sd_dir dtbo_output + $(RM) -r IDE.log $(PLATFORM_NAME) $(PLATFORM_NAME_FSBL) device-tree-xlnx mydevice dt_output dtg dtbo_output ultraclean: clean - $(RM) -r sw_comp sysroot + $(RM) -r sysroot diff --git a/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/ref_files/step2_pfm/platform_creation.py b/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/ref_files/step2_pfm/platform_creation.py new file mode 100644 index 0000000000..1318a6a029 --- /dev/null +++ b/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/ref_files/step2_pfm/platform_creation.py @@ -0,0 +1,33 @@ +#/* +#Copyright (C) 2023, Advanced Micro Devices, Inc. All rights reserved. +#SPDX-License-Identifier: X11 +#*/ + +# 2023-04-02T21:02:13.258137 +import vitis +import argparse +import os + +print("Platform generation") +parser = argparse.ArgumentParser() +parser.add_argument("--platform_name", type=str, dest="platform_name") +parser.add_argument("--xsa_path", type=str, dest="xsa_path") +parser.add_argument("--boot", type=str, dest="boot") +parser.add_argument("--dtb", type=str, dest="dtb") +args = parser.parse_args() +platform_name=args.platform_name +xsa_path=args.xsa_path +dtb=args.dtb +boot=args.boot +print('args',args) +client = vitis.create_client() +client.set_workspace(path=os.getcwd()) +platform = client.create_platform_component(name = platform_name, hw =xsa_path, os = "linux",cpu = "psu_cortexa53" ) +platform = client.get_platform_component(name=platform_name) +domain = platform.get_domain(name="linux_psu_cortexa53") +status = domain.update_name(new_name="xrt") +status = domain.generate_bif() +status = domain.add_boot_dir(path=boot) +status = domain.set_dtb(path=dtb) + +status = platform.build() diff --git a/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/ref_files/step2_pfm/xsct_create_pfm.tcl b/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/ref_files/step2_pfm/xsct_create_pfm.tcl deleted file mode 100644 index 4ada1d5324..0000000000 --- a/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/ref_files/step2_pfm/xsct_create_pfm.tcl +++ /dev/null @@ -1,53 +0,0 @@ -#/* -#Copyright (C) 2023, Advanced Micro Devices, Inc. All rights reserved. -#SPDX-License-Identifier: X11 -#*/ - - -set platform_name [lindex $argv 0] -puts "The platform name is \"$platform_name\"" -set xsa_name [lindex $argv 1] -puts "The xsa name is \"$xsa_name\"" -set xsa_path [lindex $argv 2] -puts "The xsa path is \"$xsa_path\"" -#set OUTPUT platform_repo -#we use setws command to specify the current directory as output directory. If you do not use ,you can set -out option. -setws . - -if { [string equal -nocase fsbl [lindex $argv 3]] } { - - puts "create a simple Platform to get FSBL and PMU" - platform create -name $platform_name \ - -desc "A custom platform ZCU104 platform" \ - -hw ${xsa_path}/${xsa_name}.xsa \ - -fsbl-target psu_cortexa53_0 -#-out ./${OUTPUT} - -# Standalone Domain - domain create -name standalone -proc psu_cortexa53_0 -os standalone -arch {64-bit} - platform write - platform generate -} else { - - puts "create final Vitis platform" - platform create -name $platform_name \ - -desc "A custom platform ZCU104 platform" \ - -hw ${xsa_path}/${xsa_name}.xsa \ - -no-boot-bsp -#-out ./${OUTPUT} - -# Linux domain - domain create -name xrt -proc psu_cortexa53 -os linux -arch {64-bit} -runtime {ocl} -sd-dir {./sd_dir} -bootmode {sd} - domain config -boot {./boot} - domain config -generate-bif - domain config -qemu-data ./boot - platform write - platform generate - -} - - exit - - - - diff --git a/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/ref_files/step3_validate/Makefile b/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/ref_files/step3_validate/Makefile index 96f183be93..c7c9f17397 100644 --- a/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/ref_files/step3_validate/Makefile +++ b/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/ref_files/step3_validate/Makefile @@ -8,7 +8,8 @@ PLATFORM_NAME=kv260_custom PLATFORM= $(ROOT_DIR)/../step2_pfm/$(PLATFORM_NAME)/export/$(PLATFORM_NAME)/$(PLATFORM_NAME).xpfm SW_COMP = $(ROOT_DIR)/../step2_pfm/sw_comp/ SYSROOTDIR=$(ROOT_DIR)/../step2_pfm/sysroot/ - +VERSION=2023.2 +COMMON_IMAGE_ZYNQMP ?=${PLATFORM_REPO_PATHS}/sw/zynqmp/xilinx-zynqmp-common-v$(VERSION)/ PL_EXAMPLE_PATH = Vitis_Accel_Examples/cpp_kernels/simple_vadd/ .PHONY: help @@ -29,11 +30,11 @@ Vitis_Accel_Examples: # Quick command for generating vadd hw xclbin vadd_hw: Vitis_Accel_Examples - $(MAKE) -C $(PL_EXAMPLE_PATH) all TARGET=hw PLATFORM=$(PLATFORM) HOST_ARCH=aarch64 DEV_ARCH=zynquplus EDGE_COMMON_SW=$(SW_COMP) SYSROOT=$(SYSROOTDIR)/sysroots/cortexa72-cortexa53-xilinx-linux + $(MAKE) -C $(PL_EXAMPLE_PATH) all TARGET=hw PLATFORM=$(PLATFORM) HOST_ARCH=aarch64 DEV_ARCH=zynquplus EDGE_COMMON_SW=$(COMMON_IMAGE_ZYNQMP) SYSROOT=$(SYSROOTDIR)/sysroots/cortexa72-cortexa53-xilinx-linux # vadd_hw generates the files for running on hardware. User needs to pick the files required by KV260, rename thr file and transfer them to the board # Do not use the generated sd_card.img $(PL_EXAMPLE_PATH)/simple_vadd: Vitis_Accel_Examples $(PLATFORM) - $(MAKE) -C $(PL_EXAMPLE_PATH) all TARGET=hw PLATFORM=$(PLATFORM) DEV_ARCH=zynquplus HOST_ARCH=aarch64 EDGE_COMMON_SW=$(SW_COMP) SYSROOT=$(SYSROOTDIR)/sysroots/cortexa72-cortexa53-xilinx-linux + $(MAKE) -C $(PL_EXAMPLE_PATH) all TARGET=hw PLATFORM=$(PLATFORM) DEV_ARCH=zynquplus HOST_ARCH=aarch64 EDGE_COMMON_SW=$(COMMON_IMAGE_ZYNQMP) SYSROOT=$(SYSROOTDIR)/sysroots/cortexa72-cortexa53-xilinx-linux $(PL_EXAMPLE_PATH)/shell.json: diff --git a/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/step1.md b/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/step1.md index 1df27d50fb..486e75ced8 100644 --- a/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/step1.md +++ b/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/step1.md @@ -1,6 +1,6 @@ - diff --git a/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/step2.md b/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/step2.md index 1285ab2297..966cac031b 100644 --- a/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/step2.md +++ b/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/step2.md @@ -1,6 +1,6 @@

2023.1 Vitis™ Platform Creation Tutorials

+

2023.2 Vitis™ Platform Creation Tutorials

See Vitis™ Development Environment on xilinx.com
- @@ -8,34 +8,32 @@ # Step 2: Create the Vitis Platform -In this step, you will create a Vitis platform running a Linux operation system. The Vitis platform requires several software components which need to be prepared in advance. Due to the boot flow differences between KV260 and base platforms for AMD evaluation boards like ZCU104, platform developer needs to prepare one additional DTBO file besides the normal software components for Vitis platforms because device tree file of programmalbe logic (PL) side depends on the hardware design and is loaded after Linux boots up. In addition, application developers need to add this DTBO file to the application deployment package as well. The other software components generation flow is similar to the flow described in the [ZCU104 tutorial](../02-Edge-AI-ZCU104/step2.md). However, in this case, the valuable software component is sysroot,which is used for host application cross-compilation. So you will go on utilizing the common image which provides the sysroot and expedite the process of platform creation. +In this step, you will create a Vitis platform running a Linux operation system. The Vitis platform requires several software components which need to be prepared in advance. Due to the boot flow differences between KV260 and base platforms for AMD evaluation boards like ZCU104, platform developer needs to prepare one additional DTBO file besides the normal software components for Vitis platforms because device tree file of programmable logic (PL) side depends on the hardware design and is loaded after Linux boots up. In addition, application developers need to add this DTBO file to the application deployment package as well. The other software components generation flow is similar to the flow described in the [ZCU104 tutorial](../02-Edge-AI-ZCU104/step2.md). However, in this case, the valuable software component is sysroot,which is used for host application cross-compilation. So you will go on utilizing the common image which provides the sysroot and expedite the process of platform creation. -## Prepare the Common Image +### Prepare the Common Image -1. Download common image from [Xilinx website download page.](https://www.xilinx.com/support/download.html). Go to the **WorkSpace** folder you created in step 1, and place the image package in **WorkSpace** folder similar to the following: +1. Download common image from [Xilinx website download page.](https://www.xilinx.com/support/download.html). Go to the **WorkSpace** folder you created in step 1, and place the image package in **WorkSpace** folder. ```bash cd WorkSpace tree -L 1 # to see the directory hierarchy ├── kv260_hardware_platform - └── xilinx-zynqmp-common-v2023.1.tar.gz + └── xilinx-zynqmp-common-v2023.2.tar.gz ``` 2. Extract the common image. - You will create one folder named **kv260_vitis_platform** to store the work content for this step 2. ```bash - mkdir kv260_vitis_platform - cd kv260_vitis_platform - tar xvf ../xilinx-zynqmp-common-v2023.1.tar.gz -C . + cd WorkSpace + tar xvf ../xilinx-zynqmp-common-v2023.2.tar.gz -C . ``` - You can see **xilinx-zynqmp-common-v2023.1** folder which contains the components located in **kv260_vitis_platform** folder similar to the following. + You can see **xilinx-zynqmp-common-v2023.2** folder which contains the components located in **WrokSpace** folder. ```bash tree -L 2 - ├── xilinx-zynqmp-common-v2023.1 + ├── xilinx-zynqmp-common-v2023.2 │   ├── bl31.elf │   ├── boot.scr │   ├── Image @@ -57,30 +55,30 @@ If you need to do system customization, take the following steps as reference. F Click for Detailed Steps -1. Check the [AMD Kria™ K26 SOM wiki](https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/1641152513/Kria+K26+SOM), and download the BSP package from the following link: +1. Check the [AMD Kria™ K26 SOM wiki](https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/1641152513/Kria+K26+SOM), and download the BSP package from the following link: - Save it to **WorkSpace** directory. + Save it to **WorkSpace** directory. 2. Set up the PetaLinux environment. ```bash cd WorkSpace - mkdir kv260_vitis_platform - cd kv260_vitis_platform + mkdir kv260_petalinux + cd kv260_petalinux source /settings.sh ``` 3. Update the PetaLinux eSDK to enable the recipes needed by the Starter Kit SOM BSP. ```bash - petalinux-upgrade -u 'http://petalinux.xilinx.com/sswreleases/rel-v2022/sdkupdate/' -p 'aarch64' + petalinux-upgrade -u 'http://petalinux.xilinx.com/sswreleases/rel-v2023/sdkupdate/' -p 'aarch64' ``` 4. Create PetaLinux with the Starter Kit SOM BSP, and the XSA export from step 1. ```bash - petalinux-create --type project -s xilinx-kv260-starterkit-v2023.1-final.bsp - cd xilinx-kv260-starterkit-2023.1 + petalinux-create --type project -s xilinx-kv260-starterkit-v2023.2-final.bsp + cd xilinx-kv260-starterkit-2023.2 petalinux-config --get-hw-description= --silent ``` @@ -121,10 +119,10 @@ If you need to do system customization, take the following steps as reference. F ```bash source /settings64.sh - cd kv260_vitis_platform + cd WrokSpace xsct - createdts -hw ../kv260_hardware_platform/kv260_hardware_platform.xsa -zocl -out . \ - -platform-name mydevice -git-branch xlnx_rel_v2023.1 -overlay -compile + createdts -hw kv260_hardware_platform/kv260_hardware_platform.xsa -zocl -out . \ + -platform-name mydevice -git-branch xlnx_rel_v2023.2 -overlay -compile ``` The `createdts` command has the following input values. Specify them as you need. @@ -146,7 +144,8 @@ If you need to do system customization, take the following steps as reference. F pl.dtsi:27.26-31.5: Warning (simple_bus_reg): /amba_pl@0/misc_clk_0: missing or empty reg/ranges property ``` - > **NOTE:** Createdts is a command executing in XSCT console to generate device files. This command needs several inputs to generate the device tree files. Regarding the meaning of every option, you can execute a help command to check the details. Besides XSCT is a Console tool of Vitis. You can start it by typing `xsct` in Linux terminal to start it. Or, you can select menu **Xilinx > XSCT Console** to start the XSCT tool after you launch Vitis. + > **NOTE:** The `createdts` command is used within the XSCT console to generate device tree files. This command requires several inputs to produce the desired device tree files. If you're unsure about the specific options and their meanings, you can execute a help command to access detailed information. Additionally, it's important to note that XSCT is a console tool integrated into Vitis. You can initiate it by typing `xsct` in the Linux terminal or, alternatively, select the **Xilinx > XSCT** Console option from the Vitis menu after launching the Vitis tool. + > **NOTE**: Device tree knowledge is a common know-how. Please refer to [AMD Device tree WIKI page](https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/862421121/Device+Trees) or [Device Tree WIKI page](https://en.wikipedia.org/wiki/Devicetree#Linux) for more information if you are not familiar with it. @@ -161,7 +160,7 @@ If you need to do system customization, take the following steps as reference. F Run the following command to build the dtsi file and create a directory to store the dtbo file. ```bash - cd kv260_vitis_platform + cd WrokSpace dtc -@ -O dtb -o mydevice/psu_cortexa53_0/device_tree_domain/bsp/pl.dtbo mydevice/psu_cortexa53_0/device_tree_domain/bsp/pl.dtsi mkdir dtg_output cp mydevice/psu_cortexa53_0/device_tree_domain/bsp/pl.dtbo dtg_output @@ -171,93 +170,67 @@ If you need to do system customization, take the following steps as reference. F ### Create the Vitis Platform -1. Then you create a `pfm` folder, plus `boot` and `sd_dir` inside the `pfm` folder to store all the necessary files for Vitis platform creation. The `boot` directory for boot components and `sd_dir` for FAT32 partition contents in SD card will give Vitis when creating the platform. - - ```bash - cd kv260_vitis_platform - mkdir pfm - mkdir pfm/boot - mkdir pfm/sd_dir - ``` - The following files are the content of `boot` directory and the sources of creating `BOOT.BIN` as well. They are required for the Vitis workflow, but because KV260 Starter Kit boot components are fixed in the QSPI flash, these files will not be used in our flow. So just leave it empty. +1. Install sysroot. - - `zynqmp_fsbl.elf`: MPSoC first stage boot loader - - `pmufw.elf`: MPSoC PMU Firmware - - `bl31.elf`: MPSoC Arm Trusted Firmware - - `u-boot.elf`: U-boot with device tree in the elf - - `system.dtb`: Device tree for Linux + - Go to `` directory. + - Type `./sdk.sh -d ` to install PetaLinux SDK. Use the `-d` option to provide a full pathname to the output directory. For example: `./sdk.sh -d .`. **.** means the current directory. + >**NOTE:** The environment variable **LD_LIBRARY_PATH** must not be set when running this command. - Contents in `sd_dir` directory will be packaged to FAT32 partition of `sd_card.img` by the v++ package tool. Usually, you will store `boot.scr` and `system.dtb` in this directory. Because the KV260 workflow does not program the SD card, you can skip adding contents to this directory. Leave it empty. -2. Install sysroot. + >Note: Sysroot is not mandatory components for the platform itself. It is the cross compile tool prepared for applications compilation. - - Go to `` directory. - - Type `./sdk.sh -d ` to install PetaLinux SDK. Use the `-d` option to provide a full pathname to the output directory **kv260_vitis_platform** (this is an example) and confirm. - >**NOTE:** The environment variable **LD_LIBRARY_PATH** must not be set when running this command. +2. Create a Vitis platform. - After this step, your WorkSpace directory hierarchy looks like the following. + For this example, you will use the Vitis Unifeid IDE to create the Vitis Platform. Got to `WorkSpace` directory and follow steps below to create the platform. - ```bash - - v260_hardware_platform # Vivado Project Directory - - kv260_vitis_platform # Software components and vitis platform directory - - xilinx-zynqmp-common-v2023.1 # common image directory - - device-tree-xlnx # device tree repo directory - - mydevice # device tree source file directory - - dtg_output # DTBO file directory - - sysroots # Extracted Sysroot Directory - - pfm # Platform Packaging Sources - - boot # boot components directory - - sd_dir # Files to be put in FAT32 partition of SD card - ``` + 1. Run Vitis by typing `vitis -w .` in the console. `-w` is to specify the workspace. `.` means the current workspace directory. + 2. In the Vitis Unified IDE, from menu select **File > New Component > Platform** to create a platform component. + 3. On the **Create Platform Component** setup dialog + - Enter the component name and location. For this example, type `kv260_custom` and use default location. Click **Next**. + - Click **Browse** button, select the XSA file generated by the Vivado. In this case, it is `kv260_hardware_platform.xsa`. + - Set the operating system to **linux**.
+ - Set the processor to **psu_cortexa53**.
+ - Check the option **Generate boot artifacts**. Then click **Next**.
+ >Note: Enabling this option will trigger the tool to automatically generate a PMU firmware domain and an FSBL (First Stage Boot Loader) domain into the platform + - Review the summary and click **Finish**. + >Note: After a few moments, the platform component will be prepared and available in the component view. Simultaneously, the platform configuration file, `vitis-comp.json`, will be automatically displayed in the main view. Users can access the `vitis-comp.json` file by expanding the Settings section under the platform component. -3. Create a Vitis platform. +3. Set up the software settings in the Platform configuration view by clicking the **Linux On psu_cortexa53** domain, browse to the locations and select the directory or file needed to complete the dialog box for the following: - First, create a Vitis platform project with the XSA file generated by Vivado from Step 1. + - **Display Name**: update it as `xrt` + - **Bif file**: Click the button to generate bif file or click **Browse** to select existing bif file. - 1. Launch the Vitis IDE. - - Go to the **kv260_vitis_platform** folder you created: + >**Note:** The filenames in `<>` are placeholders in the bif file. Vitis will replace the placeholders with the relative path to platform during platform packaging. V++ packager, which runs when building the final application#, would expand it further to the full path during image packaging. Filename placeholders point to the files in boot components directory. The filenames in boot directory need to match with placeholders in BIF file. `` is a reserved keyword. V++ packager will replace it with the final system bit file. - ```bash - cd - ``` + - **Pre-Built Image Directory**: Browse to **xilinx-zynqmp-common-v2023.2** and click **OK**. - - Launch Vitis by typing `vitis &` in the console. - - Select **kv260_vitis_platform** folder as workspace directory. + - **DTB File**: Browse to **mydevice/psu_cortexa53_0/device_tree_domain/bsp** and select system.dtb, then click **OK**. + >Note: If the directory you specified for Pre-build image directory already contains DTB file, this DTB field will be automatically updated. - 2. Create a new platform project. + - **FAT32 Partition Directory**: This directory is used to add additional file to the fat32 partition. User can set it according to your requirement. - - Select menu **File > New > Platform Project** to create a platform project. - - Enter the project name. For this example, type `kv260_custom`. Click **Next**. - - In the Platform page: - - Click **Browse** button, select the XSA file generated by the Vivado. In this case, it is `kv260_hardware_platform.xsa`. - - Set the operating system to **linux**. - - Set the processor to **psu_cortexa53**. - - Architecture: **64-bit** - - **Uncheck** option **Generate boot components** because we will use PetaLinux generated boot components. - - Click **Finish**. + - **QEMU Data**: This Directory is used to add additional file for emulation. User can set it accordingly. - 3. Setup software settings in Platform Settings view. + ![vitis_linux_config.PNG](./images/vitis_linux_config.png) - - Click the **linux on psu_cortexa53** domain, browse to the locations, and select the directory or file needed to complete the dialog box for the following: + >**Note:**: **Qemu Args File** and **Pmu Args File** are populated by the tool automatically. If there are additional QEMU settings, please update it accordingly. - - **Bif file**: Click the drop-down icon and select **Generate BIF**. +4. Select **kv260_custom** platform component in the flow navigator, then click the **Build** button to build the platform. - > **NOTE:** The file names in `<>` are placeholders. Vitis will replace the placeholders with the relative path to platform during platform packaging. V++ packager, which runs when building the final application would expand it further to the full path during image packaging. Filename placeholders point to the files in boot components directory. The filenames in boot directory need to match with placeholders in BIF file. `` is a reserved keyword. V++ packager will replace it with the final system bit file. + ![missing image](./images/build_vitis_platform.png) - - **Boot Components Directory**: Browse to **kv260_vitis_platform/pfm/boot** and click **OK**. + >**Note:** The generated platform is placed in the export directory. BSP and source files are also provided for rebuilding the FSBL, if required, and are associated with the platform. The platform is ready to be used for application development. - - **FAT32 Partition Directory**: Browse to **kv260_vitis_platform/pfm/sd_dir** and click **OK**. + ![missing image](./images/vitis_platform_output.png) - 4. Click **kv260_custom** project in the Vitis Explorer view, click the **Build** button to generate the platform. + >Note: Once the compilation is complete, users can find the XPFM file by expanding the Output directory, which offers a structured view of the output. The actual file path of platform file is located in the `WorkSapce/kv260_custom/export/kv260_custom/` directory. Additionally, users can access the full path of the platform file by hovering the mouse pointer over the XPFM file. - ![build_vitis_platform.png](./images/build_vitis_platform.png) + >Note: The Vitis Unified IDE will find the boot-related files mentioned in the software components in begin of this step from Pre-buit image directory and place them in the boot folder of the platform. - >**NOTE:** The generated platform is placed in the export directory. BSP and source files are also provided for re-building the FSBL and PMU, if desired, and are associated with the platform. The platform is ready to be used for application development. + If you create a Vitis application component in the same workspace as this platform component, you can find this platform available in the platform selection page in the application Creation wizard. If you want to reuse this platform in another workspace, add its path to the `PLATFORM_REPO_PATHS` environment variable before launching the Vitis GUI, or use the "Add" button on the platform selection page of the Vitis GUI to add its path. - ![vitis_platform_output.png](./images/vitis_platform_output.png) - If you would create an Vitis application in the same workspace as this platform, you can find this platform available in the platform selection page in platform creation wizard. If you want to reuse this platform in another workspace, add its path to PLATFORM_REPO_PATHS environment variable before launching Vitis GUI, or use the **Add** button in platform selection page of Vitis GUI to add its path. ### Next Step diff --git a/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/step3.md b/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/step3.md index 2e4af6d259..52c3ceb84a 100644 --- a/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/step3.md +++ b/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/step3.md @@ -1,6 +1,6 @@

2023.1 Vitis™ Platform Creation Tutorials

+

2023.2 Vitis™ Platform Creation Tutorials

See Vitis™ Development Environment on xilinx.com
- @@ -29,10 +29,8 @@ platforminfo ./kv260_custom/export/kv260_custom/kv260_custom.xpfm Basic Platform Information ========================== Platform: kv260_custom -File: Vitis-Tutorials/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/ref_files/step2_pfm/kv260_custom/export/kv260_custom/kv260_custom.xpfm +File: /Vitis-Tutorials/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/ref_files/step2_pfm/kv260_custom/export/kv260_custom/kv260_custom.xpfm Description: -A custom platform ZCU104 platform - ===================================== Hardware Platform (Shell) Information @@ -41,7 +39,7 @@ Vendor: xilinx Board: kv260_hardware_Platform Name: kv260_hardware_Platform Version: 0.0 -Generated Version: 2023.1 +Generated Version: 2023.2 Hardware: 1 Software Emulation: 1 Hardware Emulation: 1 @@ -80,28 +78,28 @@ Number of Runtimes: 1 Default System Configuration: kv260_custom System Configurations: System Config Name: kv260_custom - System Config Description: kv260_custom - System Config Default Processor Group: xrt + System Config Description: + System Config Default Processor Group: linux_psu_cortexa53 System Config Default Boot Image: standard System Config Is QEMU Supported: 1 System Config Processor Groups: - Processor Group Name: xrt + Processor Group Name: linux_psu_cortexa53 Processor Group CPU Type: cortex-a53 - Processor Group OS Name: linux + Processor Group OS Name: xrt System Config Boot Images: Boot Image Name: standard Boot Image Type: - Boot Image BIF: kv260_custom/boot/linux.bif - Boot Image Data: kv260_custom/xrt/image - Boot Image Boot Mode: sd + Boot Image BIF: boot/linux.bif + Boot Image Data: linux_psu_cortexa53/image + Boot Image Boot Mode: Boot Image RootFileSystem: - Boot Image Mount Path: /mnt - Boot Image Read Me: kv260_custom/boot/generic.readme - Boot Image QEMU Args: kv260_custom/qemu/pmu_args.txt:kv260_custom/qemu/qemu_args.txt + Boot Image Mount Path: + Boot Image Read Me: + Boot Image QEMU Args: qemu/pmu_args.txt:qemu/qemu_args.txt Boot Image QEMU Boot: Boot Image QEMU Dev Tree: Supported Runtimes: - Runtime: OpenCL + Runtime: C/C++ ``` @@ -110,35 +108,45 @@ You can verify clock information and memory information are set as expected. ### Test 2: Run Vector Addition Application -Vector addition is the simplest acceleration PL kernel. Vitis can create this application automatically. Running this test can check the AXI control bus, memory interface, and interrupt setting in platform are working properly. +Vector addition is the simplest acceleration PL kernel. Vitis Unified IDE can create this application automatically. Running this test can check the AXI control bus, memory interface, and interrupt setting in platform are working properly. 1. Create a Vector Addition Application. - - Go to workSpace, and create a application directory by typing `mkdir kv260_vitis_application`. Then, go to the application directory by typing `cd kv260_vitis_application` in the console. - - Launch Vitis by typing `vitis &` in the console. - - Select **File -> New -> Application Project**. - - Click **Next**. - - Select **kv260_custom** as platform, click **Next**. - - Name the project **vadd**, click **Next**. - - Set Domain to **linux on psu_cortexa53**. - - Set **Sys_root path** to ```/sysroots/cortexa72-cortexa53-xilinx-linux```(as you created by running **sdk.sh** in step 2). - - Click **Next**. - - Select **Acceleration templates with PL and AIE accelerators -> Vector Addition**, and click **Finish** to generate the application. - - In the Explorer window, double-click the **vadd.prj** file to open it, change the **Active Build configuration** from **Emulation-SW** to **Hardware**. - - Build the project. - - In the Explorer window, double-click **vadd_system_hw_link** to expand the directory hierarchy, then slect the **vadd_system_hw_link.prj**, and click **Build** icon in toolbar. - - In the Explorer window, double-click **vadd_kernels** to expand the directory hierarchy, then select the **vadd_kernels.prj**, and click **Build** icon in toolbar. - - The output is `binary_container_1.xclbin` located in **vadd_system_hw_link/Hardware/** directory. This binary file is the acceleration binary container for XRT configuration and includes `system.bit` and metadata that describes the kernels. - - In the Explorer window, double-click **vadd** to expand the directory hierarchy, then slect the **vadd.prj**, and click **Build** icon in toolbar. - - The output is `vadd` located in **vadd/Hardware/** directory. This file is the compiled host application. + - Go to `WorkSpace` directory created in step1 + - Run Vitis by typing `vitis -w .` in the console. `-w` is to specify the workspace. `.` means the current workspace directory. Close the welcome tab after Vitis launches. + - Go to example view by clicking the example button and click **Simple Vector Addition**. + ![example.PNG](./images/example.PNG) + - Click **Create Application from Template**. The project creation wizard would pop up. + - Input the **System project name** as `vadd` and use the default location for **System project location**. Then click **Next**. + - Select **kv260_custom** platform, click **Next**. + >Note: If the platform component is not in the current workspace user could click **+** button to add the platform component. + - Set **Sysroot** to ```xilinx-zynqmp-common-v2023.2/sysroots/cortexa72-cortexa53-xilinx-linux```. Then click **Next**. + - Review the summary of your `vadd` system project and click **Finish**. - > **NOTE:** In this step, you skip adding the image and rootfs and only compile the host application and binary file. As a result, you have to build host application and hw_link component separately. Because the Vitis V++ tool can not complete the packaging without the rootfs, Image ,and Boot components. + >**NOTE:** In this step, the addition of the kernel image and rootfs is omitted since it is recommended to use the official sd_card.img from AMD's download center. Furthermore, V++ does not incorporate the kernel image and rootfs in the generation of the sd_card.img for the SOM. - > **NOTE:** If you cannot see the **kv260_custom** platform we created, you can add it to platform list of New Project Wizard by selecting the add button, and point to **kv260_vitis_platform/kv260_custom** directory. + After seconds the vadd system project, vadd host component and vadd kernel component will be ready in the component view. + +2. Building Vector Addition Application - > **NOTE** KV260 Platform does not support emulation. + Vadd system project supports three targets: Software emulation, Hardware emulation and Hardware. User could select the target accordingly following steps below. As SOM has different development flow, we will only generate XCLBIN file and host application for hardware. -2. Prepare the files to be transferred to the board. + - Navigate to the Flow Navigator, select vadd system project, then expand the **LINK-binary_container_1** under **HARDWARE** target. + + ![build_application.PNG](./images/build_binary.PNG) + + - Click **Build Binary Container** + + >Note: Once the compilation is complete, users can find the `binary_container_1.xclbin` by expanding the Output directory, which offers a structured view of the output. The actual file path of `binary_container_1.xclbin` is located in the `WorkSpace/vadd/build/hw/hw_link/` directory. Additionally, users can access the full path of the `binary_container_1.xclbin` file by hovering the mouse pointer over the image file. + + + - Navigate to the Flow Navigator, select the vadd_host application component, and then click **Build** under the **HARDWARE** target.. + + ![build_application.PNG](./images/build_component.PNG) + + >Note: Once the compilation is complete, users can find the `vadd_host` executable file by expanding the Output directory, which offers a structured view of the output. The actual file path of `vadd_host` is located in the `WorkSpace/vadd_host/build/hw/` directory. Additionally, users can access the full path of the `vadd_host` file by hovering the mouse pointer over the image file. + +3. Prepare the files to be transferred to the board. The AMD Kria™ SOM uses `xmutil` to load applications dynamically. The load process includes downloading binary file and loading device tree overlay. `xmutil` requires the application files to be stored in `/lib/firmware/xilinx` directory. @@ -161,16 +169,16 @@ Vector addition is the simplest acceleration PL kernel. Vitis can create this ap } ``` -3. Transfer the files to the board. +4. Transfer the files to the board. Make sure the Ethernet cable of SOM Starter Kit is connected. Use SCP or SFTP to upload the files from host to target board. ```bash # Running on host machine - scp pl.dtbo binary_container_1.bin shell.json vadd petalinux@:/home/petalinux + scp pl.dtbo binary_container_1.bin shell.json vadd_host petalinux@:/home/petalinux ``` -4. Load the hardware. +5. Load the hardware. ```bash # Running on target board @@ -185,20 +193,17 @@ Vector addition is the simplest acceleration PL kernel. Vitis can create this ap If the application required files are loaded successfully, the following log is expected: ```bash - Nov 8 06:07:35 xilinx-kv260-starterkit-20231 kernel: OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga-full/firmware-name - Nov 8 06:07:35 xilinx-kv260-starterkit-20231 kernel: OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga-full/pid - Nov 8 06:07:35 xilinx-kv260-starterkit-20231 kernel: OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga-full/resets - Nov 8 06:07:35 xilinx-kv260-starterkit-20231 kernel: OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga-full/uid - Nov 8 06:07:35 xilinx-kv260-starterkit-20231 kernel: OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/overlay0 - Nov 8 06:07:35 xilinx-kv260-starterkit-20231 kernel: OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/overlay1 - Nov 8 06:07:35 xilinx-kv260-starterkit-20231 kernel: OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/afi0 - Nov 8 06:07:35 xilinx-kv260-starterkit-20231 kernel: OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/clocking0 - Nov 8 06:07:35 xilinx-kv260-starterkit-20231 kernel: OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/clocking1 - Nov 8 06:07:35 xilinx-kv260-starterkit-20231 kernel: OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/overlay2 - Nov 8 06:07:35 xilinx-kv260-starterkit-20231 kernel: OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/axi_intc_0 - Nov 8 06:07:35 xilinx-kv260-starterkit-20231 kernel: OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/misc_clk_0 - Nov 8 06:07:35 xilinx-kv260-starterkit-20231 kernel: irq-xilinx: mismatch in kind-of-intr param - Nov 8 06:07:35 xilinx-kv260-starterkit-20231 kernel: zocl-drm axi:zyxclmm_drm: error -ENXIO: IRQ index 32 not found + Nov 8 06:20:28 xilinx-kv260-starterkit-20232 kernel: OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga-full/firmware-name + Nov 8 06:20:28 xilinx-kv260-starterkit-20232 kernel: OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga-full/pid + Nov 8 06:20:28 xilinx-kv260-starterkit-20232 kernel: OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga-full/resets + Nov 8 06:20:28 xilinx-kv260-starterkit-20232 kernel: OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga-full/uid + Nov 8 06:20:28 xilinx-kv260-starterkit-20232 kernel: OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/afi0 + Nov 8 06:20:28 xilinx-kv260-starterkit-20232 kernel: OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/clocking0 + Nov 8 06:20:28 xilinx-kv260-starterkit-20232 kernel: OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/clocking1 + Nov 8 06:20:28 xilinx-kv260-starterkit-20232 kernel: OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/axi_intc_0 + Nov 8 06:20:28 xilinx-kv260-starterkit-20232 kernel: OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/misc_clk_0 + Nov 8 06:20:28 xilinx-kv260-starterkit-20232 kernel: irq-xilinx: mismatch in kind-of-intr param + Nov 8 06:20:28 xilinx-kv260-starterkit-20232 kernel: zocl-drm axi:zyxclmm_drm: error -ENXIO: IRQ index 32 not found vadd: loaded to slot 0 ``` @@ -207,14 +212,14 @@ Vector addition is the simplest acceleration PL kernel. Vitis can create this ap - Run vadd application. ```bash - chmod +x ./vadd - ./vadd binary_container_1.bin + chmod +x ./vadd_host + ./vadd_host binary_container_1.bin ``` - It should show program prints. ``` - xilinx-k26-starterkit-2021_1:~$ ./vadd binary_container_1.xclbin + xilinx-k26-starterkit-20232:~$ ./vadd_host binary_container_1.bin INFO: Reading binary_container_1.bin Loading: 'binary_container_1.bin' TEST PASSED @@ -235,7 +240,7 @@ If you encounter any issues when creating the custom platform and the validation The command line flow has slight differences comparing to Vitis IDE flow. -- The vector addition application is called `vadd` and `binary_container_1.xclbin` in Vitis IDE flow. The generated files in command line flow are called `simple_vadd` and `krnl_vadd.xclbin`. +- The vector addition application is called `vadd_host` and `binary_container_1.xclbin` in Vitis Unified IDE flow. The generated files in command line flow are called `simple_vadd` and `krnl_vadd.xclbin`. ### Next Steps

2023.1 Vitis™ Platform Creation Tutorials

+

2023.2 Vitis™ Platform Creation Tutorials

See Vitis™ Development Environment on xilinx.com