diff --git a/AI_Engine_Development/AIE-ML/AIE-ML.rst b/AI_Engine_Development/AIE-ML/AIE-ML.rst index cc484bfccc..553c7ef292 100644 --- a/AI_Engine_Development/AIE-ML/AIE-ML.rst +++ b/AI_Engine_Development/AIE-ML/AIE-ML.rst @@ -1,6 +1,6 @@ -####################################### -AI Engine Development -####################################### +############################################################################## +AI Engine for Machine Learning Development +############################################################################## .. sidebar:: More Information @@ -16,7 +16,7 @@ The tutorials under the AI Engine for Machine Learning (AIE-ML) Development help .. important:: - Before beginning a tutorial, ensure you have installed the Vitis 2023.2 software. The Vitis release includes all the embedded base platforms, including the VEK280 ES1 base platform that is used in these tutorials. In addition, ensure you have downloaded the Common Images for Embedded Vitis Platforms from `Downloads `_ . + Before beginning a tutorial, ensure you have installed the Vitis 2023.2 software. The Vitis release includes all the embedded base platforms, including the VEK280 ES1 base platform that is used in these tutorials. In addition, ensure you have downloaded the Common Images for Embedded Vitis Platforms from `Downloads `_. The `common image` package contains a prebuilt Linux kernel and root file system that can be used with the AMD Versal™ board for embedded design development using the Vitis software platform. @@ -29,7 +29,7 @@ Before starting a tutorial, run the following steps: -.. note:: +.. note:: These tutorials target VEK280 ES1 board or build custom board using ES devices, which are subject to a special license, please obtain a license for using Beta Devices in AMD tools, and make sure it's enabled by executing `enable_beta_device` (or add it to the tools initial ``.tcl`` files). @@ -47,7 +47,7 @@ These tutorials target the **VEK280 ES1** board. The table below lists the tutor :caption: Feature Tutorials :hidden: - Feature Tutorials <./docs/Feature_Tutorials/Feature_Tutorials> + Feature Tutorials <./Feature_Tutorials/Feature_Tutorials> .. csv-table:: Feature Tutorials :header: "Tutorial","Platform","OS","IDE Flow","Libraries Used","HLS Kernel","x86 simulator","aie simulator","SW Emu","HW Emu","HW","Event Trace in HW","Profile in HW" @@ -72,7 +72,7 @@ These tutorials target the **VEK280 ES1** board. The table below lists the tutor :caption: Design Tutorials :hidden: - Design Tutorials <./docs/Design_Tutorials/Design_Tutorials> + Design Tutorials <./Design_Tutorials/Design_Tutorials> diff --git a/AI_Engine_Development/AIE-ML/Design_Tutorials/01-AIE-ML-programming-and-optimization/AIEngineMLArchitecture.md b/AI_Engine_Development/AIE-ML/Design_Tutorials/01-AIE-ML-programming-and-optimization/AIEngineMLArchitecture.md index d8cf1ef7a8..a56f8ee91f 100755 --- a/AI_Engine_Development/AIE-ML/Design_Tutorials/01-AIE-ML-programming-and-optimization/AIEngineMLArchitecture.md +++ b/AI_Engine_Development/AIE-ML/Design_Tutorials/01-AIE-ML-programming-and-optimization/AIEngineMLArchitecture.md @@ -1,8 +1,8 @@ - + -

AI Engine Development

+

AIE-ML Development

See Vitis™ Development Environment on xilinx.com
 - See Vitis™ AI Development Environment on xilinx.com + See Vitis™ AI Development Environment on xilinx.com
diff --git a/AI_Engine_Development/AIE-ML/Design_Tutorials/01-AIE-ML-programming-and-optimization/ComputeOptimization.md b/AI_Engine_Development/AIE-ML/Design_Tutorials/01-AIE-ML-programming-and-optimization/ComputeOptimization.md index 7623a6fd46..ee4d2e4929 100644 --- a/AI_Engine_Development/AIE-ML/Design_Tutorials/01-AIE-ML-programming-and-optimization/ComputeOptimization.md +++ b/AI_Engine_Development/AIE-ML/Design_Tutorials/01-AIE-ML-programming-and-optimization/ComputeOptimization.md @@ -1,18 +1,18 @@ - + -

AI Engine Development

+

AIE-ML Development

See Vitis™ Development Environment on xilinx.com
 - See Vitis™ AI Development Environment on xilinx.com + See Vitis™ AI Development Environment on xilinx.com
# Compute Optimization -## _AI Engine-ML_ matrix multiplication Instruction Set +## AI Engine-ML matrix multiplication Instruction Set -The _AI Engine-ML_ has specific hardware instructions for matrix multiplications. Depending on the bitwidth of the operands, various matrix sizes are supported. In the following table the notation `MxKxN` means that matrix multiplication with a first operand of size M rows x K columns and a second operand of size K rows x N columns is supported. +The *AI Engine-ML* has specific hardware instructions for matrix multiplications. Depending on the bitwidth of the operands, various matrix sizes are supported. In the following table the notation `MxKxN` means that matrix multiplication with a first operand of size M rows x K columns and a second operand of size K rows x N columns is supported. **Matrix Multiplication modes for real types** @@ -80,11 +80,11 @@ In order to avoid too many pointer manipulations, the **A** tiles will be read 2 This way to do offloads the pointer manipulation to the DMA programming, freeing some scalar processor cycles. -The next 2 animated GIFs will show how **A** matrix is read from the Memory Tile and how **C** matrix is written to it. You can see that I chose to have __super tiles__ consisting of 2 sub-matrices one above the other: +The next 2 animated GIFs will show how **A** matrix is read from the Memory Tile and how **C** matrix is written to it. You can see that I chose to have **super tiles** consisting of 2 sub-matrices one above the other: -![Matrix **A** read order](images/OptA_Order.gif) +![Matrix A read order](images/OptA_Order.gif) -![Matrix **C** write order](images/OptC_Order.gif) +![Matrix C write order](images/OptC_Order.gif) These read write orders are obtained using the following tiling parameters: @@ -204,7 +204,7 @@ The 16-bit output version is doing a frog-leap in performances, **C** sub-matric Let's have a look to this code: -![Inner Loop as seen in `vitis_analyzer`](images/InnerLoopOpt16bits.png) +![Inner Loop as seen in vitis_analyzer](images/InnerLoopOpt16bits.png) Some lines (1568, 1584, ...) are not fully displayed in the interface, we need to get the original assembly code in the compilation directory (aie/Work1/aie/20_0/Release/20_0.lst). Let's focus on the inner loop delimited by the ZLS/ZLE flags (Zero Overhead Loop Start/End): diff --git a/AI_Engine_Development/AIE-ML/Design_Tutorials/01-AIE-ML-programming-and-optimization/FullAIEMLTable.md b/AI_Engine_Development/AIE-ML/Design_Tutorials/01-AIE-ML-programming-and-optimization/FullAIEMLTable.md index 52303cb486..c0354ed5a2 100755 --- a/AI_Engine_Development/AIE-ML/Design_Tutorials/01-AIE-ML-programming-and-optimization/FullAIEMLTable.md +++ b/AI_Engine_Development/AIE-ML/Design_Tutorials/01-AIE-ML-programming-and-optimization/FullAIEMLTable.md @@ -1,9 +1,8 @@ - -

AI Engine Development

+

AIE-ML Development

See Vitis™ Development Environment on xilinx.com
 - See Vitis™ AI Development Environment on xilinx.com + See Vitis™ AI Development Environment on xilinx.com
diff --git a/AI_Engine_Development/AIE-ML/Design_Tutorials/01-AIE-ML-programming-and-optimization/README.md b/AI_Engine_Development/AIE-ML/Design_Tutorials/01-AIE-ML-programming-and-optimization/README.md index a467c54bfa..56ff8370e5 100644 --- a/AI_Engine_Development/AIE-ML/Design_Tutorials/01-AIE-ML-programming-and-optimization/README.md +++ b/AI_Engine_Development/AIE-ML/Design_Tutorials/01-AIE-ML-programming-and-optimization/README.md @@ -1,9 +1,8 @@ - - +
-

AI Engine Development

+

AIE-ML Development

See Vitis™ Development Environment on xilinx.com
 - See Vitis™ AI Development Environment on xilinx.com + See Vitis™ AI Development Environment on xilinx.com
@@ -14,13 +13,13 @@ ## Introduction -Xilinx introduced the Versal™ AI Edge series, designed to enable AI innovation from the edge to the endpoint. This new series is mainly based on the AI Engine-ML that delivers 4X machine learning compute compared to previous AI Engine architecture and integrates new accelerator RAM with an enhanced memory hierarchy for evolving AI algorithms. +Xilinx introduced the Versal™ AI Edge series, designed to enable AI innovation from the edge to the endpoint. This new series is mainly based on the AI Engine-ML that delivers 4X machine learning compute compared to previous AI Engine architecture and integrates new accelerator RAM with an enhanced memory hierarchy for evolving AI algorithms. >**IMPORTANT**: Before beginning the tutorial make sure you have installed the Vitis 2023.2 software. The Vitis release includes all the embedded base platforms including the VEK280 base platform that is used in this tutorial. In addition, do ensure you have downloaded the Common Images for Embedded Vitis Platforms from this link [https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/embedded-platforms/2023-2.html](https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/embedded-platforms/2023-2.html) The ‘common image’ package contains a prebuilt Linux kernel and root file system that can be used with the Versal board for embedded design development using Vitis. Before starting this tutorial run the following steps: -1. Goto the directory where you have unzipped the Versal Common Image package +1. Go to the directory where you have unzipped the Versal Common Image package 2. In a Bash shell run the `/Common Images Dir/xilinx-versal-common-v2023.2/environment-setup-cortexa72-cortexa53-xilinx-linux` script. This script sets up the `SDKTARGETSYSROOT` and `CXX` variables. If the script is not present, you must run the `/Common Images Dir/xilinx-versal-common-v2023.2/sdk.sh`. 3. Set up your `ROOTFS`, and `IMAGE` to point to the `rootfs.ext4` and `Image` files located in the `/Common Images Dir/xilinx-versal-common-v2023.2` directory. 4. Set up your `PLATFORM_REPO_PATHS` environment variable to`$XILINX_VITIS/lin64/Vitis/2023.2/base_platforms` @@ -48,21 +47,23 @@ This tutorial is based on matrix multiplication which is a usual algorithm in Ma ## Prerequisite knowledge -To follow this tutorial you need to understand the architecture of the _AI Engine-ML_ as well as the art of buffer descriptor programming: +To follow this tutorial you need to understand the architecture of the *AI Engine-ML* as well as the art of buffer descriptor programming: - **AI Engine ML Architecture:**: [am020](https://docs.xilinx.com/r/en-US/am020-versal-aie-ml) - **Programming Buffer Descriptors with Tiling parameters:** [UG1603](https://docs.xilinx.com/r/en-US/ug1603-ai-engine-ml-kernel-coding) A short introduction to **AI Engine-ML** architecture is available [here](AIEngineMLArchitecture.md). -The various memory levels contains DMAs used to receive/transfer data to/from memory or Programmable Logic. These DMAs use Buffer Descriptors (BDs) that contains the parameters of these transfers. The best way to program these BDs is to use _Tiling Parameters_ that are introduced [here](TilingParametersProgramming.md). +The various memory levels contains DMAs used to receive/transfer data to/from memory or Programmable Logic. These DMAs use Buffer Descriptors (BDs) that contains the parameters of these transfers. The best way to program these BDs is to use *Tiling Parameters* that are introduced [here](TilingParametersProgramming.md). ## Matrix Multiplication Matrix multiplication is very common algorithm that can be found in numerous standard applications. The basic equation is: +``` $$ C = A.B $$ $$ \left( c_{ij} \right)_{\substack{0\leq i \lt M \\ 0 \leq j \lt N}} = \sum_{k=0}^{k DimAin = { ATILES_COLS_NS*ATILES_ROWS_NS, // Tile size A_ROWS*A_COLS/ATILES_COLS_NS/ATILES_ROWS_NS // Total number of Tiles @@ -220,7 +222,7 @@ std::vector DimBin = { The matrix multiplication kernel is very simple to write as the data have been reordered. Computing a block row of the output matrix requires to read multiple times the same block row of matrix **A** and the entire matrix **B**: -```C++ +```cpp template void ClassicMatMult(adf::input_buffer> & __restrict inA, adf::input_buffer> & __restrict inB, @@ -263,11 +265,11 @@ void ClassicMatMult(adf::input_buffer(SHIFT_RESULT); - pA -= NTilesPerCol_A; // Back to begining of row + pA -= NTilesPerCol_A; // Back to beginning of row // For matrix B the next tile is used } pA += NTilesPerCol_A; // Next Row - pB -= NTilesPerCol_B * NTilesPerRow_B; // Back to begining of matrix B + pB -= NTilesPerCol_B * NTilesPerRow_B; // Back to beginning of matrix B } } ``` @@ -328,18 +330,21 @@ Testbench creation is quite special as this tutorial is designed to evolve towar After an AIE or X86 simulation you can compare the simulation output with the reference output. This is done either with `make compareaie` or `make comparex86`. For sw_emu and hw_emu, the verification is done within the host code. -```BASH +```bash make clean-all OPT=0 data x86 x86sim comparex86 ``` + This will compile simulate and verify the result for the default size matrices using x86 simulation. -```BASH +```bash make sizeK=128 clean-all OPT=0 data x86 x86sim comparex86 ``` + Will do the same thing but with **A** matrices of size (64,128) and **B** matrices of size (128,64). AI Engine simulation can be conducted the same way: -```BASH + +```bash make clean-all OPT=0 data aie aiesim compareaie ``` @@ -349,7 +354,7 @@ Finally for hardware emulation `make OPT=0 all_hw_emu` will compile, link and cr After running AIE simulation with 64x64 matrices, we can look at the profiling results with: -```BASH +```bash make OPT=0 aieviz ``` @@ -373,7 +378,7 @@ We can see that the number of cycles to run the entire function is 2092 cycles. - number of multiplications to perform: 64 x 64 x 64 - number of parallel int8 x int8 multiplications in the SIMD vector processor: 256 -```TXT +```txt 64 x 64 x 64 Efficiency = ------------ = 0.49 2092 x 256 diff --git a/AI_Engine_Development/AIE-ML/Design_Tutorials/01-AIE-ML-programming-and-optimization/TilingParametersProgramming.md b/AI_Engine_Development/AIE-ML/Design_Tutorials/01-AIE-ML-programming-and-optimization/TilingParametersProgramming.md index c60748f83c..dddf29723e 100755 --- a/AI_Engine_Development/AIE-ML/Design_Tutorials/01-AIE-ML-programming-and-optimization/TilingParametersProgramming.md +++ b/AI_Engine_Development/AIE-ML/Design_Tutorials/01-AIE-ML-programming-and-optimization/TilingParametersProgramming.md @@ -1,8 +1,8 @@ - + -

AI Engine Development

+

AIE-ML Development

See Vitis™ Development Environment on xilinx.com
 - See Vitis™ AI Development Environment on xilinx.com + See Vitis™ AI Development Environment on xilinx.com
diff --git a/AI_Engine_Development/AIE-ML/Design_Tutorials/Design_Tutorials.rst b/AI_Engine_Development/AIE-ML/Design_Tutorials/Design_Tutorials.rst new file mode 100644 index 0000000000..0fd980eb3b --- /dev/null +++ b/AI_Engine_Development/AIE-ML/Design_Tutorials/Design_Tutorials.rst @@ -0,0 +1,35 @@ +############################################################################## +AIE-ML Development: Design Tutorials +############################################################################## + + +.. sidebar:: More Information + + See AMD Vitis™ Development Environment on `xilinx.com `_ + + + +The AI Engine Development Design Tutorials showcase the two major phases of AI Engine-ML application development: architecting the application and developing the kernels. Both phases are demonstrated in these tutorials. + + +.. toctree:: + :maxdepth: 3 + :caption: Design Tutorials + :hidden: + + Versal Custom Thin Platform Extensible System <./01-Versal_Custom_Thin_Platform_Extensible_System/README> + AIE-ML Programming <./01-AIE-ML-programming-and-optimization/README> + + +.. list-table:: + :widths: 20 80 + :header-rows: 1 + + * - Tutorial + - Description + + * - :doc:`Versal Custom Thin Platform Extensible System <./01-Versal_Custom_Thin_Platform_Extensible_System/README>` + - This is a Versal system example design based on a VEK280 thin custom platform (Minimal clocks and AXI exposed to PL) that includes HLS/RTL kernels and AI Engine kernel using a full Makefile build-flow. + + * - :doc:`LeNet Tutorial <./01-AIE-ML-programming-and-optimization/README>` + - This tutorial helps user understand the differences between AI Engine and AI Engine-ML architecture, it is based on matrix multiplication which is a usual algorithm in Machine Learning applications. diff --git a/AI_Engine_Development/AIE-ML/Design_Tutorials/README.md b/AI_Engine_Development/AIE-ML/Design_Tutorials/README.md index b9ae618f92..9e20b356d1 100644 --- a/AI_Engine_Development/AIE-ML/Design_Tutorials/README.md +++ b/AI_Engine_Development/AIE-ML/Design_Tutorials/README.md @@ -1,14 +1,14 @@ -

AIE-ML Development

- See Vitis™ Development Environment on xilinx.com
 +

AIE-ML Development

+ See AMD Vitis™ Development Environment on xilinx.com
## Design Tutorials -The AI Engine Development Design Tutorials showcase the two major phases of AI Engine-ML application development: architecting the application and developing the kernels. Both these phases are demonstrated in these tutorials. +The AI Engine Development Design Tutorials showcase the two major phases of AI Engine-ML application development: architecting the application and developing the kernels. Both phases are demonstrated in these tutorials. diff --git a/AI_Engine_Development/AIE-ML/Feature_Tutorials/Feature_Tutorials.rst b/AI_Engine_Development/AIE-ML/Feature_Tutorials/Feature_Tutorials.rst new file mode 100644 index 0000000000..a763b91c7f --- /dev/null +++ b/AI_Engine_Development/AIE-ML/Feature_Tutorials/Feature_Tutorials.rst @@ -0,0 +1,55 @@ +############################################################################## +AIE-ML Development: Feature Tutorials +############################################################################## + + +.. sidebar:: More Information + + See AMD Vitis™ Development Environment on `xilinx.com `_ + + + +The AIE-ML Development Feature Tutorials highlight specific features and flows that help develop AIE-ML applications. + + +.. toctree:: + :maxdepth: 3 + :caption: Feature Tutorials + :hidden: + + A to Z Bare-metal Flow <./01-aie_a_to_z/README> + Using GMIO with AIE-ML <./02-using-gmio/README> + Runtime Parameter Reconfiguration <./03-rtp-reconfiguration/README> + Packet Switching <./04-packet-switching/README> + Versal Integration for Hardware Emulation and Hardware <./05-AI-engine-versal-integration/README> + AIE Compiler Features <./20-aiecompiler-features/README> + + + + + +.. list-table:: + :widths: 20 80 + :header-rows: 1 + + * - Tutorial + - Description + + * - :doc:`A to Z Bare-metal Flow <./01-aie_a_to_z/README>` + - This tutorial walks through the steps to create a custom Baremetal platform, and also integrate Baremetal host application along with an AI Engines graph and PL kernels. + + * - :doc:`Using GMIO with AIE <./02-using-gmio/README>` + - This tutorial introduces the usage of global memory I/O (GMIO) for sharing data between the AI Engine-ML (AIE-ML) and external DDR. + + * - :doc:`Runtime Parameter Reconfiguration <./03-rtp-reconfiguration/README>` + - Learn how to dynamically update AI Engine-ML (AIE-ML) runtime parameters. + + * - :doc:`Packet Switching <./04-packet-switching/README>` + - This tutorial illustrates how to use data packet switching with AI Engine-ML (AIE-ML) designs to optimize efficiency. + + * - :doc:`AI Engine Versal Integration for Hardware Emulation and Hardware <./05-AI-engine-versal-integration/README>` + - This tutorial demonstrates creating a system design running on the AI Engine-ML (AIE-ML), PS, and PL and validating the design running on these heterogeneous domains by running Hardware Emulation. + + * - :doc:`AIE Compiler Features <./20-aiecompiler-features/README>` + - This tutorial shares a variety of features that are useful for AI Engine / AI Engine-ML (AIE-ML) programming to create more visible and efficient code compared to early versions of the compiler. + diff --git a/AI_Engine_Development/AIE-ML/Feature_Tutorials/README.md b/AI_Engine_Development/AIE-ML/Feature_Tutorials/README.md index 087dca6ce3..7cea00f13a 100755 --- a/AI_Engine_Development/AIE-ML/Feature_Tutorials/README.md +++ b/AI_Engine_Development/AIE-ML/Feature_Tutorials/README.md @@ -7,7 +7,8 @@
## Feature Tutorials -The AIE-ML Development Feature Tutorials highlight specific features and flows that help develop AIE-ML aplications. + +The AIE-ML Development Feature Tutorials highlight specific features and flows that help develop AIE-ML applications. @@ -20,11 +21,11 @@ The AIE-ML Development Feature Tutorials highlight specific features and flows t - + - + diff --git a/AI_Engine_Development/AIE-ML/README.md b/AI_Engine_Development/AIE-ML/README.md index 5d71326422..3a1e56a4f1 100644 --- a/AI_Engine_Development/AIE-ML/README.md +++ b/AI_Engine_Development/AIE-ML/README.md @@ -1,11 +1,13 @@
Using GMIO with AIE-MLThis tutorial introduces the usage of global memory I/O (GMIO) for sharing data between the AI Engine-ML (AIE-ML) and external DDRThis tutorial introduces the usage of global memory I/O (GMIO) for sharing data between the AI Engine-ML (AIE-ML) and external DDR.
Runtime Parameter ReconfigurationLearn how to dynamically update AI Engine-ML (AIE-ML) runtime parametersLearn how to dynamically update AI Engine-ML (AIE-ML) runtime parameters.
Packet Switching
-

AIE-ML Development

+

AIE-ML Development

See Vitis™ Development Environment on xilinx.com
+# AI Engine for Machine Learning (AIE-ML) Development + ## Introduction The tutorials under the AI Engine for Machine Learning (AIE-ML) Development help you learn how to target, develop, and deploy advanced algorithms using a Versal AIE-ML array in conjunction with PL IP/kernels and software applications running on the embedded processors. diff --git a/AI_Engine_Development/AIE/AIE.rst b/AI_Engine_Development/AIE/AIE.rst index 01c51b0754..43110fefba 100644 --- a/AI_Engine_Development/AIE/AIE.rst +++ b/AI_Engine_Development/AIE/AIE.rst @@ -10,8 +10,8 @@ AI Engine Development The tutorials under the AI Engine Development help you learn how to target, develop, and deploy advanced algorithms using a Versal AI Engine array in conjunction with PL IP/kernels and software applications running on the embedded processors. To successfully deploy AI Engine applications in hardware, you need to be aware of the Vitis and AI Engine tools and flows. -* :doc:`Feature Tutorials <./docs/Feature_Tutorials/Feature_Tutorials>` highlight specific features and flows that help develop AI Engine applications. -* :doc:`Design Tutorials <./docs/Design_Tutorials/Design_Tutorials>` showcase the two major phases of AI Engine application development: architecting the application and developing the kernels. Both phases are demonstrated in these tutorials. +* :doc:`Feature Tutorials <./Feature_Tutorials/Feature_Tutorials>` highlight specific features and flows that help develop AI Engine applications. +* :doc:`Design Tutorials <./Design_Tutorials/Design_Tutorials>` showcase the two major phases of AI Engine application development: architecting the application and developing the kernels. Both phases are demonstrated in these tutorials. Tutorials target the **VCK190** board. The table below lists the tutorials available, and the features and flows showcased in all of these tutorials. The various columns correspond to specific features/flows supported in these tutorials and will help you identify tutorials that showcase specific flows and features that you are interested in. @@ -71,11 +71,11 @@ Getting Started with AI Engine Development Using the AI Engine Tutorials -.. image:: ./docs/AI_Engine_dev_flow.png +.. image:: ./AI_Engine_dev_flow.png :alt: AI Engine Development Flow -If you are new with the AI Engine Architecture and tools, we recommend that you start with the :doc:`A to Z Bare-metal Flow <./docs/Feature_Tutorials/01-aie_a_to_z/README>`, which will guide you through the entire flow from platform creation in AMD Vivado™ to AI Engine application creation, system integration, and testing on Hardware using the Vitis IDE. +If you are new with the AI Engine Architecture and tools, we recommend that you start with the :doc:`A to Z Bare-metal Flow <./Feature_Tutorials/01-aie_a_to_z/README>`, which will guide you through the entire flow from platform creation in AMD Vivado™ to AI Engine application creation, system integration, and testing on Hardware using the Vitis IDE. AI Engine Application Development @@ -83,16 +83,16 @@ AI Engine Application Development To get started with AI Engine application development, we recommend that you look at the following tutorials: -* :doc:`DSP Library Tutorial <./docs/Feature_Tutorials/08-dsp-library/README>` which will guide you to create an AI Engine using application using the AMD provided DSP library -* :doc:`AIE DSPLib and Model Composer <./docs/Feature_Tutorials/10-aie-dsp-lib-model-composer/README>` which will also guide you to create an AI Engine using application using the AMD provided DSP library but using the ModelComposer tool which enables easy designs through a MATLAB Simulink environment. -* :doc:`Using GMIO with AIE <./docs/Feature_Tutorials/02-using-gmio/README>` which goes through using the GMIOs for connectivity between the AI Engine and the DDR (through the NoC) -* :doc:`Implementing an IIR Filter on the AIE <./docs/Feature_Tutorials/14-implementing-iir-filter/README>` will guide you into custom kernel coding using a IIR application +* :doc:`DSP Library Tutorial <./Feature_Tutorials/08-dsp-library/README>` which will guide you to create an AI Engine using application using the AMD provided DSP library +* :doc:`AIE DSPLib and Model Composer <./Feature_Tutorials/10-aie-dsp-lib-model-composer/README>` which will also guide you to create an AI Engine using application using the AMD provided DSP library but using the ModelComposer tool which enables easy designs through a MATLAB Simulink environment. +* :doc:`Using GMIO with AIE <./Feature_Tutorials/02-using-gmio/README>` which goes through using the GMIOs for connectivity between the AI Engine and the DDR (through the NoC) +* :doc:`Implementing an IIR Filter on the AIE <./Feature_Tutorials/14-implementing-iir-filter/README>` will guide you into custom kernel coding using a IIR application The following tutorials describe some features of the AI Engine, which might be useful for your application: -* :doc:`Runtime Parameter Reconfiguration <./docs/Feature_Tutorials/03-rtp-reconfiguration/README>` -* :doc:`Packet Switching <./docs/Feature_Tutorials/04-packet-switching/README>` -* :doc:`Using Floating-Point in the AIE <./docs/Feature_Tutorials/07-AI-Engine-Floating-Point/README>` +* :doc:`Runtime Parameter Reconfiguration <./Feature_Tutorials/03-rtp-reconfiguration/README>` +* :doc:`Packet Switching <./Feature_Tutorials/04-packet-switching/README>` +* :doc:`Using Floating-Point in the AIE <./Feature_Tutorials/07-AI-Engine-Floating-Point/README>` @@ -103,9 +103,9 @@ AI Engine Application Debug and Optimization After you have written your first AI Engine application you might want to verify the correct functionality of your graphs and kernels using x86 simulation and AI Engine simulation. In this regards, the following tutorials will be useful for you: -* :doc:`Debug Walkthrough Tutorial <./docs/Feature_Tutorials/09-debug-walkthrough/README>` will guide you to analyze the performance of your AI Engine application and help you with debugging functional issues. -* :doc:`AIE Performance and Deadlock Analysis <./docs/Feature_Tutorials/13-aie-performance-analysis/README>` which introduces you to performance analysis and optimization methods, and shows you how synchronization works in graph execution. -* :doc:`Python and C++ External Traffic Generators for AI Engine Simulation and Emulation Flows <./docs/Feature_Tutorials/16-external-traffic-generator-aie/README>`: This tutorial demonstrates how to create external traffic generators as Python scripts or C++ applications to exercise the AI Engine kernels in the x86 simulator, AI Engine simulator, and in hardware emulation. +* :doc:`Debug Walkthrough Tutorial <./Feature_Tutorials/09-debug-walkthrough/README>` will guide you to analyze the performance of your AI Engine application and help you with debugging functional issues. +* :doc:`AIE Performance and Deadlock Analysis <./Feature_Tutorials/13-aie-performance-analysis/README>` which introduces you to performance analysis and optimization methods, and shows you how synchronization works in graph execution. +* :doc:`Python and C++ External Traffic Generators for AI Engine Simulation and Emulation Flows <./Feature_Tutorials/16-external-traffic-generator-aie/README>`: This tutorial demonstrates how to create external traffic generators as Python scripts or C++ applications to exercise the AI Engine kernels in the x86 simulator, AI Engine simulator, and in hardware emulation. System Integration @@ -113,9 +113,9 @@ System Integration When your AI Engine Application meets your expectation (in terms of functionality and performances), it will be the right time to integrate it with the rest of the Versal System. At this stage, the following tutorials will be useful for you: -* :doc:`AIE Versal Integration <./docs/Feature_Tutorials/05-AI-engine-versal-integration/README>` demonstrates creating a system design running on the AI Engine, PS, and Programmable Logic (PL). -* :doc:`Versal System Design Clocking <./docs/Feature_Tutorials/06-versal-system-design-clocking-tutorial/README>` teaches clocking concepts for the Vitis compiler and how to define clocking for an ADF Graph, as well as PL kernels using clocking automation functionality. -* :doc:`Versal Emulation Waveform Analysis <./docs/Feature_Tutorials/11-ai-engine-emulation-waveform-analysis/README>` demonstrates how you can use the AMD Vivado Design Suite logic simulator (XSIM) waveform GUI, and the Vitis analyzer to debug and analyze your design. +* :doc:`AIE Versal Integration <./Feature_Tutorials/05-AI-engine-versal-integration/README>` demonstrates creating a system design running on the AI Engine, PS, and Programmable Logic (PL). +* :doc:`Versal System Design Clocking <./Feature_Tutorials/06-versal-system-design-clocking-tutorial/README>` teaches clocking concepts for the Vitis compiler and how to define clocking for an ADF Graph, as well as PL kernels using clocking automation functionality. +* :doc:`Versal Emulation Waveform Analysis <./Feature_Tutorials/11-ai-engine-emulation-waveform-analysis/README>` demonstrates how you can use the AMD Vivado Design Suite logic simulator (XSIM) waveform GUI, and the Vitis analyzer to debug and analyze your design. @@ -123,6 +123,9 @@ When your AI Engine Application meets your expectation (in terms of functionalit Available Tutorials ****************************************** + + + Feature Tutorials ============================================ @@ -135,40 +138,40 @@ These tutorials target the **VCK190** board. The table below lists the tutorials :caption: Feature Tutorials :hidden: - Feature Tutorials <./docs/Feature_Tutorials/Feature_Tutorials> + Feature Tutorials <./Feature_Tutorials/Feature_Tutorials> .. csv-table:: Feature Tutorials :header: "Tutorial","Platform","OS","IDE Flow","Libraries Used","HLS Kernel","x86 simulator","aie simulator","SW Emu","HW Emu","HW","Event Trace in HW","Profile in HW" :widths: 22, 8, 8, 6, 7, 8, 7, 7, 5, 6, 4, 6, 6 - ":doc:`AI Engine A-to-Z Flow for Linux <./docs/Feature_Tutorials/18-aie_a_to_z_custom_linux_platform/README>`","Base / Custom","Linux","","","MM2S / S2MM","Yes","Yes","Yes","Yes","Yes","","" - ":doc:`A to Z Bare-metal Flow <./docs/Feature_Tutorials/01-aie_a_to_z/README>`","Custom","Baremetal","Vivado, Vitis IDE","","MM2S / S2MM","","Yes","","Yes","Yes","","" - ":doc:`Using GMIO with AIE <./docs/Feature_Tutorials/02-using-gmio/README>`","Base","Linux","","","","","Yes","","Yes","Yes","","Yes" - ":doc:`Runtime Parameter Reconfiguration <./docs/Feature_Tutorials/03-rtp-reconfiguration/README>`","Base","Linux","","","MM2S / S2MM","","Yes","","Yes","Yes","","" - ":doc:`Packet Switching <./docs/Feature_Tutorials/04-packet-switching/README>`","Base","Linux","","","MM2S / S2MM","","Yes","","Yes","Yes","","" - ":doc:`AIE Versal Integration <./docs/Feature_Tutorials/05-AI-engine-versal-integration/README>`","Base","Linux","CLI, Vitis Unified IDE","","MM2S / S2MM","Yes","Yes","Yes","Yes","Yes","","" - ":doc:`Versal System Design Clocking <./docs/Feature_Tutorials/06-versal-system-design-clocking-tutorial/README>`","Base","Linux","","","MM2S / S2MM","","Yes","","Yes","Yes","","" - ":doc:`Using Floating-Point in the AIE <./docs/Feature_Tutorials/07-AI-Engine-Floating-Point/README>`","Base","Linux","","","","","Yes","","","","","" - ":doc:`DSP Library Tutorial <./docs/Feature_Tutorials/08-dsp-library/README>`","Base","Linux","","DSPLib","MM2S / S2MM Variant","","Yes","","","","","" - ":doc:`Debug Walkthrough Tutorial <./docs/Feature_Tutorials/09-debug-walkthrough/README>`","Base","Linux","Vitis IDE","","","Yes","Yes","Yes","Yes","Yes","Yes","Yes" - ":doc:`AIE DSPLib and Model Composer <./docs/Feature_Tutorials/10-aie-dsp-lib-model-composer/README>`","Base","Linux","Simulink","DSPLib","MM2S / S2MM","Yes","Yes","","","","","" - ":doc:`Versal Emulation Waveform Analysis <./docs/Feature_Tutorials/11-ai-engine-emulation-waveform-analysis/README>`","Base","Linux","","","Traffic Generators","","","","Yes","","","" - ":doc:`AXIS External Traffic Generator <./docs/Feature_Tutorials/12-axis-traffic-generator/README>`","Base","Linux","","DSPLib","MM2S / S2MM","","Yes","","Yes","","","" - ":doc:`AIE Performance and Deadlock Analysis <./docs/Feature_Tutorials/13-aie-performance-analysis/README>`","Base","Linux","","","","","Yes","","Yes","Yes","","Yes" - ":doc:`Implementing an IIR Filter on the AIE <./docs/Feature_Tutorials/14-implementing-iir-filter/README>`","Base","Linux","Vitis IDE","","","Yes","Yes","","","","","" - ":doc:`Post-Link Recompile of an AIE Application <./docs/Feature_Tutorials/15-post-link-recompile/README>`","Base","Linux","","","MM2S / S2MM","","Yes","","Yes","Yes","","" - ":doc:`Python and C++ External Traffic Generators for AI Engine Simulation and Emulation Flows <./docs/Feature_Tutorials/16-external-traffic-generator-aie/README>`","Base","Linux","","","MM2S / S2MM / PolarClip","Yes","Yes","Yes","Yes","","","" - ":doc:`Using RTL IP with AI Engines <./docs/Feature_Tutorials/17-RTL-IP-with-AIE-Engines/README>`","Custom","Linux","","","MM2S / S2MM","","Yes","","Yes","","","" - ":doc:`Using Verilog Traffic Generators in AIE Simulation <./docs/Feature_Tutorials/19-aie_external_io_sv/README>`","Base","Linux","Vivado","","","Yes","Yes","","","","","" - ":doc:`AIE Compiler Features <./docs/Feature_Tutorials/20-aiecompiler-features/README>`","Base","Linux","","","MM2S / S2MM","Yes","Yes","","Yes","Yes","Yes","Yes" + ":doc:`AI Engine A-to-Z Flow for Linux <./Feature_Tutorials/18-aie_a_to_z_custom_linux_platform/README>`","Base / Custom","Linux","","","MM2S / S2MM","Yes","Yes","Yes","Yes","Yes","","" + ":doc:`A to Z Bare-metal Flow <./Feature_Tutorials/01-aie_a_to_z/README>`","Custom","Baremetal","Vivado, Vitis IDE","","MM2S / S2MM","","Yes","","Yes","Yes","","" + ":doc:`Using GMIO with AIE <./Feature_Tutorials/02-using-gmio/README>`","Base","Linux","","","","","Yes","","Yes","Yes","","Yes" + ":doc:`Runtime Parameter Reconfiguration <./Feature_Tutorials/03-rtp-reconfiguration/README>`","Base","Linux","","","MM2S / S2MM","","Yes","","Yes","Yes","","" + ":doc:`Packet Switching <./Feature_Tutorials/04-packet-switching/README>`","Base","Linux","","","MM2S / S2MM","","Yes","","Yes","Yes","","" + ":doc:`AIE Versal Integration <./Feature_Tutorials/05-AI-engine-versal-integration/README>`","Base","Linux","CLI, Vitis Unified IDE","","MM2S / S2MM","Yes","Yes","Yes","Yes","Yes","","" + ":doc:`Versal System Design Clocking <./Feature_Tutorials/06-versal-system-design-clocking-tutorial/README>`","Base","Linux","","","MM2S / S2MM","","Yes","","Yes","Yes","","" + ":doc:`Using Floating-Point in the AIE <./Feature_Tutorials/07-AI-Engine-Floating-Point/README>`","Base","Linux","","","","","Yes","","","","","" + ":doc:`DSP Library Tutorial <./Feature_Tutorials/08-dsp-library/README>`","Base","Linux","","DSPLib","MM2S / S2MM Variant","","Yes","","","","","" + ":doc:`Debug Walkthrough Tutorial <./Feature_Tutorials/09-debug-walkthrough/README>`","Base","Linux","Vitis IDE","","","Yes","Yes","Yes","Yes","Yes","Yes","Yes" + ":doc:`AIE DSPLib and Model Composer <./Feature_Tutorials/10-aie-dsp-lib-model-composer/README>`","Base","Linux","Simulink","DSPLib","MM2S / S2MM","Yes","Yes","","","","","" + ":doc:`Versal Emulation Waveform Analysis <./Feature_Tutorials/11-ai-engine-emulation-waveform-analysis/README>`","Base","Linux","","","Traffic Generators","","","","Yes","","","" + ":doc:`AXIS External Traffic Generator <./Feature_Tutorials/12-axis-traffic-generator/README>`","Base","Linux","","DSPLib","MM2S / S2MM","","Yes","","Yes","","","" + ":doc:`AIE Performance and Deadlock Analysis <./Feature_Tutorials/13-aie-performance-analysis/README>`","Base","Linux","","","","","Yes","","Yes","Yes","","Yes" + ":doc:`Implementing an IIR Filter on the AIE <./Feature_Tutorials/14-implementing-iir-filter/README>`","Base","Linux","Vitis IDE","","","Yes","Yes","","","","","" + ":doc:`Post-Link Recompile of an AIE Application <./Feature_Tutorials/15-post-link-recompile/README>`","Base","Linux","","","MM2S / S2MM","","Yes","","Yes","Yes","","" + ":doc:`Python and C++ External Traffic Generators for AI Engine Simulation and Emulation Flows <./Feature_Tutorials/16-external-traffic-generator-aie/README>`","Base","Linux","","","MM2S / S2MM / PolarClip","Yes","Yes","Yes","Yes","","","" + ":doc:`Using RTL IP with AI Engines <./Feature_Tutorials/17-RTL-IP-with-AIE-Engines/README>`","Custom","Linux","","","MM2S / S2MM","","Yes","","Yes","","","" + ":doc:`Using Verilog Traffic Generators in AIE Simulation <./Feature_Tutorials/19-aie_external_io_sv/README>`","Base","Linux","Vivado","","","Yes","Yes","","","","","" + ":doc:`AIE Compiler Features <./Feature_Tutorials/20-aiecompiler-features/README>`","Base","Linux","","","MM2S / S2MM","Yes","Yes","","Yes","Yes","Yes","Yes" + -****************************************** Design Tutorials -****************************************** +============================================ These tutorials target the **VCK190** board. The table below lists the tutorials available, and the features and flows showcased in all of these tutorials. The various columns correspond to specific features/flows supported in these tutorials and will help you identify tutorials that showcase specific flows and features that you are interested in. @@ -178,7 +181,7 @@ These tutorials target the **VCK190** board. The table below lists the tutorials :caption: Design Tutorials :hidden: - Design Tutorials <./docs/Design_Tutorials/Design_Tutorials> + Design Tutorials <./Design_Tutorials/Design_Tutorials> @@ -186,15 +189,15 @@ These tutorials target the **VCK190** board. The table below lists the tutorials :header: "Tutorial","Platform","OS","IDE Flow","Libraries Used","HLS Kernel","x86 simulator","aie simulator","SW Emu","HW Emu","HW","Event Trace in HW","Profile in HW" :widths: 22, 8, 8, 6, 7, 8, 7, 7, 5, 6, 4, 6, 6 - ":doc:`Versal Custom Thin Platform Extensible System <./docs/Design_Tutorials/01-Versal_Custom_Thin_Platform_Extensible_System/README>`","Custom","Linux","","","MM2S / S2MM / VADD","","","","Yes","Yes","","" - ":doc:`LeNet Tutorial <./docs/Design_Tutorials/01-aie_lenet_tutorial/README>`","Base","Linux","","","MM2S / S2MM","","Yes","","Yes","Yes","","Yes" - ":doc:`Super Sampling Rate FIR Filters <./docs/Design_Tutorials/02-super_sampling_rate_fir/README>`","Base","Linux","","","","","Yes","","","","","" - ":doc:`Beamforming Design <./docs/Design_Tutorials/03-beamforming/README>`","Base","Linux","","","","","Yes","","Yes","Yes","","Yes" - ":doc:`Polyphase Channelizer <./docs/Design_Tutorials/04-Polyphase-Channelizer/README>`","Base","Linux","","","MM2S / S2MM","","","","Yes","Yes","","" - ":doc:`Prime Factor FFT <./docs/Design_Tutorials/05-Prime-Factor-FFT/README>`","Base","Linux","","","MM2S / S2MM","","","","Yes","Yes","","" - ":doc:`2D-FFT <./docs/Design_Tutorials/06-fft2d_AIEvsHLS/README>`","Base","Linux","","DSPLib","PL Data Generator and Checker","","Yes","","Yes","Yes","","Yes" - ":doc:`FIR Filter <./docs/Design_Tutorials/07-firFilter_AIEvsHLS/README>`","Base","Linux","","DSPLib","PL Data Generator and Checker","","Yes","","Yes","Yes","","Yes" - ":doc:`N-Body Simulator <./docs/Design_Tutorials/08-n-body-simulator/README>`","Base","Linux","","","PL Datamover","","Yes","","Yes","Yes","","" - ":doc:`Digital Down-conversion Chain <./docs/Design_Tutorials/09-ddc_chain/README>`","Base","Linux","","","","Yes","Yes","","","","","" - ":doc:`Versal GeMM Implementation <./docs/Design_Tutorials/10-GeMM_AIEvsDSP/README>`","Base","Linux","","DSPLib","Datamover","","Yes","","Yes","Yes","","Yes" - ":doc:`Bilinear Interpolation <./docs/Design_Tutorials/11-Bilinear_Interpolation/README>`","Base","Linux","","","","Yes","Yes","","","","","" + ":doc:`Versal Custom Thin Platform Extensible System <./Design_Tutorials/01-Versal_Custom_Thin_Platform_Extensible_System/README>`","Custom","Linux","","","MM2S / S2MM / VADD","","","","Yes","Yes","","" + ":doc:`LeNet Tutorial <./Design_Tutorials/01-aie_lenet_tutorial/README>`","Base","Linux","","","MM2S / S2MM","","Yes","","Yes","Yes","","Yes" + ":doc:`Super Sampling Rate FIR Filters <./Design_Tutorials/02-super_sampling_rate_fir/README>`","Base","Linux","","","","","Yes","","","","","" + ":doc:`Beamforming Design <./Design_Tutorials/03-beamforming/README>`","Base","Linux","","","","","Yes","","Yes","Yes","","Yes" + ":doc:`Polyphase Channelizer <./Design_Tutorials/04-Polyphase-Channelizer/README>`","Base","Linux","","","MM2S / S2MM","","","","Yes","Yes","","" + ":doc:`Prime Factor FFT <./Design_Tutorials/05-Prime-Factor-FFT/README>`","Base","Linux","","","MM2S / S2MM","","","","Yes","Yes","","" + ":doc:`2D-FFT <./Design_Tutorials/06-fft2d_AIEvsHLS/README>`","Base","Linux","","DSPLib","PL Data Generator and Checker","","Yes","","Yes","Yes","","Yes" + ":doc:`FIR Filter <./Design_Tutorials/07-firFilter_AIEvsHLS/README>`","Base","Linux","","DSPLib","PL Data Generator and Checker","","Yes","","Yes","Yes","","Yes" + ":doc:`N-Body Simulator <./Design_Tutorials/08-n-body-simulator/README>`","Base","Linux","","","PL Datamover","","Yes","","Yes","Yes","","" + ":doc:`Digital Down-conversion Chain <./Design_Tutorials/09-ddc_chain/README>`","Base","Linux","","","","Yes","Yes","","","","","" + ":doc:`Versal GeMM Implementation <./Design_Tutorials/10-GeMM_AIEvsDSP/README>`","Base","Linux","","DSPLib","Datamover","","Yes","","Yes","Yes","","Yes" + ":doc:`Bilinear Interpolation <./Design_Tutorials/11-Bilinear_Interpolation/README>`","Base","Linux","","","","Yes","Yes","","","","","" diff --git a/AI_Engine_Development/AIE/Design_Tutorials/Design_Tutorials.rst b/AI_Engine_Development/AIE/Design_Tutorials/Design_Tutorials.rst index 5c2624904e..91520754e7 100644 --- a/AI_Engine_Development/AIE/Design_Tutorials/Design_Tutorials.rst +++ b/AI_Engine_Development/AIE/Design_Tutorials/Design_Tutorials.rst @@ -25,8 +25,8 @@ The :doc:`landing page <../../AIE>` of AI Engine Development contains important LeNet Tutorial <./01-aie_lenet_tutorial/README> Super Sampling Rate FIR Filters <./02-super_sampling_rate_fir/README> Beamforming Design <./03-beamforming/README> - Polyphase Channelizer <./Design_Tutorials/04-Polyphase-Channelizer/README> - Prime Factor FFT <./Design_Tutorials/05-Prime-Factor-FFT/README> + Polyphase Channelizer <./04-Polyphase-Channelizer/README> + Prime Factor FFT <./05-Prime-Factor-FFT/README> 2D-FFT <./06-fft2d_AIEvsHLS/README> FIR Filter <./07-firFilter_AIEvsHLS/README> N-Body Simulator <./08-n-body-simulator/README> diff --git a/AI_Engine_Development/AIE/Feature_Tutorials/07-AI-Engine-Floating-Point/07-AI-Engine-Floating-Point-sourcelink.rst b/AI_Engine_Development/AIE/Feature_Tutorials/07-AI-Engine-Floating-Point/07-AI-Engine-Floating-Point-sourcelink.rst deleted file mode 100644 index 4427a5d841..0000000000 --- a/AI_Engine_Development/AIE/Feature_Tutorials/07-AI-Engine-Floating-Point/07-AI-Engine-Floating-Point-sourcelink.rst +++ /dev/null @@ -1,6 +0,0 @@ - -####################################################### -Version: Vitis 2023.1 -####################################################### - -To view the source files for this tutorial, click `here `_. diff --git a/AI_Engine_Development/AIE/Feature_Tutorials/07-AI-Engine-Floating-Point/README.md b/AI_Engine_Development/AIE/Feature_Tutorials/07-AI-Engine-Floating-Point/README.md index 547dc50c2c..63b35b0485 100644 --- a/AI_Engine_Development/AIE/Feature_Tutorials/07-AI-Engine-Floating-Point/README.md +++ b/AI_Engine_Development/AIE/Feature_Tutorials/07-AI-Engine-Floating-Point/README.md @@ -239,29 +239,31 @@ _vector_ **fpabs_mul**(_vector_ **xbuf**, _int_ **xstart**, _ ret[i] = abs(xbuf[xstart + xoffs[i]] * zbuf[zstart + zoffs[i]]) ``` - #### fpneg_mul +#### fpneg_mul - Signature is identical to `fpmul`: +Signature is identical to `fpmul`: - _vector_ **fpneg_mul**(_vector_ **xbuf**, _int_ **xstart**, _unsigned int_ **xoffs**, _vector_ **zbuf**, _int_ **zstart**, _unsigned int_ **zoffs**) +_vector_ **fpneg_mul**(_vector_ **xbuf**, _int_ **xstart**, _unsigned int_ **xoffs**, _vector_ **zbuf**, _int_ **zstart**, _unsigned int_ **zoffs**) - It returns the opposite value of the product: - ``` - for (i = 0 ; i < 8 ; i++) - ret[i] = - xbuf[xstart + xoffs[i]] * zbuf[zstart + zoffs[i]] - ``` +It returns the opposite value of the product: - #### fpneg_abs_mul +``` +for (i = 0 ; i < 8 ; i++) + ret[i] = - xbuf[xstart + xoffs[i]] * zbuf[zstart + zoffs[i]] +``` - Only for real arguments. Signature is identical to `fpmul`: +#### fpneg_abs_mul - _vector_ **fpneg_mul**(_vector_ **xbuf**, _int_ **xstart**, _unsigned int_ **xoffs**, _vector_ **zbuf**, _int_ **zstart**, _unsigned int_ **zoffs**) +Only for real arguments. Signature is identical to `fpmul`: - It returns the opposite value of the product: - ``` - for (i = 0 ; i < 8 ; i++) - ret[i] = - xbuf[xstart + xoffs[i]] * zbuf[zstart + zoffs[i]] - ``` +_vector_ **fpneg_mul**(_vector_ **xbuf**, _int_ **xstart**, _unsigned int_ **xoffs**, _vector_ **zbuf**, _int_ **zstart**, _unsigned int_ **zoffs**) + +It returns the opposite value of the product: + +``` +for (i = 0 ; i < 8 ; i++) + ret[i] = - xbuf[xstart + xoffs[i]] * zbuf[zstart + zoffs[i]] +``` #### fpmac, fpmsc, fpmac_abs, fpmsc_abs @@ -281,6 +283,7 @@ _vector_ **fpmac**(_vector_ **acc**, _vector_ **xbuf These functions are fully configurable `fpmul` and `fpmac` functions. The output can be considered to always have eight values because each part of the complex float is treated differently. A `vector` will have the loop interating over real0 - complex0 - real1 - complex1 ... This capability is introduced to allow flexibility and implement operations on conjugates. + _vector_ **fpmac_conf**(_vector_ **acc**, _vector_ **xbuf**, _int_ **xstart**, _unsigned int_ **xoffs**, _vector_ **zbuf**, _int_ **zstart**, _unsigned int_ **zoffs**, _bool_ **ones**, _bool_ **abs**, _unsigned int_ **addmode**, _unsigned int_ **addmask**, _unsigned int_ **cmpmode**, _unsigned int &_ **cmp**) Returns the multiplication result. @@ -378,14 +381,6 @@ In this design you learned: -## License - -___ - - The MIT License (MIT) - - Copyright (c) 2023 Advanced Micro Devices, Inc. All rights reserved. - SPDX-License-Identifier: MIT ## Support diff --git a/AI_Engine_Development/AIE/Feature_Tutorials/09-debug-walkthrough/AIE_Simulation/README.md b/AI_Engine_Development/AIE/Feature_Tutorials/09-debug-walkthrough/AIE_Simulation/README.md index f8409c8bcf..a9ae85c7a3 100644 --- a/AI_Engine_Development/AIE/Feature_Tutorials/09-debug-walkthrough/AIE_Simulation/README.md +++ b/AI_Engine_Development/AIE/Feature_Tutorials/09-debug-walkthrough/AIE_Simulation/README.md @@ -11,14 +11,14 @@ ## Introduction -The AI Engine simulator (aiesimulator) models the timing and resources of the AI Engine array, while using transaction-level SystemC models for the NoC and double-data rate (DDR) memory. This allows for faster performance analysis of your AI Engine applications and accurate estimation of the AI Engine resource use with cycle-approximate timing information. This takes into account the hardware constraints, such as heap/stack sizes and proram memory size for verifying the design and keeping track of those detailed timing information makes the simulation slow and resource intensive. +The AI Engine simulator (aiesimulator) models the timing and resources of the AI Engine array, while using transaction-level SystemC models for the NoC and double-data rate (DDR) memory. This allows for faster performance analysis of your AI Engine applications and accurate estimation of the AI Engine resource use with cycle-approximate timing information. This takes into account the hardware constraints, such as heap/stack sizes and proram memory size, for verifying the design and keeping track of those detailed timing information that makes the simulation slow and resource intensive. The AI Engine simulator allows stepping through the AI Engine compiler-generated assembly code which aids in code optimization; however, source level visibility could be limited due to compiler optimization. This section discusses about some important features (listed below) that ease the debugging of the design at AIE Simulation level. Before starting this tutorial: * It is expected that you have run the steps to set the environment variables as described in [Introduction](../README.md#Introduction). -* Create a system project manually using the steps mentioned in [Port the Command Line project to the Vitis IDE System Project](../CreateIDESystemProj.md), or download the Vitis exported project as instructed in [Download the Vitis IDE Project](../README.md#Download-Vitis-IDE-project). +* Create a system project manually using the steps mentioned in [Port the Command Line project to the Vitis IDE System Project](../CreateIDESystemProj.md), or download the AMD Vitis™ exported project as instructed in [Download the Vitis IDE Project](../README.md#Download-Vitis-IDE-project). * Open the Vitis IDE tool by typing `vitis` in the console, set the workspace, and the IDE opens. Click **File**->**Import**, select the **Vitis exported project zip file**, browse to the above zip file, and click `Next`. Enable the check box, **System Projects**, and click **Finish**. ## Features @@ -112,33 +112,23 @@ Shows how to calculate kernel latency and throughput using profile information. ## Build and Simulate in the Vitis IDE -1. From the left-side pane in the Vitis IDE, select the AI Engine Component and expand to locate and select the `aiecompiler.cfg` file to open the compiler configuration settings. -2. Select the **XLOpt** settings and under the **Kernel optimization** setting, select the **0 - None** from the drop-down. This gives greater visibility during the AI Engine debug. - - -![build setting](./Images/Build_setting.PNG) +1. From the left pane in the Vitis IDE, select the AI Engine Component, and expand to locate and select the `aiecompiler.cfg` file to open the compiler configuration settings. +2. Select the **XLOpt** settings and under the **Kernel optimization** setting, select the **0 - None** from the drop-down. This gives greater visibility during the AI Engine debug. + ![build setting](./Images/Build_setting.PNG) ![build target](./Images/Build_target.PNG) -2. Right-click the *[aiengine]* domain project, select **C/C++ Build Settings**, choose **Miscellaneous** -> **Optimization** -> from the drop down choose **No Optimizations(xlopt=0)**. This option helps IDE debugging capability by disabling any kernel optimizations. - -3. Now, in the **Flow** navigator window, select the **Build** option under **AIE SIMULATOR/HARDWARE**. This builds the AI Engine component for AIE Simulation target. Once the build completes, you see the **Compilation Complete** and **Build Finished Successfully** messages in the console. Also a green tick mark as highlighted below. - -![build output](./Images/build_output.PNG) - -4. In the **Flow** navigator window, under **AIE SIMULATION/HARDWARE**, select the **Run** option. If there is no existing launch configuration, you need to create one by clicking on **Create Configuration** -> **New Launch Configuration** -> **AIESim**. - -![Create_Configuration](./Images/create_configuration.PNG) - -5. You can change the Launch Config Name and click Run button to start simulation for AIE simulation target. When the simulation complete, you see the following output in the console. - +3. Right-click the *[aiengine]* domain project, select **C/C++ Build Settings**, choose **Miscellaneous** -> **Optimization** -> from the drop down choose **No Optimizations(xlopt=0)**. This option helps IDE debugging capability by disabling any kernel optimizations. +4. Now, in the **Flow** navigator window, select the **Build** option under **AIE SIMULATOR/HARDWARE**. This builds the AI Engine component for AIE Simulation target. Once the build completes, you see the **Compilation Complete** and **Build Finished Successfully** messages in the console and a green tick mark as highlighted below. + ![build output](./Images/build_output.PNG) +5. In the **Flow** navigator window, under **AIE SIMULATION/HARDWARE**, select the **Run** option. If there is no existing launch configuration, you need to create one by clicking **Create Configuration** -> **New Launch Configuration** -> **AIESim**. + ![Create_Configuration](./Images/create_configuration.PNG) +6. You can change the Launch Config Name, and click the **Run** button to start the simulation for the AIE simulation target. When the simulation completes, the following output in the console is displayed. ![aiesimulator_output](./Images/aiesimulator_output.PNG) - -6. Right-click the *[aiengine]* domain project, and select the **Run As → Launch AIE Emulator** option to start the simulation for the aiesimulation target. When the simulation completes, you see the following output in the console: +7. Right-click the *[aiengine]* domain project, and select the **Run As → Launch AIE Emulator** option to start the simulation for the aiesimulation target. When the simulation completes, the following output in the console is displayed: ![aie simulator output](./Images/aiesimulator_output.PNG) - -7. The aiesimulator output files from design are located at `${PROJECT}/Emulation-AIE/aiesimulator_output/data` and the golden output data is located at `09-debug-walkthrough/reference_output/`.Verify the output files `${PROJECT}/Emulation-AIE/aiesimulator_output/data/output_upscale.txt` and `${PROJECT}/Emulation-AIE/aiesimulator_output/data/output_data_shuffle.txt` against the golden files `09-debug-walkthrough/reference_output/upscale.txt` and `09-debug-walkthrough/reference_output/data_shuffle.txt` to ensure that the design's I/O functionalities are correct. The Vitis IDE supports compare with the feature to compare two files. - * Add the golden data to the `${PROJECT}/data/` by right clicking on the `data/` directory in *[aiengine]* domain project and select **Import sources**. +8. The aiesimulator output files from design are located at `${PROJECT}/Emulation-AIE/aiesimulator_output/data`, and the golden output data is located at `09-debug-walkthrough/reference_output/`. Verify the output files `${PROJECT}/Emulation-AIE/aiesimulator_output/data/output_upscale.txt` and `${PROJECT}/Emulation-AIE/aiesimulator_output/data/output_data_shuffle.txt` against the golden files `09-debug-walkthrough/reference_output/upscale.txt` and `09-debug-walkthrough/reference_output/data_shuffle.txt` to ensure that the design's I/O functionalities are correct. The Vitis IDE supports compare with the feature to compare two files. + * Add the golden data to the `${PROJECT}/data/` by right clicking the `data/` directory in the *[aiengine]* domain project, and select **Import sources**. * Highlight the two files to be compared. - * Right-click on one of highlighted files, and select **compare with** > **each other with transformation** . Click the **Predefined filters** icon(as shown below) > Enable **Remove timestamp** checkmark and click **OK** twice. Selecting **each other with transformation** is required because AI Engine simulation inserts a timestamp for each output data. For example, compare `${PROJECT}/data/golden_upscale.txt` and `${PROJECT}/Emulation-AIE/data/output_upscale.txt`. + * Right-click one of highlighted files, and select **compare with** > **each other with transformation**. Click the **Predefined filters** icon (as shown below). Enable the **Remove timestamp** checkmark, and click **OK** twice. Selecting **each other with transformation** is required because the AI Engine simulation inserts a timestamp for each output data. For example, compare `${PROJECT}/data/golden_upscale.txt` and `${PROJECT}/Emulation-AIE/data/output_upscale.txt`. ![predefined filter](./Images/predefined_filter.PNG). # Section 2 @@ -156,9 +146,8 @@ The simplest form of tracing is to use a formatted `printf()` statement in the c ``` >**NOTE:** Adding `printf()` statements to your AI Engine kernel code will increase the compiled size of the AI Engine program. Be careful that the compiled size of your kernel code does not exceed the per-AI Engine processor memory limit of 16 KB. - 2. Rebuild the *AI Engine* component. -3. To enable the `printf()` function, it is required to enable **profile** option in launch configuration settings. To do this, hover your mouse over the **Run** option in the **Flow** navigator and click on the settings button. Now, in the launch configuration window, tick the **Enable Profile** option under **Profile Options** as shown below. +3. To enable the `printf()` function, it is required to enable **profile** option in the launch configuration settings. To do this, hover your mouse over the **Run** option in the **Flow** navigator, and click the settings button. Now, in the launch configuration window, tick the **Enable Profile** option under **Profile Options** as follows. ![enable_profile](./Images/enable_profile.PNG) 4. Observe the following `print` statements in the console: @@ -179,7 +168,7 @@ The simplest form of tracing is to use a formatted `printf()` statement in the c Iteration-1 -> Vector-2 -> value = 6.283000 ``` -6. Revert the changes in the source file to exercise other debug features. +5. Revert the changes in the source file to exercise other debug features. # Section 3 @@ -187,46 +176,41 @@ The simplest form of tracing is to use a formatted `printf()` statement in the c This section walks you through a debug methodology that uses the Vitis IDE debugger. You can learn how to invoke the debugger, add breakpoints, view intermediate values, etc. -1. After the design is built for the aiesimulation target, click on **Flow** Navigator -> **AIE Simulation** -> **Debug** option.. -2. This gets you to the debug mode in the Vitis IDE and waits in `io_buffer_main.h` waiting to acquire the lock to read the input data. -3. Open the source file, `peak_detect.cc`, and place the breakpoint at line (vin = \*InIter++) by clicking on the empty space beside the line number in the source editor. +1. After the design is built for the aiesimulation target, click the **Flow Navigator -> **AIE Simulation** -> **Debug** option.. +2. This gets you to the debug mode in the Vitis IDE and waits in `io_buffer_main.h` to acquire the lock to read the input data. +3. Open the source file, `peak_detect.cc`, and place the breakpoint at line (vin = \*InIter++) by clicking the empty space beside the line number in the source editor. >**NOTE:** > >1. You should see the stack trace corresponding to the all the kernel functions mapped to a particular tile. For example, in this case, the kernel `peak_detect` mapped to the tile [25,0]. So, when you select the `core[25,0]` in the `Debug` window, then the **CALL STACK** shows only the trace information correspoinding to the `core[25,0]`. - >2. Not all the lines in the source code are allowed for placing the break-point. Sometimes when you try to place the breakpoint at a particular line (for example, line 27 as shown in below screenshot, the breakpoint is adjusted to the line-32 in the same source code with **Info** message at the bottom corner as highlighted below. This is because the compiler optimized the particular operation, and the breakponts can only be placed at lines that are not optimized by the compiler. + >2. Not all the lines in the source code are allowed for placing the breakpoint. Sometimes when you try to place the breakpoint at a particular line (for example, line 27 as shown in below screenshot), the breakpoint is adjusted to the line 32 in the same source code with an **Info** message at the bottom corner as highlighted below. This is because the compiler optimized the particular operation, and the breakponts can only be placed at lines that are not optimized by the compiler. > > ![breakpoint placement](./Images/breakpoint_placement.PNG) > - >* `1` -> Indicates the current location of the pointer during the debug (explained more in later steps). - >* `2` -> Try adding a breakpoint at a line that is optimized by compiler. - >* `3` -> Breakpoint automatically shifted to the other line which can be used to debug. Note the info message. - > + >* `1`: Indicates the current location of the pointer during the debug (explained more in later steps). + >* `2`: Try adding a breakpoint at a line that is optimized by the compiler. + >* `3`: Breakpoints automatically shifted to the other line which can be used to debug. Note the info message. -4. Notice the `continue`,`pause`,`step-over`,`step-into`,`step-out`, `restart` and `terminate` options in the taskbar after entering debug mode. -5. You should be able to view the variables, breakpoints, watchpoints to analyze the design at each iteration during the debug session. -![debug analysis view](./Images/debug_analysis_view.PNG) +4. Notice the `continue`,`pause`,`step-over`,`step-into`,`step-out`, `restart`, and `terminate` options in the taskbar after entering debug mode. +5. You should be able to view the variables, breakpoints, and watchpoints to analyze the design at each iteration during the debug session. -6. After placing the breakpoint in `peak_detect.cc`, click the **continue** button. You can see the debugger stops at that particular line. From the variable view you can get the address of any particular variable at that particular instance of the run. For example, the address value of the `InIter` is `0x38000`. + ![debug analysis view](./Images/debug_analysis_view.PNG) +6. After placing the breakpoint in `peak_detect.cc`, click the **continue** button. You can see the debugger stops at that particular line. From the variable view, you can get the address of any particular variable at that particular instance of the run. For example, the address value of the `InIter` is `0x38000`. ![address of variable](./Images/address_of_variable.PNG) -7. Use the **Memory** Inspector option to get the values at the address location, `0x38000`. Click the **+** button, and add the address `0x38000` to the memory monitor. You should see the values equal to the input values in `data/inx.txt`. - +7. Use the **Memory** Inspector option to get the values at the address location, `0x38000`. Click the **+** button, and add the address `0x38000` to the memory monitor. You should see the values equal to the input values in `data/inx.txt`. ![memory_view](./Images/memory_view.PNG) 8. Also, based on the location of breakpoint, you should be able to see the similar values in the **variable** view. If that variable is not visible in a particular iteration (due to compiler optimizations), you should still be able to track the value by adding in **Expressions**. - -8. Select the `+` option in `Watch` window to **Add new expression**, and type `vin`. You should see the initial zeros which matches with the values you see in the memory inspector. In each iteration, 16 values of 4-bytes (int32) are sent as an input in one iteration. - +9. Select the `+` option in `Watch` window to **Add new expression**, and type `vin`. You should see the initial zeroes which matches with the values you see in the memory inspector. In each iteration, 16 values of 4-bytes (int32) are sent as an input in one iteration. ![Add expression](./Images/add_expression.PNG) +10. Now, click the continue button again, and you should see the following next set of 16 values in the `vin`. -9. Now, click the continue button again, and you should see the following next set of 16 values in the `vin`. - -10. Get the memory address of `OutIter_1`, and validate the values. As the `OutIter_1` is just a passthrough operation from the input to the output, you should see the same values as in `InIter`. +11. Get the memory address of `OutIter_1`, and validate the values. As the `OutIter_1` is just a passthrough operation from the input to the output, you should see the same values as in `InIter`. ### Limitations -1. There are maximum four breakpoints available for each tile. Program under debug is stopped at first line of `main()`. This does not impact those available breakpoints. +1. There are a maximum of four breakpoints available for each tile. Program under debug is stopped at first line of `main()`. This does not impact those available breakpoints. 2. Expect a non-sequential execution when stepping through the source code. 3. Due to compiler optimization, some variable values are stored in registers. `N/A` is shown in **variables** view for those optimized variables values. @@ -234,30 +218,24 @@ This section walks you through a debug methodology that uses the Vitis IDE debug ## Enabling Profile and Trace Options -This section walks you through a flow to enable profiling and trace in the Vitis IDE. Using this, you should be able to get performance metrics and generate trace data which can be visualized in the Vitis Analyzer. - -1. In the Flow navigator window, under AIE SIMULATION/HARDWARE, select the Run Settings. -2. Under **aie_component_aiesim_1** Configuration, select the check box **Generate Trace**, Trace Tyep **VCD** and leave the default option **VCD** with the filename *foo*. -3. Under Profile Options tab, enable the **Generate Profile** check box, and leave the other default options under that. +This section walks you through a flow to enable profiling and trace in the Vitis IDE. Using this, you should be able to get performance metrics, and generate trace data which can be visualized in the Vitis Analyzer. - >**NOTE:** You can also try enablling profile generation for selected tiles. +1. In the Flow navigator window, under AIE SIMULATION/HARDWARE, select **Run Settings**. +2. Under **aie_component_aiesim_1** Configuration, select the **Generate Trace** check box, Trace Tyep **VCD**, and leave the default option **VCD** with the filename *foo*. +3. Under the Profile Options tab, enable the **Generate Profile** check box, and leave the other default options under that. + >**NOTE:** You can also try enablling profile generation for the selected tiles. >![profile trace run config](./Images/Profie_trace_runconfig.PNG) - - In the Flow navigator window, under AIE SIMULATION/HARDWARE, select the Run option to launch the aiesimulation. -4. Once the Run completes, In the Flow navigator window, under AIE SIMULATION/HARDWARE select **Reports** -> **trace**. This opens the following Vitis Analyzer window. + In the Flow navigator window, under AIE SIMULATION/HARDWARE, select the **Run** option to launch the aiesimulation. +4. Once the run completes, in the Flow navigator window, under AIE SIMULATION/HARDWARE, select **Reports** -> **trace**. This opens the following Vitis Analyzer window. ![profile trace in vitis analyzer](./Images/profile_trace_va.PNG) - -5. Click the **Profile** -> select the **Summary** and **Profile Details** corresponding to all the tiles ([24,0],[25,0],[25,1]), and observe the cycle count, instruction count, and program memory size. More information about the profile details is explained in the [Design Performance Debug](./README.md#Design-performance-debug) section. - +5. Click the **Profile** ->, select the **Summary** and **Profile Details** corresponding to all the tiles ([24,0],[25,0],[25,1]), and observe the cycle count, instruction count, and program memory size. More information about the profile details is explained in the [Design Performance Debug](./README.md#Design-performance-debug) section. 6. Click **Trace**, and observe the trace events corresponding to all the tiles. For example, select the core `[25,0]` corresponding to the kernel `peak_detect`. Expand the kernel function and zoom in to check the input and output values. ![trace kernel io](./Images/trace_kernel_io.PNG) - >**NOTE:** If the VCD file generated during AI Engine simulation is too large, it takes too much time for the Vitis Analyzer to analyze the VCD and open the trace view. Alternatively, you can do an online analysis of the VCD when running the AI Engine simulator using the WDB and CTF files. To generate this, you need to choose **Online** option instead of **VCD** in step 2. ### Exercise Step -Under **aie_component_aiesim_1** Configuration, select the check box **Generate Trace**, Trace Tyep **Online Wdb** and open the event trace in the Analysis View -> aie_component -> Run-aie_component -> trace. - +Under **aie_component_aiesim_1** Configuration, select the check box **Generate Trace**, Trace Type **Online Wdb**, and open the event trace in the **Analysis View -> aie_component -> Run-aie_component -> trace**. ![argument wbd](./Images/argument_wdb.PNG) # Section 5 @@ -266,27 +244,27 @@ Under **aie_component_aiesim_1** Configuration, select the check box **Generate AI Engine designs can run into simulator hangs. A common cause is insufficient input data for the requested number of graph iterations, a mismatch between production and consumption of stream data, cyclic dependency with stream, cascade stream or asynchronous buffers, or the wrong order of blocking protocol calls (acquisition of async buffers, read/write from streams). -This topic walks you through the practical scenario of deadlock during aiesimulation and different the simulator options that helps debugging. +This topic walks you through the practical scenario of deadlock during aiesimulation and the different the simulator options that help debugging. -1. Open the `src/kernels/data_shuffle.cc`, and comment out the line 24. +1. Open the `src/kernels/data_shuffle.cc`, and comment out line 24. 2. Compile the design by rebuilding the *[aie_component]* under AIE SIMULATOR/HARDWARE. -3. Run the aiesimulation by ** AIE SIMULATOR/HARDWARE ** → **Run**, and observe the hang. -4. You can wait for few seconds to confirm the hang, and click the icon located in bottom right corner that shows background operations in progress view and the kill the simulation process. +3. Run the aiesimulation by selecting **AIE SIMULATOR/HARDWARE** → **Run**, and observe the hang. +4. You can wait for few seconds to confirm the hang, and click the icon located in the bottom right corner that shows the background operations in progress view, and the kill the simulation process. ![simulation hang](./Images/simulation_hang.PNG) -5. The AI Engine simulator provides an option to exit the simulation if all active cores in stalled state after the time period (in ns). +5. The AI Engine simulator provides an option to exit the simulation if all active cores in the stalled state after the time period (in ns). 6. For example, add `--hang-detect-time=60` in the **Run configurations** -> **Additional Arguments**, and rerun the aiesimulation. You can observe the simulation exits smoothly with the following information in the console. - ``` - Enabling core(s) of graph mygraph - WARNING: All the cores are in stalled state at T=636000.000000 ps for a period of 60ns - |---------------- Core Stall Status ----------------| - (24,1) -> Lock stall -> Lock_East detected at T=571600.000000 ps - (25,1) -> Lock stall -> Lock_East detected at T=575600.000000 ps - (25,2) -> Lock stall -> Lock_South detected at T=574000.000000 ps - |---------------------------------------------------| - WARNING: This simulation is running with hang detection time of 60ns, to modify the hang detect time please rerun simulation with -hang-detect-time= option - Exiting! - ``` + ``` + Enabling core(s) of graph mygraph + WARNING: All the cores are in stalled state at T=636000.000000 ps for a period of 60ns + |---------------- Core Stall Status ----------------| + (24,1) -> Lock stall -> Lock_East detected at T=571600.000000 ps + (25,1) -> Lock stall -> Lock_East detected at T=575600.000000 ps + (25,2) -> Lock stall -> Lock_South detected at T=574000.000000 ps + |---------------------------------------------------| + WARNING: This simulation is running with hang detection time of 60ns, to modify the hang detect time please rerun simulation with -hang-detect-time= option + Exiting! + ``` 7. Revert the changes in the source file to exercise other debug features. @@ -309,7 +287,7 @@ This topic is a continuation of the [Deadlock Detection](./README.md#Deadlock-de ![stream stall](./Images/stream_stall.PNG) 3. Expand the `peak_detect` kernel function, and observe the lock stall after three iterations. ![lock stall](./Images/lock_stall.PNG) -The kernel `data_shuffle` expects more stream data from the kernel `peak_detect` which it cannot provide. So, the stream port in the `data_shuffle` went into the stream stall, and the kernel hangs. It cannot accept more inputs from buffer port which causes the back pressure on `peak_detect` kernel leading to lock stall, which is the potential root-cause for the deadlock. +The kernel `data_shuffle` expects more stream data from the kernel `peak_detect` which it cannot provide. So, the stream port in the `data_shuffle` went into the stream stall, and the kernel hangs. It cannot accept more inputs from the buffer port which causes the back pressure on the `peak_detect` kernel leading to a lock stall, which is the potential root cause for the deadlock. # Section 7 @@ -317,91 +295,91 @@ The kernel `data_shuffle` expects more stream data from the kernel `peak_detect` Memory access violations occur when a kernel is reading or writing out of bounds of an object or reading uninitialized memory. This can manifest itself in multiple ways, such as a simulator crash or hang. This debug feature helps to find out of range memory access from each tile during the AI Engine emulation runtime; however, this option impacts runtime performance negatively. The 'out of range' memory access indicates valid address assignment within each section. There could be certain addresses that are not assigned between sections. -The aiesimulator option `--enable-memory-check` helps to find out these out of range memory accesses. +The aiesimulator option, `--enable-memory-check`, helps to find out these out of range memory accesses. Besides using the simulator option, it is necessary to first identify an invalid address from the design. To do this: 1. In a Linux terminal where a valid Vitis installation/setup is done, issue the following command to list a specific tile's valid memory addresses and sizes assigned by the AI Engine compiler: - For example, to get valid memory addresses of `peak_detect` kernel: + For example, to get valid memory addresses of `peak_detect` kernel: - ``` - # For Vitis IDE project - cd ${PROJECT_PATH}/peakDetect/aie_component/build/hw/Work/aie/25_0/Release/25_0 - readelf -S 25_0 - ``` + ``` + # For Vitis IDE project + cd ${PROJECT_PATH}/peakDetect/aie_component/build/hw/Work/aie/25_0/Release/25_0 + readelf -S 25_0 + ``` 2. The output of the `readelf` command is as follows. - ``` - readelf -S 25_0 - There are 33 section headers, starting at offset 0x47484: - - Section Headers: - [Nr] Name Type Addr Off Size ES Flg Lk Inf Al - [ 0] NULL 00000000 000000 000000 00 0 0 0 - [ 1] .shstrtab STRTAB 00000000 00268f 00016c 00 0 0 1 - [ 2] .strtab STRTAB 00000000 0027fb 000872 00 0 0 0 - [ 3] .symtab SYMTAB 00000000 00306d 000410 10 2 41 0 - [ 4] .bss.DMb.16 NOBITS 00029e00 000294 000200 00 WA 0 0 1 - [ 5] .bss.DMb.16 NOBITS 0002c000 000294 000200 00 WA 0 0 1 - [ 6] .bss.DMb.16 NOBITS 00031e00 000294 000200 00 WA 0 0 1 - [ 7] .data.DMb.4 PROGBITS 000357e0 000294 000020 00 WA 0 0 1 - [ 8] .data.DM_bankA.4 PROGBITS 00035c00 0002b4 000024 00 WA 0 0 1 - [ 9] .bss.DMb.16 NOBITS 00038000 0002d8 000200 00 WA 0 0 1 - [10] .bss.DMb.16 NOBITS 0003a000 0002d8 000200 00 WA 0 0 1 - [11] .bss.DMb.16 NOBITS 0003c000 0002d8 000200 00 WA 0 0 1 - [12] .text PROGBITS 00000000 0002d8 000102 00 AX 0 0 1 - [13] .text PROGBITS 00000110 0003da 0002d8 00 AX 0 0 1 - [14] .text PROGBITS 000003f0 0006b2 0003de 00 AX 0 0 1 - [15] .text PROGBITS 000007d0 000a90 0000be 00 AX 0 0 1 - [16] .text PROGBITS 00000890 000b4e 000094 00 AX 0 0 1 - [17] .debug_line PROGBITS 00000000 00347d 00169b 00 0 0 0 - [18] .debug_info PROGBITS 00000000 004b18 00a78c 00 0 0 0 - [19] .debug_abbrev PROGBITS 00000000 00f2a4 000755 00 0 0 0 - [20] .debug_loc PROGBITS 00000000 00f9f9 005581 00 0 0 0 - [21] .debug_frame PROGBITS 00000000 014f7a 000d54 00 0 0 0 - [22] .debug_ranges PROGBITS 00000000 015cce 0017b8 00 0 0 0 - [23] .debug_str STRTAB 00000000 017486 023195 00 0 0 0 - [24] .debug_pubnames PROGBITS 00000000 03a61b 00ad75 00 0 0 0 - [25] .debug_pubtypes PROGBITS 00000000 045390 00208c 00 0 0 0 - [26] .tctmemstrtab STRTAB 00000000 000be2 000a78 00 0 0 0 - [27] .tctmemtab LOPROC+0x123456 00000000 04741c 000068 08 26 0 0 - [28] .tctmemtab LOPROC+0x123467 00000000 00165a 000068 08 26 0 0 - [29] .stackinfo LOPROC+0x123458 00000000 0016c2 000010 10 0 0 0 - [30] .rtstab LOPROC+0x123469 00000000 0016d2 0000a9 0d 0 0 0 - [31] .eoltab LOPROC+0x123470 00000000 00177b 0008f4 0c 0 0 0 - [32] .chesstypean[...] LOPROC+0x123468 00000000 00206f 000620 10 0 0 0 - Key to Flags: - W (write), A (alloc), X (execute), M (merge), S (strings), I (info), - L (link order), O (extra OS processing required), G (group), T (TLS), - C (compressed), x (unknown), o (OS specific), E (exclude), - D (mbind), p (processor specific) - ``` - - Here, the flags `WA` and `AX` indicates, this section will be loaded into tile memory. - -3. Add the memory read violation to the kernel code by opening `src/kernels/peak_detect.cc`, and change the line-26 to `v_in = *(InIter+8500)`. + ``` + readelf -S 25_0 + There are 33 section headers, starting at offset 0x47484: + + Section Headers: + [Nr] Name Type Addr Off Size ES Flg Lk Inf Al + [ 0] NULL 00000000 000000 000000 00 0 0 0 + [ 1] .shstrtab STRTAB 00000000 00268f 00016c 00 0 0 1 + [ 2] .strtab STRTAB 00000000 0027fb 000872 00 0 0 0 + [ 3] .symtab SYMTAB 00000000 00306d 000410 10 2 41 0 + [ 4] .bss.DMb.16 NOBITS 00029e00 000294 000200 00 WA 0 0 1 + [ 5] .bss.DMb.16 NOBITS 0002c000 000294 000200 00 WA 0 0 1 + [ 6] .bss.DMb.16 NOBITS 00031e00 000294 000200 00 WA 0 0 1 + [ 7] .data.DMb.4 PROGBITS 000357e0 000294 000020 00 WA 0 0 1 + [ 8] .data.DM_bankA.4 PROGBITS 00035c00 0002b4 000024 00 WA 0 0 1 + [ 9] .bss.DMb.16 NOBITS 00038000 0002d8 000200 00 WA 0 0 1 + [10] .bss.DMb.16 NOBITS 0003a000 0002d8 000200 00 WA 0 0 1 + [11] .bss.DMb.16 NOBITS 0003c000 0002d8 000200 00 WA 0 0 1 + [12] .text PROGBITS 00000000 0002d8 000102 00 AX 0 0 1 + [13] .text PROGBITS 00000110 0003da 0002d8 00 AX 0 0 1 + [14] .text PROGBITS 000003f0 0006b2 0003de 00 AX 0 0 1 + [15] .text PROGBITS 000007d0 000a90 0000be 00 AX 0 0 1 + [16] .text PROGBITS 00000890 000b4e 000094 00 AX 0 0 1 + [17] .debug_line PROGBITS 00000000 00347d 00169b 00 0 0 0 + [18] .debug_info PROGBITS 00000000 004b18 00a78c 00 0 0 0 + [19] .debug_abbrev PROGBITS 00000000 00f2a4 000755 00 0 0 0 + [20] .debug_loc PROGBITS 00000000 00f9f9 005581 00 0 0 0 + [21] .debug_frame PROGBITS 00000000 014f7a 000d54 00 0 0 0 + [22] .debug_ranges PROGBITS 00000000 015cce 0017b8 00 0 0 0 + [23] .debug_str STRTAB 00000000 017486 023195 00 0 0 0 + [24] .debug_pubnames PROGBITS 00000000 03a61b 00ad75 00 0 0 0 + [25] .debug_pubtypes PROGBITS 00000000 045390 00208c 00 0 0 0 + [26] .tctmemstrtab STRTAB 00000000 000be2 000a78 00 0 0 0 + [27] .tctmemtab LOPROC+0x123456 00000000 04741c 000068 08 26 0 0 + [28] .tctmemtab LOPROC+0x123467 00000000 00165a 000068 08 26 0 0 + [29] .stackinfo LOPROC+0x123458 00000000 0016c2 000010 10 0 0 0 + [30] .rtstab LOPROC+0x123469 00000000 0016d2 0000a9 0d 0 0 0 + [31] .eoltab LOPROC+0x123470 00000000 00177b 0008f4 0c 0 0 0 + [32] .chesstypean[...] LOPROC+0x123468 00000000 00206f 000620 10 0 0 0 + Key to Flags: + W (write), A (alloc), X (execute), M (merge), S (strings), I (info), + L (link order), O (extra OS processing required), G (group), T (TLS), + C (compressed), x (unknown), o (OS specific), E (exclude), + D (mbind), p (processor specific) + ``` + + Here, the flags `WA` and `AX` indicates, this section will be loaded into the tile memory. + +3. Add the memory read violation to the kernel code by opening `src/kernels/peak_detect.cc`, and change line 26 to `v_in = *(InIter+8500)`. 4. Build the *[aiengine]* domain project, add the `--enable-memory-check` option to the **Run Configurations**, and run the aiesimulation. 5. Observe the following messages in the console. - ``` - Waiting for core(s) of graph mygraph to finish execution ... - 670400 ps [ERROR] tl.aie_logical.aie_xtlm.math_engine.array.tile_25_1.cm.proc: dme_lda_e_out access out of boundary! address = 0xbcd20 prog_cntr = 0x00010010010100 - 670400 ps [ERROR] tl.aie_logical.aie_xtlm.math_engine.array.tile_25_1.cm.proc: dme_ldb_e_out access out of boundary! address = 0xbcd00 prog_cntr = 0x00010010010100 - 670400 ps [ERROR] tl.aie_logical.aie_xtlm.math_engine.array.tile_25_1.cm.proc: dmo_lda_e_out access out of boundary! address = 0xbcd30 prog_cntr = 0x00010010010100 - 670400 ps [ERROR] tl.aie_logical.aie_xtlm.math_engine.array.tile_25_1.cm.proc: dmo_ldb_e_out access out of boundary! address = 0xbcd10 prog_cntr = 0x00010010010100 - ``` + ``` + Waiting for core(s) of graph mygraph to finish execution ... + 670400 ps [ERROR] tl.aie_logical.aie_xtlm.math_engine.array.tile_25_1.cm.proc: dme_lda_e_out access out of boundary! address = 0xbcd20 prog_cntr = 0x00010010010100 + 670400 ps [ERROR] tl.aie_logical.aie_xtlm.math_engine.array.tile_25_1.cm.proc: dme_ldb_e_out access out of boundary! address = 0xbcd00 prog_cntr = 0x00010010010100 + 670400 ps [ERROR] tl.aie_logical.aie_xtlm.math_engine.array.tile_25_1.cm.proc: dmo_lda_e_out access out of boundary! address = 0xbcd30 prog_cntr = 0x00010010010100 + 670400 ps [ERROR] tl.aie_logical.aie_xtlm.math_engine.array.tile_25_1.cm.proc: dmo_ldb_e_out access out of boundary! address = 0xbcd10 prog_cntr = 0x00010010010100 + ``` - The address `0x0000bcd30` is out of range from the valid addresses you see from the `readelf` command. + The address `0x0000bcd30` is out of range from the valid addresses you see from the `readelf` command. 6. The AI Engine simulation generates the `${PROJECT_PATH}/peakDetect/aie_component/build/hw/AIESim_Guidance.json` file which can be viewed when the `${PROJECT_PATH}/peakDetect/aie_component/build/hw/aiesimulator_output/default.aierun_summary` file is opened in the Vitis Analyzer. ![aiesim guidance](./Images/aiesim_guidance.PNG) 7. The **PC** column in the **Memory Violations** tab helps redirecting to the kernel function that has a memory violation. - >**NOTE:** Currently, if the violation impacts the API, e.g., `aie::mul` in this case, clicking the `PC` might not redirect you to the exact kernel function. A general recommendation in these kind of cases where memory violations cannot be identified is to use the `x86simulator` with the `valgrind` option as explained in [Memory Access Violation and Valgrind Support for the x86simulator](../X86_Simulation/README.md#memory-access-violation-and-valgrind-support). + >**NOTE:** Currently, if the violation impacts the API, e.g., `aie::mul` in this case, clicking the `PC` might not redirect you to the exact kernel function. A general recommendation in these kind of cases where memory violations cannot be identified is to use the `x86simulator` with the `valgrind` option as explained in [Memory Access Violation and Valgrind Support for the x86simulator](../X86_Simulation/README.md#memory-access-violation-and-valgrind-support). -8. Revert the changes in source code to exercise other debug features. +8. Revert the changes in the source code to exercise other debug features. # Section 8 @@ -409,19 +387,14 @@ Besides using the simulator option, it is necessary to first identify an invalid The AI Engine Pipeline view in the Vitis IDE allows you to correlate instructions executed in a specific clock cycle with the labels in the Disassembly view. The underlying AI Engine pipeline is exposed in debug mode using the pipeline view. -1. So to get the pipleline view, In the Flow navigator window, under AIE SIMULATION/HARDWARE, select the Run Settings under **aie_component_aiesim_1** Configuration, select the check box **Enable Pipeline View**. +1. To get the pipleline view, in the Flow navigator window, under AIE SIMULATION/HARDWARE, select the Run Settings under **aie_component_aiesim_1** Configuration, select the check box **Enable Pipeline View**. ![enable_pipeline view](./Images/enable_pipeline.PNG) - 2. Select **Generate Profile** from the Profile Options. - 3. Enter the debug, as explained in the [Debug Using Vitis IDE Debugger](./README.md#Debug-using-Vitis-IDE-debugger) section, to observe only a single core in the **Debug** window. The **Pipeline View** automatically comes up as soon as IDE enters the debug mode. -![pipeline view](./Images/pipeline_view.PNG) - +![pipeline view](./Images/pipeline_view.PNG) 4. Click the **Step Over** button, and observe the changes in the pipeline view as well as the **Cycle Count**,**Program Counter** in Runtime statistics. The main advantage of the pipeline view is when you want to observe how many cycles a particular instruction takes. - 5. Once the debug is done, hit the **Resume** button to complete the simulation or the **Terminate** button to exit the debugger smoothly. - # Section 9 ## Design Performance Debug @@ -430,33 +403,28 @@ To estimate the design performance during the AI Engine simulation, it is necess Refer to the Section 4 [Enabling the Profile and Trace Options](./README.md#Enabling-the-profile-and-trace-options) to understand how to enable profiling in the Vitis IDE. -1. After running the AI Engine Simulation, open the profile **analysis view -> aie_component -> AIE SIMULATOR/HARDWARE -> Run-aie_component -> Profile** . +1. After running the AI Engine Simulation, open the profile **analysis view -> aie_component -> AIE SIMULATOR/HARDWARE -> Run-aie_component -> Profile**. 2. You can click the **Summary** corresponding to each tile in the landing page, and observe the cycle count, instruction count, and program memory. 3. Now, under the **Function Reports**, click the **Total Function Time** to observe the following table at the bottom for the `data_shuffle` kernel function. ![profile function time](./Images/profile_function_time.PNG) - - * The `data_shuffle` kernel function took 2,303 cycles for seven iterations, i.e., ~329 cycles for one iteration which is the **Avg Function Time**. - * The `main` function is added by the compiler and different from the `main()` function in the `graph.cpp` file. This function took 99749 cycles in total which includes the time to transfer control back and forth between each graph iteration, lock stalls, etc. - * The `_main_init` runs once for all graph iterations, and it took 26 cycles. - * The `_cxa_finalize` function took 43 cycles to call the destructors of the global c++ objects. - * The `_fini` function executes the program terminating instructions, and it took 24 cycles. - -4. If you click the AI Engine Simulation **Summary**, you can notice the AI Engine Frequency as `1250 MHz` i.e., `0.8ns`, i.e., `1` cycle = `0.8 ns` - Now, the data_shuffle function took `329` cycles for `1` iteration, i.e., `329 * 0.8 ~= 264 ns`. - -5. Try to match these valuess with the trace information. Click **Trace**, and zoom in to the period of one iteration (between two `main()` function calls as follows), and add a marker and drag it to the end of the kernel function. + * The `data_shuffle` kernel function took 2,303 cycles for seven iterations, i.e., ~329 cycles for one iteration which is the **Avg Function Time**. + * The `main` function is added by the compiler and different from the `main()` function in the `graph.cpp` file. This function took 99749 cycles in total which includes the time to transfer control back and forth between each graph iteration, lock stalls, etc. + * The `_main_init` runs once for all graph iterations, and it took 26 cycles. + * The `_cxa_finalize` function took 43 cycles to call the destructors of the global c++ objects. + * The `_fini` function executes the program terminating instructions, and it took 24 cycles. +4. If you click the AI Engine Simulation **Summary**, you can notice the AI Engine Frequency as `1250 MHz`, i.e., `0.8ns`, i.e., `1` cycle = `0.8 ns` + Now, the data_shuffle function took `329` cycles for `1` iteration, i.e., `329 × 0.8 ~= 264 ns`. +5. Try to match these values with the trace information. Click **Trace**, and zoom into the period of one iteration (between two `main()` function calls as follows), and add a marker and drag it to the end of the kernel function. ![trace function time](./Images/trace_function_time.PNG) - - The difference between the starting time and end time of the kernel function for one iteration matches with the 264 ns seen in the profiling results. + The difference between the starting time and end time of the kernel function for one iteration matches with the 264 ns seen in the profiling results. ### Calculating the Graph Throughput Using Graph Output -1. From the trace information in the run_summary in the Vitis Analyzer, navigate to the output port for which you want to calculate the throughput (`upscale` kernel in this case). Add a marker at the start of the first output sample as highlighted as follows. Then click the `Go to last time` icon, and observe the cursor moves to the end of the last iteration. Now, click the **previous transition** icon to go the start of the last iteration. Add one more marker at the end, and observe the time difference as `2282.320 ns`. +1. From the trace information in the run_summary in the Vitis Analyzer, navigate to the output port for which you want to calculate the throughput (`upscale` kernel in this case). Add a marker at the start of the first output sample as highlighted as follows. Then click the **Go to last time** icon, and observe the cursor moves to the end of the last iteration. Now, click the **previous transition** icon to go the start of the last iteration. Add one more marker at the end, and observe the time difference as `2282.320 ns`. ![trace graph throughput](./Images/trace_graph_throughput.PNG) 2. The number of bytes transferred is `128 samples * 4 Bytes * 7 iterations` = `3584` bytes. -3. Throughput = 3584/2282 * e-9 ~= 1.5 GBPS. - - Theoratically, AI Engine can transfer four bytes per cycle (in this case, 0.8 ns). So, to transfer `3584` bytes of data, it requires 896 cycles (896 * 0.8 = 716 ns). So, the theoratical througput is 5 GBPS. +3. Throughput = 3584/2273 × e-9 ~= 1.5 Gbps. + Theoretically, AI Engine can transfer four bytes per cycle (in this case, 0.8 ns). So, to transfer `3584` bytes of data, it requires 896 cycles (`896 × 0.8 = 716 ns`). So, the theoretical throughput is 5 Gbps. ## Support @@ -464,4 +432,4 @@ GitHub issues will be used for tracking requests and bugs. For questions, go to

Copyright © 2020–2023 Advanced Micro Devices, Inc

-

Terms and Conditions

+

Terms and Conditions

\ No newline at end of file diff --git a/AI_Engine_Development/AIE/Feature_Tutorials/09-debug-walkthrough/CreateIDESystemProj.md b/AI_Engine_Development/AIE/Feature_Tutorials/09-debug-walkthrough/CreateIDESystemProj.md index a3dfb74358..332d020554 100644 --- a/AI_Engine_Development/AIE/Feature_Tutorials/09-debug-walkthrough/CreateIDESystemProj.md +++ b/AI_Engine_Development/AIE/Feature_Tutorials/09-debug-walkthrough/CreateIDESystemProj.md @@ -16,9 +16,9 @@ This section walks you through the flow of porting your command line project to ## Step 1: Launch Vitis Unified IDE -**IMPORTANT:** The following steps assume you have configured the environment as described in the [*Introduction*](./README.md) of the tutorial. +**IMPORTANT:** The following steps assume you have configured the environment as described in the [*Introduction*](./README.md) of the tutorial. -To begin the tutorial, you must create a workspace for your design and launch the new Vitis unified IDE. Use the following command sequence to change directory to the current tutorial, make a workspace folder, and launch the IDE: +To begin the tutorial, you must create a workspace for your design and launch the new Vitis unified IDE. Use the following command sequence to change directory to the current tutorial, make a workspace folder, and launch the IDE: ``` cd /09-debug-walkthrough/ @@ -30,98 +30,98 @@ vitis -w peakDetect As shown in the figure above, this tutorial contains three AI Engine kernels: Interpolator, Polar_clip, and Classifier. Start by creating the AIE component that will contain the graph and kernels. Run the following steps: -1. From the main menu select **File > New Component > AI Engine** +1. From the main menu select **File > New Component > AI Engine** -This opens the Create AI Engine Component wizard on the *Name and Location* page. + This opens the Create AI Engine Component wizard on the *Name and Location* page. -2. Enter the `Component name` as aie_component (default), enter the `Component location` as the workspace (default), and click **Next**. +2. Enter the `Component name` as aie_component (default), enter the `Component location` as the workspace (default), and click **Next**. -This opens the *Add Source Files* page. + This opens the *Add Source Files* page. -3. Select `Import Sources > Add Folder` and navigate to `/09-debug-walkthrough/cmd_src/aie` and click **OK**. Repeat the process to add the `data/` directory also. +3. Select `Import Sources > Add Folder` and navigate to `/09-debug-walkthrough/cmd_src/aie` and click **OK**. Repeat the process to add the `data/` directory also. -4. Under `Select top-level file` confirm that `graph.cpp` has been selected and click **Next**. +4. Under `Select top-level file` confirm that `graph.cpp` has been selected and click **Next**. -The tool automatically selects the top-level graph from imported files. You just need to make sure it has chosen correctly. Clicking **Next** opens the *Select Part* page. + The tool automatically selects the top-level graph from imported files. You just need to make sure it has chosen correctly. Clicking **Next** opens the *Select Part* page. -5. Select the `xilinx_vck190_base_20XXX0_1` platform and click **Next** to open the *Summary* page. +5. Select the `xilinx_vck190_base_20XXX0_1` platform and click **Next** to open the *Summary* page. -6. Review the *Summary* page and click **Finish** to create the defined AI Engine component. +6. Review the *Summary* page and click **Finish** to create the defined AI Engine component. -This results in the aie_component `vitis-comp.json` file being opened. This is the file associated with the component in the Vitis unified IDE as shown in the following image. The tab at the top will display `vitis-comp.json`, but it is the aie_component you just created. + This results in the aie_component `vitis-comp.json` file being opened. This is the file associated with the component in the Vitis unified IDE as shown in the following image. The tab at the top will display `vitis-comp.json`, but it is the aie_component you just created. -![System Diagram](./Images/vitis-ide-aie-component.png) + ![System Diagram](./Images/vitis-ide-aie-component.png) -7. Select the `aiecompiler.cfg` link and open the config file. It contains `include` statements for the added `aie` source code folder. -8. Add a new line `include=/aie/kernels`. +7. Select the `aiecompiler.cfg` link and open the config file. It contains `include` statements for the added `aie` source code folder. +8. Add a new line `include=/aie/kernels`. -The `[aie]` section contains configuration commands such as the `xchess` statement. Refer to [*v++ Mode AI Engine*](https://docs.xilinx.com/r/en-US/ug1553-vitis-ide/v-Mode-AI-Engine) for more information on these configuration commands. +The `[aie]` section contains configuration commands such as the `xchess` statement. Refer to [*v++ Mode AI Engine*](https://docs.xilinx.com/r/en-US/ug1553-vitis-ide/v-Mode-AI-Engine) for more information on these configuration commands. -In the Vitis Components explorer, expand the `aie_component` and examine the included sub-folders: Settings, Includes, Sources... Notice the `aie` folder you imported into the Sources folder. +In the Vitis Components explorer, expand the `aie_component` and examine the included sub-folders: Settings, Includes, Sources, and so forth. Notice the `aie` folder you imported into the Sources folder. ## Step 3: Create HLS Components -The AIE graph application you are working on requires two PL kernels to load data onto the device. These are the `mm2s` and `s2mm` kernels. You will create separate HLS components using the following steps: +The AIE graph application you are working on requires two PL kernels to load data onto the device. These are the `mm2s` and `s2mm` kernels. You will create separate HLS components using the following steps: -1. From the main menu select **File > New Component > HLS** +1. From the main menu select **File > New Component > HLS** -This opens the Create HLS Component wizard on the *Name and Location* page. + This opens the Create HLS Component wizard on the *Name and Location* page. -2. Enter the `Component name` as mm2s, enter the `Component location` as the workspace (default), and click **Next**. +1. Enter the `Component name` as mm2s, enter the `Component location` as the workspace (default), and click **Next**. -This opens the *Configuration File* page. The configuration file contains commands for building and running the HLS component as described in [*v++ Mode HLS*](https://docs.xilinx.com/r/en-US/ug1553-vitis-ide/v-Mode-HLS). You can specify a new empty file, an existing config file, or generate a config file from an existing HLS project as described in [*Creating an HLS Component*](https://docs.xilinx.com/r/en-US/ug1553-vitis-ide/Creating-an-HLS-Component). + This opens the *Configuration File* page. The configuration file contains commands for building and running the HLS component as described in [*v++ Mode HLS*](https://docs.xilinx.com/r/en-US/ug1553-vitis-ide/v-Mode-HLS). You can specify a new empty file, an existing config file, or generate a config file from an existing HLS project as described in [*Creating an HLS Component*](https://docs.xilinx.com/r/en-US/ug1553-vitis-ide/Creating-an-HLS-Component). -3. Select `Empty File` and click **Next**. +1. Select `Empty File` and click **Next**. -This opens the *Source Files* page. + This opens the *Source Files* page. -![Unified IDE - HLS Sources](./Images/unified-hls-add-sources.png) + ![Unified IDE - HLS Sources](./Images/unified-hls-add-sources.png) -5. Select the Add Files icon to open a file browser, navigate to `/09-debug-walkthrough/cmd_src/pl_kernels/mm2s.cpp` and select **OK**. +1. Select the Add Files icon to open a file browser, navigate to `/09-debug-walkthrough/cmd_src/pl_kernels/mm2s.cpp` and select **OK**. -6. Under the Top Function browse and select the `mm2s` function and click **Next**. Note that there are no testbenches for these kernels. +1. Under the Top Function browse and select the `mm2s` function and click **Next**. Note that there are no testbenches for these kernels. -7. On the *Select Part* page select the `xilinx_vck190_base_20xxx0_1` platform and click **Next** to open the Settings page. +1. On the *Select Part* page select the `xilinx_vck190_base_20xxx0_1` platform and click **Next** to open the Settings page. -8. On the *Settings* page select the `Vitis Kernel Flow`. +1. On the *Settings* page select the `Vitis Kernel Flow`. -9. Under the Clock settings specify `8ns` for the Period, and `12%` for the Uncertainty to override the default values. Click **Next** to open the *Summary* page. +1. Under the Clock settings specify `8ns` for the Period, and `12%` for the Uncertainty to override the default values. Click **Next** to open the *Summary* page. + +1. Review the *Summary* page and click **Finish** to create the defined HLS component. -10. Review the *Summary* page and click **Finish** to create the defined HLS component. - Repeat the prior steps to create the `s2mm` HLS component. -In the `vitis-comp.json` for either the `mm2s` or `s2mm` HLS components, select the Config File link to open the `hls_config.cfg` file for the specific component. Examine the contents of the config file. It currently contains the part (defined by the platform), flow target, source cpp file and other options that you defined when creating the HLS component. Notice that most of the options fall under the `[hls]` header. +In the `vitis-comp.json` for either the `mm2s` or `s2mm` HLS components, select the Config File link to open the `hls_config.cfg` file for the specific component. Examine the contents of the config file. It currently contains the part (defined by the platform), flow target, source cpp file and other options that you defined when creating the HLS component. Notice that most of the options fall under the `[hls]` header. ## Step 4: Create the Application Component -The Application component is an application that runs on the processor, Arm or x86, that loads and runs the device binary (`.xclbin`) which you will build later. The Vitis unified IDE automatically detects whether the Application component uses XRT native API or OpenCL and compiles the code as needed. Create the Application component using the following steps: +The Application component is an application that runs on the processor, Arm or x86, that loads and runs the device binary (`.xclbin`) which you will build later. The Vitis unified IDE automatically detects whether the Application component uses XRT native API or OpenCL and compiles the code as needed. Create the Application component using the following steps: + +1. From the main menu select **File > New Component > Application** -1. From the main menu select **File > New Component > Application** + This opens the Create Application Component wizard on the *Name and Location* page. -This opens the Create Application Component wizard on the *Name and Location* page. +2. Enter the `Component name` as host, enter the `Component location` as the workspace (default), and click **Next**. -2. Enter the `Component name` as host, enter the `Component location` as the workspace (default), and click **Next**. + This opens the *Select Platform* page. -This opens the *Select Platform* page. +3. On the *Select Platform* page select the `xilinx_vck190_base_20xxx0_1` platform and click **Next** to open the *Select Domain* page. -3. On the *Select Platform* page select the `xilinx_vck190_base_20xxx0_1` platform and click **Next** to open the *Select Domain* page. + On the *Select Domain* page you will select from the available processor domains and OS. In this case there is only one choice. -On the *Select Domain* page you will select from the available processor domains and OS. In this case there is only one choice. +4. Select the xrt domain and click **Next** to open the *Sysroot* page. -4. Select the xrt domain and click **Next** to open the *Sysroot* page. + On the *Sysroot* page you will provide a path to the sysroot as part of the common images for the selected platform. You can find more information on this at [*Installing Embedded Platforms*](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Installing-Embedded-Platforms?tocId=9o7rpHmLluJkAdxzCI_2yA). -On the *Sysroot* page you will provide a path to the sysroot as part of the common images for the selected platform. You can find more information on this at [*Installing Embedded Platforms*](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Installing-Embedded-Platforms?tocId=9o7rpHmLluJkAdxzCI_2yA). + Enter the path to the Sysroot for the selected platform and click **Next** to open the *Summary* page. -Enter the path to the Sysroot for the selected platform and click **Next** to open the *Summary* page. +5. Review the *Summary* page and click **Finish** to create the defined Application component. -5. Review the *Summary* page and click **Finish** to create the defined Application component. - -The Application component `vitis-comp.json` file is opened in the center editor, and the component is added to the Component Explorer. When creating the Application component you do not specify source files so you must add the required source files after the component is created. + The Application component `vitis-comp.json` file is opened in the center editor, and the component is added to the Component Explorer. When creating the Application component you do not specify source files so you must add the required source files after the component is created. -![Unified IDE - Application Sources](./Images/unified-app-sources.png) + ![Unified IDE - Application Sources](./Images/unified-app-sources.png) -In the Vitis Components Explorer view expand the `host` component, right-click the `Sources` folder and **Import Source > Files** to import the following source files: +In the Vitis Components Explorer view, expand the `host` component, right-click the `Sources` folder and **Import Source > Files** to import the following source files: ``` /09-debug-walkthrough/cmd_src/sw/host.cpp @@ -132,42 +132,43 @@ In the Vitis Components Explorer view expand the `host` component, right-click t ## Step 5: Create the System Project -The System project is where the different components that you have built so far are integrated into a single system as described in [*Creating a System Project for Heterogeneous Computing*](https://docs.xilinx.com/r/en-US/ug1553-vitis-ide/Creating-a-System-Project-for-Heterogeneous-Computing). The AI Engine component, the HLS components, and the Application component are integrated into the system project using the following steps. +The System project is where the different components that you have built so far are integrated into a single system as described in [*Creating a System Project for Heterogeneous Computing*](https://docs.xilinx.com/r/en-US/ug1553-vitis-ide/Creating-a-System-Project-for-Heterogeneous-Computing). The AI Engine component, the HLS components, and the Application component are integrated into the system project using the following steps. -1. From the main menu select **File > New Component > System Project** +1. From the main menu select **File > New Component > System Project** -This opens the Create System Project wizard on the *Name and Location* page. + This opens the Create System Project wizard on the *Name and Location* page. -2. Enter the `Component name` as system_project (default), enter the `Component location` as the workspace (default), and click **Next**. +2. Enter the `Component name` as system_project (default), enter the `Component location` as the workspace (default), and click **Next**. -This opens the *Select Platform* page. + This opens the *Select Platform* page. -3. On the Select Part page select the `xilinx_vck190_base_20xxx0_1` platform and click **Next** to open the Embedded Component Paths page. +3. On the Select Part page select the `xilinx_vck190_base_20xxx0_1` platform and click **Next** to open the Embedded Component Paths page. -The Embedded Component Paths page lets you specify the path to the Sysroot, RootFS, and Image for the embedded processor platform as described at [*Installing Embedded Platforms*](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Installing-Embedded-Platforms?tocId=9o7rpHmLluJkAdxzCI_2yA). Enter the following choices and click **Next** to proceed: + The Embedded Component Paths page lets you specify the path to the Sysroot, RootFS, and Image for the embedded processor platform as described at [*Installing Embedded Platforms*](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Installing-Embedded-Platforms?tocId=9o7rpHmLluJkAdxzCI_2yA). Enter the following choices and click **Next** to proceed: -``` -Kernel Image: /Image -Root FS: /rootfs.ext4 -Sysroot: /sysroots/cortexa72-cortexa53-xilinx-linux -``` -**TIP:** You can enable the `Update Workspace Preference` checkbox to add the settings to any component or project that uses the specified platform as explained in [*Embedded Component Paths*](https://docs.xilinx.com/r/en-US/ug1553-vitis-ide/Embedded-Component-Paths). + ``` + Kernel Image: /Image + Root FS: /rootfs.ext4 + Sysroot: /sysroots/cortexa72-cortexa53-xilinx-linux + ``` + + **TIP:** You can enable the `Update Workspace Preference` checkbox to add the settings to any component or project that uses the specified platform as explained in [*Embedded Component Paths*](https://docs.xilinx.com/r/en-US/ug1553-vitis-ide/Embedded-Component-Paths). -6. Review the Summary page and click **Finish** to create the defined System project. - -The System project `vitis-sys.json` file is opened in the center editor, and the project is added to the Vitis Components Explorer. +4. Review the Summary page and click **Finish** to create the defined System project. -After creating the System project, you need to configure it. You must define which of the components in the current workspace should be added to the System. In this case, all the components are to be added. + The System project `vitis-sys.json` file is opened in the center editor, and the project is added to the Vitis Components Explorer. + +After creating the System project, you need to configure it. You must define which of the components in the current workspace should be added to the System. In this case, all the components are to be added. ![Unified IDE - System Project Binary](./Images/unified-sys-proj-bin.png) -Under the Hardware Linker Settings in the open `vitis-sys.json` file, start by selecting the `+` command next to the Binary Containers. This lets you add a binary container when one doesn't exist. Accept the default name `binary_container_1` and select both the HLS components that are displayed: `mm2s` and `s2mm`. This creates the binary container for the System project and lets you add HLS components at the same time. +Under the Hardware Linker Settings in the open `vitis-sys.json` file, start by selecting the `+` command next to the Binary Containers. This lets you add a binary container when one doesn't exist. Accept the default name `binary_container_1` and select both the HLS components that are displayed: `mm2s` and `s2mm`. This creates the binary container for the System project and lets you add HLS components at the same time. -Expand the Binary Container and scroll down to the AIE Graphs and select `+` to select and add the `aie_component`. +Expand the Binary Container and scroll down to the AIE Graphs and select `+` to select and add the `aie_component`. -Select the `hw_link/binary_container_1-link.cfg` to edit the configuration file containing commands that determine how the hw_link process will run and the how device binary will be generated. The Config File Editor opens and displays the V++ Linker Settings. Look through the settings to see what is available. In the lower half of the Config File Editor is a *Kernels Data* section that lets you specify the number of CUs for each kernels, or the naming convention applied. You can also enable profiling options for when the device is run. +Select the `hw_link/binary_container_1-link.cfg` to edit the configuration file containing commands that determine how the hw_link process will run and the how device binary will be generated. The Config File Editor opens and displays the V++ Linker Settings. Look through the settings to see what is available. In the lower half of the Config File Editor is a *Kernels Data* section that lets you specify the number of CUs for each kernels, or the naming convention applied. You can also enable profiling options for when the device is run. -Select the **Source Editor** command to see the text form of the Config File Editor. +Select the **Source Editor** command to see the text form of the Config File Editor. The design features a number of PL kernels as well as the AI Engine graph. You need to tell the linker how to connect the AI Engine array to PL and vice versa. You will need to replace the current lines in the config file: @@ -178,6 +179,7 @@ nk=s2mm:1:s2mm_1 ``` With the following lines: + ```ini [connectivity] nk=mm2s:1:mm2s @@ -193,22 +195,23 @@ sc=ai_engine_0.DataOut1:s2mm.s **NOTE:** For `ai_engine_0` the streaming input and output names are provided in the `graph.h`, for example: -```in = adf::input_plio::create("DataIn1", adf::plio_32_bits,"data/input.txt");``` +``` +in = adf::input_plio::create("DataIn1", adf::plio_32_bits,"data/input.txt"); +``` -Close the Config File Editor and return to the System project. +Close the Config File Editor and return to the System project. Click the link for the Package Settings config file, `package/package.cfg`. The packaging process creates the packaged SD card directory and contains everything needed to boot Linux and run your generated application and device binary. ![Unified IDE - System Project Package](./Images/unified-sys-proj-pkg.png) -Examine the file, scroll down to the AI Engine settings. Select the checkbox for **Do Not Enable Cores** to prevent the AI Engine from starting before the Application begins. Switch to the text view of the `package.cfg` file and ensure it has the `defer_aie_run=true` statement in it. - -Close the `package.cfg` file when you are finished. +Examine the file, scroll down to the AI Engine settings. Select the checkbox for **Do Not Enable Cores** to prevent the AI Engine from starting before the Application begins. Switch to the text view of the `package.cfg` file and ensure it has the `defer_aie_run=true` statement in it. -Finally, you can add the host application to the System project. Select the **Add Existing Component** link under the Component heading. Select the Application component to add. Add the `host` application. +Close the `package.cfg` file when you are finished. -The System project is now fully defined. +Finally, you can add the host application to the System project. Select the **Add Existing Component** link under the Component heading. Select the Application component to add. Add the `host` application. +The System project is now fully defined. ## Support diff --git a/AI_Engine_Development/AIE/Feature_Tutorials/09-debug-walkthrough/HW_Emulation/README.md b/AI_Engine_Development/AIE/Feature_Tutorials/09-debug-walkthrough/HW_Emulation/README.md index c7db7a1351..26e331a35a 100644 --- a/AI_Engine_Development/AIE/Feature_Tutorials/09-debug-walkthrough/HW_Emulation/README.md +++ b/AI_Engine_Development/AIE/Feature_Tutorials/09-debug-walkthrough/HW_Emulation/README.md @@ -11,7 +11,7 @@ ## Introduction -To simulate the entire system, including the AI Engine graph and programmable logic (PL) along with the XRT-based host application to control the AI Engine and PL, for a specific board and platform, you must use the hardware emulation flow. This flow includes the SystemC model of the AI Engine, transaction-level SystemC models for the NoC, double-data rate (DDR) memory, PL kernels (RTL), and processing system (PS) (running on the Quick Emulator (QEMU). This can be used in analyzing the data which helps you gauge the efficiency of the kernels, the stall and active times associated with each AI Engine, and pinpoint the AI Engine kernel whose performance might not be optimal. +To simulate the entire system, including the AI Engine graph and programmable logic (PL) along with the XRT-based host application to control the AI Engine and PL, for a specific board and platform, you must use the hardware emulation flow. This flow includes the SystemC model of the AI Engine, transaction-level SystemC models for the NoC, double-data rate (DDR) memory, PL kernels (RTL), and processing system (PS) (running on the Quick Emulator (QEMU)). This can be used in analyzing the data which helps you gauge the efficiency of the kernels, the stall and active times associated with each AI Engine, and pinpoint the AI Engine kernel whose performance might not be optimal. The following are some of the features of the hardware emulation that are covered in this section of the tutorial: @@ -51,7 +51,7 @@ This section profiles the system for hardware emulation and compares the through Command Line project Source Code Debug with the Vitis IDE -This section helps you debug your command line project by using the features of the Vitis IDE debugger without porting your system design to the IDE. +This section helps you debug your command line project by using the features of the AMD Vitis™ IDE debugger without porting your system design to the IDE. @@ -142,16 +142,14 @@ This section walks you through debugging PL kernels in the Vivado logic simulato 8. Now observe the waveform in the Vivado XSIM GUI. The system contains one `mm2s` compute unit and two `s2mm` compute units. You can notice them in the waveform viewer as follows: ![compute units](./Images/compute_units.PNG) - 9. You can form a group of signals by right-clicking anywhere in the **Name** column, and select **New Group**. Add all the MM2S and S2MM-related signals to this group by dragging them correspondingly. ![xsim waveform](./Images/xsim_waveform.PNG) - 10. Zoom into the waveform window to locate the transactions clearly. 11. The `m_axi_gmem` is the transaction level signal which indicates the `Read` transaction in `mm2s` and `write` transaction in `s2mm`. -12. The `TDATA` in `mm2s` shows the data that is being read into the AI Engine module. To correlate with the number of iterations (seven), you specified in the graph, observe the `TREADY` signal which goes high when the AI Engine module is ready to read and the `TVALID` signal goes high for all the Read transactions. +12. The `TDATA` in `mm2s` shows the data that is being read into the AI Engine module. To correlate with the number of iterations (seven), you specified in the graph, observe the `TREADY` signal which goes high when the AI Engine module is ready to read, and the `TVALID` signal goes high for all the Read transactions. 13. Similarly you can notice in `s2mm_1` the `TVALID` is high indicating the valid data and the `TLAST` goes high at the end of every iteration, goes low during start of next iteration. -This way you should be able to identify whether a data is being sent/received, to/from the AI Engine module correctly or not. + This way you should be able to identify whether a data is being sent/received, to/from the AI Engine module correctly or not. # Section 3 @@ -188,9 +186,8 @@ From the trace information, you can calculate the kernel latency as follows: #### Calculating the Graph Throughput Using the Graph Output -1. From the trace information in the run_summary in the Vitis Analyzer, navigate to the output port for which you want to calculate the throughput (Upscale kernel in this case). Add a marker at the start of the first output sample as highlighted below. Then click on the **Go** button to the last time icon and observe the cursor moves to the end of the last iteration. Now, click the previous transition icon to go the start of the last iteration. Add one more marker at the end, and observe the time difference as `2244.8 ns`. +1. From the trace information in the run_summary in the Vitis Analyzer, navigate to the output port for which you want to calculate the throughput (Upscale kernel in this case). Add a marker at the start of the first output sample as highlighted below. Then click the **Go** button to the last time icon, and observe the cursor moves to the end of the last iteration. Now, click the previous transition icon to go the start of the last iteration. Add one more marker at the end, and observe the time difference as `2244.8 ns`. ![graph throughput](./Images/graph_throughput.PNG) - 2. The number of bytes transferred is, `128` samples * `4` Bytes * `7` iterations = `3584` tes. Throughput = `3584/2244 * e-9 ~= 1.5 GBPS`. Compare the throughput with the one you got during `aiesimulation` where the AI Engine is a standalone module; see [Section 9](../AIE_Simulation/README.md#Calculating-Graph-throughput-using-Graph-output) in AIE Simulation. @@ -230,7 +227,7 @@ Before starting this tutorial: * Compiles the AI Engine kernels and generates `libadf.a`. * Compiles the PL kernels `s2mm`,`mm2s` and generates `.xo`. * Hardware linking step to link AI Engine kernels and PL kernels using the `system.cfg` file. This generates the `.xsa` file. - * Compiles the host application and generates the executable file `host.exe`.< + * Compiles the host application and generates the executable file `host.exe`. * Packages `libadf.a`,`.xsa`, and `host.exe` files. 4. To debug the source code in the Vitis IDE, you need three Linux terminals. @@ -285,8 +282,8 @@ Before starting this tutorial: ![command debug configuration menu](/.Images/cmd_debugConfigMenu.PNG) - * Create a new Debug configuration by double-clicking the **Single Application Debug**. - * Add the Debug type name, **aie_application_debug**, and **Debug Type** as **Attach to running target**. + * Create a new Debug configuration by double-clicking **Single Application Debug**. + * Add the Debug type name, **aie_application_debug** and **Debug Type** as **Attach to running target**. ![commmand debug configuration](./Images/cmd_debugConfigWin.PNG) diff --git a/AI_Engine_Development/AIE/Feature_Tutorials/09-debug-walkthrough/Hardware/README.md b/AI_Engine_Development/AIE/Feature_Tutorials/09-debug-walkthrough/Hardware/README.md index 8950c80dd4..0dc5bf0af5 100644 --- a/AI_Engine_Development/AIE/Feature_Tutorials/09-debug-walkthrough/Hardware/README.md +++ b/AI_Engine_Development/AIE/Feature_Tutorials/09-debug-walkthrough/Hardware/README.md @@ -11,13 +11,13 @@ ## Getting Started -To excercise and walk through the different hardware debug methodologies, it is required to clone the git repository, get the design files ready to build, and generate the hardware image file(`sd_card.img`). +To excercise and walk through the different hardware debug methodologies, it is required to clone the git repository, get the design files ready to build, and generate the hardware image file (`sd_card.img`). Make sure you set the environment variables as explained in this [link](../README.md#Introduction). ## Introduction -Designs running on AMD Versal™ AI Engine devices can target the AI Engine, programmable logic (PL), and Arm® host. To ensure a design targeting such multi-domain devices is functionally correct and meets the design performance specification, AMD recommends a five-stage profile and debug methodology in hardware. +Designs running on AMD Versal™ AI Engine devices can target the AI Engine, programmable logic (PL), and Arm® host. To ensure a design targeting such multi-domain devices is functionally correct and meets the design performance specification, AMD recommends a five stage profile and debug methodology in hardware. The stages are as follows: @@ -40,7 +40,7 @@ This stage helps you determine: ## [System Profiling](./Stage_2.md) -In this stage you can profile the AI Engine Core, Interface, and Memory modules in XRT or XSDB flows. It is a non-intrusive feature which can be enabled at runtime using the `XRT.ini` file or running scripts in XSDB. The feature uses performance counters available in the AI Engine array to gather profile data. The amount and type of data gathered is limited by the number of performance counters available. +In this stage, you can profile the AI Engine Core, Interface, and Memory modules in the XRT or XSDB flows. It is a non-intrusive feature which can be enabled at runtime using the `XRT.ini` file or running scripts in XSDB. The feature uses performance counters available in the AI Engine array to gather profile data. The amount and type of data gathered is limited by the number of performance counters available. ## [PL Kernel Analysis](./Stage_3.md) @@ -62,7 +62,7 @@ This stage helps you determine the AI Engine kernel or graph construct causing t The goal of this stage is to debug the host application and address application exceptions or crashes, if any exist using `printf()` or the Vitis IDE debugger. -**Complete hardware profile and debug methodology** +### Complete Hardware Profile and Debug Methodology ![hardware debug](./Images/complete_hwDebug.PNG) diff --git a/AI_Engine_Development/AIE/Feature_Tutorials/09-debug-walkthrough/Hardware/Stage_1.md b/AI_Engine_Development/AIE/Feature_Tutorials/09-debug-walkthrough/Hardware/Stage_1.md index 3f810f4efa..d45b650884 100644 --- a/AI_Engine_Development/AIE/Feature_Tutorials/09-debug-walkthrough/Hardware/Stage_1.md +++ b/AI_Engine_Development/AIE/Feature_Tutorials/09-debug-walkthrough/Hardware/Stage_1.md @@ -19,7 +19,6 @@ This stage helps you determine: ## Features - - + @@ -46,9 +45,9 @@ Explains how to use error reporting APIs to handle errors in the host code.
@@ -58,8 +57,8 @@ Explains different techniques (XRT, XBUtil, and XSDB) to analyze the design by r
Running the Design on Hardware @@ -28,15 +27,15 @@ This stage helps you determine: Explains how to determine the functional correctness of the design by running on hardware.
Error Handling and Reporting in the Host Application Explains how to use error reporting APIs to handle errors in the host code.
-       *XRT error handling APIs - This method reports errors that can be detected during the XRT runtime function call or underneath the driver, system, hardware, etc.
-     * Using XBUtil - XButil error reporting can accumulate all the errors from various classes and sorts them by timestamp.
+       - XRT error handling APIs - This method reports errors that can be detected during the XRT runtime function call or underneath the driver, system, hardware, etc.
+     - Using XBUtil - XButil error reporting can accumulate all the errors from various classes and sorts them by timestamp.
Explains different techniques (XRT, XBUtil, and XSDB) to analyze the design by running on hardware and helps to choose from the following methodologies:
-       *AI Engine status using XRT - Using XRT is fast and host executable can automatically reads the `xrt.ini` file to configure the runtime. -
-     * Manual AI Engine status using XBUtil utility - XBUtil is a standalone command utility included with XRT and does not require any special file to handle. You can directly use XBUtil commands on the console after boot.
-       * Deadlock detection using XSDB - XSDB runs independent of XRT and can analyze the results before, during, or after design runs. Also, you can use the XSDB for baremetal applications in addition to the Linux-based applications.
+      - AI Engine status using XRT - Using XRT is fast and the host executable can automatically reads the `xrt.ini` file to configure the runtime. -
+     - Manual AI Engine status using XBUtil utility - XBUtil is a standalone command utility included with XRT and does not require any special file to handle. You can directly use XBUtil commands on the console after boot.
+       - Deadlock detection using XSDB - XSDB runs independent of XRT and can analyze the results before, during, or after design runs. Also, you can use the XSDB for baremetal applications in addition to the Linux-based applications.
Explains how to modify the host code to add APIs in the host application that helps profiling the design for getting througput, latency, and bandwidth.
-       *Profiling Graph throughput - Provides insight on how to modify the host code for profiling the number of samples sent and received.
-     * Profiling to count the samples sent and received (Exercise Step) - Provides insight on how to modify the host code for profiling the number of samples sent and received.
+       - Profiling Graph throughput - Provides insight on how to modify the host code for profiling the number of samples sent and received.
+     - Profiling to count the samples sent and received (Exercise Step) - Provides insight on how to modify the host code for profiling the number of samples sent and received.
@@ -85,7 +84,6 @@ Before starting this tutorial: 2. Observe the hardware image file (`sd_card.img`) generated in the `sw/` directory. 3. Once the image is generated, you are ready to run the hardware image on board. The following are some steps to run on the board: - * Flash the SD card with the built `sd_card.img`. * Plug the flashed SD card into the SD card slot of the VCK190 board. * Connect the USB type C cable to the board and computer that supports serial port connection. @@ -120,52 +118,50 @@ It is necessary to analyze the run results to handle the design stalls by tracki 1. Now program the hardware image on to the VCK190 device, and create an `xrt.ini` file as follows: - ``` - //xrt.ini + ``` + //xrt.ini - [Debug] - aie_status=true - aie_status_interval_us=1000 - ``` + [Debug] + aie_status=true + aie_status_interval_us=1000 + ``` 2. Run the application, `host.exe a.xclbin`. 3. When the host program is running, the AI Engine status is copied to the `xrt.run_summary` file. A summary of the output files are: + * `xrt.run_summary`: Run summary that contains list of files information that can be used by the Vitis Analyzer. + * `aie_status_edge.json`: Status of AI Engine and AI Engine memory. + * `aieshim_status_edge.json`: AI Engine interface tiles status. + -`summary.csv`: Always created. - `xrt.run_summary`: Run summary that contains list of files information that can be used by the Vitis Analyzer. - `aie_status_edge.json`: Status of AI Engine and AI Engine memory. - `aieshim_status_edge.json`: AI Engine interface tiles status. - `summary.csv`: Always created. + You can also see the following messages in the console indicating the actual deadlock: - You can also see the following messages in the console indicating the actual deadlock: - - ``` - HOST: - EXE: /run/media/mmcblk0p1/host.exe - [XRT] WARNING: Potential deadlock/hang found in AI Engines. Graph : mygraph - [XRT] WARNING: Potential stuck cores found in AI Engines. Graph : mygraph Tile : (25,1) Status 0x401 : Enable,Stream_Stall_SS0 - ``` + ``` + HOST: + EXE: /run/media/mmcblk0p1/host.exe + [XRT] WARNING: Potential deadlock/hang found in AI Engines. Graph : mygraph + [XRT] WARNING: Potential stuck cores found in AI Engines. Graph : mygraph Tile : (25,1) Status 0x401 : Enable,Stream_Stall_SS0 + ``` 4. Observe the hang, and kill the application by pressing `Ctrl+c` or suspend using `Ctrl+z`. 5. Copy all these files back to the local workspace where the AI Enigne compile `Work/` directory is present, and open the `xrt.run_summary` file in the Vitis Analyzer. - ``` - vitis_analyzer --classic xrt.run_summary` - ``` + ``` + vitis_analyzer --classic xrt.run_summary` + ``` 6. Click **Set AI Engine Compile Summary**, point to the `Work/directory` manually, and observe the `graph` view to identify the stalls. ![xrt status](./Images/xrt_status.PNG) - - The highlighted path in the graph indicates the stalls in the design. You can also look at the following **Tile Status** table to get status of each tile, stalled port, etc. +The highlighted path in the graph indicates the stalls in the design. You can also look at the following **Tile Status** table to get status of each tile, stalled port, etc. Clicking each stall highlights the corresponding path in the graph view. - * `Tile Status - Status column`: Shows the Tiles (24,0),(25,0) are in lock stall and the tile (25,1) is in stream stall. If there are no stalls, you can see the `Disabled/Done` state. - * `Tile Status - Stalled Net/Port`: Shows the corresponding Nets/Ports where the stall happened. Observe the small bubble at the stream port of the peak_detect kernel in the graph view. - * `Tile Status - PC`: Shows the current Program Counter value. It can be crossprobed with the compiler generated source code by clicking on it. - * `DMA Status`: Shows each tile's DMA input/output channel status. + * `Tile Status - Status column`: Shows the Tiles (24,0),(25,0) are in lock stall and the tile (25,1) is in stream stall. If there are no stalls, you can see the `Disabled/Done` state. + * `Tile Status - Stalled Net/Port`: Shows the corresponding Nets/Ports where the stall happened. Observe the small bubble at the stream port of the peak_detect kernel in the graph view. + * `Tile Status - PC`: Shows the current Program Counter value. It can be crossprobed with the compiler generated source code by clicking on it. + * `DMA Status`: Shows each tile's DMA input/output channel status. - For more information, refer to [Analyzing AI Engine Status in Vitis Analyzer](https://docs.xilinx.com/r/en-US/ug1076-ai-engine-environment/Analyzing-AI-Engine-Status-in-Vitis-Analyzer) in *AI Engine Tools and Flows User Guide* (UG1076). + For more information, refer to [Analyzing AI Engine Status in Vitis Analyzer](https://docs.xilinx.com/r/en-US/ug1076-ai-engine-environment/Analyzing-AI-Engine-Status-in-Vitis-Analyzer) in the *AI Engine Tools and Flows User Guide* (UG1076). -### Manual AI Engine status Using the XBUtil Utility +### Manual AI Engine Status Using the XBUtil Utility >**NOTE:** This is of user interest to exercise different methodologies to detect the AI Engine status. If you have already exercised the `AI Engine status using XRT` step, you need to reboot the VCK190 board. @@ -189,11 +185,10 @@ Clicking each stall highlights the corresponding path in the graph view. * `-f`: Specifies the report format. * `-o`: Specifies the output file to direct the output. - For more information, refer to [xbutil Examine](https://xilinx.github.io/XRT/master/html/xbutil.html#xbutil-examine). - + For more information, refer to [xbutil Examine](https://xilinx.github.io/XRT/master/html/xbutil.html#xbutil-examine). 4. Copy the `JSON` to a local workspace for further analysis, open the file in the Vitis Analyzer using the option **Import XSDB/XBUtil JSON output**, and point to the `JSON`, AI Engine compile summary. 5. A new file, `aiestatus.run_summary`, gets created which can be used for further analysis. -6. The analysis in the Vitis Analyzer is similar to *AI Engine status using XRT*. +6. The analysis in the Vitis Analyzer is similar to *AI Engine Status Using XRT*. ### Deadlock Detection Using XSDB @@ -201,7 +196,6 @@ It is also possible to examine the status of the AI Engine using XSDB both on Li 1. Run the hardware server from the computer that connects to the target board. To do so, launch the hw_server from the computer that has a JTAG connection to the VCK190 board. ![launch hw server](./Images/launch_hwServer.PNG) - 2. Go to the directory where the AI Engine compile `Work/directory` was generated, and launch XSDB. 3. From the XSDB terminal, issue the following commands from the XSDB prompt: @@ -218,7 +212,7 @@ It is also possible to examine the status of the AI Engine using XSDB both on Li ``` aiestatus examine -work-dir ./Work -graphs mygraph ``` - + The output of the command is as follows: ``` @@ -229,9 +223,9 @@ It is also possible to examine the status of the AI Engine using XSDB both on Li 5. A new `JSON` file, `aie_status_.json`, gets created in the current working directory. Open the file in the Vitis Analyzer using the option, **Import XSDB/XBUtil JSON output**, point to the `JSON`, AI Engine compile summary, and output the `aiestatus.run_summary` file. - The analysis in the Vitis Analyzer is similar to *AI Engine Status Using XRT*. + The analysis in the Vitis Analyzer is similar to *AI Engine Status Using XRT*. - Revert back all the changes in the source code to exercise other features in this tutorial. + Revert back all the changes in the source code to exercise other features in this tutorial. ## Error Handling and Reporting in the Host Application @@ -241,7 +235,7 @@ XRT provides an `xrt::error` class and its member functions to retrieve the asyn To better understand the usage of error handling XRT APIs, an out of bound access in the kernel code is introduced which in turn causes issue executing the AI Engine graph controlled from the host code. -1. Add a memory read violation to the kernel code by opening `cmd_src/aie/kernels/peak_detect.cc`, and change the line 26 to v_in = *(InIter+8500000500). +1. Add a memory read violation to the kernel code by opening `cmd_src/aie/kernels/peak_detect.cc`, and change line 26 to v_in = *(InIter+8500000500). 2. Replace the `cmd_src/sw/host.cpp` file with the `Hardware/host_xrtErrorAPI.cpp`. Make sure to take the back up of the original file. 3. Observe lines 87-93. @@ -249,7 +243,7 @@ To better understand the usage of error handling XRT APIs, an out of bound acces * get_error_code() -> Member function to get the timestamp of the last error. * to_string() -> Member function to get the description string of a given error code. -4. Do `make all TARGET=hw` to build the AI Engine kernels, s2mm and mm2s, host application, link, and package steps to generate the SD card image. +4. Do `make all TARGET=hw` to build the AI Engine kernels, `s2mm` and `mm2s`, the host application, link, and package steps to generate the SD card image. 5. Repeat the steps 3 and 4 from [Running the Design on Hardware](./Stage_1.md#Running-the-design-on-hardware) to run design on hardware. 6. Observe the output from the Linux console. ![xrt error api output](./Images/xrtErrorAPI_output.PNG) @@ -259,7 +253,6 @@ To better understand the usage of error handling XRT APIs, an out of bound acces ``` * Above is the error propogated from the AI Engine array and is used to debug the application specific errors. For the list of error events, refer to the topic [AI Engine Error Events](https://docs.xilinx.com/r/en-US/ug1076-ai-engine-environment/AI-Engine-Error-Events). Notice the `error event 60` above which represents the **DM address out of range**, and the address out of range is happening in `col 25 row 1`. - * You can open the graph compile summary in Vitis Analyzer and identify the kernel corresponding to the tile which is `peak_detect` in this case. * You can debug this out of bound access at AI Engine simulation level - Refer to [Debugging memory access violations](../AIE_Simulation/README.md#Debugging-memory-access-violations) for more information. @@ -283,25 +276,21 @@ To better understand the usage of error handling XRT APIs, an out of bound acces It is also possible to report an error using `xbutil`. The error report accumulates all the errors from the various classes and sorts them by timestamp. -1. Issue the command, `xbutil examine -r error -d 0`, in the hardware Linux console, and observe the error report as follows. +1. In the hardware Linux console, issue the command, `xbutil examine -r error -d 0`, and observe the error report as follows. ![xbutil examine output](./Images/xbutilExamine_output.PNG) - - A similar description follows for the output, as explained in XRT error handling APIs. - + A similar description follows for the output, as explained in XRT error handling APIs. 2. Revert back all the changes in source code to exercise other features in this tutorial. ## Using APIs in the Host Application -In this topic, you will walk through using the APIs in the host code to profile the design to get some performance parameters. For more information on different performance metrics and details about the host APIs, refer to [Event Profile APIs for Graph Inputs and Outputs](https://docs.xilinx.com/r/en-US/ug1076-ai-engine-environment/Event-Profile-APIs-for-Graph-Inputs-and-Outputs) in ** (UG1076).AI Engine Tools and Flows User Guide +In this topic, you will walk through using the APIs in the host code to profile the design to get some performance parameters. For more information on different performance metrics and details about the host APIs, refer to [Event Profile APIs for Graph Inputs and Outputs](https://docs.xilinx.com/r/en-US/ug1076-ai-engine-environment/Event-Profile-APIs-for-Graph-Inputs-and-Outputs) in the *AI Engine Tools and Flows User Guide* (UG1076). ### Profiling Graph Throughput It can be defined as the average number of bytes produced (or consumed) per second: 1. To profile the design and calculate the port throughput, you should add the APIs in the host code. - 2. The code changes to profile the design for port throughput calculation are available in `Hardware/src/host_PortTP.cpp`. You can either do changes in `sw/host.cpp` manually by referring to `Hardware/src/host_PortTP.cpp`, or replace the `sw/host.cpp`. Make sure to take the backup of the file before replacing. - 3. In the `Hardware/src/host_PortTP.cpp`, the changes to profile the design are summarized as follows: a. Notice in the `host.cpp`, it contains only Native XRT APIs and no ADF APIs are used. For example, a graph handle is created using the `uuid` of `xclbin` and extracted the graph details using the `xrt::graph` API. @@ -310,7 +299,7 @@ It can be defined as the average number of bytes produced (or consumed) per seco auto cghdl = xrt::graph(device,xclbin_uuid,"mygraph"); ``` - b. Also note the graph run and end commands uses graph handle. + b. Also note the graph run and end commands uses graph handle. ``` cghdl.run(NIterations); @@ -342,23 +331,23 @@ It can be defined as the average number of bytes produced (or consumed) per seco std::cout<<"Throughput of the graph: "<**NOTE:** The throughput value you got above matches with the value you got during [AIE Simulation](../AIE_Simulation/README.md#Calculating-Graph-throughput-using-Graph-output) and [Hardware Emulation](../HW_Emulation/README.md#Calculating-Graph-throughput-using-Graph-output). ### Exercise Step diff --git a/AI_Engine_Development/AIE/Feature_Tutorials/09-debug-walkthrough/Hardware/Stage_2.md b/AI_Engine_Development/AIE/Feature_Tutorials/09-debug-walkthrough/Hardware/Stage_2.md index de8702d042..46fc540489 100644 --- a/AI_Engine_Development/AIE/Feature_Tutorials/09-debug-walkthrough/Hardware/Stage_2.md +++ b/AI_Engine_Development/AIE/Feature_Tutorials/09-debug-walkthrough/Hardware/Stage_2.md @@ -20,9 +20,9 @@ In this stage, you can profile the AI Engine Core, Interface, and Memory modules Hardware Profiling Feature - XRT Flow -Explains how to set up configuration file `xrt.ini` and run the hardware design to generate profile data using the XRT flow.
-      * Open multiple profile runs in Vitis Analyzer - This exercise helps you understand how to open different profile summaries (two different runs) in a single Vitis Analyzer view.
-      * Profiling Data Explanation - This explains how to analyze AI Engine core, memory, and interface profiling data. Also discusses what action should be taken based on the stall time and DMA lock time.
+Explains how to set up the configuration file `xrt.ini` and run the hardware design to generate profile data using the XRT flow.
+      - Open multiple profile runs in the AMD Vitis™ Analyzer - This exercise helps you understand how to open different profile summaries (two different runs) in a single Vitis Analyzer view.
+      - Profiling Data Explanation - This explains how to analyze the AI Engine core, memory, and interface profiling data. Also discusses what action should be taken based on the stall time and DMA lock time.
@@ -31,7 +31,7 @@ Explains how to set up configuration file `xrt.ini` and run the hardware design Hardware Profiling Feature - XSDB Flow -This method explains how to use XSDB-based flow to profile for both baremetal and Linux operating systems.
+This method explains how to use the XSDB-based flow to profile for both baremetal and Linux operating systems.
@@ -40,7 +40,7 @@ This method explains how to use XSDB-based flow to profile for both baremetal an It is expected that you already generated the hardware image from Stage 1. If not, follow the steps 1-3 from [Stage 1: Running the Design on Hardware](../Stage_1.md#Running-the-design-on-hardware). -## Hardware profiing features +## Hardware Profiing Features In this tutorial, you will learn how to use hardware profiling features to inspect the design. Two flows, XSDB and XRT flow, are supported to profile the AI Engine design. The profiling feature requires no design source code change to collect profiling data. No special options are required to build the design. @@ -63,7 +63,7 @@ In this tutorial, you will learn how to use hardware profiling features to inspe ``` For more information on these profile settings, refer to the *AI Engine Tools and Flows User Guide* ([UG1076](https://docs.xilinx.com/r/en-US/ug1076-ai-engine-environment/XRT-Flow)). -2. Save the `xrt.ini` file and it is safe to do power-cycle on the device, whenever you add/edit the `xrt.ini` file to avoid seeing any abnormal results: +2. Save the `xrt.ini` file, and it is safe to do power-cycle on the device, whenever you add/edit the `xrt.ini` file to avoid seeing any abnormal results: ``` cd /run/media/mmcblk0p1 @@ -82,12 +82,12 @@ In this tutorial, you will learn how to use hardware profiling features to inspe 6. Observe the following metrics for Tile (24,0): - * AIE TILE HEAT MAP : ACTIVE TIME = 0.003ms - * AIE TILE HEAT MAP : STALL TIME = 0.002ms - * AIE TILE HEAT MAP : VECTOR INSTRS = 112 - * AIE TILE HEAT MAP : ACTIVE UTILIZATION TIME = 0.003ms + * AIE TILE HEAT MAP: ACTIVE TIME = 0.003 ms + * AIE TILE HEAT MAP: STALL TIME = 0.00 2ms + * AIE TILE HEAT MAP: VECTOR INSTRS = 112 + * AIE TILE HEAT MAP: ACTIVE UTILIZATION TIME = 0.003 ms - Similarly for AIE MEMORY CONFLICTS and other Tiles, you can hover you mouse on the parameter(Say, `ACTIVE TIME(MS)` to get more details. + Similarly for AIE MEMORY CONFLICTS and other tiles, you can hover you mouse on the parameter(Say, `ACTIVE TIME(MS)`) to get more details. 7. Click **Interface Channels**. ![interface input](./Images/Interface_InputBW.PNG) @@ -121,7 +121,7 @@ In this section, try to use a different set of metrics in the `xrt.ini` file and 5. Add the second profile run summary file to the existing `run_summary` file using the `+` option as shown below. Observe the combined metrics of first run with the `heat_map`, `conflicts`, and `input_throughputs` metrics and the second run with `execution`, `dma_locks`, and `output_bandwidth` metrics in the Vitis Analyzer. ![multiple view](./Images/multiple_view.PNG) -6. Click on **%** to toggle between the absolute and percentage values of the collected design metrics. +6. Click **%** to toggle between the absolute and percentage values of the collected design metrics. 7. Click the column header to sort the data within those rows. Click once to display the selected row data in ascending order. Click twice to display the selected row data in descending order. Click three times to disable the sorting function. ### Profiling Data Explanation @@ -131,7 +131,7 @@ An easy way to know the definition of profile data category by moving the cursor #### AI Engine Core Profiling Data** * `Active Time (ms)` = `Stall Time (ms)` + `Active Utilization Time (ms)`. -* Take tile(25,0) as an example, tile(25,0) is active for a period of 0.003 ms, where 0.000 ms is stalled(=> Not stalled), and 0.003 ms is actively executing instructions. During the 0.003 ms active period, 0.001 milliseconds is executing vector instructions. There are 0.002 milliseconds spent on other instructions, such as load/store instructions. +* Take tile(25,0) as an example; tile(25,0) is active for a period of 0.003 ms, where 0.000 ms is stalled(=> Not stalled), and 0.003 ms is actively executing instructions. During the 0.003 ms active period, 0.001 milliseconds is executing vector instructions. There are 0.002 milliseconds spent on other instructions, such as load/store instructions. * There are a total of 672 Vector instructions, 264 Load Instructions, and 282 Store Instructions during the Active Utilization Time (ms). #### AI Engine Memory Profiling Data @@ -154,11 +154,10 @@ From **Profile_summary** -> **Interface Channels**, notice the interface tile th ### XSDB Flow It is also possible to profile the AI Engine using XSDB both on Linux and baremetal operating systems. -1. Program the device using the sd_card image, and remove any `xrt.ini` files in the sd_card to avoid any collision with XSDB commands. -2. Target connection setup - Run the hardware server from computer that connects to the target board. To do so, launch the hw_server from the computer that has the JTAG connection to the VCK190 board. +1. Program the device using the sd_card image, and remove any `xrt.ini` files in the sd_card to avoid any collision with XSDB commands. +2. Complete the target connection setup. Run the hardware server from computer that connects to the target board. To do so, launch the hw_server from the computer that has the JTAG connection to the VCK190 board. ![launch hardware server](./Images/launch_hwServer.PNG) - 3. Go to the directory where the AI Engine compile `Work/directory` is present and launch XSDB. 4. From the XSDB terminal, issue the following commands from the XSDB prompt: @@ -172,7 +171,7 @@ It is also possible to profile the AI Engine using XSDB both on Linux and bareme ``` 5. After the above `aieprofile` command is run, wait until Count: 10, Count: 20, ... is displayed from the XSDB console. This indicates XSDB is ready to collect design profiling data. -6. Switch to the Linux console of hardware and run the application: +6. Switch to the Linux console of hardware, and run the application: ``` cd /run/media/mmcblk0p1 @@ -182,14 +181,12 @@ It is also possible to profile the AI Engine using XSDB both on Linux and bareme 7. Inspect the generated files, `aie_profile.csv`, `summary.csv`, and `aie_trace_profile.run_summary` in your local workspace where XSDB is launched. 8. Open the `aie_trace_profile.run_summary` file in the Vitis Analyzer and expect to see the following result: ![xsdb profile](./Images/xsdb_profile.PNG) - A similar profile data analysis is applicable for the XSDB-generated profile summary as explained in the XRT flow. ## Support GitHub issues will be used for tracking requests and bugs. For questions, go to [support.xilinx.com](https://support.xilinx.com/). -

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diff --git a/AI_Engine_Development/AIE/Feature_Tutorials/09-debug-walkthrough/Hardware/Stage_3.md b/AI_Engine_Development/AIE/Feature_Tutorials/09-debug-walkthrough/Hardware/Stage_3.md index caf0996caa..99c5545c88 100644 --- a/AI_Engine_Development/AIE/Feature_Tutorials/09-debug-walkthrough/Hardware/Stage_3.md +++ b/AI_Engine_Development/AIE/Feature_Tutorials/09-debug-walkthrough/Hardware/Stage_3.md @@ -47,7 +47,7 @@ This is a three step process: * Add the PL profile monitors in the V++ link command, and generate the SD card image. * Prepare the `xrt.ini` file, and run the design on hardware. -* Observe the output in the Vitis Analyzer, and analyze the performance. +* Observe the output in the AMD Vitis™ Analyzer, and analyze the performance. 1. Open the `Makefile` from `cmd_src/` directory. 2. Locate the `VPP_LINK_FLAGS`, and add `--profile.data all:all:all` as follows: @@ -56,12 +56,9 @@ This is a three step process: VPP_LINK_FLAGS := -l -t $(TARGET) --platform $(BASE_PLATFORM) $(KERNEL_XO) $(GRAPH_O) --profile.data all:all:all --save-temps -g --config $(CONFIG_FILE) -o $(PFM).xsa ``` - The `--profile.data:` option enables the monitoring of data ports through the monitor IP that are added into the design. In this example, `` is set to `all:all:all`, i.e, assign the data profile to all CUs; *you can find names from `system.cfg` file as `s2mm_1`,`s2mm_2` and `mm2s`* and interfaces of all kernels, *s2mm and mm2s*. - + The `--profile.data:` option enables the monitoring of data ports through the monitor IP that are added into the design. In this example, `` is set to `all:all:all`, i.e, assign the data profile to all CUs; you can find the names from the `system.cfg` file as `s2mm_1`,`s2mm_2` and `mm2s`* and interfaces of all kernels, `s2mm` and `mm2s`. 3. Do `make all TARGET=hw`, and a hardware image `sd_card.img` gets generated inside the `sw/` directory. - 4. Flash the `sd_card.img` file to the SD card. You can follow step 3 in [Running the Design on Hardware](../Stage-1#Running-the-design-on-hardware) section. - 5. Create a `xrt.ini` file with content as follows: ``` @@ -94,10 +91,8 @@ This is a three step process: 8. Once the Vitis Analyzer opens, click the `Profile Summary` in the left side pane, and navigate to the **Compute Unit Utilization**. Observe the compute units and kernels. Also note the time and clock frequency as follows. ![CU Utilization](./Images/cu_utilization.PNG) - 9. You can get the data transfer for each compute unit and total Read/write in megabytes by navigating to **Kernel Data Transfers** -> **Top Kernel Transfer** as follows: ![Top kernel transfer](./Images/top_kernel_transfer.PNG) - 10. From the **Kernel Data Transfers** -> **Kernel Transfer** tab, you can get the transfer rate, througput utilization (%), and latency details. ## Inserting ILAs to Monitor Specific AXI Interfaces @@ -116,11 +111,9 @@ The v++ `--debug` opiton is used to enable the ILA IP core and insert in the des Notice here the `s2mm_1:s`,`s2mm_2:s`, and `mm2s:s`. The syntax is `:`. - Make sure the compute unit name matches with the one specified in the `system.cfg` file. In this exercise, monitor the stream _output from `mm2s` module going to theAI Engine, going to `s2mm` module_. - + Make sure the compute unit name matches with the one specified in the `system.cfg` file. In this exercise, monitor the stream _output from `mm2s` module going to the AI Engine, going to `s2mm` module_. >**NOTE:** V++ allows multiple `--debug.chipscope` lines to meet design debug needs. - -2. Build the design. Especially, if you have already compiled the AI Engine design and PL modules, it is required to run the linking step in the `Makefile` and repackage to generate the SD card image. +2. Build the design. Especially, if you have already compiled the AI Engine design and PL modules; it is required to run the linking step in the `Makefile` and repackage to generate the SD card image. ``` make clean @@ -141,7 +134,6 @@ The v++ `--debug` opiton is used to enable the ILA IP core and insert in the des 1. Run the hardware server from the computer that connects to the target board. To do so, launch the hardware server from the computer that has a JTAG connection to the VCK190 board. ![hardware server](./Images/launch_hwServer.PNG) - 2. Launch Vivado by issuing the command, `vivado`. 3. Set up the Vivado Hardware Manager by clicking **Flow** -> **Hardware Manager**, and click **Open target**. 4. Select **Open New Target**, and click **Next**. @@ -149,7 +141,7 @@ The v++ `--debug` opiton is used to enable the ILA IP core and insert in the des 6. After a successful connection to your host, you can verify the hardware devices `arm_dap_0`,`xcvc1902_1`, and click **Next**. 7. Click **Finish**. 8. Under the **Hardware Device Properties** window, click the ellipsis (...) to select the generated probe file from `${PROJECT_PATH}/tutorial.ltx`. -9. After the hardware device got refreshed, you can observe the following messages in the Tcl console: +9. After the hardware device got refreshed, you can observe the following messages in the Tcl Console: ``` Processed interface mm2s_s_ila1_slot0 @@ -159,14 +151,11 @@ The v++ `--debug` opiton is used to enable the ILA IP core and insert in the des 10. Click the `hw_ila_1` as follows: ![hw_ila_1](./Images/hw_ila_1.PNG) - 11. Select the `+` button from the **Trigger Setup - hw_ila_1** window, and select the `TVALID` signal probes, and click **OK**. ![add probes](./Images/add_probes.PNG) - 12. Once the probes are added, select `1 (logical one)` from the dropdown in the `Value` column for all three probes. This is required to capture the signals when `TVALID` is high. 13. Observe the **Core status** as `IDLE` in the **Settings-hw_ila_1** window. Now, select the `>(Play)` button at the top to capture the configured signals, and observe the status changes to `Waiting for Trigger` as follows: ![ILA status](./Images/ILA_status.PNG) - 14. Wait for the ILA to be ready to capture signals, and run the application on the `VCK190` board. ``` @@ -184,8 +173,7 @@ The v++ `--debug` opiton is used to enable the ILA IP core and insert in the des 1. Expand the `slot_0 : mm2s_s : Interface`. The `mm2s_s : TVALID` shows `1`, which indicates a valid data is available at the time marker pointed. Moving the time marker across the timeline, changes the AXI protocol values indicating value changes at that particular time. This is the method to determine when/what valid data is sent/received. - - >**NOTE:** The default buffer size allocated while creating a BD design in Vivado might not be sufficient enough to capture the data of all iterations. For more information on viewing ILA probe data, refer to the [Viewing ILA Probe Data in the Waveform Viewer](https://docs.xilinx.com/r/en-US/ug908-vivado-programming-debugging/Viewing-ILA-Probe-Data-in-the-Waveform-Viewer) in *Vivado Design Suite User Guide: Programming and Debugging* (UG908). + >**NOTE:** The default buffer size allocated while creating a BD design in Vivado might not be sufficient enough to capture the data of all iterations. For more information on viewing ILA probe data, refer to the [Viewing ILA Probe Data in the Waveform Viewer](https://docs.xilinx.com/r/en-US/ug908-vivado-programming-debugging/Viewing-ILA-Probe-Data-in-the-Waveform-Viewer) in the _Vivado Design Suite User Guide: Programming and Debugging_ (UG908). ## Support diff --git a/AI_Engine_Development/AIE/Feature_Tutorials/09-debug-walkthrough/Hardware/Stage_4.md b/AI_Engine_Development/AIE/Feature_Tutorials/09-debug-walkthrough/Hardware/Stage_4.md index f17c43ed03..a5b3b5b431 100644 --- a/AI_Engine_Development/AIE/Feature_Tutorials/09-debug-walkthrough/Hardware/Stage_4.md +++ b/AI_Engine_Development/AIE/Feature_Tutorials/09-debug-walkthrough/Hardware/Stage_4.md @@ -11,9 +11,9 @@ This stage helps you determine the AI Engine kernel or graph construct causing design performance drop or stall or causing a deadlock by: - * Running and analyzing runtime trace data using the AI Engine Event trace flow. - * Profiling Intra-kernel performance. - * Using the AMD Vitis™ IDE debugger to debug kernel source code. +* Running and analyzing runtime trace data using the AI Engine Event trace flow. +* Profiling Intra-kernel performance. +* Using the AMD Vitis™ IDE debugger to debug kernel source code. @@ -23,7 +23,7 @@ This stage helps you determine the AI Engine kernel or graph construct causing d @@ -32,30 +32,30 @@ Explains how to use the different event trace options for compiling and its sign Event Trace Analysis - XRT Flow - + - + @@ -75,7 +75,7 @@ This tutorial targets the event trace feature running on the hardware board that Before starting this tutorial: -* It is expected that you cloned the Git repository, and the design files are ready to build. +* It is expected that you cloned the git repository, and the design files are ready to build. * It is expected that you have run the steps to set the environment variables as described in [Introduction](../README.md#Introduction). ### Build the Design @@ -150,28 +150,25 @@ After the design is built, you are ready to run on the hardware board. 1. Open the Vitis Analyzer using the `vitis_analyzer xrt.run_summary` command. 2. It is required to set the design's compile summary file when you run the Vitis Analyzer for first time on the design. 3. Select **Trace** from the left pane of the Vitis Analyzer. Initially, details of the event are not shown. -![initial trace](./Images/Initial_trace.PNG) - + ![initial trace](./Images/Initial_trace.PNG) 4. Zoom in to see the detailed information for each state of the AI Engine tiles. -![trace zoom view](./Images/Trace_zoomView.PNG) + ![trace zoom view](./Images/Trace_zoomView.PNG) #### Details of the Event Trace Data 1. Select the `Graph` view to examine the design. Select `p_d` to identify the tile as (25,0). -![graph view trace](./Images/graph_view_trace.PNG) - + ![graph view trace](./Images/graph_view_trace.PNG) 2. Adjust the trace view to the correct size with the zoom in or zoom out icons, and move the marker to the end of `peak_detect` or the beginning of `_main`. This is considered as the beginning of an iteration. A period of lock stall indicates data is sent from the PL to AIE tile. -![adjusted trace view](./Images/adjusted_trace_view.PNG) - + ![adjusted trace view](./Images/adjusted_trace_view.PNG) 3. Observe the end of the `peak_detect` kernel corresponding to the core(25,0) and start of the core(24,0) and core(25,1). If you observe the graph view, you can notice that the kernel `peak_detect` sends data to both the `upscale` and `data_shuffle` kernels. The same behavior can be observed in the trace view as well. -4. You can calculate the execution time of one iteration as follows. Place the marker at start and end of the iteration and (1) - (2) gives 262.2 ns which is ~= 329 cycles. This matches with the `Function time` in the profile data from both the AI Engine simulation and hardware emulation. -![iteration time](./Images/iteration_time.PNG) +4. You can calculate the execution time of one iteration as follows. Place the marker at the start and end of the iteration and (1) - (2) gives 262.2 ns which is ~= 329 cycles. This matches with the `Function time` in the profile data from both the AI Engine simulation and hardware emulation. + ![iteration time](./Images/iteration_time.PNG) ### XSDB Flow 1. Program the device using the sd_card image, and remove any `xrt.ini` files in the sd_card to avoid misbehavior with the XSDB commands. -2. _Target connection setup_: Run the hardware server from the computer that connects to the target board. To do so, launch the hardware server from the computer that has a JTAG connection to the VCK190 board. -![launch hardware server](./Images/launch_hwServer.PNG) +2. *Target connection setup*: Run the hardware server from the computer that connects to the target board. To do so, launch the hardware server from the computer that has a JTAG connection to the VCK190 board. + ![launch hardware server](./Images/launch_hwServer.PNG) 3. Go to the directory where the AI Engine compile `Work/directory` is present, and launch XSDB. 4. From the XSDB terminal, issue the following commands from the XSDB prompt: @@ -186,7 +183,6 @@ After the design is built, you are ready to run on the hardware board. * `-base-address 0x900000000` is the address that needs to avoid collision with your design. * `-depth 0x8000000` is the size of the event trace file. Adjust accordingly with your design size and amount of the event trace data. - 5. After the above `aietrace` start command is run, switch to the hardware Linux console, and run the application. ``` @@ -225,7 +221,7 @@ Based on the design, select GMIO if the design has limited PL resources left for #### Event Trace Limitations -1. Due to limited resources, overruns can be seen from the event trace. Follow [Number of Event Trace Streams Methodology](#Number-of-Event-Trace-Streams-Methodology) to configure the number of trace streams to minimize the overruns issue. +1. Due to limited resources, overruns can be seen from the event trace. Follow [Number of Event Trace Streams Methodology](#number-of-event-trace-streams-methodology) to configure the number of trace streams to minimize the overruns issue. 2. It is required that the `--broadcast-enable-core` option is used to compile the design. This is to eliminate time sync issues where the start time of each tile is off by ~100 ns or more. 3. Run forever applications are supported by the XSDB flow only. @@ -233,16 +229,13 @@ Based on the design, select GMIO if the design has limited PL resources left for This section uses the system project built using the Vitis IDE and launch the IDE debugger to debug the host code and AI Engine kernel source code. Unlike debugging at simulation level, this topic walks you through connecting the harware to the IDE debugger, placing breakpoints in the host code and kernel source code, and observing intermittent values in the Varibale view, register view, and memory inspector. -1. Download the Vitis IDE project from [Download the Vitis IDE project](../README.md#Download-Vitis-IDE-project) and import in Vitis IDE. - +1. Download the Vitis IDE project from [Download the Vitis IDE project](../README.md#Download-Vitis-IDE-project) and import into the Vitis IDE. 2. Invoke the Vitis IDE, and select **File** -> **Import** -> **Vitis project exported zip file**. -3. Browse to the `PeakDetect.ide.zip`, enable the **System Projects** checkbox , and click **Finish**. +3. Browse to the `PeakDetect.ide.zip`, enable the **System Projects** checkbox, and click **Finish**. 4. Click the arrow button next to the **Manage configurations to the current project** icon in the taskbar, and select **Hardware**. 5. Right-click the **PeakDetect_system**, and select the **Build Project**. It takes 20-25 minutes to completely build for the hardware target. 6. Prepare the target hardware by flashing the `sd_card.img` on to the VCK190. (Refer to the following note). - >**NOTE:** The `sd_card.img` at the `{Project}/Hardware/package` directory is for regular use, and the `sd_card.img` at the `{Project}/Hardware/package_aie_debug` directory is for the debug run on the board. - 7. Plug in the sd_card into the SD card slot, and power up the board. 8. Once the boot completes, type `ifconfig` in the hardware console. This is required to set up the Linux TCF agent to connect with the host. @@ -278,43 +271,38 @@ This section uses the system project built using the Vitis IDE and launch the ID >**NOTE:** It is required to connect the VCK190 board to the Ethernet cable to get the ethernet address. -9. Set up the connnection to the target hardware board. - * Run the hardware server from the computer that connects to the target board. To do so, launch the hw_server from the computer that has the JTAG connection to the VCK190 board. - ![launch hardware server](./Images/launch_hwServer.PNG) - * Create the debug target connection from the Vitis IDE by right-clicking the **PeakDetect_system**, and select the **Debug** -> **Debug configuraions**. - * Under the **Main** tab -> **Target** section -> **Hardware server** option -> **Local target** -> **New** as follows. - ![target hardware setup](./Images/target_hwsetup.PNG) - * In the **Target Connection Details** window, enter the **Target name** and **Host**. The Host name should match with what you see in the launch hardware server window, and hit **Test Connection**. - * You should see the following **Connection Successful!** message: - ![connection successful](./Images/connection_successful.PNG) - - * You can also click the **>>Advanced** button to view the details of the VCK190 as follows. - ![advanced options](./Images/advanced_option.PNG) -10. Similarly, set up the Linux TCF Agent. Under the **Main** tab -> **Target** section -> **Linux TCF Agent** option, select **New** and enter the **Target** and **Host** details. Enter the `inet addr` address you see after issuing the `ifconfig` command in the hardware Linux console in the **Host** field. Click **Test Connection**. You see **Connection Successful** message as shown above. - +9. Set up the connection to the target hardware board. + + * Run the hardware server from the computer that connects to the target board. To do so, launch the hw_server from the computer that has the JTAG connection to the VCK190 board. + ![launch hardware server](./Images/launch_hwServer.PNG) + * Create the debug target connection from the Vitis IDE by right-clicking the **PeakDetect_system**, and select the **Debug** -> **Debug configuraions**. + * Under the **Main** tab -> **Target** section -> **Hardware server** option -> **Local target** -> **New** as follows. + ![target hardware setup](./Images/target_hwsetup.PNG) + * In the **Target Connection Details** window, enter the **Target name** and **Host**. The Host name should match with what you see in the launch hardware server window, and hit **Test Connection**. + * You should see the following **Connection Successful!** message: + ![connection successful](./Images/connection_successful.PNG) + * You can also click the **>>Advanced** button to view the details of the VCK190 as follows. + ![advanced options](./Images/advanced_option.PNG) +10. Similarly, set up the Linux TCF Agent. Under the **Main** tab -> **Target** section -> **Linux TCF Agent** option, select **New**, and enter the **Target** and **Host** details. Enter the `inet addr` address you see after issuing the `ifconfig` command in the hardware Linux console in the **Host** field. Click **Test Connection**. You see **Connection Successful** message as shown above. 11. Now, in the Vitis IDE, right-click the **PeakDetect_system**, and select the **Debug As** -> **Launch Hardware**. 12. The Vitis IDE switches automatically to the debug mode, and the debugger suspends the host application at an automatic breakpoint in the `host.cpp` as follows. -![host debug](./Images/host_debug.PNG) - -13. NPlace a breakpoint at line 38 in the `host.cpp`, and click **resume**. Observe the following values of different variables in the **Variables view**: -![host variables](./Images/host_variables.PNG) - - This way you can debug the host code. - + ![host debug](./Images/host_debug.PNG) +13. Place a breakpoint at line 38 in the `host.cpp`, and click **resume**. Observe the following values of diferent variables in the **Variables view**. This way you can debug the host code. + ![host variables](./Images/host_variables.PNG) 14. You can also debug the AI Engine cores by placing the breakpoints in the kernel source code. Open the `src/kernels/peak_detect.cc` kernel, and place a breakpoint at line 33. Click the **resume** button, and observe the following values in the register view and variable view. 15. You can hover your mouse over variables in the editor window and get the memory address. Add that address in the memory inspector, and observe the corresponding values. For more details, refer to the [Debug Using Vitis IDE debugger](../AIE_Simulation/README.md#Debug-using-Vitis-IDE-debugger). -![debug hardware view](./Images/debug_HardwareView.PNG) + ![debug hardware view](./Images/debug_HardwareView.PNG) 16. You can select each individual core in the AI Engine and debug using the 'step-in','step-over' options, or remove all breakpoints, select the **PeakDetect**, and click the **resume** button to run all the cores. When all cores are completed, you can see status as **Disabled** for all the cores. -![debug stack](./Images/debug_stack.PNG) -17. When the application run completes in hardware, you can observe the following **TEST PASSED** in the console . -![serial terminal passed](./Images/serial_TerminalPassed.PNG) + ![debug stack](./Images/debug_stack.PNG) +17. When the application run completes in hardware, you can observe the following **TEST PASSED** in the console. + ![serial terminal passed](./Images/serial_TerminalPassed.PNG) ### Limitations of the Source Code Debug on Hardware * There are maximum of four breakpoints available for each tile. One of these four breakpoints is assigned to first line of `main()` function by default and can be cleared and then assigned to other lines during debug. * Due to the compiler, the `-O0` option is not supported; non-sequential execution when stepping through the source code is expected. * If an individual kernel is highlighted, select the **resume** button to continue execution until the next breakpoint or blocked to wait for I/O. If the PeakDetect design is highlighted, select the **resume** button to resume all kernels execution until meet each kernel's breakpoint or blocked waiting for each kernel's I/O operation. -Due to compiler optimization, some variables' values are stored in registers. "N/A" is shown in the variables view for those optimized variables' values. + Due to compiler optimization, some variables' values are stored in registers. "N/A" is shown in the variables view for those optimized variables' values. * `printf()` is not supported in hardware debug. ## Support diff --git a/AI_Engine_Development/AIE/Feature_Tutorials/09-debug-walkthrough/README.md b/AI_Engine_Development/AIE/Feature_Tutorials/09-debug-walkthrough/README.md index 21a5215c31..2364019640 100644 --- a/AI_Engine_Development/AIE/Feature_Tutorials/09-debug-walkthrough/README.md +++ b/AI_Engine_Development/AIE/Feature_Tutorials/09-debug-walkthrough/README.md @@ -13,7 +13,7 @@ ## Introduction -The Vitis environment development methodology reflects the heterogeneous nature of AMD Versal™ adapative SoC systems, which typically consist of a processing system (PS), programmable logic (PL), and AI Engine (AIE) functionality. Using the Vitis tools, you can develop and verify these components independently and gradually integrate them to form the final system. +The AMD Vitis™ environment development methodology reflects the heterogeneous nature of AMD Versal™ adapative SoC systems, which typically consist of a processing system (PS), programmable logic (PL), and AI Engine (AIE) functionality. Using the Vitis tools, you can develop and verify these components independently and gradually integrate them to form the final system. ![development methodology](./Images/dev_methodology.PNG) @@ -28,9 +28,9 @@ Techniques to uncover both functional and performance level bugs are described i Source level debug includes visibility into the register contents view, variable values view, breakpoints view, and hence, necessitates a GUI. The Vitis integrated design environment (IDE) is the tool that supports these debug requirements. This tutorial demonstrates how to use the Vitis IDE to manage these challenges and additional tools and methodologies to assist with your design debug. ->**IMPORTANT**: Before beginning the tutorial, make sure you have installed the Vitis 2023.2 software. The Vitis release includes all the embedded base platforms including the VCK190 base platform that is used in this tutorial. In addition, ensure you have downloaded the Common Images for Embedded Vitis Platforms from this link: . +>**IMPORTANT**: Before beginning the tutorial, make sure you have installed the Vitis 2023.2 software. The Vitis release includes all the embedded base platforms including the VCK190 base platform that is used in this tutorial. Ensure you have downloaded the Common Images for Embedded Vitis Platforms from this link: . -The `common image` package contains a prebuilt Linux kernel and root file system that can be used with a Versal board for embedded design development using Vitis. Before starting this tutorial run the following steps: +The `common image` package contains a prebuilt Linux kernel and root file system that can be used with a Versal adaptive SoC board for embedded design development using Vitis. Before starting this tutorial, run the following steps: 1. Go to the directory where you have unzipped the Versal Common Image package. 2. In a Bash shell, run `/Common Images Dir/xilinx-versal-common-v2023.2/environment-setup-cortexa72-cortexa53-xilinx-linux script`. This script sets up the `SDKTARGETSYSROOT` and `CXX` variables. If the script is not present, you must run `/Common Images Dir/xilinx-versal-common-v2023.2/sdk.sh`. @@ -53,7 +53,7 @@ Use the design files from `/09-debug-walkthrough/cmd_src` and cre ## Methods -There are several ways to debug a system design that include the PS, PL, and AI Engine or an AI Engine only design. Each method has the intended goal to help debug practice. The following are some debug methodlogies that helps analyzing the design and take decisions to improve. +There are several ways to debug a system design that include the PS, PL, and AI Engine or an AI Engine only design. Each method has the intended goal to help debug practice. The following are debug methodologies that help with analyzing the design and making improvements. ## Debug Methodologies @@ -86,7 +86,7 @@ Demonstrates how to add the formatted `printf()` to print debug messages. Debug Using printf() with Vector Data Types @@ -116,7 +116,7 @@ Demonstrates how to use the x86simulator options file for debugging. Demonstrates how to use the data dump feature with a practical scenario. - + @@ -167,10 +167,10 @@ Demonstrates about debugging in command line using the GNU Debugger (GDB). x86simulation on the Command Line - + - + @@ -207,7 +207,7 @@ Demonstrates how to use Vitis IDE to build and simulate an AI Engine design. Debug Using printf @@ -216,7 +216,7 @@ Explains how to add a `printf() `statement, and view the output in the console. Debug Using the Vitis IDE Debugger @@ -296,7 +296,7 @@ Explains how to create a system project, build for sofware emulation, and run. - + - + - + - + - + - + - + - + - + - + - + - + @@ -449,10 +449,10 @@ Explains how to use different event trace options for compiling and its signific - + - + diff --git a/AI_Engine_Development/AIE/Feature_Tutorials/09-debug-walkthrough/X86_Simulation/README.md b/AI_Engine_Development/AIE/Feature_Tutorials/09-debug-walkthrough/X86_Simulation/README.md index 9a907d0bac..3db1691236 100644 --- a/AI_Engine_Development/AIE/Feature_Tutorials/09-debug-walkthrough/X86_Simulation/README.md +++ b/AI_Engine_Development/AIE/Feature_Tutorials/09-debug-walkthrough/X86_Simulation/README.md @@ -154,16 +154,16 @@ Demonstrates how to use a GDB server to debug the design. ## Build and Simulate in the Vitis IDE -1. Once the Vitis IDE is opened and the system project is created manually, select the **AI Engine Component** from the left-side pane, and expand to locate and select the `aiecompiler.cfg` file to open the compiler configuration settings. +1. Once the Vitis IDE is opened and the system project is created manually, select the **AI Engine Component** from the left-side pane, and expand to locate and select the `aiecompiler.cfg` file to open the compiler configuration settings. 2. Select the **Module-Specific** settings and click **Add item** under the **Pre-processor** setting. -![build settings](./Images/Build_setting.PNG) + ![build settings](./Images/Build_setting.PNG) 3. Add `-O0` to the Pre-processor option. This improves the debug visibility. 4. Now, in the **Flow** navigator window, select the **Build** option under **X86 SIMULATION**. This builds the AI Engine component for x86simulation target. Once the build completes, you see the **Compilation Complete** and **Build Finished Successfully** messages in the console. Also a green tick mark as highlighted below. -![build output](./Images/Build_output.PNG) -5. In the **Flow** navigator window, under **X86SIMULATION**, select the **Run** option. If there is no existing launch configuration, you need to create one by clicking on **Create Configuration** -> **New Launch Configuration** -> **x86sim**. -![Create_Configuration](./Images/create_configuration.PNG) + ![build output](./Images/Build_output.PNG) +5. In the **Flow** navigator window, under **X86SIMULATION**, select the **Run** option. If there is no existing launch configuration, you need to create one by clicking on **Create Configuration** -> **New Launch Configuration** -> **x86sim**. + ![Create_Configuration](./Images/create_configuration.PNG) 6. You can change the **Launch Config Name** and click **Run** button to start simulation for x86simulation target. When the simulation complete, you see the following output in the console. -![simulator output](./Images/x86simulator_output.PNG) + ![simulator output](./Images/x86simulator_output.PNG) # Section 2 @@ -175,10 +175,10 @@ This section talks about adding a `printf()` statement in the source code, compi 1. From the Vitis IDE, browse to the *[AI Engine]* component and expand **Sources** → **kernels** → **click** on `peak_detect.cc`. 2. Add `#include ` at the beginning of the source file and `printf("%s: %s, %d\n", __FUNCTION__, X86SIM_KERNEL_NAME, __LINE__);` after for the loop. -3. To compile the project, select the **Build** option under **X86 SIMULATION** in **FLOW** navigator. +3. To compile the project, select the **Build** option under **X86 SIMULATION** in **FLOW** navigator. 4. To run the project, select the **Run** option under **X86SIMULATION** in **Flow** navigator. 5. The expected result is as follows. -![printf support](./Images/printf_support.PNG) + ![printf support](./Images/printf_support.PNG) 6. Remove the added `printf` statement from the `peak_detect.cc` file to use it for other features. # Section 3 @@ -197,7 +197,7 @@ The x86simulator supports printing vector output data value via `printf()`. This 2. Recompile the project either by hitting the **build** option in the Flow navigator. 3. Run the x86simulation, and observe the following `printf` statements in the console. -![vector printf](./Images/vector_printf.PNG) + ![vector printf](./Images/vector_printf.PNG) 4. Remove the added `printf` statement from the `peak_detect.cc` file to use it for other features. # Section 4 @@ -210,16 +210,16 @@ This section walks you through a debug methodology that uses the Vitis IDE debug 2. This gets you to the debug mode in the Vitis IDE and waits in the `graph.cpp` file (after the *main()* function). 3. Open any source file from the Explorer window, and add the breakpoint of interest. For example, open the *peak_detect.cc* source file, and add the breakpoint at line (`vin = *InIter++`) after for loop. 4. Observe the different debug functionalities/controls available, that is, step-in, step-over, step-return, resume, terminate, disconnect, etc. -![debug controls](./Images/debug_controls.PNG) + ![debug controls](./Images/debug_controls.PNG) 5. Press **Resume** button in the toolbar. Observe the simulation stops at the user-defined breakpoint as follows. -![breakpoint](./Images/break_point.PNG) -6. You can inspect the array value `v_in` `(aie::vector)` from the Variables view. + ![breakpoint](./Images/break_point.PNG) +6. You can inspect the array value `v_in` `(aie::vector)` from the Variables view. -**Note** : You can drag the complete debug window from left-side pane down to the output console in the bottom pane and expand the Variables view to enlarge the area. You can restore it back to the original size by dragging back to the left-side. -![rearranging_debugMode](./Images/rearranging_debugMode.PNG) + **Note** : You can drag the complete debug window from left-side pane down to the output console in the bottom pane and expand the Variables view to enlarge the area. You can restore it back to the original size by dragging back to the left-side. + ![rearranging_debugMode](./Images/rearranging_debugMode.PNG) 7. Expand the variable, `v_in`, and continue expanding to `(Vin → data → val -> data -> __elems_ → __elems_[0] → val → VBitDataBase<32,true,false> → data → 0: 16)`. (Value-"16" based on the iteration in your case). -![variables view](./Images/variables_view.PNG) + ![variables view](./Images/variables_view.PNG) 8. You can either continue stepping for all iterations, or remove the breakpoint and hit the **Run** button in the taskbar. It completely runs the simulation for all iterations. Once you are done with debugging, you can switch back to **Vitis Component** view. # Section 5 @@ -320,7 +320,7 @@ This feature allows you to dump and inspect data traffic at kernel ports with da ``` -Observe that one text file per each port of each kernel is generated using the `--dump` feature and the filenames are in the format of `____[in]/[out]_index.txt` for graph input/output files. + Observe that one text file per each port of each kernel is generated using the `--dump` feature and the filenames are in the format of `____[in]/[out]_index.txt` for graph input/output files. 5. Open the `$(COMPONENT_NAME)/Output/x86sim/x86simulator_output/dump/mygraph_in_out_0.txt` file, and note the `Iteration` and `snapshot` values recorded in that file. This matches with the dimensions (buffer size) specified in the graph code per iteration. @@ -451,7 +451,7 @@ This is in continuation to the [Trace Report in the File](./README.md#Trace-Repo ``` Here you can notice that the output in the console is not as polished as the file generated by `--trace`. But this is useful when your design runs for long time, and you wish to see the event while the simulation is running. - + You may uncheck the **Trace print** option to exercise the other options. Also revert any changes to the source files. # Section 6 @@ -470,11 +470,11 @@ Memory access violations occur when a kernel is reading or writing out of bounds `x86simulator` requires `VALGRIND_HOME`, `VALGRIND_LIB`, and `PATH` environmental variables to be configured per your host computer configuration. Exit out of the Vitis IDE, and set up the following environmental variables and relaunch the Vitis IDE. For example: - ``` - export PATH=/valgrind/3.16.1/:$PATH - export VALGRIND_HOME=/valgrind/3.16.1/ - export VALGRIND_LIB=valgrind/3.16.1/lib/ - ``` +``` +export PATH=/valgrind/3.16.1/:$PATH +export VALGRIND_HOME=/valgrind/3.16.1/ +export VALGRIND_LIB=valgrind/3.16.1/lib/ +``` 1. After relaunching the Vitis IDE tool, either by enabling the **Valgrind** option in the launch configuration settings or by updating the configuration file, `$(COMPONENT_NAME)/Output/x86sim/Work/options/x86sim.options`. 2. Run x86simulation by selecting the **Run** option under **X86SIMULATION** in **Flow** navigator.. @@ -523,7 +523,7 @@ Memory access violations occur when a kernel is reading or writing out of bounds Valgrind points out the file that has out of bound read access with the line number as shown above. -### Exercise Step +### Section 6 Exercise Step 1. Add the following lines of code that creates an uninitialized variable in any kernel code and see how the Valgrind helps in identifying the issue: @@ -572,10 +572,10 @@ This topic walks you through running the x86simulator with the GDB. 2. After `x86simulator` is launched successfully with the GDB, set up a breakpoint using the `break` command. - ``` - (gdb) break data_shuffle - Breakpoint 2 at 0x410f47: file ./../.././aie/kernels/data_shuffle.cc, line 9. - ``` + ``` + (gdb) break data_shuffle + Breakpoint 2 at 0x410f47: file ./../.././aie/kernels/data_shuffle.cc, line 9. + ``` 3. Type `c` and continue execution until the breakpoint is hit. @@ -711,11 +711,11 @@ This feature uses the GDB server to debug and requires two terminals working tog ==44263== ERROR SUMMARY: 0 errors from 0 contexts (suppressed: 0 from 0) ``` -#### Exercise Step +#### Section 7 Exercise Step Insert an out-of-bound read access error as mentioned in [Memory Access Violation and Valgrind Support](./README.md#Memory-access-violation-and-valgrind-support), and perform the steps from (j)-(n). Observe the violation using the `--valgrind-gdb` command in Terminal 1. -## Support +### Support GitHub issues will be used for tracking requests and bugs. For questions, go to [support.xilinx.com](https://support.xilinx.com/). diff --git a/AI_Engine_Development/AIE/Feature_Tutorials/20-aiecompiler-features/ConditionalObjects/README.md b/AI_Engine_Development/AIE/Feature_Tutorials/20-aiecompiler-features/ConditionalObjects/README.md index 58bb44b646..ef70953e80 100755 --- a/AI_Engine_Development/AIE/Feature_Tutorials/20-aiecompiler-features/ConditionalObjects/README.md +++ b/AI_Engine_Development/AIE/Feature_Tutorials/20-aiecompiler-features/ConditionalObjects/README.md @@ -8,7 +8,7 @@
Explains how to use the different event trace options for compiling and its significance. Also walks through the steps to generate a hardware image.
-      * Prepare for hardware run +      - Prepare for hardware run
-Explains how to do an AI Engine event trace and analysis by setting up the configuration file `xrt.ini`, and run the hardware design to generate the trace data using the XRT flow.
-      * Launch Vitis Analyzer to Examine Event Trace Files
-      * Details of the Event Trace data
+Explains how to do an AI Engine event trace and analysis by setting up the configuration file, `xrt.ini`, and run the hardware design to generate the trace data using the XRT flow.
+      - Launch Vitis Analyzer to Examine Event Trace Files
+      - Details of the Event Trace data
Event Trace Analysis - XSDB Flow -This method explains how to use the SXSDB-based flow to perform event trace analysis on an AI Engine design.
+This method explains how to use the XSDB-based flow to perform event trace analysis on an AI Engine design.
Event Trace Considerations This method explains how to use the XSDB-based flow to perform event trace analysis on an AI Engine design.
-      * Event Trace Choice Considerations
-      * Number of Event Trace Streams Methodology
-      * Event Trace Limitations
+      - Event Trace Choice Considerations
+      - Number of Event Trace Streams Methodology
+      - Event Trace Limitations
-Demonstrates how to print vector output data value via `printf()`. +Demonstrates how to print the vector output data value via `printf()`.
Deadlock Detection @@ -158,7 +158,7 @@ Demonstrates how to debug memory access violations in an AI Enigne design using Using the GDB in the Command Line -Demonstrates about debugging in command line using the GNU Debugger (GDB). +Demonstrates debugging in command line using the GNU Debugger (GDB).
-Demosntrates how to run x86simulation on the command line. +Demonstrates how to run x86simulation on the command line.
x86simulation with the GDB @@ -179,7 +179,7 @@ Demosntrates how to run x86simulation on the command line. Demonstrates how to use the GDB during x86simulation.
x86simulator Using a GDB Server @@ -198,7 +198,7 @@ Demonstrates how to use a GDB server to debug the design. Build and Simulate in the Vitis IDE -Demonstrates how to use Vitis IDE to build and simulate an AI Engine design. +Demonstrates how to use the Vitis IDE to build and simulate an AI Engine design.
-Explains how to add a `printf() `statement, and view the output in the console. +Explains how to add a `printf()` statement, and view the output in the console.
-Explores different debugging techniques that uses the Vitis IDE debugger. +Explores different debugging techniques that use the Vitis IDE debugger.
Explains how to debug for software emulation using the Vitis IDE.
@@ -318,26 +318,26 @@ Explains how to use the GDB to debug in the command line using the option, `-ker Explains how to create a system project, build for hardware emulation, and run.
Debug PL Kernels Using the Vivado Logic Simulator -Explains how to use Vivado XSIM to debug the PL kernels. +Explains how to use the AMD Vivado™ XSIM to debug the PL kernels.
Performance of the AI Engine Using Hardware Emulation Results -This section profiles the system for hardware emulation and compares the throughput of the AI Engine design in hardware emulation with the throughput in AI Engine simulation. +This section profiles the system for hardware emulation and compares the throughput of the AI Engine design in hardware emulation with the throughput in a AI Engine simulation.
Command Line Project Source Code Debug with the Vitis IDE @@ -359,52 +359,52 @@ This section helps you debug your command line project using the features of the Explains how to determine the functional correctness of the design by running on hardware.
Error Handling and Reporting in the Host Application Explains how to use error reporting APIs to handle errors in the host code.
-       *Xilinx Runtime (XRT) error handling APIs - This method reports errors that can be detected during the XRT runtime function call or underneath driver, system, hardware, etc.
+       * XRT error handling APIs - This method reports errors that can be detected during the XRT runtime function call or underneath driver, system, hardware, etc.
      * Using XBUtil - XButil error reporting can accumulate all the errors from various classes and sorts them by timestamp.
Analyzing Run Results -Explains different techniques (XRT, XBUtil and XSDB) to analyze the design by running on hardware and helps to choose from the following methodologies.
-       * AI Engine status using XRT - Using XRT is fast and host executable can automatically reads the `xrt.ini` file to configure the runtime. -
+Explains different techniques (XRT, XBUtil, and XSDB) to analyze the design by running on hardware and helps to choose from the following methodologies.
+       - AI Engine status using XRT - Using XRT is fast and host executable can automatically reads the `xrt.ini` file to configure the runtime. -
      * Manual AI Engine status using XBUtil utility - XBUtil is a standalone command utility included with XRT and does not require any special file to handle. You can directly use XBUtil commands on the console after boot.
-       * Deadlock detection using XSDB - XSDB runs independent of XRT and can analyze the results before, during, or after design runs. Also, you can use the XSDB for baremetal applications in addition to the Linux-based applications.
+       - Deadlock detection using XSDB - XSDB runs independent of XRT and can analyze the results before, during, or after design runs. Also, you can use the XSDB for baremetal applications in addition to the Linux-based applications.
Using APIs in the Host Application Explains how to modify the host code to add APIs in the host application that helps profiling the design for getting throughput, latency, and bandwidth.
-       * Profiling Graph throughput - Provides insight on how to modify the host code for profiling the number of samples sent and received.
+       - Profiling Graph throughput - Provides insight on how to modify the host code for profiling the number of samples sent and received.
      * Profiling to count Samples sent and received (Exercise Step) - Provides insight on how to modify the host code for profiling the number of samples sent and received.
Hardware Profiling Feature - XRT Flow -Explains how to set up the configuration file `xrt.ini` and run the hardware design to generate profile data using the XRT flow.
-      * Open multiple profile runs in Vitis Analyzer - This exercise helps you understand how to open different profile summaries (two different runs) in a single Vitis Analyzer view.
-      * Profiling Data Explaination - This explains how to analyze AI Engine core,memory and interface profiling data. Also discusses what action should be taken based on the stall time and DMA lock time.
+Explains how to set up the configuration file `xrt.ini`, and run the hardware design to generate profile data using the XRT flow.
+      - Open multiple profile runs in Vitis Analyzer - This exercise helps you understand how to open different profile summaries (two different runs) in a single Vitis Analyzer view.
+      - Profiling Data Explaination - This explains how to analyze AI Engine core,memory and interface profiling data. Also discusses what action should be taken based on the stall time and DMA lock time.
Hardware Profiling Feature - XSDB Flow @@ -413,7 +413,7 @@ Explains how to set up the configuration file `xrt.ini` and run the hardware des This method explains how to use the XSDB-based flow to profile for both baremetal and Linux operating systems.
Profiling Using PL Profile Monitors @@ -422,7 +422,7 @@ This method explains how to use the XSDB-based flow to profile for both baremeta Explains how to insert PL profile monitors in the v++link command. This helps identify specific PL kernels(s) causing a performance drop.
Inserting ILA(s) to Monitor Specific AXI Interfaces @@ -431,14 +431,14 @@ Explains how to insert PL profile monitors in the v++link command. This helps id Explains how to insert one or more integrated logic analyzers (ILAs) to monitor specific PL AXI interfaces to help identify exactly where and when a throughput drop occurs. Also helps in identifying whether data is sent correctly to the AI Engine from the PL compenents and received correctly from the AI Engine to the PL.
Build the Design for Event Trace Analysis Explains how to use different event trace options for compiling and its significance. Also walks through the steps to generate the hardware image.
-      * Prepare for the hardware run +      - Prepare for the hardware run.
Explains how to do an AI Engine event trace and analysis by setting up the configuration file `xrt.ini` and run the hardware design to generate trace data using the XRT flow.
      * Launch Vitis Analyzer to Examine Event Trace Files
-      * Details of the Event Trace data
+      - Details of the Event Trace data
Event Trace Analysis - XSDB Flow @@ -461,16 +461,16 @@ Explains how to do an AI Engine event trace and analysis by setting up the confi This method explains how to use the XSDB-based flow to perform event trace analysis on an AI Engine design.
Event Trace Considerations This method explains how to use the XSDB-based flow to perform event trace analysis on anAI Engine design.
-      * Event Trace Choice Considerations
-      * Number of Event Trace Streams Methodology
-      * Event Trace Limitations
+      - Event Trace Choice Considerations
+      - Number of Event Trace Streams Methodology
+      - Event Trace Limitations
-# Conditionnal Objects Instantiation +# Conditional Objects Instantiation ## Introduction diff --git a/AI_Engine_Development/AIE/README.md b/AI_Engine_Development/AIE/README.md index 38ea876d85..c4ce91ea05 100644 --- a/AI_Engine_Development/AIE/README.md +++ b/AI_Engine_Development/AIE/README.md @@ -1,11 +1,14 @@ -

AI Engine Development

- See Vitis™ Development Environment on xilinx.com
 +

AMD Vitis™ AI Engine

+ See Vitis Development Environment on xilinx.com
+ +# AI Engine Development + ## Introduction The tutorials under the AI Engine Development help you learn how to target, develop, and deploy advanced algorithms using a Versal AI Engine array in conjunction with PL IP/kernels and software applications running on the embedded processors. To successfully deploy AI Engine applications in hardware, you need to be aware of the Vitis and AI Engine tools and flows. @@ -17,17 +20,22 @@ The tutorials under the AI Engine Development help you learn how to target, deve ## Getting Started ### AI Engine Documentation -To easily find the right documentation corresponding to the development stage you are at, we recommend you use the AI Engine Design Process Hub . + +To easily find the right documentation corresponding to the development stage you are at, we recommend you use the [AI Engine Design Process Hub](https://docs.xilinx.com/p/ai-engine-development). + The major documentation for AI Engine includes: -- AM009 - Versal ACAP AI Engine Architecture Manual -- UG1076 - AI Engine Tools and Flows -- UG1079 - AI Engine Kernel and Graph Programming Guide + +- *Versal ACAP AI Engine Architecture Manual* [AM009](https://docs.xilinx.com/r/en-US/am009-versal-ai-engine) +- *AI Engine Tools and Flows* [UG1076](https://docs.xilinx.com/r/en-US/ug1076-ai-engine-environment) +- *AI Engine Kernel and Graph Programming Guide* [UG1079](https://docs.xilinx.com/r/en-US/ug1079-ai-engine-kernel-coding) ### AI Engine Training + If you are new with AI Engine, the following training courses can help you understand the architechure and design flow. -- Designing with Versal AI Engine 1: Architecture and Design Flow -- Designing with Versal AI Engine 2: Graph Programming with AI Engine Kernels -- Designing with Versal AI Engine 3: Kernel Programming and Optimization + +- [Designing with Versal AI Engine 1: Architecture and Design Flow](https://xilinxprod-catalog.netexam.com/Search?searchText=Designing+with+Versal+AI+Engine+1) +- [Designing with Versal AI Engine 2: Graph Programming with AI Engine Kernels](https://xilinxprod-catalog.netexam.com/Search?searchText=Designing+with+Versal+AI+Engine+2) +- [Designing with Versal AI Engine 3: Kernel Programming and Optimization](https://xilinxprod-catalog.netexam.com/Search?searchText=Designing+with+Versal+AI+Engine+3) ### Environment Settings @@ -42,11 +50,12 @@ Run the following steps to setup environment (do **NOT** apply to tutorials that ### Getting Started with AI Engine Development Using the AI Engine Tutorials -![missing image](AI_Engine_dev_flow.png) +![missing image](AI_Engine_dev_flow.jpg) If you are new with the AI Engine Architecture and tools, we recommend that you start with the A to Z Bare-metal Flow, which will guide you through the entire flow from platform creation in AMD Vivado™ to AI Engine application creation, system integration and testing on Hardware using the Vitis IDE. #### AI Engine Application Development + To get started with AI Engine application development, we recommend that you look at the following tutorials: - DSP Library Tutorial which will guide you to create an AI Engine using application using the AMD provided DSP library - AIE DSPLib and Model Composer which will also guide you to create an AI Engine using application using the AMD provided DSP library but using the ModelComposer tool which enables easy designs through a MATLAB Simulink environment. diff --git a/AI_Engine_Development/AI_Engine_Development.rst b/AI_Engine_Development/AI_Engine_Development.rst index 7f1fa1327d..caa083c978 100644 --- a/AI_Engine_Development/AI_Engine_Development.rst +++ b/AI_Engine_Development/AI_Engine_Development.rst @@ -3,100 +3,38 @@ AI Engine Development ####################################### -.. sidebar:: More Information +********************************************************* +AI Engine Development on AIE-ML +********************************************************* - See Vitis™ Development Environment on `xilinx.com `_ -The tutorials under the AI Engine Development help you learn how to target, develop, and deploy advanced algorithms using a Versal AI Engine array in conjunction with PL IP/kernels and software applications running on the embedded processors. In order to successfully deploy AI Engine applications in hardware, you need to be aware of the Vitis and AI Engine tools and flows. - - -* :doc:`Feature Tutorials <./docs/Feature_Tutorials/Feature_Tutorials>` highlight specific features and flows that help develop AI Engine applications. -* :doc:`Design Tutorials <./docs/Design_Tutorials/Design_Tutorials>` showcase the two major phases of AI Engine application development: architecting the application and developing the kernels. Both these phases are demonstrated in these tutorials. - -Tutorials target the **VCK190** board. The table below lists the tutorials available, and the features and flows showcased in all of these tutorials. The various columns correspond to specific features/flows supported in these tutorials and will help you identify tutorials that showcase specific flows and features that you are interested in. - - -****************************************** -Environment Settings -****************************************** - -Before beginning a tutorial, read and follow the `Vitis Software Platform Release Notes `_ (v2023.1) for setting up software and installing the VCK190 base platform. - -Run the following steps to set up the environment (**NOT** apply to tutorials that do not use the VCK190 base platform): - -1. Set up your platform by running the ``xilinx-versal-common-v2023.1/environment-setup-cortexa72-cortexa53-xilinx-linux`` script as provided in the platform download. This script sets up the ``SYSROOT`` and ``CXX`` variables. If the script is not present, you **must** run the ``xilinx-versal-common-v2023.1/sdk.sh``. -2. Set up your ``ROOTFS`` to point to the ``xilinx-versal-common-v2023.1/rootfs.ext4``. -3. Set up your ``IMAGE`` to point to ``xilinx-versal-common-v2023.1/Image``. -4. Set up your ``PLATFORM_REPO_PATHS`` environment variable based upon where you downloaded the platform. - - - - -****************************************** -Feature Tutorials -****************************************** +Learn how to target, develop, and deploy advanced algorithms using Versal AIE-ML architecture in conjunction with PL IP/kernels and software applications running on the embedded processors. .. toctree:: :maxdepth: 3 - :caption: Feature Tutorials + :caption: AI Engine Development on AIE-ML :hidden: - Feature Tutorials <./docs/Feature_Tutorials/Feature_Tutorials> + AI Engine Development on AIE-ML <./docs/AIE-ML/AIE-ML> -.. csv-table:: Feature Tutorials - :header: "Tutorial","Platform","OS","IDE Flow","Libraries Used","HLS Kernel","x86 simulator","aie simulator","SW Emu","HW Emu","HW","Event Trace in HW","Profile in HW" - :widths: 22, 8, 8, 6, 7, 8, 7, 7, 5, 6, 4, 6, 6 - ":doc:`AI Engine A-to-Z Flow for Linux <./docs/Feature_Tutorials/18-aie_a_to_z_custom_linux_platform/README>`","Base / Custom","Linux","","","MM2S / S2MM","Yes","Yes","Yes","Yes","Yes",""," " - ":doc:`A to Z Bare-metal Flow <./docs/Feature_Tutorials/01-aie_a_to_z/README>`","Custom","Baremetal","Vivado, Vitis IDE","","MM2S / S2MM","","Yes","","Yes","Yes",""," " - ":doc:`Using GMIO with AIE <./docs/Feature_Tutorials/02-using-gmio/README>`","Base","Linux","","","","","Yes","","Yes","Yes","","Yes" - ":doc:`Runtime Parameter Reconfiguration <./docs/Feature_Tutorials/03-rtp-reconfiguration/README>`","Base","Linux","","","MM2S / S2MM","","Yes","","Yes","Yes",""," " - ":doc:`Packet Switching <./docs/Feature_Tutorials/04-packet-switching/README>`","Base","Linux","","","MM2S / S2MM","","Yes","","Yes","Yes",""," " - ":doc:`AIE Versal Integration <./docs/Feature_Tutorials/05-AI-engine-versal-integration/README>`","Base","Linux","","","MM2S / S2MM","Yes","Yes","Yes","Yes","Yes",""," " - ":doc:`Versal System Design Clocking <./docs/Feature_Tutorials/06-versal-system-design-clocking-tutorial/README>`","Base","Linux","","","MM2S / S2MM","","Yes","","Yes","Yes",""," " - ":doc:`Using Floating-Point in the AIE <./docs/Feature_Tutorials/07-AI-Engine-Floating-Point/README>`","Base","Linux","","","","","Yes","","","",""," " - ":doc:`DSP Library Tutorial <./docs/Feature_Tutorials/08-dsp-library/README>`","Base","Linux","","DSPLib","MM2S / S2MM Variant","","Yes","","","",""," " - ":doc:`Debug Walkthrough Tutorial <./docs/Feature_Tutorials/09-debug-walkthrough/README>`","Base","Linux","Vitis IDE","","","Yes","Yes","Yes","Yes","Yes","Yes","Yes" - ":doc:`AIE DSPLib and Model Composer <./docs/Feature_Tutorials/10-aie-dsp-lib-model-composer/README>`","Base","Linux","Simulink","DSPLib","MM2S / S2MM","Yes","Yes","","","",""," " - ":doc:`Versal Emulation Waveform Analysis <./docs/Feature_Tutorials/11-ai-engine-emulation-waveform-analysis/README>`","Base","Linux","","","Traffic Generators","","","","Yes","",""," " - ":doc:`AXIS External Traffic Generator <./docs/Feature_Tutorials/12-axis-traffic-generator/README>`","Base","Linux","","DSPLib","MM2S / S2MM","","Yes","","Yes","",""," " - ":doc:`AIE Performance and Deadlock Analysis <./docs/Feature_Tutorials/13-aie-performance-analysis/README>`","Base","Linux","","","","","Yes","","Yes","Yes","","Yes" - ":doc:`Implementing an IIR Filter on the AIE <./docs/Feature_Tutorials/14-implementing-iir-filter/README>`","Base","Linux","Vitis IDE","","","Yes","Yes","","","",""," " - ":doc:`Post-Link Recompile of an AIE Application <./docs/Feature_Tutorials/15-post-link-recompile/README>`","Base","Linux","","","MM2S / S2MM","","Yes","","Yes","Yes",""," " - ":doc:`Python and C++ External Traffic Generators for AI Engine Simulation and Emulation Flows <./docs/Feature_Tutorials/16-external-traffic-generator-aie/README>`","Base","Linux","","","MM2S / S2MM / PolarClip","Yes","Yes","Yes","Yes","",""," " - ":doc:`Using RTL IP with AI Engines <./docs/Feature_Tutorials/17-RTL-IP-with-AIE-Engines/README>`","Custom","Linux","","","MM2S / S2MM","","Yes","","Yes","",""," " - ":doc:`Using Verilog Traffic Generators in AIE Simulation <./docs/Feature_Tutorials/19-aie_external_io_sv/README>`","Base","Linux","Vivado","","","Yes","Yes","","","",""," " +********************************************************* +AI Engine Development on AIE +********************************************************* -****************************************** -Design Tutorials -****************************************** +Learn how to target, develop, and deploy advanced algorithms using a Versal AI Engine array in conjunction with PL IP/kernels and software applications running on the embedded processors. .. toctree:: :maxdepth: 3 - :caption: Design Tutorials + :caption: AI Engine Development on AIE :hidden: - Design Tutorials <./docs/Design_Tutorials/Design_Tutorials> - - - -.. csv-table:: Feature Tutorials - :header: "Tutorial","Platform","OS","IDE Flow","Libraries Used","HLS Kernel","x86 simulator","aie simulator","SW Emu","HW Emu","HW","Event Trace in HW","Profile in HW" - :widths: 22, 8, 8, 6, 7, 8, 7, 7, 5, 6, 4, 6, 6 + AI Engine Development on AIE <./docs/AIE/AIE> - ":doc:`Versal Custom Thin Platform Extensible System <./docs/Design_Tutorials/01-aie_lenet_tutorial/README>`","Custom","Linux","","","MM2S / S2MM / VADD","","","","Yes","Yes",""," " - ":doc:`LeNet Tutorial <./docs/Design_Tutorials/01-aie_lenet_tutorial/README>`","Base","Linux","","","MM2S / S2MM","","Yes","","Yes","Yes","","Yes" - ":doc:`Super Sampling Rate FIR Filters <./docs/Design_Tutorials/02-super_sampling_rate_fir/README>`","Base","Linux","","","","","Yes","","","",""," " - ":doc:`Beamforming Design <./docs/Design_Tutorials/03-beamforming/README>`","Base","Linux","","","","","Yes","","Yes","Yes","","Yes" - ":doc:`Polyphase Channelizer <./docs/Design_Tutorials/04-Polyphase-Channelizer/README>`","Base","Linux","","","MM2S / S2MM","","","","Yes","Yes","","" - ":doc:`2D-FFT <./docs/Design_Tutorials/06-fft2d_AIEvsHLS/README>`","Base","Linux","","DSPLib","PL Data Generator and Checker","","Yes","","Yes","Yes","","Yes" - ":doc:`FIR Filter <./docs/Design_Tutorials/07-firFilter_AIEvsHLS/README>`","Base","Linux","","DSPLib","PL Data Generator and Checker","","Yes","","Yes","Yes","","Yes" - ":doc:`N-Body Simulator <./docs/Design_Tutorials/08-n-body-simulator/README>`","Base","Linux","","","PL Datamover","","Yes","","Yes","Yes",""," " - ":doc:`Versal GeMM Implementation <./docs/Design_Tutorials/10-GeMM_AIEvsDSP/README>`","Base","Linux","","DSPLib","Datamover","","Yes","","Yes","Yes","","Yes" diff --git a/AI_Engine_Development/markdown_files.txt b/AI_Engine_Development/markdown_files.txt deleted file mode 100644 index 8b5e539d31..0000000000 --- a/AI_Engine_Development/markdown_files.txt +++ /dev/null @@ -1,119 +0,0 @@ -C:\GH\GHE\Vitis-Tutorials\AI_Engine_Development\AIE\README.md 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-C:\GH\GHE\Vitis-Tutorials\AI_Engine_Development\AIE-ML\Feature_Tutorials\20-aiecompiler-features\README.md diff --git a/Getting_Started/README.md b/Getting_Started/README.md index e5268e6a9b..c91a400158 100644 --- a/Getting_Started/README.md +++ b/Getting_Started/README.md @@ -1,11 +1,12 @@ -

Vitis™ Getting Started Tutorials

- See Vitis™ Development Environment on xilinx.com
 +

AMD Vitis™ Tutorials

+ See Vitis Development Environment on xilinx.com
+# Getting Started * **[Vitis Introduction and Getting Started](./Vitis)**: * An overview of the Vitis workflow including kernel development, host software creation, emulation, implementation, and analysis. This tutorial is divided into separate flows: diff --git a/Hardware_Acceleration/README.md b/Hardware_Acceleration/README.md index 257e9812c5..c8b7481c84 100644 --- a/Hardware_Acceleration/README.md +++ b/Hardware_Acceleration/README.md @@ -1,7 +1,7 @@ -

Vitis Hardware Acceleration Tutorials

- See Vitis™ Development Environment on xilinx.com +

AMD Vitis™ Hardware Acceleration Tutorials

+ See Vitis Development Environment on xilinx.com
diff --git a/README.md b/README.md index 083c862008..6cd84cb678 100755 --- a/README.md +++ b/README.md @@ -1,7 +1,7 @@

English | 日本語

-

Vitis™ In-Depth Tutorials

+

AMD Vitis™ In-Depth Tutorials
@@ -19,7 +19,7 @@ Visit more Vitis developer videos on Copyright © 2020–2023 Advanced Micro Devices, Inc

diff --git a/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/README.md b/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/README.md index 002b7a072c..fb0c6dbe0f 100644 --- a/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/README.md +++ b/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/README.md @@ -10,9 +10,9 @@ ***Version: Vitis 2023.2*** -The [AMD Kria™ KV260 Vision AI Starter Kit](https://www.xilinx.com/products/som/kria/kv260-vision-starter-kit.html) is the development platform for Kria K26 SOM. The KV260 is built for advanced vision application development without requiring complex hardware design knowledge. It is based on the AMD UltraScale+™ MPSoC technology similar to ZCU104 evaluation board. In this example, you will extend the [ZCU104 custom embedded platform creation example](../02-Edge-AI-ZCU104/) to KV260 Vision AI Starter Kit. +The [AMD Kria™ KV260 Vision AI Starter Kit](https://www.xilinx.com/products/som/kria/kv260-vision-starter-kit.html) is the development platform for Kria K26 SOM. The KV260 is built for advanced vision application development without requiring complex hardware design knowledge. It is based on the AMD UltraScale+™ MPSoC technology similar to ZCU104 evaluation board. In this example, you will extend the [ZCU104 custom embedded platform creation example](../02-Edge-AI-ZCU104/README.md) to KV260 Vision AI Starter Kit. -To highlight the differences between KV260 and ZCU104, this example will simplify the descriptions of general steps that are shared between all MPSoC platforms, but add more KV260 specific contents. If you have question in some steps, cross reference [ZCU104 custom embedded platform creation example](../02-Edge-AI-ZCU104/), or ask questions in Github Issues page. +To highlight the differences between KV260 and ZCU104, this example will simplify the descriptions of general steps that are shared between all MPSoC platforms, but add more KV260 specific contents. If you have question in some steps, cross reference [ZCU104 custom embedded platform creation example](../02-Edge-AI-ZCU104/README.md), or ask questions in Github Issues page. For your reference, The structure of this example system is shown in the following figure.. @@ -53,7 +53,7 @@ Because the Kria SOM Starter Kit provides an off-the-shelf boot image and has i | Transfer files and run | Use scp to copy generated files to Linux partition on SD card | | skip writing sd_card.img | > **NOTE:** In step 2, after extracting the common image there are a lot of output components, the only valuable output product in this case is sysroot. It is used for host application cross-compilation. Because the boot images of KV260 Starter Kit is fixed, you do not need to generate any boot components, e.g., FSBL, etc. - +> > **NOTE:** In this case, we assume you start to do this experiment after you have already had your board booted up successfully. If you do not, refer to [kv260 getting started page](https://www.xilinx.com/products/som/kria/kv260-vision-starter-kit/kv260-getting-started/getting-started.html). The following chapters will explain the details about these steps. @@ -66,7 +66,6 @@ The platform creation steps are introduced in the following pages. Each page des - [Step 2: Create the Vitis Platform](./step2.md) - [Step 3: Test the Platform](./step3.md) - [Iteration Guidelines](./Iteration_guideline.md) - ***Start from [Step 1: Vivado Design](./step1.md).*** diff --git a/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/step3.md b/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/step3.md index 52c3ceb84a..1536b40511 100644 --- a/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/step3.md +++ b/Vitis_Platform_Creation/Design_Tutorials/01-Edge-KV260/step3.md @@ -10,9 +10,10 @@ - [Step 3: Test the Platform](#step-3-test-the-platform) - [Test 1: Read Platform Info](#test-1-read-platform-info) - - [Test 2: Run Vector Addition Application](#test-2-run-vector-addition-application) - - [Congratulations](#congratulations) - - [Fast Track](#fast-track) + - [Test 2: Run Vector Addition Application](#test-2-run-vector-addition-application) + - [Congratulations](#congratulations) + - [Fast Track](#fast-track) + - [Next Steps](#next-steps) ## Test 1: Read Platform Info @@ -236,7 +237,7 @@ Feel free to check more tutorials in this repository. ### Fast Track -If you encounter any issues when creating the custom platform and the validation application in this tutorial, you can run `make all COMMON_IMAGE_ZYNQMP=` in [ref_files](./ref_files) directory to generate the reference design and compare with your design. COMMON_IMAGE_ZYNQMP is a flag to specify the common image path. Please download common image from [Xilinx website download page](https://www.xilinx.com/support/download.html) and give the path to the flag. +If you encounter any issues when creating the custom platform and the validation application in this tutorial, you can run `make all COMMON_IMAGE_ZYNQMP=` in the `ref_files` directory to generate the reference design and compare with your design. COMMON_IMAGE_ZYNQMP is a flag to specify the common image path. Please download common image from [Xilinx website download page](https://www.xilinx.com/support/download.html) and give the path to the flag. The command line flow has slight differences comparing to Vitis IDE flow. diff --git a/Vitis_Platform_Creation/Design_Tutorials/02-Edge-AI-ZCU104/02-Edge-AI-ZCU104.rst b/Vitis_Platform_Creation/Design_Tutorials/02-Edge-AI-ZCU104/02-Edge-AI-ZCU104.rst deleted file mode 100644 index b8b1303484..0000000000 --- a/Vitis_Platform_Creation/Design_Tutorials/02-Edge-AI-ZCU104/02-Edge-AI-ZCU104.rst +++ /dev/null @@ -1,5 +0,0 @@ -####################################################### -Version: Vitis 2022.2 -####################################################### - -To view the source files for this tutorial, click `here `_. \ No newline at end of file diff --git a/Vitis_Platform_Creation/Design_Tutorials/02-Edge-AI-ZCU104/Iteration_guideline.md b/Vitis_Platform_Creation/Design_Tutorials/02-Edge-AI-ZCU104/Iteration_guideline.md index 363f545441..d3cda8608c 100644 --- a/Vitis_Platform_Creation/Design_Tutorials/02-Edge-AI-ZCU104/Iteration_guideline.md +++ b/Vitis_Platform_Creation/Design_Tutorials/02-Edge-AI-ZCU104/Iteration_guideline.md @@ -1,12 +1,12 @@ -

Vitis™ Platform Creation Tutorials

- See Vitis™ Development Environment on xilinx.com
 +

Vitis Platform Creation Tutorials

+ See AMD Vitis™ Development Environment on xilinx.com
-## Iteration Guidelines +# Iteration Guidelines When using Vitis flow to create platform and develop acceleration applications, iteration could be divided into three cases: hardware updates, software update and application. Iteration steps should obey from the following steps. @@ -29,9 +29,9 @@ When using Vitis flow to create platform and develop acceleration applications, - If user update the host code, they just need to clean the host first and then rebuild the host. After copying the host ELF to the fat partition of the sd card. - If user update the Kernel code, they just need to clean the kernel and hardware link first and then rebuild the kernel and hardware link. After coping the XCLBIN file to the fat partition of the sd card. -When using Vitis export to Vivado flow to develop acceleration application, please follow [Vitis Export to Vivdao](../../Feature_Tutorials/03_Vitis_Export_To_Vivado) to do iteration. +When using Vitis export to Vivado flow to develop acceleration application, please follow [Vitis Export to Vivdao](../../Feature_Tutorials/03_Vitis_Export_To_Vivado/README.md) to do iteration.

Copyright © 2020–2023 Advanced Micro Devices, Inc

-

Terms and Conditions

\ No newline at end of file +

Terms and Conditions

diff --git a/Vitis_Platform_Creation/Design_Tutorials/02-Edge-AI-ZCU104/step2.md b/Vitis_Platform_Creation/Design_Tutorials/02-Edge-AI-ZCU104/step2.md index 3a19d28c9f..4c4663bda1 100644 --- a/Vitis_Platform_Creation/Design_Tutorials/02-Edge-AI-ZCU104/step2.md +++ b/Vitis_Platform_Creation/Design_Tutorials/02-Edge-AI-ZCU104/step2.md @@ -138,7 +138,7 @@ In addition to U-Boot file, lacks default environment variables. So you must upd 2. Create the Vitis platform. - For this example, you will use the Vitis Unifeid IDE to create the Vitis Platform. Got to `WorkSpace` directory and follow steps below to create the platform. + For this example, you will use the Vitis Unified IDE to create the Vitis Platform. Got to `WorkSpace` directory and follow steps below to create the platform. 1. Run Vitis by typing `vitis -w .` in the console. `-w` is to specify the workspace. `.` means the current worksapce directory. 2. In the Vitis Unified IDE, from menu select **File > New Component > Platform** to create a platform component. @@ -148,7 +148,7 @@ In addition to U-Boot file, lacks default environment variables. So you must upd >Note: If you want to create a platform with emulation support please click **Emulation** and select the emulation XSA file. - Set the operating system to **linux**.
- Set the processor to **psu_cortexa53**.
- - Check the option **Generate boot artifacts**. Then click **Next**.
+ - Check the option **Generate boot artifacts**. Then click **Next**.
>Note: Enabling this option will trigger the tool to automatically generate a PMU firmware domain and an FSBL (First Stage Boot Loader) domain into the platform - Review the summary and click **Finish**. >Note: After a few moments, the platform component will be prepared and available in the component view. Simultaneously, the platform configuration file, `vitis-comp.json`, will be automatically displayed in the main view. Users can access the `vitis-comp.json` file by expanding the Settings section under the platform component. @@ -156,7 +156,7 @@ In addition to U-Boot file, lacks default environment variables. So you must upd 3. Set up the software settings in the Platform configuration view by clicking the **Linux On psu_cortexa53** domain, browse to the locations and select the directory or file needed to complete the dialog box for the following: - **Display Name**: update it as `xrt` - - **Bif file**: Click the button to generate bif file or click **Browse** to select existing bif file. + - **Bif file**: Click the button to generate bif file or click **Browse** to select existing bif file. >**Note:** The filenames in `<>` are placeholders in the bif file. Vitis will replace the placeholders with the relative path to platform during platform packaging. V++ packager, which runs when building the final application#, would expand it further to the full path during image packaging. Filename placeholders point to the files in boot components directory. The filenames in boot directory need to match with placeholders in BIF file. `` is a reserved keyword. V++ packager will replace it with the final system bit file. @@ -180,14 +180,14 @@ In addition to U-Boot file, lacks default environment variables. So you must upd ![missing image](./images/vitis_platform_output.png) - >Note: After compilation, users can locate the XPFM file by expanding the Output directory. This provides a logical view of the output. The actual path of platform file is under `worksapce/zcu104_custom/export/zcu104_custom/` directory. Users can also view the complete path of the platform file by simply hovering the mouse pointer over the XPFM file. + >Note: After compilation, users can locate the XPFM file by expanding the Output directory. This provides a logical view of the output. The actual path of platform file is under `workspace/zcu104_custom/export/zcu104_custom/` directory. Users can also view the complete path of the platform file by simply hovering the mouse pointer over the XPFM file. >Note: The Vitis Unified IDE will find the boot-related files menntioned in the software components in begin of this step and place them in the boot folder of the platform. If you create a Vitis application component in the same workspace as this platform component, you can find this platform available in the platform selection page in the application Creation wizard. If you want to reuse this platform in another workspace, add its path to the `PLATFORM_REPO_PATHS` environment variable before launching the Vitis GUI, or use the "Add" button on the platform selection page of the Vitis GUI to add its path. - User could also use Vitis python command to create the platform component. + User could also use Vitis python command to create the platform component. @@ -248,6 +248,7 @@ In addition to U-Boot file, lacks default environment variables. So you must upd vitis -s platform_creation.py --platform_name <> --xsa_path <> --xsa-emu_path <> --boot <> --dtb <> ``` + ### Fast Track Scripts are provided to create the Vitis platform component. To use these scripts, run the following steps. diff --git a/Vitis_Platform_Creation/Design_Tutorials/02-Edge-AI-ZCU104/step3.md b/Vitis_Platform_Creation/Design_Tutorials/02-Edge-AI-ZCU104/step3.md index fbb3fd412a..21de5ff1a9 100644 --- a/Vitis_Platform_Creation/Design_Tutorials/02-Edge-AI-ZCU104/step3.md +++ b/Vitis_Platform_Creation/Design_Tutorials/02-Edge-AI-ZCU104/step3.md @@ -1,7 +1,7 @@ -

Vitis™ Platform Creation Tutorials

- See Vitis™ Development Environment on xilinx.com
 +

Vitis Platform Creation Tutorials

+ See AMD Vitis™ Development Environment on xilinx.com
@@ -9,10 +9,11 @@ # Step 3: Test the Platform - [Step 3: Test the Platform](#step-3-test-the-platform) - - [Test 1: Read Platform Info](#test-1-read-platform-info) - - [Test 2: Run Vector Addition Application](#test-2-run-vector-addition-application) + - [Test 1: Read Platform Info](#test-1-read-platform-info) + - [Test 2: Run Vector Addition Application](#test-2-run-vector-addition-application) - [Fast Track for Vector Addition](#fast-track-for-vector-addition) - - [Congratulations](#congratulations) + - [Congratulations](#congratulations) + - [Next Steps](#next-steps) ## Test 1: Read Platform Info @@ -101,6 +102,7 @@ System Configurations: Supported Runtimes: Runtime: C/C++ ``` + You can verify clock information and memory information are set as expected. @@ -124,11 +126,11 @@ Vector addition is the simplest acceleration PL kernel. The Vitis Unified IDE ca - Set **Sysroot** to ```zcu104_software_platform/xilinx-zynqmp-common-v2023.1/sysroots/cortexa72-cortexa53-xilinx-linux```. Then click **Next**. - Review the summary of your `vadd` system project and click **Finish**. - After seconds the vadd system project, vadd host component and vadd kernel component will be ready in the component view. - + After seconds the vadd system project, vadd host component and vadd kernel component will be ready in the component view. + 2. Building Vector Addition Application - Vadd system project supports three targets: Software emulation, Hardware emulation and Hardware. User could select the target accordingly following steps below. + Vadd system project supports three targets: Software emulation, Hardware emulation and Hardware. User could select the target accordingly following steps below. - Go to flow navigator and select vadd system project. @@ -172,7 +174,7 @@ Vector addition is the simplest acceleration PL kernel. The Vitis Unified IDE ca First, login with user `petalinux` and set up a new password (it is then also the sudo password): 1. Log into the system - + ```bash petalinux login:petalinux You are required to change your password immediately (administrator enforced). @@ -200,7 +202,7 @@ Vector addition is the simplest acceleration PL kernel. The Vitis Unified IDE ca ./simple_vadd krnl_vadd.xclbin ``` - It should show program prints and XRT debug information . + It should show program prints and XRT debug information. ``` TEST PASSED diff --git a/Vitis_Platform_Creation/Design_Tutorials/03_Edge_VCK190/Iteration_guideline.md b/Vitis_Platform_Creation/Design_Tutorials/03_Edge_VCK190/Iteration_guideline.md index 363f545441..10b79623b4 100644 --- a/Vitis_Platform_Creation/Design_Tutorials/03_Edge_VCK190/Iteration_guideline.md +++ b/Vitis_Platform_Creation/Design_Tutorials/03_Edge_VCK190/Iteration_guideline.md @@ -29,7 +29,7 @@ When using Vitis flow to create platform and develop acceleration applications, - If user update the host code, they just need to clean the host first and then rebuild the host. After copying the host ELF to the fat partition of the sd card. - If user update the Kernel code, they just need to clean the kernel and hardware link first and then rebuild the kernel and hardware link. After coping the XCLBIN file to the fat partition of the sd card. -When using Vitis export to Vivado flow to develop acceleration application, please follow [Vitis Export to Vivdao](../../Feature_Tutorials/03_Vitis_Export_To_Vivado) to do iteration. +When using Vitis export to Vivado flow to develop acceleration application, please follow [Vitis Export to Vivdao](../../Feature_Tutorials/03_Vitis_Export_To_Vivado/README.md) to do iteration.

Copyright © 2020–2023 Advanced Micro Devices, Inc

diff --git a/Vitis_Platform_Creation/Design_Tutorials/03_Edge_VCK190/README.md b/Vitis_Platform_Creation/Design_Tutorials/03_Edge_VCK190/README.md index d18abb069e..a658bf9b12 100644 --- a/Vitis_Platform_Creation/Design_Tutorials/03_Edge_VCK190/README.md +++ b/Vitis_Platform_Creation/Design_Tutorials/03_Edge_VCK190/README.md @@ -1,7 +1,7 @@ -

Vitis™ Platform Creation Tutorials

- See Vitis™ Development Environment on xilinx.com
 +

Vitis Platform Creation Tutorials

+ See AMD Vitis™ Development Environment on xilinx.com
@@ -10,7 +10,7 @@ ***Version: 2023.2*** -In this module, we treat the VCK190 board as if it were a custom solution tailored to our customer's specific needs. Our approach involves leveraging the AMD Versal™ Adaptive SoC Extensible Part Support Example Design and harnessing the power of a pre-built Linux common image, along with the createdts command, to generate essential software components. These components are then used to construct a dedicated embedded Versal acceleration platform designed exclusively for our customer's board. As the final step, you will run several applications to test this platform. If you merely create a platform to validate your kernels, then the [Vitis Platform Quick Start](../../../Getting_Started/Vitis_Platform/README.md) would be a quick choice for you. +In this module, we treat the VCK190 board as if it were a custom solution tailored to our customer's specific needs. Our approach involves leveraging the AMD Versal™ Adaptive SoC Extensible Part Support Example Design and harnessing the power of a pre-built Linux common image, along with the createdts command, to generate essential software components. These components are then used to construct a dedicated embedded Versal acceleration platform designed exclusively for our customer's board. As the final step, you will run several applications to test this platform. If you merely create a platform to validate your kernels, then the [Vitis Platform Quick Start](https://docs.xilinx.com/r/en-US/Vitis-Tutorials-Getting-Started/Vitis-Platform) would be a quick choice for you. For your reference, the overall structure of this example system closely resembles the following: @@ -25,7 +25,7 @@ In a general Vitis acceleration platform design, the Vitis platform and applicat 4. Create applications in Vitis against the platform. Vitis generates a host application, xclbin, and `sd_card.img`. 5. Write `sd_card.img` to a SD card or update host application and xclbin to an existing SD card. -In this module, you will utilize the Versal Extensible Part Support Design (CED) to create a hardware design. In contrast to the Versal Extensible Design, which is used in [Vitis Platform Quick Start](../../../Getting_Started/Vitis_Platform/README.md), the part support design takes a slightly different approach. Specifically, it empowers you to handle board-level configurations independently. This includes configuring processing system (PS) side peripherals and fine-tuning parameters related to double data rate (DDR) as needed. This flexibility ensures that you have full control over the configuration process to meet the unique requirements of your application. +In this module, you will utilize the Versal Extensible Part Support Design (CED) to create a hardware design. In contrast to the Versal Extensible Design, which is used in [Vitis Platform Quick Start](https://docs.xilinx.com/r/en-US/Vitis-Tutorials-Getting-Started/Vitis-Platform), the part support design takes a slightly different approach. Specifically, it empowers you to handle board-level configurations independently. This includes configuring processing system (PS) side peripherals and fine-tuning parameters related to double data rate (DDR) as needed. This flexibility ensures that you have full control over the configuration process to meet the unique requirements of your application. To prepare the software components, you will utilize common image released by AMD and `createdts` command to generate the device tree file. After the whole software and hardware components are ready, you will package the platform. diff --git a/Vitis_Platform_Creation/Design_Tutorials/03_Edge_VCK190/step1.md b/Vitis_Platform_Creation/Design_Tutorials/03_Edge_VCK190/step1.md index 6cf0241412..a4d0cc33f0 100644 --- a/Vitis_Platform_Creation/Design_Tutorials/03_Edge_VCK190/step1.md +++ b/Vitis_Platform_Creation/Design_Tutorials/03_Edge_VCK190/step1.md @@ -289,7 +289,7 @@ Some blocks in the block design has multiple types of simulation models. Vitis e ### Validate the Output of Step 1 - Refer to [Platform Validation Example](../..//Feature_Tutorials/03_platform_validation/) + Refer to [Platform Validation Example](../../Feature_Tutorials/04_platform_validation/README.md) ### Fast Track diff --git a/Vitis_Platform_Creation/Design_Tutorials/04_Edge_VCK190_DFX/04_Edge_VCK190_DFX.rst b/Vitis_Platform_Creation/Design_Tutorials/04_Edge_VCK190_DFX/04_Edge_VCK190_DFX.rst deleted file mode 100644 index ee0b9832f5..0000000000 --- a/Vitis_Platform_Creation/Design_Tutorials/04_Edge_VCK190_DFX/04_Edge_VCK190_DFX.rst +++ /dev/null @@ -1,5 +0,0 @@ -####################################################### -Version: Vitis 2022.2 -####################################################### - -To view the source files for this tutorial, click `here `_. \ No newline at end of file diff --git a/Vitis_Platform_Creation/Design_Tutorials/04_Edge_VCK190_DFX/Iteration_guideline.md b/Vitis_Platform_Creation/Design_Tutorials/04_Edge_VCK190_DFX/Iteration_guideline.md index 363f545441..081aaae0e7 100644 --- a/Vitis_Platform_Creation/Design_Tutorials/04_Edge_VCK190_DFX/Iteration_guideline.md +++ b/Vitis_Platform_Creation/Design_Tutorials/04_Edge_VCK190_DFX/Iteration_guideline.md @@ -1,7 +1,7 @@ -

Vitis™ Platform Creation Tutorials

- See Vitis™ Development Environment on xilinx.com
 +

Vitis Platform Creation Tutorials

+ See AMD Vitis™ Development Environment on xilinx.com
@@ -29,7 +29,7 @@ When using Vitis flow to create platform and develop acceleration applications, - If user update the host code, they just need to clean the host first and then rebuild the host. After copying the host ELF to the fat partition of the sd card. - If user update the Kernel code, they just need to clean the kernel and hardware link first and then rebuild the kernel and hardware link. After coping the XCLBIN file to the fat partition of the sd card. -When using Vitis export to Vivado flow to develop acceleration application, please follow [Vitis Export to Vivdao](../../Feature_Tutorials/03_Vitis_Export_To_Vivado) to do iteration. +When using Vitis export to Vivado flow to develop acceleration application, please follow [Vitis Export to Vivdao](../../Feature_Tutorials/03_Vitis_Export_To_Vivado/README.md) to do iteration.

Copyright © 2020–2023 Advanced Micro Devices, Inc

diff --git a/Vitis_Platform_Creation/Design_Tutorials/04_Edge_VCK190_DFX/README.md b/Vitis_Platform_Creation/Design_Tutorials/04_Edge_VCK190_DFX/README.md index ddcaf2ac99..e53214ab5c 100644 --- a/Vitis_Platform_Creation/Design_Tutorials/04_Edge_VCK190_DFX/README.md +++ b/Vitis_Platform_Creation/Design_Tutorials/04_Edge_VCK190_DFX/README.md @@ -1,7 +1,7 @@  -

Vitis™ Platform Creation Tutorials

- See Vitis™ Development Environment on xilinx.com
 +

Vitis Platform Creation Tutorials

+ See AMD Vitis™ Development Environment on xilinx.com
diff --git a/Vitis_Platform_Creation/Design_Tutorials/04_Edge_VCK190_DFX/faq.md b/Vitis_Platform_Creation/Design_Tutorials/04_Edge_VCK190_DFX/faq.md index ee4761d859..d8450a6d08 100644 --- a/Vitis_Platform_Creation/Design_Tutorials/04_Edge_VCK190_DFX/faq.md +++ b/Vitis_Platform_Creation/Design_Tutorials/04_Edge_VCK190_DFX/faq.md @@ -1,6 +1,7 @@ - +
-

Versal Custom Platform Creation Tutorial

+

Vitis Platform Creation Tutorials

+ See AMD Vitis™ Development Environment on xilinx.com
diff --git a/Vitis_Platform_Creation/Design_Tutorials/04_Edge_VCK190_DFX/step1.md b/Vitis_Platform_Creation/Design_Tutorials/04_Edge_VCK190_DFX/step1.md index 50cfec61d6..147e050cef 100644 --- a/Vitis_Platform_Creation/Design_Tutorials/04_Edge_VCK190_DFX/step1.md +++ b/Vitis_Platform_Creation/Design_Tutorials/04_Edge_VCK190_DFX/step1.md @@ -1,6 +1,7 @@ - +
-

Custom Versal DFX Platform Creation Tutorial

+

Vitis Platform Creation Tutorials

+ See AMD Vitis™ Development Environment on xilinx.com
diff --git a/Vitis_Platform_Creation/Design_Tutorials/04_Edge_VCK190_DFX/step2.md b/Vitis_Platform_Creation/Design_Tutorials/04_Edge_VCK190_DFX/step2.md index 24333c7963..98d1877909 100644 --- a/Vitis_Platform_Creation/Design_Tutorials/04_Edge_VCK190_DFX/step2.md +++ b/Vitis_Platform_Creation/Design_Tutorials/04_Edge_VCK190_DFX/step2.md @@ -1,6 +1,7 @@ - +
-

Versal Custom Platform Creation Tutorial

+

Vitis Platform Creation Tutorials

+ See AMD Vitis™ Development Environment on xilinx.com
diff --git a/Vitis_Platform_Creation/Design_Tutorials/04_Edge_VCK190_DFX/step3.md b/Vitis_Platform_Creation/Design_Tutorials/04_Edge_VCK190_DFX/step3.md index b8919089ec..c2c94bb438 100644 --- a/Vitis_Platform_Creation/Design_Tutorials/04_Edge_VCK190_DFX/step3.md +++ b/Vitis_Platform_Creation/Design_Tutorials/04_Edge_VCK190_DFX/step3.md @@ -1,6 +1,7 @@ - +
-

Versal Custom Platform Creation Tutorial

+

Vitis Platform Creation Tutorials

+ See AMD Vitis™ Development Environment on xilinx.com
diff --git a/Vitis_Platform_Creation/Design_Tutorials/Design_Tutorials.rst b/Vitis_Platform_Creation/Design_Tutorials/Design_Tutorials.rst index f6995cab24..8bab4c5656 100644 --- a/Vitis_Platform_Creation/Design_Tutorials/Design_Tutorials.rst +++ b/Vitis_Platform_Creation/Design_Tutorials/Design_Tutorials.rst @@ -5,7 +5,7 @@ Vitis Platform Creation: Design Tutorials .. sidebar:: More Information - See Vitis™ Development Environment on `xilinx.com `_ + See AMD Vitis™ Development Environment on `xilinx.com `_ @@ -40,5 +40,5 @@ Vitis Platform Creation: Design Tutorials - This tutorial demonstrates how you can create a custom Vitis platform on VCK190 demo board and validate the platform. * - :doc:`Custom Kria SOM Platform Creation Example <./01-Edge-KV260/README>` - - Extend the :doc:`Custom Platform Creation Tutorial on MPSoC <./02-Edge-AI-ZCU104/README>` to the popular MPSoC board, the Kria SOM KV260 Starter Kit. + - Extend the :doc:`Custom Platform Creation Tutorial on MPSoC <./02-Edge-AI-ZCU104/README>` to the popular MPSoC board, the AMD Kria™ SOM KV260 Starter Kit. diff --git a/Vitis_Platform_Creation/Design_Tutorials/README.md b/Vitis_Platform_Creation/Design_Tutorials/README.md index 0696f01d52..62731cb248 100644 --- a/Vitis_Platform_Creation/Design_Tutorials/README.md +++ b/Vitis_Platform_Creation/Design_Tutorials/README.md @@ -1,6 +1,6 @@ - @@ -10,7 +10,7 @@

Vitis™ Platform Creation Tutorials

+

AMD Vitis™ Platform Creation Tutorials
-### Design Tutorials +## Design Tutorials @@ -34,7 +34,7 @@ -
Custom Kria SOM Platform Creation ExampleExtend the ZCU104 custom embedded platform creation example to the popular MPSoC board: Kria SOM KV260 Starter Kit. + Extend the ZCU104 custom embedded platform creation example to the popular MPSoC board, the AMD Kria™ SOM KV260 Starter Kit.
diff --git a/Vitis_Platform_Creation/Feature_Tutorials/01_platform_creation_streaming_ip/README.md b/Vitis_Platform_Creation/Feature_Tutorials/01_platform_creation_streaming_ip/README.md index e8f0adb213..a260657457 100644 --- a/Vitis_Platform_Creation/Feature_Tutorials/01_platform_creation_streaming_ip/README.md +++ b/Vitis_Platform_Creation/Feature_Tutorials/01_platform_creation_streaming_ip/README.md @@ -9,11 +9,12 @@ ***Version: Vitis 2023.2*** -This tutorial explains how to add custom IPs into a Versal™ adaptive SoC platform. This tutorial is an 'add-on' to the basic [Versal platform creation tutorial](../../Design_Tutorials/03_Edge_VCK190/). Therefore, for each step, there is a pointer to the corresponding part of that tutorial, as required. +This tutorial explains how to add custom IPs into a Versal™ adaptive SoC platform. This tutorial is an 'add-on' to the basic [Versal platform creation tutorial](../../Design_Tutorials/03_Edge_VCK190/README.md). Therefore, for each step, there is a pointer to the corresponding part of that tutorial, as required. -This tutorial targets the Versal board. +This tutorial targets the Versal board. ## Overview + The tutorial is structured as follows: - [Versal Platform Creation with Custom IP](#versal-platform-creation-with-custom-ip) - [Overview](#overview) @@ -59,7 +60,7 @@ In this step, you add a DDS compiler IP into the platform design that you create You can adjust the frequency value but keep the sample rate in mind. The clocking rate is 300 MHz. If there are too few samples within one cycle, the sine wave cannot be sampled correctly. - ![missing image](images/dds_freq.png) + ![missing image](images/dds_freq.png) 4. Exit the configuration page and connect the `aclk` port to the `clk_out1` signal of clocking wizard. diff --git a/Vitis_Platform_Creation/Feature_Tutorials/03_Vitis_Export_To_Vivado/README.md b/Vitis_Platform_Creation/Feature_Tutorials/03_Vitis_Export_To_Vivado/README.md index 2c97352b99..d38ce88ec7 100644 --- a/Vitis_Platform_Creation/Feature_Tutorials/03_Vitis_Export_To_Vivado/README.md +++ b/Vitis_Platform_Creation/Feature_Tutorials/03_Vitis_Export_To_Vivado/README.md @@ -1,11 +1,8 @@ - - - - +

Vitis™ Platform Creation Tutorials

-
-

Vitis Platform Creation Tutorials

+ See AMD Vitis™ Development Environment on xilinx.com
 +
@@ -15,7 +12,7 @@ ## Introduction -The Vitis Export to Vivado is the new feature release in AMD Vivado™ 2023.1/Vitis 2023.1 suites which enables bidirectional hardware hand-offs between the Vitis tools and the Vivado Design Suite to improve developer productivity. You can do the hardware design development in the Vivado Design Suite and use the Vitis tool to do the software development, such as, Xilinx Runtime (XRT), AI Engine (AIE) development, and programmable logic (PL) kernels development in the Vitis tool. Prior to this release, for any change in the hardware design, you needed to export the extensible XSA, go to the Vitis environment, and carry out the further development flow in the Vitis tool. This flow provides the flexibility to do the hardware design development in the Vivado design, which includes hardware design development, synthesis, implementation, and timing closure in Vivado and other development tasks like XRT, AIE development, application development, HLS kernel development, etc. in the Vitis tool. In 2023.1, the flow supports hardware development only (i.e., `TARGET=HW`). +The Vitis Export to Vivado is the new feature release in AMD Vivado™ 2023.1/Vitis 2023.1 suites which enables bidirectional hardware hand-offs between the Vitis tools and the Vivado Design Suite to improve developer productivity. You can do the hardware design development in the Vivado Design Suite and use the Vitis tool to do the software development, such as, Xilinx Runtime (XRT), AI Engine (AIE) development, and programmable logic (PL) kernels development in the Vitis tool. Prior to this release, for any change in the hardware design, you needed to export the extensible XSA, go to the Vitis environment, and carry out the further development flow in the Vitis tool. This flow provides the flexibility to do the hardware design development in the Vivado design, which includes hardware design development, synthesis, implementation, and timing closure in Vivado and other development tasks like XRT, AIE development, application development, HLS kernel development, etc. in the Vitis tool. In 2023.1, the flow supports hardware development only (i.e., `TARGET=HW`). The tutorial describes the flow which starts from the Vivado Design Suite. The hardware design to be developed in the Vivado design and export the extensible hardware platform (.xsa) from the Vivado Design Suite that forms the basis of many differentiated Vitis hardware applications. The extensible platform is imported into the Vitis environment to perform the development of the AI Engine Graph application and additional PL kernels for the system design. Compile the AIE graph and PL kernels. Link the compiled output, extensible platform to export the VMA during the v++ linking phase using the new v++ switch. Import the VMA file into Vivado using the new Tcl API and later, design development work can be continued in the Vivado design. Design flow section shared the complete design flow. @@ -52,8 +49,6 @@ After completing the tutorial, you will be able to do the following: ## DESIGN FILES --------------- - 1. The following Tcl files used to create the Vivado project are in the `vivado_impl` directory: - [Flat.tcl](./vivado_impl/flat.tcl) @@ -117,7 +112,7 @@ Output: The generated extensible XSA is located in the director `vivado_impl/fla #### Step 2 -After exporting the XSA, you need to compile AIE and PL Kernels, and generate `libadf.a` and `.xo ` file respectively before running the v++ linker (same as the Vitis integrated flow). +After exporting the XSA, you need to compile AIE and PL Kernels, and generate `libadf.a` and `.xo` file respectively before running the v++ linker (same as the Vitis integrated flow). ##### 2.1: Compile the AIE Graph and Generate `libadf.a` diff --git a/Vitis_Platform_Creation/Feature_Tutorials/04_platform_validation/README.md b/Vitis_Platform_Creation/Feature_Tutorials/04_platform_validation/README.md index a0cd211812..e3df07c6bf 100644 --- a/Vitis_Platform_Creation/Feature_Tutorials/04_platform_validation/README.md +++ b/Vitis_Platform_Creation/Feature_Tutorials/04_platform_validation/README.md @@ -1,7 +1,7 @@  -

Vitis™ Platform Creation Tutorials

- See Vitis™ Development Environment on xilinx.com
 +

Vitis Platform Creation Tutorials

+ See AMD Vitis™ Development Environment on xilinx.com
@@ -10,47 +10,49 @@ ***Version: Vitis 2023.2*** -In this tutorial, you will learn how to validate a Versal® ACAP extensible platform. This tutorial is an 'add-on' to the basic [Versal platform creation tutorial](../../Design_Tutorials/03_Edge_VCK190/). So for each step, there will be a pointer to the corresponding part of that tutorial, as required. +In this tutorial, you will learn how to validate an AMD Versal® ACAP extensible platform. This tutorial is an 'add-on' to the basic [Versal platform creation tutorial](../../Design_Tutorials/03_Edge_VCK190/README.md). So for each step, there will be a pointer to the corresponding part of that tutorial, as required. -This tutorial targets the Versal board or Versal parts. +This tutorial targets the Versal board or Versal parts. ## Overview + The tutorial is structured as follows: -- [Versal Platform Validation](#versal-platform-validation) + +- [Versal Extensible Hardware Design Validation](#versal-extensible-hardware-design-validation) - [Overview](#overview) - [Extensible platform validation general outline](#extensible-platform-validation-general-outline) - [Platform hardware validation](#platform-hardware-validation) - - [Stage I](#stage-i-base-bootable-design-verification) - - [Step 1: Prepare a hardware design](#step-1-prepare-a-hardware-design) - - [Step 2: Validate the hardware design](#step-2-validate-the-hardware-design) - - [Test1: Go through implementation](#test1-go-through-implementation) - - [Test2: Validate PDI on Hardware](#test2-validate-pdi-on-hardware) - - [Test3: Peripheral bare-metal test](#test3-peripheral-bare-metal-test) - - [Stage II Extensible platform interface verification](#stage-ii-extensible-platform-interface-verification) - - [Step 1: Prepare a Hardware Platform](#step-1-prepare-a-hardware-platform) - - [Step 2: Utilize the V++ linker to link a kernel and generate fixed XSA file](#step-2-utilize-the-v-linker-to-link-a-kernel-and-generate-fixed-xsa-file) - - [Step 3: Create a platform with standalone domain](#step-3-create-a-platform-with-standalone-domain) - - [Step 4: Create application base on the platform](#step-4-create-application-base-on-the-platform) - - [Extensible platform validation Demonstration](#extensible-platform-validation-Demonstration) - - [Test example 1: Interrupt connection check](#test-example-1-interrupt-connection-check) - - [Test example 2: Test Example 2: AIE test](#test-example-2-aie-test) - - [Support](#support) - + - [Stage I Base bootable design verification](#stage-i-base-bootable-design-verification) + - [Step 1: Prepare a hardware design](#step-1-prepare-a-hardware-design) + - [Step 2: Validate the hardware design](#step-2-validate-the-hardware-design) + - [Test1: Go through implementation](#test1-go-through-implementation) + - [Test2: Validate PDI on Hardware](#test2-validate-pdi-on-hardware) + - [Test3: Peripheral bare-metal test](#test3-peripheral-bare-metal-test) + - [Stage II Extensible platform interface verification](#stage-ii-extensible-platform-interface-verification) + - [Step 1: Prepare a Hardware Platform](#step-1-prepare-a-hardware-platform) + - [Step 2: Utilize the V++ linker to link a kernel and generate fixed XSA file](#step-2-utilize-the-v-linker-to-link-a-kernel-and-generate-fixed-xsa-file) + - [Step 3: Create a platform with standalone domain](#step-3-create-a-platform-with-standalone-domain) + - [Step 4: Create application base on the platform](#step-4-create-application-base-on-the-platform) + - [Extensible platform validation demonstration](#extensible-platform-validation-demonstration) + - [Test example 1: Interrupt connection check](#test-example-1-interrupt-connection-check) + - [Test Example 2: AIE test](#test-example-2-aie-test) + - [Support](#support) + ## Extensible platform validation general outline No matter user use Vitis flow or Vitis export to Vivado flow to develop their acceleration application, the extensible hardware platform (XSA) which provides the hardware environment for application kernels is the development start point. Thereby, hardware platform validation is necessary before going to next stage. ->Note: For Vitis export to Vivado flow, please refer to [Vitis Export To Vivado](03_Vitis_Export_To_Vivado). +>Note: For Vitis export to Vivado flow, please refer to [Vitis Export To Vivado](../03_Vitis_Export_To_Vivado/README.md). Hardware platform validation can be divided into two stage. The first stage is to validate the peripherals to ensure a bootable design. -The second stage is to validate the platform interface exported to kernel. Extensible hardware platform provides the interface like: AXI master interface, AXI slave interface, AXI streaming interface and interrupt interface for kernels. These interface guarantee the kernel control, memory access, large data moving and interrupt control. Validating the platform, that is to validate the interfaces provided to kernels. +The second stage is to validate the platform interface exported to kernel. Extensible hardware platform provides the interface like: AXI master interface, AXI slave interface, AXI streaming interface and interrupt interface for kernels. These interface guarantee the kernel control, memory access, large data moving and interrupt control. Validating the platform, that is to validate the interfaces provided to kernels. ![missing image](images/interface.svg) -The interfaces exported for extensible XSA is linked by V++ linker to connect PL or AIE kernels. V++ linker supports to take XSA or XPFM as input. Linking a kernel with the hardware XSA and testing from kernel side would be the easiest way for validation. +The interfaces exported for extensible XSA is linked by V++ linker to connect PL or AIE kernels. V++ linker supports to take XSA or XPFM as input. Linking a kernel with the hardware XSA and testing from kernel side would be the easiest way for validation. The validation can include following tests: @@ -76,7 +78,7 @@ Please follow the instructions in [Versal platform creation tutorial-Step1](../. #### Test1: Go through implementation - As the hardware platform is created from part support example design or from scratch, it's recommended to run through implementation and device image generation to find errors in early stage for the base bootable design. The platform doesn't need the implementation results, the implementation is used for design validation only. + As the hardware platform is created from part support example design or from scratch, it's recommended to run through implementation and device image generation to find errors in early stage for the base bootable design. The platform doesn't need the implementation results, the implementation is used for design validation only.
Show Detailed Steps of Implementation @@ -90,7 +92,7 @@ Please follow the instructions in [Versal platform creation tutorial-Step1](../. - In Sources tab, right click system.bd and select ***Create HDL Wrapper***. In the pop-up window, select ***Let Vivado Manage***. -3. Select ***Run implementation*** from Flow Navigator, Click **OK** in **Launch Runs** setup dialog. +3. Select ***Run implementation*** from Flow Navigator, Click **OK** in **Launch Runs** setup dialog. 4. Generate Device Image (For Method2) @@ -232,7 +234,7 @@ Please refer to [Versal platform creation tutorial-Step3](../../Design_Tutorials 2. Kernel accesses the memory to determine whether the memory is accessible or not from kernel side, and thus indirectly determine whether AXI slave interface for memory is working or not. 3. Kernel triggers interrupt to PS and PS try to capture the interrupt to determine whether the interrupt connection is correct or not, and thus indirectly determine whether the interrupt is working or not. - One reference design [examples](ref_files/) is provided under ref_file directory for your reference. Next we will demonstrate how to use the examples provided in ref_files directory to do validation. + One reference design example is provided in the `ref_files` directory for your reference. Next we will demonstrate how to use the examples provided in ref_files directory to do validation. ### Extensible platform validation demonstration @@ -245,7 +247,7 @@ Please refer to [Versal platform creation tutorial-Step3](../../Design_Tutorials ![missing image](images/delete_irq_connection.PNG) - 2. Go to [ref_files](ref_files/) directory. + 2. Go to the `ref_files` directory. ```bash cd ref_files/pl_validation @@ -289,7 +291,7 @@ Please refer to [Versal platform creation tutorial-Step3](../../Design_Tutorials 1. Please follow the instructions in [Versal platform creation tutorial-Step1](../../Design_Tutorials/03_Edge_VCK190/step1.md) to create a custom hardware platform. You can skip the optional steps. - 2. Go to [ref_files](ref_files/) directory. + 2. Go to the `ref_files` directory. ```bash cd ref_files/aie_validation diff --git a/Vitis_Platform_Creation/Feature_Tutorials/Feature_Tutorials.rst b/Vitis_Platform_Creation/Feature_Tutorials/Feature_Tutorials.rst index c5f727b46a..1a8d94a821 100644 --- a/Vitis_Platform_Creation/Feature_Tutorials/Feature_Tutorials.rst +++ b/Vitis_Platform_Creation/Feature_Tutorials/Feature_Tutorials.rst @@ -5,7 +5,7 @@ AI Engine Development: Feature Tutorials .. sidebar:: More Information - See Vitis™ Development Environment on `xilinx.com `_ + See AMD Vitis™ Development Environment on `xilinx.com `_ @@ -14,10 +14,10 @@ AI Engine Development: Feature Tutorials :caption: Feature Tutorials :hidden: - Incorporation Stream Interfaces <./01_platform_creation_streaming_ip/README> + Incorporating Stream Interfaces <./01_platform_creation_streaming_ip/README> PetaLinux Building and System Customization <./02_petalinux_customization/README> Hardware Design Fast Iteration with Vitis Export to Vivado <./03_Vitis_Export_To_Vivado/README> - + Versal Extensible Hardware Design Validation <./04_platform_validation/README> @@ -28,13 +28,16 @@ AI Engine Development: Feature Tutorials * - Tutorial - Description - * - :doc:`Incorporation Stream Interfaces <./01_platform_creation_streaming_ip/README>` + * - :doc:`Incorporating Stream Interfaces <./01_platform_creation_streaming_ip/README>` - This tutorial demonstrates how you can stream data between Vitis kernels and AXI stream connections exposed in the platform. * - :doc:`PetaLinux Building and System Customization <./02_petalinux_customization/README>` - This tutorial demonstrates how you can customize a PetaLinux project to work for Vitis acceleration applications. * - :doc:`Hardware Design Fast Iteration with Vitis Export to Vivado <./03_Vitis_Export_To_Vivado/README>` - - The Vitis export to Vivado is the new feature release in the Vivado 2023.1 / Vitis 2023.1 suite that enables bi-directional hardware hand-offs between the Vitis tools and the Vivado design suite, which improves developer productivity. + - The Vitis export to AMD Vivado™ feature enables bi-directional hardware hand-offs between the Vitis tools and the Vivado design suite, which improves developer productivity. + + * - :doc:`Versal Extensible Hardware Design Validation <./04_platform_validation/README>` + - In this tutorial, you will learn how to validate an AMD Versal™ ACAP extensible platform. This tutorial is an **add-on** to the basic Versal platform creation tutorial. diff --git a/Vitis_Platform_Creation/Feature_Tutorials/README.md b/Vitis_Platform_Creation/Feature_Tutorials/README.md index 27814dd262..90ecb691bc 100644 --- a/Vitis_Platform_Creation/Feature_Tutorials/README.md +++ b/Vitis_Platform_Creation/Feature_Tutorials/README.md @@ -1,11 +1,11 @@ -

Vitis™ Platform Creation Tutorials

+

AMD Vitis™ Platform Creation Tutorials
-### Feature Tutorials +## Feature Tutorials These tutorials illustrate various platform features and how you can incorporate them into your own custom platforms. @@ -24,11 +24,11 @@ These tutorials illustrate various platform features and how you can incorporate Hardware Design Fast Iteration with Vitis Export to Vivado - The Vitis export to Vivado is the new feature release in the Vivado 2023.1 / Vitis 2023.1 suite that enables bi-directional hardware hand-offs between the Vitis tools and the Vivado design suite, which improves developer productivity. + The Vitis export to AMD Vivado™ feature enables bi-directional hardware hand-offs between the Vitis tools and the Vivado design suite, which improves developer productivity. Versal Extensible Hardware Design Validation - In this tutorial, you will learn how to validate a Versal® ACAP extensible platform. This tutorial is an 'add-on' to the basic Versal platform creation tutorial. + In this tutorial, you will learn how to validate an AMD Versal™ ACAP extensible platform. This tutorial is an add-on to the basic Versal platform creation tutorial. diff --git a/Vitis_Platform_Creation/README.md b/Vitis_Platform_Creation/README.md index 1682ca18ab..95c4c6b805 100644 --- a/Vitis_Platform_Creation/README.md +++ b/Vitis_Platform_Creation/README.md @@ -6,9 +6,9 @@ -## Vitis Platform Creation Tutorials +# Vitis Platform Creation Tutorials -### What is a Platform +## What is a Platform Before going to platform creation, Let's get an initial idea of platform. @@ -16,7 +16,7 @@ Before going to platform creation, Let's get an initial idea of platform. Briefly speaking, a platform is a package that contains the HPFM（`.xsa`）file and SPFM (software components). When you input the `.xsa` file and software components, the Vitis IDE tool will package them together and generate a platform `.xpfm` file, while the `.xsa` file is designed and exported from the AMD Vivado tool. Software components are prepared by AMD and ready to use for evaluation. Software components customization is also supported with Petalinux, if needed. -#### Platform Creation Example Quick Access +### Platform Creation Example Quick Access - For a first experience of platforms, refer to [Vitis Platform Quick Start](../Getting_Started/Vitis_Platform/) - For **ZYNQMP** device family, refer to [ZCU104 platform tutorial](./Design_Tutorials/02-Edge-AI-ZCU104/) @@ -25,7 +25,7 @@ Briefly speaking, a platform is a package that contains the HPFM（`.xsa`）file - For **SOM** series, refer to [KV260 platform tutorial](./Design_Tutorials/01-Edge-KV260/) - For **PetaLinux** customization, refer to [PetaLinux customization](./Feature_Tutorials/02_petalinux_customization/) -### Platform Creation Tutorials +## Platform Creation Tutorials The tutorials under the Vitis Platform Creation category help you learn how to develop an extensible platform for your own board, or customize the Vitis platform on Xilinx demo boards. @@ -33,7 +33,7 @@ The tutorials under the Vitis Platform Creation category help you learn how to d - The **[Feature Tutorials](./Feature_Tutorials/)** highlight specific features and flows that help develop the platform. -#### Design Tutorials +### Design Tutorials @@ -127,7 +127,7 @@ The tutorials under the Vitis Platform Creation category help you learn how to d
-#### Feature Tutorials +### Feature Tutorials These tutorials illustrate various platform features and how you can incorporate them into your own custom platforms. @@ -201,7 +201,7 @@ These tutorials illustrate various platform features and how you can incorporate -### Abbreviation +## Abbreviation - **XSA** : Vivado exported archive file that contains hardware information required for Vitis and PetaLinux - **DFX** ：Dynamic Function eXchange diff --git a/Vitis_Platform_Creation/Vitis_Platform_Creation.rst b/Vitis_Platform_Creation/Vitis_Platform_Creation.rst index e1c535965e..5833aeb369 100644 --- a/Vitis_Platform_Creation/Vitis_Platform_Creation.rst +++ b/Vitis_Platform_Creation/Vitis_Platform_Creation.rst @@ -11,11 +11,11 @@ What is a Platform? -.. image:: ./docs/XPFM.png +.. image:: ./docs/images/XPFM.png :alt: Vitis Platform -Briefly speaking, a platform is a package that contains the HPFM (``.xsa``) file and SPFM (software components). When you input the ``.xsa`` file and software components, the Vitis™ IDE tool will package them together and generate a platform ``.xpfm`` file, while the ``.xsa`` file is designed and exported from the AMD Vivado™ tool. Software components are prepared by AMD and ready to use for evaluation. Software components customization is also supported with Petalinux, if needed. +Briefly speaking, a platform is a package that contains the HPFM (``.xsa``) file and SPFM (software components). When you input the ``.xsa`` file and software components, the AMD Vitis™ IDE tool will package them together and generate a platform ``.xpfm`` file, while the ``.xsa`` file is designed and exported from the AMD Vivado™ tool. Software components are prepared by AMD and ready to use for evaluation. Software components customization is also supported with Petalinux, if needed. Platform Creation Example Quick Access @@ -55,13 +55,6 @@ Design Tutorials -.. note:: - - This design flow is applicable to most AMD demo boards. - - - - .. list-table:: :widths: 21 8 8 6 12 45 :header-rows: 1 @@ -73,7 +66,7 @@ Design Tutorials - IDE Flow - Design Target - * - :doc:`Versal Platform Creation Quick Start <./docs/Design_Tutorials/Vitis_Platform/README>` + * - `Vitis Platform Quick Start `_ - Versal AI Core - VCK190 - Flat @@ -87,6 +80,7 @@ Design Tutorials - **Hardware design**: Using Vivado Customizable Example Design template to quick start. - **Software design**: Using ``createdts`` and Common Image to quick start. - **Verification**: Vector Addition. + .. note:: This design flow is applicable to most AMD demo boards. @@ -105,7 +99,10 @@ Design Tutorials - **Hardware design**: Using Vivado Customizable Example Design (device part based) to create the hardware and do further customizations. - **Software design**: Using ``createdts`` and Common Image to quick start. - **Verification**: Vector Addition. - Note: This tutorial uses VCK190 board as a custom board. The design does not use any of its presets. + + .. note:: + + This tutorial uses VCK190 board as a custom board. The design does not use any of its presets. * - :doc:`Versal DFX Platform Creation Tutorial <./docs/Design_Tutorials/04_Edge_VCK190_DFX/README>` - Versal AI Core @@ -270,15 +267,6 @@ Feature Tutorials - - - - - - - - - .. sidebar:: More Information See Vitis Development Environment on `xilinx.com `_.