From 0733809a4dfc28d306806022f6f01d161113de0f Mon Sep 17 00:00:00 2001 From: Roopa Malavally <56051583+Rmalavally@users.noreply.github.com> Date: Sun, 31 May 2020 14:47:13 -0700 Subject: [PATCH] Update ROCm-Glossary.rst --- ROCm_Glossary/ROCm-Glossary.rst | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/ROCm_Glossary/ROCm-Glossary.rst b/ROCm_Glossary/ROCm-Glossary.rst index 2d6f0938..12214017 100644 --- a/ROCm_Glossary/ROCm-Glossary.rst +++ b/ROCm_Glossary/ROCm-Glossary.rst @@ -6,13 +6,11 @@ ROCm Glossary **host, host cpu** : Executes the HIP runtime API and is capable of initiating kernel launches to one or more devices. -**default device** : Each host thread maintains a “default device. Most HIP runtime APIs (including memory allocation, copy commands, kernel launches) do not use accept an explicit device argument but instead implicitly use the default device. The default device can be set with hipSetDevice. +**default device** : Each host thread maintains a default device. Most HIP runtime APIs (including memory allocation, copy commands, kernel launches) do not use accept an explicit device argument but instead implicitly use the default device. The default device can be set with hipSetDevice. **active host thread** - the thread which is running the HIP APIs -**completion_future** becomes ready, Completes. - -**HCC** = Heterogeneous Compute Compiler (https://github.com/RadeonOpenCompute/hcc). Starting ROCM v3.5 release, the HCC compiler is deprecated and HIP-Clang compiler is introduced for compiling HIP programs +**completion_future** becomes ready, "Completes". **HIP-Clang** - Heterogeneous AMDGPU Compiler, with its capability to compile HIP programs on AMD platform (https://github.com/RadeonOpenCompute/llvm-project). @@ -34,6 +32,10 @@ The HSA runtime is a thin, user-mode API that exposes the necessary interfaces t **HCC (Heterogeneous Compute Compiler) :** HCC is an Open Source, Optimizing C++ Compiler for Heterogeneous Compute. It supports heterogeneous offload to AMD APUs and discrete GPUs via HSA enabled runtimes and drivers.It is based on Clang, the LLVM Compiler Infrastructure and the 'libc++' C++ standard library.The goal is to implement a compiler that takes a program that conforms to a parallel programming standard such as C++ AMP, HC, C++ 17 ParallelSTL, or OpenMP, and transforms it into the AMD GCN ISA. +In the AMD ROCM v3.5 release, the HCC compiler is deprecated and HIP-Clang compiler is introduced for compiling HIP programs + +(https://github.com/RadeonOpenCompute/hcc) + Accelerator Modes Supported: * HC C++ API * HIP