[Project] Backend Miscompilation: overwrited sp

[sbkim28]

안녕하세요, 백엔드에서 miscompilation이 발생하는 것 같아 이를 제보하고자 합니다.

다음은 제가 임의로 작성한 c 코드입니다. 여기서 excessiveRegUse1과 excessiveRegUse2는 backend에서 register 할당 과정에 stack memory를 사용하도록 의도하는 목적으로 설계하였습니다.

void excessiveRegUse2(unsigned n, int64_t* a, int64_t* b) {
  for (unsigned i = 0; i < n; i += 16) {
    a[i] = b[i];
    a[i + 1] = b[i + 1];
    a[i + 2] = b[i + 2];
    a[i + 3] = b[i + 3];
    a[i + 4] = b[i + 4];
    a[i + 5] = b[i + 5];
    a[i + 6] = b[i + 6];
    a[i + 7] = b[i + 7];
    a[i + 8] = b[i + 8];
    a[i + 9] = b[i + 9];
    a[i + 10] = b[i + 10];
    a[i + 11] = b[i + 11];
    a[i + 12] = b[i + 12];
    a[i + 13] = b[i + 13];
    a[i + 14] = b[i + 14];
    a[i + 15] = b[i + 15];
  }

  write(1000);
  write(1001);
  write(1002);
  write(1003);
  write(2000);
  write(2001);
  write(2002);
  write(2003);
  write(3000);
  write(3001);
  write(3002);
  write(3003);
  write(4000);
  write(4001);
  write(4002);
  write(4003);
}

void excessiveRegUse1(unsigned n, int64_t* a, int64_t* b) {
  for (unsigned i = 0; i < n; i += 16) {
    a[i] = b[i];
    a[i + 1] = b[i + 1];
    a[i + 2] = b[i + 2];
    a[i + 3] = b[i + 3];
    a[i + 4] = b[i + 4];
    a[i + 5] = b[i + 5];
    a[i + 6] = b[i + 6];
    a[i + 7] = b[i + 7];
    a[i + 8] = b[i + 8];
    a[i + 9] = b[i + 9];
    a[i + 10] = b[i + 10];
    a[i + 11] = b[i + 11];
    a[i + 12] = b[i + 12];
    a[i + 13] = b[i + 13];
    a[i + 14] = b[i + 14];
    a[i + 15] = b[i + 15];
  }
  excessiveRegUse2(n, a, b);
  write(100);
  write(101);
  write(102);
  write(103);
  write(200);
  write(201);
  write(202);
  write(203);
  write(300);
  write(301);
  write(302);
  write(303);
  write(400);
  write(401);
  write(402);
  write(403);
}

int main() {
  int n = 16;
  int64_t* a = malloc(16 * n);
  int64_t* b = malloc(16 * n);
  excessiveRegUse1(n, a, b);
}

해당 코드를 실행시키면 다음과 같은 출력이 나옵니다.

1000 1001 1002 1003 2000 2001 2002 2003 3000 3001 3002 3003 4000 4001 4002 4003 
1000 101 1002 1003 200 201 202 203 300 301 302 303 400 401 402 403

일부 상수가 잘못된 값을 출력함을 확인할 수 있습니다.

다음은 어셈블리 코드를 살펴보았을 때 문제가 되는 부분입니다.

start excessiveRegUse2 3:
.entry:
sp = const 88
sp = sub sp sp 64
   (... omit ...)
start excessiveRegUse1 3:
.entry:
sp = const 88
sp = sub sp sp 64

sub sp sp 64에서 sp가 두 함수 모두 0이 되는데, 이게 의도하지 않은 동작으로 보입니다.

해당 문제를 확인해주셨으면 합니다. 감사합니다.

[sbkim28]

또한 추가로 해당 코드를 컴파일하였을 때 vector instruction을 사용하지 않았음에도 vbcast나 vstore와 같은 instruction이 생성됩니다.

vector move를 목적으로 사용된 constant 때문에 이 vector instruction들이 발생하는 것으로 추정되는데, 해당 vector instruction이 남아있는 것이 의도하신 동작인지 여쭙고자 합니다.

EDIT: 관련해서 확인해보니 num_general_colors와 num_vector_colors 둘 중 하나만 최대 register 개수를 초과하더라도, 두 종류의 register 모두에 대해서 load & store pair을 생성하고 있는 것 같습니다. 이게 의도하신 동작인지 궁금합니다.

[cr0sh]

@strikef 혹시 이 에러에 대해서는 별도의 처리가 필요하지 않을까요?

[cr0sh]

추가로 제보하자면, matmul3에서 동일한 유형의 오류가 발생하고 있는 상황입니다. (matmul 함수의 entry block에 sub sp sp 가 존재합니다.)

click to expand the full output

start matmul 4:
.entry:
sp = const 160
sp = sub sp sp 64
r1 = const 0
store 8 r1 sp
r2 = const 1
r1 = load 8 sp
r7 = mul r1 r2 32
r4 = const 8
r5 = const 2
r6 = const 3
r1 = const 4
r3 = const 72
r3 = add sp r3 64
store 8 r1 r3
v1 = vbcast r2 32
r1 = const 8
r1 = add sp r1 64
vstore v1 r1
v1 = vbcast r2 64
r1 = const 8
r1 = add sp r1 64
vstore v1 r1
br .for.cond
.for.cond:
r1 = icmp ult r7 arg1 32
br r1 .for.body .for.end425
.for.body:
r1 = load 8 sp
r3 = mul r1 r2 32
br .for.cond1
.for.cond1:
r1 = icmp ult r3 arg1 32
br r1 .for.body3 .for.end422
.for.body3:
r1 = load 8 sp
r8 = mul r1 r2 32
br .for.cond4
.for.cond4:
r1 = icmp ult r8 arg1 32
br r1 .for.body6 .for.end
.for.body6:
r1 = mul r7 arg1 32
r1 = add r1 r8 32
r1 = mul r1 r4 64
r1 = add arg3 r1 64
r9 = load 8 r1
r1 = mul r7 arg1 32
r1 = add r1 r8 32
r1 = add r1 r2 32
r1 = mul r1 r4 64
r1 = add arg3 r1 64
r10 = load 8 r1
r1 = mul r7 arg1 32
r1 = add r1 r8 32
r1 = add r1 r5 32
r1 = mul r1 r4 64
r1 = add arg3 r1 64
r11 = load 8 r1
r1 = const 80
r1 = add sp r1 64
store 8 r11 r1
r1 = mul r7 arg1 32
r1 = add r1 r8 32
r1 = add r1 r6 32
r1 = mul r1 r4 64
r1 = add arg3 r1 64
r11 = load 8 r1
r1 = const 88
r1 = add sp r1 64
store 8 r11 r1
r1 = add r7 r2 32
r1 = mul r1 arg1 32
r1 = add r1 r8 32
r1 = mul r1 r4 64
r1 = add arg3 r1 64
r11 = load 8 r1
r1 = const 96
r1 = add sp r1 64
store 8 r11 r1
r1 = add r7 r2 32
r1 = mul r1 arg1 32
r1 = add r1 r8 32
r1 = add r1 r2 32
r1 = mul r1 r4 64
r1 = add arg3 r1 64
r11 = load 8 r1
r1 = const 104
r1 = add sp r1 64
store 8 r11 r1
r1 = add r7 r2 32
r1 = mul r1 arg1 32
r1 = add r1 r8 32
r1 = add r1 r5 32
r1 = mul r1 r4 64
r1 = add arg3 r1 64
r11 = load 8 r1
r1 = const 112
r1 = add sp r1 64
store 8 r11 r1
r1 = add r7 r2 32
r1 = mul r1 arg1 32
r1 = add r1 r8 32
r1 = add r1 r6 32
r1 = mul r1 r4 64
r1 = add arg3 r1 64
r11 = load 8 r1
r1 = const 120
r1 = add sp r1 64
store 8 r11 r1
r1 = add r7 r5 32
r1 = mul r1 arg1 32
r1 = add r1 r8 32
r1 = mul r1 r4 64
r1 = add arg3 r1 64
r11 = load 8 r1
r1 = const 128
r1 = add sp r1 64
store 8 r11 r1
r1 = add r7 r5 32
r1 = mul r1 arg1 32
r1 = add r1 r8 32
r1 = add r1 r2 32
r1 = mul r1 r4 64
r1 = add arg3 r1 64
r11 = load 8 r1
r1 = const 136
r1 = add sp r1 64
store 8 r11 r1
r1 = add r7 r5 32
r1 = mul r1 arg1 32
r1 = add r1 r8 32
r1 = add r1 r5 32
r1 = mul r1 r4 64
r1 = add arg3 r1 64
r11 = load 8 r1
r1 = const 144
r1 = add sp r1 64
store 8 r11 r1
r1 = add r7 r5 32
r1 = mul r1 arg1 32
r1 = add r1 r8 32
r1 = add r1 r6 32
r1 = mul r1 r4 64
r1 = add arg3 r1 64
r11 = load 8 r1
r1 = const 152
r1 = add sp r1 64
store 8 r11 r1
r1 = add r7 r6 32
r1 = mul r1 arg1 32
r1 = add r1 r8 32
r1 = mul r1 r4 64
r1 = add arg3 r1 64
r11 = load 8 r1
r1 = add r7 r6 32
r1 = mul r1 arg1 32
r1 = add r1 r8 32
r1 = add r1 r2 32
r1 = mul r1 r4 64
r1 = add arg3 r1 64
r12 = load 8 r1
r1 = add r7 r6 32
r1 = mul r1 arg1 32
r1 = add r1 r8 32
r1 = add r1 r5 32
r1 = mul r1 r4 64
r1 = add arg3 r1 64
r13 = load 8 r1
r1 = add r7 r6 32
r1 = mul r1 arg1 32
r1 = add r1 r8 32
r1 = add r1 r6 32
r1 = mul r1 r4 64
r1 = add arg3 r1 64
r14 = load 8 r1
r1 = mul r8 arg1 32
r1 = add r1 r3 32
r1 = mul r1 r4 64
r1 = add arg4 r1 64
r15 = load 8 r1
r1 = mul r8 arg1 32
r1 = add r1 r3 32
r1 = add r1 r2 32
r1 = mul r1 r4 64
r1 = add arg4 r1 64
r16 = load 8 r1
r1 = mul r8 arg1 32
r1 = add r1 r3 32
r1 = add r1 r5 32
r1 = mul r1 r4 64
r1 = add arg4 r1 64
r17 = load 8 r1
r1 = mul r8 arg1 32
r1 = add r1 r3 32
r1 = add r1 r6 32
r1 = mul r1 r4 64
r1 = add arg4 r1 64
r18 = load 8 r1
r1 = add r8 r2 32
r1 = mul r1 arg1 32
r1 = add r1 r3 32
r1 = mul r1 r4 64
r1 = add arg4 r1 64
r19 = load 8 r1
r1 = add r8 r2 32
r1 = mul r1 arg1 32
r1 = add r1 r3 32
r1 = add r1 r2 32
r1 = mul r1 r4 64
r1 = add arg4 r1 64
r20 = load 8 r1
r1 = add r8 r2 32
r1 = mul r1 arg1 32
r1 = add r1 r3 32
r1 = add r1 r5 32
r1 = mul r1 r4 64
r1 = add arg4 r1 64
r21 = load 8 r1
r1 = add r8 r2 32
r1 = mul r1 arg1 32
r1 = add r1 r3 32
r1 = add r1 r6 32
r1 = mul r1 r4 64
r1 = add arg4 r1 64
r22 = load 8 r1
r1 = add r8 r5 32
r1 = mul r1 arg1 32
r1 = add r1 r3 32
r1 = mul r1 r4 64
r1 = add arg4 r1 64
r23 = load 8 r1
r1 = add r8 r5 32
r1 = mul r1 arg1 32
r1 = add r1 r3 32
r1 = add r1 r2 32
r1 = mul r1 r4 64
r1 = add arg4 r1 64
r24 = load 8 r1
r1 = add r8 r5 32
r1 = mul r1 arg1 32
r1 = add r1 r3 32
r1 = add r1 r5 32
r1 = mul r1 r4 64
r1 = add arg4 r1 64
r25 = load 8 r1
r1 = add r8 r5 32
r1 = mul r1 arg1 32
r1 = add r1 r3 32
r1 = add r1 r6 32
r1 = mul r1 r4 64
r1 = add arg4 r1 64
r26 = load 8 r1
r1 = add r8 r6 32
r1 = mul r1 arg1 32
r1 = add r1 r3 32
r1 = mul r1 r4 64
r1 = add arg4 r1 64
r27 = load 8 r1
r1 = add r8 r6 32
r1 = mul r1 arg1 32
r1 = add r1 r3 32
r1 = add r1 r2 32
r1 = mul r1 r4 64
r1 = add arg4 r1 64
r28 = load 8 r1
r1 = add r8 r6 32
r1 = mul r1 arg1 32
r1 = add r1 r3 32
r1 = add r1 r5 32
r1 = mul r1 r4 64
r1 = add arg4 r1 64
r29 = load 8 r1
r1 = add r8 r6 32
r1 = mul r1 arg1 32
r1 = add r1 r3 32
r1 = add r1 r6 32
r1 = mul r1 r4 64
r1 = add arg4 r1 64
r31 = load 8 r1
r1 = mul r9 r15 64
r30 = mul r10 r19 64
r30 = add r1 r30 64
r1 = const 80
r1 = add sp r1 64
r1 = load 8 r1
r1 = mul r1 r23 64
r30 = add r30 r1 64
r1 = const 88
r1 = add sp r1 64
r1 = load 8 r1
r1 = mul r1 r27 64
r30 = add r30 r1 64
r1 = mul r7 arg1 32
r1 = add r1 r3 32
r1 = mul r1 r4 64
r32 = add arg2 r1 64
r1 = load 8 r32
r1 = add r1 r30 64
store 8 r1 r32
r1 = mul r9 r16 64
r30 = mul r10 r20 64
r30 = add r1 r30 64
r1 = const 80
r1 = add sp r1 64
r1 = load 8 r1
r1 = mul r1 r24 64
r30 = add r30 r1 64
r1 = const 88
r1 = add sp r1 64
r1 = load 8 r1
r1 = mul r1 r28 64
r30 = add r30 r1 64
r1 = mul r7 arg1 32
r1 = add r1 r3 32
r1 = add r1 r2 32
r1 = mul r1 r4 64
r32 = add arg2 r1 64
r1 = load 8 r32
r1 = add r1 r30 64
store 8 r1 r32
r1 = mul r9 r17 64
r30 = mul r10 r21 64
r30 = add r1 r30 64
r1 = const 80
r1 = add sp r1 64
r1 = load 8 r1
r1 = mul r1 r25 64
r30 = add r30 r1 64
r1 = const 88
r1 = add sp r1 64
r1 = load 8 r1
r1 = mul r1 r29 64
r30 = add r30 r1 64
r1 = mul r7 arg1 32
r1 = add r1 r3 32
r1 = add r1 r5 32
r1 = mul r1 r4 64
r32 = add arg2 r1 64
r1 = load 8 r32
r1 = add r1 r30 64
store 8 r1 r32
r1 = mul r9 r18 64
r9 = mul r10 r22 64
r9 = add r1 r9 64
r1 = const 80
r1 = add sp r1 64
r1 = load 8 r1
r1 = mul r1 r26 64
r9 = add r9 r1 64
r1 = const 88
r1 = add sp r1 64
r1 = load 8 r1
r1 = mul r1 r31 64
r9 = add r9 r1 64
r1 = mul r7 arg1 32
r1 = add r1 r3 32
r1 = add r1 r6 32
r1 = mul r1 r4 64
r10 = add arg2 r1 64
r1 = load 8 r10
r1 = add r1 r9 64
store 8 r1 r10
r1 = const 96
r1 = add sp r1 64
r1 = load 8 r1
r9 = mul r1 r15 64
r1 = const 104
r1 = add sp r1 64
r1 = load 8 r1
r1 = mul r1 r19 64
r9 = add r9 r1 64
r1 = const 112
r1 = add sp r1 64
r1 = load 8 r1
r1 = mul r1 r23 64
r9 = add r9 r1 64
r1 = const 120
r1 = add sp r1 64
r1 = load 8 r1
r1 = mul r1 r27 64
r9 = add r9 r1 64
r1 = add r7 r2 32
r1 = mul r1 arg1 32
r1 = add r1 r3 32
r1 = mul r1 r4 64
r10 = add arg2 r1 64
r1 = load 8 r10
r1 = add r1 r9 64
store 8 r1 r10
r1 = const 96
r1 = add sp r1 64
r1 = load 8 r1
r9 = mul r1 r16 64
r1 = const 104
r1 = add sp r1 64
r1 = load 8 r1
r1 = mul r1 r20 64
r9 = add r9 r1 64
r1 = const 112
r1 = add sp r1 64
r1 = load 8 r1
r1 = mul r1 r24 64
r9 = add r9 r1 64
r1 = const 120
r1 = add sp r1 64
r1 = load 8 r1
r1 = mul r1 r28 64
r9 = add r9 r1 64
r1 = add r7 r2 32
r1 = mul r1 arg1 32
r1 = add r1 r3 32
r1 = add r1 r2 32
r1 = mul r1 r4 64
r10 = add arg2 r1 64
r1 = load 8 r10
r1 = add r1 r9 64
store 8 r1 r10
r1 = const 96
r1 = add sp r1 64
r1 = load 8 r1
r9 = mul r1 r17 64
r1 = const 104
r1 = add sp r1 64
r1 = load 8 r1
r1 = mul r1 r21 64
r9 = add r9 r1 64
r1 = const 112
r1 = add sp r1 64
r1 = load 8 r1
r1 = mul r1 r25 64
r9 = add r9 r1 64
r1 = const 120
r1 = add sp r1 64
r1 = load 8 r1
r1 = mul r1 r29 64
r9 = add r9 r1 64
r1 = add r7 r2 32
r1 = mul r1 arg1 32
r1 = add r1 r3 32
r1 = add r1 r5 32
r1 = mul r1 r4 64
r10 = add arg2 r1 64
r1 = load 8 r10
r1 = add r1 r9 64
store 8 r1 r10
r1 = const 96
r1 = add sp r1 64
r1 = load 8 r1
r9 = mul r1 r18 64
r1 = const 104
r1 = add sp r1 64
r1 = load 8 r1
r1 = mul r1 r22 64
r9 = add r9 r1 64
r1 = const 112
r1 = add sp r1 64
r1 = load 8 r1
r1 = mul r1 r26 64
r9 = add r9 r1 64
r1 = const 120
r1 = add sp r1 64
r1 = load 8 r1
r1 = mul r1 r31 64
r9 = add r9 r1 64
r1 = add r7 r2 32
r1 = mul r1 arg1 32
r1 = add r1 r3 32
r1 = add r1 r6 32
r1 = mul r1 r4 64
r10 = add arg2 r1 64
r1 = load 8 r10
r1 = add r1 r9 64
store 8 r1 r10
r1 = const 128
r1 = add sp r1 64
r1 = load 8 r1
r9 = mul r1 r15 64
r1 = const 136
r1 = add sp r1 64
r1 = load 8 r1
r1 = mul r1 r19 64
r9 = add r9 r1 64
r1 = const 144
r1 = add sp r1 64
r1 = load 8 r1
r1 = mul r1 r23 64
r9 = add r9 r1 64
r1 = const 152
r1 = add sp r1 64
r1 = load 8 r1
r1 = mul r1 r27 64
r9 = add r9 r1 64
r1 = add r7 r5 32
r1 = mul r1 arg1 32
r1 = add r1 r3 32
r1 = mul r1 r4 64
r10 = add arg2 r1 64
r1 = load 8 r10
r1 = add r1 r9 64
store 8 r1 r10
r1 = const 128
r1 = add sp r1 64
r1 = load 8 r1
r9 = mul r1 r16 64
r1 = const 136
r1 = add sp r1 64
r1 = load 8 r1
r1 = mul r1 r20 64
r9 = add r9 r1 64
r1 = const 144
r1 = add sp r1 64
r1 = load 8 r1
r1 = mul r1 r24 64
r9 = add r9 r1 64
r1 = const 152
r1 = add sp r1 64
r1 = load 8 r1
r1 = mul r1 r28 64
r9 = add r9 r1 64
r1 = add r7 r5 32
r1 = mul r1 arg1 32
r1 = add r1 r3 32
r1 = add r1 r2 32
r1 = mul r1 r4 64
r10 = add arg2 r1 64
r1 = load 8 r10
r1 = add r1 r9 64
store 8 r1 r10
r1 = const 128
r1 = add sp r1 64
r1 = load 8 r1
r9 = mul r1 r17 64
r1 = const 136
r1 = add sp r1 64
r1 = load 8 r1
r1 = mul r1 r21 64
r9 = add r9 r1 64
r1 = const 144
r1 = add sp r1 64
r1 = load 8 r1
r1 = mul r1 r25 64
r9 = add r9 r1 64
r1 = const 152
r1 = add sp r1 64
r1 = load 8 r1
r1 = mul r1 r29 64
r9 = add r9 r1 64
r1 = add r7 r5 32
r1 = mul r1 arg1 32
r1 = add r1 r3 32
r1 = add r1 r5 32
r1 = mul r1 r4 64
r10 = add arg2 r1 64
r1 = load 8 r10
r1 = add r1 r9 64
store 8 r1 r10
r1 = const 128
r1 = add sp r1 64
r1 = load 8 r1
r9 = mul r1 r18 64
r1 = const 136
r1 = add sp r1 64
r1 = load 8 r1
r1 = mul r1 r22 64
r9 = add r9 r1 64
r1 = const 144
r1 = add sp r1 64
r1 = load 8 r1
r1 = mul r1 r26 64
r9 = add r9 r1 64
r1 = const 152
r1 = add sp r1 64
r1 = load 8 r1
r1 = mul r1 r31 64
r9 = add r9 r1 64
r1 = add r7 r5 32
r1 = mul r1 arg1 32
r1 = add r1 r3 32
r1 = add r1 r6 32
r1 = mul r1 r4 64
r10 = add arg2 r1 64
r1 = load 8 r10
r1 = add r1 r9 64
store 8 r1 r10
r1 = mul r11 r15 64
r9 = mul r12 r19 64
r1 = add r1 r9 64
r9 = mul r13 r23 64
r1 = add r1 r9 64
r9 = mul r14 r27 64
r9 = add r1 r9 64
r1 = add r7 r6 32
r1 = mul r1 arg1 32
r1 = add r1 r3 32
r1 = mul r1 r4 64
r10 = add arg2 r1 64
r1 = load 8 r10
r1 = add r1 r9 64
store 8 r1 r10
r1 = mul r11 r16 64
r9 = mul r12 r20 64
r1 = add r1 r9 64
r9 = mul r13 r24 64
r1 = add r1 r9 64
r9 = mul r14 r28 64
r9 = add r1 r9 64
r1 = add r7 r6 32
r1 = mul r1 arg1 32
r1 = add r1 r3 32
r1 = add r1 r2 32
r1 = mul r1 r4 64
r10 = add arg2 r1 64
r1 = load 8 r10
r1 = add r1 r9 64
store 8 r1 r10
r1 = mul r11 r17 64
r9 = mul r12 r21 64
r1 = add r1 r9 64
r9 = mul r13 r25 64
r1 = add r1 r9 64
r9 = mul r14 r29 64
r9 = add r1 r9 64
r1 = add r7 r6 32
r1 = mul r1 arg1 32
r1 = add r1 r3 32
r1 = add r1 r5 32
r1 = mul r1 r4 64
r10 = add arg2 r1 64
r1 = load 8 r10
r1 = add r1 r9 64
store 8 r1 r10
r1 = mul r11 r18 64
r9 = mul r12 r22 64
r1 = add r1 r9 64
r9 = mul r13 r26 64
r1 = add r1 r9 64
r9 = mul r14 r31 64
r9 = add r1 r9 64
r1 = add r7 r6 32
r1 = mul r1 arg1 32
r1 = add r1 r3 32
r1 = add r1 r6 32
r1 = mul r1 r4 64
r10 = add arg2 r1 64
r1 = load 8 r10
r1 = add r1 r9 64
store 8 r1 r10
br .for.inc
.for.inc:
r1 = const 72
r1 = add sp r1 64
r1 = load 8 r1
r8 = add r8 r1 32
br .for.cond4
.for.end:
br .for.inc420
.for.inc420:
r1 = const 72
r1 = add sp r1 64
r1 = load 8 r1
r3 = add r3 r1 32
br .for.cond1
.for.end422:
br .for.inc423
.for.inc423:
r1 = const 72
r1 = add sp r1 64
r1 = load 8 r1
r7 = add r7 r1 32
br .for.cond
.for.end425:
ret
end matmul

start read_mat 2:
.entry:
r1 = const 0
r2 = const 1
r4 = mul r1 r2 32
r3 = const 8
br .for.cond
.for.cond:
r5 = icmp ult r4 arg1 32
br r5 .for.body .for.end6
.for.body:
r6 = mul r1 r2 32
br .for.cond1
.for.cond1:
r5 = icmp ult r6 arg1 32
br r5 .for.body3 .for.end
.for.body3:
r7 = call read
r5 = mul r4 arg1 32
r5 = add r5 r6 32
r5 = mul r5 r3 64
r5 = add arg2 r5 64
store 8 r7 r5
br .for.inc
.for.inc:
r6 = add r6 r2 32
br .for.cond1
.for.end:
br .for.inc4
.for.inc4:
r4 = add r4 r2 32
br .for.cond
.for.end6:
ret
end read_mat

start print_mat 2:
.entry:
r1 = const 0
r2 = const 1
r4 = mul r1 r2 32
r3 = const 8
br .for.cond
.for.cond:
r5 = icmp ult r4 arg1 32
br r5 .for.body .for.end6
.for.body:
r6 = mul r1 r2 32
br .for.cond1
.for.cond1:
r5 = icmp ult r6 arg1 32
br r5 .for.body3 .for.end
.for.body3:
r5 = mul r4 arg1 32
r5 = add r5 r6 32
r5 = mul r5 r3 64
r5 = add arg2 r5 64
r5 = load 8 r5
call write r5
br .for.inc
.for.inc:
r6 = add r6 r2 32
br .for.cond1
.for.end:
br .for.inc4
.for.inc4:
r4 = add r4 r2 32
br .for.cond
.for.end6:
ret
end print_mat

start main 0:
.entry:
r1 = call read
r2 = const 1
r3 = mul r1 r2 32
r1 = const 4
r1 = urem r3 r1 32
r4 = const 0
r1 = icmp ne r1 r4 32
r5 = const 8
br r1 .if.then .if.end
.if.then:
br .cleanup
.if.end:
r1 = mul r3 r3 32
r1 = mul r1 r5 64
r2 = malloc r1
r1 = mul r3 r3 32
r1 = mul r1 r5 64
r6 = malloc r1
r1 = mul r3 r3 32
r1 = mul r1 r5 64
r1 = malloc r1
call read_mat r3 r2
call read_mat r3 r6
call matmul r3 r1 r2 r6
call print_mat r3 r1
br .cleanup
.cleanup:
ret r4
end main

[strikef]

@sbkim28 @cr0sh 제가 Issue를 놓쳤네요... 일단 register allocation의 버그는 맞는 것 같습니다.