Class6-Sequential-Logic.md

CLASS 6 Sequential Logic

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Maximum Clock Frequency

$\displaystyle T_{Cmin} = t_{setup} + t_{ffpd(max)} + t_{comb(max)}$

$\displaystyle f_c = \frac{1}{T_c} \le \frac{1}{t_{setup} + t_{ffpd(max)} + t_{comb(max)}}$

Setup and Hold-time Violation

• Setup-time margin > 0

  $t_{clk} - t_{ffpd}(max) - t_{comb}(max) - t_{setup}$

  (ffpd: flip-flop propagation delay)

• Hold-time margin > 0

  $t_{ffpd}(min) + t_{comb}(min) - t_{hold}$

Multibit Registers and Latches

Constructing Counters

• Given Modulo-N counters, construct a Modulo-M counter

  • N > M

    1. Asynchronous reset: State SM -> S0 (immediately)
    2. Synchronous reset: State SM-1 -> S0

  • N < M

    multiple modulo-N counters

Shift Register

Self-correcting (Ring) Counter

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