Simulation inconsistency bug caused by path

[smlz123]

The relevant documents are as follows
synthesis_4693.zip

For experiments with different paths but the same actual simulation content, as shown in the figure above, there are inconsistencies, which is also very surprising to us.

The first path is '/doc/zh_zh/test'     
The second path is '/doc/zh_zh'    

[martinwhitaker]

The -y option specifies a path to a directory that is searched for library modules, not a path to a file. Furthermore, you are including syn_yosys.v in yosys_testbench.v, so what you actually need to do is use the -I option to specify a path to a directory that is searched for include files. Use man iverilog to get more details.

This command line should work

iverilog -o ./test/yosys_main2 -I ./test ./test/yosys_testbench.v

[martinwhitaker]

By the way, what version of iverilog are you using? Using the latest code from the master branch, your second example gives me the following output:

% iverilog -y ./test/syn_yosys.v ./test/yosys_testbench.v
./test/yosys_testbench.v:2: Include file syn_yosys.v not found
Preprocessor failed with 1 errors.

[smlz123]

My Icarus Verilog version is 11.0 (stable) .

[smlz123]

By the way, what version of iverilog are you using? Using the latest code from the master branch, your second example gives me the following output:

% iverilog -y ./test/syn_yosys.v ./test/yosys_testbench.v
./test/yosys_testbench.v:2: Include file syn_yosys.v not found
Preprocessor failed with 1 errors.

Is this an error in the iverilog simulation for this design?

[martinwhitaker]

It's an error in the usage of iverilog, as I have already explained. The first line of the yosys_testbench.v in the attached zip file is

`include "syn_yosys.v"

So unless syn_yosys.v is in the current working directory, the compiler needs to be told where to find it.

v11 gives same error message. Check that the files in your /doc/zh_zh/test directory are the same as the files in the attached zip file.