Iverilog as a Verilog parser to a graph structure

[fabiosur]

Hi! I have a question for my project I hope you will be able to help me!
I want to generate a graph structure of Verilog netlist. I would like the atomic logic gates as the vertices and all the links between these logic gates as the edges.
First of all, does this kind of project already exist?
If not, I have a problem managing the 'super gates' ( ivl_net_logic_t with a size ivl_logic_width()>1).
How can I get through the graph, I mean how can I reach the ivl_net_logic_t targets from an ivl_net_logic_t source which is a 'super gate'?
In the same way, is there an easier way to manage the Verilog arrays ( ivl_signal_t with ivl_signal_width()>1) than using ivl_lpm_t structure?

[caryr]

I do not know of any project like you are suggesting.

Look at the vlog95 target. It traverses most of the compiler structures and generates Verilog code that you should understand.

[fabiosur]

Thank you for your answer, unfortunately I have already looked at the vlog95 ... I do not want to traverse the structure scope by scope, but I would like to start from root input signals and follow the signal path to the outputs through the scope hierarchy

[caryr]

I do not think that is currently possible. I think your only choice to get what you want would be to build new data structures using the existing access methods and then traverse these new datastructures as you want.

[steveicarus]

There are various other code generator targets. You can look at the "stub" target which is a debug aid and scans the entire internal structure, and there is also the BIF code generator that generates gates. For what you want to do, I suspect you may want to generate your own graph using the provided information.

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On Tue, Dec 13, 2022 at 7:58 AM Cary R. ***@***.***> wrote: I do not think that is currently possible. I think your only choice to get what you want would be to build new data structures using the existing access methods and then traverse these new datastructures as you want. — Reply to this email directly, view it on GitHub <#814 (comment)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/AAACKMTAOD24NJDFC2YKU5TWNCMLJANCNFSM6AAAAAAS3WYFWM> . You are receiving this because you are subscribed to this thread.Message ID: ***@***.*** com>

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[fabiosur]

Thank you, in fact I have already looked at the others tgt to make my own, and unlike the others tgt like tgt-blif which traverse the structure scope by scope I try to follow a signal through the lpm CONCAT and VP.