From a1316e83dcb1e92fb52cc1d5d04a5bd066f14575 Mon Sep 17 00:00:00 2001 From: Max Ekman Date: Tue, 28 Apr 2020 19:33:46 +0200 Subject: [PATCH] Update to embedded-hal v1.0.0-alpha.1 --- Cargo.toml | 3 +- examples/delay-blinky.rs | 8 +- examples/pwm.rs | 6 +- examples/rng-display.rs | 2 +- examples/timer-syst.rs | 18 +-- src/adc.rs | 8 +- src/delay.rs | 38 ++++-- src/dwt.rs | 23 +++- src/gpio.rs | 46 +++---- src/i2c.rs | 15 +- src/prelude.rs | 8 +- src/pwm.rs | 287 ++++++++++++++++++++++----------------- src/qei.rs | 16 ++- src/rng.rs | 2 +- src/serial.rs | 40 +++--- src/spi.rs | 4 +- src/timer.rs | 30 ++-- src/watchdog.rs | 12 +- 18 files changed, 329 insertions(+), 237 deletions(-) diff --git a/Cargo.toml b/Cargo.toml index 73c11909..13c3e77d 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -48,8 +48,7 @@ default-features = false version = "1.0.2" [dependencies.embedded-hal] -features = ["unproven"] -version = "0.2.3" +version = "=1.0.0-alpha.1" [dev-dependencies] panic-semihosting = "0.5.3" diff --git a/examples/delay-blinky.rs b/examples/delay-blinky.rs index b9e94a68..4ebd3a5d 100644 --- a/examples/delay-blinky.rs +++ b/examples/delay-blinky.rs @@ -31,10 +31,10 @@ fn main() -> ! { loop { // On for 1s, off for 1s. - led.set_high().unwrap(); - delay.delay_ms(1000_u32); - led.set_low().unwrap(); - delay.delay_ms(1000_u32); + led.try_set_high().unwrap(); + delay.try_delay_ms(1000_u32).unwrap(); + led.try_set_low().unwrap(); + delay.try_delay_ms(1000_u32).unwrap(); } } diff --git a/examples/pwm.rs b/examples/pwm.rs index 66904fda..3c5096ca 100644 --- a/examples/pwm.rs +++ b/examples/pwm.rs @@ -24,9 +24,9 @@ fn main() -> ! { let pwm = pwm::tim1(dp.TIM1, channels, clocks, 20u32.khz()); let (mut ch1, _ch2) = pwm; - let max_duty = ch1.get_max_duty(); - ch1.set_duty(max_duty / 2); - ch1.enable(); + let max_duty = ch1.try_get_max_duty().unwrap(); + ch1.try_set_duty(max_duty / 2); + ch1.try_enable(); } loop { diff --git a/examples/rng-display.rs b/examples/rng-display.rs index c628c227..29955d19 100644 --- a/examples/rng-display.rs +++ b/examples/rng-display.rs @@ -99,7 +99,7 @@ fn main() -> ! { } disp.flush().unwrap(); //delay a little while between refreshes so the display is readable - delay_source.delay_ms(100u8); + delay_source.try_delay_ms(100u8).unwrap(); } } diff --git a/examples/timer-syst.rs b/examples/timer-syst.rs index 69f91c37..82daeceb 100644 --- a/examples/timer-syst.rs +++ b/examples/timer-syst.rs @@ -1,4 +1,4 @@ -//! Start and stop a periodic system timer. +//! Start and stop a periodic system timer.try_ //! //! This example should run on all stm32f4xx boards but it was tested with //! stm32f4-discovery board (model STM32F407G-DISC1). @@ -36,29 +36,29 @@ fn main() -> ! { hprintln!("hello!").unwrap(); // wait until timer expires - nb::block!(timer.wait()).unwrap(); + nb::block!(timer.try_wait()).unwrap(); hprintln!("timer expired 1").unwrap(); // the function syst() creates a periodic timer, so it is automatically // restarted - nb::block!(timer.wait()).unwrap(); + nb::block!(timer.try_wait()).unwrap(); hprintln!("timer expired 2").unwrap(); // cancel current timer - timer.cancel().unwrap(); + timer.try_cancel().unwrap(); // start it again - timer.start(24.hz()); - nb::block!(timer.wait()).unwrap(); + timer.try_start(24.hz()); + nb::block!(timer.try_wait()).unwrap(); hprintln!("timer expired 3").unwrap(); - timer.cancel().unwrap(); - let cancel_outcome = timer.cancel(); + timer.try_cancel().unwrap(); + let cancel_outcome = timer.try_cancel(); assert_eq!(cancel_outcome, Err(timer::Error::Disabled)); hprintln!("ehy, you cannot cancel a timer two times!").unwrap(); // this time the timer was not restarted, therefore this function should // wait forever - nb::block!(timer.wait()).unwrap(); + nb::block!(timer.try_wait()).unwrap(); // you should never see this print hprintln!("if you see this there is something wrong").unwrap(); panic!(); diff --git a/src/adc.rs b/src/adc.rs index 4b72ae36..0e68a718 100644 --- a/src/adc.rs +++ b/src/adc.rs @@ -26,7 +26,7 @@ macro_rules! adc_pins { $( impl Channel for $pin { type ID = u8; - fn channel() -> u8 { $chan } + const CHANNEL: Self::ID = $chan; } )+ }; @@ -665,7 +665,7 @@ macro_rules! adc { } let vref_cal = VrefCal::get().read(); - let vref_samp = self.read(&mut Vref).unwrap(); //This can't actually fail, it's just in a result to satisfy hal trait + let vref_samp = self.try_read(&mut Vref).unwrap(); //This can't actually fail, it's just in a result to satisfy hal trait self.calibrated_vdda = (VDDA_CALIB * u32::from(vref_cal)) / u32::from(vref_samp); if !vref_en { @@ -873,7 +873,7 @@ macro_rules! adc { } }); - let channel = CHANNEL::channel(); + let channel = CHANNEL::CHANNEL; //Set the channel in the right sequence field match sequence { @@ -976,7 +976,7 @@ macro_rules! adc { { type Error = (); - fn read(&mut self, pin: &mut PIN) -> nb::Result { + fn try_read(&mut self, pin: &mut PIN) -> nb::Result { let enabled = self.is_enabled(); if !enabled { self.enable(); diff --git a/src/delay.rs b/src/delay.rs index 56beca43..4092afc8 100644 --- a/src/delay.rs +++ b/src/delay.rs @@ -1,6 +1,8 @@ //! Delays use cast::u32; +use core::convert::Infallible; + use cortex_m::peripheral::syst::SystClkSource; use cortex_m::peripheral::SYST; @@ -28,25 +30,33 @@ impl Delay { } impl DelayMs for Delay { - fn delay_ms(&mut self, ms: u32) { - self.delay_us(ms * 1_000); + type Error = Infallible; + + fn try_delay_ms(&mut self, ms: u32) -> Result<(), Self::Error> { + self.try_delay_us(ms * 1_000) } } impl DelayMs for Delay { - fn delay_ms(&mut self, ms: u16) { - self.delay_ms(u32(ms)); + type Error = Infallible; + + fn try_delay_ms(&mut self, ms: u16) -> Result<(), Self::Error> { + self.try_delay_ms(u32(ms)) } } impl DelayMs for Delay { - fn delay_ms(&mut self, ms: u8) { - self.delay_ms(u32(ms)); + type Error = Infallible; + + fn try_delay_ms(&mut self, ms: u8) -> Result<(), Self::Error> { + self.try_delay_ms(u32(ms)) } } impl DelayUs for Delay { - fn delay_us(&mut self, us: u32) { + type Error = Infallible; + + fn try_delay_us(&mut self, us: u32) -> Result<(), Self::Error> { // The SysTick Reload Value register supports values between 1 and 0x00FFFFFF. const MAX_RVR: u32 = 0x00FF_FFFF; @@ -70,17 +80,23 @@ impl DelayUs for Delay { self.syst.disable_counter(); } + + Ok(()) } } impl DelayUs for Delay { - fn delay_us(&mut self, us: u16) { - self.delay_us(u32(us)) + type Error = Infallible; + + fn try_delay_us(&mut self, us: u16) -> Result<(), Self::Error> { + self.try_delay_us(u32(us)) } } impl DelayUs for Delay { - fn delay_us(&mut self, us: u8) { - self.delay_us(u32(us)) + type Error = Infallible; + + fn try_delay_us(&mut self, us: u8) -> Result<(), Self::Error> { + self.try_delay_us(u32(us)) } } diff --git a/src/dwt.rs b/src/dwt.rs index b650ecac..d83f6754 100644 --- a/src/dwt.rs +++ b/src/dwt.rs @@ -1,8 +1,11 @@ //! Debug and trace and stuff +use core::convert::Infallible; + use crate::rcc::Clocks; use crate::time::Hertz; use cortex_m::peripheral::{DCB, DWT}; + use embedded_hal::blocking::delay::{DelayMs, DelayUs}; pub trait DwtExt { @@ -65,13 +68,13 @@ pub struct Delay { } impl Delay { /// Delay for `ClockDuration::ticks` - pub fn delay(duration: ClockDuration) { + pub fn try_delay(duration: ClockDuration) -> Result<(), Infallible> { let ticks = duration.ticks as u64; - Delay::delay_ticks(DWT::get_cycle_count(), ticks); + Delay::try_delay_ticks(DWT::get_cycle_count(), ticks) } /// Delay ticks /// NOTE DCB and DWT need to be set up for this to work, so it is private - fn delay_ticks(mut start: u32, ticks: u64) { + fn try_delay_ticks(mut start: u32, ticks: u64) -> Result<(), Infallible> { if ticks < (core::u32::MAX / 2) as u64 { // Simple delay let ticks = ticks as u32; @@ -96,24 +99,30 @@ impl Delay { while (DWT::get_cycle_count().wrapping_sub(start)) > ticks {} } } + + Ok(()) } } // Implement DelayUs/DelayMs for various integer types impl> DelayUs for Delay { - fn delay_us(&mut self, us: T) { + type Error = Infallible; + + fn try_delay_us(&mut self, us: T) -> Result<(), Self::Error> { // Convert us to ticks let start = DWT::get_cycle_count(); let ticks = (us.into() * self.clock.0 as u64) / 1_000_000; - Delay::delay_ticks(start, ticks); + Delay::try_delay_ticks(start, ticks) } } impl> DelayMs for Delay { - fn delay_ms(&mut self, ms: T) { + type Error = Infallible; + + fn try_delay_ms(&mut self, ms: T) -> Result<(), Self::Error> { // Convert ms to ticks let start = DWT::get_cycle_count(); let ticks = (ms.into() * self.clock.0 as u64) / 1_000; - Delay::delay_ticks(start, ticks); + Delay::try_delay_ticks(start, ticks) } } diff --git a/src/gpio.rs b/src/gpio.rs index a57c8193..959a2158 100644 --- a/src/gpio.rs +++ b/src/gpio.rs @@ -244,7 +244,7 @@ macro_rules! gpio { use core::marker::PhantomData; use core::convert::Infallible; - use embedded_hal::digital::v2::{InputPin, OutputPin, StatefulOutputPin, toggleable}; + use embedded_hal::digital::{InputPin, OutputPin, StatefulOutputPin, toggleable}; use crate::stm32::$GPIOX; use crate::stm32::{RCC, EXTI, SYSCFG}; @@ -293,13 +293,13 @@ macro_rules! gpio { impl OutputPin for $PXx> { type Error = Infallible; - fn set_high(&mut self) -> Result<(), Self::Error> { + fn try_set_high(&mut self) -> Result<(), Self::Error> { // NOTE(unsafe) atomic write to a stateless register unsafe { (*$GPIOX::ptr()).bsrr.write(|w| w.bits(1 << self.i)) }; Ok(()) } - fn set_low(&mut self) -> Result<(), Self::Error> { + fn try_set_low(&mut self) -> Result<(), Self::Error> { // NOTE(unsafe) atomic write to a stateless register unsafe { (*$GPIOX::ptr()).bsrr.write(|w| w.bits(1 << (self.i + 16))) }; Ok(()) @@ -307,11 +307,11 @@ macro_rules! gpio { } impl StatefulOutputPin for $PXx> { - fn is_set_high(&self) -> Result { - self.is_set_low().map(|v| !v) + fn try_is_set_high(&self) -> Result { + self.try_is_set_low().map(|v| !v) } - fn is_set_low(&self) -> Result { + fn try_is_set_low(&self) -> Result { // NOTE(unsafe) atomic read with no side effects Ok(unsafe { (*$GPIOX::ptr()).odr.read().bits() & (1 << self.i) == 0 }) } @@ -322,11 +322,11 @@ macro_rules! gpio { impl InputPin for $PXx> { type Error = Infallible; - fn is_high(&self) -> Result { - self.is_low().map(|v| !v) + fn try_is_high(&self) -> Result { + self.try_is_low().map(|v| !v) } - fn is_low(&self) -> Result { + fn try_is_low(&self) -> Result { // NOTE(unsafe) atomic read with no side effects Ok(unsafe { (*$GPIOX::ptr()).idr.read().bits() & (1 << self.i) == 0 }) } @@ -335,11 +335,11 @@ macro_rules! gpio { impl InputPin for $PXx> { type Error = Infallible; - fn is_high(&self) -> Result { - self.is_low().map(|v| !v) + fn try_is_high(&self) -> Result { + self.try_is_low().map(|v| !v) } - fn is_low(&self) -> Result { + fn try_is_low(&self) -> Result { // NOTE(unsafe) atomic read with no side effects Ok(unsafe { (*$GPIOX::ptr()).idr.read().bits() & (1 << self.i) == 0 }) } @@ -754,13 +754,13 @@ macro_rules! gpio { impl OutputPin for $PXi> { type Error = Infallible; - fn set_high(&mut self) -> Result<(), Self::Error> { + fn try_set_high(&mut self) -> Result<(), Self::Error> { // NOTE(unsafe) atomic write to a stateless register unsafe { (*$GPIOX::ptr()).bsrr.write(|w| w.bits(1 << $i)) }; Ok(()) } - fn set_low(&mut self) -> Result<(), Self::Error> { + fn try_set_low(&mut self) -> Result<(), Self::Error> { // NOTE(unsafe) atomic write to a stateless register unsafe { (*$GPIOX::ptr()).bsrr.write(|w| w.bits(1 << ($i + 16))) }; Ok(()) @@ -768,11 +768,11 @@ macro_rules! gpio { } impl StatefulOutputPin for $PXi> { - fn is_set_high(&self) -> Result { - self.is_set_low().map(|v| !v) + fn try_is_set_high(&self) -> Result { + self.try_is_set_low().map(|v| !v) } - fn is_set_low(&self) -> Result { + fn try_is_set_low(&self) -> Result { // NOTE(unsafe) atomic read with no side effects Ok(unsafe { (*$GPIOX::ptr()).odr.read().bits() & (1 << $i) == 0 }) } @@ -783,11 +783,11 @@ macro_rules! gpio { impl InputPin for $PXi> { type Error = Infallible; - fn is_high(&self) -> Result { - self.is_low().map(|v| !v) + fn try_is_high(&self) -> Result { + self.try_is_low().map(|v| !v) } - fn is_low(&self) -> Result { + fn try_is_low(&self) -> Result { // NOTE(unsafe) atomic read with no side effects Ok(unsafe { (*$GPIOX::ptr()).idr.read().bits() & (1 << $i) == 0 }) } @@ -796,11 +796,11 @@ macro_rules! gpio { impl InputPin for $PXi> { type Error = Infallible; - fn is_high(&self) -> Result { - self.is_low().map(|v| !v) + fn try_is_high(&self) -> Result { + self.try_is_low().map(|v| !v) } - fn is_low(&self) -> Result { + fn try_is_low(&self) -> Result { // NOTE(unsafe) atomic read with no side effects Ok(unsafe { (*$GPIOX::ptr()).idr.read().bits() & (1 << $i) == 0 }) } diff --git a/src/i2c.rs b/src/i2c.rs index 8d7c3eb3..140f913c 100644 --- a/src/i2c.rs +++ b/src/i2c.rs @@ -905,9 +905,14 @@ where { type Error = Error; - fn write_read(&mut self, addr: u8, bytes: &[u8], buffer: &mut [u8]) -> Result<(), Self::Error> { - self.write_bytes(addr, bytes)?; - self.read(addr, buffer)?; + fn try_write_read( + &mut self, + addr: u8, + bytes: &[u8], + buffer: &mut [u8], + ) -> Result<(), Self::Error> { + self.try_write(addr, bytes)?; + self.try_read(addr, buffer)?; Ok(()) } @@ -919,7 +924,7 @@ where { type Error = Error; - fn write(&mut self, addr: u8, bytes: &[u8]) -> Result<(), Self::Error> { + fn try_write(&mut self, addr: u8, bytes: &[u8]) -> Result<(), Self::Error> { self.write_bytes(addr, bytes)?; // Send a STOP condition @@ -939,7 +944,7 @@ where { type Error = Error; - fn read(&mut self, addr: u8, buffer: &mut [u8]) -> Result<(), Self::Error> { + fn try_read(&mut self, addr: u8, buffer: &mut [u8]) -> Result<(), Self::Error> { if let Some((last, buffer)) = buffer.split_last_mut() { // Send a START condition and set ACK bit self.i2c diff --git a/src/prelude.rs b/src/prelude.rs index f4dd80fc..52b26883 100644 --- a/src/prelude.rs +++ b/src/prelude.rs @@ -1,7 +1,7 @@ -pub use embedded_hal::digital::v2::InputPin as _embedded_hal_digital_v2_InputPin; -pub use embedded_hal::digital::v2::OutputPin as _embedded_hal_digital_v2_OutputPin; -pub use embedded_hal::digital::v2::StatefulOutputPin as _embedded_hal_digital_v2_StatefulOutputPin; -pub use embedded_hal::digital::v2::ToggleableOutputPin as _embedded_hal_digital_v2_ToggleableOutputPin; +pub use embedded_hal::digital::InputPin as _embedded_hal_digital_v2_InputPin; +pub use embedded_hal::digital::OutputPin as _embedded_hal_digital_v2_OutputPin; +pub use embedded_hal::digital::StatefulOutputPin as _embedded_hal_digital_v2_StatefulOutputPin; +pub use embedded_hal::digital::ToggleableOutputPin as _embedded_hal_digital_v2_ToggleableOutputPin; pub use embedded_hal::prelude::*; #[cfg(all( diff --git a/src/pwm.rs b/src/pwm.rs index c3740403..194d4cc0 100644 --- a/src/pwm.rs +++ b/src/pwm.rs @@ -1,4 +1,5 @@ use cast::{u16, u32}; +use core::convert::Infallible; use core::{marker::PhantomData, mem::MaybeUninit}; #[cfg(any( @@ -220,119 +221,135 @@ macro_rules! pwm_all_channels { unsafe { MaybeUninit::uninit().assume_init() } } - impl hal::PwmPin for PwmChannels<$TIMX, C1> { + impl hal::pwm::PwmPin for PwmChannels<$TIMX, C1> { + type Error = Infallible; type Duty = u16; //NOTE(unsafe) atomic write with no side effects - fn disable(&mut self) { - unsafe { bb::clear(&(*$TIMX::ptr()).ccer, 0) } + fn try_disable(&mut self) -> Result<(), Self::Error> { + unsafe { bb::clear(&(*$TIMX::ptr()).ccer, 0) }; + Ok(()) } //NOTE(unsafe) atomic write with no side effects - fn enable(&mut self) { - unsafe { bb::set(&(*$TIMX::ptr()).ccer, 0) } + fn try_enable(&mut self) -> Result<(), Self::Error> { + unsafe { bb::set(&(*$TIMX::ptr()).ccer, 0) }; + Ok(()) } //NOTE(unsafe) atomic read with no side effects - fn get_duty(&self) -> u16 { - unsafe { (*$TIMX::ptr()).ccr1.read().ccr().bits() as u16 } + fn try_get_duty(&self) -> Result { + Ok(unsafe { (*$TIMX::ptr()).ccr1.read().ccr().bits() as u16 }) } //NOTE(unsafe) atomic read with no side effects - fn get_max_duty(&self) -> u16 { - unsafe { (*$TIMX::ptr()).arr.read().arr().bits() as u16 } + fn try_get_max_duty(&self) -> Result { + Ok(unsafe { (*$TIMX::ptr()).arr.read().arr().bits() as u16 }) } //NOTE(unsafe) atomic write with no side effects - fn set_duty(&mut self, duty: u16) { - unsafe { (*$TIMX::ptr()).ccr1.write(|w| w.ccr().bits(duty.into())) } + fn try_set_duty(&mut self, duty: u16) -> Result<(), Self::Error> { + unsafe { (*$TIMX::ptr()).ccr1.write(|w| w.ccr().bits(duty.into())) }; + Ok(()) } } - impl hal::PwmPin for PwmChannels<$TIMX, C2> { + impl hal::pwm::PwmPin for PwmChannels<$TIMX, C2> { + type Error = Infallible; type Duty = u16; //NOTE(unsafe) atomic write with no side effects - fn disable(&mut self) { - unsafe { bb::clear(&(*$TIMX::ptr()).ccer, 4) } + fn try_disable(&mut self) -> Result<(), Self::Error> { + unsafe { bb::clear(&(*$TIMX::ptr()).ccer, 4) }; + Ok(()) } //NOTE(unsafe) atomic write with no side effects - fn enable(&mut self) { - unsafe { bb::set(&(*$TIMX::ptr()).ccer, 4) } + fn try_enable(&mut self) -> Result<(), Self::Error> { + unsafe { bb::set(&(*$TIMX::ptr()).ccer, 4) }; + Ok(()) } //NOTE(unsafe) atomic read with no side effects - fn get_duty(&self) -> u16 { - unsafe { (*$TIMX::ptr()).ccr2.read().ccr().bits() as u16 } + fn try_get_duty(&self) -> Result { + Ok(unsafe { (*$TIMX::ptr()).ccr2.read().ccr().bits() as u16 }) } //NOTE(unsafe) atomic read with no side effects - fn get_max_duty(&self) -> u16 { - unsafe { (*$TIMX::ptr()).arr.read().arr().bits() as u16 } + fn try_get_max_duty(&self) -> Result { + Ok(unsafe { (*$TIMX::ptr()).arr.read().arr().bits() as u16 }) } //NOTE(unsafe) atomic write with no side effects - fn set_duty(&mut self, duty: u16) { - unsafe { (*$TIMX::ptr()).ccr2.write(|w| w.ccr().bits(duty.into())) } + fn try_set_duty(&mut self, duty: u16) -> Result<(), Self::Error> { + unsafe { (*$TIMX::ptr()).ccr2.write(|w| w.ccr().bits(duty.into())) }; + Ok(()) } } - impl hal::PwmPin for PwmChannels<$TIMX, C3> { + impl hal::pwm::PwmPin for PwmChannels<$TIMX, C3> { + type Error = Infallible; type Duty = u16; //NOTE(unsafe) atomic write with no side effects - fn disable(&mut self) { - unsafe { bb::clear(&(*$TIMX::ptr()).ccer, 8) } + fn try_disable(&mut self) -> Result<(), Self::Error> { + unsafe { bb::clear(&(*$TIMX::ptr()).ccer, 8) }; + Ok(()) } //NOTE(unsafe) atomic write with no side effects - fn enable(&mut self) { - unsafe { bb::set(&(*$TIMX::ptr()).ccer, 8) } + fn try_enable(&mut self) -> Result<(), Self::Error> { + unsafe { bb::set(&(*$TIMX::ptr()).ccer, 8) }; + Ok(()) } //NOTE(unsafe) atomic read with no side effects - fn get_duty(&self) -> u16 { - unsafe { (*$TIMX::ptr()).ccr3.read().ccr().bits() as u16 } + fn try_get_duty(&self) -> Result { + Ok(unsafe { (*$TIMX::ptr()).ccr3.read().ccr().bits() as u16 }) } //NOTE(unsafe) atomic read with no side effects - fn get_max_duty(&self) -> u16 { - unsafe { (*$TIMX::ptr()).arr.read().arr().bits() as u16 } + fn try_get_max_duty(&self) -> Result { + Ok(unsafe { (*$TIMX::ptr()).arr.read().arr().bits() as u16 }) } //NOTE(unsafe) atomic write with no side effects - fn set_duty(&mut self, duty: u16) { - unsafe { (*$TIMX::ptr()).ccr3.write(|w| w.ccr().bits(duty.into())) } + fn try_set_duty(&mut self, duty: u16) -> Result<(), Self::Error> { + unsafe { (*$TIMX::ptr()).ccr3.write(|w| w.ccr().bits(duty.into())) }; + Ok(()) } } - impl hal::PwmPin for PwmChannels<$TIMX, C4> { + impl hal::pwm::PwmPin for PwmChannels<$TIMX, C4> { + type Error = Infallible; type Duty = u16; //NOTE(unsafe) atomic write with no side effects - fn disable(&mut self) { - unsafe { bb::clear(&(*$TIMX::ptr()).ccer, 12) } + fn try_disable(&mut self) -> Result<(), Self::Error> { + unsafe { bb::clear(&(*$TIMX::ptr()).ccer, 12) }; + Ok(()) } //NOTE(unsafe) atomic write with no side effects - fn enable(&mut self) { - unsafe { bb::set(&(*$TIMX::ptr()).ccer, 12) } + fn try_enable(&mut self) -> Result<(), Self::Error> { + unsafe { bb::set(&(*$TIMX::ptr()).ccer, 12) }; + Ok(()) } //NOTE(unsafe) atomic read with no side effects - fn get_duty(&self) -> u16 { - unsafe { (*$TIMX::ptr()).ccr4.read().ccr().bits() as u16 } + fn try_get_duty(&self) -> Result { + Ok(unsafe { (*$TIMX::ptr()).ccr4.read().ccr().bits() as u16 }) } //NOTE(unsafe) atomic read with no side effects - fn get_max_duty(&self) -> u16 { - unsafe { (*$TIMX::ptr()).arr.read().arr().bits() as u16 } + fn try_get_max_duty(&self) -> Result { + Ok(unsafe { (*$TIMX::ptr()).arr.read().arr().bits() as u16 }) } //NOTE(unsafe) atomic write with no side effects - fn set_duty(&mut self, duty: u16) { - unsafe { (*$TIMX::ptr()).ccr4.write(|w| w.ccr().bits(duty.into())) } + fn try_set_duty(&mut self, duty: u16) -> Result<(), Self::Error> { + unsafe { (*$TIMX::ptr()).ccr4.write(|w| w.ccr().bits(duty.into())) }; + Ok(()) } } )+ @@ -397,61 +414,69 @@ macro_rules! pwm_2_channels { unsafe { MaybeUninit::uninit().assume_init() } } - impl hal::PwmPin for PwmChannels<$TIMX, C1> { + impl hal::pwm::PwmPin for PwmChannels<$TIMX, C1> { + type Error = Infallible; type Duty = u16; //NOTE(unsafe) atomic write with no side effects - fn disable(&mut self) { - unsafe { bb::clear(&(*$TIMX::ptr()).ccer, 0) } + fn try_disable(&mut self) -> Result<(), Self::Error> { + unsafe { bb::clear(&(*$TIMX::ptr()).ccer, 0) }; + Ok(()) } //NOTE(unsafe) atomic write with no side effects - fn enable(&mut self) { - unsafe { bb::set(&(*$TIMX::ptr()).ccer, 0) } + fn try_enable(&mut self) -> Result<(), Self::Error> { + unsafe { bb::set(&(*$TIMX::ptr()).ccer, 0) }; + Ok(()) } //NOTE(unsafe) atomic read with no side effects - fn get_duty(&self) -> u16 { - unsafe { (*$TIMX::ptr()).ccr1.read().ccr().bits() as u16 } + fn try_get_duty(&self) -> Result { + Ok(unsafe { (*$TIMX::ptr()).ccr1.read().ccr().bits() as u16 }) } //NOTE(unsafe) atomic read with no side effects - fn get_max_duty(&self) -> u16 { - unsafe { (*$TIMX::ptr()).arr.read().arr().bits() as u16 } + fn try_get_max_duty(&self) -> Result { + Ok(unsafe { (*$TIMX::ptr()).arr.read().arr().bits() as u16 }) } //NOTE(unsafe) atomic write with no side effects - fn set_duty(&mut self, duty: u16) { - unsafe { (*$TIMX::ptr()).ccr1.write(|w| w.ccr().bits(duty.into())) } + fn try_set_duty(&mut self, duty: u16) -> Result<(), Self::Error> { + unsafe { (*$TIMX::ptr()).ccr1.write(|w| w.ccr().bits(duty.into())) }; + Ok(()) } } - impl hal::PwmPin for PwmChannels<$TIMX, C2> { + impl hal::pwm::PwmPin for PwmChannels<$TIMX, C2> { + type Error = Infallible; type Duty = u16; //NOTE(unsafe) atomic write with no side effects - fn disable(&mut self) { - unsafe { bb::clear(&(*$TIMX::ptr()).ccer, 4) } + fn try_disable(&mut self) -> Result<(), Self::Error> { + unsafe { bb::clear(&(*$TIMX::ptr()).ccer, 4) }; + Ok(()) } //NOTE(unsafe) atomic write with no side effects - fn enable(&mut self) { - unsafe { bb::set(&(*$TIMX::ptr()).ccer, 4) } + fn try_enable(&mut self) -> Result<(), Self::Error> { + unsafe { bb::set(&(*$TIMX::ptr()).ccer, 4) }; + Ok(()) } //NOTE(unsafe) atomic read with no side effects - fn get_duty(&self) -> u16 { - unsafe { (*$TIMX::ptr()).ccr2.read().ccr().bits() as u16 } + fn try_get_duty(&self) -> Result { + Ok(unsafe { (*$TIMX::ptr()).ccr2.read().ccr().bits() as u16 }) } //NOTE(unsafe) atomic read with no side effects - fn get_max_duty(&self) -> u16 { - unsafe { (*$TIMX::ptr()).arr.read().arr().bits() as u16 } + fn try_get_max_duty(&self) -> Result { + Ok(unsafe { (*$TIMX::ptr()).arr.read().arr().bits() as u16 }) } //NOTE(unsafe) atomic write with no side effects - fn set_duty(&mut self, duty: u16) { - unsafe { (*$TIMX::ptr()).ccr2.write(|w| w.ccr().bits(duty.into())) } + fn try_set_duty(&mut self, duty: u16) -> Result<(), Self::Error> { + unsafe { (*$TIMX::ptr()).ccr2.write(|w| w.ccr().bits(duty.into())) }; + Ok(()) } } )+ @@ -509,32 +534,36 @@ macro_rules! pwm_1_channel { unsafe { MaybeUninit::uninit().assume_init() } } - impl hal::PwmPin for PwmChannels<$TIMX, C1> { + impl hal::pwm::PwmPin for PwmChannels<$TIMX, C1> { + type Error = Infallible; type Duty = u16; //NOTE(unsafe) atomic write with no side effects - fn disable(&mut self) { - unsafe { bb::clear(&(*$TIMX::ptr()).ccer, 0) } + fn try_disable(&mut self) -> Result<(), Self::Error> { + unsafe { bb::clear(&(*$TIMX::ptr()).ccer, 0) }; + Ok(()) } //NOTE(unsafe) atomic write with no side effects - fn enable(&mut self) { - unsafe { bb::set(&(*$TIMX::ptr()).ccer, 0) } + fn try_enable(&mut self) -> Result<(), Self::Error> { + unsafe { bb::set(&(*$TIMX::ptr()).ccer, 0) }; + Ok(()) } //NOTE(unsafe) atomic read with no side effects - fn get_duty(&self) -> u16 { - unsafe { (*$TIMX::ptr()).ccr1.read().ccr().bits() as u16 } + fn try_get_duty(&self) -> Result { + Ok(unsafe { (*$TIMX::ptr()).ccr1.read().ccr().bits() as u16 }) } //NOTE(unsafe) atomic read with no side effects - fn get_max_duty(&self) -> u16 { - unsafe { (*$TIMX::ptr()).arr.read().arr().bits() as u16 } + fn try_get_max_duty(&self) -> Result { + Ok(unsafe { (*$TIMX::ptr()).arr.read().arr().bits() as u16 }) } //NOTE(unsafe) atomic write with no side effects - fn set_duty(&mut self, duty: u16) { - unsafe { (*$TIMX::ptr()).ccr1.write(|w| w.ccr().bits(duty.into())) } + fn try_set_duty(&mut self, duty: u16) -> Result<(), Self::Error> { + unsafe { (*$TIMX::ptr()).ccr1.write(|w| w.ccr().bits(duty.into())) }; + Ok(()) } } )+ @@ -608,119 +637,135 @@ macro_rules! pwm_tim5_f410 { unsafe { MaybeUninit::uninit().assume_init() } } - impl hal::PwmPin for PwmChannels<$TIMX, C1> { + impl hal::pwm::PwmPin for PwmChannels<$TIMX, C1> { + type Error = Infallible; type Duty = u16; //NOTE(unsafe) atomic write with no side effects - fn disable(&mut self) { - unsafe { bb::clear(&(*$TIMX::ptr()).ccer, 0) } + fn try_disable(&mut self) -> Result<(), Self::Error> { + unsafe { bb::clear(&(*$TIMX::ptr()).ccer, 0) }; + Ok(()) } //NOTE(unsafe) atomic write with no side effects - fn enable(&mut self) { - unsafe { bb::set(&(*$TIMX::ptr()).ccer, 0) } + fn try_enable(&mut self) -> Result<(), Self::Error> { + unsafe { bb::set(&(*$TIMX::ptr()).ccer, 0) }; + Ok(()) } //NOTE(unsafe) atomic read with no side effects - fn get_duty(&self) -> u16 { - unsafe { (*$TIMX::ptr()).ccr1.read().ccr1_l().bits() as u16 } + fn try_get_duty(&self) -> Result { + Ok(unsafe { (*$TIMX::ptr()).ccr1.read().ccr1_l().bits() as u16 }) } //NOTE(unsafe) atomic read with no side effects - fn get_max_duty(&self) -> u16 { - unsafe { (*$TIMX::ptr()).arr.read().arr_l().bits() as u16 } + fn try_get_max_duty(&self) -> Result { + Ok(unsafe { (*$TIMX::ptr()).arr.read().arr_l().bits() as u16 }) } //NOTE(unsafe) atomic write with no side effects - fn set_duty(&mut self, duty: u16) { - unsafe { (*$TIMX::ptr()).ccr1.write(|w| w.ccr1_l().bits(duty.into())) } + fn try_set_duty(&mut self, duty: u16) -> Result<(), Self::Error> { + unsafe { (*$TIMX::ptr()).ccr1.write(|w| w.ccr1_l().bits(duty.into())) }; + Ok(()) } } - impl hal::PwmPin for PwmChannels<$TIMX, C2> { + impl hal::pwm::PwmPin for PwmChannels<$TIMX, C2> { + type Error = Infallible; type Duty = u16; //NOTE(unsafe) atomic write with no side effects - fn disable(&mut self) { - unsafe { bb::clear(&(*$TIMX::ptr()).ccer, 4) } + fn try_disable(&mut self) -> Result<(), Self::Error> { + unsafe { bb::clear(&(*$TIMX::ptr()).ccer, 4) }; + Ok(()) } //NOTE(unsafe) atomic write with no side effects - fn enable(&mut self) { - unsafe { bb::set(&(*$TIMX::ptr()).ccer, 4) } + fn try_enable(&mut self) -> Result<(), Self::Error> { + unsafe { bb::set(&(*$TIMX::ptr()).ccer, 4) }; + Ok(()) } //NOTE(unsafe) atomic read with no side effects - fn get_duty(&self) -> u16 { - unsafe { (*$TIMX::ptr()).ccr2.read().ccr1_l().bits() as u16 } + fn try_get_duty(&self) -> Result { + Ok(unsafe { (*$TIMX::ptr()).ccr2.read().ccr1_l().bits() as u16 }) } //NOTE(unsafe) atomic read with no side effects - fn get_max_duty(&self) -> u16 { - unsafe { (*$TIMX::ptr()).arr.read().arr_l().bits() as u16 } + fn try_get_max_duty(&self) -> Result { + Ok(unsafe { (*$TIMX::ptr()).arr.read().arr_l().bits() as u16 }) } //NOTE(unsafe) atomic write with no side effects - fn set_duty(&mut self, duty: u16) { - unsafe { (*$TIMX::ptr()).ccr2.write(|w| w.ccr1_l().bits(duty.into())) } + fn try_set_duty(&mut self, duty: u16) -> Result<(), Self::Error> { + unsafe { (*$TIMX::ptr()).ccr2.write(|w| w.ccr1_l().bits(duty.into())) }; + Ok(()) } } - impl hal::PwmPin for PwmChannels<$TIMX, C3> { + impl hal::pwm::PwmPin for PwmChannels<$TIMX, C3> { + type Error = Infallible; type Duty = u16; //NOTE(unsafe) atomic write with no side effects - fn disable(&mut self) { - unsafe { bb::clear(&(*$TIMX::ptr()).ccer, 8) } + fn try_disable(&mut self) -> Result<(), Self::Error> { + unsafe { bb::clear(&(*$TIMX::ptr()).ccer, 8) }; + Ok(()) } //NOTE(unsafe) atomic write with no side effects - fn enable(&mut self) { - unsafe { bb::set(&(*$TIMX::ptr()).ccer, 8) } + fn try_enable(&mut self) -> Result<(), Self::Error> { + unsafe { bb::set(&(*$TIMX::ptr()).ccer, 8) }; + Ok(()) } //NOTE(unsafe) atomic read with no side effects - fn get_duty(&self) -> u16 { - unsafe { (*$TIMX::ptr()).ccr3.read().ccr1_l().bits() as u16 } + fn try_get_duty(&self) -> Result { + Ok(unsafe { (*$TIMX::ptr()).ccr3.read().ccr1_l().bits() as u16 }) } //NOTE(unsafe) atomic read with no side effects - fn get_max_duty(&self) -> u16 { - unsafe { (*$TIMX::ptr()).arr.read().arr_l().bits() as u16 } + fn try_get_max_duty(&self) -> Result { + Ok(unsafe { (*$TIMX::ptr()).arr.read().arr_l().bits() as u16 }) } //NOTE(unsafe) atomic write with no side effects - fn set_duty(&mut self, duty: u16) { - unsafe { (*$TIMX::ptr()).ccr3.write(|w| w.ccr1_l().bits(duty.into())) } + fn try_set_duty(&mut self, duty: u16) -> Result<(), Self::Error> { + unsafe { (*$TIMX::ptr()).ccr3.write(|w| w.ccr1_l().bits(duty.into())) }; + Ok(()) } } - impl hal::PwmPin for PwmChannels<$TIMX, C4> { + impl hal::pwm::PwmPin for PwmChannels<$TIMX, C4> { + type Error = Infallible; type Duty = u16; //NOTE(unsafe) atomic write with no side effects - fn disable(&mut self) { - unsafe { bb::clear(&(*$TIMX::ptr()).ccer, 12) } + fn try_disable(&mut self) -> Result<(), Self::Error> { + unsafe { bb::clear(&(*$TIMX::ptr()).ccer, 12) }; + Ok(()) } //NOTE(unsafe) atomic write with no side effects - fn enable(&mut self) { - unsafe { bb::set(&(*$TIMX::ptr()).ccer, 12) } + fn try_enable(&mut self) -> Result<(), Self::Error> { + unsafe { bb::set(&(*$TIMX::ptr()).ccer, 12) }; + Ok(()) } //NOTE(unsafe) atomic read with no side effects - fn get_duty(&self) -> u16 { - unsafe { (*$TIMX::ptr()).ccr4.read().ccr1_l().bits() as u16 } + fn try_get_duty(&self) -> Result { + Ok(unsafe { (*$TIMX::ptr()).ccr4.read().ccr1_l().bits() as u16 }) } //NOTE(unsafe) atomic read with no side effects - fn get_max_duty(&self) -> u16 { - unsafe { (*$TIMX::ptr()).arr.read().arr_l().bits() as u16 } + fn try_get_max_duty(&self) -> Result { + Ok(unsafe { (*$TIMX::ptr()).arr.read().arr_l().bits() as u16 }) } //NOTE(unsafe) atomic write with no side effects - fn set_duty(&mut self, duty: u16) { - unsafe { (*$TIMX::ptr()).ccr4.write(|w| w.ccr1_l().bits(duty.into())) } + fn try_set_duty(&mut self, duty: u16) -> Result<(), Self::Error> { + unsafe { (*$TIMX::ptr()).ccr4.write(|w| w.ccr1_l().bits(duty.into())) }; + Ok(()) } } )+ diff --git a/src/qei.rs b/src/qei.rs index 3a90c831..79f9ca76 100644 --- a/src/qei.rs +++ b/src/qei.rs @@ -1,6 +1,7 @@ //! # Quadrature Encoder Interface -use crate::hal::{self, Direction}; +use crate::hal::{self, qei::Direction}; use crate::stm32::RCC; +use core::convert::Infallible; #[cfg(any( feature = "stm32f401", @@ -126,18 +127,19 @@ macro_rules! hal { } } - impl hal::Qei for Qei<$TIM, PINS> { + impl hal::qei::Qei for Qei<$TIM, PINS> { + type Error = Infallible; type Count = $bits; - fn count(&self) -> $bits { - self.tim.cnt.read().bits() as $bits + fn try_count(&self) -> Result { + Ok(self.tim.cnt.read().bits() as $bits) } - fn direction(&self) -> Direction { + fn try_direction(&self) -> Result { if self.tim.cr1.read().dir().bit_is_clear() { - hal::Direction::Upcounting + Ok(Direction::Upcounting) } else { - hal::Direction::Downcounting + Ok(Direction::Downcounting) } } } diff --git a/src/rng.rs b/src/rng.rs index 5a6ec2e9..64868b5a 100644 --- a/src/rng.rs +++ b/src/rng.rs @@ -93,7 +93,7 @@ impl Rng { impl rng::Read for Rng { type Error = rand_core::Error; - fn read(&mut self, buffer: &mut [u8]) -> Result<(), Self::Error> { + fn try_read(&mut self, buffer: &mut [u8]) -> Result<(), Self::Error> { self.try_fill_bytes(buffer) } } diff --git a/src/serial.rs b/src/serial.rs index cf33dc82..6d8b5f44 100644 --- a/src/serial.rs +++ b/src/serial.rs @@ -1544,18 +1544,18 @@ macro_rules! halUsartImpl { impl serial::Read for Serial<$USARTX, PINS> { type Error = Error; - fn read(&mut self) -> nb::Result { + fn try_read(&mut self) -> nb::Result { let mut rx: Rx<$USARTX> = Rx { _usart: PhantomData, }; - rx.read() + rx.try_read() } } impl serial::Read for Rx<$USARTX> { type Error = Error; - fn read(&mut self) -> nb::Result { + fn try_read(&mut self) -> nb::Result { // NOTE(unsafe) atomic read with no side effects let sr = unsafe { (*$USARTX::ptr()).sr.read() }; @@ -1597,18 +1597,18 @@ macro_rules! halUsartImpl { impl serial::Write for Serial<$USARTX, PINS> { type Error = Error; - fn flush(&mut self) -> nb::Result<(), Self::Error> { + fn try_flush(&mut self) -> nb::Result<(), Self::Error> { let mut tx: Tx<$USARTX> = Tx { _usart: PhantomData, }; - tx.flush() + tx.try_flush() } - fn write(&mut self, byte: u8) -> nb::Result<(), Self::Error> { + fn try_write(&mut self, byte: u8) -> nb::Result<(), Self::Error> { let mut tx: Tx<$USARTX> = Tx { _usart: PhantomData, }; - tx.write(byte) + tx.try_write(byte) } } @@ -1624,7 +1624,7 @@ macro_rules! halUsartImpl { impl serial::Write for Tx<$USARTX> { type Error = Error; - fn flush(&mut self) -> nb::Result<(), Self::Error> { + fn try_flush(&mut self) -> nb::Result<(), Self::Error> { // NOTE(unsafe) atomic read with no side effects let sr = unsafe { (*$USARTX::ptr()).sr.read() }; @@ -1635,7 +1635,7 @@ macro_rules! halUsartImpl { } } - fn write(&mut self, byte: u8) -> nb::Result<(), Self::Error> { + fn try_write(&mut self, byte: u8) -> nb::Result<(), Self::Error> { // NOTE(unsafe) atomic read with no side effects let sr = unsafe { (*$USARTX::ptr()).sr.read() }; @@ -1653,10 +1653,10 @@ macro_rules! halUsartImpl { impl blocking::serial::Write for Tx<$USARTX> { type Error = Error; - fn bwrite_all(&mut self, bytes: &[u8]) -> Result<(), Self::Error> { + fn try_bwrite_all(&mut self, bytes: &[u8]) -> Result<(), Self::Error> { for &b in bytes { loop { - match self.write(b) { + match self.try_write(b) { Err(nb::Error::WouldBlock) => continue, Err(nb::Error::Other(err)) => return Err(err), Ok(()) => break, @@ -1666,9 +1666,9 @@ macro_rules! halUsartImpl { Ok(()) } - fn bflush(&mut self) -> Result<(), Self::Error> { + fn try_bflush(&mut self) -> Result<(), Self::Error> { loop { - match self.flush() { + match self.try_flush() { Ok(()) => return Ok(()), Err(nb::Error::WouldBlock) => continue, Err(nb::Error::Other(err)) => return Err(err), @@ -1680,18 +1680,18 @@ macro_rules! halUsartImpl { impl blocking::serial::Write for Serial<$USARTX, PINS> { type Error = Error; - fn bwrite_all(&mut self, bytes: &[u8]) -> Result<(), Self::Error> { + fn try_bwrite_all(&mut self, bytes: &[u8]) -> Result<(), Self::Error> { let mut tx: Tx<$USARTX> = Tx { _usart: PhantomData, }; - tx.bwrite_all(bytes) + tx.try_bwrite_all(bytes) } - fn bflush(&mut self) -> Result<(), Self::Error> { + fn try_bflush(&mut self) -> Result<(), Self::Error> { let mut tx: Tx<$USARTX> = Tx { _usart: PhantomData, }; - tx.bflush() + tx.try_bflush() } } )+ @@ -1864,7 +1864,11 @@ where Tx: serial::Write, { fn write_str(&mut self, s: &str) -> fmt::Result { - let _ = s.as_bytes().iter().map(|c| block!(self.write(*c))).last(); + let _ = s + .as_bytes() + .iter() + .map(|c| block!(self.try_write(*c))) + .last(); Ok(()) } } diff --git a/src/spi.rs b/src/spi.rs index d16aedd4..49c60cfc 100644 --- a/src/spi.rs +++ b/src/spi.rs @@ -1013,7 +1013,7 @@ where { type Error = Error; - fn read(&mut self) -> nb::Result { + fn try_read(&mut self) -> nb::Result { let sr = self.spi.sr.read(); Err(if sr.ovr().bit_is_set() { @@ -1031,7 +1031,7 @@ where }) } - fn send(&mut self, byte: u8) -> nb::Result<(), Error> { + fn try_send(&mut self, byte: u8) -> nb::Result<(), Error> { let sr = self.spi.sr.read(); Err(if sr.ovr().bit_is_set() { diff --git a/src/timer.rs b/src/timer.rs index cc9c6445..b29a5dee 100644 --- a/src/timer.rs +++ b/src/timer.rs @@ -1,10 +1,11 @@ //! Timers use cast::{u16, u32}; + use cortex_m::peripheral::syst::SystClkSource; use cortex_m::peripheral::SYST; use embedded_hal::timer::{Cancel, CountDown, Periodic}; -use void::Void; +use nb; use crate::stm32::RCC; #[cfg(any( @@ -111,7 +112,7 @@ impl Timer { { syst.set_clock_source(SystClkSource::Core); let mut timer = Timer { tim: syst, clocks }; - timer.start(timeout); + let _ = timer.try_start(timeout); timer } @@ -131,9 +132,10 @@ impl Timer { } impl CountDown for Timer { + type Error = Error; type Time = Hertz; - fn start(&mut self, timeout: T) + fn try_start(&mut self, timeout: T) -> Result<(), Self::Error> where T: Into, { @@ -144,9 +146,11 @@ impl CountDown for Timer { self.tim.set_reload(rvr); self.tim.clear_current(); self.tim.enable_counter(); + + Ok(()) } - fn wait(&mut self) -> nb::Result<(), Void> { + fn try_wait(&mut self) -> nb::Result<(), Self::Error> { if self.tim.has_wrapped() { Ok(()) } else { @@ -156,9 +160,7 @@ impl CountDown for Timer { } impl Cancel for Timer { - type Error = Error; - - fn cancel(&mut self) -> Result<(), Self::Error> { + fn try_cancel(&mut self) -> Result<(), Self::Error> { if !self.tim.is_counter_enabled() { return Err(Self::Error::Disabled); } @@ -189,7 +191,7 @@ macro_rules! hal { clocks, tim, }; - timer.start(timeout); + let _ = timer.try_start(timeout); timer } @@ -239,9 +241,10 @@ macro_rules! hal { } impl CountDown for Timer<$TIM> { + type Error = Error; type Time = Hertz; - fn start(&mut self, timeout: T) + fn try_start(&mut self, timeout: T) -> Result<(), Self::Error> where T: Into, { @@ -262,13 +265,16 @@ macro_rules! hal { // start counter self.tim.cr1.modify(|_, w| w.cen().set_bit()); + + Ok(()) } - fn wait(&mut self) -> nb::Result<(), Void> { + fn try_wait(&mut self) -> nb::Result<(), Self::Error> { if self.tim.sr.read().uif().bit_is_clear() { Err(nb::Error::WouldBlock) } else { self.tim.sr.modify(|_, w| w.uif().clear_bit()); + Ok(()) } } @@ -276,9 +282,7 @@ macro_rules! hal { impl Cancel for Timer<$TIM> { - type Error = Error; - - fn cancel(&mut self) -> Result<(), Self::Error> { + fn try_cancel(&mut self) -> Result<(), Self::Error> { let is_counter_enabled = self.tim.cr1.read().cen().is_enabled(); if !is_counter_enabled { return Err(Self::Error::Disabled); diff --git a/src/watchdog.rs b/src/watchdog.rs index 440afb57..31f87a2b 100644 --- a/src/watchdog.rs +++ b/src/watchdog.rs @@ -5,6 +5,7 @@ use crate::{ stm32::{DBGMCU, IWDG}, time::MilliSeconds, }; +use core::convert::Infallible; /// Wraps the Independent Watchdog (IWDG) peripheral pub struct IndependentWatchdog { @@ -88,17 +89,24 @@ impl IndependentWatchdog { } impl WatchdogEnable for IndependentWatchdog { + type Error = Infallible; type Time = MilliSeconds; - fn start>(&mut self, period: T) { + fn try_start>(&mut self, period: T) -> Result<(), Self::Error> { self.setup(period.into().0); self.iwdg.kr.write(|w| unsafe { w.key().bits(KR_START) }); + + Ok(()) } } impl Watchdog for IndependentWatchdog { - fn feed(&mut self) { + type Error = Infallible; + + fn try_feed(&mut self) -> Result<(), Self::Error> { self.iwdg.kr.write(|w| unsafe { w.key().bits(KR_RELOAD) }); + + Ok(()) } }