From 9d7c037ce2869d07a1a4641cda95e5e40f13e9d0 Mon Sep 17 00:00:00 2001 From: Takeshi Yoneda Date: Mon, 8 Jan 2024 08:47:28 -0800 Subject: [PATCH] wazevo(amd64): adds stubs for all necessary methods Signed-off-by: Takeshi Yoneda --- .../engine/wazevo/backend/isa/amd64/instr.go | 90 ++++++++++++++++++- .../wazevo/backend/isa/amd64/machine.go | 29 ++++-- .../backend/isa/amd64/machine_regalloc.go | 48 ++++++++++ 3 files changed, 158 insertions(+), 9 deletions(-) create mode 100644 internal/engine/wazevo/backend/isa/amd64/machine_regalloc.go diff --git a/internal/engine/wazevo/backend/isa/amd64/instr.go b/internal/engine/wazevo/backend/isa/amd64/instr.go index 8cf1369b27..e280147da9 100644 --- a/internal/engine/wazevo/backend/isa/amd64/instr.go +++ b/internal/engine/wazevo/backend/isa/amd64/instr.go @@ -1,12 +1,87 @@ package amd64 +import ( + "github.com/tetratelabs/wazero/internal/engine/wazevo/backend/regalloc" +) + type instruction struct { - prev, next *instruction + kind instructionKind + prev, next *instruction + addedBeforeRegAlloc bool +} + +// Next implements regalloc.Instr. +func (i *instruction) Next() regalloc.Instr { + return i.next +} + +// Prev implements regalloc.Instr. +func (i *instruction) Prev() regalloc.Instr { + return i.prev +} + +// String implements regalloc.Instr. +func (i *instruction) String() string { + // TODO implement me + panic("implement me") +} + +// Defs implements regalloc.Instr. +func (i *instruction) Defs(i2 *[]regalloc.VReg) []regalloc.VReg { + // TODO implement me + panic("implement me") +} + +// Uses implements regalloc.Instr. +func (i *instruction) Uses(i2 *[]regalloc.VReg) []regalloc.VReg { + // TODO implement me + panic("implement me") +} + +// AssignUse implements regalloc.Instr. +func (i *instruction) AssignUse(index int, v regalloc.VReg) { + // TODO implement me + panic("implement me") +} + +// AssignDef implements regalloc.Instr. +func (i *instruction) AssignDef(reg regalloc.VReg) { + // TODO implement me + panic("implement me") +} + +// IsCopy implements regalloc.Instr. +func (i *instruction) IsCopy() bool { + // TODO implement me + panic("implement me") +} + +// IsCall implements regalloc.Instr. +func (i *instruction) IsCall() bool { + // TODO implement me + panic("implement me") +} + +// IsIndirectCall implements regalloc.Instr. +func (i *instruction) IsIndirectCall() bool { + // TODO implement me + panic("implement me") +} + +// IsReturn implements regalloc.Instr. +func (i *instruction) IsReturn() bool { + // TODO implement me + panic("implement me") +} + +// AddedBeforeRegAlloc implements regalloc.Instr. +func (i *instruction) AddedBeforeRegAlloc() bool { + // TODO implement me + panic("implement me") } func resetInstruction(i *instruction) { - i.prev = nil - i.next = nil + *i = instruction{} } func setNext(i *instruction, next *instruction) { @@ -17,5 +92,12 @@ func setPrev(i *instruction, prev *instruction) { i.prev = prev } -func asNop(*instruction) { +func asNop(i *instruction) { + i.kind = nop0 } + +type instructionKind int + +const ( + nop0 instructionKind = iota + 1 +) diff --git a/internal/engine/wazevo/backend/isa/amd64/machine.go b/internal/engine/wazevo/backend/isa/amd64/machine.go index 9815700e6d..3eb0fec630 100644 --- a/internal/engine/wazevo/backend/isa/amd64/machine.go +++ b/internal/engine/wazevo/backend/isa/amd64/machine.go @@ -29,14 +29,23 @@ type machine struct { ectx *backend.ExecutableContextT[instruction] stackBoundsCheckDisabled bool - regAlloc regalloc.Allocator - currentABI *backend.FunctionABI + regAlloc regalloc.Allocator + regAllocFn *backend.RegAllocFunction[*instruction, *machine] + regAllocStarted bool + + spillSlotSize int64 + currentABI *backend.FunctionABI + clobberedRegs []regalloc.VReg } // Reset implements backend.Machine. func (m *machine) Reset() { m.stackBoundsCheckDisabled = false m.ectx.Reset() + + m.regAllocFn.Reset() + m.regAlloc.Reset() + m.regAllocStarted = false } // ExecutableContext implements backend.Machine. @@ -53,6 +62,19 @@ func (m *machine) SetCurrentABI(abi *backend.FunctionABI) { m.currentABI = abi } +// RegAlloc implements backend.Machine. +func (m *machine) RegAlloc() { + rf := m.regAllocFn + for _, pos := range m.ectx.OrderedBlockLabels { + rf.AddBlock(pos.SB, pos.L, pos.Begin, pos.End) + } + + m.regAllocStarted = true + m.regAlloc.DoAllocation(rf) + // Now that we know the final spill slot size, we must align spillSlotSize to 16 bytes. + m.spillSlotSize = (m.spillSlotSize + 15) &^ 15 +} + // LowerSingleBranch implements backend.Machine. func (m *machine) LowerSingleBranch(b *ssa.Instruction) { // TODO implement me @@ -142,6 +164,3 @@ func (m *machine) CompileEntryPreamble(signature *ssa.Signature) []byte { // TODO implement me panic("implement me") } - -// RegAlloc implements backend.Machine. -func (m *machine) RegAlloc() { panic("implement me") } diff --git a/internal/engine/wazevo/backend/isa/amd64/machine_regalloc.go b/internal/engine/wazevo/backend/isa/amd64/machine_regalloc.go new file mode 100644 index 0000000000..ac6e60006c --- /dev/null +++ b/internal/engine/wazevo/backend/isa/amd64/machine_regalloc.go @@ -0,0 +1,48 @@ +package amd64 + +import ( + "github.com/tetratelabs/wazero/internal/engine/wazevo/backend" + "github.com/tetratelabs/wazero/internal/engine/wazevo/backend/regalloc" + "github.com/tetratelabs/wazero/internal/engine/wazevo/ssa" +) + +// InsertMoveBefore implements backend.RegAllocFunctionMachine. +func (m *machine) InsertMoveBefore(dst, src regalloc.VReg, instr *instruction) { + // TODO implement me + panic("implement me") +} + +// InsertStoreRegisterAt implements backend.RegAllocFunctionMachine. +func (m *machine) InsertStoreRegisterAt(v regalloc.VReg, instr *instruction, after bool) *instruction { + // TODO implement me + panic("implement me") +} + +// InsertReloadRegisterAt implements backend.RegAllocFunctionMachine. +func (m *machine) InsertReloadRegisterAt(v regalloc.VReg, instr *instruction, after bool) *instruction { + // TODO implement me + panic("implement me") +} + +// ClobberedRegisters implements backend.RegAllocFunctionMachine. +func (m *machine) ClobberedRegisters(regs []regalloc.VReg) { + m.clobberedRegs = append(m.clobberedRegs[:0], regs...) +} + +// Swap implements backend.RegAllocFunctionMachine. +func (m *machine) Swap(cur *instruction, x1, x2, tmp regalloc.VReg) { + // TODO implement me + panic("implement me") +} + +// LastInstrForInsertion implements backend.RegAllocFunctionMachine. +func (m *machine) LastInstrForInsertion(begin, end *instruction) *instruction { + // TODO implement me + panic("implement me") +} + +// SSABlockLabel implements backend.RegAllocFunctionMachine. +func (m *machine) SSABlockLabel(id ssa.BasicBlockID) backend.Label { + // TODO implement me + panic("implement me") +}