DspComplex[T].zero not initialized

[joshsanz]

I'm trying to create a reg vector which will be initialized to zeros, but running into uninitialized errors. Based on the cookbook I wrote the code below:

val zeroComplex = DspComplex(Real[T].zero, Real[T].zero)
  val dataVec = RegInit(VecInit(Seq.fill(windowSize)(Wire(zeroComplex))))

When run, I get many errors which look like

[info]   firrtl.passes.PassExceptions: firrtl.passes.CheckInitialization$RefNotInitializedException:  @[PacketDetect.scala 139:32] : [module PacketDetect]  Reference _T_66 is not fully initialized.
[info]    : _T_44.imag <= VOID
[info]    @[PacketDetect.scala 139:32] : _T_66[12].imag <= _T_44.imag @[PacketDetect.scala 139:32]
[info] firrtl.passes.CheckInitialization$RefNotInitializedException:  @[PacketDetect.scala 139:32] : [module PacketDetect]  Reference _T_66 is not fully initialized.
[info]    : _T_8.real <= VOID
[info]    @[PacketDetect.scala 139:32] : _T_66[0].real <= _T_8.real @[PacketDetect.scala 139:32]

Creating zeroComplex by instantiating a wire then tying the real and imag components to Real[T].zero separately seemed to work, but looking at the code I don't understand why this doesn't.

[shunshou]

I think it's because the version of Chisel you're using doesn't accept Literals in Bundles. The shorthand for doing what you did is to use

val zeroComplex = DspComplex.wire(Real[T].zero, Real[T].zero)

You can assign elements in bundles to literals, but they can't be literals themselves.

This is, of course, not a long-term good solution, but things will get better when literals in bundles are a thing (and they might already be in recent Chisel versions? -- I haven't been following as closely... EDIT: see chipsalliance/chisel#820).