From ef1871e918e470c5b6d77b4c956a96c6c1293ca5 Mon Sep 17 00:00:00 2001 From: Anna Antonenko Date: Thu, 18 Apr 2024 19:46:30 +0300 Subject: [PATCH] MVP --- .gitignore | 9 + .gitmodules | 3 + CMakeLists.txt | 9 + README.md | 62 ++ bracket.scad | 57 ++ flash.sh | 6 + main/CMakeLists.txt | 3 + main/auth.c | 273 ++++++ main/hass.c | 36 + main/include/auth.h | 23 + main/include/common.h | 8 + main/include/config.h | 17 + main/include/hass.h | 5 + main/include/pn532.h | 170 ++++ main/main.c | 152 ++++ main/pn532.c | 1529 +++++++++++++++++++++++++++++++ partitions.csv | 5 + sdkconfig | 1990 +++++++++++++++++++++++++++++++++++++++++ 18 files changed, 4357 insertions(+) create mode 100644 .gitignore create mode 100644 .gitmodules create mode 100644 CMakeLists.txt create mode 100644 README.md create mode 100644 bracket.scad create mode 100755 flash.sh create mode 100644 main/CMakeLists.txt create mode 100644 main/auth.c create mode 100644 main/hass.c create mode 100644 main/include/auth.h create mode 100644 main/include/common.h create mode 100644 main/include/config.h create mode 100644 main/include/hass.h create mode 100644 main/include/pn532.h create mode 100644 main/main.c create mode 100644 main/pn532.c create mode 100644 partitions.csv create mode 100644 sdkconfig diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..cf2fd04 --- /dev/null +++ b/.gitignore @@ -0,0 +1,9 @@ +main/include/secrets.h +/build +/.vscode +/sdkconfig.old +/managed_components +/bracket.stl +/bracket.gcode +/flash_key.bin +/signing_key.pem diff --git a/.gitmodules b/.gitmodules new file mode 100644 index 0000000..b02accf --- /dev/null +++ b/.gitmodules @@ -0,0 +1,3 @@ +[submodule "esp-idf-lib"] + path = esp-idf-lib + url = https://github.com/UncleRus/esp-idf-lib.git diff --git a/CMakeLists.txt b/CMakeLists.txt new file mode 100644 index 0000000..953d860 --- /dev/null +++ b/CMakeLists.txt @@ -0,0 +1,9 @@ +# The following lines of boilerplate have to be in your project's +# CMakeLists in this exact order for cmake to work correctly +cmake_minimum_required(VERSION 3.16) + +include($ENV{IDF_PATH}/tools/cmake/project.cmake) +set(EXTRA_COMPONENT_DIRS esp-idf-lib/components) +project(undef_rfid) +idf_build_set_property(COMPILE_OPTIONS "-Wno-error=format" + "-fsanitize=undefined" "-fno-sanitize=shift-base" APPEND) diff --git a/README.md b/README.md new file mode 100644 index 0000000..7ddbc50 --- /dev/null +++ b/README.md @@ -0,0 +1,62 @@ +# undef_rfid +RFID-считыватель [undef.space](https://undef.club) + +# Что делает? +Впускает админов в спейс по картам MIFARE. Аутентификация происходит по номеру +карты Тройка или по UID любой другой карты. + +# Документация +Устройство состоит из: + - отладочной платы на базе ESP32-C3 + - NFC-считывателя на базе PN532 + - платы реле + - держателя + +## Использование +Поднесите карту к считывателю. Если авторизация прошла успешно, светодиод +загорится зелёным, устройство откроет дверь и зафиксирует факт входа в админской +беседе. Если нет - светодиод загорится красным. + +## Администрирование +Чтобы использовать встроенный REPL, подключите устройство по USB и откройте +монитор порта (например, при помощи `idf.py monitor`). Если любая из команд +`add`, `remove` или `list` используется впервые за последние пять минут, нужно +будет ввести пароль. Используйте `help`, чтобы узнать список команд с +аргументами. + +Формат `credential`: + - `T<10 цифр>` - карта Тройка + - `U<8 hex-цифр>` - любая карта с 4-байтовым UID + - `U<14 hex-цифр>` - любая карта с 7-байтовым UID + +## Сборка + +### Держатель +TODO: + +### Электроника +TODO: + +### Прошивка +Написана на C с использованием ESP-IDF. Чтобы собрать прошивку: + - установите ESP-IDF + - склонируйте репозиторий + - скачайте зависимости: `git submodule update --recursive` + - создайте файл `main/include/secrets.h` со следующим содержанием: + ```c + #pragma once + #define WIFI_SSID "название сети" + #define WIFI_PASS "пароль сети" + #define HASS_KEY "ключ API HomeAssistant" + #define REPL_PASS "пароль от REPL" + ``` + - получите ключи шифрования: + - если собираете новое устройство, сгенерируйте ключи: + `espsecure.py generate_flash_encryption_key flash_key.bin`, + `espsecure.py generate_signing_key --version 1 signing_key.pem` + - если работаете с уже собранным устройством, получите их от админов и + поместите в корень проекта (файлы `flash_key.bin` и `signing_key.pem`) + - соберите проект: `idf.py build` + - загрузите прошивку: + - в самый первый раз: `idf.py flash monitor` + - в последующие разы, в т.ч. для уже собранного устройства: `./flash.sh` diff --git a/bracket.scad b/bracket.scad new file mode 100644 index 0000000..5a189f5 --- /dev/null +++ b/bracket.scad @@ -0,0 +1,57 @@ +$fn = 100; + +pn532_w = 43; +pn532_h = 40.5; + +pn532_screws_w = 28; +pn532_screws_h = 26; +pn532_screws_offs_x = 7.5; +pn532_screws_offs_y = 7.3; + +pn532_pins_offs_x = 13.2; +pn532_pins_offs_y = 5.25; +pn532_pins_w = 21.5; +pn532_pins_h = 2.5; +pn532_pins_t = 1.5; + +panel_t = 3; +side_panel_h = 15; +stiffener = 7; +thread_indent_t = 3.2; + +// top panel +translate(v = [panel_t, 0, 0]) +difference() { + cube(size = [pn532_w, pn532_h + (2 * panel_t), panel_t]); + + translate(v = [0, panel_t, 0]) { + // pin cavity + translate(v = [pn532_pins_offs_x, pn532_pins_offs_y, 0]) + cube(size = [pn532_pins_w, pn532_pins_h, pn532_pins_t]); + + // thread indents + for(i = [0, 1]) + translate(v = [pn532_screws_offs_x + (i * pn532_screws_w), pn532_screws_offs_y + (i * pn532_screws_h), 0]) + cylinder(h = panel_t * 2, r = thread_indent_t / 2, center=true); + } +} + +// side panel +side_panel_w = pn532_h + (2 * panel_t); +translate(v = [0, 0, -side_panel_h]) +difference() { + cube(size = [panel_t, side_panel_w, side_panel_h + panel_t]); + + // thread indents + for(i = [side_panel_w / 4, side_panel_w * 3 / 4]) + translate(v = [0, i, side_panel_h / 2]) + rotate(a = [0, -90, 0]) + cylinder(h = panel_t * 2, r = thread_indent_t / 2, center=true); +} + +// stiffeners +for(y = [0, pn532_h + panel_t]) +translate(v = [panel_t, y, 0]) +rotate(a = [-90, 0, 0]) +linear_extrude(height = panel_t) + polygon(points=[[0, 0], [stiffener, 0], [0, stiffener]]); diff --git a/flash.sh b/flash.sh new file mode 100755 index 0000000..78c0cd5 --- /dev/null +++ b/flash.sh @@ -0,0 +1,6 @@ +#!/usr/bin/env sh + +idf.py build +espsecure.py encrypt_flash_data --aes_xts --keyfile flash_key.bin --address 0x10000 --output build/encrypted_app.bin build/undef_rfid.bin +esptool.py write_flash --force 0x10000 build/encrypted_app.bin +idf.py monitor diff --git a/main/CMakeLists.txt b/main/CMakeLists.txt new file mode 100644 index 0000000..40a799b --- /dev/null +++ b/main/CMakeLists.txt @@ -0,0 +1,3 @@ +idf_component_register( + SRCS "hass.c" "pn532.c" "main.c" "auth.c" "hass.c" + INCLUDE_DIRS "include/") diff --git a/main/auth.c b/main/auth.c new file mode 100644 index 0000000..2c09932 --- /dev/null +++ b/main/auth.c @@ -0,0 +1,273 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "config.h" +#include "secrets.h" +#include "common.h" +#include "auth.h" +#include "hass.h" + +#define TAG "auth" + +QueueHandle_t scan_queue; +static nvs_handle_t auth_nvs_handle; +static int64_t auth_last_repl_logon = -REPL_LOGON_TIMEOUT; + +static esp_err_t _auth_repl_logon() { + if(esp_timer_get_time() - auth_last_repl_logon < REPL_LOGON_TIMEOUT) + return ESP_OK; + + // request password + char passwd[64]; + printf("enter password: "); + fgets(passwd, 64, stdin); + puts(""); + passwd[strlen(passwd) - 1] = 0; // remove trailing newline + + // check password + if(strcmp(passwd, REPL_PASS) == 0) { + auth_last_repl_logon = esp_timer_get_time(); + return ESP_OK; + } else { + // TODO: send notification to admin group + return ESP_ERR_NOT_ALLOWED; + } +} + +static esp_err_t _auth_fetch_info(char* credential, auth_info_t* info) { + // check blob size + size_t size = 0; + EARLY_ERR_RETURN(nvs_get_blob(auth_nvs_handle, credential, NULL, &size)); + if(size != sizeof(auth_info_t)) { + ESP_LOGW(TAG, "credential %s: auth info size != sizeof(auth_info_t)", credential); + return ESP_ERR_INVALID_SIZE; + } + + // get data + EARLY_ERR_RETURN(nvs_get_blob(auth_nvs_handle, credential, info, &size)); + return ESP_OK; +} + +static const char* gendered_verb_table[] = { "вошёл", "вошло", "вошла", "вошли" }; +static const char* gender_table[] = { "m", "n", "f", "nb" }; + +static struct { + struct arg_str* credential; + struct arg_str* tg_username; + struct arg_str* gender; + struct arg_end* end; +} add_args; +static esp_err_t _auth_repl_add(int argc, char** argv) { + EARLY_ERR_RETURN(_auth_repl_logon()); + + // parse args + int arg_errors = arg_parse(argc, argv, (void**)&add_args); + if(arg_errors != 0) { + arg_print_errors(stderr, add_args.end, argv[0]); + return ESP_ERR_INVALID_ARG; + } + + // validate credential + if(!((add_args.credential->sval[0][0] == 'T') || (add_args.credential->sval[0][0] == 'U'))) { + ESP_LOGE(TAG, "invalid credential type"); + return ESP_ERR_INVALID_ARG; + } + if(!((strlen(add_args.credential->sval[0]) == 11) || + (strlen(add_args.credential->sval[0]) == 9) || + (strlen(add_args.credential->sval[0]) == 15))) { + ESP_LOGE(TAG, "invalid credential length"); + return ESP_ERR_INVALID_ARG; + } + + // validate tg username + if(strlen(add_args.tg_username->sval[0]) > 30) { + ESP_LOGE(TAG, "username too long"); + return ESP_ERR_INVALID_ARG; + } + + // parse gender + gender_t gender = -1; + if(strcmp(add_args.gender->sval[0], "m") == 0) gender = gender_m; + if(strcmp(add_args.gender->sval[0], "n") == 0) gender = gender_n; + if(strcmp(add_args.gender->sval[0], "f") == 0) gender = gender_f; + if(strcmp(add_args.gender->sval[0], "nb") == 0) gender = gender_nb; + if(gender == -1) { + ESP_LOGE(TAG, "invalid gender"); + return ESP_ERR_INVALID_ARG; + } + + // construct auth info + auth_info_t info = { + .gender = gender, + }; + strcpy(info.tg_username, add_args.tg_username->sval[0]); + + // write entry + EARLY_ERR_RETURN(nvs_set_blob(auth_nvs_handle, add_args.credential->sval[0], &info, sizeof(auth_info_t))); + EARLY_ERR_RETURN(nvs_commit(auth_nvs_handle)); + return ESP_OK; +} + +static struct { + struct arg_str* credential; + struct arg_end* end; +} remove_args; +static esp_err_t _auth_repl_remove(int argc, char** argv) { + EARLY_ERR_RETURN(_auth_repl_logon()); + + // parse args + int arg_errors = arg_parse(argc, argv, (void**)&remove_args); + if(arg_errors != 0) { + arg_print_errors(stderr, remove_args.end, argv[0]); + return ESP_ERR_INVALID_ARG; + } + + // remove entry + EARLY_ERR_RETURN(nvs_erase_key(auth_nvs_handle, remove_args.credential->sval[0])); + EARLY_ERR_RETURN(nvs_commit(auth_nvs_handle)); + return ESP_OK; +} + +static esp_err_t _auth_repl_list(int argc, char** argv) { + EARLY_ERR_RETURN(_auth_repl_logon()); + + // print table header + ESP_LOGI(TAG, "+-----------------+--------------------------------+--------+"); + ESP_LOGI(TAG, "| %-15s | %-30s | %-6s |", "credential", "tg_username", "gender"); + ESP_LOGI(TAG, "+-----------------+--------------------------------+--------+"); + + // iterate over entries + nvs_iterator_t iter; + nvs_entry_info_t entry; + esp_err_t err; + int entries = 0; + err = nvs_entry_find_in_handle(auth_nvs_handle, NVS_TYPE_BLOB, &iter); + while(err != ESP_ERR_NVS_NOT_FOUND) { + nvs_entry_info(iter, &entry); + // we're iterating over all blob entries in all namespaces + if(strcmp(entry.namespace_name, "auth") != 0) + goto next; + + // fetch value + auth_info_t info; + EARLY_ERR_RETURN(_auth_fetch_info(entry.key, &info)); + + // print row + ESP_LOGI(TAG, "| %-15s | %-30s | %-6s |", entry.key, info.tg_username, gender_table[info.gender]); + entries++; + + next: + err = nvs_entry_next(&iter); + } + + // finish iterating + nvs_release_iterator(iter); + if(err != ESP_OK && err != ESP_ERR_NVS_NOT_FOUND) + EARLY_ERR_RETURN(err); + + // print table footer + ESP_LOGI(TAG, "+-----------------+--------------------------------+--------+"); + ESP_LOGI(TAG, "<%d entries>", entries); + return ESP_OK; +} + +void auth_init(void) { + // initialize credential queue + scan_queue = xQueueCreate(SCAN_Q_SIZE, SCAN_CRED_SIZE); + + // initialize GPIO + gpio_config_t relay_conf = { + .mode = GPIO_MODE_OUTPUT, + .pin_bit_mask = 1 << DOOR_RELAY, + }; + gpio_config(&relay_conf); + + // initialize NVS + ESP_ERROR_CHECK(nvs_open("auth", NVS_READWRITE, &auth_nvs_handle)); + + // initialize REPL + esp_console_repl_t* repl = NULL; + esp_console_repl_config_t repl_config = ESP_CONSOLE_REPL_CONFIG_DEFAULT(); + esp_console_dev_uart_config_t uart_config = ESP_CONSOLE_DEV_UART_CONFIG_DEFAULT(); + repl_config.prompt = ">"; + + // register commands + const esp_console_cmd_t add_cmd = { + .command = "add", + .help = "Add person to authentication/authorization database", + .hint = NULL, + .func = &_auth_repl_add, + .argtable = &add_args, + }; + add_args.credential = arg_str1(NULL, NULL, "", "authentication credential"); + add_args.tg_username = arg_str1(NULL, NULL, "", "Telegram username"); + add_args.gender = arg_str1(NULL, NULL, "", "gender used for entry notification messages"); + add_args.end = arg_end(1); + ESP_ERROR_CHECK(esp_console_cmd_register(&add_cmd)); + + const esp_console_cmd_t remove_cmd = { + .command = "remove", + .help = "Remove person from authentication/authorization database", + .hint = NULL, + .func = &_auth_repl_remove, + .argtable = &remove_args, + }; + remove_args.credential = arg_str1(NULL, NULL, "", "authentication credential"); + remove_args.end = arg_end(1); + ESP_ERROR_CHECK(esp_console_cmd_register(&remove_cmd)); + + const esp_console_cmd_t list_cmd = { + .command = "list", + .help = "List credentials in authentication/authorization database", + .hint = NULL, + .func = &_auth_repl_list, + }; + ESP_ERROR_CHECK(esp_console_cmd_register(&list_cmd)); + + ESP_ERROR_CHECK(esp_console_register_help_command()); + + // start REPL + ESP_ERROR_CHECK(esp_console_new_repl_uart(&uart_config, &repl_config, &repl)); + ESP_ERROR_CHECK(esp_console_start_repl(repl)); +} + +void auth_task(void* _arg) { + char credential[SCAN_CRED_SIZE]; + while(1) { + // get scanned credential + if(!xQueueReceive(scan_queue, &credential, portMAX_DELAY)) + continue; + + // print credential + ESP_LOGI(TAG, "scanned credential: %s", credential); + + // get data from NVS + auth_info_t info; + esp_err_t err = _auth_fetch_info(credential, &info); + + if(err == ESP_OK) { + ESP_LOGI(TAG, "@%s %s", info.tg_username, gendered_verb_table[info.gender]); + + // open door + gpio_set_level(DOOR_RELAY, 1); + vTaskDelay(OPEN_DOOR_FOR); + gpio_set_level(DOOR_RELAY, 0); + + // send notifications + ESP_ERROR_CHECK(hass_log_entry(info.tg_username)); + // TODO: send notification to admin group + } else if(err == ESP_ERR_NVS_NOT_FOUND) { + // unknown credential + } else { + ESP_ERROR_CHECK(err); + } + } +} diff --git a/main/hass.c b/main/hass.c new file mode 100644 index 0000000..282755e --- /dev/null +++ b/main/hass.c @@ -0,0 +1,36 @@ +#include +#include +#include + +#include "common.h" +#include "hass.h" +#include "secrets.h" +#include "config.h" + +#define TAG "hass" + +static esp_err_t _hass_http_event_handler(esp_http_client_event_t *evt) { + return ESP_OK; +} + +esp_err_t hass_log_entry(char* username) { + // format JSON + char post_data[200]; + sprintf(post_data, "{\"name\": \"Open Ring 1\", \"message\": \"triggered by %s's card\", \"domain\": \"lock\", \"entity_id\": \"button.open_ring_1\"}", username); + + // configure HTTP client + esp_http_client_config_t config = { + .url = "http://" HASS_SERVER "/api/events/logbook_entry", + .method = HTTP_METHOD_POST, + .event_handler = _hass_http_event_handler, + }; + esp_http_client_handle_t client = esp_http_client_init(&config); + esp_http_client_set_header(client, "Content-Type", "application/json"); + esp_http_client_set_header(client, "Authorization", "Bearer " HASS_KEY); + esp_http_client_set_post_field(client, post_data, strlen(post_data)); + + // perform request + EARLY_ERR_RETURN(esp_http_client_perform(client)); + ESP_LOGI(TAG, "HTTP status: %d", esp_http_client_get_status_code(client)); + return ESP_OK; +} diff --git a/main/include/auth.h b/main/include/auth.h new file mode 100644 index 0000000..7487712 --- /dev/null +++ b/main/include/auth.h @@ -0,0 +1,23 @@ +#pragma once + +#include +#include + +typedef enum __attribute__((__packed__)) { + gender_m, + gender_n, + gender_f, + gender_nb, +} gender_t; + +typedef struct __attribute__((__packed__)) { + char tg_username[31]; + gender_t gender; +} auth_info_t; + +#define SCAN_CRED_SIZE 16 +#define SCAN_Q_SIZE 4 +extern QueueHandle_t scan_queue; + +void auth_init(void); +void auth_task(void* _arg); diff --git a/main/include/common.h b/main/include/common.h new file mode 100644 index 0000000..7e755ee --- /dev/null +++ b/main/include/common.h @@ -0,0 +1,8 @@ +#pragma once + +#define EARLY_ERR_RETURN(x) do { \ + esp_err_t err_rc_ = (x); \ + if (unlikely(err_rc_ != ESP_OK)) { \ + return err_rc_; \ + } \ + } while(0) diff --git a/main/include/config.h b/main/include/config.h new file mode 100644 index 0000000..a92d6e7 --- /dev/null +++ b/main/include/config.h @@ -0,0 +1,17 @@ +#pragma once + +#include + +#define NTP_SERVER "pool.ntp.org" +#define TZ "GMT-3" +#define HASS_SERVER "undef:8123" + +#define PN532_SCK 4 +#define PN532_MISO 5 +#define PN532_MOSI 6 +#define PN532_SS 7 +#define DOOR_RELAY 10 + +#define SCAN_TIMEOUT (5 * 1000 * 1000) // uS +#define REPL_LOGON_TIMEOUT (5 * 60 * 1000 * 1000) // uS +#define OPEN_DOOR_FOR (5000 / portTICK_PERIOD_MS) diff --git a/main/include/hass.h b/main/include/hass.h new file mode 100644 index 0000000..d530b1f --- /dev/null +++ b/main/include/hass.h @@ -0,0 +1,5 @@ +#pragma once + +#include + +esp_err_t hass_log_entry(char* username); diff --git a/main/include/pn532.h b/main/include/pn532.h new file mode 100644 index 0000000..e0e1b9e --- /dev/null +++ b/main/include/pn532.h @@ -0,0 +1,170 @@ +#ifndef __PN532_H__ +#define __PN532_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#define PN532_PREAMBLE (0x00) +#define PN532_STARTCODE1 (0x00) +#define PN532_STARTCODE2 (0xFF) +#define PN532_POSTAMBLE (0x00) + +#define PN532_HOSTTOPN532 (0xD4) +#define PN532_PN532TOHOST (0xD5) + +// PN532 Commands +#define PN532_COMMAND_DIAGNOSE (0x00) +#define PN532_COMMAND_GETFIRMWAREVERSION (0x02) +#define PN532_COMMAND_GETGENERALSTATUS (0x04) +#define PN532_COMMAND_READREGISTER (0x06) +#define PN532_COMMAND_WRITEREGISTER (0x08) +#define PN532_COMMAND_READGPIO (0x0C) +#define PN532_COMMAND_WRITEGPIO (0x0E) +#define PN532_COMMAND_SETSERIALBAUDRATE (0x10) +#define PN532_COMMAND_SETPARAMETERS (0x12) +#define PN532_COMMAND_SAMCONFIGURATION (0x14) +#define PN532_COMMAND_POWERDOWN (0x16) +#define PN532_COMMAND_RFCONFIGURATION (0x32) +#define PN532_COMMAND_RFREGULATIONTEST (0x58) +#define PN532_COMMAND_INJUMPFORDEP (0x56) +#define PN532_COMMAND_INJUMPFORPSL (0x46) +#define PN532_COMMAND_INLISTPASSIVETARGET (0x4A) +#define PN532_COMMAND_INATR (0x50) +#define PN532_COMMAND_INPSL (0x4E) +#define PN532_COMMAND_INDATAEXCHANGE (0x40) +#define PN532_COMMAND_INCOMMUNICATETHRU (0x42) +#define PN532_COMMAND_INDESELECT (0x44) +#define PN532_COMMAND_INRELEASE (0x52) +#define PN532_COMMAND_INSELECT (0x54) +#define PN532_COMMAND_INAUTOPOLL (0x60) +#define PN532_COMMAND_TGINITASTARGET (0x8C) +#define PN532_COMMAND_TGSETGENERALBYTES (0x92) +#define PN532_COMMAND_TGGETDATA (0x86) +#define PN532_COMMAND_TGSETDATA (0x8E) +#define PN532_COMMAND_TGSETMETADATA (0x94) +#define PN532_COMMAND_TGGETINITIATORCOMMAND (0x88) +#define PN532_COMMAND_TGRESPONSETOINITIATOR (0x90) +#define PN532_COMMAND_TGGETTARGETSTATUS (0x8A) + +#define PN532_RESPONSE_INDATAEXCHANGE (0x41) +#define PN532_RESPONSE_INLISTPASSIVETARGET (0x4B) + +#define PN532_WAKEUP (0x55) + +#define PN532_SPI_STATREAD (0x02) +#define PN532_SPI_DATAWRITE (0x01) +#define PN532_SPI_DATAREAD (0x03) +#define PN532_SPI_READY (0x01) + +#define PN532_I2C_ADDRESS (0x48 >> 1) +#define PN532_I2C_READBIT (0x01) +#define PN532_I2C_BUSY (0x00) +#define PN532_I2C_READY (0x01) +#define PN532_I2C_READYTIMEOUT (20) + +#define PN532_MIFARE_ISO14443A (0x00) + +// Mifare Commands +#define MIFARE_CMD_AUTH_A (0x60) +#define MIFARE_CMD_AUTH_B (0x61) +#define MIFARE_CMD_READ (0x30) +#define MIFARE_CMD_WRITE (0xA0) +#define MIFARE_CMD_TRANSFER (0xB0) +#define MIFARE_CMD_DECREMENT (0xC0) +#define MIFARE_CMD_INCREMENT (0xC1) +#define MIFARE_CMD_STORE (0xC2) +#define MIFARE_ULTRALIGHT_CMD_WRITE (0xA2) + +// Prefixes for NDEF Records (to identify record type) +#define NDEF_URIPREFIX_NONE (0x00) +#define NDEF_URIPREFIX_HTTP_WWWDOT (0x01) +#define NDEF_URIPREFIX_HTTPS_WWWDOT (0x02) +#define NDEF_URIPREFIX_HTTP (0x03) +#define NDEF_URIPREFIX_HTTPS (0x04) +#define NDEF_URIPREFIX_TEL (0x05) +#define NDEF_URIPREFIX_MAILTO (0x06) +#define NDEF_URIPREFIX_FTP_ANONAT (0x07) +#define NDEF_URIPREFIX_FTP_FTPDOT (0x08) +#define NDEF_URIPREFIX_FTPS (0x09) +#define NDEF_URIPREFIX_SFTP (0x0A) +#define NDEF_URIPREFIX_SMB (0x0B) +#define NDEF_URIPREFIX_NFS (0x0C) +#define NDEF_URIPREFIX_FTP (0x0D) +#define NDEF_URIPREFIX_DAV (0x0E) +#define NDEF_URIPREFIX_NEWS (0x0F) +#define NDEF_URIPREFIX_TELNET (0x10) +#define NDEF_URIPREFIX_IMAP (0x11) +#define NDEF_URIPREFIX_RTSP (0x12) +#define NDEF_URIPREFIX_URN (0x13) +#define NDEF_URIPREFIX_POP (0x14) +#define NDEF_URIPREFIX_SIP (0x15) +#define NDEF_URIPREFIX_SIPS (0x16) +#define NDEF_URIPREFIX_TFTP (0x17) +#define NDEF_URIPREFIX_BTSPP (0x18) +#define NDEF_URIPREFIX_BTL2CAP (0x19) +#define NDEF_URIPREFIX_BTGOEP (0x1A) +#define NDEF_URIPREFIX_TCPOBEX (0x1B) +#define NDEF_URIPREFIX_IRDAOBEX (0x1C) +#define NDEF_URIPREFIX_FILE (0x1D) +#define NDEF_URIPREFIX_URN_EPC_ID (0x1E) +#define NDEF_URIPREFIX_URN_EPC_TAG (0x1F) +#define NDEF_URIPREFIX_URN_EPC_PAT (0x20) +#define NDEF_URIPREFIX_URN_EPC_RAW (0x21) +#define NDEF_URIPREFIX_URN_EPC (0x22) +#define NDEF_URIPREFIX_URN_NFC (0x23) + +#define PN532_GPIO_VALIDATIONBIT (0x80) +#define PN532_GPIO_P30 (0) +#define PN532_GPIO_P31 (1) +#define PN532_GPIO_P32 (2) +#define PN532_GPIO_P33 (3) +#define PN532_GPIO_P34 (4) +#define PN532_GPIO_P35 (5) + + +typedef struct { + uint8_t _clk; + uint8_t _miso; + uint8_t _mosi; + uint8_t _ss; + + uint8_t _uid[7]; // ISO14443A uid + uint8_t _uidLen; // uid len + uint8_t _key[6]; // Mifare Classic key + uint8_t _inListedTag; // Tg number of inlisted tag. + +} pn532_t; + +void pn532_spi_init(pn532_t *obj, uint8_t clk, uint8_t miso, uint8_t mosi, uint8_t ss); +void pn532_begin(pn532_t *obj); +uint32_t pn532_getFirmwareVersion(pn532_t *obj); +bool pn532_sendCommandCheckAck(pn532_t *obj, uint8_t *cmd, uint8_t cmdlen, uint16_t timeout); +bool pn532_writeGPIO(pn532_t *obj, uint8_t pinstate); +uint8_t pn532_readGPIO(pn532_t *obj); +bool pn532_SAMConfig(pn532_t *obj); +bool pn532_setPassiveActivationRetries(pn532_t *obj, uint8_t maxRetries); +bool pn532_readPassiveTargetID(pn532_t *obj, uint8_t cardbaudrate, uint8_t *uid, uint8_t *uidLength, uint16_t timeout); +bool pn532_inDataExchange(pn532_t *obj, uint8_t *send, uint8_t sendLength, uint8_t *response, uint8_t *responseLength); +bool pn532_inListPassiveTarget(pn532_t *obj); +bool pn532_mifareclassic_IsFirstBlock(pn532_t *obj, uint32_t uiBlock); +bool pn532_mifareclassic_IsTrailerBlock(pn532_t *obj, uint32_t uiBlock); +uint8_t pn532_mifareclassic_AuthenticateBlock(pn532_t *obj, uint8_t *uid, uint8_t uidLen, uint32_t blockNumber, uint8_t keyNumber, uint8_t *keyData); +uint8_t pn532_mifareclassic_ReadDataBlock(pn532_t *obj, uint8_t blockNumber, uint8_t *data); +uint8_t pn532_mifareclassic_WriteDataBlock(pn532_t *obj, uint8_t blockNumber, uint8_t *data); +uint8_t pn532_mifareclassic_FormatNDEF(pn532_t *obj); +uint8_t pn532_mifareclassic_WriteNDEFURI(pn532_t *obj, uint8_t sectorNumber, uint8_t uriIdentifier, const char *url); +uint8_t pn532_mifareultralight_ReadPage(pn532_t *obj, uint8_t page, uint8_t *buffer); +uint8_t pn532_mifareultralight_WritePage(pn532_t *obj, uint8_t page, uint8_t *data); +uint8_t pn532_ntag2xx_ReadPage(pn532_t *obj, uint8_t page, uint8_t *buffer); +uint8_t pn532_ntag2xx_WritePage(pn532_t *obj, uint8_t page, uint8_t *data); +uint8_t pn532_ntag2xx_WriteNDEFURI(pn532_t *obj, uint8_t uriIdentifier, char *url, uint8_t dataLen); +uint8_t pn532_AsTarget(pn532_t *obj); +uint8_t pn532_getDataTarget(pn532_t *obj, uint8_t *cmd, uint8_t *cmdlen); +uint8_t pn532_setDataTarget(pn532_t *obj, uint8_t *cmd, uint8_t cmdlen); + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/main/main.c b/main/main.c new file mode 100644 index 0000000..387a2b1 --- /dev/null +++ b/main/main.c @@ -0,0 +1,152 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "pn532.h" +#include "auth.h" +#include "secrets.h" +#include "config.h" + +// declarations +void app_main(void); +void nfc_task(void* _arg); + +// pls don't sue us +const uint8_t troika_sector2_key_a[] = { 0x2A, 0xA0, 0x5E, 0xD1, 0x85, 0x6F }; +const uint8_t troika_sector2_key_b[] = { 0xEA, 0xAC, 0x88, 0xE5, 0xDC, 0x99 }; + +static uint8_t last_uid[8]; +static time_t last_uid_time = -SCAN_TIMEOUT; + +#define TAG "main" + +void wifi_event_handler(void* arg, esp_event_base_t event_base, int32_t event_id, void* event_data) { + if(event_base != WIFI_EVENT) + return; + + if(event_id == WIFI_EVENT_STA_START || event_id == WIFI_EVENT_STA_DISCONNECTED) + esp_wifi_connect(); + + if(event_id == WIFI_EVENT_STA_CONNECTED) + ESP_LOGI(TAG, "wifi connected"); + else if(event_id == WIFI_EVENT_STA_DISCONNECTED) + ESP_LOGI(TAG, "wifi disconnected"); +} + +void nfc_task(void* _arg){ + // initialize PN532 + pn532_t nfc; + pn532_spi_init(&nfc, PN532_SCK, PN532_MISO, PN532_MOSI, PN532_SS); + pn532_begin(&nfc); + + // print firmware version + uint32_t version = pn532_getFirmwareVersion(&nfc); + if (!version) { + ESP_LOGI(TAG, "Didn't find PN53x board"); + while (1) { + vTaskDelay(1000 / portTICK_PERIOD_MS); + } + } + ESP_LOGI(TAG, "Found chip PN5%x", (version >> 24) & 0xFF); + ESP_LOGI(TAG, "Firmware ver. %d.%d", (version >> 16) & 0xFF, (version >> 8) & 0xFF); + + // initialize secure access module + pn532_SAMConfig(&nfc); + + // scan cards + uint8_t data_buf[16] = {0}; + uint8_t uid_len; + char credential[SCAN_CRED_SIZE]; + while (1) { + uint8_t success = pn532_readPassiveTargetID(&nfc, PN532_MIFARE_ISO14443A, data_buf, &uid_len, 0); + if(!success) + continue; + + // timeout + if(uid_len == last_uid[0] && memcmp(data_buf, last_uid + 1, uid_len) == 0 // same UID + && esp_timer_get_time() - last_uid_time < SCAN_TIMEOUT) // scanned recently + continue; + last_uid_time = esp_timer_get_time(); + last_uid[0] = uid_len; + memcpy(last_uid + 1, data_buf, uid_len); + + // read block 8 (contains Troika ID) + success = pn532_mifareclassic_AuthenticateBlock(&nfc, data_buf, uid_len, 8, 0, troika_sector2_key_a); + if(!success) { + // not a troika card + if(uid_len == 4) + snprintf(credential, SCAN_CRED_SIZE, "U%02x%02x%02x%02x", + data_buf[0], data_buf[1], + data_buf[2], data_buf[3]); + else // uid_len == 7 + snprintf(credential, SCAN_CRED_SIZE, "U%02x%02x%02x%02x%02x%02x%02x", + data_buf[0], data_buf[1], + data_buf[2], data_buf[3], + data_buf[4], data_buf[5], + data_buf[6]); + xQueueSend(scan_queue, &credential, portMAX_DELAY); + continue; + } + success = pn532_mifareclassic_ReadDataBlock(&nfc, 8, data_buf); + if(!success) + continue; + + snprintf(credential, SCAN_CRED_SIZE, "T%02x%02x%02x%02x%02x", + data_buf[7], data_buf[8], + data_buf[9], data_buf[10], + data_buf[11]); + xQueueSend(scan_queue, &credential, portMAX_DELAY); + } +} + +void app_main(void) { + // initialize NVS + esp_err_t ret = nvs_flash_init(); + if (ret == ESP_ERR_NVS_NO_FREE_PAGES || ret == ESP_ERR_NVS_NEW_VERSION_FOUND) { + ESP_ERROR_CHECK(nvs_flash_erase()); + ret = nvs_flash_init(); + } + ESP_ERROR_CHECK(ret); + + // connect to to Wi-Fi + ESP_ERROR_CHECK(esp_netif_init()); + ESP_ERROR_CHECK(esp_event_loop_create_default()); + esp_netif_create_default_wifi_sta(); + wifi_init_config_t default_cfg = WIFI_INIT_CONFIG_DEFAULT(); + ESP_ERROR_CHECK(esp_wifi_init(&default_cfg)); + esp_event_handler_instance_t event_handler_instance; + ESP_ERROR_CHECK(esp_event_handler_instance_register(WIFI_EVENT, + ESP_EVENT_ANY_ID, &wifi_event_handler, NULL, &event_handler_instance)); + wifi_config_t wifi_config = { + .sta = { + .ssid = WIFI_SSID, + .password = WIFI_PASS, + }, + }; + ESP_ERROR_CHECK(esp_wifi_set_mode(WIFI_MODE_STA)); + ESP_ERROR_CHECK(esp_wifi_set_config(WIFI_IF_STA, &wifi_config)); + ESP_ERROR_CHECK(esp_wifi_start()); + + // set up NTP + setenv("TZ", TZ, 1); + tzset(); + esp_sntp_config_t sntp_config = ESP_NETIF_SNTP_DEFAULT_CONFIG(NTP_SERVER); + esp_netif_sntp_init(&sntp_config); + + // set up auth + auth_init(); + + // start tasks + xTaskCreate(&nfc_task, "nfc", 4096, NULL, 4, NULL); + xTaskCreate(&auth_task, "auth", 4096, NULL, 5, NULL); +} diff --git a/main/pn532.c b/main/pn532.c new file mode 100644 index 0000000..a4673ca --- /dev/null +++ b/main/pn532.c @@ -0,0 +1,1529 @@ +#include +#include +#include +#include + +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" +#include "freertos/queue.h" +#include "sdkconfig.h" + +#include +#include + +#include "driver/gpio.h" +#include "pn532.h" + +//#define PN532_DEBUG_EN +//#define MIFARE_DEBUG_EN + +#ifdef PN532_DEBUG_EN +#define PN532_DEBUG(fmt, ...) printf(fmt, ##__VA_ARGS__) +#else +#define PN532_DEBUG(fmt, ...) +#endif + +#ifdef MIFARE_DEBUG_EN +#define MIFARE_DEBUG(fmt, ...) printf(fmt, ##__VA_ARGS__) +#else +#define MIFARE_DEBUG(fmt, ...) +#endif + +#define PN532_PACKBUFFSIZ 64 + +#ifndef _BV +#define _BV(bit) (1 << (bit)) +#endif + +#define PN532_DELAY(ms) vTaskDelay(ms / portTICK_PERIOD_MS) + +static uint8_t pn532ack[] = {0x00, 0x00, 0xFF, 0x00, 0xFF, 0x00}; +static uint8_t pn532response_firmwarevers[] = {0x00, 0xFF, 0x06, 0xFA, 0xD5, 0x03}; +static uint8_t pn532_packetbuffer[PN532_PACKBUFFSIZ]; + +static void pn532_readdata(pn532_t *obj, uint8_t *buff, uint8_t n); +static void pn532_writecommand(pn532_t *obj, uint8_t *cmd, uint8_t cmdlen); +static bool pn532_readack(pn532_t *obj); +static bool pn532_isready(pn532_t *obj); +static bool pn532_waitready(pn532_t *obj, uint16_t timeout); +static void pn532_spi_write(pn532_t *obj, uint8_t c); +static uint8_t pn532_spi_read(pn532_t *obj); + +void pn532_spi_init(pn532_t *obj, uint8_t clk, uint8_t miso, uint8_t mosi, uint8_t ss) +{ + obj->_clk = clk; + obj->_miso = miso; + obj->_mosi = mosi; + obj->_ss = ss; + + esp_rom_gpio_pad_select_gpio(obj->_clk); + esp_rom_gpio_pad_select_gpio(obj->_miso); + esp_rom_gpio_pad_select_gpio(obj->_mosi); + esp_rom_gpio_pad_select_gpio(obj->_ss); + + gpio_set_direction(obj->_ss, GPIO_MODE_OUTPUT); + gpio_set_level(obj->_ss, 1); + gpio_set_direction(obj->_clk, GPIO_MODE_OUTPUT); + gpio_set_direction(obj->_mosi, GPIO_MODE_OUTPUT); + gpio_set_direction(obj->_miso, GPIO_MODE_INPUT); +} + +/**************************************************************************/ +/*! + @brief Setups the HW +*/ +/**************************************************************************/ +void pn532_begin(pn532_t *obj) +{ + gpio_set_level(obj->_ss, 0); + + PN532_DELAY(1000); + + // not exactly sure why but we have to send a dummy command to get synced up + pn532_packetbuffer[0] = PN532_COMMAND_GETFIRMWAREVERSION; + pn532_sendCommandCheckAck(obj, pn532_packetbuffer, 1, 1000); + + // ignore response! + gpio_set_level(obj->_ss, 1); +} + +/**************************************************************************/ +/*! + @brief Checks the firmware version of the PN5xx chip + + @returns The chip's firmware version and ID +*/ +/**************************************************************************/ +uint32_t pn532_getFirmwareVersion(pn532_t *obj) +{ + uint32_t response; + + pn532_packetbuffer[0] = PN532_COMMAND_GETFIRMWAREVERSION; + + if (!pn532_sendCommandCheckAck(obj, pn532_packetbuffer, 1, 1000)) + { + return 0; + } + + // read data packet + pn532_readdata(obj, pn532_packetbuffer, 12); + + // check some basic stuff + if (0 != strncmp((char *)pn532_packetbuffer, (char *)pn532response_firmwarevers, 6)) + { + PN532_DEBUG("Firmware doesn't match!\n"); + return 0; + } + + int offset = 6; + response = pn532_packetbuffer[offset++]; + response <<= 8; + response |= pn532_packetbuffer[offset++]; + response <<= 8; + response |= pn532_packetbuffer[offset++]; + response <<= 8; + response |= pn532_packetbuffer[offset++]; + + return response; +} + +/**************************************************************************/ +/*! + @brief Sends a command and waits a specified period for the ACK + + @param cmd Pointer to the command buffer + @param cmdlen The size of the command in bytes + @param timeout timeout before giving up + + @returns 1 if everything is OK, 0 if timeout occured before an + ACK was recieved +*/ +/**************************************************************************/ +// default timeout of one second +bool pn532_sendCommandCheckAck(pn532_t *obj, uint8_t *cmd, uint8_t cmdlen, uint16_t timeout) +{ + // write the command + pn532_writecommand(obj, cmd, cmdlen); + + // Wait for chip to say its ready! + if (!pn532_waitready(obj, timeout)) + { + return false; + } + + // read acknowledgement + if (!pn532_readack(obj)) + { + PN532_DEBUG("No ACK frame received!\n"); + return false; + } + + // For SPI only wait for the chip to be ready again. + // This is unnecessary with I2C. + if (!pn532_waitready(obj, timeout)) + { + return false; + } + + return true; // ack'd command +} + +/**************************************************************************/ +/*! + Writes an 8-bit value that sets the state of the PN532's GPIO pins + + @warning This function is provided exclusively for board testing and + is dangerous since it will throw an error if any pin other + than the ones marked "Can be used as GPIO" are modified! All + pins that can not be used as GPIO should ALWAYS be left high + (value = 1) or the system will become unstable and a HW reset + will be required to recover the PN532. + + pinState[0] = P30 Can be used as GPIO + pinState[1] = P31 Can be used as GPIO + pinState[2] = P32 *** RESERVED (Must be 1!) *** + pinState[3] = P33 Can be used as GPIO + pinState[4] = P34 *** RESERVED (Must be 1!) *** + pinState[5] = P35 Can be used as GPIO + + @returns 1 if everything executed properly, 0 for an error +*/ +/**************************************************************************/ +bool pn532_writeGPIO(pn532_t *obj, uint8_t pinstate) +{ + + // Make sure pinstate does not try to toggle P32 or P34 + pinstate |= (1 << PN532_GPIO_P32) | (1 << PN532_GPIO_P34); + + // Fill command buffer + pn532_packetbuffer[0] = PN532_COMMAND_WRITEGPIO; + pn532_packetbuffer[1] = PN532_GPIO_VALIDATIONBIT | pinstate; // P3 Pins + pn532_packetbuffer[2] = 0x00; // P7 GPIO Pins (not used ... taken by SPI) + + PN532_DEBUG("Writing P3 GPIO: %02x\n", pn532_packetbuffer[1]); + + // Send the WRITEGPIO command (0x0E) + if (!pn532_sendCommandCheckAck(obj, pn532_packetbuffer, 3, 1000)) + return 0x0; + + // Read response packet (00 FF PLEN PLENCHECKSUM D5 CMD+1(0x0F) DATACHECKSUM 00) + pn532_readdata(obj, pn532_packetbuffer, 8); + + PN532_DEBUG("Received:"); + for (int i = 0; i < 8; i++) + { + PN532_DEBUG(" %02x", pn532_packetbuffer[i]); + } + PN532_DEBUG("\n"); + + int offset = 5; + return (pn532_packetbuffer[offset] == 0x0F); +} + +/**************************************************************************/ +/*! + Reads the state of the PN532's GPIO pins + + @returns An 8-bit value containing the pin state where: + + pinState[0] = P30 + pinState[1] = P31 + pinState[2] = P32 + pinState[3] = P33 + pinState[4] = P34 + pinState[5] = P35 +*/ +/**************************************************************************/ +uint8_t pn532_readGPIO(pn532_t *obj) +{ + pn532_packetbuffer[0] = PN532_COMMAND_READGPIO; + + // Send the READGPIO command (0x0C) + if (!pn532_sendCommandCheckAck(obj, pn532_packetbuffer, 1, 1000)) + return 0x0; + + // Read response packet (00 FF PLEN PLENCHECKSUM D5 CMD+1(0x0D) P3 P7 IO1 DATACHECKSUM 00) + pn532_readdata(obj, pn532_packetbuffer, 11); + + /* READGPIO response should be in the following format: + + uint8_t Description + ------------- ------------------------------------------ + b0..5 Frame header and preamble (with I2C there is an extra 0x00) + b6 P3 GPIO Pins + b7 P7 GPIO Pins (not used ... taken by SPI) + b8 Interface Mode Pins (not used ... bus select pins) + b9..10 checksum */ + + int p3offset = 6; + + PN532_DEBUG("Received:"); + for (int i = 0; i < 11; i++) + { + PN532_DEBUG(" %02x", pn532_packetbuffer[i]); + } + PN532_DEBUG("\n"); + + PN532_DEBUG("P3 GPIO: %02x\n", pn532_packetbuffer[p3offset]); + PN532_DEBUG("P7 GPIO: %02x\n", pn532_packetbuffer[p3offset + 1]); + PN532_DEBUG("IO GPIO: %02x\n", pn532_packetbuffer[p3offset + 2]); + // Note: You can use the IO GPIO value to detect the serial bus being used + switch (pn532_packetbuffer[p3offset + 2]) + { + case 0x00: // Using UART + PN532_DEBUG("Using UART (IO = 0x00)\n"); + break; + case 0x01: // Using I2C + PN532_DEBUG("Using I2C (IO = 0x01)\n"); + break; + case 0x02: // Using SPI + PN532_DEBUG("Using SPI (IO = 0x02)\n"); + break; + } + + return pn532_packetbuffer[p3offset]; +} + +/**************************************************************************/ +/*! + @brief Configures the SAM (Secure Access Module) +*/ +/**************************************************************************/ +bool pn532_SAMConfig(pn532_t *obj) +{ + pn532_packetbuffer[0] = PN532_COMMAND_SAMCONFIGURATION; + pn532_packetbuffer[1] = 0x01; // normal mode; + pn532_packetbuffer[2] = 0x14; // timeout 50ms * 20 = 1 second + pn532_packetbuffer[3] = 0x01; // use IRQ pin! + + if (!pn532_sendCommandCheckAck(obj, pn532_packetbuffer, 4, 1000)) + return false; + + // read data packet + pn532_readdata(obj, pn532_packetbuffer, 8); + + int offset = 5; + return (pn532_packetbuffer[offset] == 0x15); +} + +/**************************************************************************/ +/*! + Sets the MxRtyPassiveActivation uint8_t of the RFConfiguration register + + @param maxRetries 0xFF to wait forever, 0x00..0xFE to timeout + after mxRetries + + @returns 1 if everything executed properly, 0 for an error +*/ +/**************************************************************************/ +bool pn532_setPassiveActivationRetries(pn532_t *obj, uint8_t maxRetries) +{ + pn532_packetbuffer[0] = PN532_COMMAND_RFCONFIGURATION; + pn532_packetbuffer[1] = 5; // Config item 5 (MaxRetries) + pn532_packetbuffer[2] = 0xFF; // MxRtyATR (default = 0xFF) + pn532_packetbuffer[3] = 0x01; // MxRtyPSL (default = 0x01) + pn532_packetbuffer[4] = maxRetries; + + PN532_DEBUG("Setting MxRtyPassiveActivation to %d\n", maxRetries); + + if (!pn532_sendCommandCheckAck(obj, pn532_packetbuffer, 5, 1000)) + return 0x0; // no ACK + + return 1; +} + +/***** ISO14443A Commands ******/ + +/**************************************************************************/ +/*! + Waits for an ISO14443A target to enter the field + + @param cardBaudRate Baud rate of the card + @param uid Pointer to the array that will be populated + with the card's UID (up to 7 bytes) + @param uidLength Pointer to the variable that will hold the + length of the card's UID. + + @returns 1 if everything executed properly, 0 for an error +*/ +/**************************************************************************/ +bool pn532_readPassiveTargetID(pn532_t *obj, uint8_t cardbaudrate, uint8_t *uid, uint8_t *uidLength, uint16_t timeout) +{ + pn532_packetbuffer[0] = PN532_COMMAND_INLISTPASSIVETARGET; + pn532_packetbuffer[1] = 1; // max 1 cards at once (we can set this to 2 later) + pn532_packetbuffer[2] = cardbaudrate; + + if (!pn532_sendCommandCheckAck(obj, pn532_packetbuffer, 3, timeout)) + { + PN532_DEBUG("No card(s) read\n"); + return 0x0; // no cards read + } + + // read data packet + pn532_readdata(obj, pn532_packetbuffer, 20); + // check some basic stuff + + /* ISO14443A card response should be in the following format: + + uint8_t Description + ------------- ------------------------------------------ + b0..6 Frame header and preamble + b7 Tags Found + b8 Tag Number (only one used in this example) + b9..10 SENS_RES + b11 SEL_RES + b12 NFCID Length + b13..NFCIDLen NFCID */ + + PN532_DEBUG("Found %d tags\n", pn532_packetbuffer[7]); + if (pn532_packetbuffer[7] != 1) + return 0; + + uint16_t sens_res = pn532_packetbuffer[9]; + sens_res <<= 8; + sens_res |= pn532_packetbuffer[10]; + PN532_DEBUG("ATQA: %02x\n", sens_res); + PN532_DEBUG("SAK: %02x\n", pn532_packetbuffer[11]); + + /* Card appears to be Mifare Classic */ + *uidLength = pn532_packetbuffer[12]; + + for (uint8_t i = 0; i < pn532_packetbuffer[12]; i++) + { + uid[i] = pn532_packetbuffer[13 + i]; + } + + PN532_DEBUG("UID:"); + for (int i = 0; i < pn532_packetbuffer[12]; i++) + { + PN532_DEBUG(" %02x", uid[i]); + } + PN532_DEBUG("\n"); + + return 1; +} + +/**************************************************************************/ +/*! + @brief Exchanges an APDU with the currently inlisted peer + + @param send Pointer to data to send + @param sendLength Length of the data to send + @param response Pointer to response data + @param responseLength Pointer to the response data length +*/ +/**************************************************************************/ +bool pn532_inDataExchange(pn532_t *obj, uint8_t *send, uint8_t sendLength, uint8_t *response, uint8_t *responseLength) +{ + if (sendLength > PN532_PACKBUFFSIZ - 2) + { + PN532_DEBUG("APDU length too long for packet buffer\n"); + return false; + } + uint8_t i; + + pn532_packetbuffer[0] = 0x40; // PN532_COMMAND_INDATAEXCHANGE; + pn532_packetbuffer[1] = obj->_inListedTag; + for (i = 0; i < sendLength; ++i) + { + pn532_packetbuffer[i + 2] = send[i]; + } + + if (!pn532_sendCommandCheckAck(obj, pn532_packetbuffer, sendLength + 2, 1000)) + { + PN532_DEBUG("Could not send APDU\n"); + return false; + } + + if (!pn532_waitready(obj, 1000)) + { + PN532_DEBUG("Response never received for APDU...\n"); + return false; + } + + pn532_readdata(obj, pn532_packetbuffer, sizeof(pn532_packetbuffer)); + + if (pn532_packetbuffer[0] == 0 && pn532_packetbuffer[1] == 0 && pn532_packetbuffer[2] == 0xff) + { + uint8_t length = pn532_packetbuffer[3]; + if (pn532_packetbuffer[4] != (uint8_t)(~length + 1)) + { + PN532_DEBUG("Length check invalid %02x%02x\n", length, (~length) + 1); + return false; + } + if (pn532_packetbuffer[5] == PN532_PN532TOHOST && pn532_packetbuffer[6] == PN532_RESPONSE_INDATAEXCHANGE) + { + if ((pn532_packetbuffer[7] & 0x3f) != 0) + { + PN532_DEBUG("Status code indicates an error\n"); + return false; + } + + length -= 3; + + if (length > *responseLength) + { + length = *responseLength; // silent truncation... + } + + for (i = 0; i < length; ++i) + { + response[i] = pn532_packetbuffer[8 + i]; + } + *responseLength = length; + + return true; + } + else + { + PN532_DEBUG("Don't know how to handle this command: %02x\n", pn532_packetbuffer[6]); + return false; + } + } + else + { + PN532_DEBUG("Preamble missing\n"); + return false; + } +} + +/**************************************************************************/ +/*! + @brief 'InLists' a passive target. PN532 acting as reader/initiator, + peer acting as card/responder. +*/ +/**************************************************************************/ +bool pn532_inListPassiveTarget(pn532_t *obj) +{ + pn532_packetbuffer[0] = PN532_COMMAND_INLISTPASSIVETARGET; + pn532_packetbuffer[1] = 1; + pn532_packetbuffer[2] = 0; + + PN532_DEBUG("About to inList passive target\n"); + + if (!pn532_sendCommandCheckAck(obj, pn532_packetbuffer, 3, 1000)) + { + PN532_DEBUG("Could not send inlist message\n"); + return false; + } + + if (!pn532_waitready(obj, 30000)) + { + return false; + } + + pn532_readdata(obj, pn532_packetbuffer, sizeof(pn532_packetbuffer)); + + if (pn532_packetbuffer[0] == 0 && pn532_packetbuffer[1] == 0 && pn532_packetbuffer[2] == 0xff) + { + uint8_t length = pn532_packetbuffer[3]; + if (pn532_packetbuffer[4] != (uint8_t)(~length + 1)) + { + PN532_DEBUG("Length check invalid %02x%02x\n", length, (~length) + 1); + return false; + } + if (pn532_packetbuffer[5] == PN532_PN532TOHOST && pn532_packetbuffer[6] == PN532_RESPONSE_INLISTPASSIVETARGET) + { + if (pn532_packetbuffer[7] != 1) + { + PN532_DEBUG("Unhandled number of targets inlisted\n"); + PN532_DEBUG("Number of tags inlisted: %d\n", pn532_packetbuffer[7]); + return false; + } + + obj->_inListedTag = pn532_packetbuffer[8]; + PN532_DEBUG("Tag number: %d\n", obj->_inListedTag); + + return true; + } + else + { + PN532_DEBUG("Unexpected response to inlist passive host\n"); + return false; + } + } + else + { + PN532_DEBUG("Preamble missing\n"); + return false; + } + + return true; +} + +/***** Mifare Classic Functions ******/ + +/**************************************************************************/ +/*! + Indicates whether the specified block number is the first block + in the sector (block 0 relative to the current sector) +*/ +/**************************************************************************/ +bool pn532_mifareclassic_IsFirstBlock(pn532_t *obj, uint32_t uiBlock) +{ + // Test if we are in the small or big sectors + if (uiBlock < 128) + return ((uiBlock) % 4 == 0); + else + return ((uiBlock) % 16 == 0); +} + +/**************************************************************************/ +/*! + Indicates whether the specified block number is the sector trailer +*/ +/**************************************************************************/ +bool pn532_mifareclassic_IsTrailerBlock(pn532_t *obj, uint32_t uiBlock) +{ + // Test if we are in the small or big sectors + if (uiBlock < 128) + return ((uiBlock + 1) % 4 == 0); + else + return ((uiBlock + 1) % 16 == 0); +} + +/**************************************************************************/ +/*! + Tries to authenticate a block of memory on a MIFARE card using the + INDATAEXCHANGE command. See section 7.3.8 of the PN532 User Manual + for more information on sending MIFARE and other commands. + + @param uid Pointer to a uint8_t array containing the card UID + @param uidLen The length (in bytes) of the card's UID (Should + be 4 for MIFARE Classic) + @param blockNumber The block number to authenticate. (0..63 for + 1KB cards, and 0..255 for 4KB cards). + @param keyNumber Which key type to use during authentication + (0 = MIFARE_CMD_AUTH_A, 1 = MIFARE_CMD_AUTH_B) + @param keyData Pointer to a uint8_t array containing the 6 uint8_t + key value + + @returns 1 if everything executed properly, 0 for an error +*/ +/**************************************************************************/ +uint8_t pn532_mifareclassic_AuthenticateBlock(pn532_t *obj, uint8_t *uid, uint8_t uidLen, uint32_t blockNumber, uint8_t keyNumber, uint8_t *keyData) +{ + uint8_t i; + + // Hang on to the key and uid data + memcpy(obj->_key, keyData, 6); + memcpy(obj->_uid, uid, uidLen); + obj->_uidLen = uidLen; + + MIFARE_DEBUG("Trying to authenticate card\n"); + for (int i = 0; i < obj->_uidLen; i++) + { + MIFARE_DEBUG(" %02x", obj->_uid[i]); + } + MIFARE_DEBUG("\n"); + MIFARE_DEBUG("Using authentication KEY %c\n", keyNumber ? 'B' : 'A'); + for (int i = 0; i < 6; i++) + { + MIFARE_DEBUG(" %02x", obj->_key[i]); + } + MIFARE_DEBUG("\n"); + + // Prepare the authentication command // + pn532_packetbuffer[0] = PN532_COMMAND_INDATAEXCHANGE; /* Data Exchange Header */ + pn532_packetbuffer[1] = 1; /* Max card numbers */ + pn532_packetbuffer[2] = (keyNumber) ? MIFARE_CMD_AUTH_B : MIFARE_CMD_AUTH_A; + pn532_packetbuffer[3] = blockNumber; /* Block Number (1K = 0..63, 4K = 0..255 */ + memcpy(pn532_packetbuffer + 4, obj->_key, 6); + uint8_t uid_offs = (obj->_uidLen == 7) ? 3 : 0; + for (i = 0; i < 4; i++) + { + pn532_packetbuffer[10 + i] = obj->_uid[uid_offs + i]; /* 4 uint8_t card ID */ + } + + if (!pn532_sendCommandCheckAck(obj, pn532_packetbuffer, 14, 1000)) + return 0; + + // Read the response packet + pn532_readdata(obj, pn532_packetbuffer, 12); + + // check if the response is valid and we are authenticated??? + // for an auth success it should be bytes 5-7: 0xD5 0x41 0x00 + // Mifare auth error is technically uint8_t 7: 0x14 but anything other and 0x00 is not good + if (pn532_packetbuffer[6] != 0x00) + { + MIFARE_DEBUG("Authentification failed\n"); + for (int i = 0; i < 12; i++) + { + MIFARE_DEBUG(" %02x", pn532_packetbuffer[i]); + } + MIFARE_DEBUG("\n"); + return 0; + } + + return 1; +} + +/**************************************************************************/ +/*! + Tries to read an entire 16-uint8_t data block at the specified block + address. + + @param blockNumber The block number to authenticate. (0..63 for + 1KB cards, and 0..255 for 4KB cards). + @param data Pointer to the uint8_t array that will hold the + retrieved data (if any) + + @returns 1 if everything executed properly, 0 for an error +*/ +/**************************************************************************/ +uint8_t pn532_mifareclassic_ReadDataBlock(pn532_t *obj, uint8_t blockNumber, uint8_t *data) +{ + MIFARE_DEBUG("Trying to read 16 bytes from block %d\n", blockNumber); + + /* Prepare the command */ + pn532_packetbuffer[0] = PN532_COMMAND_INDATAEXCHANGE; + pn532_packetbuffer[1] = 1; /* Card number */ + pn532_packetbuffer[2] = MIFARE_CMD_READ; /* Mifare Read command = 0x30 */ + pn532_packetbuffer[3] = blockNumber; /* Block Number (0..63 for 1K, 0..255 for 4K) */ + + /* Send the command */ + if (!pn532_sendCommandCheckAck(obj, pn532_packetbuffer, 4, 1000)) + { + MIFARE_DEBUG("Failed to receive ACK for read command\n"); + return 0; + } + + /* Read the response packet */ + pn532_readdata(obj, pn532_packetbuffer, 26); + + /* If uint8_t 8 isn't 0x00 we probably have an error */ + if (pn532_packetbuffer[6] != 0x00) + { + MIFARE_DEBUG("Unexpected response:"); + for (int i = 0; i < 26; i++) + { + MIFARE_DEBUG(" %02x", pn532_packetbuffer[i]); + } + MIFARE_DEBUG("\n"); + return 0; + } + + /* Copy the 16 data bytes to the output buffer */ + /* Block content starts at uint8_t 9 of a valid response */ + memcpy(data, pn532_packetbuffer + 7, 16); + +/* Display data for debug if requested */ + MIFARE_DEBUG("Block %d\n", blockNumber); + for (int i = 0; i < 16; i++) + { + MIFARE_DEBUG(" %02x", data[i]); + } + MIFARE_DEBUG("\n"); + + return 1; +} + +/**************************************************************************/ +/*! + Tries to write an entire 16-uint8_t data block at the specified block + address. + + @param blockNumber The block number to authenticate. (0..63 for + 1KB cards, and 0..255 for 4KB cards). + @param data The uint8_t array that contains the data to write. + + @returns 1 if everything executed properly, 0 for an error +*/ +/**************************************************************************/ +uint8_t pn532_mifareclassic_WriteDataBlock(pn532_t *obj, uint8_t blockNumber, uint8_t *data) +{ + MIFARE_DEBUG("Trying to write 16 bytes to block %d\n", blockNumber); + + /* Prepare the first command */ + pn532_packetbuffer[0] = PN532_COMMAND_INDATAEXCHANGE; + pn532_packetbuffer[1] = 1; /* Card number */ + pn532_packetbuffer[2] = MIFARE_CMD_WRITE; /* Mifare Write command = 0xA0 */ + pn532_packetbuffer[3] = blockNumber; /* Block Number (0..63 for 1K, 0..255 for 4K) */ + memcpy(pn532_packetbuffer + 4, data, 16); /* Data Payload */ + + /* Send the command */ + if (!pn532_sendCommandCheckAck(obj, pn532_packetbuffer, 20, 1000)) + { + MIFARE_DEBUG("Failed to receive ACK for write command\n"); + return 0; + } + PN532_DELAY(10); + + /* Read the response packet */ + pn532_readdata(obj, pn532_packetbuffer, 26); + + return 1; +} + +/**************************************************************************/ +/*! + Formats a Mifare Classic card to store NDEF Records + + @returns 1 if everything executed properly, 0 for an error +*/ +/**************************************************************************/ +uint8_t pn532_mifareclassic_FormatNDEF(pn532_t *obj) +{ + uint8_t sectorbuffer1[16] = {0x14, 0x01, 0x03, 0xE1, 0x03, 0xE1, 0x03, 0xE1, 0x03, 0xE1, 0x03, 0xE1, 0x03, 0xE1, 0x03, 0xE1}; + uint8_t sectorbuffer2[16] = {0x03, 0xE1, 0x03, 0xE1, 0x03, 0xE1, 0x03, 0xE1, 0x03, 0xE1, 0x03, 0xE1, 0x03, 0xE1, 0x03, 0xE1}; + uint8_t sectorbuffer3[16] = {0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0x78, 0x77, 0x88, 0xC1, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}; + + // Note 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 must be used for key A + // for the MAD sector in NDEF records (sector 0) + + // Write block 1 and 2 to the card + if (!(pn532_mifareclassic_WriteDataBlock(obj, 1, sectorbuffer1))) + return 0; + if (!(pn532_mifareclassic_WriteDataBlock(obj, 2, sectorbuffer2))) + return 0; + // Write key A and access rights card + if (!(pn532_mifareclassic_WriteDataBlock(obj, 3, sectorbuffer3))) + return 0; + + // Seems that everything was OK (?!) + return 1; +} + +/**************************************************************************/ +/*! + Writes an NDEF URI Record to the specified sector (1..15) + + Note that this function assumes that the Mifare Classic card is + already formatted to work as an "NFC Forum Tag" and uses a MAD1 + file system. You can use the NXP TagWriter app on Android to + properly format cards for this. + + @param sectorNumber The sector that the URI record should be written + to (can be 1..15 for a 1K card) + @param uriIdentifier The uri identifier code (0 = none, 0x01 = + "http://www.\n", etc.) + @param url The uri text to write (max 38 characters). + + @returns 1 if everything executed properly, 0 for an error +*/ +/**************************************************************************/ +uint8_t pn532_mifareclassic_WriteNDEFURI(pn532_t *obj, uint8_t sectorNumber, uint8_t uriIdentifier, const char *url) +{ + // Figure out how long the string is + uint8_t len = strlen(url); + + // Make sure we're within a 1K limit for the sector number + if ((sectorNumber < 1) || (sectorNumber > 15)) + return 0; + + // Make sure the URI payload is between 1 and 38 chars + if ((len < 1) || (len > 38)) + return 0; + + // Note 0xD3 0xF7 0xD3 0xF7 0xD3 0xF7 must be used for key A + // in NDEF records + + // Setup the sector buffer (w/pre-formatted TLV wrapper and NDEF message) + uint8_t sectorbuffer1[16] = {0x00, 0x00, 0x03, len + 5, 0xD1, 0x01, len + 1, 0x55, uriIdentifier, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; + uint8_t sectorbuffer2[16] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; + uint8_t sectorbuffer3[16] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; + uint8_t sectorbuffer4[16] = {0xD3, 0xF7, 0xD3, 0xF7, 0xD3, 0xF7, 0x7F, 0x07, 0x88, 0x40, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}; + if (len <= 6) + { + // Unlikely we'll get a url this short, but why not ... + memcpy(sectorbuffer1 + 9, url, len); + sectorbuffer1[len + 9] = 0xFE; + } + else if (len == 7) + { + // 0xFE needs to be wrapped around to next block + memcpy(sectorbuffer1 + 9, url, len); + sectorbuffer2[0] = 0xFE; + } + else if ((len > 7) && (len <= 22)) + { + // Url fits in two blocks + memcpy(sectorbuffer1 + 9, url, 7); + memcpy(sectorbuffer2, url + 7, len - 7); + sectorbuffer2[len - 7] = 0xFE; + } + else if (len == 23) + { + // 0xFE needs to be wrapped around to final block + memcpy(sectorbuffer1 + 9, url, 7); + memcpy(sectorbuffer2, url + 7, len - 7); + sectorbuffer3[0] = 0xFE; + } + else + { + // Url fits in three blocks + memcpy(sectorbuffer1 + 9, url, 7); + memcpy(sectorbuffer2, url + 7, 16); + memcpy(sectorbuffer3, url + 23, len - 24); + sectorbuffer3[len - 22] = 0xFE; + } + + // Now write all three blocks back to the card + if (!(pn532_mifareclassic_WriteDataBlock(obj, sectorNumber * 4, sectorbuffer1))) + return 0; + if (!(pn532_mifareclassic_WriteDataBlock(obj, (sectorNumber * 4) + 1, sectorbuffer2))) + return 0; + if (!(pn532_mifareclassic_WriteDataBlock(obj, (sectorNumber * 4) + 2, sectorbuffer3))) + return 0; + if (!(pn532_mifareclassic_WriteDataBlock(obj, (sectorNumber * 4) + 3, sectorbuffer4))) + return 0; + + // Seems that everything was OK (?!) + return 1; +} + +/***** Mifare Ultralight Functions ******/ + +/**************************************************************************/ +/*! + Tries to read an entire 4-uint8_t page at the specified address. + + @param page The page number (0..63 in most cases) + @param buffer Pointer to the uint8_t array that will hold the + retrieved data (if any) +*/ +/**************************************************************************/ +uint8_t pn532_mifareultralight_ReadPage(pn532_t *obj, uint8_t page, uint8_t *buffer) +{ + if (page >= 64) + { + MIFARE_DEBUG("Page value out of range\n"); + return 0; + } + + MIFARE_DEBUG("Reading page %d\n", page); + + /* Prepare the command */ + pn532_packetbuffer[0] = PN532_COMMAND_INDATAEXCHANGE; + pn532_packetbuffer[1] = 1; /* Card number */ + pn532_packetbuffer[2] = MIFARE_CMD_READ; /* Mifare Read command = 0x30 */ + pn532_packetbuffer[3] = page; /* Page Number (0..63 in most cases) */ + + /* Send the command */ + if (!pn532_sendCommandCheckAck(obj, pn532_packetbuffer, 4, 1000)) + { + MIFARE_DEBUG("Failed to receive ACK for write command\n"); + return 0; + } + + /* Read the response packet */ + pn532_readdata(obj, pn532_packetbuffer, 26); + MIFARE_DEBUG("Received:"); + for (int i = 0; i < 26; i++) + { + MIFARE_DEBUG(" %02x", pn532_packetbuffer[i]); + } + MIFARE_DEBUG("\n"); + + /* If uint8_t 8 isn't 0x00 we probably have an error */ + if (pn532_packetbuffer[7] == 0x00) + { + /* Copy the 4 data bytes to the output buffer */ + /* Block content starts at uint8_t 9 of a valid response */ + /* Note that the command actually reads 16 uint8_t or 4 */ + /* pages at a time ... we simply discard the last 12 */ + /* bytes */ + memcpy(buffer, pn532_packetbuffer + 8, 4); + } + else + { + MIFARE_DEBUG("Unexpected response reading block:"); + for (int i = 0; i < 26; i++) + { + MIFARE_DEBUG(" %02x", pn532_packetbuffer[i]); + } + MIFARE_DEBUG("\n"); + return 0; + } + +/* Display data for debug if requested */ + MIFARE_DEBUG("Page %d:", page); + for (int i = 0; i < 4; i++) + { + MIFARE_DEBUG(" %02x", buffer[i]); + } + MIFARE_DEBUG("\n"); + + // Return OK signal + return 1; +} + +/**************************************************************************/ +/*! + Tries to write an entire 4-uint8_t page at the specified block + address. + + @param page The page number to write. (0..63 for most cases) + @param data The uint8_t array that contains the data to write. + Should be exactly 4 bytes long. + + @returns 1 if everything executed properly, 0 for an error +*/ +/**************************************************************************/ +uint8_t pn532_mifareultralight_WritePage(pn532_t *obj, uint8_t page, uint8_t *data) +{ + + if (page >= 64) + { + MIFARE_DEBUG("Page value out of range\n"); + // Return Failed Signal + return 0; + } + + MIFARE_DEBUG("Trying to write 4 uint8_t page %d\n", page); + + /* Prepare the first command */ + pn532_packetbuffer[0] = PN532_COMMAND_INDATAEXCHANGE; + pn532_packetbuffer[1] = 1; /* Card number */ + pn532_packetbuffer[2] = MIFARE_ULTRALIGHT_CMD_WRITE; /* Mifare Ultralight Write command = 0xA2 */ + pn532_packetbuffer[3] = page; /* Page Number (0..63 for most cases) */ + memcpy(pn532_packetbuffer + 4, data, 4); /* Data Payload */ + + /* Send the command */ + if (!pn532_sendCommandCheckAck(obj, pn532_packetbuffer, 8, 1000)) + { + MIFARE_DEBUG("Failed to receive ACK for write command\n"); + // Return Failed Signal + return 0; + } + PN532_DELAY(10); + + /* Read the response packet */ + pn532_readdata(obj, pn532_packetbuffer, 26); + + // Return OK Signal + return 1; +} + +/***** NTAG2xx Functions ******/ + +/**************************************************************************/ +/*! + Tries to read an entire 4-uint8_t page at the specified address. + + @param page The page number (0..63 in most cases) + @param buffer Pointer to the uint8_t array that will hold the + retrieved data (if any) +*/ +/**************************************************************************/ +uint8_t pn532_ntag2xx_ReadPage(pn532_t *obj, uint8_t page, uint8_t *buffer) +{ + // TAG Type PAGES USER START USER STOP + // -------- ----- ---------- --------- + // NTAG 203 42 4 39 + // NTAG 213 45 4 39 + // NTAG 215 135 4 129 + // NTAG 216 231 4 225 + + if (page >= 231) + { + MIFARE_DEBUG("Page value out of range\n"); + return 0; + } + + MIFARE_DEBUG("Reading page %d\n", page); + + /* Prepare the command */ + pn532_packetbuffer[0] = PN532_COMMAND_INDATAEXCHANGE; + pn532_packetbuffer[1] = 1; /* Card number */ + pn532_packetbuffer[2] = MIFARE_CMD_READ; /* Mifare Read command = 0x30 */ + pn532_packetbuffer[3] = page; /* Page Number (0..63 in most cases) */ + + /* Send the command */ + if (!pn532_sendCommandCheckAck(obj, pn532_packetbuffer, 4, 1000)) + { + MIFARE_DEBUG("Failed to receive ACK for write command\n"); + return 0; + } + + /* Read the response packet */ + pn532_readdata(obj, pn532_packetbuffer, 26); + MIFARE_DEBUG("Received:"); + for (int i = 0; i < 26; i++) + { + MIFARE_DEBUG(" %02x", pn532_packetbuffer[i]); + } + MIFARE_DEBUG("\n"); + + /* If uint8_t 8 isn't 0x00 we probably have an error */ + if (pn532_packetbuffer[7] == 0x00) + { + /* Copy the 4 data bytes to the output buffer */ + /* Block content starts at uint8_t 9 of a valid response */ + /* Note that the command actually reads 16 uint8_t or 4 */ + /* pages at a time ... we simply discard the last 12 */ + /* bytes */ + memcpy(buffer, pn532_packetbuffer + 8, 4); + } + else + { + MIFARE_DEBUG("Unexpected response reading block:"); + for (int i = 0; i < 26; i++) + { + MIFARE_DEBUG(" %02x", pn532_packetbuffer[i]); + } + MIFARE_DEBUG("\n"); + return 0; + } + +/* Display data for debug if requested */ + MIFARE_DEBUG("Page %d:", page); + for (int i = 0; i < 4; i++) + { + MIFARE_DEBUG(" %02x", buffer[i]); + } + MIFARE_DEBUG("\n"); + + // Return OK signal + return 1; +} + +/**************************************************************************/ +/*! + Tries to write an entire 4-uint8_t page at the specified block + address. + + @param page The page number to write. (0..63 for most cases) + @param data The uint8_t array that contains the data to write. + Should be exactly 4 bytes long. + + @returns 1 if everything executed properly, 0 for an error +*/ +/**************************************************************************/ +uint8_t pn532_ntag2xx_WritePage(pn532_t *obj, uint8_t page, uint8_t *data) +{ + // TAG Type PAGES USER START USER STOP + // -------- ----- ---------- --------- + // NTAG 203 42 4 39 + // NTAG 213 45 4 39 + // NTAG 215 135 4 129 + // NTAG 216 231 4 225 + + if ((page < 4) || (page > 225)) + { + MIFARE_DEBUG("Page value out of range\n"); + // Return Failed Signal + return 0; + } + + MIFARE_DEBUG("Trying to write 4 uint8_t page %d\n", page); + + /* Prepare the first command */ + pn532_packetbuffer[0] = PN532_COMMAND_INDATAEXCHANGE; + pn532_packetbuffer[1] = 1; /* Card number */ + pn532_packetbuffer[2] = MIFARE_ULTRALIGHT_CMD_WRITE; /* Mifare Ultralight Write command = 0xA2 */ + pn532_packetbuffer[3] = page; /* Page Number (0..63 for most cases) */ + memcpy(pn532_packetbuffer + 4, data, 4); /* Data Payload */ + + /* Send the command */ + if (!pn532_sendCommandCheckAck(obj, pn532_packetbuffer, 8, 1000)) + { + MIFARE_DEBUG("Failed to receive ACK for write command\n"); + + // Return Failed Signal + return 0; + } + PN532_DELAY(10); + + /* Read the response packet */ + pn532_readdata(obj, pn532_packetbuffer, 26); + + // Return OK Signal + return 1; +} + +/**************************************************************************/ +/*! + Writes an NDEF URI Record starting at the specified page (4..nn) + + Note that this function assumes that the NTAG2xx card is + already formatted to work as an "NFC Forum Tag". + + @param uriIdentifier The uri identifier code (0 = none, 0x01 = + "http://www.\n", etc.) + @param url The uri text to write (null-terminated string). + @param dataLen The size of the data area for overflow checks. + + @returns 1 if everything executed properly, 0 for an error +*/ +/**************************************************************************/ +uint8_t pn532_ntag2xx_WriteNDEFURI(pn532_t *obj, uint8_t uriIdentifier, char *url, uint8_t dataLen) +{ + uint8_t pageBuffer[4] = {0, 0, 0, 0}; + + // Remove NDEF record overhead from the URI data (pageHeader below) + uint8_t wrapperSize = 12; + + // Figure out how long the string is + uint8_t len = strlen(url); + + // Make sure the URI payload will fit in dataLen (include 0xFE trailer) + if ((len < 1) || (len + 1 > (dataLen - wrapperSize))) + return 0; + + // Setup the record header + // See NFCForum-TS-Type-2-Tag_1.1.pdf for details + uint8_t pageHeader[12] = + { + /* NDEF Lock Control TLV (must be first and always present) */ + 0x01, /* Tag Field (0x01 = Lock Control TLV) */ + 0x03, /* Payload Length (always 3) */ + 0xA0, /* The position inside the tag of the lock bytes (upper 4 = page address, lower 4 = uint8_t offset) */ + 0x10, /* Size in bits of the lock area */ + 0x44, /* Size in bytes of a page and the number of bytes each lock bit can lock (4 bit + 4 bits) */ + /* NDEF Message TLV - URI Record */ + 0x03, /* Tag Field (0x03 = NDEF Message) */ + len + 5, /* Payload Length (not including 0xFE trailer) */ + 0xD1, /* NDEF Record Header (TNF=0x1:Well known record + SR + ME + MB) */ + 0x01, /* Type Length for the record type indicator */ + len + 1, /* Payload len */ + 0x55, /* Record Type Indicator (0x55 or 'U' = URI Record) */ + uriIdentifier /* URI Prefix (ex. 0x01 = "http://www.\n") */ + }; + + // Write 12 uint8_t header (three pages of data starting at page 4) + memcpy(pageBuffer, pageHeader, 4); + if (!(pn532_ntag2xx_WritePage(obj, 4, pageBuffer))) + return 0; + memcpy(pageBuffer, pageHeader + 4, 4); + if (!(pn532_ntag2xx_WritePage(obj, 5, pageBuffer))) + return 0; + memcpy(pageBuffer, pageHeader + 8, 4); + if (!(pn532_ntag2xx_WritePage(obj, 6, pageBuffer))) + return 0; + + // Write URI (starting at page 7) + uint8_t currentPage = 7; + char *urlcopy = url; + while (len) + { + if (len < 4) + { + memset(pageBuffer, 0, 4); + memcpy(pageBuffer, urlcopy, len); + pageBuffer[len] = 0xFE; // NDEF record footer + if (!(pn532_ntag2xx_WritePage(obj, currentPage, pageBuffer))) + return 0; + // DONE! + return 1; + } + else if (len == 4) + { + memcpy(pageBuffer, urlcopy, len); + if (!(pn532_ntag2xx_WritePage(obj, currentPage, pageBuffer))) + return 0; + memset(pageBuffer, 0, 4); + pageBuffer[0] = 0xFE; // NDEF record footer + currentPage++; + if (!(pn532_ntag2xx_WritePage(obj, currentPage, pageBuffer))) + return 0; + // DONE! + return 1; + } + else + { + // More than one page of data left + memcpy(pageBuffer, urlcopy, 4); + if (!(pn532_ntag2xx_WritePage(obj, currentPage, pageBuffer))) + return 0; + currentPage++; + urlcopy += 4; + len -= 4; + } + } + + // Seems that everything was OK (?!) + return 1; +} + +/************** high level communication functions (handles both I2C and SPI) */ + +/**************************************************************************/ +/*! + @brief Tries to read the SPI or I2C ACK signal +*/ +/**************************************************************************/ +bool pn532_readack(pn532_t *obj) +{ + uint8_t ackbuff[6]; + + pn532_readdata(obj, ackbuff, 6); + + return (0 == strncmp((char *)ackbuff, (char *)pn532ack, 6)); +} + +/**************************************************************************/ +/*! + @brief Return true if the PN532 is ready with a response. +*/ +/**************************************************************************/ +bool pn532_isready(pn532_t *obj) +{ + gpio_set_level(obj->_ss, 0); + PN532_DELAY(10); + pn532_spi_write(obj, PN532_SPI_STATREAD); + // read uint8_t + uint8_t x = pn532_spi_read(obj); + + gpio_set_level(obj->_ss, 1); + + // Check if status is ready. + return x == PN532_SPI_READY; +} + +/**************************************************************************/ +/*! + @brief Waits until the PN532 is ready. + + @param timeout Timeout before giving up +*/ +/**************************************************************************/ +bool pn532_waitready(pn532_t *obj, uint16_t timeout) +{ + uint16_t timer = 0; + while (!pn532_isready(obj)) + { + if (timeout != 0) + { + timer += 10; + if (timer > timeout) + { + PN532_DEBUG("TIMEOUT!\n"); + return false; + } + } + PN532_DELAY(10); + } + return true; +} + +/**************************************************************************/ +/*! + @brief Reads n bytes of data from the PN532 via SPI or I2C. + + @param buff Pointer to the buffer where data will be written + @param n Number of bytes to be read +*/ +/**************************************************************************/ +void pn532_readdata(pn532_t *obj, uint8_t *buff, uint8_t n) +{ + gpio_set_level(obj->_ss, 0); + PN532_DELAY(10); + pn532_spi_write(obj, PN532_SPI_DATAREAD); + + PN532_DEBUG("Reading:"); + for (uint8_t i = 0; i < n; i++) + { + PN532_DELAY(10); + buff[i] = pn532_spi_read(obj); + } + for (int i = 0; i < n; i++) + { + PN532_DEBUG(" %02x", buff[i]); + } + PN532_DEBUG("\n"); + + gpio_set_level(obj->_ss, 1); +} + +/**************************************************************************/ +/*! + @brief set the PN532 as iso14443a Target behaving as a SmartCard + @param None + #author Salvador Mendoza(salmg.net) new functions: + -AsTarget + -getDataTarget + -setDataTarget +*/ +/**************************************************************************/ +uint8_t pn532_AsTarget(pn532_t *obj) +{ + pn532_packetbuffer[0] = 0x8C; + uint8_t target[] = { + 0x8C, // INIT AS TARGET + 0x00, // MODE -> BITFIELD + 0x08, 0x00, //SENS_RES - MIFARE PARAMS + 0xdc, 0x44, 0x20, //NFCID1T + 0x60, //SEL_RES + 0x01, 0xfe, //NFCID2T MUST START WITH 01fe - FELICA PARAMS - POL_RES + 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, + 0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7, //PAD + 0xff, 0xff, //SYSTEM CODE + 0xaa, 0x99, 0x88, 0x77, 0x66, 0x55, 0x44, 0x33, 0x22, 0x11, 0x01, 0x00, //NFCID3t MAX 47 BYTES ATR_RES + 0x0d, 0x52, 0x46, 0x49, 0x44, 0x49, 0x4f, 0x74, 0x20, 0x50, 0x4e, 0x35, 0x33, 0x32 //HISTORICAL BYTES + }; + if (!pn532_sendCommandCheckAck(obj, target, sizeof(target), 1000)) + return false; + + // read data packet + pn532_readdata(obj, pn532_packetbuffer, 8); + + int offset = 5; + return (pn532_packetbuffer[offset] == 0x15); +} +/**************************************************************************/ +/*! + @brief retrieve response from the emulation mode + + @param cmd = data + @param cmdlen = data length +*/ +/**************************************************************************/ +uint8_t pn532_getDataTarget(pn532_t *obj, uint8_t *cmd, uint8_t *cmdlen) +{ + uint8_t length; + pn532_packetbuffer[0] = 0x86; + if (!pn532_sendCommandCheckAck(obj, pn532_packetbuffer, 1, 1000)) + { + PN532_DEBUG("Error en ack\n"); + return false; + } + + // read data packet + pn532_readdata(obj, pn532_packetbuffer, 64); + length = pn532_packetbuffer[3] - 3; + + //if (length > *responseLength) {// Bug, should avoid it in the reading target data + // length = *responseLength; // silent truncation... + //} + + for (int i = 0; i < length; ++i) + { + cmd[i] = pn532_packetbuffer[8 + i]; + } + *cmdlen = length; + return true; +} + +/**************************************************************************/ +/*! + @brief set data in PN532 in the emulation mode + + @param cmd = data + @param cmdlen = data length +*/ +/**************************************************************************/ +uint8_t pn532_setDataTarget(pn532_t *obj, uint8_t *cmd, uint8_t cmdlen) +{ + uint8_t length; + //cmd1[0] = 0x8E; Must! + + if (!pn532_sendCommandCheckAck(obj, cmd, cmdlen, 1000)) + return false; + + // read data packet + pn532_readdata(obj, pn532_packetbuffer, 8); + length = pn532_packetbuffer[3] - 3; + for (int i = 0; i < length; ++i) + { + cmd[i] = pn532_packetbuffer[8 + i]; + } + //cmdl = 0 + cmdlen = length; + + int offset = 5; + return (pn532_packetbuffer[offset] == 0x15); +} + +/**************************************************************************/ +/*! + @brief Writes a command to the PN532, automatically inserting the + preamble and required frame details (checksum, len, etc.) + + @param cmd Pointer to the command buffer + @param cmdlen Command length in bytes +*/ +/**************************************************************************/ +void pn532_writecommand(pn532_t *obj, uint8_t *cmd, uint8_t cmdlen) +{ + uint8_t checksum; + + cmdlen++; + + PN532_DEBUG("Sending:"); + + gpio_set_level(obj->_ss, 0); + PN532_DELAY(10); // or whatever the PN532_DELAY is for waking up the board + pn532_spi_write(obj, PN532_SPI_DATAWRITE); + + checksum = PN532_PREAMBLE + PN532_PREAMBLE + PN532_STARTCODE2; + pn532_spi_write(obj, PN532_PREAMBLE); + pn532_spi_write(obj, PN532_PREAMBLE); + pn532_spi_write(obj, PN532_STARTCODE2); + + pn532_spi_write(obj, cmdlen); + pn532_spi_write(obj, ~cmdlen + 1); + + pn532_spi_write(obj, PN532_HOSTTOPN532); + checksum += PN532_HOSTTOPN532; + + PN532_DEBUG(" %02x %02x %02x %02x %02x %02x", (uint8_t)PN532_PREAMBLE, (uint8_t)PN532_PREAMBLE, (uint8_t)PN532_STARTCODE2, (uint8_t)cmdlen, (uint8_t)(~cmdlen + 1), (uint8_t)PN532_HOSTTOPN532); + + for (uint8_t i = 0; i < cmdlen - 1; i++) + { + pn532_spi_write(obj, cmd[i]); + checksum += cmd[i]; + PN532_DEBUG(" %02x", cmd[i]); + } + + pn532_spi_write(obj, ~checksum); + pn532_spi_write(obj, PN532_POSTAMBLE); + gpio_set_level(obj->_ss, 1); + + PN532_DEBUG(" %02x %02x\n", (uint8_t)~checksum, (uint8_t)PN532_POSTAMBLE); +} +/************** low level SPI */ + +/**************************************************************************/ +/*! + @brief Low-level SPI write wrapper + + @param c 8-bit command to write to the SPI bus +*/ +/**************************************************************************/ +void pn532_spi_write(pn532_t *obj, uint8_t c) +{ + int8_t i; + gpio_set_level(obj->_clk, 1); + + for (i = 0; i < 8; i++) + { + gpio_set_level(obj->_clk, 0); + if (c & _BV(i)) + { + gpio_set_level(obj->_mosi, 1); + } + else + { + gpio_set_level(obj->_mosi, 0); + } + gpio_set_level(obj->_clk, 1); + } +} + +/**************************************************************************/ +/*! + @brief Low-level SPI read wrapper + + @returns The 8-bit value that was read from the SPI bus +*/ +/**************************************************************************/ +uint8_t pn532_spi_read(pn532_t *obj) +{ + int8_t i, x; + x = 0; + + gpio_set_level(obj->_clk, 1); + + for (i = 0; i < 8; i++) + { + if (gpio_get_level(obj->_miso)) + { + x |= _BV(i); + } + gpio_set_level(obj->_clk, 0); + gpio_set_level(obj->_clk, 1); + } + + return x; +} diff --git a/partitions.csv b/partitions.csv new file mode 100644 index 0000000..1a38dca --- /dev/null +++ b/partitions.csv @@ -0,0 +1,5 @@ +# Name, Type, SubType, Offset, Size, Flags +nvs, data, nvs, 0x9000, 0x6000, +phy_init, data, phy, 0xf000, 0x1000, +factory, app, factory, 0x10000, 2M, +nvs_key, data, nvs_keys, , 0x1000, encrypted diff --git a/sdkconfig b/sdkconfig new file mode 100644 index 0000000..ebf8518 --- /dev/null +++ b/sdkconfig @@ -0,0 +1,1990 @@ +# +# Automatically generated file. DO NOT EDIT. +# Espressif IoT Development Framework (ESP-IDF) 5.2.1 Project Configuration +# +CONFIG_SOC_ADC_SUPPORTED=y +CONFIG_SOC_DEDICATED_GPIO_SUPPORTED=y +CONFIG_SOC_UART_SUPPORTED=y +CONFIG_SOC_GDMA_SUPPORTED=y +CONFIG_SOC_AHB_GDMA_SUPPORTED=y +CONFIG_SOC_GPTIMER_SUPPORTED=y +CONFIG_SOC_TWAI_SUPPORTED=y +CONFIG_SOC_BT_SUPPORTED=y +CONFIG_SOC_ASYNC_MEMCPY_SUPPORTED=y +CONFIG_SOC_USB_SERIAL_JTAG_SUPPORTED=y +CONFIG_SOC_TEMP_SENSOR_SUPPORTED=y +CONFIG_SOC_XT_WDT_SUPPORTED=y +CONFIG_SOC_WIFI_SUPPORTED=y +CONFIG_SOC_SUPPORTS_SECURE_DL_MODE=y +CONFIG_SOC_EFUSE_KEY_PURPOSE_FIELD=y +CONFIG_SOC_EFUSE_HAS_EFUSE_RST_BUG=y +CONFIG_SOC_EFUSE_SUPPORTED=y +CONFIG_SOC_RTC_FAST_MEM_SUPPORTED=y +CONFIG_SOC_RTC_MEM_SUPPORTED=y +CONFIG_SOC_I2S_SUPPORTED=y +CONFIG_SOC_RMT_SUPPORTED=y +CONFIG_SOC_SDM_SUPPORTED=y +CONFIG_SOC_GPSPI_SUPPORTED=y +CONFIG_SOC_LEDC_SUPPORTED=y +CONFIG_SOC_I2C_SUPPORTED=y +CONFIG_SOC_SYSTIMER_SUPPORTED=y +CONFIG_SOC_SUPPORT_COEXISTENCE=y +CONFIG_SOC_AES_SUPPORTED=y +CONFIG_SOC_MPI_SUPPORTED=y +CONFIG_SOC_SHA_SUPPORTED=y +CONFIG_SOC_HMAC_SUPPORTED=y +CONFIG_SOC_DIG_SIGN_SUPPORTED=y +CONFIG_SOC_FLASH_ENC_SUPPORTED=y +CONFIG_SOC_SECURE_BOOT_SUPPORTED=y +CONFIG_SOC_MEMPROT_SUPPORTED=y +CONFIG_SOC_BOD_SUPPORTED=y +CONFIG_SOC_CLK_TREE_SUPPORTED=y +CONFIG_SOC_ASSIST_DEBUG_SUPPORTED=y +CONFIG_SOC_WDT_SUPPORTED=y +CONFIG_SOC_SPI_FLASH_SUPPORTED=y +CONFIG_SOC_XTAL_SUPPORT_40M=y +CONFIG_SOC_AES_SUPPORT_DMA=y +CONFIG_SOC_AES_GDMA=y +CONFIG_SOC_AES_SUPPORT_AES_128=y +CONFIG_SOC_AES_SUPPORT_AES_256=y +CONFIG_SOC_ADC_DIG_CTRL_SUPPORTED=y +CONFIG_SOC_ADC_ARBITER_SUPPORTED=y +CONFIG_SOC_ADC_DIG_IIR_FILTER_SUPPORTED=y +CONFIG_SOC_ADC_MONITOR_SUPPORTED=y +CONFIG_SOC_ADC_DMA_SUPPORTED=y +CONFIG_SOC_ADC_PERIPH_NUM=2 +CONFIG_SOC_ADC_MAX_CHANNEL_NUM=5 +CONFIG_SOC_ADC_ATTEN_NUM=4 +CONFIG_SOC_ADC_DIGI_CONTROLLER_NUM=1 +CONFIG_SOC_ADC_PATT_LEN_MAX=8 +CONFIG_SOC_ADC_DIGI_MIN_BITWIDTH=12 +CONFIG_SOC_ADC_DIGI_MAX_BITWIDTH=12 +CONFIG_SOC_ADC_DIGI_RESULT_BYTES=4 +CONFIG_SOC_ADC_DIGI_DATA_BYTES_PER_CONV=4 +CONFIG_SOC_ADC_DIGI_IIR_FILTER_NUM=2 +CONFIG_SOC_ADC_DIGI_MONITOR_NUM=2 +CONFIG_SOC_ADC_SAMPLE_FREQ_THRES_HIGH=83333 +CONFIG_SOC_ADC_SAMPLE_FREQ_THRES_LOW=611 +CONFIG_SOC_ADC_RTC_MIN_BITWIDTH=12 +CONFIG_SOC_ADC_RTC_MAX_BITWIDTH=12 +CONFIG_SOC_ADC_CALIBRATION_V1_SUPPORTED=y +CONFIG_SOC_ADC_SELF_HW_CALI_SUPPORTED=y +CONFIG_SOC_ADC_SHARED_POWER=y +CONFIG_SOC_APB_BACKUP_DMA=y +CONFIG_SOC_BROWNOUT_RESET_SUPPORTED=y +CONFIG_SOC_SHARED_IDCACHE_SUPPORTED=y +CONFIG_SOC_CACHE_MEMORY_IBANK_SIZE=0x4000 +CONFIG_SOC_CPU_CORES_NUM=1 +CONFIG_SOC_CPU_INTR_NUM=32 +CONFIG_SOC_CPU_HAS_FLEXIBLE_INTC=y +CONFIG_SOC_CPU_BREAKPOINTS_NUM=8 +CONFIG_SOC_CPU_WATCHPOINTS_NUM=8 +CONFIG_SOC_CPU_WATCHPOINT_MAX_REGION_SIZE=0x80000000 +CONFIG_SOC_DS_SIGNATURE_MAX_BIT_LEN=3072 +CONFIG_SOC_DS_KEY_PARAM_MD_IV_LENGTH=16 +CONFIG_SOC_DS_KEY_CHECK_MAX_WAIT_US=1100 +CONFIG_SOC_AHB_GDMA_VERSION=1 +CONFIG_SOC_GDMA_NUM_GROUPS_MAX=1 +CONFIG_SOC_GDMA_PAIRS_PER_GROUP_MAX=3 +CONFIG_SOC_GPIO_PORT=1 +CONFIG_SOC_GPIO_PIN_COUNT=22 +CONFIG_SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER=y +CONFIG_SOC_GPIO_FILTER_CLK_SUPPORT_APB=y +CONFIG_SOC_GPIO_SUPPORT_FORCE_HOLD=y +CONFIG_SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP=y +CONFIG_SOC_GPIO_IN_RANGE_MAX=21 +CONFIG_SOC_GPIO_OUT_RANGE_MAX=21 +CONFIG_SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK=0 +CONFIG_SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK=0x00000000003FFFC0 +CONFIG_SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX=y +CONFIG_SOC_DEDIC_GPIO_OUT_CHANNELS_NUM=8 +CONFIG_SOC_DEDIC_GPIO_IN_CHANNELS_NUM=8 +CONFIG_SOC_DEDIC_PERIPH_ALWAYS_ENABLE=y +CONFIG_SOC_I2C_NUM=1 +CONFIG_SOC_I2C_FIFO_LEN=32 +CONFIG_SOC_I2C_CMD_REG_NUM=8 +CONFIG_SOC_I2C_SUPPORT_SLAVE=y +CONFIG_SOC_I2C_SUPPORT_HW_CLR_BUS=y +CONFIG_SOC_I2C_SUPPORT_XTAL=y +CONFIG_SOC_I2C_SUPPORT_RTC=y +CONFIG_SOC_I2C_SUPPORT_10BIT_ADDR=y +CONFIG_SOC_I2C_SLAVE_SUPPORT_BROADCAST=y +CONFIG_SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE=y +CONFIG_SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS=y +CONFIG_SOC_I2S_NUM=1 +CONFIG_SOC_I2S_HW_VERSION_2=y +CONFIG_SOC_I2S_SUPPORTS_XTAL=y +CONFIG_SOC_I2S_SUPPORTS_PLL_F160M=y +CONFIG_SOC_I2S_SUPPORTS_PCM=y +CONFIG_SOC_I2S_SUPPORTS_PDM=y +CONFIG_SOC_I2S_SUPPORTS_PDM_TX=y +CONFIG_SOC_I2S_PDM_MAX_TX_LINES=2 +CONFIG_SOC_I2S_SUPPORTS_TDM=y +CONFIG_SOC_LEDC_SUPPORT_APB_CLOCK=y +CONFIG_SOC_LEDC_SUPPORT_XTAL_CLOCK=y +CONFIG_SOC_LEDC_CHANNEL_NUM=6 +CONFIG_SOC_LEDC_TIMER_BIT_WIDTH=14 +CONFIG_SOC_LEDC_SUPPORT_FADE_STOP=y +CONFIG_SOC_MMU_LINEAR_ADDRESS_REGION_NUM=1 +CONFIG_SOC_MMU_PERIPH_NUM=1 +CONFIG_SOC_MPU_MIN_REGION_SIZE=0x20000000 +CONFIG_SOC_MPU_REGIONS_MAX_NUM=8 +CONFIG_SOC_RMT_GROUPS=1 +CONFIG_SOC_RMT_TX_CANDIDATES_PER_GROUP=2 +CONFIG_SOC_RMT_RX_CANDIDATES_PER_GROUP=2 +CONFIG_SOC_RMT_CHANNELS_PER_GROUP=4 +CONFIG_SOC_RMT_MEM_WORDS_PER_CHANNEL=48 +CONFIG_SOC_RMT_SUPPORT_RX_PINGPONG=y +CONFIG_SOC_RMT_SUPPORT_RX_DEMODULATION=y +CONFIG_SOC_RMT_SUPPORT_TX_ASYNC_STOP=y +CONFIG_SOC_RMT_SUPPORT_TX_LOOP_COUNT=y +CONFIG_SOC_RMT_SUPPORT_TX_SYNCHRO=y +CONFIG_SOC_RMT_SUPPORT_TX_CARRIER_DATA_ONLY=y +CONFIG_SOC_RMT_SUPPORT_XTAL=y +CONFIG_SOC_RMT_SUPPORT_APB=y +CONFIG_SOC_RMT_SUPPORT_RC_FAST=y +CONFIG_SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH=128 +CONFIG_SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM=108 +CONFIG_SOC_RTCIO_PIN_COUNT=0 +CONFIG_SOC_MPI_MEM_BLOCKS_NUM=4 +CONFIG_SOC_MPI_OPERATIONS_NUM=3 +CONFIG_SOC_RSA_MAX_BIT_LEN=3072 +CONFIG_SOC_SHA_DMA_MAX_BUFFER_SIZE=3968 +CONFIG_SOC_SHA_SUPPORT_DMA=y +CONFIG_SOC_SHA_SUPPORT_RESUME=y +CONFIG_SOC_SHA_GDMA=y +CONFIG_SOC_SHA_SUPPORT_SHA1=y +CONFIG_SOC_SHA_SUPPORT_SHA224=y +CONFIG_SOC_SHA_SUPPORT_SHA256=y +CONFIG_SOC_SDM_GROUPS=1 +CONFIG_SOC_SDM_CHANNELS_PER_GROUP=4 +CONFIG_SOC_SDM_CLK_SUPPORT_APB=y +CONFIG_SOC_SPI_PERIPH_NUM=2 +CONFIG_SOC_SPI_MAX_CS_NUM=6 +CONFIG_SOC_SPI_MAXIMUM_BUFFER_SIZE=64 +CONFIG_SOC_SPI_SUPPORT_DDRCLK=y +CONFIG_SOC_SPI_SLAVE_SUPPORT_SEG_TRANS=y +CONFIG_SOC_SPI_SUPPORT_CD_SIG=y +CONFIG_SOC_SPI_SUPPORT_CONTINUOUS_TRANS=y +CONFIG_SOC_SPI_SUPPORT_SLAVE_HD_VER2=y +CONFIG_SOC_SPI_SUPPORT_CLK_APB=y +CONFIG_SOC_SPI_SUPPORT_CLK_XTAL=y +CONFIG_SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT=y +CONFIG_SOC_MEMSPI_IS_INDEPENDENT=y +CONFIG_SOC_SPI_MAX_PRE_DIVIDER=16 +CONFIG_SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE=y +CONFIG_SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND=y +CONFIG_SOC_SPI_MEM_SUPPORT_AUTO_RESUME=y +CONFIG_SOC_SPI_MEM_SUPPORT_IDLE_INTR=y +CONFIG_SOC_SPI_MEM_SUPPORT_SW_SUSPEND=y +CONFIG_SOC_SPI_MEM_SUPPORT_CHECK_SUS=y +CONFIG_SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE=y +CONFIG_SOC_SPI_MEM_SUPPORT_WRAP=y +CONFIG_SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED=y +CONFIG_SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED=y +CONFIG_SOC_MEMSPI_SRC_FREQ_26M_SUPPORTED=y +CONFIG_SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED=y +CONFIG_SOC_SYSTIMER_COUNTER_NUM=2 +CONFIG_SOC_SYSTIMER_ALARM_NUM=3 +CONFIG_SOC_SYSTIMER_BIT_WIDTH_LO=32 +CONFIG_SOC_SYSTIMER_BIT_WIDTH_HI=20 +CONFIG_SOC_SYSTIMER_FIXED_DIVIDER=y +CONFIG_SOC_SYSTIMER_INT_LEVEL=y +CONFIG_SOC_SYSTIMER_ALARM_MISS_COMPENSATE=y +CONFIG_SOC_TIMER_GROUPS=2 +CONFIG_SOC_TIMER_GROUP_TIMERS_PER_GROUP=1 +CONFIG_SOC_TIMER_GROUP_COUNTER_BIT_WIDTH=54 +CONFIG_SOC_TIMER_GROUP_SUPPORT_XTAL=y +CONFIG_SOC_TIMER_GROUP_SUPPORT_APB=y +CONFIG_SOC_TIMER_GROUP_TOTAL_TIMERS=2 +CONFIG_SOC_MWDT_SUPPORT_XTAL=y +CONFIG_SOC_TWAI_CONTROLLER_NUM=1 +CONFIG_SOC_TWAI_CLK_SUPPORT_APB=y +CONFIG_SOC_TWAI_BRP_MIN=2 +CONFIG_SOC_TWAI_BRP_MAX=16384 +CONFIG_SOC_TWAI_SUPPORTS_RX_STATUS=y +CONFIG_SOC_EFUSE_DIS_DOWNLOAD_ICACHE=y +CONFIG_SOC_EFUSE_DIS_PAD_JTAG=y +CONFIG_SOC_EFUSE_DIS_USB_JTAG=y +CONFIG_SOC_EFUSE_DIS_DIRECT_BOOT=y +CONFIG_SOC_EFUSE_SOFT_DIS_JTAG=y +CONFIG_SOC_EFUSE_DIS_ICACHE=y +CONFIG_SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK=y +CONFIG_SOC_SECURE_BOOT_V2_RSA=y +CONFIG_SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS=3 +CONFIG_SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS=y +CONFIG_SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY=y +CONFIG_SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX=32 +CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES=y +CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES_128=y +CONFIG_SOC_MEMPROT_CPU_PREFETCH_PAD_SIZE=16 +CONFIG_SOC_MEMPROT_MEM_ALIGN_SIZE=512 +CONFIG_SOC_UART_NUM=2 +CONFIG_SOC_UART_HP_NUM=2 +CONFIG_SOC_UART_FIFO_LEN=128 +CONFIG_SOC_UART_BITRATE_MAX=5000000 +CONFIG_SOC_UART_SUPPORT_APB_CLK=y +CONFIG_SOC_UART_SUPPORT_RTC_CLK=y +CONFIG_SOC_UART_SUPPORT_XTAL_CLK=y +CONFIG_SOC_UART_SUPPORT_WAKEUP_INT=y +CONFIG_SOC_UART_SUPPORT_FSM_TX_WAIT_SEND=y +CONFIG_SOC_COEX_HW_PTI=y +CONFIG_SOC_PHY_DIG_REGS_MEM_SIZE=21 +CONFIG_SOC_MAC_BB_PD_MEM_SIZE=192 +CONFIG_SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH=12 +CONFIG_SOC_PM_SUPPORT_WIFI_WAKEUP=y +CONFIG_SOC_PM_SUPPORT_BT_WAKEUP=y +CONFIG_SOC_PM_SUPPORT_CPU_PD=y +CONFIG_SOC_PM_SUPPORT_WIFI_PD=y +CONFIG_SOC_PM_SUPPORT_BT_PD=y +CONFIG_SOC_PM_SUPPORT_RC_FAST_PD=y +CONFIG_SOC_PM_SUPPORT_VDDSDIO_PD=y +CONFIG_SOC_PM_SUPPORT_MAC_BB_PD=y +CONFIG_SOC_PM_CPU_RETENTION_BY_RTCCNTL=y +CONFIG_SOC_PM_MODEM_RETENTION_BY_BACKUPDMA=y +CONFIG_SOC_CLK_RC_FAST_D256_SUPPORTED=y +CONFIG_SOC_RTC_SLOW_CLK_SUPPORT_RC_FAST_D256=y +CONFIG_SOC_CLK_RC_FAST_SUPPORT_CALIBRATION=y +CONFIG_SOC_CLK_XTAL32K_SUPPORTED=y +CONFIG_SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC=y +CONFIG_SOC_TEMPERATURE_SENSOR_SUPPORT_XTAL=y +CONFIG_SOC_WIFI_HW_TSF=y +CONFIG_SOC_WIFI_FTM_SUPPORT=y +CONFIG_SOC_WIFI_GCMP_SUPPORT=y +CONFIG_SOC_WIFI_WAPI_SUPPORT=y +CONFIG_SOC_WIFI_CSI_SUPPORT=y +CONFIG_SOC_WIFI_MESH_SUPPORT=y +CONFIG_SOC_WIFI_SUPPORT_VARIABLE_BEACON_WINDOW=y +CONFIG_SOC_BLE_SUPPORTED=y +CONFIG_SOC_BLE_MESH_SUPPORTED=y +CONFIG_SOC_BLE_50_SUPPORTED=y +CONFIG_SOC_BLE_DEVICE_PRIVACY_SUPPORTED=y +CONFIG_SOC_BLUFI_SUPPORTED=y +CONFIG_SOC_PHY_COMBO_MODULE=y +CONFIG_IDF_CMAKE=y +CONFIG_IDF_TOOLCHAIN="gcc" +CONFIG_IDF_TARGET_ARCH_RISCV=y +CONFIG_IDF_TARGET_ARCH="riscv" +CONFIG_IDF_TARGET="esp32c3" +CONFIG_IDF_INIT_VERSION="5.2.1" +CONFIG_IDF_TARGET_ESP32C3=y +CONFIG_IDF_FIRMWARE_CHIP_ID=0x0005 + +# +# Build type +# +CONFIG_APP_BUILD_TYPE_APP_2NDBOOT=y +# CONFIG_APP_BUILD_TYPE_RAM is not set +CONFIG_APP_BUILD_GENERATE_BINARIES=y +CONFIG_APP_BUILD_BOOTLOADER=y +CONFIG_APP_BUILD_USE_FLASH_SECTIONS=y +# CONFIG_APP_REPRODUCIBLE_BUILD is not set +# CONFIG_APP_NO_BLOBS is not set +# end of Build type + +# +# Bootloader config +# + +# +# Bootloader manager +# +CONFIG_BOOTLOADER_COMPILE_TIME_DATE=y +CONFIG_BOOTLOADER_PROJECT_VER=1 +# end of Bootloader manager + +CONFIG_BOOTLOADER_OFFSET_IN_FLASH=0x0 +CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y +# CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_DEBUG is not set +# CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_PERF is not set +# CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_NONE is not set +# CONFIG_BOOTLOADER_LOG_LEVEL_NONE is not set +# CONFIG_BOOTLOADER_LOG_LEVEL_ERROR is not set +# CONFIG_BOOTLOADER_LOG_LEVEL_WARN is not set +CONFIG_BOOTLOADER_LOG_LEVEL_INFO=y +# CONFIG_BOOTLOADER_LOG_LEVEL_DEBUG is not set +# CONFIG_BOOTLOADER_LOG_LEVEL_VERBOSE is not set +CONFIG_BOOTLOADER_LOG_LEVEL=3 + +# +# Serial Flash Configurations +# +# CONFIG_BOOTLOADER_FLASH_DC_AWARE is not set +CONFIG_BOOTLOADER_FLASH_XMC_SUPPORT=y +# end of Serial Flash Configurations + +# CONFIG_BOOTLOADER_FACTORY_RESET is not set +# CONFIG_BOOTLOADER_APP_TEST is not set +CONFIG_BOOTLOADER_REGION_PROTECTION_ENABLE=y +CONFIG_BOOTLOADER_WDT_ENABLE=y +# CONFIG_BOOTLOADER_WDT_DISABLE_IN_USER_CODE is not set +CONFIG_BOOTLOADER_WDT_TIME_MS=9000 +# CONFIG_BOOTLOADER_APP_ROLLBACK_ENABLE is not set +# CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP is not set +# CONFIG_BOOTLOADER_SKIP_VALIDATE_ON_POWER_ON is not set +# CONFIG_BOOTLOADER_SKIP_VALIDATE_ALWAYS is not set +CONFIG_BOOTLOADER_RESERVE_RTC_SIZE=0 +# CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC is not set +# end of Bootloader config + +# +# Security features +# +CONFIG_SECURE_SIGNED_ON_UPDATE=y +CONFIG_SECURE_SIGNED_APPS=y +CONFIG_SECURE_BOOT_V2_RSA_SUPPORTED=y +CONFIG_SECURE_BOOT_V2_PREFERRED=y +CONFIG_SECURE_SIGNED_APPS_NO_SECURE_BOOT=y +CONFIG_SECURE_SIGNED_APPS_RSA_SCHEME=y +CONFIG_SECURE_SIGNED_ON_UPDATE_NO_SECURE_BOOT=y +CONFIG_SECURE_BOOT_BUILD_SIGNED_BINARIES=y +CONFIG_SECURE_BOOT_SIGNING_KEY="signing_key.pem" +CONFIG_SECURE_FLASH_ENC_ENABLED=y +# CONFIG_SECURE_FLASH_ENCRYPTION_MODE_DEVELOPMENT is not set +CONFIG_SECURE_FLASH_ENCRYPTION_MODE_RELEASE=y +CONFIG_SECURE_FLASH_HAS_WRITE_PROTECTION_CACHE=y + +# +# Potentially insecure options +# +# CONFIG_SECURE_BOOT_ALLOW_SHORT_APP_PARTITION is not set +# CONFIG_SECURE_FLASH_SKIP_WRITE_PROTECTION_CACHE is not set +# end of Potentially insecure options + +# CONFIG_SECURE_FLASH_ENCRYPT_ONLY_IMAGE_LEN_IN_APP_PART is not set +CONFIG_SECURE_FLASH_CHECK_ENC_EN_IN_APP=y +CONFIG_SECURE_ROM_DL_MODE_ENABLED=y +# CONFIG_SECURE_DISABLE_ROM_DL_MODE is not set +CONFIG_SECURE_ENABLE_SECURE_ROM_DL_MODE=y +# CONFIG_SECURE_INSECURE_ALLOW_DL_MODE is not set +# end of Security features + +# +# Application manager +# +CONFIG_APP_COMPILE_TIME_DATE=y +# CONFIG_APP_EXCLUDE_PROJECT_VER_VAR is not set +# CONFIG_APP_EXCLUDE_PROJECT_NAME_VAR is not set +# CONFIG_APP_PROJECT_VER_FROM_CONFIG is not set +CONFIG_APP_RETRIEVE_LEN_ELF_SHA=9 +# end of Application manager + +CONFIG_ESP_ROM_HAS_CRC_LE=y +CONFIG_ESP_ROM_HAS_CRC_BE=y +CONFIG_ESP_ROM_HAS_MZ_CRC32=y +CONFIG_ESP_ROM_HAS_JPEG_DECODE=y +CONFIG_ESP_ROM_UART_CLK_IS_XTAL=y +CONFIG_ESP_ROM_USB_SERIAL_DEVICE_NUM=3 +CONFIG_ESP_ROM_HAS_RETARGETABLE_LOCKING=y +CONFIG_ESP_ROM_HAS_ERASE_0_REGION_BUG=y +CONFIG_ESP_ROM_GET_CLK_FREQ=y +CONFIG_ESP_ROM_NEEDS_SWSETUP_WORKAROUND=y +CONFIG_ESP_ROM_HAS_LAYOUT_TABLE=y +CONFIG_ESP_ROM_HAS_SPI_FLASH=y +CONFIG_ESP_ROM_HAS_ETS_PRINTF_BUG=y +CONFIG_ESP_ROM_HAS_NEWLIB_NANO_FORMAT=y +CONFIG_ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE=y +CONFIG_ESP_ROM_RAM_APP_NEEDS_MMU_INIT=y +CONFIG_ESP_ROM_HAS_SW_FLOAT=y + +# +# Boot ROM Behavior +# +CONFIG_BOOT_ROM_LOG_ALWAYS_ON=y +# CONFIG_BOOT_ROM_LOG_ALWAYS_OFF is not set +# CONFIG_BOOT_ROM_LOG_ON_GPIO_HIGH is not set +# CONFIG_BOOT_ROM_LOG_ON_GPIO_LOW is not set +# end of Boot ROM Behavior + +# +# Serial flasher config +# +CONFIG_ESPTOOLPY_NO_STUB=y +# CONFIG_ESPTOOLPY_FLASHMODE_QIO is not set +# CONFIG_ESPTOOLPY_FLASHMODE_QOUT is not set +CONFIG_ESPTOOLPY_FLASHMODE_DIO=y +# CONFIG_ESPTOOLPY_FLASHMODE_DOUT is not set +CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_STR=y +CONFIG_ESPTOOLPY_FLASHMODE="dio" +CONFIG_ESPTOOLPY_FLASHFREQ_80M=y +# CONFIG_ESPTOOLPY_FLASHFREQ_40M is not set +# CONFIG_ESPTOOLPY_FLASHFREQ_26M is not set +# CONFIG_ESPTOOLPY_FLASHFREQ_20M is not set +CONFIG_ESPTOOLPY_FLASHFREQ_80M_DEFAULT=y +CONFIG_ESPTOOLPY_FLASHFREQ="80m" +# CONFIG_ESPTOOLPY_FLASHSIZE_1MB is not set +# CONFIG_ESPTOOLPY_FLASHSIZE_2MB is not set +CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y +# CONFIG_ESPTOOLPY_FLASHSIZE_8MB is not set +# CONFIG_ESPTOOLPY_FLASHSIZE_16MB is not set +# CONFIG_ESPTOOLPY_FLASHSIZE_32MB is not set +# CONFIG_ESPTOOLPY_FLASHSIZE_64MB is not set +# CONFIG_ESPTOOLPY_FLASHSIZE_128MB is not set +CONFIG_ESPTOOLPY_FLASHSIZE="4MB" +# CONFIG_ESPTOOLPY_HEADER_FLASHSIZE_UPDATE is not set +CONFIG_ESPTOOLPY_BEFORE_RESET=y +# CONFIG_ESPTOOLPY_BEFORE_NORESET is not set +CONFIG_ESPTOOLPY_BEFORE="default_reset" +CONFIG_ESPTOOLPY_AFTER_RESET=y +# CONFIG_ESPTOOLPY_AFTER_NORESET is not set +CONFIG_ESPTOOLPY_AFTER="hard_reset" +CONFIG_ESPTOOLPY_MONITOR_BAUD=115200 +# end of Serial flasher config + +# +# Partition Table +# +# CONFIG_PARTITION_TABLE_SINGLE_APP is not set +# CONFIG_PARTITION_TABLE_SINGLE_APP_LARGE is not set +# CONFIG_PARTITION_TABLE_TWO_OTA is not set +CONFIG_PARTITION_TABLE_CUSTOM=y +# CONFIG_PARTITION_TABLE_SINGLE_APP_ENCRYPTED_NVS is not set +# CONFIG_PARTITION_TABLE_SINGLE_APP_LARGE_ENC_NVS is not set +# CONFIG_PARTITION_TABLE_TWO_OTA_ENCRYPTED_NVS is not set +CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions.csv" +CONFIG_PARTITION_TABLE_FILENAME="partitions.csv" +CONFIG_PARTITION_TABLE_OFFSET=0x8000 +CONFIG_PARTITION_TABLE_MD5=y +# end of Partition Table + +# +# Compiler options +# +# CONFIG_COMPILER_OPTIMIZATION_DEBUG is not set +# CONFIG_COMPILER_OPTIMIZATION_SIZE is not set +CONFIG_COMPILER_OPTIMIZATION_PERF=y +# CONFIG_COMPILER_OPTIMIZATION_NONE is not set +CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_ENABLE=y +# CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT is not set +# CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_DISABLE is not set +CONFIG_COMPILER_FLOAT_LIB_FROM_GCCLIB=y +CONFIG_COMPILER_OPTIMIZATION_ASSERTION_LEVEL=2 +# CONFIG_COMPILER_OPTIMIZATION_CHECKS_SILENT is not set +CONFIG_COMPILER_HIDE_PATHS_MACROS=y +# CONFIG_COMPILER_CXX_EXCEPTIONS is not set +# CONFIG_COMPILER_CXX_RTTI is not set +# CONFIG_COMPILER_STACK_CHECK_MODE_NONE is not set +# CONFIG_COMPILER_STACK_CHECK_MODE_NORM is not set +# CONFIG_COMPILER_STACK_CHECK_MODE_STRONG is not set +CONFIG_COMPILER_STACK_CHECK_MODE_ALL=y +CONFIG_COMPILER_STACK_CHECK=y +# CONFIG_COMPILER_WARN_WRITE_STRINGS is not set +CONFIG_COMPILER_SAVE_RESTORE_LIBCALLS=y +# CONFIG_COMPILER_DISABLE_GCC12_WARNINGS is not set +# CONFIG_COMPILER_DISABLE_GCC13_WARNINGS is not set +# CONFIG_COMPILER_DUMP_RTL_FILES is not set +CONFIG_COMPILER_RT_LIB_GCCLIB=y +CONFIG_COMPILER_RT_LIB_NAME="gcc" +# end of Compiler options + +# +# Component config +# + +# +# Application Level Tracing +# +# CONFIG_APPTRACE_DEST_JTAG is not set +CONFIG_APPTRACE_DEST_NONE=y +# CONFIG_APPTRACE_DEST_UART1 is not set +# CONFIG_APPTRACE_DEST_USB_CDC is not set +CONFIG_APPTRACE_DEST_UART_NONE=y +CONFIG_APPTRACE_UART_TASK_PRIO=1 +CONFIG_APPTRACE_LOCK_ENABLE=y +# end of Application Level Tracing + +# +# Bluetooth +# +# CONFIG_BT_ENABLED is not set +# end of Bluetooth + +# +# Driver Configurations +# + +# +# Legacy ADC Configuration +# +# CONFIG_ADC_SUPPRESS_DEPRECATE_WARN is not set + +# +# Legacy ADC Calibration Configuration +# +# CONFIG_ADC_CALI_SUPPRESS_DEPRECATE_WARN is not set +# end of Legacy ADC Calibration Configuration +# end of Legacy ADC Configuration + +# +# SPI Configuration +# +# CONFIG_SPI_MASTER_IN_IRAM is not set +CONFIG_SPI_MASTER_ISR_IN_IRAM=y +# CONFIG_SPI_SLAVE_IN_IRAM is not set +CONFIG_SPI_SLAVE_ISR_IN_IRAM=y +# end of SPI Configuration + +# +# TWAI Configuration +# +# CONFIG_TWAI_ISR_IN_IRAM is not set +CONFIG_TWAI_ERRATA_FIX_LISTEN_ONLY_DOM=y +# end of TWAI Configuration + +# +# Temperature sensor Configuration +# +# CONFIG_TEMP_SENSOR_SUPPRESS_DEPRECATE_WARN is not set +# CONFIG_TEMP_SENSOR_ENABLE_DEBUG_LOG is not set +# end of Temperature sensor Configuration + +# +# UART Configuration +# +# CONFIG_UART_ISR_IN_IRAM is not set +# end of UART Configuration + +# +# GPIO Configuration +# +# CONFIG_GPIO_CTRL_FUNC_IN_IRAM is not set +# end of GPIO Configuration + +# +# Sigma Delta Modulator Configuration +# +# CONFIG_SDM_CTRL_FUNC_IN_IRAM is not set +# CONFIG_SDM_SUPPRESS_DEPRECATE_WARN is not set +# CONFIG_SDM_ENABLE_DEBUG_LOG is not set +# end of Sigma Delta Modulator Configuration + +# +# GPTimer Configuration +# +CONFIG_GPTIMER_ISR_HANDLER_IN_IRAM=y +# CONFIG_GPTIMER_CTRL_FUNC_IN_IRAM is not set +# CONFIG_GPTIMER_ISR_IRAM_SAFE is not set +# CONFIG_GPTIMER_SUPPRESS_DEPRECATE_WARN is not set +# CONFIG_GPTIMER_ENABLE_DEBUG_LOG is not set +# end of GPTimer Configuration + +# +# RMT Configuration +# +# CONFIG_RMT_ISR_IRAM_SAFE is not set +# CONFIG_RMT_RECV_FUNC_IN_IRAM is not set +# CONFIG_RMT_SUPPRESS_DEPRECATE_WARN is not set +# CONFIG_RMT_ENABLE_DEBUG_LOG is not set +# end of RMT Configuration + +# +# I2S Configuration +# +# CONFIG_I2S_ISR_IRAM_SAFE is not set +# CONFIG_I2S_SUPPRESS_DEPRECATE_WARN is not set +# CONFIG_I2S_ENABLE_DEBUG_LOG is not set +# end of I2S Configuration + +# +# USB Serial/JTAG Configuration +# +# CONFIG_USJ_NO_AUTO_LS_ON_CONNECTION is not set +# end of USB Serial/JTAG Configuration + +# +# LEDC Configuration +# +# CONFIG_LEDC_CTRL_FUNC_IN_IRAM is not set +# end of LEDC Configuration + +# +# I2C Configuration +# +# CONFIG_I2C_ISR_IRAM_SAFE is not set +# CONFIG_I2C_ENABLE_DEBUG_LOG is not set +# end of I2C Configuration +# end of Driver Configurations + +# +# eFuse Bit Manager +# +# CONFIG_EFUSE_CUSTOM_TABLE is not set +# CONFIG_EFUSE_VIRTUAL is not set +CONFIG_EFUSE_MAX_BLK_LEN=256 +# end of eFuse Bit Manager + +# +# ESP-TLS +# +CONFIG_ESP_TLS_USING_MBEDTLS=y +CONFIG_ESP_TLS_USE_DS_PERIPHERAL=y +# CONFIG_ESP_TLS_CLIENT_SESSION_TICKETS is not set +# CONFIG_ESP_TLS_SERVER is not set +# CONFIG_ESP_TLS_PSK_VERIFICATION is not set +# CONFIG_ESP_TLS_INSECURE is not set +# end of ESP-TLS + +# +# ADC and ADC Calibration +# +# CONFIG_ADC_ONESHOT_CTRL_FUNC_IN_IRAM is not set +# CONFIG_ADC_CONTINUOUS_ISR_IRAM_SAFE is not set +# CONFIG_ADC_CONTINUOUS_FORCE_USE_ADC2_ON_C3_S3 is not set +# CONFIG_ADC_ONESHOT_FORCE_USE_ADC2_ON_C3 is not set +# end of ADC and ADC Calibration + +# +# Wireless Coexistence +# +# CONFIG_ESP_COEX_EXTERNAL_COEXIST_ENABLE is not set +# end of Wireless Coexistence + +# +# Common ESP-related +# +CONFIG_ESP_ERR_TO_NAME_LOOKUP=y +# end of Common ESP-related + +# +# Ethernet +# +# CONFIG_ETH_USE_SPI_ETHERNET is not set +# CONFIG_ETH_USE_OPENETH is not set +# end of Ethernet + +# +# Event Loop Library +# +# CONFIG_ESP_EVENT_LOOP_PROFILING is not set +CONFIG_ESP_EVENT_POST_FROM_ISR=y +CONFIG_ESP_EVENT_POST_FROM_IRAM_ISR=y +# end of Event Loop Library + +# +# GDB Stub +# +# CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME is not set +# end of GDB Stub + +# +# ESP HTTP client +# +CONFIG_ESP_HTTP_CLIENT_ENABLE_HTTPS=y +# CONFIG_ESP_HTTP_CLIENT_ENABLE_BASIC_AUTH is not set +# CONFIG_ESP_HTTP_CLIENT_ENABLE_DIGEST_AUTH is not set +# end of ESP HTTP client + +# +# HTTP Server +# +CONFIG_HTTPD_MAX_REQ_HDR_LEN=512 +CONFIG_HTTPD_MAX_URI_LEN=512 +CONFIG_HTTPD_ERR_RESP_NO_DELAY=y +CONFIG_HTTPD_PURGE_BUF_LEN=32 +# CONFIG_HTTPD_LOG_PURGE_DATA is not set +# CONFIG_HTTPD_WS_SUPPORT is not set +# CONFIG_HTTPD_QUEUE_WORK_BLOCKING is not set +# end of HTTP Server + +# +# ESP HTTPS OTA +# +# CONFIG_ESP_HTTPS_OTA_DECRYPT_CB is not set +# CONFIG_ESP_HTTPS_OTA_ALLOW_HTTP is not set +# end of ESP HTTPS OTA + +# +# ESP HTTPS server +# +# CONFIG_ESP_HTTPS_SERVER_ENABLE is not set +# end of ESP HTTPS server + +# +# Hardware Settings +# + +# +# Chip revision +# +# CONFIG_ESP32C3_REV_MIN_0 is not set +# CONFIG_ESP32C3_REV_MIN_1 is not set +CONFIG_ESP32C3_REV_MIN_2=y +# CONFIG_ESP32C3_REV_MIN_3 is not set +# CONFIG_ESP32C3_REV_MIN_4 is not set +# CONFIG_ESP32C3_REV_MIN_101 is not set +CONFIG_ESP32C3_REV_MIN_FULL=2 +CONFIG_ESP_REV_MIN_FULL=2 + +# +# Maximum Supported ESP32-C3 Revision (Rev v1.99) +# +CONFIG_ESP32C3_REV_MAX_FULL=199 +CONFIG_ESP_REV_MAX_FULL=199 +# end of Chip revision + +# +# MAC Config +# +CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_STA=y +CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_AP=y +CONFIG_ESP_MAC_ADDR_UNIVERSE_BT=y +CONFIG_ESP_MAC_ADDR_UNIVERSE_ETH=y +CONFIG_ESP_MAC_UNIVERSAL_MAC_ADDRESSES_FOUR=y +# CONFIG_ESP32C3_UNIVERSAL_MAC_ADDRESSES_TWO is not set +CONFIG_ESP32C3_UNIVERSAL_MAC_ADDRESSES_FOUR=y +CONFIG_ESP32C3_UNIVERSAL_MAC_ADDRESSES=4 +# CONFIG_ESP_MAC_USE_CUSTOM_MAC_AS_BASE_MAC is not set +# end of MAC Config + +# +# Sleep Config +# +# CONFIG_ESP_SLEEP_POWER_DOWN_FLASH is not set +CONFIG_ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND=y +# CONFIG_ESP_SLEEP_MSPI_NEED_ALL_IO_PU is not set +CONFIG_ESP_SLEEP_GPIO_RESET_WORKAROUND=y +CONFIG_ESP_SLEEP_WAIT_FLASH_READY_EXTRA_DELAY=0 +# CONFIG_ESP_SLEEP_CACHE_SAFE_ASSERTION is not set +# CONFIG_ESP_SLEEP_DEBUG is not set +CONFIG_ESP_SLEEP_GPIO_ENABLE_INTERNAL_RESISTORS=y +# end of Sleep Config + +CONFIG_ESP_SLEEP_SYSTIMER_STALL_WORKAROUND=y + +# +# RTC Clock Config +# +CONFIG_RTC_CLK_SRC_INT_RC=y +# CONFIG_RTC_CLK_SRC_EXT_CRYS is not set +# CONFIG_RTC_CLK_SRC_EXT_OSC is not set +# CONFIG_RTC_CLK_SRC_INT_8MD256 is not set +CONFIG_RTC_CLK_CAL_CYCLES=1024 +# end of RTC Clock Config + +# +# Peripheral Control +# +CONFIG_PERIPH_CTRL_FUNC_IN_IRAM=y +# end of Peripheral Control + +# +# GDMA Configuration +# +# CONFIG_GDMA_CTRL_FUNC_IN_IRAM is not set +# CONFIG_GDMA_ISR_IRAM_SAFE is not set +# CONFIG_GDMA_ENABLE_DEBUG_LOG is not set +# end of GDMA Configuration + +# +# Main XTAL Config +# +CONFIG_XTAL_FREQ_40=y +CONFIG_XTAL_FREQ=40 +# end of Main XTAL Config +# end of Hardware Settings + +# +# LCD and Touch Panel +# + +# +# LCD Touch Drivers are maintained in the IDF Component Registry +# + +# +# LCD Peripheral Configuration +# +CONFIG_LCD_PANEL_IO_FORMAT_BUF_SIZE=32 +# CONFIG_LCD_ENABLE_DEBUG_LOG is not set +# end of LCD Peripheral Configuration +# end of LCD and Touch Panel + +# +# ESP NETIF Adapter +# +CONFIG_ESP_NETIF_IP_LOST_TIMER_INTERVAL=120 +CONFIG_ESP_NETIF_TCPIP_LWIP=y +# CONFIG_ESP_NETIF_LOOPBACK is not set +CONFIG_ESP_NETIF_USES_TCPIP_WITH_BSD_API=y +# CONFIG_ESP_NETIF_RECEIVE_REPORT_ERRORS is not set +# CONFIG_ESP_NETIF_L2_TAP is not set +# CONFIG_ESP_NETIF_BRIDGE_EN is not set +# end of ESP NETIF Adapter + +# +# Partition API Configuration +# +# end of Partition API Configuration + +# +# PHY +# +CONFIG_ESP_PHY_CALIBRATION_AND_DATA_STORAGE=y +# CONFIG_ESP_PHY_INIT_DATA_IN_PARTITION is not set +CONFIG_ESP_PHY_MAX_WIFI_TX_POWER=20 +CONFIG_ESP_PHY_MAX_TX_POWER=20 +# CONFIG_ESP_PHY_REDUCE_TX_POWER is not set +CONFIG_ESP_PHY_ENABLE_USB=y +# CONFIG_ESP_PHY_ENABLE_CERT_TEST is not set +CONFIG_ESP_PHY_RF_CAL_PARTIAL=y +# CONFIG_ESP_PHY_RF_CAL_NONE is not set +# CONFIG_ESP_PHY_RF_CAL_FULL is not set +CONFIG_ESP_PHY_CALIBRATION_MODE=0 +# end of PHY + +# +# Power Management +# +CONFIG_PM_ENABLE=y +# CONFIG_PM_DFS_INIT_AUTO is not set +# CONFIG_PM_PROFILING is not set +# CONFIG_PM_TRACE is not set +CONFIG_PM_LIGHTSLEEP_RTC_OSC_CAL_INTERVAL=1 +CONFIG_PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP=y +# end of Power Management + +# +# ESP PSRAM +# + +# +# ESP Ringbuf +# +# CONFIG_RINGBUF_PLACE_FUNCTIONS_INTO_FLASH is not set +# end of ESP Ringbuf + +# +# ESP System Settings +# +# CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_80 is not set +CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_160=y +CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ=160 +# CONFIG_ESP_SYSTEM_PANIC_PRINT_HALT is not set +CONFIG_ESP_SYSTEM_PANIC_PRINT_REBOOT=y +# CONFIG_ESP_SYSTEM_PANIC_SILENT_REBOOT is not set +# CONFIG_ESP_SYSTEM_PANIC_GDBSTUB is not set +CONFIG_ESP_SYSTEM_PANIC_REBOOT_DELAY_SECONDS=5 +CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE=y +CONFIG_ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK=y +CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP=y +# CONFIG_ESP_SYSTEM_USE_EH_FRAME is not set + +# +# Memory protection +# +CONFIG_ESP_SYSTEM_MEMPROT_FEATURE=y +CONFIG_ESP_SYSTEM_MEMPROT_FEATURE_LOCK=y +# end of Memory protection + +CONFIG_ESP_SYSTEM_EVENT_QUEUE_SIZE=32 +CONFIG_ESP_SYSTEM_EVENT_TASK_STACK_SIZE=2304 +CONFIG_ESP_MAIN_TASK_STACK_SIZE=3584 +CONFIG_ESP_MAIN_TASK_AFFINITY_CPU0=y +# CONFIG_ESP_MAIN_TASK_AFFINITY_NO_AFFINITY is not set +CONFIG_ESP_MAIN_TASK_AFFINITY=0x0 +CONFIG_ESP_MINIMAL_SHARED_STACK_SIZE=2048 +CONFIG_ESP_CONSOLE_UART_DEFAULT=y +# CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG is not set +# CONFIG_ESP_CONSOLE_UART_CUSTOM is not set +# CONFIG_ESP_CONSOLE_NONE is not set +# CONFIG_ESP_CONSOLE_SECONDARY_NONE is not set +CONFIG_ESP_CONSOLE_SECONDARY_USB_SERIAL_JTAG=y +CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG_ENABLED=y +CONFIG_ESP_CONSOLE_UART=y +CONFIG_ESP_CONSOLE_UART_NUM=0 +CONFIG_ESP_CONSOLE_UART_BAUDRATE=115200 +CONFIG_ESP_INT_WDT=y +CONFIG_ESP_INT_WDT_TIMEOUT_MS=300 +CONFIG_ESP_TASK_WDT_EN=y +CONFIG_ESP_TASK_WDT_INIT=y +# CONFIG_ESP_TASK_WDT_PANIC is not set +CONFIG_ESP_TASK_WDT_TIMEOUT_S=5 +CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0=y +# CONFIG_ESP_PANIC_HANDLER_IRAM is not set +# CONFIG_ESP_DEBUG_STUBS_ENABLE is not set +CONFIG_ESP_DEBUG_OCDAWARE=y +CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_4=y + +# +# Brownout Detector +# +CONFIG_ESP_BROWNOUT_DET=y +CONFIG_ESP_BROWNOUT_DET_LVL_SEL_7=y +# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_6 is not set +# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_5 is not set +# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_4 is not set +# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_3 is not set +# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_2 is not set +CONFIG_ESP_BROWNOUT_DET_LVL=7 +# end of Brownout Detector + +CONFIG_ESP_SYSTEM_BROWNOUT_INTR=y +CONFIG_ESP_SYSTEM_HW_STACK_GUARD=y +# end of ESP System Settings + +# +# IPC (Inter-Processor Call) +# +CONFIG_ESP_IPC_TASK_STACK_SIZE=1024 +# end of IPC (Inter-Processor Call) + +# +# High resolution timer (esp_timer) +# +# CONFIG_ESP_TIMER_PROFILING is not set +CONFIG_ESP_TIME_FUNCS_USE_RTC_TIMER=y +CONFIG_ESP_TIME_FUNCS_USE_ESP_TIMER=y +CONFIG_ESP_TIMER_TASK_STACK_SIZE=3584 +CONFIG_ESP_TIMER_INTERRUPT_LEVEL=1 +# CONFIG_ESP_TIMER_SHOW_EXPERIMENTAL is not set +CONFIG_ESP_TIMER_TASK_AFFINITY=0x0 +CONFIG_ESP_TIMER_TASK_AFFINITY_CPU0=y +CONFIG_ESP_TIMER_ISR_AFFINITY=0x1 +CONFIG_ESP_TIMER_ISR_AFFINITY_CPU0=y +# CONFIG_ESP_TIMER_SUPPORTS_ISR_DISPATCH_METHOD is not set +CONFIG_ESP_TIMER_IMPL_SYSTIMER=y +# end of High resolution timer (esp_timer) + +# +# Wi-Fi +# +CONFIG_ESP_WIFI_ENABLED=y +CONFIG_ESP_WIFI_STATIC_RX_BUFFER_NUM=10 +CONFIG_ESP_WIFI_DYNAMIC_RX_BUFFER_NUM=32 +# CONFIG_ESP_WIFI_STATIC_TX_BUFFER is not set +CONFIG_ESP_WIFI_DYNAMIC_TX_BUFFER=y +CONFIG_ESP_WIFI_TX_BUFFER_TYPE=1 +CONFIG_ESP_WIFI_DYNAMIC_TX_BUFFER_NUM=32 +CONFIG_ESP_WIFI_STATIC_RX_MGMT_BUFFER=y +# CONFIG_ESP_WIFI_DYNAMIC_RX_MGMT_BUFFER is not set +CONFIG_ESP_WIFI_DYNAMIC_RX_MGMT_BUF=0 +CONFIG_ESP_WIFI_RX_MGMT_BUF_NUM_DEF=5 +# CONFIG_ESP_WIFI_CSI_ENABLED is not set +CONFIG_ESP_WIFI_AMPDU_TX_ENABLED=y +CONFIG_ESP_WIFI_TX_BA_WIN=6 +CONFIG_ESP_WIFI_AMPDU_RX_ENABLED=y +CONFIG_ESP_WIFI_RX_BA_WIN=6 +CONFIG_ESP_WIFI_NVS_ENABLED=y +CONFIG_ESP_WIFI_SOFTAP_BEACON_MAX_LEN=752 +CONFIG_ESP_WIFI_MGMT_SBUF_NUM=32 +CONFIG_ESP_WIFI_IRAM_OPT=y +# CONFIG_ESP_WIFI_EXTRA_IRAM_OPT is not set +CONFIG_ESP_WIFI_RX_IRAM_OPT=y +CONFIG_ESP_WIFI_ENABLE_WPA3_SAE=y +CONFIG_ESP_WIFI_ENABLE_SAE_PK=y +CONFIG_ESP_WIFI_SOFTAP_SAE_SUPPORT=y +CONFIG_ESP_WIFI_ENABLE_WPA3_OWE_STA=y +# CONFIG_ESP_WIFI_SLP_IRAM_OPT is not set +# CONFIG_ESP_WIFI_FTM_ENABLE is not set +CONFIG_ESP_WIFI_STA_DISCONNECTED_PM_ENABLE=y +# CONFIG_ESP_WIFI_GCMP_SUPPORT is not set +# CONFIG_ESP_WIFI_GMAC_SUPPORT is not set +CONFIG_ESP_WIFI_SOFTAP_SUPPORT=y +# CONFIG_ESP_WIFI_SLP_BEACON_LOST_OPT is not set +CONFIG_ESP_WIFI_ESPNOW_MAX_ENCRYPT_NUM=7 +CONFIG_ESP_WIFI_MBEDTLS_CRYPTO=y +CONFIG_ESP_WIFI_MBEDTLS_TLS_CLIENT=y +# CONFIG_ESP_WIFI_WAPI_PSK is not set +# CONFIG_ESP_WIFI_SUITE_B_192 is not set +# CONFIG_ESP_WIFI_11KV_SUPPORT is not set +# CONFIG_ESP_WIFI_MBO_SUPPORT is not set +# CONFIG_ESP_WIFI_DPP_SUPPORT is not set +# CONFIG_ESP_WIFI_11R_SUPPORT is not set +# CONFIG_ESP_WIFI_WPS_SOFTAP_REGISTRAR is not set + +# +# WPS Configuration Options +# +# CONFIG_ESP_WIFI_WPS_STRICT is not set +# CONFIG_ESP_WIFI_WPS_PASSPHRASE is not set +# end of WPS Configuration Options + +# CONFIG_ESP_WIFI_DEBUG_PRINT is not set +# CONFIG_ESP_WIFI_TESTING_OPTIONS is not set +CONFIG_ESP_WIFI_ENTERPRISE_SUPPORT=y +# CONFIG_ESP_WIFI_ENT_FREE_DYNAMIC_BUFFER is not set +# end of Wi-Fi + +# +# Core dump +# +# CONFIG_ESP_COREDUMP_ENABLE_TO_FLASH is not set +# CONFIG_ESP_COREDUMP_ENABLE_TO_UART is not set +CONFIG_ESP_COREDUMP_ENABLE_TO_NONE=y +# end of Core dump + +# +# FAT Filesystem support +# +CONFIG_FATFS_VOLUME_COUNT=2 +CONFIG_FATFS_LFN_NONE=y +# CONFIG_FATFS_LFN_HEAP is not set +# CONFIG_FATFS_LFN_STACK is not set +# CONFIG_FATFS_SECTOR_512 is not set +CONFIG_FATFS_SECTOR_4096=y +# CONFIG_FATFS_CODEPAGE_DYNAMIC is not set +CONFIG_FATFS_CODEPAGE_437=y +# CONFIG_FATFS_CODEPAGE_720 is not set +# CONFIG_FATFS_CODEPAGE_737 is not set +# CONFIG_FATFS_CODEPAGE_771 is not set +# CONFIG_FATFS_CODEPAGE_775 is not set +# CONFIG_FATFS_CODEPAGE_850 is not set +# CONFIG_FATFS_CODEPAGE_852 is not set +# CONFIG_FATFS_CODEPAGE_855 is not set +# CONFIG_FATFS_CODEPAGE_857 is not set +# CONFIG_FATFS_CODEPAGE_860 is not set +# CONFIG_FATFS_CODEPAGE_861 is not set +# CONFIG_FATFS_CODEPAGE_862 is not set +# CONFIG_FATFS_CODEPAGE_863 is not set +# CONFIG_FATFS_CODEPAGE_864 is not set +# CONFIG_FATFS_CODEPAGE_865 is not set +# CONFIG_FATFS_CODEPAGE_866 is not set +# CONFIG_FATFS_CODEPAGE_869 is not set +# CONFIG_FATFS_CODEPAGE_932 is not set +# CONFIG_FATFS_CODEPAGE_936 is not set +# CONFIG_FATFS_CODEPAGE_949 is not set +# CONFIG_FATFS_CODEPAGE_950 is not set +CONFIG_FATFS_CODEPAGE=437 +CONFIG_FATFS_FS_LOCK=0 +CONFIG_FATFS_TIMEOUT_MS=10000 +CONFIG_FATFS_PER_FILE_CACHE=y +# CONFIG_FATFS_USE_FASTSEEK is not set +CONFIG_FATFS_VFS_FSTAT_BLKSIZE=0 +# CONFIG_FATFS_IMMEDIATE_FSYNC is not set +# end of FAT Filesystem support + +# +# FreeRTOS +# + +# +# Kernel +# +# CONFIG_FREERTOS_SMP is not set +CONFIG_FREERTOS_UNICORE=y +CONFIG_FREERTOS_HZ=100 +CONFIG_FREERTOS_OPTIMIZED_SCHEDULER=y +# CONFIG_FREERTOS_CHECK_STACKOVERFLOW_NONE is not set +# CONFIG_FREERTOS_CHECK_STACKOVERFLOW_PTRVAL is not set +CONFIG_FREERTOS_CHECK_STACKOVERFLOW_CANARY=y +CONFIG_FREERTOS_THREAD_LOCAL_STORAGE_POINTERS=1 +CONFIG_FREERTOS_IDLE_TASK_STACKSIZE=1536 +# CONFIG_FREERTOS_USE_IDLE_HOOK is not set +# CONFIG_FREERTOS_USE_TICK_HOOK is not set +CONFIG_FREERTOS_MAX_TASK_NAME_LEN=16 +# CONFIG_FREERTOS_ENABLE_BACKWARD_COMPATIBILITY is not set +CONFIG_FREERTOS_TIMER_SERVICE_TASK_NAME="Tmr Svc" +CONFIG_FREERTOS_TIMER_TASK_PRIORITY=1 +CONFIG_FREERTOS_TIMER_TASK_STACK_DEPTH=2048 +CONFIG_FREERTOS_TIMER_QUEUE_LENGTH=10 +CONFIG_FREERTOS_QUEUE_REGISTRY_SIZE=0 +CONFIG_FREERTOS_TASK_NOTIFICATION_ARRAY_ENTRIES=1 +# CONFIG_FREERTOS_USE_TRACE_FACILITY is not set +# CONFIG_FREERTOS_GENERATE_RUN_TIME_STATS is not set +# CONFIG_FREERTOS_USE_TICKLESS_IDLE is not set +# end of Kernel + +# +# Port +# +# CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK is not set +CONFIG_FREERTOS_TLSP_DELETION_CALLBACKS=y +# CONFIG_FREERTOS_TASK_PRE_DELETION_HOOK is not set +# CONFIG_FREERTOS_ENABLE_STATIC_TASK_CLEAN_UP is not set +CONFIG_FREERTOS_CHECK_MUTEX_GIVEN_BY_OWNER=y +CONFIG_FREERTOS_ISR_STACKSIZE=1536 +CONFIG_FREERTOS_INTERRUPT_BACKTRACE=y +CONFIG_FREERTOS_TICK_SUPPORT_SYSTIMER=y +CONFIG_FREERTOS_CORETIMER_SYSTIMER_LVL1=y +# CONFIG_FREERTOS_CORETIMER_SYSTIMER_LVL3 is not set +CONFIG_FREERTOS_SYSTICK_USES_SYSTIMER=y +# CONFIG_FREERTOS_PLACE_FUNCTIONS_INTO_FLASH is not set +# CONFIG_FREERTOS_CHECK_PORT_CRITICAL_COMPLIANCE is not set +# end of Port + +CONFIG_FREERTOS_PORT=y +CONFIG_FREERTOS_NO_AFFINITY=0x7FFFFFFF +CONFIG_FREERTOS_SUPPORT_STATIC_ALLOCATION=y +CONFIG_FREERTOS_DEBUG_OCDAWARE=y +CONFIG_FREERTOS_ENABLE_TASK_SNAPSHOT=y +CONFIG_FREERTOS_PLACE_SNAPSHOT_FUNS_INTO_FLASH=y +# end of FreeRTOS + +# +# Hardware Abstraction Layer (HAL) and Low Level (LL) +# +CONFIG_HAL_ASSERTION_EQUALS_SYSTEM=y +# CONFIG_HAL_ASSERTION_DISABLE is not set +# CONFIG_HAL_ASSERTION_SILENT is not set +# CONFIG_HAL_ASSERTION_ENABLE is not set +CONFIG_HAL_DEFAULT_ASSERTION_LEVEL=2 +CONFIG_HAL_SPI_MASTER_FUNC_IN_IRAM=y +CONFIG_HAL_SPI_SLAVE_FUNC_IN_IRAM=y +# end of Hardware Abstraction Layer (HAL) and Low Level (LL) + +# +# Heap memory debugging +# +# CONFIG_HEAP_POISONING_DISABLED is not set +# CONFIG_HEAP_POISONING_LIGHT is not set +CONFIG_HEAP_POISONING_COMPREHENSIVE=y +CONFIG_HEAP_TRACING_OFF=y +# CONFIG_HEAP_TRACING_STANDALONE is not set +# CONFIG_HEAP_TRACING_TOHOST is not set +# CONFIG_HEAP_USE_HOOKS is not set +# CONFIG_HEAP_TASK_TRACKING is not set +CONFIG_HEAP_ABORT_WHEN_ALLOCATION_FAILS=y +# CONFIG_HEAP_PLACE_FUNCTION_INTO_FLASH is not set +# end of Heap memory debugging + +# +# Log output +# +# CONFIG_LOG_DEFAULT_LEVEL_NONE is not set +# CONFIG_LOG_DEFAULT_LEVEL_ERROR is not set +# CONFIG_LOG_DEFAULT_LEVEL_WARN is not set +CONFIG_LOG_DEFAULT_LEVEL_INFO=y +# CONFIG_LOG_DEFAULT_LEVEL_DEBUG is not set +# CONFIG_LOG_DEFAULT_LEVEL_VERBOSE is not set +CONFIG_LOG_DEFAULT_LEVEL=3 +CONFIG_LOG_MAXIMUM_EQUALS_DEFAULT=y +# CONFIG_LOG_MAXIMUM_LEVEL_DEBUG is not set +# CONFIG_LOG_MAXIMUM_LEVEL_VERBOSE is not set +CONFIG_LOG_MAXIMUM_LEVEL=3 +# CONFIG_LOG_MASTER_LEVEL is not set +CONFIG_LOG_COLORS=y +# CONFIG_LOG_TIMESTAMP_SOURCE_RTOS is not set +CONFIG_LOG_TIMESTAMP_SOURCE_SYSTEM=y +# end of Log output + +# +# LWIP +# +CONFIG_LWIP_ENABLE=y +CONFIG_LWIP_LOCAL_HOSTNAME="espressif" +# CONFIG_LWIP_NETIF_API is not set +CONFIG_LWIP_TCPIP_TASK_PRIO=18 +# CONFIG_LWIP_TCPIP_CORE_LOCKING is not set +# CONFIG_LWIP_CHECK_THREAD_SAFETY is not set +CONFIG_LWIP_DNS_SUPPORT_MDNS_QUERIES=y +# CONFIG_LWIP_L2_TO_L3_COPY is not set +# CONFIG_LWIP_IRAM_OPTIMIZATION is not set +# CONFIG_LWIP_EXTRA_IRAM_OPTIMIZATION is not set +CONFIG_LWIP_TIMERS_ONDEMAND=y +CONFIG_LWIP_ND6=y +# CONFIG_LWIP_FORCE_ROUTER_FORWARDING is not set +CONFIG_LWIP_MAX_SOCKETS=10 +# CONFIG_LWIP_USE_ONLY_LWIP_SELECT is not set +# CONFIG_LWIP_SO_LINGER is not set +CONFIG_LWIP_SO_REUSE=y +CONFIG_LWIP_SO_REUSE_RXTOALL=y +# CONFIG_LWIP_SO_RCVBUF is not set +# CONFIG_LWIP_NETBUF_RECVINFO is not set +CONFIG_LWIP_IP_DEFAULT_TTL=64 +CONFIG_LWIP_IP4_FRAG=y +CONFIG_LWIP_IP6_FRAG=y +# CONFIG_LWIP_IP4_REASSEMBLY is not set +# CONFIG_LWIP_IP6_REASSEMBLY is not set +CONFIG_LWIP_IP_REASS_MAX_PBUFS=10 +# CONFIG_LWIP_IP_FORWARD is not set +# CONFIG_LWIP_STATS is not set +CONFIG_LWIP_ESP_GRATUITOUS_ARP=y +CONFIG_LWIP_GARP_TMR_INTERVAL=60 +CONFIG_LWIP_ESP_MLDV6_REPORT=y +CONFIG_LWIP_MLDV6_TMR_INTERVAL=40 +CONFIG_LWIP_TCPIP_RECVMBOX_SIZE=32 +CONFIG_LWIP_DHCP_DOES_ARP_CHECK=y +# CONFIG_LWIP_DHCP_DISABLE_CLIENT_ID is not set +CONFIG_LWIP_DHCP_DISABLE_VENDOR_CLASS_ID=y +# CONFIG_LWIP_DHCP_RESTORE_LAST_IP is not set +CONFIG_LWIP_DHCP_OPTIONS_LEN=68 +CONFIG_LWIP_NUM_NETIF_CLIENT_DATA=0 +CONFIG_LWIP_DHCP_COARSE_TIMER_SECS=1 + +# +# DHCP server +# +CONFIG_LWIP_DHCPS=y +CONFIG_LWIP_DHCPS_LEASE_UNIT=60 +CONFIG_LWIP_DHCPS_MAX_STATION_NUM=8 +CONFIG_LWIP_DHCPS_STATIC_ENTRIES=y +# end of DHCP server + +# CONFIG_LWIP_AUTOIP is not set +CONFIG_LWIP_IPV4=y +CONFIG_LWIP_IPV6=y +# CONFIG_LWIP_IPV6_AUTOCONFIG is not set +CONFIG_LWIP_IPV6_NUM_ADDRESSES=3 +# CONFIG_LWIP_IPV6_FORWARD is not set +# CONFIG_LWIP_NETIF_STATUS_CALLBACK is not set +CONFIG_LWIP_NETIF_LOOPBACK=y +CONFIG_LWIP_LOOPBACK_MAX_PBUFS=8 + +# +# TCP +# +CONFIG_LWIP_MAX_ACTIVE_TCP=16 +CONFIG_LWIP_MAX_LISTENING_TCP=16 +CONFIG_LWIP_TCP_HIGH_SPEED_RETRANSMISSION=y +CONFIG_LWIP_TCP_MAXRTX=12 +CONFIG_LWIP_TCP_SYNMAXRTX=12 +CONFIG_LWIP_TCP_MSS=1440 +CONFIG_LWIP_TCP_TMR_INTERVAL=250 +CONFIG_LWIP_TCP_MSL=60000 +CONFIG_LWIP_TCP_FIN_WAIT_TIMEOUT=20000 +CONFIG_LWIP_TCP_SND_BUF_DEFAULT=5760 +CONFIG_LWIP_TCP_WND_DEFAULT=5760 +CONFIG_LWIP_TCP_RECVMBOX_SIZE=6 +CONFIG_LWIP_TCP_QUEUE_OOSEQ=y +CONFIG_LWIP_TCP_OOSEQ_TIMEOUT=6 +CONFIG_LWIP_TCP_OOSEQ_MAX_PBUFS=4 +# CONFIG_LWIP_TCP_SACK_OUT is not set +CONFIG_LWIP_TCP_OVERSIZE_MSS=y +# CONFIG_LWIP_TCP_OVERSIZE_QUARTER_MSS is not set +# CONFIG_LWIP_TCP_OVERSIZE_DISABLE is not set +CONFIG_LWIP_TCP_RTO_TIME=1500 +# end of TCP + +# +# UDP +# +CONFIG_LWIP_MAX_UDP_PCBS=16 +CONFIG_LWIP_UDP_RECVMBOX_SIZE=6 +# end of UDP + +# +# Checksums +# +# CONFIG_LWIP_CHECKSUM_CHECK_IP is not set +# CONFIG_LWIP_CHECKSUM_CHECK_UDP is not set +CONFIG_LWIP_CHECKSUM_CHECK_ICMP=y +# end of Checksums + +CONFIG_LWIP_TCPIP_TASK_STACK_SIZE=3072 +CONFIG_LWIP_TCPIP_TASK_AFFINITY_NO_AFFINITY=y +# CONFIG_LWIP_TCPIP_TASK_AFFINITY_CPU0 is not set +CONFIG_LWIP_TCPIP_TASK_AFFINITY=0x7FFFFFFF +# CONFIG_LWIP_PPP_SUPPORT is not set +CONFIG_LWIP_IPV6_MEMP_NUM_ND6_QUEUE=3 +CONFIG_LWIP_IPV6_ND6_NUM_NEIGHBORS=5 +# CONFIG_LWIP_SLIP_SUPPORT is not set + +# +# ICMP +# +CONFIG_LWIP_ICMP=y +# CONFIG_LWIP_MULTICAST_PING is not set +# CONFIG_LWIP_BROADCAST_PING is not set +# end of ICMP + +# +# LWIP RAW API +# +CONFIG_LWIP_MAX_RAW_PCBS=16 +# end of LWIP RAW API + +# +# SNTP +# +CONFIG_LWIP_SNTP_MAX_SERVERS=1 +# CONFIG_LWIP_DHCP_GET_NTP_SRV is not set +CONFIG_LWIP_SNTP_UPDATE_DELAY=3600000 +# end of SNTP + +# +# DNS +# +CONFIG_LWIP_DNS_MAX_SERVERS=3 +# CONFIG_LWIP_FALLBACK_DNS_SERVER_SUPPORT is not set +# end of DNS + +CONFIG_LWIP_BRIDGEIF_MAX_PORTS=7 +CONFIG_LWIP_ESP_LWIP_ASSERT=y + +# +# Hooks +# +# CONFIG_LWIP_HOOK_TCP_ISN_NONE is not set +CONFIG_LWIP_HOOK_TCP_ISN_DEFAULT=y +# CONFIG_LWIP_HOOK_TCP_ISN_CUSTOM is not set +CONFIG_LWIP_HOOK_IP6_ROUTE_NONE=y +# CONFIG_LWIP_HOOK_IP6_ROUTE_DEFAULT is not set +# CONFIG_LWIP_HOOK_IP6_ROUTE_CUSTOM is not set +CONFIG_LWIP_HOOK_ND6_GET_GW_NONE=y +# CONFIG_LWIP_HOOK_ND6_GET_GW_DEFAULT is not set +# CONFIG_LWIP_HOOK_ND6_GET_GW_CUSTOM is not set +CONFIG_LWIP_HOOK_IP6_SELECT_SRC_ADDR_NONE=y +# CONFIG_LWIP_HOOK_IP6_SELECT_SRC_ADDR_DEFAULT is not set +# CONFIG_LWIP_HOOK_IP6_SELECT_SRC_ADDR_CUSTOM is not set +CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_NONE=y +# CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_DEFAULT is not set +# CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_CUSTOM is not set +CONFIG_LWIP_HOOK_IP6_INPUT_NONE=y +# CONFIG_LWIP_HOOK_IP6_INPUT_DEFAULT is not set +# CONFIG_LWIP_HOOK_IP6_INPUT_CUSTOM is not set +# end of Hooks + +# CONFIG_LWIP_DEBUG is not set +# end of LWIP + +# +# mbedTLS +# +CONFIG_MBEDTLS_INTERNAL_MEM_ALLOC=y +# CONFIG_MBEDTLS_DEFAULT_MEM_ALLOC is not set +# CONFIG_MBEDTLS_CUSTOM_MEM_ALLOC is not set +CONFIG_MBEDTLS_ASYMMETRIC_CONTENT_LEN=y +CONFIG_MBEDTLS_SSL_IN_CONTENT_LEN=16384 +CONFIG_MBEDTLS_SSL_OUT_CONTENT_LEN=4096 +# CONFIG_MBEDTLS_DYNAMIC_BUFFER is not set +# CONFIG_MBEDTLS_DEBUG is not set + +# +# mbedTLS v3.x related +# +# CONFIG_MBEDTLS_SSL_PROTO_TLS1_3 is not set +# CONFIG_MBEDTLS_SSL_VARIABLE_BUFFER_LENGTH is not set +# CONFIG_MBEDTLS_X509_TRUSTED_CERT_CALLBACK is not set +# CONFIG_MBEDTLS_SSL_CONTEXT_SERIALIZATION is not set +CONFIG_MBEDTLS_SSL_KEEP_PEER_CERTIFICATE=y +CONFIG_MBEDTLS_PKCS7_C=y +# end of mbedTLS v3.x related + +# +# Certificate Bundle +# +CONFIG_MBEDTLS_CERTIFICATE_BUNDLE=y +CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_DEFAULT_FULL=y +# CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_DEFAULT_CMN is not set +# CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_DEFAULT_NONE is not set +# CONFIG_MBEDTLS_CUSTOM_CERTIFICATE_BUNDLE is not set +CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_MAX_CERTS=200 +# end of Certificate Bundle + +# CONFIG_MBEDTLS_ECP_RESTARTABLE is not set +CONFIG_MBEDTLS_CMAC_C=y +CONFIG_MBEDTLS_HARDWARE_AES=y +CONFIG_MBEDTLS_AES_USE_INTERRUPT=y +CONFIG_MBEDTLS_AES_INTERRUPT_LEVEL=0 +CONFIG_MBEDTLS_HARDWARE_MPI=y +CONFIG_MBEDTLS_MPI_USE_INTERRUPT=y +CONFIG_MBEDTLS_MPI_INTERRUPT_LEVEL=0 +CONFIG_MBEDTLS_HARDWARE_SHA=y +CONFIG_MBEDTLS_ROM_MD5=y +# CONFIG_MBEDTLS_ATCA_HW_ECDSA_SIGN is not set +# CONFIG_MBEDTLS_ATCA_HW_ECDSA_VERIFY is not set +CONFIG_MBEDTLS_HAVE_TIME=y +# CONFIG_MBEDTLS_PLATFORM_TIME_ALT is not set +# CONFIG_MBEDTLS_HAVE_TIME_DATE is not set +CONFIG_MBEDTLS_ECDSA_DETERMINISTIC=y +CONFIG_MBEDTLS_SHA512_C=y +CONFIG_MBEDTLS_TLS_SERVER_AND_CLIENT=y +# CONFIG_MBEDTLS_TLS_SERVER_ONLY is not set +# CONFIG_MBEDTLS_TLS_CLIENT_ONLY is not set +# CONFIG_MBEDTLS_TLS_DISABLED is not set +CONFIG_MBEDTLS_TLS_SERVER=y +CONFIG_MBEDTLS_TLS_CLIENT=y +CONFIG_MBEDTLS_TLS_ENABLED=y + +# +# TLS Key Exchange Methods +# +# CONFIG_MBEDTLS_PSK_MODES is not set +CONFIG_MBEDTLS_KEY_EXCHANGE_RSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ELLIPTIC_CURVE=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_RSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_RSA=y +# end of TLS Key Exchange Methods + +CONFIG_MBEDTLS_SSL_RENEGOTIATION=y +CONFIG_MBEDTLS_SSL_PROTO_TLS1_2=y +# CONFIG_MBEDTLS_SSL_PROTO_GMTSSL1_1 is not set +# CONFIG_MBEDTLS_SSL_PROTO_DTLS is not set +CONFIG_MBEDTLS_SSL_ALPN=y +CONFIG_MBEDTLS_CLIENT_SSL_SESSION_TICKETS=y +CONFIG_MBEDTLS_SERVER_SSL_SESSION_TICKETS=y + +# +# Symmetric Ciphers +# +CONFIG_MBEDTLS_AES_C=y +# CONFIG_MBEDTLS_CAMELLIA_C is not set +# CONFIG_MBEDTLS_DES_C is not set +# CONFIG_MBEDTLS_BLOWFISH_C is not set +# CONFIG_MBEDTLS_XTEA_C is not set +CONFIG_MBEDTLS_CCM_C=y +CONFIG_MBEDTLS_GCM_C=y +# CONFIG_MBEDTLS_NIST_KW_C is not set +# end of Symmetric Ciphers + +# CONFIG_MBEDTLS_RIPEMD160_C is not set + +# +# Certificates +# +CONFIG_MBEDTLS_PEM_PARSE_C=y +CONFIG_MBEDTLS_PEM_WRITE_C=y +CONFIG_MBEDTLS_X509_CRL_PARSE_C=y +CONFIG_MBEDTLS_X509_CSR_PARSE_C=y +# end of Certificates + +CONFIG_MBEDTLS_ECP_C=y +# CONFIG_MBEDTLS_DHM_C is not set +CONFIG_MBEDTLS_ECDH_C=y +CONFIG_MBEDTLS_ECDSA_C=y +# CONFIG_MBEDTLS_ECJPAKE_C is not set +CONFIG_MBEDTLS_ECP_DP_SECP192R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP224R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP256R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP384R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP521R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP192K1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP224K1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP256K1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_BP256R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_BP384R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_BP512R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_CURVE25519_ENABLED=y +CONFIG_MBEDTLS_ECP_NIST_OPTIM=y +CONFIG_MBEDTLS_ECP_FIXED_POINT_OPTIM=y +# CONFIG_MBEDTLS_POLY1305_C is not set +# CONFIG_MBEDTLS_CHACHA20_C is not set +# CONFIG_MBEDTLS_HKDF_C is not set +# CONFIG_MBEDTLS_THREADING_C is not set +CONFIG_MBEDTLS_LARGE_KEY_SOFTWARE_MPI=y +# end of mbedTLS + +# +# ESP-MQTT Configurations +# +CONFIG_MQTT_PROTOCOL_311=y +# CONFIG_MQTT_PROTOCOL_5 is not set +CONFIG_MQTT_TRANSPORT_SSL=y +CONFIG_MQTT_TRANSPORT_WEBSOCKET=y +CONFIG_MQTT_TRANSPORT_WEBSOCKET_SECURE=y +# CONFIG_MQTT_MSG_ID_INCREMENTAL is not set +# CONFIG_MQTT_SKIP_PUBLISH_IF_DISCONNECTED is not set +# CONFIG_MQTT_REPORT_DELETED_MESSAGES is not set +# CONFIG_MQTT_USE_CUSTOM_CONFIG is not set +# CONFIG_MQTT_TASK_CORE_SELECTION_ENABLED is not set +# CONFIG_MQTT_CUSTOM_OUTBOX is not set +# end of ESP-MQTT Configurations + +# +# Newlib +# +CONFIG_NEWLIB_STDOUT_LINE_ENDING_CRLF=y +# CONFIG_NEWLIB_STDOUT_LINE_ENDING_LF is not set +# CONFIG_NEWLIB_STDOUT_LINE_ENDING_CR is not set +# CONFIG_NEWLIB_STDIN_LINE_ENDING_CRLF is not set +# CONFIG_NEWLIB_STDIN_LINE_ENDING_LF is not set +CONFIG_NEWLIB_STDIN_LINE_ENDING_CR=y +# CONFIG_NEWLIB_NANO_FORMAT is not set +CONFIG_NEWLIB_TIME_SYSCALL_USE_RTC_HRT=y +# CONFIG_NEWLIB_TIME_SYSCALL_USE_RTC is not set +# CONFIG_NEWLIB_TIME_SYSCALL_USE_HRT is not set +# CONFIG_NEWLIB_TIME_SYSCALL_USE_NONE is not set +# end of Newlib + +# +# NVS +# +CONFIG_NVS_ENCRYPTION=y +# CONFIG_NVS_COMPATIBLE_PRE_V4_3_ENCRYPTION_FLAG is not set +# CONFIG_NVS_ASSERT_ERROR_CHECK is not set +# CONFIG_NVS_LEGACY_DUP_KEYS_COMPATIBILITY is not set +# end of NVS + +# +# NVS Security Provider +# +CONFIG_NVS_SEC_KEY_PROTECT_USING_FLASH_ENC=y +# CONFIG_NVS_SEC_KEY_PROTECT_USING_HMAC is not set +# end of NVS Security Provider + +# +# OpenThread +# +# CONFIG_OPENTHREAD_ENABLED is not set + +# +# Thread Operational Dataset +# +CONFIG_OPENTHREAD_NETWORK_NAME="OpenThread-ESP" +CONFIG_OPENTHREAD_MESH_LOCAL_PREFIX="fd00:db8:a0:0::/64" +CONFIG_OPENTHREAD_NETWORK_CHANNEL=15 +CONFIG_OPENTHREAD_NETWORK_PANID=0x1234 +CONFIG_OPENTHREAD_NETWORK_EXTPANID="dead00beef00cafe" +CONFIG_OPENTHREAD_NETWORK_MASTERKEY="00112233445566778899aabbccddeeff" +CONFIG_OPENTHREAD_NETWORK_PSKC="104810e2315100afd6bc9215a6bfac53" +# end of Thread Operational Dataset + +CONFIG_OPENTHREAD_XTAL_ACCURACY=130 +# CONFIG_OPENTHREAD_SPINEL_ONLY is not set +CONFIG_OPENTHREAD_RX_ON_WHEN_IDLE=y + +# +# Thread Address Query Config +# +# end of Thread Address Query Config +# end of OpenThread + +# +# Protocomm +# +CONFIG_ESP_PROTOCOMM_SUPPORT_SECURITY_VERSION_0=y +CONFIG_ESP_PROTOCOMM_SUPPORT_SECURITY_VERSION_1=y +CONFIG_ESP_PROTOCOMM_SUPPORT_SECURITY_VERSION_2=y +# end of Protocomm + +# +# PThreads +# +CONFIG_PTHREAD_TASK_PRIO_DEFAULT=5 +CONFIG_PTHREAD_TASK_STACK_SIZE_DEFAULT=3072 +CONFIG_PTHREAD_STACK_MIN=768 +CONFIG_PTHREAD_TASK_CORE_DEFAULT=-1 +CONFIG_PTHREAD_TASK_NAME_DEFAULT="pthread" +# end of PThreads + +# +# MMU Config +# +CONFIG_MMU_PAGE_SIZE_64KB=y +CONFIG_MMU_PAGE_MODE="64KB" +CONFIG_MMU_PAGE_SIZE=0x10000 +# end of MMU Config + +# +# Main Flash configuration +# + +# +# SPI Flash behavior when brownout +# +CONFIG_SPI_FLASH_BROWNOUT_RESET_XMC=y +CONFIG_SPI_FLASH_BROWNOUT_RESET=y +# end of SPI Flash behavior when brownout + +# +# Optional and Experimental Features (READ DOCS FIRST) +# + +# +# Features here require specific hardware (READ DOCS FIRST!) +# +CONFIG_SPI_FLASH_SUSPEND_QVL_SUPPORTED=y +# CONFIG_SPI_FLASH_AUTO_SUSPEND is not set +# end of Optional and Experimental Features (READ DOCS FIRST) +# end of Main Flash configuration + +# +# SPI Flash driver +# +CONFIG_SPI_FLASH_VERIFY_WRITE=y +CONFIG_SPI_FLASH_LOG_FAILED_WRITE=y +# CONFIG_SPI_FLASH_WARN_SETTING_ZERO_TO_ONE is not set +# CONFIG_SPI_FLASH_ENABLE_COUNTERS is not set +CONFIG_SPI_FLASH_ROM_DRIVER_PATCH=y +# CONFIG_SPI_FLASH_ROM_IMPL is not set +CONFIG_SPI_FLASH_DANGEROUS_WRITE_ABORTS=y +# CONFIG_SPI_FLASH_DANGEROUS_WRITE_FAILS is not set +# CONFIG_SPI_FLASH_DANGEROUS_WRITE_ALLOWED is not set +# CONFIG_SPI_FLASH_BYPASS_BLOCK_ERASE is not set +CONFIG_SPI_FLASH_YIELD_DURING_ERASE=y +CONFIG_SPI_FLASH_ERASE_YIELD_DURATION_MS=20 +CONFIG_SPI_FLASH_ERASE_YIELD_TICKS=1 +CONFIG_SPI_FLASH_WRITE_CHUNK_SIZE=8192 +# CONFIG_SPI_FLASH_SIZE_OVERRIDE is not set +# CONFIG_SPI_FLASH_CHECK_ERASE_TIMEOUT_DISABLED is not set +# CONFIG_SPI_FLASH_OVERRIDE_CHIP_DRIVER_LIST is not set + +# +# Auto-detect flash chips +# +CONFIG_SPI_FLASH_VENDOR_XMC_SUPPORTED=y +CONFIG_SPI_FLASH_VENDOR_GD_SUPPORTED=y +CONFIG_SPI_FLASH_VENDOR_ISSI_SUPPORTED=y +CONFIG_SPI_FLASH_VENDOR_MXIC_SUPPORTED=y +CONFIG_SPI_FLASH_VENDOR_WINBOND_SUPPORTED=y +CONFIG_SPI_FLASH_VENDOR_BOYA_SUPPORTED=y +CONFIG_SPI_FLASH_VENDOR_TH_SUPPORTED=y +CONFIG_SPI_FLASH_SUPPORT_ISSI_CHIP=y +CONFIG_SPI_FLASH_SUPPORT_MXIC_CHIP=y +CONFIG_SPI_FLASH_SUPPORT_GD_CHIP=y +CONFIG_SPI_FLASH_SUPPORT_WINBOND_CHIP=y +CONFIG_SPI_FLASH_SUPPORT_BOYA_CHIP=y +CONFIG_SPI_FLASH_SUPPORT_TH_CHIP=y +# end of Auto-detect flash chips + +CONFIG_SPI_FLASH_ENABLE_ENCRYPTED_READ_WRITE=y +# end of SPI Flash driver + +# +# SPIFFS Configuration +# +CONFIG_SPIFFS_MAX_PARTITIONS=3 + +# +# SPIFFS Cache Configuration +# +CONFIG_SPIFFS_CACHE=y +CONFIG_SPIFFS_CACHE_WR=y +# CONFIG_SPIFFS_CACHE_STATS is not set +# end of SPIFFS Cache Configuration + +CONFIG_SPIFFS_PAGE_CHECK=y +CONFIG_SPIFFS_GC_MAX_RUNS=10 +# CONFIG_SPIFFS_GC_STATS is not set +CONFIG_SPIFFS_PAGE_SIZE=256 +CONFIG_SPIFFS_OBJ_NAME_LEN=32 +# CONFIG_SPIFFS_FOLLOW_SYMLINKS is not set +CONFIG_SPIFFS_USE_MAGIC=y +CONFIG_SPIFFS_USE_MAGIC_LENGTH=y +CONFIG_SPIFFS_META_LENGTH=4 +CONFIG_SPIFFS_USE_MTIME=y + +# +# Debug Configuration +# +# CONFIG_SPIFFS_DBG is not set +# CONFIG_SPIFFS_API_DBG is not set +# CONFIG_SPIFFS_GC_DBG is not set +# CONFIG_SPIFFS_CACHE_DBG is not set +# CONFIG_SPIFFS_CHECK_DBG is not set +# CONFIG_SPIFFS_TEST_VISUALISATION is not set +# end of Debug Configuration +# end of SPIFFS Configuration + +# +# TCP Transport +# + +# +# Websocket +# +CONFIG_WS_TRANSPORT=y +CONFIG_WS_BUFFER_SIZE=1024 +# CONFIG_WS_DYNAMIC_BUFFER is not set +# end of Websocket +# end of TCP Transport + +# +# Unity unit testing library +# +CONFIG_UNITY_ENABLE_FLOAT=y +CONFIG_UNITY_ENABLE_DOUBLE=y +# CONFIG_UNITY_ENABLE_64BIT is not set +# CONFIG_UNITY_ENABLE_COLOR is not set +CONFIG_UNITY_ENABLE_IDF_TEST_RUNNER=y +# CONFIG_UNITY_ENABLE_FIXTURE is not set +# CONFIG_UNITY_ENABLE_BACKTRACE_ON_FAIL is not set +# end of Unity unit testing library + +# +# Virtual file system +# +CONFIG_VFS_SUPPORT_IO=y +CONFIG_VFS_SUPPORT_DIR=y +CONFIG_VFS_SUPPORT_SELECT=y +CONFIG_VFS_SUPPRESS_SELECT_DEBUG_OUTPUT=y +# CONFIG_VFS_SELECT_IN_RAM is not set +CONFIG_VFS_SUPPORT_TERMIOS=y +CONFIG_VFS_MAX_COUNT=8 + +# +# Host File System I/O (Semihosting) +# +CONFIG_VFS_SEMIHOSTFS_MAX_MOUNT_POINTS=1 +# end of Host File System I/O (Semihosting) +# end of Virtual file system + +# +# Wear Levelling +# +# CONFIG_WL_SECTOR_SIZE_512 is not set +CONFIG_WL_SECTOR_SIZE_4096=y +CONFIG_WL_SECTOR_SIZE=4096 +# end of Wear Levelling + +# +# Wi-Fi Provisioning Manager +# +CONFIG_WIFI_PROV_SCAN_MAX_ENTRIES=16 +CONFIG_WIFI_PROV_AUTOSTOP_TIMEOUT=30 +# CONFIG_WIFI_PROV_BLE_FORCE_ENCRYPTION is not set +CONFIG_WIFI_PROV_STA_ALL_CHANNEL_SCAN=y +# CONFIG_WIFI_PROV_STA_FAST_SCAN is not set +# end of Wi-Fi Provisioning Manager + +# +# Button +# +CONFIG_BUTTON_MAX=5 +CONFIG_BUTTON_POLL_TIMEOUT=10 +CONFIG_BUTTON_LONG_PRESS_TIMEOUT=1000 +CONFIG_BUTTON_AUTOREPEAT_TIMEOUT=500 +CONFIG_BUTTON_AUTOREPEAT_INTERVAL=250 +# end of Button + +# +# DPS310 driver +# +CONFIG_DPS310_PROTOCOL_USING_I2C=y +# end of DPS310 driver + +# +# Rotary encoders +# +CONFIG_RE_MAX=1 +CONFIG_RE_INTERVAL_US=1000 +CONFIG_RE_BTN_DEAD_TIME_US=10000 +CONFIG_RE_BTN_PRESSED_LEVEL_0=y +# CONFIG_RE_BTN_PRESSED_LEVEL_1 is not set +CONFIG_RE_BTN_LONG_PRESS_TIME_US=500000 +# end of Rotary encoders + +# +# Example +# +CONFIG_EXAMPLE_USING_FOO=y +# CONFIG_EXAMPLE_USING_BAR is not set +CONFIG_EXAMPLE_NUMBER=1 +# end of Example + +# +# HMC5883L +# +CONFIG_HMC5883L_MEAS_TIMEOUT=6000 +# end of HMC5883L + +# +# I2C +# +CONFIG_I2CDEV_TIMEOUT=1000 +# CONFIG_I2CDEV_NOLOCK is not set +# end of I2C + +# +# LED strip +# +CONFIG_LED_STRIP_FLUSH_TIMEOUT=1000 +CONFIG_LED_STRIP_PAUSE_LENGTH=50 +# end of LED strip + +# +# LED strip SPI +# +CONFIG_LED_STRIP_SPI_USING_SK9822=y +CONFIG_LED_STRIP_SPI_MUTEX_TIMEOUT_MS=1 +# end of LED strip SPI + +# +# MAX1704X Battery Fuel Gauge +# +CONFIG_MAX1704X_MODEL_3_4=y +# CONFIG_MAX1704X_MODEL_8_9 is not set +# end of MAX1704X Battery Fuel Gauge + +# +# MCP23x17 +# +CONFIG_MCP23X17_IFACE_I2C=y +# CONFIG_MCP23X17_IFACE_SPI is not set +# end of MCP23x17 + +# +# MPU6050 +# +# CONFIG_AUTO_CONFIG_ADDR is not set +# end of MPU6050 + +# +# OneWire +# +# CONFIG_ONEWIRE_CRC8_TABLE is not set +# end of OneWire +# end of Component config + +# CONFIG_IDF_EXPERIMENTAL_FEATURES is not set + +# Deprecated options for backward compatibility +# CONFIG_APP_BUILD_TYPE_ELF_RAM is not set +# CONFIG_NO_BLOBS is not set +# CONFIG_LOG_BOOTLOADER_LEVEL_NONE is not set +# CONFIG_LOG_BOOTLOADER_LEVEL_ERROR is not set +# CONFIG_LOG_BOOTLOADER_LEVEL_WARN is not set +CONFIG_LOG_BOOTLOADER_LEVEL_INFO=y +# CONFIG_LOG_BOOTLOADER_LEVEL_DEBUG is not set +# CONFIG_LOG_BOOTLOADER_LEVEL_VERBOSE is not set +CONFIG_LOG_BOOTLOADER_LEVEL=3 +# CONFIG_APP_ROLLBACK_ENABLE is not set +CONFIG_FLASH_ENCRYPTION_ENABLED=y +# CONFIG_FLASH_ENCRYPTION_INSECURE is not set +# CONFIG_FLASHMODE_QIO is not set +# CONFIG_FLASHMODE_QOUT is not set +CONFIG_FLASHMODE_DIO=y +# CONFIG_FLASHMODE_DOUT is not set +CONFIG_MONITOR_BAUD=115200 +# CONFIG_OPTIMIZATION_LEVEL_DEBUG is not set +# CONFIG_COMPILER_OPTIMIZATION_LEVEL_DEBUG is not set +# CONFIG_COMPILER_OPTIMIZATION_DEFAULT is not set +# CONFIG_OPTIMIZATION_LEVEL_RELEASE is not set +# CONFIG_COMPILER_OPTIMIZATION_LEVEL_RELEASE is not set +CONFIG_OPTIMIZATION_ASSERTIONS_ENABLED=y +# CONFIG_OPTIMIZATION_ASSERTIONS_SILENT is not set +# CONFIG_OPTIMIZATION_ASSERTIONS_DISABLED is not set +CONFIG_OPTIMIZATION_ASSERTION_LEVEL=2 +# CONFIG_CXX_EXCEPTIONS is not set +# CONFIG_STACK_CHECK_NONE is not set +# CONFIG_STACK_CHECK_NORM is not set +# CONFIG_STACK_CHECK_STRONG is not set +CONFIG_STACK_CHECK_ALL=y +CONFIG_STACK_CHECK=y +# CONFIG_WARN_WRITE_STRINGS is not set +# CONFIG_ESP32_APPTRACE_DEST_TRAX is not set +CONFIG_ESP32_APPTRACE_DEST_NONE=y +CONFIG_ESP32_APPTRACE_LOCK_ENABLE=y +# CONFIG_EXTERNAL_COEX_ENABLE is not set +# CONFIG_ESP_WIFI_EXTERNAL_COEXIST_ENABLE is not set +# CONFIG_EVENT_LOOP_PROFILING is not set +CONFIG_POST_EVENTS_FROM_ISR=y +CONFIG_POST_EVENTS_FROM_IRAM_ISR=y +# CONFIG_OTA_ALLOW_HTTP is not set +# CONFIG_ESP_SYSTEM_PD_FLASH is not set +CONFIG_ESP32C3_LIGHTSLEEP_GPIO_RESET_WORKAROUND=y +CONFIG_ESP32C3_RTC_CLK_SRC_INT_RC=y +# CONFIG_ESP32C3_RTC_CLK_SRC_EXT_CRYS is not set +# CONFIG_ESP32C3_RTC_CLK_SRC_EXT_OSC is not set +# CONFIG_ESP32C3_RTC_CLK_SRC_INT_8MD256 is not set +CONFIG_ESP32C3_RTC_CLK_CAL_CYCLES=1024 +CONFIG_ESP32_PHY_CALIBRATION_AND_DATA_STORAGE=y +# CONFIG_ESP32_PHY_INIT_DATA_IN_PARTITION is not set +CONFIG_ESP32_PHY_MAX_WIFI_TX_POWER=20 +CONFIG_ESP32_PHY_MAX_TX_POWER=20 +# CONFIG_REDUCE_PHY_TX_POWER is not set +# CONFIG_ESP32_REDUCE_PHY_TX_POWER is not set +CONFIG_ESP_SYSTEM_PM_POWER_DOWN_CPU=y +# CONFIG_ESP32C3_DEFAULT_CPU_FREQ_80 is not set +CONFIG_ESP32C3_DEFAULT_CPU_FREQ_160=y +CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ=160 +CONFIG_ESP32C3_MEMPROT_FEATURE=y +CONFIG_ESP32C3_MEMPROT_FEATURE_LOCK=y +CONFIG_SYSTEM_EVENT_QUEUE_SIZE=32 +CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE=2304 +CONFIG_MAIN_TASK_STACK_SIZE=3584 +CONFIG_CONSOLE_UART_DEFAULT=y +# CONFIG_CONSOLE_UART_CUSTOM is not set +# CONFIG_CONSOLE_UART_NONE is not set +# CONFIG_ESP_CONSOLE_UART_NONE is not set +CONFIG_CONSOLE_UART=y +CONFIG_CONSOLE_UART_NUM=0 +CONFIG_CONSOLE_UART_BAUDRATE=115200 +CONFIG_INT_WDT=y +CONFIG_INT_WDT_TIMEOUT_MS=300 +CONFIG_TASK_WDT=y +CONFIG_ESP_TASK_WDT=y +# CONFIG_TASK_WDT_PANIC is not set +CONFIG_TASK_WDT_TIMEOUT_S=5 +CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU0=y +# CONFIG_ESP32_DEBUG_STUBS_ENABLE is not set +CONFIG_ESP32C3_DEBUG_OCDAWARE=y +CONFIG_BROWNOUT_DET=y +CONFIG_ESP32C3_BROWNOUT_DET=y +CONFIG_ESP32C3_BROWNOUT_DET=y +CONFIG_BROWNOUT_DET_LVL_SEL_7=y +CONFIG_ESP32C3_BROWNOUT_DET_LVL_SEL_7=y +# CONFIG_BROWNOUT_DET_LVL_SEL_6 is not set +# CONFIG_ESP32C3_BROWNOUT_DET_LVL_SEL_6 is not set +# CONFIG_BROWNOUT_DET_LVL_SEL_5 is not set +# CONFIG_ESP32C3_BROWNOUT_DET_LVL_SEL_5 is not set +# CONFIG_BROWNOUT_DET_LVL_SEL_4 is not set +# CONFIG_ESP32C3_BROWNOUT_DET_LVL_SEL_4 is not set +# CONFIG_BROWNOUT_DET_LVL_SEL_3 is not set +# CONFIG_ESP32C3_BROWNOUT_DET_LVL_SEL_3 is not set +# CONFIG_BROWNOUT_DET_LVL_SEL_2 is not set +# CONFIG_ESP32C3_BROWNOUT_DET_LVL_SEL_2 is not set +CONFIG_BROWNOUT_DET_LVL=7 +CONFIG_ESP32C3_BROWNOUT_DET_LVL=7 +CONFIG_IPC_TASK_STACK_SIZE=1024 +CONFIG_TIMER_TASK_STACK_SIZE=3584 +CONFIG_ESP32_WIFI_ENABLED=y +CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM=10 +CONFIG_ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM=32 +# CONFIG_ESP32_WIFI_STATIC_TX_BUFFER is not set +CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER=y +CONFIG_ESP32_WIFI_TX_BUFFER_TYPE=1 +CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER_NUM=32 +# CONFIG_ESP32_WIFI_CSI_ENABLED is not set +CONFIG_ESP32_WIFI_AMPDU_TX_ENABLED=y +CONFIG_ESP32_WIFI_TX_BA_WIN=6 +CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED=y +CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED=y +CONFIG_ESP32_WIFI_RX_BA_WIN=6 +CONFIG_ESP32_WIFI_RX_BA_WIN=6 +CONFIG_ESP32_WIFI_NVS_ENABLED=y +CONFIG_ESP32_WIFI_SOFTAP_BEACON_MAX_LEN=752 +CONFIG_ESP32_WIFI_MGMT_SBUF_NUM=32 +CONFIG_ESP32_WIFI_IRAM_OPT=y +CONFIG_ESP32_WIFI_RX_IRAM_OPT=y +CONFIG_ESP32_WIFI_ENABLE_WPA3_SAE=y +CONFIG_ESP32_WIFI_ENABLE_WPA3_OWE_STA=y +CONFIG_WPA_MBEDTLS_CRYPTO=y +CONFIG_WPA_MBEDTLS_TLS_CLIENT=y +# CONFIG_WPA_WAPI_PSK is not set +# CONFIG_WPA_SUITE_B_192 is not set +# CONFIG_WPA_11KV_SUPPORT is not set +# CONFIG_WPA_MBO_SUPPORT is not set +# CONFIG_WPA_DPP_SUPPORT is not set +# CONFIG_WPA_11R_SUPPORT is not set +# CONFIG_WPA_WPS_SOFTAP_REGISTRAR is not set +# CONFIG_WPA_WPS_STRICT is not set +# CONFIG_WPA_DEBUG_PRINT is not set +# CONFIG_WPA_TESTING_OPTIONS is not set +# CONFIG_ESP32_ENABLE_COREDUMP_TO_FLASH is not set +# CONFIG_ESP32_ENABLE_COREDUMP_TO_UART is not set +CONFIG_ESP32_ENABLE_COREDUMP_TO_NONE=y +CONFIG_TIMER_TASK_PRIORITY=1 +CONFIG_TIMER_TASK_STACK_DEPTH=2048 +CONFIG_TIMER_QUEUE_LENGTH=10 +# CONFIG_ENABLE_STATIC_TASK_CLEAN_UP_HOOK is not set +# CONFIG_HAL_ASSERTION_SILIENT is not set +# CONFIG_L2_TO_L3_COPY is not set +CONFIG_ESP_GRATUITOUS_ARP=y +CONFIG_GARP_TMR_INTERVAL=60 +CONFIG_TCPIP_RECVMBOX_SIZE=32 +CONFIG_TCP_MAXRTX=12 +CONFIG_TCP_SYNMAXRTX=12 +CONFIG_TCP_MSS=1440 +CONFIG_TCP_MSL=60000 +CONFIG_TCP_SND_BUF_DEFAULT=5760 +CONFIG_TCP_WND_DEFAULT=5760 +CONFIG_TCP_RECVMBOX_SIZE=6 +CONFIG_TCP_QUEUE_OOSEQ=y +CONFIG_TCP_OVERSIZE_MSS=y +# CONFIG_TCP_OVERSIZE_QUARTER_MSS is not set +# CONFIG_TCP_OVERSIZE_DISABLE is not set +CONFIG_UDP_RECVMBOX_SIZE=6 +CONFIG_TCPIP_TASK_STACK_SIZE=3072 +CONFIG_TCPIP_TASK_AFFINITY_NO_AFFINITY=y +# CONFIG_TCPIP_TASK_AFFINITY_CPU0 is not set +CONFIG_TCPIP_TASK_AFFINITY=0x7FFFFFFF +# CONFIG_PPP_SUPPORT is not set +CONFIG_ESP32C3_TIME_SYSCALL_USE_RTC_SYSTIMER=y +# CONFIG_ESP32C3_TIME_SYSCALL_USE_RTC is not set +# CONFIG_ESP32C3_TIME_SYSCALL_USE_SYSTIMER is not set +# CONFIG_ESP32C3_TIME_SYSCALL_USE_NONE is not set +CONFIG_ESP32_PTHREAD_TASK_PRIO_DEFAULT=5 +CONFIG_ESP32_PTHREAD_TASK_STACK_SIZE_DEFAULT=3072 +CONFIG_ESP32_PTHREAD_STACK_MIN=768 +CONFIG_ESP32_PTHREAD_TASK_CORE_DEFAULT=-1 +CONFIG_ESP32_PTHREAD_TASK_NAME_DEFAULT="pthread" +CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ABORTS=y +# CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_FAILS is not set +# CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ALLOWED is not set +CONFIG_SUPPRESS_SELECT_DEBUG_OUTPUT=y +CONFIG_SUPPORT_TERMIOS=y +CONFIG_SEMIHOSTFS_MAX_MOUNT_POINTS=1 +# End of deprecated options