From 0d5e9acd34b622be867db9fcc4c42934622a6130 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Martin=20Povi=C5=A1er?= <povik@cutebit.org>
Date: Mon, 10 Jul 2023 12:54:02 +0200
Subject: [PATCH] README.md: s/write_ilang/write_rtlil/

It's my understanding write_ilang is deprecated so best no to mention it
in the README.
---
 README.md | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/README.md b/README.md
index f3a63cbec39..5e5a8ec3e12 100644
--- a/README.md
+++ b/README.md
@@ -156,9 +156,10 @@ reading and elaborating the design using the Verilog frontend:
 	yosys> read -sv tests/simple/fiedler-cooley.v
 	yosys> hierarchy -top up3down5
 
-writing the design to the console in Yosys's internal format:
+writing the design to the console in the RTLIL format used by Yosys
+internally:
 
-	yosys> write_ilang
+	yosys> write_rtlil
 
 convert processes (``always`` blocks) to netlist elements and perform
 some simple optimizations: