diff --git a/docs/source/CHAPTER_CellLib.rst b/docs/source/CHAPTER_CellLib.rst
index 4bbbe0ea85b..494c0651c6a 100644
--- a/docs/source/CHAPTER_CellLib.rst
+++ b/docs/source/CHAPTER_CellLib.rst
@@ -644,7 +644,7 @@ has the following parameters:
 	True if triggered on specific signals defined in ``\TRG``; false if
 	triggered whenever ``\ARGS`` or ``\EN`` change and ``\EN`` is 1.
 
-If ``\TRG_ENABLE`` is true, the following parameters are also set:
+If ``\TRG_ENABLE`` is true, the following parameters also apply:
 
 ``\TRG_WIDTH``
 	The number of bits in the ``\TRG`` port.
@@ -653,6 +653,10 @@ If ``\TRG_ENABLE`` is true, the following parameters are also set:
 	For each bit in ``\TRG``, 1 if that signal is positive-edge triggered, 0 if
 	negative-edge triggered.
 
+``\PRIORITY``
+	When multiple ``$print`` cells fire on the same trigger, they execute in
+	descending priority order.
+
 Ports:
 
 ``\TRG``
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index 849b5ebad46..81fb3189d94 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -315,7 +315,10 @@ struct AST_INTERNAL::ProcessGenerator
 	// Buffer for generating the init action
 	RTLIL::SigSpec init_lvalue, init_rvalue;
 
-	ProcessGenerator(AstNode *always, RTLIL::SigSpec initSyncSignalsArg = RTLIL::SigSpec()) : always(always), initSyncSignals(initSyncSignalsArg)
+	// The most recently assigned $print cell \PRIORITY.
+	int last_print_priority;
+
+	ProcessGenerator(AstNode *always, RTLIL::SigSpec initSyncSignalsArg = RTLIL::SigSpec()) : always(always), initSyncSignals(initSyncSignalsArg), last_print_priority(0)
 	{
 		// rewrite lookahead references
 		LookaheadRewriter la_rewriter(always);
@@ -716,6 +719,7 @@ struct AST_INTERNAL::ProcessGenerator
 				cell->parameters[ID::TRG_WIDTH] = triggers.size();
 				cell->parameters[ID::TRG_ENABLE] = !triggers.empty();
 				cell->parameters[ID::TRG_POLARITY] = polarity;
+				cell->parameters[ID::PRIORITY] = --last_print_priority;
 				cell->setPort(ID::TRG, triggers);
 
 				Wire *wire = current_module->addWire(sstr.str() + "_EN", 1);
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 09fe0800078..7a59c526275 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -1724,6 +1724,7 @@ namespace {
 				param(ID(FORMAT));
 				param_bool(ID::TRG_ENABLE);
 				param(ID::TRG_POLARITY);
+				param(ID::PRIORITY);
 				port(ID::EN, 1);
 				port(ID::TRG, param(ID::TRG_WIDTH));
 				port(ID::ARGS, param(ID::ARGS_WIDTH));
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index 32f2b693740..cdb6e02e762 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -1805,6 +1805,7 @@ module \$print (EN, TRG, ARGS);
 
 parameter FORMAT = "";
 parameter ARGS_WIDTH = 0;
+parameter PRIORITY = 0;
 parameter TRG_ENABLE = 1;
 
 parameter TRG_WIDTH = 0;