rah_sha_bridge.v

module rah_sha_bridge (
    input wire clk,                              // Clock signal
    input wire wr_fifo_empty,                   // FIFO empty signal
    input wire wr_fifo_a_empty,                 // FIFO almost empty signal
    input wire [511:0] wr_fifo_read_data,       // FIFO read data
    output wire wr_fifo_read_en,                // FIFO read enable signal
    
    input wire output_valid,                    // Output valid from the miner
    input wire [255:0] hash1_out,               // Intermediate hash output from the miner
    input wire [255:0] hash_result,             // Final hash result from the miner

    output wire input_valid,                    // Input valid signal
    output wire [511:0] block_header,           // Block header for miner input

    output wire pp_rd_fifo_en,                  // Enable for post-processing FIFO
    output reg [255:0] pp_rd_fifo_data,         // Data for post-processing FIFO
    output wire rst                              // Reset signal (output instead of input)
);

// Parameters
parameter DATA_WIDTH = 512;
parameter RESET_THRESHOLD = 5000000;
parameter BYTE_SIZE = 11;                       // Byte size for header assembly
parameter FIFO_CHUNK_SIZE = 48;                // Size of chunks for reading

// Registers
reg [DATA_WIDTH-1:0] r_block_header = 0;       // Register to hold block header
reg r_fifo_read_en = 0;                        // Register for FIFO read enable
reg [23:0] reset_counter = 0;                  // Reset counter
reg [3:0] byte_counter = 0;                    // Byte counter for block header assembly
reg data_sample_flag = 0;                      // Flag for data sampling
reg start_transfer = 0;                        // Transfer start flag
reg [255:0] r_hash_out = 0;                    // Register to store intermediate hash output
reg [15:0] rd_counter = 0;                     // Counter for read transfer
reg [2:0] rd_byte_counter = 0;                 // Counter for 48-bit chunk read from pp_rd_fifo_data
reg data_transfer;
reg block_header_en;

// FIFO read control
always @(posedge clk) begin
    if (!wr_fifo_empty) begin
        r_fifo_read_en <= 1;
    end else if (wr_fifo_a_empty) begin
        r_fifo_read_en <= 0;
    end 
    data_transfer <= r_fifo_read_en;
end

// Block header assembly (fixed case statement)
always @(posedge clk) begin
    if (data_transfer) begin
        case (byte_counter)
                10: r_block_header[31:0] <= wr_fifo_read_data[47:16];
                9: r_block_header[79:32] <= wr_fifo_read_data;
                8: r_block_header[127:80] <= wr_fifo_read_data;
                7: r_block_header[175:128] <= wr_fifo_read_data;
                6: r_block_header[223:176] <= wr_fifo_read_data;
                5: r_block_header[271:224] <= wr_fifo_read_data;
                4: r_block_header[319:272] <= wr_fifo_read_data;
                3: r_block_header[367:320] <= wr_fifo_read_data;
                2: r_block_header[415:368] <= wr_fifo_read_data;
                1: r_block_header[463:416] <= wr_fifo_read_data; 
                0: r_block_header[511:464] <= wr_fifo_read_data;
        endcase
        if (byte_counter <= 4'd10) begin
            byte_counter <= byte_counter + 1'b1;
            block_header_en <= 1'b0;
        end else begin
            block_header_en <= 1'b1;
            byte_counter <= 0;
        end
    end
end

// Read pp_rd_fifo_data in 48-bit chunks
always @(posedge clk) begin
    if (pp_rd_fifo_en) begin
        rd_byte_counter <= 0;
        pp_rd_fifo_data <= 0;
    end else if (start_transfer) begin
        case (rd_byte_counter)
            5: pp_rd_fifo_data[15:0] <= hash1_out[15:0];
            4: pp_rd_fifo_data[63:16] <= hash1_out[63:16];
            3: pp_rd_fifo_data[111:64] <= hash1_out[111:64];
            2: pp_rd_fifo_data[159:112] <= hash1_out[159:112];
            1: pp_rd_fifo_data[207:160] <= hash1_out[207:160];
            0: pp_rd_fifo_data[255:208] <= hash1_out[255:208];
        endcase

        if (rd_byte_counter == 5) begin
            rd_byte_counter <= 0;
        end else begin
            rd_byte_counter <= rd_byte_counter + 1;
        end
    end
end

// Reset logic
always @(posedge clk) begin
    if (byte_counter != 0 || r_fifo_read_en) begin
        reset_counter <= reset_counter + 1;
    end else begin
        reset_counter <= 0;
    end
end

// Hash handling and post-processing
always @(posedge clk) begin
    if (pp_rd_fifo_en) begin
        start_transfer <= 0;
        r_hash_out <= 0;
        rd_counter <= 0;
    end else if (output_valid) begin
        start_transfer <= 1;
        r_hash_out <= hash1_out;
    end

    if (start_transfer) begin
        rd_counter <= rd_counter + 1;
    end
end

// Output assignments
assign wr_fifo_read_en = r_fifo_read_en;
assign input_valid = r_fifo_read_en;
assign block_header = r_block_header;
assign pp_rd_fifo_en = start_transfer;
assign rst = (reset_counter > RESET_THRESHOLD) ? 1'b1 : 1'b0;

endmodule