From 8149ddbdb7072fa10ded3cd740a297f0f9f79232 Mon Sep 17 00:00:00 2001 From: Stefan Voss Date: Fri, 7 Feb 2025 21:27:59 +0100 Subject: [PATCH] flash align --- src/tang/nano20k_lcd/vic20nano_top_tn20k_lcd.vhd | 5 ++++- src/tang/primer20k/vic20nano_top_tp20k.vhd | 10 +++++++--- src/tang/primer20k_lcd/vic20nano_top_tp20k_lcd.vhd | 7 +++++-- src/vic20nano_top_tn20k.vhd | 5 ++++- 4 files changed, 20 insertions(+), 7 deletions(-) diff --git a/src/tang/nano20k_lcd/vic20nano_top_tn20k_lcd.vhd b/src/tang/nano20k_lcd/vic20nano_top_tn20k_lcd.vhd index 9a53159..f35f0e3 100644 --- a/src/tang/nano20k_lcd/vic20nano_top_tn20k_lcd.vhd +++ b/src/tang/nano20k_lcd/vic20nano_top_tn20k_lcd.vhd @@ -367,6 +367,7 @@ signal pll_locked_d1 : std_logic; signal pll_locked_hid : std_logic; signal paddle_1_analogA: std_logic; signal flash_ready : std_logic; +signal pll_locked_comb : std_logic; constant TAP_ADDR : std_logic_vector(22 downto 0) := 23x"200000"; @@ -835,6 +836,8 @@ port map( -- TP25k XTX XT25F64FWOIG -- TM138k Winbond 25Q128BVEA +pll_locked_comb <= pll_locked_hid and flash_lock; + -- 100Mhz for flash controller c1541 ROM flashclock: rPLL generic map ( @@ -1080,7 +1083,7 @@ module_inst: entity work.sysctrl flash_inst: entity work.flash port map( clk => flash_clk, - resetn => pll_locked, + resetn => pll_locked_comb, ready => flash_ready, busy => open, address => (x"2" & "000" & dos_sel & c1541rom_addr), diff --git a/src/tang/primer20k/vic20nano_top_tp20k.vhd b/src/tang/primer20k/vic20nano_top_tp20k.vhd index 05edf44..751dc1a 100644 --- a/src/tang/primer20k/vic20nano_top_tp20k.vhd +++ b/src/tang/primer20k/vic20nano_top_tp20k.vhd @@ -400,6 +400,8 @@ signal paddle_1_analogA : std_logic; signal paddle_1_analogB : std_logic; signal paddle_2_analogA : std_logic; signal paddle_2_analogB : std_logic; +signal flash_ready : std_logic; +signal pll_locked_comb : std_logic; constant TAP_ADDR : std_logic_vector(22 downto 0) := 23x"200000"; @@ -627,7 +629,7 @@ variable pause_cnt : integer range 0 to 2147483647; end if; end process; -disk_reset <= '1' when disk_pause or c1541_osd_reset or c1541_reset or resetvic20 else '0'; +disk_reset <= '1' when not flash_ready or disk_pause or c1541_osd_reset or c1541_reset or resetvic20 else '0'; -- rising edge sd_change triggers detection of new disk process(clk32, pll_locked_hid) @@ -1027,6 +1029,8 @@ port map( -- phase shift 135° TN20k, TP25k -- 270° TM 138k -- 90° TP20k +pll_locked_comb <= pll_locked_hid and flash_lock; + -- 100Mhz for flash controller c1541 ROM flashclock: rPLL generic map ( @@ -1316,8 +1320,8 @@ module_inst: entity work.sysctrl flash_inst: entity work.flash port map( clk => flash_clk, - resetn => pll_locked, - ready => open, + resetn => pll_locked_comb, + ready => flash_ready, busy => open, address => (x"2" & "000" & dos_sel & c1541rom_addr), cs => c1541rom_cs, diff --git a/src/tang/primer20k_lcd/vic20nano_top_tp20k_lcd.vhd b/src/tang/primer20k_lcd/vic20nano_top_tp20k_lcd.vhd index 4dc2f35..1139f77 100644 --- a/src/tang/primer20k_lcd/vic20nano_top_tp20k_lcd.vhd +++ b/src/tang/primer20k_lcd/vic20nano_top_tp20k_lcd.vhd @@ -399,7 +399,8 @@ signal lcd_r_i : std_logic_vector(5 downto 0); signal lcd_b_i : std_logic_vector(5 downto 0); signal uart_ext_rx : std_logic := '1'; signal uart_ext_tx : std_logic; -signal flash_ready : std_logic; +signal flash_ready : std_logic; +signal pll_locked_comb : std_logic; constant TAP_ADDR : std_logic_vector(22 downto 0) := 23x"200000"; @@ -956,6 +957,8 @@ port map( -- phase shift 135° TN20k, TP25k -- 270° TM 138k -- 90° TP20k +pll_locked_comb <= pll_locked_hid and flash_lock; + -- 100Mhz for flash controller c1541 ROM flashclock: rPLL generic map ( @@ -1245,7 +1248,7 @@ module_inst: entity work.sysctrl flash_inst: entity work.flash port map( clk => flash_clk, - resetn => pll_locked, + resetn => pll_locked_comb, ready => flash_ready, busy => open, address => (x"2" & "000" & dos_sel & c1541rom_addr), diff --git a/src/vic20nano_top_tn20k.vhd b/src/vic20nano_top_tn20k.vhd index f4b8477..d9f58b3 100644 --- a/src/vic20nano_top_tn20k.vhd +++ b/src/vic20nano_top_tn20k.vhd @@ -366,6 +366,7 @@ signal paddle_1_analogA: std_logic; signal ds_cs_i : std_logic; signal ds_miso_i : std_logic; signal flash_ready : std_logic; +signal pll_locked_comb : std_logic; constant TAP_ADDR : std_logic_vector(22 downto 0) := 23x"200000"; @@ -877,6 +878,8 @@ port map( -- TP25k XTX XT25F64FWOIG -- TM138k Winbond 25Q128BVEA +pll_locked_comb <= pll_locked_hid and flash_lock; + -- 100Mhz for flash controller c1541 ROM flashclock: rPLL generic map ( @@ -1122,7 +1125,7 @@ module_inst: entity work.sysctrl flash_inst: entity work.flash port map( clk => flash_clk, - resetn => pll_locked, + resetn => pll_locked_comb, ready => flash_ready, busy => open, address => (x"2" & "000" & dos_sel & c1541rom_addr),