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lra.c
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/* LRA (local register allocator) driver and LRA utilities.
Copyright (C) 2010-2020 Free Software Foundation, Inc.
Contributed by Vladimir Makarov <[email protected]>.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3, or (at your option) any later
version.
GCC is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
/* The Local Register Allocator (LRA) is a replacement of former
reload pass. It is focused to simplify code solving the reload
pass tasks, to make the code maintenance easier, and to implement new
perspective optimizations.
The major LRA design solutions are:
o division small manageable, separated sub-tasks
o reflection of all transformations and decisions in RTL as more
as possible
o insn constraints as a primary source of the info (minimizing
number of target-depended macros/hooks)
In brief LRA works by iterative insn process with the final goal is
to satisfy all insn and address constraints:
o New reload insns (in brief reloads) and reload pseudos might be
generated;
o Some pseudos might be spilled to assign hard registers to
new reload pseudos;
o Recalculating spilled pseudo values (rematerialization);
o Changing spilled pseudos to stack memory or their equivalences;
o Allocation stack memory changes the address displacement and
new iteration is needed.
Here is block diagram of LRA passes:
------------------------
--------------- | Undo inheritance for | ---------------
| Memory-memory | | spilled pseudos, | | New (and old) |
| move coalesce |<---| splits for pseudos got |<-- | pseudos |
--------------- | the same hard regs, | | assignment |
Start | | and optional reloads | ---------------
| | ------------------------ ^
V | ---------------- |
----------- V | Update virtual | |
| Remove |----> ------------>| register | |
| scratches | ^ | displacements | |
----------- | ---------------- |
| | |
| V New |
| ------------ pseudos -------------------
| |Constraints:| or insns | Inheritance/split |
| | RTL |--------->| transformations |
| | transfor- | | in EBB scope |
| substi- | mations | -------------------
| tutions ------------
| | No change
---------------- V
| Spilled pseudo | -------------------
| to memory |<----| Rematerialization |
| substitution | -------------------
----------------
| No susbtitions
V
-------------------------
| Hard regs substitution, |
| devirtalization, and |------> Finish
| restoring scratches got |
| memory |
-------------------------
To speed up the process:
o We process only insns affected by changes on previous
iterations;
o We don't use DFA-infrastructure because it results in much slower
compiler speed than a special IR described below does;
o We use a special insn representation for quick access to insn
info which is always *synchronized* with the current RTL;
o Insn IR is minimized by memory. It is divided on three parts:
o one specific for each insn in RTL (only operand locations);
o one common for all insns in RTL with the same insn code
(different operand attributes from machine descriptions);
o one oriented for maintenance of live info (list of pseudos).
o Pseudo data:
o all insns where the pseudo is referenced;
o live info (conflicting hard regs, live ranges, # of
references etc);
o data used for assigning (preferred hard regs, costs etc).
This file contains LRA driver, LRA utility functions and data, and
code for dealing with scratches. */
#include "config.h"
#include "system.h"
#include "coretypes.h"
#include "backend.h"
#include "target.h"
#include "rtl.h"
#include "tree.h"
#include "predict.h"
#include "df.h"
#include "memmodel.h"
#include "tm_p.h"
#include "optabs.h"
#include "regs.h"
#include "ira.h"
#include "recog.h"
#include "expr.h"
#include "cfgrtl.h"
#include "cfgbuild.h"
#include "lra.h"
#include "lra-int.h"
#include "print-rtl.h"
#include "function-abi.h"
/* Dump bitmap SET with TITLE and BB INDEX. */
void
lra_dump_bitmap_with_title (const char *title, bitmap set, int index)
{
unsigned int i;
int count;
bitmap_iterator bi;
static const int max_nums_on_line = 10;
if (bitmap_empty_p (set))
return;
fprintf (lra_dump_file, " %s %d:", title, index);
fprintf (lra_dump_file, "\n");
count = max_nums_on_line + 1;
EXECUTE_IF_SET_IN_BITMAP (set, 0, i, bi)
{
if (count > max_nums_on_line)
{
fprintf (lra_dump_file, "\n ");
count = 0;
}
fprintf (lra_dump_file, " %4u", i);
count++;
}
fprintf (lra_dump_file, "\n");
}
/* Hard registers currently not available for allocation. It can
changed after some hard registers become not eliminable. */
HARD_REG_SET lra_no_alloc_regs;
static int get_new_reg_value (void);
static void expand_reg_info (void);
static void invalidate_insn_recog_data (int);
static int get_insn_freq (rtx_insn *);
static void invalidate_insn_data_regno_info (lra_insn_recog_data_t,
rtx_insn *, int);
static void remove_scratches_1 (rtx_insn *);
/* Expand all regno related info needed for LRA. */
static void
expand_reg_data (int old)
{
resize_reg_info ();
expand_reg_info ();
ira_expand_reg_equiv ();
for (int i = (int) max_reg_num () - 1; i >= old; i--)
lra_change_class (i, ALL_REGS, " Set", true);
}
/* Create and return a new reg of ORIGINAL mode. If ORIGINAL is NULL
or of VOIDmode, use MD_MODE for the new reg. Initialize its
register class to RCLASS. Print message about assigning class
RCLASS containing new register name TITLE unless it is NULL. Use
attributes of ORIGINAL if it is a register. The created register
will have unique held value. */
rtx
lra_create_new_reg_with_unique_value (machine_mode md_mode, rtx original,
enum reg_class rclass, const char *title)
{
machine_mode mode;
rtx new_reg;
if (original == NULL_RTX || (mode = GET_MODE (original)) == VOIDmode)
mode = md_mode;
lra_assert (mode != VOIDmode);
new_reg = gen_reg_rtx (mode);
if (original == NULL_RTX || ! REG_P (original))
{
if (lra_dump_file != NULL)
fprintf (lra_dump_file, " Creating newreg=%i", REGNO (new_reg));
}
else
{
if (ORIGINAL_REGNO (original) >= FIRST_PSEUDO_REGISTER)
ORIGINAL_REGNO (new_reg) = ORIGINAL_REGNO (original);
REG_USERVAR_P (new_reg) = REG_USERVAR_P (original);
REG_POINTER (new_reg) = REG_POINTER (original);
REG_ATTRS (new_reg) = REG_ATTRS (original);
if (lra_dump_file != NULL)
fprintf (lra_dump_file, " Creating newreg=%i from oldreg=%i",
REGNO (new_reg), REGNO (original));
}
if (lra_dump_file != NULL)
{
if (title != NULL)
fprintf (lra_dump_file, ", assigning class %s to%s%s r%d",
reg_class_names[rclass], *title == '\0' ? "" : " ",
title, REGNO (new_reg));
fprintf (lra_dump_file, "\n");
}
expand_reg_data (max_reg_num ());
setup_reg_classes (REGNO (new_reg), rclass, NO_REGS, rclass);
return new_reg;
}
/* Analogous to the previous function but also inherits value of
ORIGINAL. */
rtx
lra_create_new_reg (machine_mode md_mode, rtx original,
enum reg_class rclass, const char *title)
{
rtx new_reg;
new_reg
= lra_create_new_reg_with_unique_value (md_mode, original, rclass, title);
if (original != NULL_RTX && REG_P (original))
lra_assign_reg_val (REGNO (original), REGNO (new_reg));
return new_reg;
}
/* Set up for REGNO unique hold value. */
void
lra_set_regno_unique_value (int regno)
{
lra_reg_info[regno].val = get_new_reg_value ();
}
/* Invalidate INSN related info used by LRA. The info should never be
used after that. */
void
lra_invalidate_insn_data (rtx_insn *insn)
{
lra_invalidate_insn_regno_info (insn);
invalidate_insn_recog_data (INSN_UID (insn));
}
/* Mark INSN deleted and invalidate the insn related info used by
LRA. */
void
lra_set_insn_deleted (rtx_insn *insn)
{
lra_invalidate_insn_data (insn);
SET_INSN_DELETED (insn);
}
/* Delete an unneeded INSN and any previous insns who sole purpose is
loading data that is dead in INSN. */
void
lra_delete_dead_insn (rtx_insn *insn)
{
rtx_insn *prev = prev_real_insn (insn);
rtx prev_dest;
/* If the previous insn sets a register that dies in our insn,
delete it too. */
if (prev && GET_CODE (PATTERN (prev)) == SET
&& (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest))
&& reg_mentioned_p (prev_dest, PATTERN (insn))
&& find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
&& ! side_effects_p (SET_SRC (PATTERN (prev))))
lra_delete_dead_insn (prev);
lra_set_insn_deleted (insn);
}
/* Emit insn x = y + z. Return NULL if we failed to do it.
Otherwise, return the insn. We don't use gen_add3_insn as it might
clobber CC. */
static rtx_insn *
emit_add3_insn (rtx x, rtx y, rtx z)
{
rtx_insn *last;
last = get_last_insn ();
if (have_addptr3_insn (x, y, z))
{
rtx_insn *insn = gen_addptr3_insn (x, y, z);
/* If the target provides an "addptr" pattern it hopefully does
for a reason. So falling back to the normal add would be
a bug. */
lra_assert (insn != NULL_RTX);
emit_insn (insn);
return insn;
}
rtx_insn *insn = emit_insn (gen_rtx_SET (x, gen_rtx_PLUS (GET_MODE (y),
y, z)));
if (recog_memoized (insn) < 0)
{
delete_insns_since (last);
insn = NULL;
}
return insn;
}
/* Emit insn x = x + y. Return the insn. We use gen_add2_insn as the
last resort. */
static rtx_insn *
emit_add2_insn (rtx x, rtx y)
{
rtx_insn *insn = emit_add3_insn (x, x, y);
if (insn == NULL_RTX)
{
insn = gen_add2_insn (x, y);
if (insn != NULL_RTX)
emit_insn (insn);
}
return insn;
}
/* Target checks operands through operand predicates to recognize an
insn. We should have a special precaution to generate add insns
which are frequent results of elimination.
Emit insns for x = y + z. X can be used to store intermediate
values and should be not in Y and Z when we use X to store an
intermediate value. Y + Z should form [base] [+ index[ * scale]] [
+ disp] where base and index are registers, disp and scale are
constants. Y should contain base if it is present, Z should
contain disp if any. index[*scale] can be part of Y or Z. */
void
lra_emit_add (rtx x, rtx y, rtx z)
{
int old;
rtx_insn *last;
rtx a1, a2, base, index, disp, scale, index_scale;
bool ok_p;
rtx_insn *add3_insn = emit_add3_insn (x, y, z);
old = max_reg_num ();
if (add3_insn != NULL)
;
else
{
disp = a2 = NULL_RTX;
if (GET_CODE (y) == PLUS)
{
a1 = XEXP (y, 0);
a2 = XEXP (y, 1);
disp = z;
}
else
{
a1 = y;
if (CONSTANT_P (z))
disp = z;
else
a2 = z;
}
index_scale = scale = NULL_RTX;
if (GET_CODE (a1) == MULT)
{
index_scale = a1;
index = XEXP (a1, 0);
scale = XEXP (a1, 1);
base = a2;
}
else if (a2 != NULL_RTX && GET_CODE (a2) == MULT)
{
index_scale = a2;
index = XEXP (a2, 0);
scale = XEXP (a2, 1);
base = a1;
}
else
{
base = a1;
index = a2;
}
if ((base != NULL_RTX && ! (REG_P (base) || GET_CODE (base) == SUBREG))
|| (index != NULL_RTX
&& ! (REG_P (index) || GET_CODE (index) == SUBREG))
|| (disp != NULL_RTX && ! CONSTANT_P (disp))
|| (scale != NULL_RTX && ! CONSTANT_P (scale)))
{
/* Probably we have no 3 op add. Last chance is to use 2-op
add insn. To succeed, don't move Z to X as an address
segment always comes in Y. Otherwise, we might fail when
adding the address segment to register. */
lra_assert (x != y && x != z);
emit_move_insn (x, y);
rtx_insn *insn = emit_add2_insn (x, z);
lra_assert (insn != NULL_RTX);
}
else
{
if (index_scale == NULL_RTX)
index_scale = index;
if (disp == NULL_RTX)
{
/* Generate x = index_scale; x = x + base. */
lra_assert (index_scale != NULL_RTX && base != NULL_RTX);
emit_move_insn (x, index_scale);
rtx_insn *insn = emit_add2_insn (x, base);
lra_assert (insn != NULL_RTX);
}
else if (scale == NULL_RTX)
{
/* Try x = base + disp. */
lra_assert (base != NULL_RTX);
last = get_last_insn ();
rtx_insn *move_insn =
emit_move_insn (x, gen_rtx_PLUS (GET_MODE (base), base, disp));
if (recog_memoized (move_insn) < 0)
{
delete_insns_since (last);
/* Generate x = disp; x = x + base. */
emit_move_insn (x, disp);
rtx_insn *add2_insn = emit_add2_insn (x, base);
lra_assert (add2_insn != NULL_RTX);
}
/* Generate x = x + index. */
if (index != NULL_RTX)
{
rtx_insn *insn = emit_add2_insn (x, index);
lra_assert (insn != NULL_RTX);
}
}
else
{
/* Try x = index_scale; x = x + disp; x = x + base. */
last = get_last_insn ();
rtx_insn *move_insn = emit_move_insn (x, index_scale);
ok_p = false;
if (recog_memoized (move_insn) >= 0)
{
rtx_insn *insn = emit_add2_insn (x, disp);
if (insn != NULL_RTX)
{
if (base == NULL_RTX)
ok_p = true;
else
{
insn = emit_add2_insn (x, base);
if (insn != NULL_RTX)
ok_p = true;
}
}
}
if (! ok_p)
{
rtx_insn *insn;
delete_insns_since (last);
/* Generate x = disp; x = x + base; x = x + index_scale. */
emit_move_insn (x, disp);
if (base != NULL_RTX)
{
insn = emit_add2_insn (x, base);
lra_assert (insn != NULL_RTX);
}
insn = emit_add2_insn (x, index_scale);
lra_assert (insn != NULL_RTX);
}
}
}
}
/* Functions emit_... can create pseudos -- so expand the pseudo
data. */
if (old != max_reg_num ())
expand_reg_data (old);
}
/* The number of emitted reload insns so far. */
int lra_curr_reload_num;
/* Emit x := y, processing special case when y = u + v or y = u + v *
scale + w through emit_add (Y can be an address which is base +
index reg * scale + displacement in general case). X may be used
as intermediate result therefore it should be not in Y. */
void
lra_emit_move (rtx x, rtx y)
{
int old;
if (GET_CODE (y) != PLUS)
{
if (rtx_equal_p (x, y))
return;
old = max_reg_num ();
rtx_insn *insn = emit_move_insn (x, y);
/* The move pattern may require scratch registers, so convert them
into real registers now. */
if (insn != NULL_RTX)
remove_scratches_1 (insn);
if (REG_P (x))
lra_reg_info[ORIGINAL_REGNO (x)].last_reload = ++lra_curr_reload_num;
/* Function emit_move can create pseudos -- so expand the pseudo
data. */
if (old != max_reg_num ())
expand_reg_data (old);
return;
}
lra_emit_add (x, XEXP (y, 0), XEXP (y, 1));
}
/* Update insn operands which are duplication of operands whose
numbers are in array of NOPS (with end marker -1). The insn is
represented by its LRA internal representation ID. */
void
lra_update_dups (lra_insn_recog_data_t id, signed char *nops)
{
int i, j, nop;
struct lra_static_insn_data *static_id = id->insn_static_data;
for (i = 0; i < static_id->n_dups; i++)
for (j = 0; (nop = nops[j]) >= 0; j++)
if (static_id->dup_num[i] == nop)
*id->dup_loc[i] = *id->operand_loc[nop];
}
/* This page contains code dealing with info about registers in the
insns. */
/* Pools for insn reg info. */
object_allocator<lra_insn_reg> lra_insn_reg_pool ("insn regs");
/* Create LRA insn related info about a reference to REGNO in INSN
with TYPE (in/out/inout), biggest reference mode MODE, flag that it
is reference through subreg (SUBREG_P), and reference to the next
insn reg info (NEXT). If REGNO can be early clobbered,
alternatives in which it can be early clobbered are given by
EARLY_CLOBBER_ALTS. */
static struct lra_insn_reg *
new_insn_reg (rtx_insn *insn, int regno, enum op_type type,
machine_mode mode, bool subreg_p,
alternative_mask early_clobber_alts,
struct lra_insn_reg *next)
{
lra_insn_reg *ir = lra_insn_reg_pool.allocate ();
ir->type = type;
ir->biggest_mode = mode;
if (NONDEBUG_INSN_P (insn)
&& partial_subreg_p (lra_reg_info[regno].biggest_mode, mode))
lra_reg_info[regno].biggest_mode = mode;
ir->subreg_p = subreg_p;
ir->early_clobber_alts = early_clobber_alts;
ir->regno = regno;
ir->next = next;
return ir;
}
/* Free insn reg info list IR. */
static void
free_insn_regs (struct lra_insn_reg *ir)
{
struct lra_insn_reg *next_ir;
for (; ir != NULL; ir = next_ir)
{
next_ir = ir->next;
lra_insn_reg_pool.remove (ir);
}
}
/* Finish pool for insn reg info. */
static void
finish_insn_regs (void)
{
lra_insn_reg_pool.release ();
}
/* This page contains code dealing LRA insn info (or in other words
LRA internal insn representation). */
/* Map INSN_CODE -> the static insn data. This info is valid during
all translation unit. */
struct lra_static_insn_data *insn_code_data[NUM_INSN_CODES];
/* Debug insns are represented as a special insn with one input
operand which is RTL expression in var_location. */
/* The following data are used as static insn operand data for all
debug insns. If structure lra_operand_data is changed, the
initializer should be changed too. */
static struct lra_operand_data debug_operand_data =
{
NULL, /* alternative */
0, /* early_clobber_alts */
E_VOIDmode, /* We are not interesting in the operand mode. */
OP_IN,
0, 0, 0
};
/* The following data are used as static insn data for all debug
bind insns. If structure lra_static_insn_data is changed, the
initializer should be changed too. */
static struct lra_static_insn_data debug_bind_static_data =
{
&debug_operand_data,
0, /* Duplication operands #. */
-1, /* Commutative operand #. */
1, /* Operands #. There is only one operand which is debug RTL
expression. */
0, /* Duplications #. */
0, /* Alternatives #. We are not interesting in alternatives
because we does not proceed debug_insns for reloads. */
NULL, /* Hard registers referenced in machine description. */
NULL /* Descriptions of operands in alternatives. */
};
/* The following data are used as static insn data for all debug
marker insns. If structure lra_static_insn_data is changed, the
initializer should be changed too. */
static struct lra_static_insn_data debug_marker_static_data =
{
&debug_operand_data,
0, /* Duplication operands #. */
-1, /* Commutative operand #. */
0, /* Operands #. There isn't any operand. */
0, /* Duplications #. */
0, /* Alternatives #. We are not interesting in alternatives
because we does not proceed debug_insns for reloads. */
NULL, /* Hard registers referenced in machine description. */
NULL /* Descriptions of operands in alternatives. */
};
/* Called once per compiler work to initialize some LRA data related
to insns. */
static void
init_insn_code_data_once (void)
{
memset (insn_code_data, 0, sizeof (insn_code_data));
}
/* Called once per compiler work to finalize some LRA data related to
insns. */
static void
finish_insn_code_data_once (void)
{
for (unsigned int i = 0; i < NUM_INSN_CODES; i++)
{
if (insn_code_data[i] != NULL)
{
free (insn_code_data[i]);
insn_code_data[i] = NULL;
}
}
}
/* Return static insn data, allocate and setup if necessary. Although
dup_num is static data (it depends only on icode), to set it up we
need to extract insn first. So recog_data should be valid for
normal insn (ICODE >= 0) before the call. */
static struct lra_static_insn_data *
get_static_insn_data (int icode, int nop, int ndup, int nalt)
{
struct lra_static_insn_data *data;
size_t n_bytes;
lra_assert (icode < (int) NUM_INSN_CODES);
if (icode >= 0 && (data = insn_code_data[icode]) != NULL)
return data;
lra_assert (nop >= 0 && ndup >= 0 && nalt >= 0);
n_bytes = sizeof (struct lra_static_insn_data)
+ sizeof (struct lra_operand_data) * nop
+ sizeof (int) * ndup;
data = XNEWVAR (struct lra_static_insn_data, n_bytes);
data->operand_alternative = NULL;
data->n_operands = nop;
data->n_dups = ndup;
data->n_alternatives = nalt;
data->operand = ((struct lra_operand_data *)
((char *) data + sizeof (struct lra_static_insn_data)));
data->dup_num = ((int *) ((char *) data->operand
+ sizeof (struct lra_operand_data) * nop));
if (icode >= 0)
{
int i;
insn_code_data[icode] = data;
for (i = 0; i < nop; i++)
{
data->operand[i].constraint
= insn_data[icode].operand[i].constraint;
data->operand[i].mode = insn_data[icode].operand[i].mode;
data->operand[i].strict_low = insn_data[icode].operand[i].strict_low;
data->operand[i].is_operator
= insn_data[icode].operand[i].is_operator;
data->operand[i].type
= (data->operand[i].constraint[0] == '=' ? OP_OUT
: data->operand[i].constraint[0] == '+' ? OP_INOUT
: OP_IN);
data->operand[i].is_address = false;
}
for (i = 0; i < ndup; i++)
data->dup_num[i] = recog_data.dup_num[i];
}
return data;
}
/* The current length of the following array. */
int lra_insn_recog_data_len;
/* Map INSN_UID -> the insn recog data (NULL if unknown). */
lra_insn_recog_data_t *lra_insn_recog_data;
/* Alloc pool we allocate entries for lra_insn_recog_data from. */
static object_allocator<class lra_insn_recog_data>
lra_insn_recog_data_pool ("insn recog data pool");
/* Initialize LRA data about insns. */
static void
init_insn_recog_data (void)
{
lra_insn_recog_data_len = 0;
lra_insn_recog_data = NULL;
}
/* Expand, if necessary, LRA data about insns. */
static void
check_and_expand_insn_recog_data (int index)
{
int i, old;
if (lra_insn_recog_data_len > index)
return;
old = lra_insn_recog_data_len;
lra_insn_recog_data_len = index * 3 / 2 + 1;
lra_insn_recog_data = XRESIZEVEC (lra_insn_recog_data_t,
lra_insn_recog_data,
lra_insn_recog_data_len);
for (i = old; i < lra_insn_recog_data_len; i++)
lra_insn_recog_data[i] = NULL;
}
/* Finish LRA DATA about insn. */
static void
free_insn_recog_data (lra_insn_recog_data_t data)
{
if (data->operand_loc != NULL)
free (data->operand_loc);
if (data->dup_loc != NULL)
free (data->dup_loc);
if (data->arg_hard_regs != NULL)
free (data->arg_hard_regs);
if (data->icode < 0 && NONDEBUG_INSN_P (data->insn))
{
if (data->insn_static_data->operand_alternative != NULL)
free (const_cast <operand_alternative *>
(data->insn_static_data->operand_alternative));
free_insn_regs (data->insn_static_data->hard_regs);
free (data->insn_static_data);
}
free_insn_regs (data->regs);
data->regs = NULL;
lra_insn_recog_data_pool.remove (data);
}
/* Pools for copies. */
static object_allocator<lra_copy> lra_copy_pool ("lra copies");
/* Finish LRA data about all insns. */
static void
finish_insn_recog_data (void)
{
int i;
lra_insn_recog_data_t data;
for (i = 0; i < lra_insn_recog_data_len; i++)
if ((data = lra_insn_recog_data[i]) != NULL)
free_insn_recog_data (data);
finish_insn_regs ();
lra_copy_pool.release ();
lra_insn_reg_pool.release ();
lra_insn_recog_data_pool.release ();
free (lra_insn_recog_data);
}
/* Setup info about operands in alternatives of LRA DATA of insn. */
static void
setup_operand_alternative (lra_insn_recog_data_t data,
const operand_alternative *op_alt)
{
int i, j, nop, nalt;
int icode = data->icode;
struct lra_static_insn_data *static_data = data->insn_static_data;
static_data->commutative = -1;
nop = static_data->n_operands;
nalt = static_data->n_alternatives;
static_data->operand_alternative = op_alt;
for (i = 0; i < nop; i++)
{
static_data->operand[i].early_clobber_alts = 0;
static_data->operand[i].is_address = false;
if (static_data->operand[i].constraint[0] == '%')
{
/* We currently only support one commutative pair of operands. */
if (static_data->commutative < 0)
static_data->commutative = i;
else
lra_assert (icode < 0); /* Asm */
/* The last operand should not be marked commutative. */
lra_assert (i != nop - 1);
}
}
for (j = 0; j < nalt; j++)
for (i = 0; i < nop; i++, op_alt++)
{
if (op_alt->earlyclobber)
static_data->operand[i].early_clobber_alts |= (alternative_mask) 1 << j;
static_data->operand[i].is_address |= op_alt->is_address;
}
}
/* Recursively process X and collect info about registers, which are
not the insn operands, in X with TYPE (in/out/inout) and flag that
it is early clobbered in the insn (EARLY_CLOBBER) and add the info
to LIST. X is a part of insn given by DATA. Return the result
list. */
static struct lra_insn_reg *
collect_non_operand_hard_regs (rtx_insn *insn, rtx *x,
lra_insn_recog_data_t data,
struct lra_insn_reg *list,
enum op_type type, bool early_clobber)
{
int i, j, regno, last;
bool subreg_p;
machine_mode mode;
struct lra_insn_reg *curr;
rtx op = *x;
enum rtx_code code = GET_CODE (op);
const char *fmt = GET_RTX_FORMAT (code);
for (i = 0; i < data->insn_static_data->n_operands; i++)
if (! data->insn_static_data->operand[i].is_operator
&& x == data->operand_loc[i])
/* It is an operand loc. Stop here. */
return list;
for (i = 0; i < data->insn_static_data->n_dups; i++)
if (x == data->dup_loc[i])
/* It is a dup loc. Stop here. */
return list;
mode = GET_MODE (op);
subreg_p = false;
if (code == SUBREG)
{
mode = wider_subreg_mode (op);
if (read_modify_subreg_p (op))
subreg_p = true;
op = SUBREG_REG (op);
code = GET_CODE (op);
}
if (REG_P (op))
{
if ((regno = REGNO (op)) >= FIRST_PSEUDO_REGISTER)
return list;
/* Process all regs even unallocatable ones as we need info
about all regs for rematerialization pass. */
for (last = end_hard_regno (mode, regno); regno < last; regno++)
{
for (curr = list; curr != NULL; curr = curr->next)
if (curr->regno == regno && curr->subreg_p == subreg_p
&& curr->biggest_mode == mode)
{
if (curr->type != type)
curr->type = OP_INOUT;
if (early_clobber)
curr->early_clobber_alts = ALL_ALTERNATIVES;
break;
}
if (curr == NULL)
{
/* This is a new hard regno or the info cannot be
integrated into the found structure. */
#ifdef STACK_REGS
early_clobber
= (early_clobber
/* This clobber is to inform popping floating
point stack only. */
&& ! (FIRST_STACK_REG <= regno
&& regno <= LAST_STACK_REG));
#endif
list = new_insn_reg (data->insn, regno, type, mode, subreg_p,
early_clobber ? ALL_ALTERNATIVES : 0, list);
}
}
return list;
}
switch (code)
{
case SET:
list = collect_non_operand_hard_regs (insn, &SET_DEST (op), data,
list, OP_OUT, false);
list = collect_non_operand_hard_regs (insn, &SET_SRC (op), data,
list, OP_IN, false);
break;
case CLOBBER:
/* We treat clobber of non-operand hard registers as early clobber. */
list = collect_non_operand_hard_regs (insn, &XEXP (op, 0), data,
list, OP_OUT, true);
break;
case PRE_INC: case PRE_DEC: case POST_INC: case POST_DEC:
list = collect_non_operand_hard_regs (insn, &XEXP (op, 0), data,
list, OP_INOUT, false);
break;
case PRE_MODIFY: case POST_MODIFY:
list = collect_non_operand_hard_regs (insn, &XEXP (op, 0), data,
list, OP_INOUT, false);
list = collect_non_operand_hard_regs (insn, &XEXP (op, 1), data,
list, OP_IN, false);
break;
default:
fmt = GET_RTX_FORMAT (code);
for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
{
if (fmt[i] == 'e')
list = collect_non_operand_hard_regs (insn, &XEXP (op, i), data,
list, OP_IN, false);
else if (fmt[i] == 'E')
for (j = XVECLEN (op, i) - 1; j >= 0; j--)
list = collect_non_operand_hard_regs (insn, &XVECEXP (op, i, j),
data, list, OP_IN, false);
}
}
return list;
}
/* Set up and return info about INSN. Set up the info if it is not set up
yet. */
lra_insn_recog_data_t
lra_set_insn_recog_data (rtx_insn *insn)
{
lra_insn_recog_data_t data;
int i, n, icode;
rtx **locs;
unsigned int uid = INSN_UID (insn);
struct lra_static_insn_data *insn_static_data;
check_and_expand_insn_recog_data (uid);
if (DEBUG_INSN_P (insn))
icode = -1;
else
{
icode = INSN_CODE (insn);
if (icode < 0)
/* It might be a new simple insn which is not recognized yet. */
INSN_CODE (insn) = icode = recog_memoized (insn);
}
data = lra_insn_recog_data_pool.allocate ();
lra_insn_recog_data[uid] = data;
data->insn = insn;
data->used_insn_alternative = LRA_UNKNOWN_ALT;
data->icode = icode;
data->regs = NULL;
if (DEBUG_INSN_P (insn))
{
data->dup_loc = NULL;
data->arg_hard_regs = NULL;
data->preferred_alternatives = ALL_ALTERNATIVES;
if (DEBUG_BIND_INSN_P (insn))
{
data->insn_static_data = &debug_bind_static_data;
data->operand_loc = XNEWVEC (rtx *, 1);
data->operand_loc[0] = &INSN_VAR_LOCATION_LOC (insn);
}
else if (DEBUG_MARKER_INSN_P (insn))
{
data->insn_static_data = &debug_marker_static_data;
data->operand_loc = NULL;
}
return data;
}
if (icode < 0)
{
int nop, nalt;
machine_mode operand_mode[MAX_RECOG_OPERANDS];
const char *constraints[MAX_RECOG_OPERANDS];
nop = asm_noperands (PATTERN (insn));
data->operand_loc = data->dup_loc = NULL;
nalt = 1;
if (nop < 0)
{
/* It is a special insn like USE or CLOBBER. We should
recognize any regular insn otherwise LRA can do nothing
with this insn. */