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postreload.c
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/* Perform simple optimizations to clean up the result of reload.
Copyright (C) 1987-2020 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3, or (at your option) any later
version.
GCC is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
#include "config.h"
#include "system.h"
#include "coretypes.h"
#include "backend.h"
#include "target.h"
#include "rtl.h"
#include "tree.h"
#include "predict.h"
#include "df.h"
#include "memmodel.h"
#include "tm_p.h"
#include "optabs.h"
#include "regs.h"
#include "emit-rtl.h"
#include "recog.h"
#include "cfgrtl.h"
#include "cfgbuild.h"
#include "cfgcleanup.h"
#include "reload.h"
#include "cselib.h"
#include "tree-pass.h"
#include "dbgcnt.h"
#include "function-abi.h"
#include "rtl-iter.h"
static int reload_cse_noop_set_p (rtx);
static bool reload_cse_simplify (rtx_insn *, rtx);
static void reload_cse_regs_1 (void);
static int reload_cse_simplify_set (rtx, rtx_insn *);
static int reload_cse_simplify_operands (rtx_insn *, rtx);
static void reload_combine (void);
static void reload_combine_note_use (rtx *, rtx_insn *, int, rtx);
static void reload_combine_note_store (rtx, const_rtx, void *);
static bool reload_cse_move2add (rtx_insn *);
static void move2add_note_store (rtx, const_rtx, void *);
/* Call cse / combine like post-reload optimization phases.
FIRST is the first instruction. */
static void
reload_cse_regs (rtx_insn *first ATTRIBUTE_UNUSED)
{
bool moves_converted;
reload_cse_regs_1 ();
reload_combine ();
moves_converted = reload_cse_move2add (first);
if (flag_expensive_optimizations)
{
if (moves_converted)
reload_combine ();
reload_cse_regs_1 ();
}
}
/* See whether a single set SET is a noop. */
static int
reload_cse_noop_set_p (rtx set)
{
if (cselib_reg_set_mode (SET_DEST (set)) != GET_MODE (SET_DEST (set)))
return 0;
return rtx_equal_for_cselib_p (SET_DEST (set), SET_SRC (set));
}
/* Try to simplify INSN. Return true if the CFG may have changed. */
static bool
reload_cse_simplify (rtx_insn *insn, rtx testreg)
{
rtx body = PATTERN (insn);
basic_block insn_bb = BLOCK_FOR_INSN (insn);
unsigned insn_bb_succs = EDGE_COUNT (insn_bb->succs);
/* If NO_FUNCTION_CSE has been set by the target, then we should not try
to cse function calls. */
if (NO_FUNCTION_CSE && CALL_P (insn))
return false;
if (GET_CODE (body) == SET)
{
int count = 0;
/* Simplify even if we may think it is a no-op.
We may think a memory load of a value smaller than WORD_SIZE
is redundant because we haven't taken into account possible
implicit extension. reload_cse_simplify_set() will bring
this out, so it's safer to simplify before we delete. */
count += reload_cse_simplify_set (body, insn);
if (!count && reload_cse_noop_set_p (body))
{
if (check_for_inc_dec (insn))
delete_insn_and_edges (insn);
/* We're done with this insn. */
goto done;
}
if (count > 0)
apply_change_group ();
else
reload_cse_simplify_operands (insn, testreg);
}
else if (GET_CODE (body) == PARALLEL)
{
int i;
int count = 0;
rtx value = NULL_RTX;
/* Registers mentioned in the clobber list for an asm cannot be reused
within the body of the asm. Invalidate those registers now so that
we don't try to substitute values for them. */
if (asm_noperands (body) >= 0)
{
for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
{
rtx part = XVECEXP (body, 0, i);
if (GET_CODE (part) == CLOBBER && REG_P (XEXP (part, 0)))
cselib_invalidate_rtx (XEXP (part, 0));
}
}
/* If every action in a PARALLEL is a noop, we can delete
the entire PARALLEL. */
for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
{
rtx part = XVECEXP (body, 0, i);
if (GET_CODE (part) == SET)
{
if (! reload_cse_noop_set_p (part))
break;
if (REG_P (SET_DEST (part))
&& REG_FUNCTION_VALUE_P (SET_DEST (part)))
{
if (value)
break;
value = SET_DEST (part);
}
}
else if (GET_CODE (part) != CLOBBER && GET_CODE (part) != USE)
break;
}
if (i < 0)
{
if (check_for_inc_dec (insn))
delete_insn_and_edges (insn);
/* We're done with this insn. */
goto done;
}
/* It's not a no-op, but we can try to simplify it. */
for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
if (GET_CODE (XVECEXP (body, 0, i)) == SET)
count += reload_cse_simplify_set (XVECEXP (body, 0, i), insn);
if (count > 0)
apply_change_group ();
else
reload_cse_simplify_operands (insn, testreg);
}
done:
return (EDGE_COUNT (insn_bb->succs) != insn_bb_succs);
}
/* Do a very simple CSE pass over the hard registers.
This function detects no-op moves where we happened to assign two
different pseudo-registers to the same hard register, and then
copied one to the other. Reload will generate a useless
instruction copying a register to itself.
This function also detects cases where we load a value from memory
into two different registers, and (if memory is more expensive than
registers) changes it to simply copy the first register into the
second register.
Another optimization is performed that scans the operands of each
instruction to see whether the value is already available in a
hard register. It then replaces the operand with the hard register
if possible, much like an optional reload would. */
static void
reload_cse_regs_1 (void)
{
bool cfg_changed = false;
basic_block bb;
rtx_insn *insn;
rtx testreg = gen_rtx_REG (word_mode, LAST_VIRTUAL_REGISTER + 1);
cselib_init (CSELIB_RECORD_MEMORY);
init_alias_analysis ();
FOR_EACH_BB_FN (bb, cfun)
FOR_BB_INSNS (bb, insn)
{
if (INSN_P (insn))
cfg_changed |= reload_cse_simplify (insn, testreg);
cselib_process_insn (insn);
}
/* Clean up. */
end_alias_analysis ();
cselib_finish ();
if (cfg_changed)
cleanup_cfg (0);
}
/* Try to simplify a single SET instruction. SET is the set pattern.
INSN is the instruction it came from.
This function only handles one case: if we set a register to a value
which is not a register, we try to find that value in some other register
and change the set into a register copy. */
static int
reload_cse_simplify_set (rtx set, rtx_insn *insn)
{
int did_change = 0;
int dreg;
rtx src;
reg_class_t dclass;
int old_cost;
cselib_val *val;
struct elt_loc_list *l;
enum rtx_code extend_op = UNKNOWN;
bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn));
dreg = true_regnum (SET_DEST (set));
if (dreg < 0)
return 0;
src = SET_SRC (set);
if (side_effects_p (src) || true_regnum (src) >= 0)
return 0;
dclass = REGNO_REG_CLASS (dreg);
/* When replacing a memory with a register, we need to honor assumptions
that combine made wrt the contents of sign bits. We'll do this by
generating an extend instruction instead of a reg->reg copy. Thus
the destination must be a register that we can widen. */
if (MEM_P (src)
&& (extend_op = load_extend_op (GET_MODE (src))) != UNKNOWN
&& !REG_P (SET_DEST (set)))
return 0;
val = cselib_lookup (src, GET_MODE (SET_DEST (set)), 0, VOIDmode);
if (! val)
return 0;
/* If memory loads are cheaper than register copies, don't change them. */
if (MEM_P (src))
old_cost = memory_move_cost (GET_MODE (src), dclass, true);
else if (REG_P (src))
old_cost = register_move_cost (GET_MODE (src),
REGNO_REG_CLASS (REGNO (src)), dclass);
else
old_cost = set_src_cost (src, GET_MODE (SET_DEST (set)), speed);
for (l = val->locs; l; l = l->next)
{
rtx this_rtx = l->loc;
int this_cost;
if (CONSTANT_P (this_rtx) && ! references_value_p (this_rtx, 0))
{
if (extend_op != UNKNOWN)
{
wide_int result;
if (!CONST_SCALAR_INT_P (this_rtx))
continue;
switch (extend_op)
{
case ZERO_EXTEND:
result = wide_int::from (rtx_mode_t (this_rtx,
GET_MODE (src)),
BITS_PER_WORD, UNSIGNED);
break;
case SIGN_EXTEND:
result = wide_int::from (rtx_mode_t (this_rtx,
GET_MODE (src)),
BITS_PER_WORD, SIGNED);
break;
default:
gcc_unreachable ();
}
this_rtx = immed_wide_int_const (result, word_mode);
}
this_cost = set_src_cost (this_rtx, GET_MODE (SET_DEST (set)), speed);
}
else if (REG_P (this_rtx))
{
if (extend_op != UNKNOWN)
{
this_rtx = gen_rtx_fmt_e (extend_op, word_mode, this_rtx);
this_cost = set_src_cost (this_rtx, word_mode, speed);
}
else
this_cost = register_move_cost (GET_MODE (this_rtx),
REGNO_REG_CLASS (REGNO (this_rtx)),
dclass);
}
else
continue;
/* If equal costs, prefer registers over anything else. That
tends to lead to smaller instructions on some machines. */
if (this_cost < old_cost
|| (this_cost == old_cost
&& REG_P (this_rtx)
&& !REG_P (SET_SRC (set))))
{
if (extend_op != UNKNOWN
&& REG_CAN_CHANGE_MODE_P (REGNO (SET_DEST (set)),
GET_MODE (SET_DEST (set)), word_mode))
{
rtx wide_dest = gen_rtx_REG (word_mode, REGNO (SET_DEST (set)));
ORIGINAL_REGNO (wide_dest) = ORIGINAL_REGNO (SET_DEST (set));
validate_change (insn, &SET_DEST (set), wide_dest, 1);
}
validate_unshare_change (insn, &SET_SRC (set), this_rtx, 1);
old_cost = this_cost, did_change = 1;
}
}
return did_change;
}
/* Try to replace operands in INSN with equivalent values that are already
in registers. This can be viewed as optional reloading.
For each non-register operand in the insn, see if any hard regs are
known to be equivalent to that operand. Record the alternatives which
can accept these hard registers. Among all alternatives, select the
ones which are better or equal to the one currently matching, where
"better" is in terms of '?' and '!' constraints. Among the remaining
alternatives, select the one which replaces most operands with
hard registers. */
static int
reload_cse_simplify_operands (rtx_insn *insn, rtx testreg)
{
int i, j;
/* For each operand, all registers that are equivalent to it. */
HARD_REG_SET equiv_regs[MAX_RECOG_OPERANDS];
const char *constraints[MAX_RECOG_OPERANDS];
/* Vector recording how bad an alternative is. */
int *alternative_reject;
/* Vector recording how many registers can be introduced by choosing
this alternative. */
int *alternative_nregs;
/* Array of vectors recording, for each operand and each alternative,
which hard register to substitute, or -1 if the operand should be
left as it is. */
int *op_alt_regno[MAX_RECOG_OPERANDS];
/* Array of alternatives, sorted in order of decreasing desirability. */
int *alternative_order;
extract_constrain_insn (insn);
if (recog_data.n_alternatives == 0 || recog_data.n_operands == 0)
return 0;
alternative_reject = XALLOCAVEC (int, recog_data.n_alternatives);
alternative_nregs = XALLOCAVEC (int, recog_data.n_alternatives);
alternative_order = XALLOCAVEC (int, recog_data.n_alternatives);
memset (alternative_reject, 0, recog_data.n_alternatives * sizeof (int));
memset (alternative_nregs, 0, recog_data.n_alternatives * sizeof (int));
/* For each operand, find out which regs are equivalent. */
for (i = 0; i < recog_data.n_operands; i++)
{
cselib_val *v;
struct elt_loc_list *l;
rtx op;
CLEAR_HARD_REG_SET (equiv_regs[i]);
/* cselib blows up on CODE_LABELs. Trying to fix that doesn't seem
right, so avoid the problem here. Similarly NOTE_INSN_DELETED_LABEL.
Likewise if we have a constant and the insn pattern doesn't tell us
the mode we need. */
if (LABEL_P (recog_data.operand[i])
|| (NOTE_P (recog_data.operand[i])
&& NOTE_KIND (recog_data.operand[i]) == NOTE_INSN_DELETED_LABEL)
|| (CONSTANT_P (recog_data.operand[i])
&& recog_data.operand_mode[i] == VOIDmode))
continue;
op = recog_data.operand[i];
if (MEM_P (op) && load_extend_op (GET_MODE (op)) != UNKNOWN)
{
rtx set = single_set (insn);
/* We might have multiple sets, some of which do implicit
extension. Punt on this for now. */
if (! set)
continue;
/* If the destination is also a MEM or a STRICT_LOW_PART, no
extension applies.
Also, if there is an explicit extension, we don't have to
worry about an implicit one. */
else if (MEM_P (SET_DEST (set))
|| GET_CODE (SET_DEST (set)) == STRICT_LOW_PART
|| GET_CODE (SET_SRC (set)) == ZERO_EXTEND
|| GET_CODE (SET_SRC (set)) == SIGN_EXTEND)
; /* Continue ordinary processing. */
/* If the register cannot change mode to word_mode, it follows that
it cannot have been used in word_mode. */
else if (REG_P (SET_DEST (set))
&& !REG_CAN_CHANGE_MODE_P (REGNO (SET_DEST (set)),
GET_MODE (SET_DEST (set)),
word_mode))
; /* Continue ordinary processing. */
/* If this is a straight load, make the extension explicit. */
else if (REG_P (SET_DEST (set))
&& recog_data.n_operands == 2
&& SET_SRC (set) == op
&& SET_DEST (set) == recog_data.operand[1-i])
{
validate_change (insn, recog_data.operand_loc[i],
gen_rtx_fmt_e (load_extend_op (GET_MODE (op)),
word_mode, op),
1);
validate_change (insn, recog_data.operand_loc[1-i],
gen_rtx_REG (word_mode, REGNO (SET_DEST (set))),
1);
if (! apply_change_group ())
return 0;
return reload_cse_simplify_operands (insn, testreg);
}
else
/* ??? There might be arithmetic operations with memory that are
safe to optimize, but is it worth the trouble? */
continue;
}
if (side_effects_p (op))
continue;
v = cselib_lookup (op, recog_data.operand_mode[i], 0, VOIDmode);
if (! v)
continue;
for (l = v->locs; l; l = l->next)
if (REG_P (l->loc))
SET_HARD_REG_BIT (equiv_regs[i], REGNO (l->loc));
}
alternative_mask preferred = get_preferred_alternatives (insn);
for (i = 0; i < recog_data.n_operands; i++)
{
machine_mode mode;
int regno;
const char *p;
op_alt_regno[i] = XALLOCAVEC (int, recog_data.n_alternatives);
for (j = 0; j < recog_data.n_alternatives; j++)
op_alt_regno[i][j] = -1;
p = constraints[i] = recog_data.constraints[i];
mode = recog_data.operand_mode[i];
/* Add the reject values for each alternative given by the constraints
for this operand. */
j = 0;
while (*p != '\0')
{
char c = *p++;
if (c == ',')
j++;
else if (c == '?')
alternative_reject[j] += 3;
else if (c == '!')
alternative_reject[j] += 300;
}
/* We won't change operands which are already registers. We
also don't want to modify output operands. */
regno = true_regnum (recog_data.operand[i]);
if (regno >= 0
|| constraints[i][0] == '='
|| constraints[i][0] == '+')
continue;
for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
{
enum reg_class rclass = NO_REGS;
if (! TEST_HARD_REG_BIT (equiv_regs[i], regno))
continue;
set_mode_and_regno (testreg, mode, regno);
/* We found a register equal to this operand. Now look for all
alternatives that can accept this register and have not been
assigned a register they can use yet. */
j = 0;
p = constraints[i];
for (;;)
{
char c = *p;
switch (c)
{
case 'g':
rclass = reg_class_subunion[rclass][GENERAL_REGS];
break;
default:
rclass
= (reg_class_subunion
[rclass]
[reg_class_for_constraint (lookup_constraint (p))]);
break;
case ',': case '\0':
/* See if REGNO fits this alternative, and set it up as the
replacement register if we don't have one for this
alternative yet and the operand being replaced is not
a cheap CONST_INT. */
if (op_alt_regno[i][j] == -1
&& TEST_BIT (preferred, j)
&& reg_fits_class_p (testreg, rclass, 0, mode)
&& (!CONST_INT_P (recog_data.operand[i])
|| (set_src_cost (recog_data.operand[i], mode,
optimize_bb_for_speed_p
(BLOCK_FOR_INSN (insn)))
> set_src_cost (testreg, mode,
optimize_bb_for_speed_p
(BLOCK_FOR_INSN (insn))))))
{
alternative_nregs[j]++;
op_alt_regno[i][j] = regno;
}
j++;
rclass = NO_REGS;
break;
}
p += CONSTRAINT_LEN (c, p);
if (c == '\0')
break;
}
}
}
/* Record all alternatives which are better or equal to the currently
matching one in the alternative_order array. */
for (i = j = 0; i < recog_data.n_alternatives; i++)
if (alternative_reject[i] <= alternative_reject[which_alternative])
alternative_order[j++] = i;
recog_data.n_alternatives = j;
/* Sort it. Given a small number of alternatives, a dumb algorithm
won't hurt too much. */
for (i = 0; i < recog_data.n_alternatives - 1; i++)
{
int best = i;
int best_reject = alternative_reject[alternative_order[i]];
int best_nregs = alternative_nregs[alternative_order[i]];
for (j = i + 1; j < recog_data.n_alternatives; j++)
{
int this_reject = alternative_reject[alternative_order[j]];
int this_nregs = alternative_nregs[alternative_order[j]];
if (this_reject < best_reject
|| (this_reject == best_reject && this_nregs > best_nregs))
{
best = j;
best_reject = this_reject;
best_nregs = this_nregs;
}
}
std::swap (alternative_order[best], alternative_order[i]);
}
/* Substitute the operands as determined by op_alt_regno for the best
alternative. */
j = alternative_order[0];
for (i = 0; i < recog_data.n_operands; i++)
{
machine_mode mode = recog_data.operand_mode[i];
if (op_alt_regno[i][j] == -1)
continue;
validate_change (insn, recog_data.operand_loc[i],
gen_rtx_REG (mode, op_alt_regno[i][j]), 1);
}
for (i = recog_data.n_dups - 1; i >= 0; i--)
{
int op = recog_data.dup_num[i];
machine_mode mode = recog_data.operand_mode[op];
if (op_alt_regno[op][j] == -1)
continue;
validate_change (insn, recog_data.dup_loc[i],
gen_rtx_REG (mode, op_alt_regno[op][j]), 1);
}
return apply_change_group ();
}
/* If reload couldn't use reg+reg+offset addressing, try to use reg+reg
addressing now.
This code might also be useful when reload gave up on reg+reg addressing
because of clashes between the return register and INDEX_REG_CLASS. */
/* The maximum number of uses of a register we can keep track of to
replace them with reg+reg addressing. */
#define RELOAD_COMBINE_MAX_USES 16
/* Describes a recorded use of a register. */
struct reg_use
{
/* The insn where a register has been used. */
rtx_insn *insn;
/* Points to the memory reference enclosing the use, if any, NULL_RTX
otherwise. */
rtx containing_mem;
/* Location of the register within INSN. */
rtx *usep;
/* The reverse uid of the insn. */
int ruid;
};
/* If the register is used in some unknown fashion, USE_INDEX is negative.
If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID
indicates where it is first set or clobbered.
Otherwise, USE_INDEX is the index of the last encountered use of the
register (which is first among these we have seen since we scan backwards).
USE_RUID indicates the first encountered, i.e. last, of these uses.
If ALL_OFFSETS_MATCH is true, all encountered uses were inside a PLUS
with a constant offset; OFFSET contains this constant in that case.
STORE_RUID is always meaningful if we only want to use a value in a
register in a different place: it denotes the next insn in the insn
stream (i.e. the last encountered) that sets or clobbers the register.
REAL_STORE_RUID is similar, but clobbers are ignored when updating it.
EXPR is the expression used when storing the register. */
static struct
{
struct reg_use reg_use[RELOAD_COMBINE_MAX_USES];
rtx offset;
int use_index;
int store_ruid;
int real_store_ruid;
int use_ruid;
bool all_offsets_match;
rtx expr;
} reg_state[FIRST_PSEUDO_REGISTER];
/* Reverse linear uid. This is increased in reload_combine while scanning
the instructions from last to first. It is used to set last_label_ruid
and the store_ruid / use_ruid fields in reg_state. */
static int reload_combine_ruid;
/* The RUID of the last label we encountered in reload_combine. */
static int last_label_ruid;
/* The RUID of the last jump we encountered in reload_combine. */
static int last_jump_ruid;
/* The register numbers of the first and last index register. A value of
-1 in LAST_INDEX_REG indicates that we've previously computed these
values and found no suitable index registers. */
static int first_index_reg = -1;
static int last_index_reg;
#define LABEL_LIVE(LABEL) \
(label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno])
/* Subroutine of reload_combine_split_ruids, called to fix up a single
ruid pointed to by *PRUID if it is higher than SPLIT_RUID. */
static inline void
reload_combine_split_one_ruid (int *pruid, int split_ruid)
{
if (*pruid > split_ruid)
(*pruid)++;
}
/* Called when we insert a new insn in a position we've already passed in
the scan. Examine all our state, increasing all ruids that are higher
than SPLIT_RUID by one in order to make room for a new insn. */
static void
reload_combine_split_ruids (int split_ruid)
{
unsigned i;
reload_combine_split_one_ruid (&reload_combine_ruid, split_ruid);
reload_combine_split_one_ruid (&last_label_ruid, split_ruid);
reload_combine_split_one_ruid (&last_jump_ruid, split_ruid);
for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
{
int j, idx = reg_state[i].use_index;
reload_combine_split_one_ruid (®_state[i].use_ruid, split_ruid);
reload_combine_split_one_ruid (®_state[i].store_ruid, split_ruid);
reload_combine_split_one_ruid (®_state[i].real_store_ruid,
split_ruid);
if (idx < 0)
continue;
for (j = idx; j < RELOAD_COMBINE_MAX_USES; j++)
{
reload_combine_split_one_ruid (®_state[i].reg_use[j].ruid,
split_ruid);
}
}
}
/* Called when we are about to rescan a previously encountered insn with
reload_combine_note_use after modifying some part of it. This clears all
information about uses in that particular insn. */
static void
reload_combine_purge_insn_uses (rtx_insn *insn)
{
unsigned i;
for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
{
int j, k, idx = reg_state[i].use_index;
if (idx < 0)
continue;
j = k = RELOAD_COMBINE_MAX_USES;
while (j-- > idx)
{
if (reg_state[i].reg_use[j].insn != insn)
{
k--;
if (k != j)
reg_state[i].reg_use[k] = reg_state[i].reg_use[j];
}
}
reg_state[i].use_index = k;
}
}
/* Called when we need to forget about all uses of REGNO after an insn
which is identified by RUID. */
static void
reload_combine_purge_reg_uses_after_ruid (unsigned regno, int ruid)
{
int j, k, idx = reg_state[regno].use_index;
if (idx < 0)
return;
j = k = RELOAD_COMBINE_MAX_USES;
while (j-- > idx)
{
if (reg_state[regno].reg_use[j].ruid >= ruid)
{
k--;
if (k != j)
reg_state[regno].reg_use[k] = reg_state[regno].reg_use[j];
}
}
reg_state[regno].use_index = k;
}
/* Find the use of REGNO with the ruid that is highest among those
lower than RUID_LIMIT, and return it if it is the only use of this
reg in the insn. Return NULL otherwise. */
static struct reg_use *
reload_combine_closest_single_use (unsigned regno, int ruid_limit)
{
int i, best_ruid = 0;
int use_idx = reg_state[regno].use_index;
struct reg_use *retval;
if (use_idx < 0)
return NULL;
retval = NULL;
for (i = use_idx; i < RELOAD_COMBINE_MAX_USES; i++)
{
struct reg_use *use = reg_state[regno].reg_use + i;
int this_ruid = use->ruid;
if (this_ruid >= ruid_limit)
continue;
if (this_ruid > best_ruid)
{
best_ruid = this_ruid;
retval = use;
}
else if (this_ruid == best_ruid)
retval = NULL;
}
if (last_label_ruid >= best_ruid)
return NULL;
return retval;
}
/* After we've moved an add insn, fix up any debug insns that occur
between the old location of the add and the new location. REG is
the destination register of the add insn; REPLACEMENT is the
SET_SRC of the add. FROM and TO specify the range in which we
should make this change on debug insns. */
static void
fixup_debug_insns (rtx reg, rtx replacement, rtx_insn *from, rtx_insn *to)
{
rtx_insn *insn;
for (insn = from; insn != to; insn = NEXT_INSN (insn))
{
rtx t;
if (!DEBUG_BIND_INSN_P (insn))
continue;
t = INSN_VAR_LOCATION_LOC (insn);
t = simplify_replace_rtx (t, reg, replacement);
validate_change (insn, &INSN_VAR_LOCATION_LOC (insn), t, 0);
}
}
/* Subroutine of reload_combine_recognize_const_pattern. Try to replace REG
with SRC in the insn described by USE, taking costs into account. Return
true if we made the replacement. */
static bool
try_replace_in_use (struct reg_use *use, rtx reg, rtx src)
{
rtx_insn *use_insn = use->insn;
rtx mem = use->containing_mem;
bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (use_insn));
if (mem != NULL_RTX)
{
addr_space_t as = MEM_ADDR_SPACE (mem);
rtx oldaddr = XEXP (mem, 0);
rtx newaddr = NULL_RTX;
int old_cost = address_cost (oldaddr, GET_MODE (mem), as, speed);
int new_cost;
newaddr = simplify_replace_rtx (oldaddr, reg, src);
if (memory_address_addr_space_p (GET_MODE (mem), newaddr, as))
{
XEXP (mem, 0) = newaddr;
new_cost = address_cost (newaddr, GET_MODE (mem), as, speed);
XEXP (mem, 0) = oldaddr;
if (new_cost <= old_cost
&& validate_change (use_insn,
&XEXP (mem, 0), newaddr, 0))
return true;
}
}
else
{
rtx new_set = single_set (use_insn);
if (new_set
&& REG_P (SET_DEST (new_set))
&& GET_CODE (SET_SRC (new_set)) == PLUS
&& REG_P (XEXP (SET_SRC (new_set), 0))
&& CONSTANT_P (XEXP (SET_SRC (new_set), 1)))
{
rtx new_src;
machine_mode mode = GET_MODE (SET_DEST (new_set));
int old_cost = set_src_cost (SET_SRC (new_set), mode, speed);
gcc_assert (rtx_equal_p (XEXP (SET_SRC (new_set), 0), reg));
new_src = simplify_replace_rtx (SET_SRC (new_set), reg, src);
if (set_src_cost (new_src, mode, speed) <= old_cost
&& validate_change (use_insn, &SET_SRC (new_set),
new_src, 0))
return true;
}
}
return false;
}
/* Called by reload_combine when scanning INSN. This function tries to detect
patterns where a constant is added to a register, and the result is used
in an address.
Return true if no further processing is needed on INSN; false if it wasn't
recognized and should be handled normally. */
static bool
reload_combine_recognize_const_pattern (rtx_insn *insn)
{
int from_ruid = reload_combine_ruid;
rtx set, pat, reg, src, addreg;
unsigned int regno;
struct reg_use *use;
bool must_move_add;
rtx_insn *add_moved_after_insn = NULL;
int add_moved_after_ruid = 0;
int clobbered_regno = -1;
set = single_set (insn);
if (set == NULL_RTX)
return false;
reg = SET_DEST (set);
src = SET_SRC (set);
if (!REG_P (reg)
|| REG_NREGS (reg) != 1
|| GET_MODE (reg) != Pmode
|| reg == stack_pointer_rtx)
return false;
regno = REGNO (reg);
/* We look for a REG1 = REG2 + CONSTANT insn, followed by either
uses of REG1 inside an address, or inside another add insn. If
possible and profitable, merge the addition into subsequent
uses. */
if (GET_CODE (src) != PLUS
|| !REG_P (XEXP (src, 0))
|| !CONSTANT_P (XEXP (src, 1)))
return false;
addreg = XEXP (src, 0);
must_move_add = rtx_equal_p (reg, addreg);
pat = PATTERN (insn);
if (must_move_add && set != pat)
{
/* We have to be careful when moving the add; apart from the
single_set there may also be clobbers. Recognize one special
case, that of one clobber alongside the set (likely a clobber
of the CC register). */
gcc_assert (GET_CODE (PATTERN (insn)) == PARALLEL);
if (XVECLEN (pat, 0) != 2 || XVECEXP (pat, 0, 0) != set
|| GET_CODE (XVECEXP (pat, 0, 1)) != CLOBBER
|| !REG_P (XEXP (XVECEXP (pat, 0, 1), 0)))
return false;
clobbered_regno = REGNO (XEXP (XVECEXP (pat, 0, 1), 0));
}
do
{
use = reload_combine_closest_single_use (regno, from_ruid);
if (use)
/* Start the search for the next use from here. */
from_ruid = use->ruid;
if (use && GET_MODE (*use->usep) == Pmode)
{
bool delete_add = false;
rtx_insn *use_insn = use->insn;
int use_ruid = use->ruid;
/* Avoid moving the add insn past a jump. */
if (must_move_add && use_ruid <= last_jump_ruid)
break;
/* If the add clobbers another hard reg in parallel, don't move
it past a real set of this hard reg. */
if (must_move_add && clobbered_regno >= 0
&& reg_state[clobbered_regno].real_store_ruid >= use_ruid)
break;
/* Do not separate cc0 setter and cc0 user on HAVE_cc0 targets. */
if (HAVE_cc0 && must_move_add && sets_cc0_p (PATTERN (use_insn)))
break;
gcc_assert (reg_state[regno].store_ruid <= use_ruid);
/* Avoid moving a use of ADDREG past a point where it is stored. */
if (reg_state[REGNO (addreg)].store_ruid > use_ruid)
break;
/* We also must not move the addition past an insn that sets
the same register, unless we can combine two add insns. */