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dsl_hal_support.c
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/*******************************************************************************
* FILE PURPOSE: DSL Driver API functions for Sangam
*********************************************************************************
* FILE NAME: dsl_hal_support.c
*
* DESCRIPTION:
* Contains DSL HAL APIs for Modem Control
*
*
* (C) Copyright 2001-02, Texas Instruments, Inc.
* History
* Date Version Notes
* 06Feb03 0.00.00 RamP Created
* 21Mar03 0.00.01 RamP Inserted byteswap functions
* 07Apr03 0.00.02 RamP Implemented new error reporting scheme
* Changed Commenting to C style only
* 12Apr03 0.00.03 RamP Added function to set Interrupt Bit
* Masks for bitfield & Mailboxes
* 14Apr03 0.00.04 RamP Added function to process modem state
* bit fields; renamed REG32 macros
* Changed interrupt bit field settings
* 15Apr03 0.00.05 RamP Fixed exit condition on dslShutdown
* 21Apr03 0.01.00 RamP Fixed dslShutdown function & changed
* loop counter for overlay byteswaps
* (Alpha) Added cache writeback for overlays
* Added function acknowledgeInterrupt
* 22Apr03 0.01.01 RamP Moved acknowledgeInterrupt into api
* 24Apr03 0.01.02 RamP Added function to compare crc32 with
* pre-computed value as a recovery
* scheme for corrupt overlay pages
* 28Apr03 0.01.03 RamP Fixed a parameter in crc32 fxn call
* 05May03 0.01.04 RamP Fixed Message structure access in
* writeHostMailbox function
* 14May03 0.01.05 RamP Lookup to netService of dsp version
* (alpha ++) to determine pots/isdn service
* 21May03 0.01.06 RamP Added support for CO profiles
* 29May03 0.01.07 RamP Added critical section tabs for block
* read/write operations
* Added functions to reload overlay pages
* and CO Profiles
* 04Jun03 0.01.08 RamP Added state transition timing counters
* 06Jun03 0.01.09 RamP Added Interrupt source parsing function
* Interrupt masking for heartbeat added
* 09Jun03 0.01.10 RamP Modified modem state bit field processing
* for structure changes in ITIDSLHW
* fixed problem in free memory for CO prof
* 18Jul03 0.01.11 RamP Optimized free memory for CO profiles &
* overlay pages in the supporting APIs
* 28Jul03 0.02.00 RamP Modified the process bitfield functn
* for LED & Application State report
* 21Aug03 0.03.00 RamP Added logic to allocate & communicate
* memory for constellation buffer display
* 29Sep03 0.03.01 RamP Added API switch calls to advcfg module
* to abstract them from the API module
* 12Oct03 0.03.02 RamP Added API to gather ADSL2 Messages
* 14Oct03 0.03.03 RamP Added function to read CMsgsRA
* 23Oct03 0.03.04 RamP Changed train history index to circular
* buffer upon rollover
* 29Oct03 0.03.05 RamP Added Adsl2 Delt Message Parsing
* 12Nov03 0.03.06 RamP Fixed endianness issues with
* Constellation Display
* 14Nov03 0.03.07 RamP Added function to gather CRates1/RRates1
* before they get overwritten by CRatesRA
* 19Nov03 0.03.08 JohnP Revised dslhal_support_aocBitSwapProcessing to
* prevent duplicate ATU-R bitswaps going to ACT
* 24Nov03 0.03.09 RamP Implemented detailed State Tracking through
* Modem State bit fields for ADSL/2
* 12Dec03 0.03.10 RamP Tokenized advanced configuration code
* 12Dec03 0.03.11 RamP Added state reset upon IDLE
* 19Dec03 0.03.12 RamP Added static adsl2 byteswap function for
* handling pointer to pointer cases
* Changed adsl2 messages to correct pointer to
* pointer dereferencing problems in some OS
* 26Dec03 0.03.13 RamP Setting Current Address for Constellation
* buffer in addition to start address
* Added additional check to overlay page malloc
* 02Mar04 0.03.14 RamP Changed overlay page number constant to
* refer to the host interface constant
* 20Apr04 0.03.15 RamP decoupled overlay page check from host
* interface, modified Profiles to support
* multiple profile sections, modified reload
* training info functions
* 27Apr04 0.03.16 RamP Fixed out of bounds situation with train
* state indices; removed return based on
* MAXSECTIONS, replaced by warning
* 29Apr04 0.03.17 RamP Added code to process ADSL2+ DELT messages
* Added function to determine dsNumTones
* Added switch case for missing ADSL2 DELT msgs
* 04May04 0.03.18 RamP Removed bState setting in Idle processing fxn
* 14May04 0.03.19 RamP Moved SNR fetch function to this module
* 30Jun04 0.04.00 RamP Changed address translation function to support
* Ohio chipset
* 14Jul04 0.03.20 RamP Changed DSP unreset function for increased DSP
* processor speed & buck voltage
* 25Aug04 0.03.21 RamP Removed changes for buck voltage & processor
* speed; to be done with ATM driver & Firmware
* 26Aug04 0.03.22 Brian Made changes to support switching DSP
* frequency to 250Mhz
* 20Aug04 0.03.23 RamP Fixed a bug with block write for 16-bit aligned
* addresses where source pointer was corrupted
* 27Jan05 0.04.00 CPH Added support for Ohio250, code cleanup
* 02Feb05 0.04.01 CPH Pull dev_host_interface.h out from dsl_hal_register.h
* 02Mar05 0.04.02 CPH Add DSL phy ENV feature control support
* 13Jun05 0.04.03 CPH Change download debug msg level to 7. (was 5)
* 14June05 0.05.00 CPH Added dslhal_support_getTrainedModeEx(), change AnxB
* default training mode to MultiMode.
* 20June05 0.05.01 CPH Fixed memory read crash bug in dslhal_support_blockRead()
* Claen up & optimize
* 21June05 0.05.02 CPH CQ9717 Fixed scratch memory odd bytes not swapped problem.
* 29Jun05 0.04.03 SAN Added logic to flush the memory during the
* dsp firmware download and increased the delay
* from 0x5000 to 0x8000.
* 30Jun05 0.04.04 AV Removed the flushing of the cache as in some
* cases it can cause a crash. Added a retry
* mechanisim to deal with the download jitter.
* 26Jul05 0.05.00 CPH - Added dslhal_support_getTrainedMode(),
* dslhal_support_readInternalOffset(),
* dslhal_support_readOffset(),
* dslhal_support_getMaxUsTones()
* - Rename dslhal_support_getNumTones() to dslhal_support_getMaxDsTones()
* - Rename dsNumTones to max_ds_tones in various places.
* 01Aug05 0.06.00 CPH Fixed dslhal_support_blockRead() problem when the read length is
* less than 4 bytes and not 32bit aligned.
* 05Sept05 0.07.00 CPH Remove initialization for SNRpsds_p, QLNpsds_p & HLOGpsds_p in
* dslhal_support_hostDspCodedownload().
* 06Oct05 0.08.00 CPH Comment out redundent code in dslhal_support_writeHostMailbox()
* which could cause crash.
* 7 Oct05 0.08.00 AV/CPH Changed dprintf to dgprintf for code size reduction.
* 31Oct05 0.10.00 CPH CQ10020: Fixed non-aligned dest in dslhal_support_blockWrite() with less than 4
* bytes aligned-word causes CG5.1 generated datapump code crash problem.
* 04Nov05 0.11.00 CPH Fixed T1413 mode got Zero DS/US rate when DSL_BIT_TMODE is set.
* 03Feb06 0.00.36 CPH CQ10280: Add extended PHY feature bit support.
// UR8_MERGE_START CQ10386 PeterHou
* 15Mar06 0.12.00 CPH CQ10386: Add SNR format comment for dslhal_support_gatherSnrPerBin().
// UR8_MERGE_END CQ10386
// UR8_MERGE_START CQ10774 Ram
* 19Jul06 0.13.00 Ram CQ10774: Added EOCAOC Mask to the list of disabled Mailbox Interrupts
* from the DSP.
* Also changed assignment into an |= to ensure that no DSP defaults for
* oamFeature are overriden
// UR8_MERGE_END CQ10774 Ram
* UR8_MERGE_START_END CQ11922 Tim
* 04Sep07 0.14.00 Tim CQ11922: Added support for new scratchram for INP NDR tables
*******************************************************************************/
#include <dev_host_interface.h>
#include <dsl_hal_register.h>
#include <dsl_hal_support.h>
#define NUM_READ_RETRIES 3
static unsigned int dslhal_support_adsl2ByteSwap32(unsigned int in32Bits);
static unsigned int dslhal_support_findProfileIndex(tidsl_t *ptidsl, unsigned int profileAddr);
//dsl phy ENV feature control
unsigned int _dsl_Feature_0;
unsigned int _dsl_Feature_1;
unsigned int _dsl_Feature_0_defined;
unsigned int _dsl_Feature_1_defined;
//CQ10280
unsigned int _dsl_PhyControl_0;
unsigned int _dsl_PhyControl_1;
unsigned int _dsl_PhyControl_0_defined;
unsigned int _dsl_PhyControl_1_defined;
unsigned int _DEBUG_HALT_=0;
/******************************************************************************************
* FUNCTION NAME: dslhal_support_readInternalOffset
*
*******************************************************************************************
* DESCRIPTION: This function return endian converted 32 bit values from
* Internal Host-DSP Interface based on the offste array passed in.
* This is mainly used to get first level address from Internal
* Host-DSP Interface (Internal used only)
*
* INPUT: PITIDSLHW_T *ptidsl
* int offsetnum: # entries in offset[]
* int *offset
*
* RETURN: endian converted 32 bit value for the specified entry. (32 bit)
*
*****************************************************************************************/
#define DEV_HOST_DSP_OAM_INTERNAL_POINTER_LOCATION 0x80000004
unsigned int dslhal_support_readInternalOffset(tidsl_t *ptidsl, int offsetnum, int *offset)
{
unsigned int dslReg;
void *pInternal;
dslhal_support_blockRead((char *)DEV_HOST_DSP_OAM_INTERNAL_POINTER_LOCATION,
&pInternal, sizeof(unsigned int));
pInternal=(void *) dslhal_support_byteSwap32((unsigned int) pInternal);
dslhal_api_dspInterfaceRead(ptidsl,(unsigned int) pInternal, offsetnum,
(unsigned int *)offset, (unsigned char *)&dslReg, 4);
return dslhal_support_byteSwap32(dslReg);
}
/******************************************************************************************
* FUNCTION NAME: dslhal_support_readOffset
*
*******************************************************************************************
* DESCRIPTION: This function return endian converted 32 bit values from
* Host-DSP Interface based on the offste array passed in.
* This is mainly used to get first level address from
* Host-DSP Interface (Internal used only)
*
* INPUT: PITIDSLHW_T *ptidsl
* int offsetnum: # entries in offset[]
* int *offset
*
* RETURN: endian converted address for the specified entry. (32 bit)
*
*****************************************************************************************/
unsigned int dslhal_support_readOffset(tidsl_t *ptidsl, int offsetnum, int *offset)
{
unsigned int dslReg;
dslhal_api_dspInterfaceRead(ptidsl,(unsigned int)ptidsl->pmainAddr, offsetnum,
(unsigned int *)offset, (unsigned char *)&dslReg, 4);
return dslhal_support_byteSwap32(dslReg);
}
//
//get DSP Address from offset array. (internal use only)
// type: 0: main pointers Table
// 1: Internal pointers Table
//
unsigned int dslhal_support_addrFromOffset(tidsl_t *ptidsl, int offsetnum, int *offsets, int type)
{
int rc=0, off=0;
unsigned int prevAddr,currAddr;
unsigned int pInternal;
if (type==0) // main pointers Table
prevAddr = (unsigned int) ptidsl->pmainAddr;
else { // internal pointerss Table
dslhal_support_blockRead((char *)DEV_HOST_DSP_OAM_INTERNAL_POINTER_LOCATION,
&pInternal, sizeof(unsigned int));
prevAddr = dslhal_support_byteSwap32(pInternal);
}
currAddr = prevAddr;
for(off=0;off<offsetnum-1;off++)
{
rc += dslhal_support_blockRead((PVOID)(prevAddr+(4*offsets[off])), &currAddr,4);
currAddr = dslhal_support_byteSwap32(currAddr);
prevAddr = currAddr;
// dgprintf(5,"Curr Addr = 0x%x Current Level: %d \n",currAddr,off);
}
currAddr += offsets[offsetnum-1]*4;
return currAddr;
}
unsigned int dslhal_support_writeFromOffset(tidsl_t *ptidsl, int offsetnum, int *offset, unsigned int data, int type)
{
unsigned int dspAddr;
int rc=0;
dgprintf(4, "dslhal_support_writeFromOffset\n");
dspAddr = dslhal_support_addrFromOffset(ptidsl, offsetnum, offset, type);
rc=dslhal_support_hostDspAddressTranslate((unsigned int)dspAddr);
if(rc== DSLHAL_ERROR_ADDRESS_TRANSLATE)
{
dgprintf(1, "dslhal_support_hostDspAddressTranslate failed\n");
return DSLHAL_ERROR_ADDRESS_TRANSLATE;
}
DSLHAL_REG32(rc) = data; // write
return DSLHAL_ERROR_NO_ERRORS;
}
/******************************************************************************************
* FUNCTION NAME: dslhal_support_getTrainedMode
*
*******************************************************************************************
* DESCRIPTION: This function return the current 32 trained mode.
* Internally called dslhal_support_getTrainedModeEx.
*
* INPUT: PITIDSLHW_T *ptidsl
*
* RETURN: converted extended TrainMode. (32 bit)
* If the TIOIDINFO.useBitField is not set then the returned mode is the old (ordinal) mode.
* If the TIOIDINFO.useBitField is set, then the returned mode is the bitfield mode.
*****************************************************************************************/
unsigned int dslhal_support_getTrainedMode (tidsl_t *ptidsl)
{
int offset[]={3};
DEV_HOST_dspWrNegoParaDef_t *dspWrNego_p;
unsigned short annex_selected, psd_mask_qualifier;
unsigned char trainedMode8;
unsigned int TrainedModeEx;
dgprintf(4, "dslhal_support_getTrainedMode\n");
dspWrNego_p = (DEV_HOST_dspWrNegoParaDef_t *) dslhal_support_readOffset(ptidsl, 1, offset);
// read Trained mode, don't need to swap since it's only 'char' (8 bit)
dslhal_support_blockRead((void*) &dspWrNego_p->trainMode, &trainedMode8, sizeof(trainedMode8));
// read annex_selected
dslhal_support_blockRead((void*) &dspWrNego_p->annex_selected,
&annex_selected, sizeof(dspWrNego_p->annex_selected));
// read psd_mask_qualifier
dslhal_support_blockRead((void*) &dspWrNego_p->psd_mask_qualifier,
&psd_mask_qualifier, sizeof(dspWrNego_p->psd_mask_qualifier));
ptidsl->AppData.annex_selected = dslhal_support_byteSwap16(annex_selected);
ptidsl->AppData.psd_mask_qualifier= dslhal_support_byteSwap16(psd_mask_qualifier);
dgprintf(4," trainMode8=%02x, annex_selected=%04x, psd_mask_qualifier\n",
trainedMode8, ptidsl->AppData.annex_selected, ptidsl->AppData.psd_mask_qualifier);
TrainedModeEx = dslhal_support_getTrainedModeEx(trainedMode8, ptidsl->AppData.annex_selected);
if(!ptidsl->AppData.useBitField)
{
// override
if (trainedMode8 == T1413_MODE)
TrainedModeEx = DSLTRAIN_T1413_MODE;
else if (trainedMode8 == GDMT_MODE)
TrainedModeEx = DSLTRAIN_GDMT_MODE;
}
ptidsl->AppData.TrainedMode= TrainedModeEx;
return TrainedModeEx;
}
/******************************************************************************************
* FUNCTION NAME: dslhal_support_getTrainedModeEx
*
*******************************************************************************************
* DESCRIPTION: This function construct TrainModeEx(32 bit trainmode) from
* trainmode (8 bit) and annex_selected.
* This function is used to support AnnexB/AnnexM where it has extended definition
* trainModeEx (32 bit).
*
* INPUT: trainMode (8 bit), annex_selected
*
* RETURN: converted extended TrainMode. (32 bit)
*
*****************************************************************************************/
unsigned int dslhal_support_getTrainedModeEx (unsigned int trainMode8, unsigned int annex_selected)
{
// construct TrainedModeEx from trainMode and annex_selected
unsigned int TrainedModeEx= trainMode8;
dgprintf(4, "dslhal_support_getTrainedModeEx\n");
switch (annex_selected) {
case ANNEXI:
if (trainMode8 & ADSL2_MODE)
TrainedModeEx = ADSL2_ANNEX_I;
else if (trainMode8 & ADSL2PLUS_MODE)
TrainedModeEx = ADSL2PLUS_ANNEX_I;
break;
case ANNEXJ:
if (trainMode8 & ADSL2_MODE)
TrainedModeEx = ADSL2_ANNEX_J;
else if (trainMode8 & ADSL2PLUS_MODE)
TrainedModeEx = ADSL2PLUS_ANNEX_J;
break;
case ANNEXM:
if (trainMode8 & ADSL2_MODE)
TrainedModeEx = ADSL2_ANNEX_M;
else if (trainMode8 & ADSL2PLUS_MODE)
TrainedModeEx = ADSL2PLUS_ANNEX_M;
break;
case ANNEXA:
case ANNEXB:
case ANNEXL:
default: // same as trainMode8
break;
}; // switch
TrainedModeEx |= (trainMode8 & DELT_ENABLE); // preserve DELT bit
dgprintf(4, "trainMode=%02x, annex_selected=%04x -> TrainModeEx=%04x\n",
trainMode8, annex_selected, TrainedModeEx);
dgprintf(4, "dslhal_support_getTrainedModeEx Done\n");
return TrainedModeEx;
}
/******************************************************************************************
* FUNCTION NAME: dslhal_support_unresetDslSubsystem
*
*******************************************************************************************
* DESCRIPTION: This function unreset Dsl Subsystem
*
* INPUT: None
*
* RETURN: 0 if Pass; 1 if Fail
*
*****************************************************************************************/
int dslhal_support_unresetDslSubsystem(void)
{
unsigned int clock_pllm=0;
unsigned int chip_id;
int rc;
chip_id = DSLHAL_REG32(REG_CVR) & 0xFFFF;
switch(chip_id)
{
case CHIP_AR7: /* Sangam Chip */
dgprintf(5, "Start programming PLL for Sangam chip\n");
/*
* In Sangam, MIPS_PLL Multiplication factor is REG_MIPS_PLLM[15:12]
* check PLLM to determine desired dsp clock at 200 or 250Mhz.
* This value was set in dslhal_api_boostDspFrequency().
* For this reason, this code need to be running after
* dslhal_api_boostDspFrequency() has been executed
*/
clock_pllm = (DSLHAL_REG32(REG_MIPS_PLLM) >> 12) & 0x0F;
dgprintf(5, "clock_ ID = 0x%08x\n", clock_pllm);
if ((clock_pllm < 7) || (clock_pllm > 9))
{
dgprintf(4," dslhal_support_unresetDslSubsystem()\n");
/* Put ADSLSS in to reset */
DSLHAL_REG32(REG_VSERCLKSELR) = 0x1;
shim_osClockWait(64);
dgprintf(5,"Selected APLL Reg \n");
DSLHAL_REG32(REG_MIPS_PLLM) = 0x4;
shim_osClockWait(64);
dgprintf(5,"Enable Analog PLL \n");
DSLHAL_REG32(REG_MIPS_PLLM) = 0x77fe; /* set default to 200MHz */
shim_osClockWait(64);
dgprintf(5,"Set PLL for DSP\n");
dgprintf(5, "Run DSP at 200Mhz\n");
}
else
{
dgprintf(5, "Run DSP at the preset freq\n");
}
break;
case CHIP_AR7O_250_212:
case CHIP_AR7O_212: /* Ohio Chip */
/*
* Comment out the following code because:
* - The setting for various clock mode (eg. 1:1 sync mode) is different.
* - Change setting of these registers in DSLHAL might be too late for other
* peripherials that relys on the setting based on bootloader setting.
* =>These setting should've been done in bootLoader
*/
#if 0
dgprintf(5, "Start programming PLL for Ohio chip\n");
DSLHAL_REG32(REG_MIPS_PLLCSR) = 0;
DSLHAL_REG32(REG_MIPS_PREDIV) = DIVEN | (0 & 0x1F);
DSLHAL_REG32(REG_MIPS_PLLM) = 0x00000005;
shim_osClockWait(64);
while (DSLHAL_REG32(REG_MIPS_PLLSTAT) & GOSTAT)
dgprintf(5, "Wait for GOSTAT in PLL STAT to go to 0 -- Step 1\n");
DSLHAL_REG32(REG_MIPS_POSTDIV) = DIVEN | (0 & 0x1F);
DSLHAL_REG32(REG_MIPS_PLLCMDEN) = GOSETEN;
DSLHAL_REG32(REG_MIPS_PLLCMD) = GOSET;
while (DSLHAL_REG32(REG_MIPS_PLLSTAT) & GOSTAT)
dgprintf(5, "Wait for GOSTAT in PLL STAT to go to 0 -- Step 2\n");
DSLHAL_REG32(REG_MIPS_PLLCSR) |= PLLEN;
#endif
break;
default:
return(DSLHAL_ERROR_UNRESET_ADSLSS);
}
/* DSLHAL_REG32(0xa8611600) = 0x007f1bdf;*/
DSLHAL_REG32(REG_PRCR) |= PRCR_ADSLSS;
shim_osClockWait(64);
dgprintf(5,"Brought ADSLSS out of Reset \n");
DSLHAL_REG32(REG_GPIOENR) &= ~(BIT20|BIT21|BIT22|BIT23|BIT24|BIT25);
shim_osClockWait(64);
dgprintf(5,"Configured GPIO 20-25 for McBSP \n");
/* DSLHAL_REG32(0xa8611a04) = 0x00000001;
shim_osClockWait(64); */
/*
* The following code is used to boost CODEC voltage for Sangam250 by setting
* Buck Trim Bits in CTRL2. For Ohio250, the setting of Buck Trim Bits need
* to be set in datapump code because each reset of CODEC will clean these
* Buck Trim Bits.
* For Ohio(212&250), the following code will be skipped.
*/
if ((chip_id == CHIP_AR7) && (clock_pllm== 9))
{
rc = dslhal_support_hostDspAddressTranslate((unsigned int)0x02040010);
if (rc== DSLHAL_ERROR_ADDRESS_TRANSLATE)
{
dgprintf(1, "dslhal_support_hostDspAddressTranslate failed\n");
return DSLHAL_ERROR_ADDRESS_TRANSLATE;
}
DSLHAL_REG32(rc) |= 0x0000f000; /* set Buck Trim Bits in CTRL2 */
shim_osClockWait(64);
dgprintf(5,"Set Buck Voltage for DSP\n");
dgprintf(6,"Current Contents of PRCR: 0x%x\n",(unsigned int)DSLHAL_REG32(REG_PRCR));
}
dgprintf(4," dslhal_support_unresetDslSubsystem done\n");
return DSLHAL_ERROR_NO_ERRORS;
}
/******************************************************************************************
* FUNCTION NAME: dslhal_support_resetDslSubsystem
*
*******************************************************************************************
* DESCRIPTION: This function unreset Dsl Subsystem
*
* INPUT: None
*
* RETURN: 0 if Pass; 1 if Fail
*
*****************************************************************************************/
int dslhal_support_resetDslSubsystem(void)
{
dgprintf(4, "dslhal_support_resetDslSubsystem \n");
/* Put ADSLSS into reset */
DSLHAL_REG32(REG_PRCR) &= ~PRCR_ADSLSS;
shim_osClockWait(64);
/* DSLHAL_REG32(0xa8611a04) = 0x00000000;
shim_osClockWait(64); */
dgprintf(4, "dslhal_support_resetDslSubsystem Done \n");
return DSLHAL_ERROR_NO_ERRORS;
}
/******************************************************************************************
* FUNCTION NAME: dslhal_support_unresetDsp()
*
*******************************************************************************************
* DESCRIPTION: This fuction takes ax5 daugter board out of reset.
*
* INPUT: None
*
* RETURN: 0 --successful.
* 1 --failed
*
*****************************************************************************************/
int dslhal_support_unresetDsp(void)
{
#ifdef PRE_SILICON
/* unsigned char value; */
rc=dslhal_support_hostDspAddressTranslate((unsigned int)DEV_MDMA0_SRC_ADDR);
if(rc==DSLHAL_ERROR_ADDRESS_TRANSLATE)
{
dgprintf(1, "dslhal_support_hostDspAddressTranslate failed\n");
return DSLHAL_ERROR_ADDRESS_TRANSLATE;
}
dgprintf(5,"MDMA SRC: %08x\n", rc);
DSLHAL_REG32(rc) = 0x80000001;
rc=dslhal_support_hostDspAddressTranslate((unsigned int)DEV_MDMA0_DST_ADDR);
if(rc==DSLHAL_ERROR_ADDRESS_TRANSLATE)
{
dgprintf(1, "dslhal_support_hostDspAddressTranslate failed\n");
return DSLHAL_ERROR_ADDRESS_TRANSLATE;
}
dgprintf(5,"MDMA DST: %08x\n", rc);
DSLHAL_REG32(rc) = 0x02090001;
rc=dslhal_support_hostDspAddressTranslate((unsigned int)DEV_MDMA0_CTL_ADDR);
if(rc== DSLHAL_ERROR_ADDRESS_TRANSLATE)
{
dgprintf(1, "dslhal_support_hostDspAddressTranslate failed\n");
return DSLHAL_ERROR_ADDRESS_TRANSLATE;
}
dgprintf(5,"MDMA CTL: %08x\n", rc);
DSLHAL_REG32(rc) = (DEV_MDMA_START | DEV_MDMA_DST_INC | DEV_MDMA_SRC_INC |
DEV_MDMA_BURST1 | (1 << DEV_MDMA_LEN_SHF));
/* statusMask = 0x00000010;*/
#else
dgprintf(4, "dslhal_support_unresetDsp()\n");
/* Bring the DSP core out of reset */
/* DSLHAL_REG32(0xa8611600) = 0x00ff1bdf; */
DSLHAL_REG32(REG_PRCR) |= PRCR_DSP;
// shim_osClockWait(64);
dgprintf(5,"Brought DSP out of Reset \n");
/* DSLHAL_REG32(0xa8611a0c) = 0x00000007;
shim_osClockWait(64); */
#endif
dgprintf(4, "dslhal_support_unresetDsp() done\n");
return DSLHAL_ERROR_NO_ERRORS;
}
/******************************************************************************************
* FUNCTION NAME: dslhal_support_resetDsp()
*
*******************************************************************************************
* DESCRIPTION: This fuction takes ax5 daugter board into reset.
*
* INPUT: None
*
* RETURN: 0 --successful.
* 1 --failed
*
*****************************************************************************************/
int dslhal_support_resetDsp(void)
{
dgprintf(4, "dslhal_support_resetDsp \n");
/* Put ADSLSS into reset */
DSLHAL_REG32(REG_PRCR) &= ~PRCR_DSP;
shim_osClockWait(64);
dgprintf(4, "dslhal_support_resetDsp Done \n");
return DSLHAL_ERROR_NO_ERRORS;
}
/********************************************************************************************
* FUNCTION NAME: dslhal_support_setDsp250MHzTrigger(void)
*
*********************************************************************************************
* DESCRIPTION:
* Set the trigger to run DSP at 250Mhz.
*
* Input: none
*
* Return: >=0, success
* -1, failure
*
*
********************************************************************************************/
int dslhal_support_setDsp250MHzTrigger(tidsl_t *ptidsl)
{
DEV_HOST_oamWrNegoParaDef_t NegoParm;
DEV_HOST_dspOamSharedInterface_t dspOamSharedInterface, *pdspOamSharedInterface;
int rc;
pdspOamSharedInterface = (DEV_HOST_dspOamSharedInterface_t *)(ptidsl->pmainAddr);
/* get the pointer to DSP-OAM Shared Interface */
rc = dslhal_support_blockRead(pdspOamSharedInterface, &dspOamSharedInterface,
sizeof(DEV_HOST_dspOamSharedInterface_t));
if (rc)
{
return DSLHAL_ERROR_BLOCK_READ;
}
dspOamSharedInterface.oamWriteNegoParams_p = (DEV_HOST_oamWrNegoParaDef_t *)dslhal_support_byteSwap32((unsigned int)dspOamSharedInterface.oamWriteNegoParams_p);
rc = dslhal_support_blockRead((PVOID)dspOamSharedInterface.oamWriteNegoParams_p,&NegoParm, sizeof(DEV_HOST_oamWrNegoParaDef_t));
if (rc)
{
dgprintf(5, "dslhal_support_blockRead failed\n");
return DSLHAL_ERROR_BLOCK_READ;
}
NegoParm.mhzFlag = 1;
rc = dslhal_support_blockWrite(&NegoParm,
(PVOID)dspOamSharedInterface.oamWriteNegoParams_p,
sizeof(DEV_HOST_oamWrNegoParaDef_t));
if(rc)
{
dgprintf(5, "dslhal_support_blockRead failed\n");
return DSLHAL_ERROR_BLOCK_WRITE;
}
return DSLHAL_ERROR_NO_ERRORS;
}
/********************************************************************************************
* FUNCTION NAME: dslhal_support_hostDspAddressTranslate()
*
*********************************************************************************************
* DESCRIPTION:
* Maps ax5 daugter card dsp memory address to avalanche memory space
*
* Input: unsigned int addr, dsp memory address.
*
* Return: >=0, unsigned int, mapped Avalanche address(VBUS address).
* -1, mapping failed
*
*
********************************************************************************************/
/* static unsigned int bbifmap0,bbifmap1; */
unsigned int dslhal_support_hostDspAddressTranslate( unsigned int addr )
{
unsigned int addrMap;
unsigned int chipID=0x05;
/* This function should just be used to move the memory window of the ADSLSS */
dgprintf(6, "dslhal_support_hostDspAddressTranslate()\n");
chipID = DSLHAL_REG32(REG_CVR) & 0xFFFF;
dgprintf(6, "Chip Version %x\n",chipID);
/* select vbus to xbus memory */
/* addrMap = addr & 0xff000000; */
addrMap = addr & ADSLSSADRMASK;
dgprintf(6, "dslhal_support_hostDspAddressTranslate() done\n");
if ( ((chipID == CHIP_AR7O_212) ||(chipID == CHIP_AR7O_250_212))
&&((addrMap == DSP_PMEM_MASK)||(addrMap == DSP_DMEM_MASK)))
{
switch(addrMap)
{
case DSP_PMEM_MASK:
#ifdef PRE_SILICON
return(ADSLSS2_BASE | (~ADSLSSADRMASK & addr)+ 0x00000100);
#else
return(ADSLSS2_BASE | (~ADSLSSADRMASK & addr));
#endif
break;
case DSP_DMEM_MASK:
#ifdef PRE_SILICON
return(ADSLSS3_BASE | (~ADSLSSADRMASK & addr)+ 0x00000100);
#else
return(ADSLSS3_BASE | (~ADSLSSADRMASK & addr));
#endif
break;
}
}
else
{
/* AR7 case & default case, neither PMEM nor DMEM for AR7O */
DSLHAL_REG32(ADSLSSADR) = addrMap;
#ifdef PRE_SILICON
/* Added 0x100 for Pre-Silicon VLNQ offset.. to be removed for Silicon */
return ((ADSLSS_BASE | (~ADSLSSADRMASK & addr))+ 0x00000100);
#else
return ((ADSLSS_BASE | (~ADSLSSADRMASK & addr)));
#endif
}
return DSLHAL_ERROR_ADDRESS_TRANSLATE;
}
/******************************************************************************************
* FUNCTION NAME: dslhal_support_blockWrite
*
*******************************************************************************************
* DESCRIPTION: This rouin simulates DSP memory write as done in ax5 pci nic card
*
* INPUT: void *buffer, data need to written
* void *adde, memory address to be written
* size_t count, number of bytes to be written
*
* RETURN: 0 --succeeded
* 1 --Failed
*
*****************************************************************************************/
#if 0 //cph org code
int dslhal_support_blockWrite(void *buffer, void *addr, size_t count)
{
int rc, byteCnt=0;
unsigned char* ptr;
union
{
unsigned char *cptr;
short *sptr;
int *iptr;
} src;
union
{
int anint; /* DSP location */
unsigned char *cptr; /* to avoid casts */
} dst;
union
{
unsigned int anint;
unsigned char byte[4];
}data,dword,sword;
/* Enter Critical Section */
shim_osCriticalEnter();
dgprintf(6, "dslhal_support_blockWrite\n");
dgprintf(6,"addr=0x%X, length=0x%X, buffer=0x%X\n", (unsigned int) addr, (unsigned int) count, (unsigned int)buffer);
src.cptr = (unsigned char*) buffer; /* local buffer */
dst.cptr = addr; /* DSP memory location */
/*Maps address first*/
rc=dslhal_support_hostDspAddressTranslate((unsigned int)addr);
dgprintf(5, "NewAddr: %08x\n", rc);
if(rc== DSLHAL_ERROR_ADDRESS_TRANSLATE)
{
dgprintf(1, "dslhal_support_hostDspAddressTranslate failed\n");
return DSLHAL_ERROR_ADDRESS_TRANSLATE;
}
dst.cptr=(unsigned char *)rc;
/* check wether address is at 32bits boundary */
if ((dst.anint & 0x3) && count)
{
sword.anint = *(unsigned int*)((unsigned int)src.cptr & 0xfffffffc); // aligned read source
dword.anint = DSLHAL_REG32((unsigned int)dst.cptr & 0xfffffffc); // aligned read destination
sword.anint = (unsigned int) dslhal_support_byteSwap32(sword.anint);
dword.anint = (unsigned int) dslhal_support_byteSwap32(dword.anint);
ptr = (unsigned char *)((unsigned int)dst.cptr & 0xfffffffc);
if((dst.anint & 3) ==3) /* last byte of a dword */
{
dword.byte[3] = sword.byte[3];
dst.anint++; /* bump the address by one */
byteCnt++;
count--;
}
if((dst.anint & 3) ==1) /* second byte */
{
if(count>3)
{
dword.byte[3] = sword.byte[3];
dst.anint++;
count--;
byteCnt++;
}
if(count>2)
{
dword.byte[2] = sword.byte[2];
dst.anint++;
count--;
byteCnt++;
}
if(count)
{
dword.byte[1] = sword.byte[1];
dst.anint++;
count--;
byteCnt++;
}
}
if((dst.anint & 3) && (count >1))
{
dword.byte[2] = sword.byte[2];
dword.byte[3] = sword.byte[3];
byteCnt+=2;
dst.anint += 2; /* bump the address by two */
count -= 2; /* decrement the byte count by two */
}
if((dst.anint & 3) && (count==1))
{
dword.byte[2] = sword.byte[2];
dst.anint++;
byteCnt++;
count--;
}
src.cptr = (char *)((unsigned int)src.cptr & 0xfffffffc); /* fix 032802 */
dword.anint = dslhal_support_byteSwap32(dword.anint);
DSLHAL_REG32((unsigned int)ptr) = dword.anint;
/* Removed by Ram 09-20-2004 */
/*
ptr = src.cptr;
for(rc=0;rc<count;rc++)
{
*ptr = *(ptr+byteCnt);
ptr++;
}
*/
}
/* the dst pointer should now be on a 32-bit boundary */
while (count > 3)
{
DSLHAL_REG32((unsigned int)dst.cptr) = dslhal_support_byteSwap32(*src.iptr);
src.iptr++; /* bump the data pointer by four */
dst.anint += 4; /* bump the address by four */
count -= 4; /* decrement the byte count by four */
}
/* write remaining bytes */
if(count)
{
int i;
// do read-modify-write
data.anint= DSLHAL_REG32((unsigned int)dst.cptr);
data.anint=dslhal_support_byteSwap32(data.anint);
for (i=0; i< count; i++)
{
data.byte[i]=*(src.cptr+i);
}
data.anint=dslhal_support_byteSwap32(data.anint);
DSLHAL_REG32((unsigned int)dst.cptr) = data.anint;
src.cptr +=count;
dst.anint +=count;
count=0;
}
dgprintf(6, "dslhal_support_blockWrite done\n");
/* Exit Critical Section */
shim_osCriticalExit();
return DSLHAL_ERROR_NO_ERRORS;
} /* end of dslhal_support_blockWrite() */
#endif
int dslhal_support_blockWrite(void *buffer, void *addr, size_t count)
{
int rc; //, byteCnt=0;
// unsigned char* ptr;
union
{
unsigned char *cptr;
short *sptr;
int *iptr;
} src;
union
{
int anint; /* DSP location */
unsigned char *cptr; /* to avoid casts */
} dst;
union
{
unsigned int anint;
unsigned char byte[4];
}data,dsttmp; //,srctmp;
int misaligned_flag, i;
unsigned int trailing_misaligned_bytes;
unsigned int misaligned_bytes;
if (count==0) return DSLHAL_ERROR_NO_ERRORS; // do nothing
/* Enter Critical Section */
shim_osCriticalEnter();
dgprintf(6, "dslhal_support_blockWrite\n");
dgprintf(6,"addr=0x%X, length=0x%X, buffer=0x%X\n", (unsigned int) addr, (unsigned int) count, (unsigned int)buffer);
src.cptr = (unsigned char*) buffer; /* local buffer */
dst.cptr = addr; /* DSP memory location */
misaligned_flag = (((unsigned int) addr&0x03) || ((unsigned int) buffer&0x03)) ? 1: 0;
/*Maps address first*/
rc=dslhal_support_hostDspAddressTranslate((unsigned int)addr);
dgprintf(5, "NewAddr: %08x\n", rc);
if(rc== DSLHAL_ERROR_ADDRESS_TRANSLATE)
{
dgprintf(1, "dslhal_support_hostDspAddressTranslate failed\n");
return DSLHAL_ERROR_ADDRESS_TRANSLATE;
}
dst.cptr=(unsigned char *)rc;
/* check wether address is at 32bits boundary */
#if 1 //cph optimize
if (misaligned_flag)
{ //
// For misaligned dst, do read-modify-write to preserve the un-written data
// For misaligned src, always use byte handling
//
unsigned int pre_aligned_addr=(unsigned int)dst.cptr & 0xfffffffc;
dsttmp.anint = DSLHAL_REG32(pre_aligned_addr); // aligned read destination
// trailing_misaligned_bytes = (count+(dst.anint&3)) & 3;
misaligned_bytes = count+(dst.anint&3);
if (misaligned_bytes<4)
trailing_misaligned_bytes = 0;
else
trailing_misaligned_bytes = misaligned_bytes & 3;
for (i=(dst.anint&3); i<4; i++, count--, dst.anint++)
{
if (count==0) break; // in case the data can't even fill up the first aligned-word
dsttmp.byte[i]= *src.cptr++;
}
DSLHAL_REG32(pre_aligned_addr) = dslhal_support_byteSwap32(dsttmp.anint);
for (i=0; count>0; count--)
{
dsttmp.byte[i++]=*src.cptr++;
i &=3;
if (i==0)
{
// for each aligned 4 bytes do output
dsttmp.anint=dslhal_support_byteSwap32(dsttmp.anint);
DSLHAL_REG32((unsigned int)dst.cptr) = dsttmp.anint; // dst.cptr must be aligned
dst.anint+=4;
if (count ==(trailing_misaligned_bytes+1))
{
// read modify write
dsttmp.anint = DSLHAL_REG32((unsigned int) dst.anint);