From c628ed88421a2df9d7a3ee1f794ab05b7df6a405 Mon Sep 17 00:00:00 2001 From: marcoe87 Date: Sat, 9 Nov 2024 10:17:02 +0100 Subject: [PATCH 1/2] added support for S32K148 --- s32/mcux/devices/S32K148/S32K148_device.h | 830 ++++++++++++++++++ s32/mcux/devices/S32K148/S32K148_features.h | 313 +++++++ s32/mcux/devices/S32K148/device_CMSIS.cmake | 12 + s32/mcux/devices/S32K148/device_system.cmake | 10 + .../S32K148/drivers/driver_memory.cmake | 10 + .../S32K148/drivers/driver_reset.cmake | 10 + s32/mcux/devices/S32K148/drivers/fsl_clock.h | 12 + .../devices/S32K148/fsl_device_registers.h | 32 + s32/soc/s32k148/CMakeLists.txt | 4 + s32/soc/s32k148/include/Clock_Ip_Cfg.h | 117 +++ .../s32k148/include/Clock_Ip_Cfg_Defines.h | 301 +++++++ s32/soc/s32k148/include/OsIf_ArchCfg.h | 89 ++ s32/soc/s32k148/include/OsIf_Cfg.h | 132 +++ s32/soc/s32k148/include/Soc_Ips.h | 265 ++++++ 14 files changed, 2137 insertions(+) create mode 100644 s32/mcux/devices/S32K148/S32K148_device.h create mode 100644 s32/mcux/devices/S32K148/S32K148_features.h create mode 100644 s32/mcux/devices/S32K148/device_CMSIS.cmake create mode 100644 s32/mcux/devices/S32K148/device_system.cmake create mode 100644 s32/mcux/devices/S32K148/drivers/driver_memory.cmake create mode 100644 s32/mcux/devices/S32K148/drivers/driver_reset.cmake create mode 100644 s32/mcux/devices/S32K148/drivers/fsl_clock.h create mode 100644 s32/mcux/devices/S32K148/fsl_device_registers.h create mode 100644 s32/soc/s32k148/CMakeLists.txt create mode 100644 s32/soc/s32k148/include/Clock_Ip_Cfg.h create mode 100644 s32/soc/s32k148/include/Clock_Ip_Cfg_Defines.h create mode 100644 s32/soc/s32k148/include/OsIf_ArchCfg.h create mode 100644 s32/soc/s32k148/include/OsIf_Cfg.h create mode 100644 s32/soc/s32k148/include/Soc_Ips.h diff --git a/s32/mcux/devices/S32K148/S32K148_device.h b/s32/mcux/devices/S32K148/S32K148_device.h new file mode 100644 index 000000000..7e96ce4e2 --- /dev/null +++ b/s32/mcux/devices/S32K148/S32K148_device.h @@ -0,0 +1,830 @@ +/* + * Copyright 2023-2024 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _S32K148_DEVICE_H_ +#define _S32K148_DEVICE_H_ + +/* ---------------------------------------------------------------------------- + -- SYSMPU Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SYSMPU_Peripheral_Access_Layer SYSMPU Peripheral Access Layer + * @{ + */ + +/** SYSMPU - Register Layout Typedef */ +typedef struct { + __IO uint32_t CESR; /**< Control/Error Status Register, offset: 0x0 */ + uint8_t RESERVED_0[12]; + struct { /* offset: 0x10, array step: 0x8 */ + __I uint32_t EAR; /**< Error Address Register, slave port n, array offset: 0x10, array step: 0x8 */ + __I uint32_t EDR; /**< Error Detail Register, slave port n, array offset: 0x14, array step: 0x8 */ + } SP[4]; + uint8_t RESERVED_1[976]; + __IO uint32_t WORD[8][4]; /**< Region Descriptor n, Word 0..Region Descriptor n, Word 3, array offset: 0x400, array step: index*0x10, index2*0x4 */ + uint8_t RESERVED_2[896]; + __IO uint32_t RGDAAC[8]; /**< Region Descriptor Alternate Access Control n, array offset: 0x800, array step: 0x4 */ +} SYSMPU_Type; + +/* ---------------------------------------------------------------------------- + -- SYSMPU Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SYSMPU_Register_Masks SYSMPU Register Masks + * @{ + */ + +/*! @name CESR - Control/Error Status Register */ +/*! @{ */ + +#define SYSMPU_CESR_VLD_MASK (0x1U) +#define SYSMPU_CESR_VLD_SHIFT (0U) +/*! VLD - Valid + * 0b0..MPU is disabled. All accesses from all bus masters are allowed. + * 0b1..MPU is enabled + */ +#define SYSMPU_CESR_VLD(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_VLD_SHIFT)) & SYSMPU_CESR_VLD_MASK) + +#define SYSMPU_CESR_NRGD_MASK (0xF00U) +#define SYSMPU_CESR_NRGD_SHIFT (8U) +/*! NRGD - Number Of Region Descriptors + * 0b0000..8 region descriptors + * 0b0001..12 region descriptors + * 0b0010..16 region descriptors + */ +#define SYSMPU_CESR_NRGD(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_NRGD_SHIFT)) & SYSMPU_CESR_NRGD_MASK) + +#define SYSMPU_CESR_NSP_MASK (0xF000U) +#define SYSMPU_CESR_NSP_SHIFT (12U) +/*! NSP - Number Of Slave Ports + */ +#define SYSMPU_CESR_NSP(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_NSP_SHIFT)) & SYSMPU_CESR_NSP_MASK) + +#define SYSMPU_CESR_HRL_MASK (0xF0000U) +#define SYSMPU_CESR_HRL_SHIFT (16U) +/*! HRL - Hardware Revision Level + */ +#define SYSMPU_CESR_HRL(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_HRL_SHIFT)) & SYSMPU_CESR_HRL_MASK) + +#define SYSMPU_CESR_SPERR_MASK (0xC0000000U) +#define SYSMPU_CESR_SPERR_SHIFT (30U) +/*! SPERR - Slave Port n Error + * 0b00..No error has occurred for slave port n. + * 0b01..An error has occurred for slave port n. + */ +#define SYSMPU_CESR_SPERR(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_SPERR_SHIFT)) & SYSMPU_CESR_SPERR_MASK) +/*! @} */ + +/*! @name EAR - Error Address Register, slave port n */ +/*! @{ */ + +#define SYSMPU_EAR_EADDR_MASK (0xFFFFFFFFU) +#define SYSMPU_EAR_EADDR_SHIFT (0U) +/*! EADDR - Error Address + */ +#define SYSMPU_EAR_EADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EAR_EADDR_SHIFT)) & SYSMPU_EAR_EADDR_MASK) +/*! @} */ + +/* The count of SYSMPU_EAR */ +#define SYSMPU_EAR_COUNT (2U) + +/*! @name EDR - Error Detail Register, slave port n */ +/*! @{ */ + +#define SYSMPU_EDR_ERW_MASK (0x1U) +#define SYSMPU_EDR_ERW_SHIFT (0U) +/*! ERW - Error Read/Write + * 0b0..Read + * 0b1..Write + */ +#define SYSMPU_EDR_ERW(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_ERW_SHIFT)) & SYSMPU_EDR_ERW_MASK) + +#define SYSMPU_EDR_EATTR_MASK (0xEU) +#define SYSMPU_EDR_EATTR_SHIFT (1U) +/*! EATTR - Error Attributes + * 0b000..User mode, instruction access + * 0b001..User mode, data access + * 0b010..Supervisor mode, instruction access + * 0b011..Supervisor mode, data access + */ +#define SYSMPU_EDR_EATTR(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EATTR_SHIFT)) & SYSMPU_EDR_EATTR_MASK) + +#define SYSMPU_EDR_EMN_MASK (0xF0U) +#define SYSMPU_EDR_EMN_SHIFT (4U) +/*! EMN - Error Master Number + */ +#define SYSMPU_EDR_EMN(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EMN_SHIFT)) & SYSMPU_EDR_EMN_MASK) + +#define SYSMPU_EDR_EPID_MASK (0xFF00U) +#define SYSMPU_EDR_EPID_SHIFT (8U) +/*! EPID - Error Process Identification + */ +#define SYSMPU_EDR_EPID(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EPID_SHIFT)) & SYSMPU_EDR_EPID_MASK) + +#define SYSMPU_EDR_EACD_MASK (0xFFFF0000U) +#define SYSMPU_EDR_EACD_SHIFT (16U) +/*! EACD - Error Access Control Detail + */ +#define SYSMPU_EDR_EACD(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EACD_SHIFT)) & SYSMPU_EDR_EACD_MASK) +/*! @} */ + +/* The count of SYSMPU_EDR */ +#define SYSMPU_EDR_COUNT (2U) + +/*! @name WORD - Region Descriptor n, Word 0..Region Descriptor n, Word 3 */ +/*! @{ */ + +#define SYSMPU_WORD_M0UM_MASK (0x7U) +#define SYSMPU_WORD_M0UM_SHIFT (0U) +/*! M0UM - Bus Master 0 User Mode Access Control + */ +#define SYSMPU_WORD_M0UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M0UM_SHIFT)) & SYSMPU_WORD_M0UM_MASK) + +#define SYSMPU_WORD_VLD_MASK (0x1U) +#define SYSMPU_WORD_VLD_SHIFT (0U) +/*! VLD - Valid + * 0b0..Region descriptor is invalid + * 0b1..Region descriptor is valid + */ +#define SYSMPU_WORD_VLD(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_VLD_SHIFT)) & SYSMPU_WORD_VLD_MASK) + +#define SYSMPU_WORD_M0SM_MASK (0x18U) +#define SYSMPU_WORD_M0SM_SHIFT (3U) +/*! M0SM - Bus Master 0 Supervisor Mode Access Control + */ +#define SYSMPU_WORD_M0SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M0SM_SHIFT)) & SYSMPU_WORD_M0SM_MASK) + +#define SYSMPU_WORD_ENDADDR_MASK (0xFFFFFFE0U) +#define SYSMPU_WORD_ENDADDR_SHIFT (5U) +/*! ENDADDR - End Address + */ +#define SYSMPU_WORD_ENDADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_ENDADDR_SHIFT)) & SYSMPU_WORD_ENDADDR_MASK) + +#define SYSMPU_WORD_M0PE_MASK (0x20U) +#define SYSMPU_WORD_M0PE_SHIFT (5U) +/*! M0PE - Bus Master 0 Process Identifier enable + */ +#define SYSMPU_WORD_M0PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M0PE_SHIFT)) & SYSMPU_WORD_M0PE_MASK) + +#define SYSMPU_WORD_SRTADDR_MASK (0xFFFFFFE0U) +#define SYSMPU_WORD_SRTADDR_SHIFT (5U) +/*! SRTADDR - Start Address + */ +#define SYSMPU_WORD_SRTADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_SRTADDR_SHIFT)) & SYSMPU_WORD_SRTADDR_MASK) + +#define SYSMPU_WORD_M1UM_MASK (0x1C0U) +#define SYSMPU_WORD_M1UM_SHIFT (6U) +/*! M1UM - Bus Master 1 User Mode Access Control + */ +#define SYSMPU_WORD_M1UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M1UM_SHIFT)) & SYSMPU_WORD_M1UM_MASK) + +#define SYSMPU_WORD_M1SM_MASK (0x600U) +#define SYSMPU_WORD_M1SM_SHIFT (9U) +/*! M1SM - Bus Master 1 Supervisor Mode Access Control + */ +#define SYSMPU_WORD_M1SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M1SM_SHIFT)) & SYSMPU_WORD_M1SM_MASK) + +#define SYSMPU_WORD_M1PE_MASK (0x800U) +#define SYSMPU_WORD_M1PE_SHIFT (11U) +/*! M1PE - Bus Master 1 Process Identifier enable + */ +#define SYSMPU_WORD_M1PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M1PE_SHIFT)) & SYSMPU_WORD_M1PE_MASK) + +#define SYSMPU_WORD_M2UM_MASK (0x7000U) +#define SYSMPU_WORD_M2UM_SHIFT (12U) +/*! M2UM - Bus Master 2 User Mode Access control + */ +#define SYSMPU_WORD_M2UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M2UM_SHIFT)) & SYSMPU_WORD_M2UM_MASK) + +#define SYSMPU_WORD_M2SM_MASK (0x18000U) +#define SYSMPU_WORD_M2SM_SHIFT (15U) +/*! M2SM - Bus Master 2 Supervisor Mode Access Control + */ +#define SYSMPU_WORD_M2SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M2SM_SHIFT)) & SYSMPU_WORD_M2SM_MASK) + +#define SYSMPU_WORD_PIDMASK_MASK (0xFF0000U) +#define SYSMPU_WORD_PIDMASK_SHIFT (16U) +/*! PIDMASK - Process Identifier Mask + */ +#define SYSMPU_WORD_PIDMASK(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_PIDMASK_SHIFT)) & SYSMPU_WORD_PIDMASK_MASK) + +#define SYSMPU_WORD_M2PE_MASK (0x20000U) +#define SYSMPU_WORD_M2PE_SHIFT (17U) +/*! M2PE - Bus Master 2 Process Identifier Enable + */ +#define SYSMPU_WORD_M2PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M2PE_SHIFT)) & SYSMPU_WORD_M2PE_MASK) + +#define SYSMPU_WORD_M3UM_MASK (0x1C0000U) +#define SYSMPU_WORD_M3UM_SHIFT (18U) +/*! M3UM - Bus Master 3 User Mode Access Control + * 0b000..An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. + * 0b001..Allows the given access type to occur + */ +#define SYSMPU_WORD_M3UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3UM_SHIFT)) & SYSMPU_WORD_M3UM_MASK) + +#define SYSMPU_WORD_M3SM_MASK (0x600000U) +#define SYSMPU_WORD_M3SM_SHIFT (21U) +/*! M3SM - Bus Master 3 Supervisor Mode Access Control + * 0b00..r/w/x; read, write and execute allowed + * 0b01..r/x; read and execute allowed, but no write + * 0b10..r/w; read and write allowed, but no execute + * 0b11..Same as User mode defined in M3UM + */ +#define SYSMPU_WORD_M3SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3SM_SHIFT)) & SYSMPU_WORD_M3SM_MASK) + +#define SYSMPU_WORD_M3PE_MASK (0x800000U) +#define SYSMPU_WORD_M3PE_SHIFT (23U) +/*! M3PE - Bus Master 3 Process Identifier Enable + * 0b0..Do not include the process identifier in the evaluation + * 0b1..Include the process identifier and mask (RGDn_WORD3) in the region hit evaluation + */ +#define SYSMPU_WORD_M3PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3PE_SHIFT)) & SYSMPU_WORD_M3PE_MASK) + +#define SYSMPU_WORD_M4WE_MASK (0x1000000U) +#define SYSMPU_WORD_M4WE_SHIFT (24U) +/*! M4WE - Bus Master 4 Write Enable + * 0b0..Bus master 4 writes terminate with an access error and the write is not performed + * 0b1..Bus master 4 writes allowed + */ +#define SYSMPU_WORD_M4WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M4WE_SHIFT)) & SYSMPU_WORD_M4WE_MASK) + +#define SYSMPU_WORD_PID_MASK (0xFF000000U) +#define SYSMPU_WORD_PID_SHIFT (24U) +/*! PID - Process Identifier + */ +#define SYSMPU_WORD_PID(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_PID_SHIFT)) & SYSMPU_WORD_PID_MASK) + +#define SYSMPU_WORD_M4RE_MASK (0x2000000U) +#define SYSMPU_WORD_M4RE_SHIFT (25U) +/*! M4RE - Bus Master 4 Read Enable + * 0b0..Bus master 4 reads terminate with an access error and the read is not performed + * 0b1..Bus master 4 reads allowed + */ +#define SYSMPU_WORD_M4RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M4RE_SHIFT)) & SYSMPU_WORD_M4RE_MASK) + +#define SYSMPU_WORD_M5WE_MASK (0x4000000U) +#define SYSMPU_WORD_M5WE_SHIFT (26U) +/*! M5WE - Bus Master 5 Write Enable + * 0b0..Bus master 5 writes terminate with an access error and the write is not performed + * 0b1..Bus master 5 writes allowed + */ +#define SYSMPU_WORD_M5WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M5WE_SHIFT)) & SYSMPU_WORD_M5WE_MASK) + +#define SYSMPU_WORD_M5RE_MASK (0x8000000U) +#define SYSMPU_WORD_M5RE_SHIFT (27U) +/*! M5RE - Bus Master 5 Read Enable + * 0b0..Bus master 5 reads terminate with an access error and the read is not performed + * 0b1..Bus master 5 reads allowed + */ +#define SYSMPU_WORD_M5RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M5RE_SHIFT)) & SYSMPU_WORD_M5RE_MASK) + +#define SYSMPU_WORD_M6WE_MASK (0x10000000U) +#define SYSMPU_WORD_M6WE_SHIFT (28U) +/*! M6WE - Bus Master 6 Write Enable + * 0b0..Bus master 6 writes terminate with an access error and the write is not performed + * 0b1..Bus master 6 writes allowed + */ +#define SYSMPU_WORD_M6WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M6WE_SHIFT)) & SYSMPU_WORD_M6WE_MASK) + +#define SYSMPU_WORD_M6RE_MASK (0x20000000U) +#define SYSMPU_WORD_M6RE_SHIFT (29U) +/*! M6RE - Bus Master 6 Read Enable + * 0b0..Bus master 6 reads terminate with an access error and the read is not performed + * 0b1..Bus master 6 reads allowed + */ +#define SYSMPU_WORD_M6RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M6RE_SHIFT)) & SYSMPU_WORD_M6RE_MASK) + +#define SYSMPU_WORD_M7WE_MASK (0x40000000U) +#define SYSMPU_WORD_M7WE_SHIFT (30U) +/*! M7WE - Bus Master 7 Write Enable + * 0b0..Bus master 7 writes terminate with an access error and the write is not performed + * 0b1..Bus master 7 writes allowed + */ +#define SYSMPU_WORD_M7WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M7WE_SHIFT)) & SYSMPU_WORD_M7WE_MASK) + +#define SYSMPU_WORD_M7RE_MASK (0x80000000U) +#define SYSMPU_WORD_M7RE_SHIFT (31U) +/*! M7RE - Bus Master 7 Read Enable + * 0b0..Bus master 7 reads terminate with an access error and the read is not performed + * 0b1..Bus master 7 reads allowed + */ +#define SYSMPU_WORD_M7RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M7RE_SHIFT)) & SYSMPU_WORD_M7RE_MASK) +/*! @} */ + +/* The count of SYSMPU_WORD */ +#define SYSMPU_WORD_COUNT (8U) + +/* The count of SYSMPU_WORD */ +#define SYSMPU_WORD_COUNT2 (4U) + +/*! @name RGDAAC - Region Descriptor Alternate Access Control n */ +/*! @{ */ + +#define SYSMPU_RGDAAC_M0UM_MASK (0x7U) +#define SYSMPU_RGDAAC_M0UM_SHIFT (0U) +/*! M0UM - Bus Master 0 User Mode Access Control + */ +#define SYSMPU_RGDAAC_M0UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M0UM_SHIFT)) & SYSMPU_RGDAAC_M0UM_MASK) + +#define SYSMPU_RGDAAC_M0SM_MASK (0x18U) +#define SYSMPU_RGDAAC_M0SM_SHIFT (3U) +/*! M0SM - Bus Master 0 Supervisor Mode Access Control + */ +#define SYSMPU_RGDAAC_M0SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M0SM_SHIFT)) & SYSMPU_RGDAAC_M0SM_MASK) + +#define SYSMPU_RGDAAC_M0PE_MASK (0x20U) +#define SYSMPU_RGDAAC_M0PE_SHIFT (5U) +/*! M0PE - Bus Master 0 Process Identifier Enable + */ +#define SYSMPU_RGDAAC_M0PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M0PE_SHIFT)) & SYSMPU_RGDAAC_M0PE_MASK) + +#define SYSMPU_RGDAAC_M1UM_MASK (0x1C0U) +#define SYSMPU_RGDAAC_M1UM_SHIFT (6U) +/*! M1UM - Bus Master 1 User Mode Access Control + */ +#define SYSMPU_RGDAAC_M1UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M1UM_SHIFT)) & SYSMPU_RGDAAC_M1UM_MASK) + +#define SYSMPU_RGDAAC_M1SM_MASK (0x600U) +#define SYSMPU_RGDAAC_M1SM_SHIFT (9U) +/*! M1SM - Bus Master 1 Supervisor Mode Access Control + */ +#define SYSMPU_RGDAAC_M1SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M1SM_SHIFT)) & SYSMPU_RGDAAC_M1SM_MASK) + +#define SYSMPU_RGDAAC_M1PE_MASK (0x800U) +#define SYSMPU_RGDAAC_M1PE_SHIFT (11U) +/*! M1PE - Bus Master 1 Process Identifier Enable + */ +#define SYSMPU_RGDAAC_M1PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M1PE_SHIFT)) & SYSMPU_RGDAAC_M1PE_MASK) + +#define SYSMPU_RGDAAC_M2UM_MASK (0x7000U) +#define SYSMPU_RGDAAC_M2UM_SHIFT (12U) +/*! M2UM - Bus Master 2 User Mode Access Control + */ +#define SYSMPU_RGDAAC_M2UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M2UM_SHIFT)) & SYSMPU_RGDAAC_M2UM_MASK) + +#define SYSMPU_RGDAAC_M2SM_MASK (0x18000U) +#define SYSMPU_RGDAAC_M2SM_SHIFT (15U) +/*! M2SM - Bus Master 2 Supervisor Mode Access Control + */ +#define SYSMPU_RGDAAC_M2SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M2SM_SHIFT)) & SYSMPU_RGDAAC_M2SM_MASK) + +#define SYSMPU_RGDAAC_M2PE_MASK (0x20000U) +#define SYSMPU_RGDAAC_M2PE_SHIFT (17U) +/*! M2PE - Bus Master 2 Process Identifier Enable + */ +#define SYSMPU_RGDAAC_M2PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M2PE_SHIFT)) & SYSMPU_RGDAAC_M2PE_MASK) + +#define SYSMPU_RGDAAC_M3UM_MASK (0x1C0000U) +#define SYSMPU_RGDAAC_M3UM_SHIFT (18U) +/*! M3UM - Bus Master 3 User Mode Access Control + * 0b000..An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. + * 0b001..Allows the given access type to occur + */ +#define SYSMPU_RGDAAC_M3UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3UM_SHIFT)) & SYSMPU_RGDAAC_M3UM_MASK) + +#define SYSMPU_RGDAAC_M3SM_MASK (0x600000U) +#define SYSMPU_RGDAAC_M3SM_SHIFT (21U) +/*! M3SM - Bus Master 3 Supervisor Mode Access Control + * 0b00..r/w/x; read, write and execute allowed + * 0b01..r/x; read and execute allowed, but no write + * 0b10..r/w; read and write allowed, but no execute + * 0b11..Same as User mode defined in M3UM + */ +#define SYSMPU_RGDAAC_M3SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3SM_SHIFT)) & SYSMPU_RGDAAC_M3SM_MASK) + +#define SYSMPU_RGDAAC_M3PE_MASK (0x800000U) +#define SYSMPU_RGDAAC_M3PE_SHIFT (23U) +/*! M3PE - Bus Master 3 Process Identifier Enable + * 0b0..Do not include the process identifier in the evaluation + * 0b1..Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation + */ +#define SYSMPU_RGDAAC_M3PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3PE_SHIFT)) & SYSMPU_RGDAAC_M3PE_MASK) + +#define SYSMPU_RGDAAC_M4WE_MASK (0x1000000U) +#define SYSMPU_RGDAAC_M4WE_SHIFT (24U) +/*! M4WE - Bus Master 4 Write Enable + * 0b0..Bus master 4 writes terminate with an access error and the write is not performed + * 0b1..Bus master 4 writes allowed + */ +#define SYSMPU_RGDAAC_M4WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M4WE_SHIFT)) & SYSMPU_RGDAAC_M4WE_MASK) + +#define SYSMPU_RGDAAC_M4RE_MASK (0x2000000U) +#define SYSMPU_RGDAAC_M4RE_SHIFT (25U) +/*! M4RE - Bus Master 4 Read Enable + * 0b0..Bus master 4 reads terminate with an access error and the read is not performed + * 0b1..Bus master 4 reads allowed + */ +#define SYSMPU_RGDAAC_M4RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M4RE_SHIFT)) & SYSMPU_RGDAAC_M4RE_MASK) + +#define SYSMPU_RGDAAC_M5WE_MASK (0x4000000U) +#define SYSMPU_RGDAAC_M5WE_SHIFT (26U) +/*! M5WE - Bus Master 5 Write Enable + * 0b0..Bus master 5 writes terminate with an access error and the write is not performed + * 0b1..Bus master 5 writes allowed + */ +#define SYSMPU_RGDAAC_M5WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M5WE_SHIFT)) & SYSMPU_RGDAAC_M5WE_MASK) + +#define SYSMPU_RGDAAC_M5RE_MASK (0x8000000U) +#define SYSMPU_RGDAAC_M5RE_SHIFT (27U) +/*! M5RE - Bus Master 5 Read Enable + * 0b0..Bus master 5 reads terminate with an access error and the read is not performed + * 0b1..Bus master 5 reads allowed + */ +#define SYSMPU_RGDAAC_M5RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M5RE_SHIFT)) & SYSMPU_RGDAAC_M5RE_MASK) + +#define SYSMPU_RGDAAC_M6WE_MASK (0x10000000U) +#define SYSMPU_RGDAAC_M6WE_SHIFT (28U) +/*! M6WE - Bus Master 6 Write Enable + * 0b0..Bus master 6 writes terminate with an access error and the write is not performed + * 0b1..Bus master 6 writes allowed + */ +#define SYSMPU_RGDAAC_M6WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M6WE_SHIFT)) & SYSMPU_RGDAAC_M6WE_MASK) + +#define SYSMPU_RGDAAC_M6RE_MASK (0x20000000U) +#define SYSMPU_RGDAAC_M6RE_SHIFT (29U) +/*! M6RE - Bus Master 6 Read Enable + * 0b0..Bus master 6 reads terminate with an access error and the read is not performed + * 0b1..Bus master 6 reads allowed + */ +#define SYSMPU_RGDAAC_M6RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M6RE_SHIFT)) & SYSMPU_RGDAAC_M6RE_MASK) + +#define SYSMPU_RGDAAC_M7WE_MASK (0x40000000U) +#define SYSMPU_RGDAAC_M7WE_SHIFT (30U) +/*! M7WE - Bus Master 7 Write Enable + * 0b0..Bus master 7 writes terminate with an access error and the write is not performed + * 0b1..Bus master 7 writes allowed + */ +#define SYSMPU_RGDAAC_M7WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M7WE_SHIFT)) & SYSMPU_RGDAAC_M7WE_MASK) + +#define SYSMPU_RGDAAC_M7RE_MASK (0x80000000U) +#define SYSMPU_RGDAAC_M7RE_SHIFT (31U) +/*! M7RE - Bus Master 7 Read Enable + * 0b0..Bus master 7 reads terminate with an access error and the read is not performed + * 0b1..Bus master 7 reads allowed + */ +#define SYSMPU_RGDAAC_M7RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M7RE_SHIFT)) & SYSMPU_RGDAAC_M7RE_MASK) +/*! @} */ + +/* The count of SYSMPU_RGDAAC */ +#define SYSMPU_RGDAAC_COUNT (8U) + + +/*! + * @} + */ /* end of group SYSMPU_Register_Masks */ + + +/* SYSMPU - Peripheral instance base addresses */ +/** Peripheral SYSMPU base address */ +#define SYSMPU_BASE (0x4000D000u) +/** Peripheral SYSMPU base pointer */ +#define SYSMPU ((SYSMPU_Type *)SYSMPU_BASE) +/** Array initializer of SYSMPU peripheral base addresses */ +#define SYSMPU_BASE_ADDRS { SYSMPU_BASE } +/** Array initializer of SYSMPU peripheral base pointers */ +#define SYSMPU_BASE_PTRS { SYSMPU } + +/*! + * @} + */ /* end of group SYSMPU_Peripheral_Access_Layer */ + +/* ---------------------------------------------------------------------------- + -- MSCM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MSCM_Peripheral_Access_Layer MSCM Peripheral Access Layer + * @{ + */ + +/* MSCM - Peripheral instance base addresses */ +/** Peripheral MSCM base address */ +#define MSCM_BASE IP_MSCM_BASE +/** Peripheral MSCM base pointer */ +#define MSCM IP_MSCM +/** Array initializer of MSCM peripheral base addresses */ +#define MSCM_BASE_ADDRS IP_MSCM_BASE_ADDRS +/** Array initializer of MSCM peripheral base pointers */ +#define MSCM_BASE_PTRS IP_MSCM_BASE_PTRS + +/*! + * @} + */ /* end of group MSCM_Peripheral_Access_Layer */ + +/* ---------------------------------------------------------------------------- + -- LPUART Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer + * @{ + */ + +/* LPUART - Peripheral instance base addresses */ +/** Peripheral LPUART0 base address */ +#define LPUART0_BASE IP_LPUART0_BASE +/** Peripheral LPUART0 base pointer */ +#define LPUART0 IP_LPUART0 +/** Peripheral LPUART1 base address */ +#define LPUART1_BASE IP_LPUART1_BASE +/** Peripheral LPUART1 base pointer */ +#define LPUART1 IP_LPUART1 +/** Peripheral LPUART2 base address */ +#define LPUART2_BASE IP_LPUART2_BASE +/** Peripheral LPUART2 base pointer */ +#define LPUART2 IP_LPUART2 +/** Array initializer of LPUART peripheral base addresses */ +#define LPUART_BASE_ADDRS IP_LPUART_BASE_ADDRS +/** Array initializer of LPUART peripheral base pointers */ +#define LPUART_BASE_PTRS IP_LPUART_BASE_PTRS +/** Interrupt vectors for the LPUART peripheral type */ +#define LPUART_RX_TX_IRQS { LPUART0_RxTx_IRQn, LPUART1_RxTx_IRQn, LPUART2_RxTx_IRQn } +#define LPUART_ERR_IRQS { LPUART0_RxTx_IRQn, LPUART1_RxTx_IRQn, LPUART2_RxTx_IRQn } + +/*! + * @} + */ /* end of group LPUART_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- LPI2C Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPI2C_Peripheral_Access_Layer LPI2C Peripheral Access Layer + * @{ + */ + +/* LPI2C - Peripheral instance base addresses */ +/** Peripheral LPI2C0 base address */ +#define LPI2C0_BASE IP_LPI2C0_BASE +/** Peripheral LPI2C0 base pointer */ +#define LPI2C0 IP_LPI2C0 +/** Peripheral LPI2C1 base address */ +#define LPI2C1_BASE IP_LPI2C1_BASE +/** Peripheral LPI2C1 base pointer */ +#define LPI2C1 IP_LPI2C1 +/** Array initializer of LPI2C peripheral base addresses */ +#define LPI2C_BASE_ADDRS IP_LPI2C_BASE_ADDRS +/** Array initializer of LPI2C peripheral base pointers */ +#define LPI2C_BASE_PTRS IP_LPI2C_BASE_PTRS +/** Interrupt vectors for the LPI2C peripheral type */ +#define LPI2C_IRQS { LPI2C0_Master_IRQn, LPI2C1_Master_IRQn } + +/*! + * @} + */ /* end of group LPI2C_Peripheral_Access_Layer */ + +/* ---------------------------------------------------------------------------- + -- LPSPI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPSPI_Peripheral_Access_Layer LPSPI Peripheral Access Layer + * @{ + */ + +/* LPSPI - Peripheral instance base addresses */ +/** Peripheral LPSPI0 base address */ +#define LPSPI0_BASE IP_LPSPI0_BASE +/** Peripheral LPSPI0 base pointer */ +#define LPSPI0 IP_LPSPI0 +/** Peripheral LPSPI1 base address */ +#define LPSPI1_BASE IP_LPSPI1_BASE +/** Peripheral LPSPI1 base pointer */ +#define LPSPI1 IP_LPSPI1 +/** Peripheral LPSPI2 base address */ +#define LPSPI2_BASE IP_LPSPI2_BASE +/** Peripheral LPSPI2 base pointer */ +#define LPSPI2 IP_LPSPI2 +/** Array initializer of LPSPI peripheral base addresses */ +#define LPSPI_BASE_ADDRS IP_LPSPI_BASE_ADDRS +/** Array initializer of LPSPI peripheral base pointers */ +#define LPSPI_BASE_PTRS IP_LPSPI_BASE_PTRS +/** Interrupt vectors for the LPSPI peripheral type */ +#define LPSPI_IRQS { LPSPI0_IRQn, LPSPI1_IRQn, LPSPI2_IRQn } + +/*! + * @} + */ /* end of group LPSPI_Peripheral_Access_Layer */ + +/* ---------------------------------------------------------------------------- + -- LMEM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LMEM_Peripheral_Access_Layer LMEM Peripheral Access Layer + * @{ + */ + +/*! + * @addtogroup LMEM_Register_Masks LMEM Register Masks + * @{ + */ + +/*! @name PCCCR - Cache control register */ +/*! @{ */ + +/* ENWRBUF - Enable Write Buffer is not available on this SoC */ +#define LMEM_PCCCR_ENWRBUF_MASK (0U) +#define LMEM_PCCCR_ENWRBUF_SHIFT (0U) +#define LMEM_PCCCR_ENWRBUF(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_ENWRBUF_SHIFT)) & LMEM_PCCCR_ENWRBUF_MASK) +/*! @} */ + +/*! + * @} + */ /* end of group LMEM_Register_Masks */ + +/* LMEM - Peripheral instance base addresses */ +/** Peripheral LMEM base address */ +#define LMEM_BASE IP_LMEM_BASE +/** Peripheral LMEM base pointer */ +#define LMEM IP_LMEM +/** Array initializer of LMEM peripheral base addresses */ +#define LMEM_BASE_ADDRS IP_LMEM_BASE_ADDRS +/** Array initializer of LMEM peripheral base pointers */ +#define LMEM_BASE_PTRS IP_LMEM_BASE_PTRS + +/*! + * @} + */ /* end of group LMEM_Peripheral_Access_Layer */ + +/* ---------------------------------------------------------------------------- + -- FTM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FTM_Peripheral_Access_Layer FTM Peripheral Access Layer + * @{ + */ + +/* FTM - Peripheral instance base addresses */ +/** Peripheral FTM0 base address */ +#define FTM0_BASE IP_FTM0_BASE +/** Peripheral FTM0 base pointer */ +#define FTM0 IP_FTM0 +/** Peripheral FTM1 base address */ +#define FTM1_BASE IP_FTM1_BASE +/** Peripheral FTM1 base pointer */ +#define FTM1 IP_FTM1 +/** Peripheral FTM2 base address */ +#define FTM2_BASE IP_FTM2_BASE +/** Peripheral FTM2 base pointer */ +#define FTM2 IP_FTM2 +/** Peripheral FTM3 base address */ +#define FTM3_BASE IP_FTM3_BASE +/** Peripheral FTM3 base pointer */ +#define FTM3 IP_FTM3 +/** Peripheral FTM4 base address */ +#define FTM4_BASE IP_FTM4_BASE +/** Peripheral FTM4 base pointer */ +#define FTM4 IP_FTM4 +/** Peripheral FTM5 base address */ +#define FTM5_BASE IP_FTM5_BASE +/** Peripheral FTM5 base pointer */ +#define FTM5 IP_FTM5 +/** Peripheral FTM6 base address */ +#define FTM6_BASE IP_FTM6_BASE +/** Peripheral FTM6 base pointer */ +#define FTM6 IP_FTM6 +/** Peripheral FTM7 base address */ +#define FTM7_BASE IP_FTM7_BASE +/** Peripheral FTM7 base pointer */ +#define FTM7 IP_FTM7 +/** Array initializer of FTM peripheral base addresses */ +#define FTM_BASE_ADDRS IP_FTM_BASE_ADDRS +/** Array initializer of FTM peripheral base pointers */ +#define FTM_BASE_PTRS IP_FTM_BASE_PTRS + +/*! + * @} + */ /* end of group FTM_Peripheral_Access_Layer */ + +/* ---------------------------------------------------------------------------- + -- CAN Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer + * @{ + */ + +/* CAN - Peripheral instance base addresses */ +/** Peripheral CAN_0 base address */ +#define CAN0_BASE IP_FLEXCAN0_BASE +/** Peripheral CAN_0 base pointer */ +#define CAN0 IP_FLEXCAN0 +/** Peripheral CAN_1 base address */ +#define CAN1_BASE IP_FLEXCAN1_BASE +/** Peripheral CAN_1 base pointer */ +#define CAN1 IP_FLEXCAN1 +/** Peripheral CAN_2 base address */ +#define CAN2_BASE IP_FLEXCAN2_BASE +/** Peripheral CAN_2 base pointer */ +#define CAN2 IP_FLEXCAN2 +/** Array initializer of CAN peripheral base addresses */ +#define CAN_BASE_ADDRS IP_FLEXCAN_BASE_ADDRS +/** Array initializer of CAN peripheral base pointers */ +#define CAN_BASE_PTRS IP_FLEXCAN_BASE_PTRS +/** Interrupt vectors for the CAN peripheral type */ +#define CAN_Rx_Warning_IRQS { CAN0_ORed_IRQn, CAN1_ORed_IRQn, CAN2_ORed_IRQn } +#define CAN_Tx_Warning_IRQS { CAN0_ORed_IRQn, CAN1_ORed_IRQn, CAN2_ORed_IRQn } +#define CAN_Wake_Up_IRQS { CAN0_Wake_Up_IRQn, NotAvail_IRQn, NotAvail_IRQn } +#define CAN_Error_IRQS { CAN0_Error_IRQn, CAN1_Error_IRQn, CAN2_Error_IRQn } +#define CAN_Bus_Off_IRQS { CAN0_ORed_IRQn, CAN1_ORed_IRQn, CAN2_ORed_IRQn } +#define CAN_ORed_Message_buffer_0_15_IRQS { CAN0_ORed_0_15_MB_IRQn, CAN1_ORed_0_15_MB_IRQn, CAN2_ORed_0_15_MB_IRQn } +#define CAN_ORed_Message_buffer_16_31_IRQS { CAN0_ORed_16_31_MB_IRQn, CAN1_ORed_16_31_MB_IRQn, CAN2_ORed_16_31_MB_IRQn } +#define CAN_ORed_Message_buffer_IRQS { CAN0_ORed_IRQn, CAN1_ORed_IRQn, CAN2_ORed_IRQn } + +/*! + * @} + */ /* end of group CAN_Peripheral_Access_Layer */ + +/* ---------------------------------------------------------------------------- + -- WDOG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer + * @{ + */ + + /* WDOG - Peripheral instance base addresses */ +/** Peripheral WDOG base address */ +#define WDOG_BASE IP_WDOG_BASE +/** Peripheral WDOG base pointer */ +#define WDOG IP_WDOG +/** Array initializer of WDOG peripheral base addresses */ +#define WDOG_BASE_ADDRS IP_WDOG_BASE_ADDRS +/** Array initializer of WDOG peripheral base pointers */ +#define WDOG_BASE_PTRS IP_WDOG_BASE_PTRS +/** Interrupt vectors for the WDOG peripheral type */ +#define WDOG_IRQS { WDOG_EWM_IRQn } +#define WDOG_UPDATE_KEY (0xD928C520U) +#define WDOG_REFRESH_KEY (0xB480A602U) + +/*! + * @} + */ /* end of group WDOG_Peripheral_Access_Layer */ + +/* ---------------------------------------------------------------------------- + -- RTC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer + * @{ + */ + +/* RTC - Peripheral instance base addresses */ +/** Peripheral RTC base address */ +#define RTC_BASE IP_RTC_BASE +/** Peripheral RTC base pointer */ +#define RTC IP_RTC +/** Array initializer of RTC peripheral base addresses */ +#define RTC_BASE_ADDRS IP_RTC_BASE_ADDRS +/** Array initializer of RTC peripheral base pointers */ +#define RTC_BASE_PTRS IP_RTC_BASE_PTRS +/** Interrupt vectors for the RTC peripheral type */ +#define RTC_IRQS { RTC_IRQn } +#define RTC_SECONDS_IRQS { RTC_Seconds_IRQn } + +/*! + * @} + */ /* end of group RTC_Peripheral_Access_Layer */ + +/* ---------------------------------------------------------------------------- + -- ADC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer + * @{ + */ + +/* ADC - Peripheral instance base addresses */ +/** Peripheral ADC0 base address */ +#define ADC0_BASE IP_ADC0_BASE +/** Peripheral ADC0 base pointer */ +#define ADC0 IP_ADC0 +/** Peripheral ADC1 base address */ +#define ADC1_BASE IP_ADC1_BASE +/** Peripheral ADC1 base pointer */ +#define ADC1 IP_ADC1 +/** Array initializer of ADC peripheral base addresses */ +#define ADC_BASE_ADDRS IP_ADC_BASE_ADDRS +/** Array initializer of ADC peripheral base pointers */ +#define ADC_BASE_PTRS IP_ADC_BASE_PTRS +/** Interrupt vectors for the ADC peripheral type */ +#define ADC_IRQS { ADC0_IRQn, ADC1_IRQn } + +/*! + * @} + */ /* end of group ADC_Peripheral_Access_Layer */ + +#endif /* _S32K148_DEVICE_H_ */ diff --git a/s32/mcux/devices/S32K148/S32K148_features.h b/s32/mcux/devices/S32K148/S32K148_features.h new file mode 100644 index 000000000..4867903f2 --- /dev/null +++ b/s32/mcux/devices/S32K148/S32K148_features.h @@ -0,0 +1,313 @@ +/* + * Copyright 2023-2024 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _S32K148_FEATURES_H_ +#define _S32K148_FEATURES_H_ + +/* SOC module features */ + +/* @brief ADC12 availability on the SoC. */ +#define FSL_FEATURE_SOC_ADC12_COUNT (2) +/* @brief SYSMPU availability on the SoC. */ +#define FSL_FEATURE_SOC_SYSMPU_COUNT (1) +/* @brief PORT availability on the SoC. */ +#define FSL_FEATURE_SOC_PORT_COUNT (5) +/* @brief GPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_GPIO_COUNT (5) +/* @brief LPUART availability on the SoC. */ +#define FSL_FEATURE_SOC_LPUART_COUNT (3) +/* @brief LPI2C availability on the SoC. */ +#define FSL_FEATURE_SOC_LPI2C_COUNT (2) +/* @brief LPSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_LPSPI_COUNT (3) +/* @brief LMEM availability on the SoC. */ +#define FSL_FEATURE_SOC_LMEM_COUNT (1) +/* @brief FTM availability on the SoC. */ +#define FSL_FEATURE_SOC_FTM_COUNT (8) +/* @brief FLEXCAN availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXCAN_COUNT (3) +/* @brief WDOG availability on the SoC. */ +#define FSL_FEATURE_SOC_WDOG_COUNT (1) +/* @brief RTC availability on the SoC. */ +#define FSL_FEATURE_SOC_RTC_COUNT (1) + +/* SYSMPU module features */ + +/* @brief Specifies number of descriptors available. */ +#define FSL_FEATURE_SYSMPU_DESCRIPTOR_COUNT (8) +/* @brief Has process identifier support. */ +#define FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER (1) +/* @brief Total number of MPU slave. */ +#define FSL_FEATURE_SYSMPU_SLAVE_COUNT (4) +/* @brief Total number of MPU master. */ +#define FSL_FEATURE_SYSMPU_MASTER_COUNT (4) + +/* PORT module features */ + +/* @brief Has control lock (register bit PCR[LK]). */ +#define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1) +/* @brief Has open drain control (register bit PCR[ODE]). */ +#define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (0) +/* @brief Has digital filter (registers DFER, DFCR and DFWR). */ +#define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (1) +/* @brief Has DMA request (register bit field PCR[IRQC] values). */ +#define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1) +/* @brief Has pull resistor selection available. */ +#define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1) +/* @brief Has pull resistor enable (register bit PCR[PE]). */ +#define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1) +/* @brief Has slew rate control (register bit PCR[SRE]). */ +#define FSL_FEATURE_PORT_HAS_SLEW_RATE (0) +/* @brief Has passive filter (register bit field PCR[PFE]). */ +#define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) +/* @brief Has drive strength control (register bit PCR[DSE]). */ +#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) +/* @brief Has separate drive strength register (HDRVE). */ +#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0) +/* @brief Has glitch filter (register IOFLT). */ +#define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0) +/* @brief Defines width of PCR[MUX] field. */ +#define FSL_FEATURE_PORT_PCR_MUX_WIDTH (3) +/* @brief Has dedicated interrupt vector. */ +#define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1) +/* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */ +#define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (1) +/* @brief Defines whether PCR[IRQC] bit-field has flag states. */ +#define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0) +/* @brief Defines whether PCR[IRQC] bit-field has trigger states. */ +#define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0) + +/* GPIO module features */ + +/* @brief Has GPIO attribute checker register (GACR). */ +#define FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER (0) + +/* LPUART module features */ + +/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ +#define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0) +/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) +/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_HAS_FIFO (1) +/* @brief Has 32-bit register MODIR */ +#define FSL_FEATURE_LPUART_HAS_MODIR (1) +/* @brief Hardware flow control (RTS, CTS) is supported. */ +#define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1) +/* @brief Infrared (modulation) is supported. */ +#define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1) +/* @brief 2 bits long stop bit is available. */ +#define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1) +/* @brief If 10-bit mode is supported. */ +#define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1) +/* @brief If 7-bit mode is supported. */ +#define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (1) +/* @brief Baud rate fine adjustment is available. */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) +/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) +/* @brief Peripheral type. */ +#define FSL_FEATURE_LPUART_IS_SCI (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) +/* @brief Supports two match addresses to filter incoming frames. */ +#define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) +/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1) +/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ +#define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) +/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) +/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ +#define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) +/* @brief Has improved smart card (ISO7816 protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) +/* @brief Has local operation network (CEA709.1-B protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) +/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ +#define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1) +/* @brief Lin break detect available (has bit BAUD[LBKDIE]). */ +#define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1) +/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ +#define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (0) +/* @brief Has separate RX and TX interrupts. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0) +/* @brief Has LPAURT_PARAM. */ +#define FSL_FEATURE_LPUART_HAS_PARAM (1) +/* @brief Has LPUART_VERID. */ +#define FSL_FEATURE_LPUART_HAS_VERID (1) +/* @brief Has LPUART_GLOBAL. */ +#define FSL_FEATURE_LPUART_HAS_GLOBAL (1) +/* @brief Has LPUART_PINCFG. */ +#define FSL_FEATURE_LPUART_HAS_PINCFG (1) + +/* LPI2C module features */ + +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (4) + +/* LPSPI module features */ + +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (4) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Has CCR1 (related to existence of registers CCR1). */ +#define FSL_FEATURE_LPSPI_HAS_CCR1 (0) + +/* LMEM module features */ + +/* @brief Has process identifier support. */ +#define FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE (0) +/* @brief Has L1 cache. */ +#define FSL_FEATURE_HAS_L1CACHE (1) +/* @brief L1 ICACHE line size in byte. */ +#define FSL_FEATURE_L1ICACHE_LINESIZE_BYTE (16) +/* @brief L1 DCACHE line size in byte. */ +#define FSL_FEATURE_L1DCACHE_LINESIZE_BYTE (16) + +/* FTM module features */ + +/* @brief Number of channels. */ +#define FSL_FEATURE_FTM_CHANNEL_COUNTn(x) (8) +/* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */ +#define FSL_FEATURE_FTM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (1) +/* @brief Has extended deadtime value. */ +#define FSL_FEATURE_FTM_HAS_EXTENDED_DEADTIME_VALUE (1) +/* @brief Enable pwm output for the module. */ +#define FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT (1) +/* @brief Has half-cycle reload for the module. */ +#define FSL_FEATURE_FTM_HAS_HALFCYCLE_RELOAD (1) +/* @brief Has reload interrupt. */ +#define FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT (1) +/* @brief Has reload initialization trigger. */ +#define FSL_FEATURE_FTM_HAS_RELOAD_INITIALIZATION_TRIGGER (1) +/* @brief Has DMA support, bitfield CnSC[DMA]. */ +#define FSL_FEATURE_FTM_HAS_DMA_SUPPORT (1) +/* @brief If channel 6 is used to generate channel trigger, bitfield EXTTRIG[CH6TRIG]. */ +#define FSL_FEATURE_FTM_HAS_CHANNEL6_TRIGGER (1) +/* @brief If channel 7 is used to generate channel trigger, bitfield EXTTRIG[CH7TRIG]. */ +#define FSL_FEATURE_FTM_HAS_CHANNEL7_TRIGGER (1) +/* @brief If instance has only TPM function. */ +#define FSL_FEATURE_FTM_IS_TPM_ONLY_INSTANCEn(x) (0) +/* @brief Has frequency of the reload opportunities, bitfield CONF[LDFQ]. */ +#define FSL_FEATURE_FTM_HAS_CONF_LDFQ_BIT (1) + +/* FLEXCAN module features */ + +/* @brief Message buffer size */ +#define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) \ + (((x) == CAN0) ? (32) : \ + (((x) == CAN1) ? (32) : \ + (((x) == CAN2) ? (32) : (-1)))) +/* @brief Has doze mode support (register bit field MCR[DOZE]). */ +#define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (0) +/* @brief Insatnce has doze mode support (register bit field MCR[DOZE]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_DOZE_MODE_SUPPORTn(x) (0) +/* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */ +#define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (0) +/* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */ +#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (0) +/* @brief Instance has extended bit timing register (register CBT). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTENDED_TIMING_REGISTERn(x) (1) +/* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */ +#define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (1) +/* @brief Instance has a receive FIFO DMA feature (register bit field MCR[DMA]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_RX_FIFO_DMAn(x) (1) +/* @brief Remove CAN Engine Clock Source Selection from unsupported part. */ +#define FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE (0) +/* @brief Instance remove CAN Engine Clock Source Selection from unsupported part. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_SUPPORT_ENGINE_CLK_SEL_REMOVEn(x) (0) +/* @brief Has CAN with Flexible Data rate (CAN FD) protocol. */ +#define FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE (1) +/* @brief CAN instance support Flexible Data rate (CAN FD) protocol. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(x) \ + (((x) == CAN0) ? (1) : \ + (((x) == CAN1) ? (1) : \ + (((x) == CAN2) ? (1) : (0)))) +/* @brief Has memory error control (register MECR). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL (0) +/* @brief Has enhanced bit timing register (register EPRS, ENCBT, EDCBT and ETDC). */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG (0) +/* @brief Has Pretended Networking mode support. */ +#define FSL_FEATURE_FLEXCAN_HAS_PN_MODE (0) +/* @brief Has Enhanced Rx FIFO. */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO (0) +/* @brief Does not support Supervisor Mode (bitfield MCR[SUPV]. */ +#define FSL_FEATURE_FLEXCAN_HAS_NO_SUPV_SUPPORT (0) + +/* WDOG module features */ + +/* @brief Watchdog is available. */ +#define FSL_FEATURE_WDOG_HAS_WATCHDOG (1) +/* @brief WDOG_CNT can be 32-bit written. */ +#define FSL_FEATURE_WDOG_HAS_32BIT_ACCESS (1) + +/* RTC module features */ + +/* @brief Has wakeup pin. */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (0) +/* @brief Has wakeup pin selection (bit field CR[WPS]). */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (0) +/* @brief Has low power features (registers MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_MONOTONIC (0) +/* @brief Has read/write access control (registers WAR and RAR). */ +#define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (0) +/* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_SECURITY (0) +/* @brief Has RTC_CLKIN available. */ +#define FSL_FEATURE_RTC_HAS_RTC_CLKIN (1) +/* @brief Has prescaler adjust for LPO. */ +#define FSL_FEATURE_RTC_HAS_LPO_ADJUST (1) +/* @brief Has Clock Pin Enable field. */ +#define FSL_FEATURE_RTC_HAS_CPE (1) +/* @brief Has Timer Seconds Interrupt Configuration field. */ +#define FSL_FEATURE_RTC_HAS_TSIC (1) +/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ +#define FSL_FEATURE_RTC_HAS_OSC_SCXP (0) +/* @brief Has Tamper Interrupt Register (register TIR). */ +#define FSL_FEATURE_RTC_HAS_TIR (0) +/* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */ +#define FSL_FEATURE_RTC_HAS_TIR_TPIE (0) +/* @brief Has Security Interrupt Enable (bitfield TIR[SIE]). */ +#define FSL_FEATURE_RTC_HAS_TIR_SIE (0) +/* @brief Has Loss of Clock Interrupt Enable (bitfield TIR[LCIE]). */ +#define FSL_FEATURE_RTC_HAS_TIR_LCIE (0) +/* @brief Has Tamper Interrupt Detect Flag (bitfield SR[TIDF]). */ +#define FSL_FEATURE_RTC_HAS_SR_TIDF (0) +/* @brief Has Tamper Detect Register (register TDR). */ +#define FSL_FEATURE_RTC_HAS_TDR (0) +/* @brief Has Tamper Pin Flag (bitfield TDR[TPF]). */ +#define FSL_FEATURE_RTC_HAS_TDR_TPF (0) +/* @brief Has Security Tamper Flag (bitfield TDR[STF]). */ +#define FSL_FEATURE_RTC_HAS_TDR_STF (0) +/* @brief Has Loss of Clock Tamper Flag (bitfield TDR[LCTF]). */ +#define FSL_FEATURE_RTC_HAS_TDR_LCTF (0) +/* @brief Has Tamper Time Seconds Register (register TTSR). */ +#define FSL_FEATURE_RTC_HAS_TTSR (0) +/* @brief Has Pin Configuration Register (register PCR). */ +#define FSL_FEATURE_RTC_HAS_PCR (0) +/* @brief Has Oscillator Enable(bitfield CR[OSCE]). */ +#define FSL_FEATURE_RTC_HAS_NO_CR_OSCE (1) + +/* ADC12 module features */ + +/* @brief Has DMA support (bit SC2[DMAEN]. */ +#define FSL_FEATURE_ADC12_HAS_DMA_SUPPORT (1) +/* @brief Conversion control count (related to number of registers SC1n and Rn). */ +#define FSL_FEATURE_ADC12_CONVERSION_CONTROL_COUNT (24) + +#endif /* _S32K148_FEATURES_H_ */ diff --git a/s32/mcux/devices/S32K148/device_CMSIS.cmake b/s32/mcux/devices/S32K148/device_CMSIS.cmake new file mode 100644 index 000000000..d1460aa40 --- /dev/null +++ b/s32/mcux/devices/S32K148/device_CMSIS.cmake @@ -0,0 +1,12 @@ +include_guard(GLOBAL) +message("device_CMSIS component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + # nothing to build +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/. +) + +include(CMSIS_Include_core_cm) diff --git a/s32/mcux/devices/S32K148/device_system.cmake b/s32/mcux/devices/S32K148/device_system.cmake new file mode 100644 index 000000000..86fc2336e --- /dev/null +++ b/s32/mcux/devices/S32K148/device_system.cmake @@ -0,0 +1,10 @@ +include_guard(GLOBAL) +message("device_system component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + # nothing to build +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + # nothing to include +) diff --git a/s32/mcux/devices/S32K148/drivers/driver_memory.cmake b/s32/mcux/devices/S32K148/drivers/driver_memory.cmake new file mode 100644 index 000000000..9a3e27b0b --- /dev/null +++ b/s32/mcux/devices/S32K148/drivers/driver_memory.cmake @@ -0,0 +1,10 @@ +include_guard(GLOBAL) +message("driver_memory component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + # nothing to build +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/. +) diff --git a/s32/mcux/devices/S32K148/drivers/driver_reset.cmake b/s32/mcux/devices/S32K148/drivers/driver_reset.cmake new file mode 100644 index 000000000..2b6dfc6d4 --- /dev/null +++ b/s32/mcux/devices/S32K148/drivers/driver_reset.cmake @@ -0,0 +1,10 @@ +include_guard(GLOBAL) +message("driver_reset component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + # nothing to build +) + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/. +) diff --git a/s32/mcux/devices/S32K148/drivers/fsl_clock.h b/s32/mcux/devices/S32K148/drivers/fsl_clock.h new file mode 100644 index 000000000..9f6c08148 --- /dev/null +++ b/s32/mcux/devices/S32K148/drivers/fsl_clock.h @@ -0,0 +1,12 @@ +/* + * Copyright 2023 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_CLOCK_H_ +#define _FSL_CLOCK_H_ + +#include "fsl_common.h" + +#endif /* _FSL_CLOCK_H_ */ diff --git a/s32/mcux/devices/S32K148/fsl_device_registers.h b/s32/mcux/devices/S32K148/fsl_device_registers.h new file mode 100644 index 000000000..6f8b38c36 --- /dev/null +++ b/s32/mcux/devices/S32K148/fsl_device_registers.h @@ -0,0 +1,32 @@ +/* + * Copyright 2023 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __FSL_DEVICE_REGISTERS_H__ +#define __FSL_DEVICE_REGISTERS_H__ + +/* + * Include the cpu specific register header files. + * + * The CPU macro should be declared in the project or makefile. + */ + +#if defined(CPU_S32K148) + +/* CMSIS-style register definitions */ +#include +#include "S32K148_device.h" + +/* CPU specific feature definitions */ +#include "S32K148_features.h" + +/* Needed for MCUX fsl_common.h */ +#include "core_cm4.h" + +#else + #error "No valid CPU defined!" +#endif + +#endif /* __FSL_DEVICE_REGISTERS_H__ */ diff --git a/s32/soc/s32k148/CMakeLists.txt b/s32/soc/s32k148/CMakeLists.txt new file mode 100644 index 000000000..ac3dd682e --- /dev/null +++ b/s32/soc/s32k148/CMakeLists.txt @@ -0,0 +1,4 @@ +# Copyright 2023 NXP +# SPDX-License-Identifier: BSD-3-Clause + +zephyr_include_directories(include) diff --git a/s32/soc/s32k148/include/Clock_Ip_Cfg.h b/s32/soc/s32k148/include/Clock_Ip_Cfg.h new file mode 100644 index 000000000..d83f8b8ea --- /dev/null +++ b/s32/soc/s32k148/include/Clock_Ip_Cfg.h @@ -0,0 +1,117 @@ +/* + * Copyright 2023 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/** +* @file Clock_Ip_Cfg.h +* @version 2.0.0 +* +* @brief AUTOSAR Mcu - Clock configuration header file. +* @details This file is the header containing all the necessary information for CLOCK +* module configuration(s). +* +* @addtogroup CLOCK_DRIVER_CONFIGURATION Clock Driver +* @{ +*/ + +#ifndef CLOCK_IP_CFG_H +#define CLOCK_IP_CFG_H + + +#ifdef __cplusplus +extern "C"{ +#endif + + +/*================================================================================================== + INCLUDE FILES + 1) system and project includes + 2) needed interfaces from external units + 3) internal and external interfaces from this unit +==================================================================================================*/ + +/*================================================================================================== +* SOURCE FILE VERSION INFORMATION +==================================================================================================*/ +#define CLOCK_IP_CFG_VENDOR_ID 43 +#define CLOCK_IP_CFG_AR_RELEASE_MAJOR_VERSION 4 +#define CLOCK_IP_CFG_AR_RELEASE_MINOR_VERSION 7 +#define CLOCK_IP_CFG_AR_RELEASE_REVISION_VERSION 0 +#define CLOCK_IP_CFG_SW_MAJOR_VERSION 2 +#define CLOCK_IP_CFG_SW_MINOR_VERSION 0 +#define CLOCK_IP_CFG_SW_PATCH_VERSION 0 + +/*================================================================================================== +* FILE VERSION CHECKS +==================================================================================================*/ +/*================================================================================================== + DEFINES AND MACROS +==================================================================================================*/ +/** +* @brief Pre-processor switch for enabling the default error detection and reporting to the DET. +* The detection of default errors is configurable (ON / OFF) at pre-compile time. +*/ +#define CLOCK_IP_DEV_ERROR_DETECT (STD_OFF) + +#define CLOCK_IP_TIMEOUT_TYPE (OSIF_COUNTER_DUMMY) + +#define CLOCK_IP_TIMEOUT_VALUE_US (50000) + +/** +* @brief Support for User mode. +* If this parameter has been configured to 'TRUE' the Clock can be executed from both supervisor and user mode. +*/ +#define CLOCK_IP_ENABLE_USER_MODE_SUPPORT (STD_OFF) + +/** Check the driver user mode is enabled only when the MCAL_ENABLE_USER_MODE_SUPPORT is enabled */ +#ifndef MCAL_ENABLE_USER_MODE_SUPPORT + #if (STD_ON == CLOCK_IP_ENABLE_USER_MODE_SUPPORT) + #error MCAL_ENABLE_USER_MODE_SUPPORT is not enabled. For running Clock in user mode the MCAL_ENABLE_USER_MODE_SUPPORT needs to be defined. + #endif /* (STD_ON == CLOCK_IP_ENABLE_USER_MODE_SUPPORT) */ +#endif /* ifndef MCAL_ENABLE_USER_MODE_SUPPORT */ + +/*================================================================================================== + ENUMS +==================================================================================================*/ + + + +/*================================================================================================== + STRUCTURES AND OTHER TYPEDEFS +==================================================================================================*/ + +/*================================================================================================== +* FUNCTION PROTOTYPES +==================================================================================================*/ +#define MCU_START_SEC_CODE +#include "Mcu_MemMap.h" + +#define MCU_STOP_SEC_CODE +#include "Mcu_MemMap.h" + + +#define MCU_START_SEC_CONFIG_DATA_UNSPECIFIED +#include "Mcu_MemMap.h" + + +/* ************************************************************************* + * Configuration structure for Clock Configuration + * ************************************************************************* */ + +extern const Clock_Ip_ClockConfigType Clock_Ip_aClockConfig[]; + + +#define MCU_STOP_SEC_CONFIG_DATA_UNSPECIFIED +#include "Mcu_MemMap.h" + +#ifdef __cplusplus +} +#endif + +#endif /* CLOCK_IP_CFG_H */ + +/** @} */ + + diff --git a/s32/soc/s32k148/include/Clock_Ip_Cfg_Defines.h b/s32/soc/s32k148/include/Clock_Ip_Cfg_Defines.h new file mode 100644 index 000000000..1e784d471 --- /dev/null +++ b/s32/soc/s32k148/include/Clock_Ip_Cfg_Defines.h @@ -0,0 +1,301 @@ +/* + * Copyright 2023 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/** +* @file Clock_Ip_Cfg_Defines.h +* @version 2.0.0 +* +* @brief AUTOSAR Mcu - Post-Build(PB) configuration file code template. +* @details Code template for Post-Build(PB) configuration file generation. +* +* @addtogroup CLOCK_DRIVER_CONFIGURATION Clock Driver +* @{ +*/ + +#ifndef CLOCK_IP_CFG_DEFINES_H +#define CLOCK_IP_CFG_DEFINES_H + + +#ifdef __cplusplus +extern "C"{ +#endif + + +/*================================================================================================== + INCLUDE FILES + 1) system and project includes + 2) needed interfaces from external units + 3) internal and external interfaces from this unit +==================================================================================================*/ +#include "S32K148_SIM.h" +#include "S32K148_SCG.h" +#include "S32K148_PCC.h" +#include "S32K148_SMC.h" +#include "S32K148_QUADSPI.h" +/*================================================================================================== + SOURCE FILE VERSION INFORMATION +==================================================================================================*/ +#define CLOCK_IP_CFG_DEFINES_VENDOR_ID 43 +#define CLOCK_IP_CFG_DEFINES_AR_RELEASE_MAJOR_VERSION 4 +#define CLOCK_IP_CFG_DEFINES_AR_RELEASE_MINOR_VERSION 7 +#define CLOCK_IP_CFG_DEFINES_AR_RELEASE_REVISION_VERSION 0 +#define CLOCK_IP_CFG_DEFINES_SW_MAJOR_VERSION 2 +#define CLOCK_IP_CFG_DEFINES_SW_MINOR_VERSION 0 +#define CLOCK_IP_CFG_DEFINES_SW_PATCH_VERSION 0 + +/*================================================================================================== + DEFINES AND MACROS +==================================================================================================*/ +/** +* @brief Derivative used. +*/ +#define CLOCK_IP_S32K148 +/** +* @brief HW sseries used. +*/ +#define CLOCK_IP_S32K1 +/** +* @brief Max number of internal oscillators +*/ +#define CLOCK_IP_IRCOSCS_COUNT (2U) + +/** +* @brief Max number of external oscillators +*/ +#define CLOCK_IP_XOSCS_COUNT (1U) + +/** +* @brief Max number of pll devices +*/ +#define CLOCK_IP_PLLS_COUNT (1U) + +/** +* @brief Max number of selectors +*/ +#define CLOCK_IP_SELECTORS_COUNT (38U) + +/** +* @brief Max number of dividers +*/ +#define CLOCK_IP_DIVIDERS_COUNT (21U) + +/** +* @brief Max number of divider triggers +*/ +#define CLOCK_IP_DIVIDER_TRIGGERS_COUNT (0U) + +/** +* @brief Max number of fractional dividers +*/ +#define CLOCK_IP_FRACTIONAL_DIVIDERS_COUNT (0U) + +/** +* @brief Max number of external clocks +*/ +#define CLOCK_IP_EXT_CLKS_COUNT (4U) + +/** +* @brief Max number of pcfs +*/ +#define CLOCK_IP_PCFS_COUNT (0U) + +/** +* @brief Max number of clock gates +*/ +#define CLOCK_IP_GATES_COUNT (50U) + +/** +* @brief Max number of clock monitoring units +*/ +#define CLOCK_IP_CMUS_COUNT (0U) + +/** +* @brief Max number of configured frequencies values +*/ +#define CLOCK_IP_CONFIGURED_FREQUENCIES_COUNT (1U) + +/** +* @brief Max number of specific peripheral (eMIOS) units +*/ +#define CLOCK_IP_SPECIFIC_PERIPH_COUNT (0U) + +/** +* @brief Supported power mode. +*/ +#define CLOCK_IP_HAS_RUN_MODE 0U + +#define CLOCK_IP_LPO_128K_FREQUENCY 128000U + +#define CLOCK_IP_FIRC_FREQUENCY 48000000U + +#define CLOCK_IP_SIRC_FREQUENCY 8000000U + +#define CLOCK_IP_DEFAULT_SOSC_FREQUENCY 40000000U + +#define CLOCK_IP_HAS_LOW_GAIN 0U + +#define CLOCK_IP_HAS_HIGH_GAIN 1U + +#define CLOCK_IP_HAS_MONITOR_DISABLE 0U + +#define CLOCK_IP_HAS_MONITOR_INT 1U + +#define CLOCK_IP_HAS_MONITOR_RESET 2U + +#define CLOCK_IP_HAS_SAFE_CLOCK_DISABLEMENT 1U + +#if CLOCK_IP_CMUS_COUNT > 0U +/** +* @brief Cmu formula constant values. +*/ +#define CLOCK_IP_FEATURE_OFFSET_REFERENCE_COUNT_FORMULA1 1U +#define CLOCK_IP_FEATURE_MULTIPLIER_REFERENCE_COUNT_FORMULA1 3U +#define CLOCK_IP_FEATURE_OFFSET_REFERENCE_COUNT_FORMULA2 7U +#define CLOCK_IP_FEATURE_MULTIPLIER_REFERENCE_COUNT_FORMULA2 3U +#endif + +/** +* @brief Clock ip supports clock frequency. +*/ +#define CLOCK_IP_GET_FREQUENCY_API (STD_ON) + +/** +* @brief Supports wait states configuration +*/ +#define CLOCK_IP_SUPPORTS_WAIT_STATES STD_OFF + + +/** +* @brief Clock ip supports power mode change notification +*/ +#define CLOCK_IP_POWER_MODE_CHANGE_NOTIFICATION STD_ON + + +/** +* @brief Supported clocks. +*/ +#define CLOCK_IP_HAS_LPO_128K_CLK 1U +#define CLOCK_IP_HAS_SIRC_CLK 2U +#define CLOCK_IP_HAS_SIRC_VLP_CLK 3U +#define CLOCK_IP_HAS_SIRC_STOP_CLK 4U +#define CLOCK_IP_HAS_FIRC_CLK 5U +#define CLOCK_IP_HAS_FIRC_VLP_CLK 6U +#define CLOCK_IP_HAS_FIRC_STOP_CLK 7U +#define CLOCK_IP_HAS_SOSC_CLK 8U +#define CLOCK_IP_HAS_SPLL_CLK 9U +#define CLOCK_IP_HAS_SIRCDIV1_CLK 10U +#define CLOCK_IP_HAS_SIRCDIV2_CLK 11U +#define CLOCK_IP_HAS_FIRCDIV1_CLK 12U +#define CLOCK_IP_HAS_FIRCDIV2_CLK 13U +#define CLOCK_IP_HAS_SOSCDIV1_CLK 14U +#define CLOCK_IP_HAS_SOSCDIV2_CLK 15U +#define CLOCK_IP_HAS_SPLLDIV1_CLK 16U +#define CLOCK_IP_HAS_SPLLDIV2_CLK 17U +#define CLOCK_IP_HAS_LPO_32K_CLK 18U +#define CLOCK_IP_HAS_LPO_1K_CLK 19U +#define CLOCK_IP_HAS_TCLK0_REF_CLK 20U +#define CLOCK_IP_HAS_TCLK1_REF_CLK 21U +#define CLOCK_IP_HAS_TCLK2_REF_CLK 22U +#define CLOCK_IP_HAS_RTC_CLKIN 23U +#define CLOCK_IP_HAS_SCS_CLK 24U +#define CLOCK_IP_HAS_SCS_RUN_CLK 25U +#define CLOCK_IP_HAS_SCS_VLPR_CLK 26U +#define CLOCK_IP_HAS_SCS_HSRUN_CLK 27U +#define CLOCK_IP_HAS_CORE_CLK 28U +#define CLOCK_IP_HAS_CORE_RUN_CLK 29U +#define CLOCK_IP_HAS_CORE_VLPR_CLK 30U +#define CLOCK_IP_HAS_CORE_HSRUN_CLK 31U +#define CLOCK_IP_HAS_BUS_CLK 32U +#define CLOCK_IP_HAS_BUS_RUN_CLK 33U +#define CLOCK_IP_HAS_BUS_VLPR_CLK 34U +#define CLOCK_IP_HAS_BUS_HSRUN_CLK 35U +#define CLOCK_IP_HAS_SLOW_CLK 36U +#define CLOCK_IP_HAS_SLOW_RUN_CLK 37U +#define CLOCK_IP_HAS_SLOW_VLPR_CLK 38U +#define CLOCK_IP_HAS_SLOW_HSRUN_CLK 39U +#define CLOCK_IP_HAS_RTC_CLK 40U +#define CLOCK_IP_HAS_LPO_CLK 41U +#define CLOCK_IP_HAS_SCG_CLKOUT_CLK 42U +#define CLOCK_IP_HAS_FTM0_EXT_CLK 43U +#define CLOCK_IP_HAS_FTM1_EXT_CLK 44U +#define CLOCK_IP_HAS_FTM2_EXT_CLK 45U +#define CLOCK_IP_HAS_FTM3_EXT_CLK 46U +#define CLOCK_IP_HAS_FTM4_EXT_CLK 47U +#define CLOCK_IP_HAS_FTM5_EXT_CLK 48U +#define CLOCK_IP_HAS_FTM6_EXT_CLK 49U +#define CLOCK_IP_HAS_FTM7_EXT_CLK 50U +#define CLOCK_IP_FEATURE_PRODUCERS_NO 51U +#define CLOCK_IP_HAS_ADC0_CLK 52U +#define CLOCK_IP_HAS_ADC1_CLK 53U +#define CLOCK_IP_HAS_CLKOUT0_CLK 54U +#define CLOCK_IP_HAS_CMP0_CLK 55U +#define CLOCK_IP_HAS_CRC0_CLK 56U +#define CLOCK_IP_HAS_DMA0_CLK 57U +#define CLOCK_IP_HAS_DMAMUX0_CLK 58U +#define CLOCK_IP_HAS_EIM0_CLK 59U +#define CLOCK_IP_HAS_ENET_CLK 60U +#define CLOCK_IP_HAS_ERM0_CLK 61U +#define CLOCK_IP_HAS_EWM0_CLK 62U +#define CLOCK_IP_HAS_FLEXCAN0_CLK 63U +#define CLOCK_IP_HAS_FLEXCAN1_CLK 64U +#define CLOCK_IP_HAS_FLEXCAN2_CLK 65U +#define CLOCK_IP_HAS_FlexIO_CLK 66U +#define CLOCK_IP_HAS_FTFC_CLK 67U +#define CLOCK_IP_HAS_FTM0_CLK 68U +#define CLOCK_IP_HAS_FTM1_CLK 69U +#define CLOCK_IP_HAS_FTM2_CLK 70U +#define CLOCK_IP_HAS_FTM3_CLK 71U +#define CLOCK_IP_HAS_FTM4_CLK 72U +#define CLOCK_IP_HAS_FTM5_CLK 73U +#define CLOCK_IP_HAS_FTM6_CLK 74U +#define CLOCK_IP_HAS_FTM7_CLK 75U +#define CLOCK_IP_HAS_LPI2C0_CLK 76U +#define CLOCK_IP_HAS_LPI2C1_CLK 77U +#define CLOCK_IP_HAS_LPIT0_CLK 78U +#define CLOCK_IP_HAS_LPSPI0_CLK 79U +#define CLOCK_IP_HAS_LPSPI1_CLK 80U +#define CLOCK_IP_HAS_LPSPI2_CLK 81U +#define CLOCK_IP_HAS_LPTMR0_CLK 82U +#define CLOCK_IP_HAS_LPUART0_CLK 83U +#define CLOCK_IP_HAS_LPUART1_CLK 84U +#define CLOCK_IP_HAS_LPUART2_CLK 85U +#define CLOCK_IP_HAS_MPU0_CLK 86U +#define CLOCK_IP_HAS_MSCM0_CLK 87U +#define CLOCK_IP_HAS_PDB0_CLK 88U +#define CLOCK_IP_HAS_PDB1_CLK 89U +#define CLOCK_IP_HAS_PORTA_CLK 90U +#define CLOCK_IP_HAS_PORTB_CLK 91U +#define CLOCK_IP_HAS_PORTC_CLK 92U +#define CLOCK_IP_HAS_PORTD_CLK 93U +#define CLOCK_IP_HAS_PORTE_CLK 94U +#define CLOCK_IP_HAS_QSPI_CLK 95U +#define CLOCK_IP_HAS_QSPI_SFIF_CLK_HYP_PREMUX_CLK 96U +#define CLOCK_IP_HAS_QSPI_SFIF_CLK 97U +#define CLOCK_IP_HAS_QSPI_2xSFIF_CLK 98U +#define CLOCK_IP_HAS_RTC0_CLK 99U +#define CLOCK_IP_HAS_SAI0_CLK 100U +#define CLOCK_IP_HAS_SAI1_CLK 101U +#define CLOCK_IP_HAS_TRACE_CLK 102U +#define CLOCK_IP_FEATURE_NAMES_NO 103U + +/*================================================================================================== + ENUMS +==================================================================================================*/ + + +/*================================================================================================== + STRUCTURES AND OTHER TYPEDEFS +==================================================================================================*/ + + + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef CLOCK_IP_CFG_DEFINES_H */ + +/** @} */ diff --git a/s32/soc/s32k148/include/OsIf_ArchCfg.h b/s32/soc/s32k148/include/OsIf_ArchCfg.h new file mode 100644 index 000000000..9643c8434 --- /dev/null +++ b/s32/soc/s32k148/include/OsIf_ArchCfg.h @@ -0,0 +1,89 @@ +/* + * Copyright 2023 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/** +* @file OsIf_ArchCfg.h +* +* @version 2.0.0 +* +* +* @addtogroup OSIF_DRIVER +* @{ +*/ + +#ifndef OSIF_ARCHCFG_H +#define OSIF_ARCHCFG_H + +#ifdef __cplusplus +extern "C"{ +#endif + +/*================================================================================================== + INCLUDE FILES + 1) system and project includes + 2) needed interfaces from external units + 3) internal and external interfaces from this unit +==================================================================================================*/ + +/*================================================================================================== +* SOURCE FILE VERSION INFORMATION +==================================================================================================*/ +#define OSIF_ARCHCFG_VENDOR_ID 43 +#define OSIF_ARCHCFG_AR_RELEASE_MAJOR_VERSION 4 +#define OSIF_ARCHCFG_AR_RELEASE_MINOR_VERSION 7 +#define OSIF_ARCHCFG_AR_RELEASE_REVISION_VERSION 0 +#define OSIF_ARCHCFG_SW_MAJOR_VERSION 2 +#define OSIF_ARCHCFG_SW_MINOR_VERSION 0 +#define OSIF_ARCHCFG_SW_PATCH_VERSION 0 + +/*================================================================================================== +* FILE VERSION CHECKS +==================================================================================================*/ + +/*================================================================================================== +* CONSTANTS +==================================================================================================*/ +#define MCAL_ARM_MARCH (16) /* for ARM M4 Thumb2 */ +#define MCAL_ARM_AARCH32 (32) /* for ARM ARCH32 */ +#define MCAL_ARM_AARCH64 (64) /* for ARM ARCH64 */ +#define MCAL_ARM_RARCH (52) /* for ARM R platform */ + +/*================================================================================================== +* DEFINES AND MACROS +==================================================================================================*/ +/* ARM_MARCH - is used to specify the ARM architecture MCAL_MARCH, MCAL_RARCH, MCAL_AARCH32, MCAL_AARCH64 */ +#define MCAL_PLATFORM_ARM MCAL_ARM_MARCH + + + + +/*================================================================================================== +* ENUMS +==================================================================================================*/ + +/*================================================================================================== +* STRUCTURES AND OTHER TYPEDEFS +==================================================================================================*/ + +/*================================================================================================== +* GLOBAL VARIABLE DECLARATIONS +==================================================================================================*/ + +/*================================================================================================== + GLOBAL CONSTANTS +==================================================================================================*/ + +/*================================================================================================== +* FUNCTION PROTOTYPES +==================================================================================================*/ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* OSIF_ARCHCFG_H */ +/** @} */ + diff --git a/s32/soc/s32k148/include/OsIf_Cfg.h b/s32/soc/s32k148/include/OsIf_Cfg.h new file mode 100644 index 000000000..57fd02aa6 --- /dev/null +++ b/s32/soc/s32k148/include/OsIf_Cfg.h @@ -0,0 +1,132 @@ +/* + * Copyright 2023 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/** +* @file OsIf_Cfg.h +* @version 2.0.0 +* +* +* @addtogroup OSIF_DRIVER +* @{ +*/ + +#ifndef OSIF_CFG_H +#define OSIF_CFG_H + +#ifdef __cplusplus +extern "C"{ +#endif + +/*================================================================================================== + INCLUDE FILES + 1) system and project includes + 2) needed interfaces from external units + 3) internal and external interfaces from this unit +==================================================================================================*/ +#include "OsIf_ArchCfg.h" +#include "StandardTypes.h" +#include "S32K148_SYSTICK.h" +/*================================================================================================== +* SOURCE FILE VERSION INFORMATION +==================================================================================================*/ +#define OSIF_CFG_VENDOR_ID 43 +#define OSIF_CFG_AR_RELEASE_MAJOR_VERSION 4 +#define OSIF_CFG_AR_RELEASE_MINOR_VERSION 7 +#define OSIF_CFG_AR_RELEASE_REVISION_VERSION 0 +#define OSIF_CFG_SW_MAJOR_VERSION 2 +#define OSIF_CFG_SW_MINOR_VERSION 0 +#define OSIF_CFG_SW_PATCH_VERSION 0 + +/*================================================================================================== +* FILE VERSION CHECKS +==================================================================================================*/ +/* Check if OsIf_Cfg.h file and OsIf_ArchCfg.h file are of the same vendor */ +#if (OSIF_CFG_VENDOR_ID != OSIF_ARCHCFG_VENDOR_ID) + #error "OsIf_Cfg.h and OsIf_ArchCfg.h have different vendor ids" +#endif +/* Check if OsIf_Cfg.h file and OsIf_ArchCfg.h file are of the same Autosar version */ +#if ((OSIF_CFG_AR_RELEASE_MAJOR_VERSION != OSIF_ARCHCFG_AR_RELEASE_MAJOR_VERSION) || \ + (OSIF_CFG_AR_RELEASE_MINOR_VERSION != OSIF_ARCHCFG_AR_RELEASE_MINOR_VERSION) || \ + (OSIF_CFG_AR_RELEASE_REVISION_VERSION != OSIF_ARCHCFG_AR_RELEASE_REVISION_VERSION)) + #error "AUTOSAR Version Numbers of OsIf_Cfg.h and OsIf_ArchCfg.h are different" +#endif +/* Check if OsIf_Cfg.h file and OsIf_ArchCfg.h file are of the same Software version */ +#if ((OSIF_CFG_SW_MAJOR_VERSION != OSIF_ARCHCFG_SW_MAJOR_VERSION) || \ + (OSIF_CFG_SW_MINOR_VERSION != OSIF_ARCHCFG_SW_MINOR_VERSION) || \ + (OSIF_CFG_SW_PATCH_VERSION != OSIF_ARCHCFG_SW_PATCH_VERSION)) + #error "Software Version Numbers of OsIf_Cfg.h and OsIf_ArchCfg.h are different" +#endif + +/* Check if OsIf_Cfg.h file and StandardTypes.h file are of the same Autosar version */ +#ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK + #if ((OSIF_CFG_AR_RELEASE_MAJOR_VERSION != STD_AR_RELEASE_MAJOR_VERSION) || \ + (OSIF_CFG_AR_RELEASE_MINOR_VERSION != STD_AR_RELEASE_MINOR_VERSION)) + #error "AutoSar Version Numbers of OsIf_Cfg.h and StandardTypes.h are different" + #endif +#endif /* DISABLE_MCAL_INTERMODULE_ASR_CHECK */ +/*================================================================================================== +* CONSTANTS +==================================================================================================*/ + +/*================================================================================================== +* DEFINES AND MACROS +==================================================================================================*/ +/* General OSIF configuration */ +#define OSIF_MODULE_ID (255U) + +#define OSIF_DRIVER_INSTANCE (255U) + +#define OSIF_ENABLE_USER_MODE_SUPPORT (STD_OFF) + +#ifndef MCAL_ENABLE_USER_MODE_SUPPORT + #if (STD_ON == OSIF_ENABLE_USER_MODE_SUPPORT) + #error MCAL_ENABLE_USER_MODE_SUPPORT is not enabled. For running OsIf in user mode, MCAL_ENABLE_USER_MODE_SUPPORT needs to be defined. + #endif /* (STD_ON == OSIF_ENABLE_USER_MODE_SUPPORT */ +#endif /* ifndef MCAL_ENABLE_USER_MODE_SUPPORT */ + +#define OSIF_ENABLE_MULTICORE_SUPPORT (STD_OFF) + +#define OSIF_MAX_COREIDX_SUPPORTED (1U) + +#define OSIF_DEV_ERROR_DETECT (STD_OFF) + +#define USING_OS_ZEPHYR + +#define OSIF_USE_SYSTEM_TIMER (STD_OFF) + +#define OSIF_USE_CUSTOM_TIMER (STD_OFF) + +/* Autosar OS Specific */ + +/* Baremetal Specific */ + +/*================================================================================================== +* ENUMS +==================================================================================================*/ + +/*================================================================================================== +* STRUCTURES AND OTHER TYPEDEFS +==================================================================================================*/ + +/*================================================================================================== +* GLOBAL VARIABLE DECLARATIONS +==================================================================================================*/ + +/*================================================================================================== + GLOBAL CONSTANTS +==================================================================================================*/ + +/*================================================================================================== +* FUNCTION PROTOTYPES +==================================================================================================*/ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* OSIF_CFG_H */ +/** @} */ + diff --git a/s32/soc/s32k148/include/Soc_Ips.h b/s32/soc/s32k148/include/Soc_Ips.h new file mode 100644 index 000000000..ee72281ad --- /dev/null +++ b/s32/soc/s32k148/include/Soc_Ips.h @@ -0,0 +1,265 @@ +/* + * Copyright 2023 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SOC_IPS_H +#define SOC_IPS_H + +/** +* @file Soc_Ips.h +* +* @addtogroup BASENXP_COMPONENT +* @{ +*/ + +#ifdef __cplusplus +extern "C"{ +#endif + + +/*================================================================================================== +* INCLUDE FILES +* 1) system and project includes +* 2) needed interfaces from external units +* 3) internal and external interfaces from this unit +==================================================================================================*/ +#include "Platform_Types.h" +#include "IpVersionMacros.h" + +/*================================================================================================== +* SOURCE FILE VERSION INFORMATION +==================================================================================================*/ +#define SOC_IPS_VENDOR_ID 43 +#define SOC_IPS_MODULE_ID 0 +#define SOC_IPS_AR_RELEASE_MAJOR_VERSION 4 +#define SOC_IPS_AR_RELEASE_MINOR_VERSION 7 +#define SOC_IPS_AR_RELEASE_REVISION_VERSION 0 +#define SOC_IPS_SW_MAJOR_VERSION 2 +#define SOC_IPS_SW_MINOR_VERSION 0 +#define SOC_IPS_SW_PATCH_VERSION 0 + +/*================================================================================================== +* FILE VERSION CHECKS +==================================================================================================*/ +#ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK + /* Check if source file and Platform_Types.h header file are of the same Autosar version */ + #if ((SOC_IPS_AR_RELEASE_MAJOR_VERSION != PLATFORM_AR_RELEASE_MAJOR_VERSION) || \ + (SOC_IPS_AR_RELEASE_MINOR_VERSION != PLATFORM_AR_RELEASE_MINOR_VERSION)) + #error "AutoSar Version Numbers of Soc_Ips.h and Platform_Types.h are different" + #endif + + /* Check if source file and IpVersionMacros.h header file are of the same Autosar version */ + #if ((SOC_IPS_AR_RELEASE_MAJOR_VERSION != IPVERSIONMACROS_AR_RELEASE_MAJOR_VERSION) || \ + (SOC_IPS_AR_RELEASE_MINOR_VERSION != IPVERSIONMACROS_AR_RELEASE_MINOR_VERSION)) + #error "AutoSar Version Numbers of Soc_Ips.h and IpVersionMacros.h are different" + #endif +#endif + +/*================================================================================================== +* CONSTANTS +==================================================================================================*/ +/* 40 = 0x28 = CORTEXM_PLATFORM + * 02 = 0x02 = S32K1 DERIVATIVE ID + * 13 = 0x0C = Rev. 13 + * 00 = 0x00 = Not a Draft (A-B-C-D-E-F-G-H-I-J-K-L-M-N-O-P-Q-R-S-T-U-V-W-X-Y-Z) +*/ + +/** +* @brief PMC IP Version: PMC v03.00.01.00 +* @details S32K14X IP Versions +*/ +#define IPV_PMC (0x28020C00UL) + + +/** +* @brief PIT_RTI IP Version: PIT_RTI v05.00.06.11 +* @details S32K14X IP Versions +*/ +#define IPV_PIT (0x28020C00UL) + + +/** +* @brief RTC IP Version: RTC 00.00.03.06 +* @details S32K14X IP Versions +*/ +#define IPV_RTC (0x28020C00UL) + + +/** +* @brief ADCDIG IP Version: v00.00.18.00 +* @details S32K14X IP Versions +*/ +#define IPV_ADCDIG (0x28020C00UL) + + +/** +* @brief SIUL2 IP Version: v00.00.00.10 +* @details S32K14X IP Versions +*/ +#define IPV_SIULV2 (0x28020C00UL) + +/** +* @brief MC IP Version: D_IP_magic_carpet_SYN_302 [v07.00.02.03] +* @details S32K14X IP Versions +*/ +#define IPV_MC (0x28020C00UL) + +/** +* @brief PLLDIG IP Version: DA_IP_PLL_SYS_C40ESF3_008 [v00.00.03.04] +* @details S32K14X IP Versions +*/ +#define IPV_PLLDIG (0x28020C00UL) + +/** +* @brief FXOSC IP Version: DA_IP_FXOSC_C [v40.00.00.02.05] +* @details S32K14X IP Versions +*/ +#define IPV_FXOSC (0x28020C00UL) + +/** +* @brief FIRC IP Version: D_IP_FIRC_SYN_SPEC [v00.00.00.21] +* @details S32K14X IP Versions +*/ +#define IPV_FIRC (0x28020C00UL) + +/** +* @brief GMAC IP Version: D_IP_3P_ENET_MAC_SYN_017 [v02.00.00.08] +* @details S32K14X IP Versions +*/ +#define IPV_GMAC (0x28020C00UL) + +/** +* @brief C40ASF IP Version: M_IP_c40asf_spec [v00.00.00.04] +* @details S32K14X IP Versions +*/ +#define IPV_C40ASF (0x28020C00UL) + +/** +* @brief PFLASH IP Version: pflash_c40asf_s32k_spec [v00.00.00.11] +* @details S32K14X IP Versions +*/ +#define IPV_PFLASH (0x28020C00UL) + +/** +* @brief C40ASF IP Version: M_IP_c40asf_spec [v00.00.00.04] +* @details S32K14X IP Versions +*/ +#define IPV_FLASH_ARRAY (0x28020C00UL) + +/** +* @brief PFLASH IP Version: pflash_c40asf_s32k_spec [v00.00.00.11] +* @details S32K14X IP Versions +*/ +#define IPV_FLASH_CONTROLLER (0x28020C00UL) + +/** +* @brief QSPI IP Version: QSPI d_ip_quadspi_v2_sync_spec.025 +* @details S32K14X IP Versions +*/ +#define IPV_QSPI (0x28020C00UL) + +/** +* @brief Clock Monitoring Unit Frequency Check (CMU_FC) IP Version +* @details S32K14X IP Versions +*/ +#define IPV_CMU_FC (0x28020C00UL) + +/** +* @brief Flexible I/O (FLEXIO) IP Version +* @details S32K14X IP Versions +*/ +#define IPV_FLEXIO (0x28020C00UL) + +/*================================================================================================== +* REGISTER PROTECTION (REG_PROT) +==================================================================================================*/ +/** +* @brief Register Protection IP Version +* @details S32K14X IP Versions +*/ +#define IPV_REG_PROT (0x28020C00UL) + +/*================================================================================================== +* Software Erratas for Hardware Erratas +==================================================================================================*/ +/** +* @brief Hardware errata for RTC: (e10716) +* @details e10716 RTC: Timer Alarm Flag can assert erroneously +*/ +#define ERR_IPV_RTC_ERR010716 (STD_ON) + +/** +* @brief Hardware errata for FTM: (e10856) +* @details e10856 FTM: Safe state is not removed from channel outputs after fault conditionends if SWOCTRL is being used to control the pin +*/ +#define ERR_IPV_FTM_ERR010856 (STD_ON) + + +/** +* @brief Hardware errata for FlexCAN: (e050246) +* @details e050246 FlexCAN: Receive Message Buffers may have its Code Field corrupted +* if the Receive FIFO function is used (same to E050443) +*/ +#define ERR_IPV_FLEXCAN_E050246 (STD_ON) + +/** +* @brief Hardware errata for SCG: (e010777) +* @details e010777 SCG: Corrupted status when the system clock is switching. +*/ +#define ERR_IPV_SCG_ERR010777 (STD_ON) + +/*================================================================================================== +* DEFINES AND MACROS +==================================================================================================*/ +/** +* @brief Enable CACHE management feature +* @details Global define to enable CACHE management at runtime +*/ +#define MCAL_CACHE_RUNTIME_MNGMNT (STD_ON) + +/** +* @brief number of EMIOS channels per each interrupt +* @details S32K14X Platform specific Defines/Configurations for EMIOS. +* Can be 1U, 2U, 4U, etc.. depending on the platform +*/ +#define EMIOS_CHANNELS_PER_INTERRUPT (4U) + +/* ARM sub-architecture cortex M4 */ +#define MCAL_PLATFORM_ARM_M4 + +/*================================================================================================== +* ENUMS +==================================================================================================*/ + + +/*================================================================================================== +* STRUCTURES AND OTHER TYPEDEFS +==================================================================================================*/ + + +/*================================================================================================== +* GLOBAL VARIABLE DECLARATIONS +==================================================================================================*/ +/** +* @brief User Mode feature is enabled +* @details User Mode feature - MCAL is configured to run in supervisor mode, by default. +*/ + +#ifdef MCAL_ENABLE_SUPERVISOR_MODE + #undef MCAL_ENABLE_USER_MODE_SUPPORT +#endif +/*================================================================================================== +* FUNCTION PROTOTYPES +==================================================================================================*/ + +#ifdef __cplusplus +} +#endif + + +/** @} */ + +#endif /* SOC_IPS_H */ + From fbfa00d6547258a65c971fa39fcc84e420317a98 Mon Sep 17 00:00:00 2001 From: "M. Elia" Date: Mon, 11 Nov 2024 18:25:21 +0100 Subject: [PATCH 2/2] added ENET peripheral --- s32/mcux/devices/S32K148/S32K148_device.h | 31 +++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/s32/mcux/devices/S32K148/S32K148_device.h b/s32/mcux/devices/S32K148/S32K148_device.h index 7e96ce4e2..5ae6e0e3f 100644 --- a/s32/mcux/devices/S32K148/S32K148_device.h +++ b/s32/mcux/devices/S32K148/S32K148_device.h @@ -827,4 +827,35 @@ typedef struct { * @} */ /* end of group ADC_Peripheral_Access_Layer */ + /* ---------------------------------------------------------------------------- + -- ENET Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer + * @{ + */ + + /* ENET - Peripheral instance base addresses */ +/** Peripheral ENET base address */ +#define ENET_BASE IP_ENET_BASE +/** Peripheral ENET base pointer */ +#define ENET IP_ENET +/** Array initializer of ENET peripheral base addresses */ +#define ENET_BASE_ADDRS IP_ENET_BASE_ADDRS +/** Array initializer of ENET peripheral base pointers */ +#define ENET_BASE_PTRS IP_ENET_BASE_PTRS +/** Interrupt vectors for the ENET peripheral type */ +#define ENET_Transmit_IRQS { ENET_TX_Buffer_IRQn } +#define ENET_Receive_IRQS { ENET_RX_Buffer_IRQn } +#define ENET_Error_IRQS { ENET_PRE_IRQn } +#define ENET_1588_Timer_IRQS { ENET_Timer_IRQn } +#define ENET_Ts_IRQS { ENET_Timer_IRQn } +/* ENET Buffer Descriptor and Buffer Address Alignment. */ +#define ENET_BUFF_ALIGNMENT (16U) + +/*! + * @} + */ /* end of group ENET_Peripheral_Access_Layer */ + #endif /* _S32K148_DEVICE_H_ */