From 51a04f828c70a020402afe6dc1cd00bab02ec011 Mon Sep 17 00:00:00 2001 From: Quy Tran Date: Tue, 20 Aug 2024 04:53:02 +0000 Subject: [PATCH 1/9] hal: renesas: Initial commit to support Renesas RX HAL layer This is initial commit to support Renesas RX with RX driver package (rdp) Signed-off-by: Quy Tran --- drivers/CMakeLists.txt | 1 + drivers/rx/CMakeLists.txt | 22 + drivers/rx/README | 34 + .../rdp/src/r_bsp/board/generic_rx130/r_bsp.h | 89 + .../rx/rdp/src/r_bsp/mcu/all/r_bsp_common.c | 245 + .../rx/rdp/src/r_bsp/mcu/all/r_bsp_common.h | 173 + .../rdp/src/r_bsp/mcu/all/r_bsp_interrupts.c | 1114 ++ .../rdp/src/r_bsp/mcu/all/r_bsp_interrupts.h | 87 + .../rx/rdp/src/r_bsp/mcu/all/r_rx_compiler.h | 1648 +++ .../r_bsp/mcu/all/r_rx_intrinsic_functions.c | 1254 ++ .../r_bsp/mcu/all/r_rx_intrinsic_functions.h | 991 ++ .../rx/rdp/src/r_bsp/mcu/rx130/mcu_clocks.c | 887 ++ .../rx/rdp/src/r_bsp/mcu/rx130/mcu_clocks.h | 57 + drivers/rx/rdp/src/r_bsp/mcu/rx130/mcu_info.h | 219 + drivers/rx/rdp/src/r_bsp/mcu/rx130/mcu_init.c | 168 + drivers/rx/rdp/src/r_bsp/mcu/rx130/mcu_init.h | 50 + .../rdp/src/r_bsp/mcu/rx130/mcu_interrupts.c | 207 + .../rdp/src/r_bsp/mcu/rx130/mcu_interrupts.h | 129 + .../mcu/rx130/register_access/gnuc/iodefine.h | 11700 ++++++++++++++++ drivers/rx/rdp/src/r_bsp/mcu/rx130/vecttbl.c | 132 + drivers/rx/rdp/src/r_bsp/mcu/rx130/vecttbl.h | 49 + drivers/rx/rdp/src/r_bsp/platform.h | 246 + zephyr/CMakeLists.txt | 1 + zephyr/rx/CMakeLists.txt | 3 + zephyr/rx/rdp_cfg/CMakeLists.txt | 4 + .../rx/rdp_cfg/r_config/rx130/r_bsp_config.h | 686 + 26 files changed, 20196 insertions(+) create mode 100644 drivers/rx/CMakeLists.txt create mode 100644 drivers/rx/README create mode 100644 drivers/rx/rdp/src/r_bsp/board/generic_rx130/r_bsp.h create mode 100644 drivers/rx/rdp/src/r_bsp/mcu/all/r_bsp_common.c create mode 100644 drivers/rx/rdp/src/r_bsp/mcu/all/r_bsp_common.h create mode 100644 drivers/rx/rdp/src/r_bsp/mcu/all/r_bsp_interrupts.c create mode 100644 drivers/rx/rdp/src/r_bsp/mcu/all/r_bsp_interrupts.h create mode 100644 drivers/rx/rdp/src/r_bsp/mcu/all/r_rx_compiler.h create mode 100644 drivers/rx/rdp/src/r_bsp/mcu/all/r_rx_intrinsic_functions.c create mode 100644 drivers/rx/rdp/src/r_bsp/mcu/all/r_rx_intrinsic_functions.h create mode 100644 drivers/rx/rdp/src/r_bsp/mcu/rx130/mcu_clocks.c create mode 100644 drivers/rx/rdp/src/r_bsp/mcu/rx130/mcu_clocks.h create mode 100644 drivers/rx/rdp/src/r_bsp/mcu/rx130/mcu_info.h create mode 100644 drivers/rx/rdp/src/r_bsp/mcu/rx130/mcu_init.c create mode 100644 drivers/rx/rdp/src/r_bsp/mcu/rx130/mcu_init.h create mode 100644 drivers/rx/rdp/src/r_bsp/mcu/rx130/mcu_interrupts.c create mode 100644 drivers/rx/rdp/src/r_bsp/mcu/rx130/mcu_interrupts.h create mode 100644 drivers/rx/rdp/src/r_bsp/mcu/rx130/register_access/gnuc/iodefine.h create mode 100644 drivers/rx/rdp/src/r_bsp/mcu/rx130/vecttbl.c create mode 100644 drivers/rx/rdp/src/r_bsp/mcu/rx130/vecttbl.h create mode 100644 drivers/rx/rdp/src/r_bsp/platform.h create mode 100644 zephyr/rx/CMakeLists.txt create mode 100644 zephyr/rx/rdp_cfg/CMakeLists.txt create mode 100644 zephyr/rx/rdp_cfg/r_config/rx130/r_bsp_config.h diff --git a/drivers/CMakeLists.txt b/drivers/CMakeLists.txt index a6156c37..36a6b1e8 100644 --- a/drivers/CMakeLists.txt +++ b/drivers/CMakeLists.txt @@ -1,3 +1,4 @@ # SPDX-License-Identifier: Apache-2.0 add_subdirectory_ifdef(CONFIG_HAS_RENESAS_RA_FSP ra) +add_subdirectory_ifdef(CONFIG_HAS_RENESAS_RX_RDP rx) diff --git a/drivers/rx/CMakeLists.txt b/drivers/rx/CMakeLists.txt new file mode 100644 index 00000000..3e9b6e4e --- /dev/null +++ b/drivers/rx/CMakeLists.txt @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: Apache-2.0 + +set(include_dirs + rdp_cfg + rdp_cfg/r_config + rdp/src/r_bsp + rdp/src/r_bsp/mcu + rdp/src/r_bsp/mcu/all + rdp/src/r_bsp/mcu/${CONFIG_SOC_SERIES} + rdp/src/r_bsp/mcu/${CONFIG_SOC_SERIES}/register_access/gnuc +) + +set(srcs + rdp/src/r_bsp/mcu/all/r_bsp_common.c + rdp/src/r_bsp/mcu/${CONFIG_SOC_SERIES}/mcu_clocks.c + rdp/src/r_bsp/mcu/${CONFIG_SOC_SERIES}/mcu_init.c +) + +zephyr_include_directories(${include_dirs}) +zephyr_library_sources(${srcs}) + +# Optional build base on feature configuration diff --git a/drivers/rx/README b/drivers/rx/README new file mode 100644 index 00000000..b05e2d7e --- /dev/null +++ b/drivers/rx/README @@ -0,0 +1,34 @@ +Firmware Integration Technology (FIT) +##################################### + +Origin: + Renesas Electronics Corporation + https://www.renesas.com/us/en/software-tool/fit + +Status: + version v1.44 + +Purpose: + Firmware Integration Technology (FIT) for Renesas RX MCU Family. + +Description: + This package is a snapshot from the RX FSP software released by Renesas Electronics Corporation + It contain the HAL and a set of CMSIS headers files for the Renesas RX MCUs + +Dependencies: + None. + +URL: + https://github.com/renesas/rx-driver-package + +Commit: + 04cc6a5ae3450fc7b00123635549e33fbf78458c + +Maintained-by: + Renesas Electronics Corporation + +License: + BSD-3-Clause + +License Link: + https://opensource.org/licenses/BSD-3-Clause diff --git a/drivers/rx/rdp/src/r_bsp/board/generic_rx130/r_bsp.h b/drivers/rx/rdp/src/r_bsp/board/generic_rx130/r_bsp.h new file mode 100644 index 00000000..37f5004d --- /dev/null +++ b/drivers/rx/rdp/src/r_bsp/board/generic_rx130/r_bsp.h @@ -0,0 +1,89 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2017 - 2024 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_bsp.h +* H/W Platform : GENERIC_RX130 +* Description : Has the header files that should be included for this platform. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 15.05.2017 1.00 First release +* : 28.02.2019 2.00 Added the following include path. +* - r_rx_compiler.h +* - r_rtos.h +* - r_bsp_interrupts.h +* - mcu_clocks.h +* - r_rx_intrinsic_functions.h +* Modified the following include path. +* - lowsrc.h +* - r_bsp_mcu_startup.h +* - vecttbl.h +* Added support for GNUC and ICCRX. +* Fixed coding style. +* : 08.10.2019 2.01 Added the following include path. +* - r_bsp_software_interrupt.h +* Changed include of r_bsp_config.h for added support of Renesas RTOS(RI600V4 or RI600PX). +* : 23.04.2021 2.02 Added the include of fsp_common_api.h and r_fsp_error.h. +* : 30.11.2021 2.03 Modified the include file. +***********************************************************************************************************************/ + +/* Make sure that no other platforms have already been defined. Do not touch this! */ +#ifdef PLATFORM_DEFINED +#error "Error - Multiple platforms defined in platform.h!" +#else +#define PLATFORM_DEFINED +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/*********************************************************************************************************************** +INCLUDE APPROPRIATE MCU AND BOARD FILES +***********************************************************************************************************************/ +#include "r_bsp_config.h" +#include "r_bsp_common.h" +#include "r_rx_compiler.h" + +#if defined(__CCRX__) +#include "register_access/ccrx/iodefine.h" +#elif defined(__GNUC__) +#include "iodefine.h" +#elif defined(__ICCRX__) +#include "register_access/iccrx/iodefine.h" +#endif /* defined(__CCRX__), defined(__GNUC__), defined(__ICCRX__) */ +#include "mcu_clocks.h" +#include "mcu_info.h" +#include "mcu_init.h" +#include "mcu_interrupts.h" +#include "vecttbl.h" + +#include "r_bsp_interrupts.h" +#include "r_rx_intrinsic_functions.h" + + +#ifdef __cplusplus +} +#endif + +#ifndef BSP_BOARD_GENERIC_RX130 +#define BSP_BOARD_GENERIC_RX130 + +#endif /* BSP_BOARD_GENERIC_RX130 */ + diff --git a/drivers/rx/rdp/src/r_bsp/mcu/all/r_bsp_common.c b/drivers/rx/rdp/src/r_bsp/mcu/all/r_bsp_common.c new file mode 100644 index 00000000..c8d699ea --- /dev/null +++ b/drivers/rx/rdp/src/r_bsp/mcu/all/r_bsp_common.c @@ -0,0 +1,245 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013 - 2024 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_bsp_common.c +* Description : Implements functions that apply to all r_bsp boards and MCUs. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 06.05.2013 1.00 First Release +* : 26.03.2014 1.10 Added R_BSP_SoftwareDelay() function +* : 03.09.2014 1.20 Corrected R_BSP_SoftwareDelay() timing when using an RX64M +* : 30.09.2015 1.30 Added RX23T +* : 01.02.2016 1.40 Added RX24T +* Changed the value of the following macro definition. +* - OVERHEAD_CYCLES +* - OVERHEAD_CYCLES_64 +* : 29.02.2016 1.50 Added RX230 +* : 01.10.2016 1.60 Added RX65N +* : 22.08.2016 1.70 Added RX24U +* : 15.05.2017 1.80 Changed method of selecting the number of CPU cycles required to execute +* the delayWait() loop. +* : 27.07.2018 1.90 Changed the value of the following macro definition, because added RX66T. +* - CPU_CYCLES_PER_LOOP +* : 28.02.2019 2.00 Deleted the following definition. +* (The following definition moved to the common file (mcu_info.h).) +* - CPU_CYCLES_PER_LOOP +* Added support for GNUC and ICCRX. +* Fixed coding style. +* Renamed following macro definitions. +* - BSP_PRV_OVERHEAD_CYCLES +* - BSP_PRV_OVERHEAD_CYCLES_64 +* - BSP_PRV_CKSEL_LOCO +* Renamed following function. +* - delay_wait +* : 26.07.2019 2.01 Modified comment of API function to Doxygen style. +* : 21.11.2023 2.02 Added the R_BSP_ClockReset_Bootloader function. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +/* Get information about current board and MCU. */ +#include "platform.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +#define BSP_PRV_OVERHEAD_CYCLES (2) /* R_BSP_SoftwareDelay() overhead per call */ +#define BSP_PRV_OVERHEAD_CYCLES_64 (2) /* R_BSP_SoftwareDelay() overhead per call using 64-bit ints */ + +#define BSP_PRV_CKSEL_LOCO (0x0) /* SCKCR3 register setting for LOCO */ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +/********************************************************************************************************************** + * Function Name: R_BSP_GetVersion + ******************************************************************************************************************//** + * @brief Returns the current version of the r_bsp. + * @return Version of the r_bsp. + * @details This function will return the version of the currently installed r_bsp. The version number is encoded + * where the top 2 bytes are the major version number and the bottom 2 bytes are the minor version number. For + * example, Version 4.25 would be returned as 0x00040019. + */ +uint32_t R_BSP_GetVersion (void) +{ + /* These version macros are defined in platform.h. */ + return ((((uint32_t)R_BSP_VERSION_MAJOR) << 16) | (uint32_t)R_BSP_VERSION_MINOR); +} /* End of function R_BSP_GetVersion() */ + + +/*********************************************************************************************************************** +* Function Name: delay_wait +* Description : This asm loop executes a known number (5) of CPU cycles. If a value of '4' is passed +* in as an argument, then this function would consume 20 CPU cycles before returning. +* Arguments : loop_cnt - A single 32-bit value is provided as the number of loops to execute. +* Return Value : None +***********************************************************************************************************************/ +R_BSP_PRAGMA_STATIC_INLINE_ASM(delay_wait) +void delay_wait (unsigned long loop_cnt) +{ + R_BSP_ASM_INTERNAL_USED(loop_cnt) + R_BSP_ASM_BEGIN + R_BSP_ASM( BRA.B R_BSP_ASM_LAB_NEXT(0) ) + R_BSP_ASM( NOP ) + R_BSP_ASM_LAB(0: ) + R_BSP_ASM( NOP ) + R_BSP_ASM( SUB #01H, R1 ) + R_BSP_ASM( BNE.B R_BSP_ASM_LAB_PREV(0) ) + R_BSP_ASM_END +} /* End of function delay_wait() */ + + +/********************************************************************************************************************** + * Function Name: R_BSP_GetIClkFreqHz + ******************************************************************************************************************//** + * @brief Returns the system clock frequency. + * @return System clock frequency specified by the r_bsp. + * @details This function returns the system clock frequency. For example, when the system clock is set to 120 MHz in + * r_bsp_config_h and the r_bsp has completed to specify the clock setting, then even if the user changed the system + * clock frequency to 60 MHz, the return value is '60000000'. + */ +uint32_t R_BSP_GetIClkFreqHz(void) +{ + return get_iclk_freq_hz(); // Get the MCU specific ICLK frequency +} /* End of function R_BSP_GetIClkFreqHz() */ + + +/********************************************************************************************************************** + * Function Name: R_BSP_SoftwareDelay + ******************************************************************************************************************//** + * @brief Delay the specified duration in units and return. + * @param[in] delay The number of 'units' to delay. + * @param[in] units The 'base' for the units specified. + * @retval true True if delay executed. + * @retval false False if delay/units combination resulted in overflow/underflow. + * @details This is function that may be called for all MCU targets to implement a specific wait time. + * The actual delay time is plus the overhead at a specified duration. The overhead changes under the influence of + * the compiler, operating frequency and ROM cache. When the operating frequency is low, or the specified duration in + * units of microsecond level, please note that the error becomes large. + */ +bool R_BSP_SoftwareDelay(uint32_t delay, bsp_delay_units_t units) +{ + volatile uint32_t iclk_rate; + volatile uint32_t delay_cycles; + volatile uint32_t loop_cnt; + volatile uint64_t delay_cycles_64; + volatile uint64_t loop_cnt_64; + +#ifdef BSP_CFG_PARAM_CHECKING_ENABLE + if ((BSP_DELAY_MICROSECS != units) && (BSP_DELAY_MILLISECS != units) && (BSP_DELAY_SECS != units)) + { + return(false); + } +#endif + + iclk_rate = R_BSP_GetIClkFreqHz(); /* Get the current ICLK frequency */ + + /* + * In order to handle all possible combinations of delay/ICLK it is necessary to use 64-bit + * integers (not all MCUs have floating point support). However, there is no native hw support + * for 64 bit integers so it requires many more clock cycles. This is not an issue if the + * requested delay is long enough and the ICLK is fast, but for delays in the low microseconds + * and/or a slow ICLK we use 32 bit integers to reduce the overhead cycles of this function + * by approximately a third and stand the best chance of achieving the requested delay. + */ + if ( (BSP_DELAY_MICROSECS == units) && + (delay <= (0xFFFFFFFFUL / iclk_rate)) ) /* Ensure (iclk_rate * delay) will not exceed 32 bits */ + { + delay_cycles = ((iclk_rate * delay) / units); + + if (delay_cycles > BSP_PRV_OVERHEAD_CYCLES) + { + delay_cycles -= BSP_PRV_OVERHEAD_CYCLES; + } + else + { + delay_cycles = 0; + } + + loop_cnt = delay_cycles / CPU_CYCLES_PER_LOOP; + + if (0 == loop_cnt) + { + /* The requested delay is too large/small for the current ICLK. Return false which + * also results in the minimum possible delay. */ + return(false); + } + } + else + { + /* Casting is valid because it matches the type to the right side or argument. */ + delay_cycles_64 = (((uint64_t)iclk_rate * (uint64_t)delay) / units); + + if (delay_cycles_64 > BSP_PRV_OVERHEAD_CYCLES_64) + { + delay_cycles_64 -= BSP_PRV_OVERHEAD_CYCLES_64; + } + else + { + delay_cycles = 0; + } + + loop_cnt_64 = delay_cycles_64 / CPU_CYCLES_PER_LOOP; + + if ((loop_cnt_64 > 0xFFFFFFFFUL) || (0 == loop_cnt_64)) + { + /* The requested delay is too large/small for the current ICLK. Return false which + * also results in the minimum possible delay. */ + return(false); + } + + /* Casting is valid because it matches the type to the right side or argument. */ + loop_cnt = (uint32_t)loop_cnt_64; + } + + delay_wait(loop_cnt); + + return(true); +} /* End of function R_BSP_SoftwareDelay() */ + +#if defined(BSP_CFG_BOOTLOADER_PROJECT) + #if BSP_CFG_BOOTLOADER_PROJECT == 1 +/********************************************************************************************************************** + * Function Name: R_BSP_ClockReset_Bootloader + ******************************************************************************************************************//** + * @brief Returns the MCU clock settings to the reset state. + * @return none. + * @details This function returns the MCU clock settings to the reset state. The system clock returns to LOCO. + * @note This function for bootloader only. This function is valid only in the bootloader project. + * Assume the default clock settings in r_bsp_config.h. If the clock settings in r_bsp_config.h are not in the + * default state, some clock types will not return to the reset state. + */ +void R_BSP_ClockReset_Bootloader(void) +{ + bsp_mcu_clock_reset_bootloader(); +} /* End of function R_BSP_ClockReset_Bootloader() */ + #endif /* BSP_CFG_BOOTLOADER_PROJECT == 1 */ +#endif /* defined(BSP_CFG_BOOTLOADER_PROJECT) */ + diff --git a/drivers/rx/rdp/src/r_bsp/mcu/all/r_bsp_common.h b/drivers/rx/rdp/src/r_bsp/mcu/all/r_bsp_common.h new file mode 100644 index 00000000..40f44895 --- /dev/null +++ b/drivers/rx/rdp/src/r_bsp/mcu/all/r_bsp_common.h @@ -0,0 +1,173 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013 - 2024 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_bsp_common.h +* Description : Implements functions that apply to all r_bsp boards and MCUs. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 06.05.2013 1.00 First Release +* : 25.06.2013 1.10 Now contains standard includes (stdint.h, stdbool.h, etc) as well as include for +* r_typedefs.h when needed. +* : 02.07.2013 1.11 Added #include for machine.h. +* : 10.02.2014 1.12 Changed minor version to '40'. +* : 24.03.2014 1.12 Changed minor version to '60'. +* : 14.04.2014 1.12 Added typedef for fit_callback_t. +* : 30.09.2015 1.13 Changed Major/Minor version to 3.00 +* : 30.09.2015 1.14 Changed Minor version to 3.01 +* : 01.12.2015 1.15 Changed Minor version to 3.10 +* : 01.02.2016 1.16 Changed Minor version to 3.20 +* : 29.02.2016 1.17 Changed Minor version to 3.30 +* : 13.04.2016 1.18 Changed Minor version to 3.31 +* : 01.10.2016 1.19 Changed Minor version to 3.40 +* : 04.11.2016 1.20 Changed Minor version to 3.50 +* : 15.05.2017 1.21 Changed Minor version to 3.60 +* : 01.11.2017 1.22 Changed Minor version to 3.70 +* : 01.12.2017 1.23 Changed Minor version to 3.71 +* : 01.07.2018 1.24 Changed Minor version to 3.80 +* : 27.07.2018 1.25 Changed Minor version to 3.90. +* : 31.08.2018 1.26 Changed Minor version to 3.91. +* : 31.10.2018 1.27 Changed Major/Minor version to 4.00. +* : 11.01.2019 1.28 Changed Minor version to 4.01. +* : 28.02.2019 1.29 Changed Major version to 5.00. +* Added the following macro definition. +* - INTERNAL_NOT_USED(p) +* Added support for GNUC and ICCRX. +* Fixed coding style. +* : 29.03.2019 1.30 Changed Minor version to 5.10. +* : 08.04.2019 1.31 Changed Minor version to 5.20. +* : 23.07.2019 1.32 Changed Minor version to 5.21. +* : 26.07.2019 1.33 Changed Minor version to 5.30. +* : 31.07.2019 1.34 Changed Minor version to 5.40. +* : 08.10.2019 1.35 Changed Minor version to 5.50. +* : 10.12.2019 1.36 Changed Minor version to 5.51. +* : 14.02.2020 1.37 Changed Minor version to 5.52. +* : 31.07.2020 1.38 Changed Minor version to 5.60. +* : 04.08.2020 1.39 Changed Minor version to 5.61. +* : 20.11.2020 1.40 Changed Minor version to 5.62. +* : 29.01.2021 1.41 Changed Minor version to 5.63. +* : 26.02.2021 1.42 Changed Minor version to 5.64. +* : 23.04.2021 1.43 Changed Minor version to 5.65. +* : 14.05.2021 1.44 Changed Minor version to 5.66. +* : 18.05.2021 1.45 Changed Major/Minor version to 6.11. +* : 30.06.2021 1.45 Changed Minor version to 6.20. +* : 20.08.2021 1.46 Changed Minor version to 6.21. +* : 30.11.2021 1.47 Changed Major/Minor version to 7.00. +* Modified the compile switch. +* : 11.02.2022 1.48 Changed Minor version to 7.10. +* : 22.04.2022 1.49 Changed Minor version to 7.20. +* : 25.11.2022 1.50 Changed Minor version to 7.21. +* : 28.02.2023 1.51 Changed Minor version to 7.30. +* : 10.03.2023 1.52 Changed Minor version to 7.40. +* : 26.04.2023 1.53 Changed Minor version to 7.41. +* : 21.11.2023 1.54 Changed Minor version to 7.42. +* Added definition of R_BSP_ClockReset_Bootloader function. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_bsp_config.h" + +/* C99 (or later) is necessary because r_rx_compiler.h uses Pragma operator and variadic macros. + * This means that r_typedefs.h is not used in any case. */ +#if (BSP_CFG_CPLUSPLUS == 0) && !defined(CPPAPP) +/* All implementation is C99 (or later) */ +#if defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 199901L) +#include +#include +#include +#include +#else +#error "This version of FIT needs C99 (or later)." +#endif +#else /* (BSP_CFG_CPLUSPLUS == 1) || defined(CPPAPP) */ +/* Interface might be referred from C++ */ +#include +#include +#include +#include +#endif /* (BSP_CFG_CPLUSPLUS == 0) && !defined(CPPAPP) */ + +#if defined(__CCRX__) || defined(__ICCRX__) +/* Intrinsic functions provided by compiler. */ +#include +#elif defined(__GNUC__) +/* No header file for intrinsic functions. */ +#else +/* PORT: Use header file for other compiler and port r_rx_compiler.h. */ +#endif /* defined(__CCRX__), defined(__GNUC__), defined(__ICCRX__) */ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef R_BSP_COMMON_H +#define R_BSP_COMMON_H + +/* Version Number of r_bsp. */ +#define R_BSP_VERSION_MAJOR (7) +#define R_BSP_VERSION_MINOR (42) + +/* This macro is used to suppress compiler messages about not only a parameter but also a auto variable not being used + * in a function. The nice thing about using this implementation is that it does not take any extra RAM or ROM. + * This macro is available for the followings: + * CC-RX's 'M0520826:Parameter "XXXX" was never referenced' + * CC-RX's 'W0520550:Variable "XXXX" was set but never used' + * GNURX's 'unused parameter 'XXXX' [-Wunused-parameter]' + * GNURX's 'variable 'XXXX' set but not used [-Wunused-but-set-variable]' + * When the variable is declared as volatile, the '&' can be applied like 'R_INTERNAL_NOT_USED(&volatile_variable);'. + */ +#define INTERNAL_NOT_USED(p) ((void)(p)) + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ +/* Available delay units. */ +typedef enum +{ + BSP_DELAY_MICROSECS = 1000000, // Requested delay amount is in microseconds + BSP_DELAY_MILLISECS = 1000, // Requested delay amount is in milliseconds + BSP_DELAY_SECS = 1 // Requested delay amount is in seconds +} bsp_delay_units_t; + +/* Easy to use typedef for FIT module callback functions. */ +typedef void (*fit_callback_t)(void *p_args); + +/*********************************************************************************************************************** +Exported global variables +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ +uint32_t R_BSP_GetVersion(void); +bool R_BSP_SoftwareDelay(uint32_t delay, bsp_delay_units_t units); +uint32_t R_BSP_GetIClkFreqHz(void); + +#if defined(BSP_CFG_BOOTLOADER_PROJECT) + #if BSP_CFG_BOOTLOADER_PROJECT == 1 +/* Enable the following functions in the bootloader project. */ +void R_BSP_ClockReset_Bootloader(void); + #endif /* BSP_CFG_BOOTLOADER_PROJECT == 1 */ +#endif /* defined(BSP_CFG_BOOTLOADER_PROJECT) */ + +/* End of multiple inclusion prevention macro */ +#endif /* R_BSP_COMMON_H */ + diff --git a/drivers/rx/rdp/src/r_bsp/mcu/all/r_bsp_interrupts.c b/drivers/rx/rdp/src/r_bsp/mcu/all/r_bsp_interrupts.c new file mode 100644 index 00000000..8c09b817 --- /dev/null +++ b/drivers/rx/rdp/src/r_bsp/mcu/all/r_bsp_interrupts.c @@ -0,0 +1,1114 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013 - 2024 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_bsp_interrupts.c +* Description : This module allows for callbacks to be registered for certain interrupts. +* And handle exception interrupts. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 28.02.2019 1.00 First Release +* : 08.04.2019 1.01 Added process for Group IE0 interrupts. +* Added process for EXNMI interrupts. +* : 26.07.2019 1.10 Modified comment of API function to Doxygen style. +* Modified the following function for added function. +* - R_BSP_InterruptControl +* Added the following functions. +* - bsp_fit_interrupts_control +* - bsp_fit_interrupt_enable +* - bsp_fit_interrupt_disable +* Fixed coding style. +* : 08.10.2019 1.11 Added process for software interrupt. +* : 10.12.2019 1.12 Modified comment. +* : 18.05.2021 1.13 Added function for Address exceptions. +* : 21.11.2023 1.14 Added error handling when BSP_INT_SRC_BUS_ERROR_ILLEGAL_ACCESS and +* BSP_INT_SRC_BUS_ERROR_TIMEOUT are specified as vector in the R_BSP_InterruptWrite +* function. +* Modified comment. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "platform.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +#ifdef BSP_MCU_FLOATING_POINT +/* Defines CV, CO, CZ, CU, CX, and CE bits. */ +#define BSP_PRV_FPU_CAUSE_FLAGS (0x000000FC) +#endif + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ +/* This array holds callback functions. */ +static void (* g_bsp_vectors[BSP_INT_SRC_TOTAL_ITEMS])(void * pdata); + +static bsp_int_err_t bsp_fit_interrupts_control (bool enable, bsp_int_ctrl_t * pdata); + +#ifdef BSP_MCU_GROUP_INTERRUPT +static bsp_int_err_t bsp_gr_int_enable_disable (bsp_int_src_t vector, bool enable, uint32_t ipl); +#endif /* BSP_MCU_GROUP_INTERRUPT */ + +/********************************************************************************************************************** + * Function Name: R_BSP_InterruptRequestEnable + ******************************************************************************************************************//** + * @brief Enable the specified interrupt request. + * @param[in] vector Interrupt vector number. + * @details Enable the specified interrupt request. Calculate the corresponding IER [m].IEN [j] from the vector number + * of the argument, and set "1" to that bit. The macro defined in iodefine.h can be used to the setting of the + * argument "vector". A description example is shown in Example. + * @note When setting an immediate value for an argument "vector", the argument must be 0 to 255. Don't set the + * vector number of the reserved interrupt source to the argument. + */ +void R_BSP_InterruptRequestEnable (uint32_t vector) +{ + uint32_t ier_reg_num; + uint32_t ien_bit_num; + uint8_t *p_ier_addr; + + /* Calculate the register number. (IER[m].IENj)(m = vector_number / 8) */ + ier_reg_num = vector >> 3; + + /* Calculate the bit number. (IERm.IEN[j])(j = vector_number % 8) */ + ien_bit_num = vector & 0x00000007; + + /* Casting is valid because it matches the type to the right side or argument. */ + p_ier_addr = (uint8_t *)&ICU.IER[ier_reg_num].BYTE; + + /* Casting is valid because it matches the type to the right side or argument. */ + R_BSP_BIT_SET(p_ier_addr, ien_bit_num); +} /* End of function R_BSP_InterruptRequestEnable() */ + +/********************************************************************************************************************** + * Function Name: R_BSP_InterruptRequestDisable + ******************************************************************************************************************//** + * @brief Disable the specified interrupt request. + * @param[in] vector Interrupt vector number. + * @details Disable the specified interrupt request. Calculate the corresponding IER [m].IEN [j] from the vector + * number of the argument, and clear "0" to that bit. The macro defined in iodefine.h can be used to the setting of + * the argument "vector". A description example is shown in Example. + * @note When setting an immediate value for an argument "vector", the argument must be 0 to 255. Don't set the + * vector number of the reserved interrupt source to the argument. + */ +void R_BSP_InterruptRequestDisable (uint32_t vector) +{ + uint32_t ier_reg_num; + uint32_t ien_bit_num; + uint8_t *p_ier_addr; + + /* Calculate the register number. (IER[m].IENj)(m = vector_number / 8) */ + ier_reg_num = vector >> 3; + + /* Calculate the bit number. (IERm.IEN[j])(j = vector_number % 8) */ + ien_bit_num = vector & 0x00000007; + + /* Casting is valid because it matches the type to the right side or argument. */ + p_ier_addr = (uint8_t *)&ICU.IER[ier_reg_num].BYTE; + + /* Casting is valid because it matches the type to the right side or argument. */ + R_BSP_BIT_CLEAR(p_ier_addr, ien_bit_num); +} /* End of function R_BSP_InterruptRequestDisable() */ + +/*********************************************************************************************************************** +* Function Name: bsp_interrupt_open +* Description : Initialize callback function array. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void bsp_interrupt_open (void) +{ + uint32_t i; + + /* WAIT_LOOP */ + for (i = 0; i < BSP_INT_SRC_TOTAL_ITEMS; i++) + { + /* Casting is valid because it matches the type to the right side or argument. */ + g_bsp_vectors[i] = FIT_NO_FUNC; + } + +#ifdef BSP_MCU_SOFTWARE_CONFIGURABLE_INTERRUPT + /* Initialize mapped interrupts. */ + bsp_mapped_interrupt_open(); +#endif + +#if (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) + R_BSP_SoftwareInterruptOpen(BSP_SWINT_UNIT1); +#endif /* (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) */ +#if (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) + R_BSP_SoftwareInterruptOpen(BSP_SWINT_UNIT2); +#endif /* (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) */ +} /* End of function bsp_interrupt_open() */ + +/********************************************************************************************************************** + * Function Name: R_BSP_InterruptWrite + ******************************************************************************************************************//** + * @brief Registers a callback function for an interrupt. + * @param[in] vector Which interrupt to register a callback for. + * @param[in] callback Pointer to function to call when interrupt occurs. + * @retval BSP_INT_SUCCESS Successful, callback has been registered. + * @retval BSP_INT_ERR_INVALID_ARG An invalid interrupt source was specified for vector. + * @details This function registers a callback function for an interrupt. If FIT_NO_FUNC, NULL, or any other invalid + * function address is passed for the callback argument then any previously registered callbacks are unregistered. + * If one of the interrupts that is handled by this code is triggered then the interrupt handler will query this code + * to see if a valid callback function is registered. If one is found then the callback function will be called. + * If one is not found then the interrupt handler will clear the appropriate flag(s) and exit. If the user has a + * callback function registered and wishes to no longer handle the interrupt then the user should call this function + * again with FIT_NO_FUNC as the vector parameter. + * @note Use of FIT_NO_FUNC is preferred over NULL since access to the address defined by FIT_NO_FUNC will cause a + * bus error which is easy for the user to catch. NULL typically resolves to 0 which is a valid address on RX MCUs. + */ +bsp_int_err_t R_BSP_InterruptWrite (bsp_int_src_t vector, bsp_int_cb_t callback) +{ + bsp_int_err_t err; + + err = BSP_INT_SUCCESS; + + /* Check for valid address. */ + if (((uint32_t)callback == (uint32_t)NULL) || ((uint32_t)callback == (uint32_t)FIT_NO_FUNC)) + { + /* Casting is valid because it matches the type to the right side or argument. */ + g_bsp_vectors[vector] = FIT_NO_FUNC; + } + else + { + if((BSP_INT_SRC_BUS_ERROR_ILLEGAL_ACCESS == vector) || (BSP_INT_SRC_BUS_ERROR_TIMEOUT == vector) || + (BSP_INT_SRC_EMPTY <= vector)) + { + /* When registering a bus error callback function, specify BSP_INT_SRC_BUS_ERROR in the vector. */ + err = BSP_INT_ERR_INVALID_ARG; + } + else + { + g_bsp_vectors[vector] = callback; + } + } + + return err; +} /* End of function R_BSP_InterruptWrite() */ + +/********************************************************************************************************************** + * Function Name: R_BSP_InterruptRead + ******************************************************************************************************************//** + * @brief Gets the callback for an interrupt if one is registered. + * @param[in] vector Which interrupt to read the callback for. + * @param[out] callback Pointer to where to store callback address. + * @retval BSP_INT_SUCCESS Successful, callback address has been returned. + * @retval BSP_INT_ERR_NO_REGISTERED_CALLBACK No valid callback has been registered for this interrupt source. + * @details This function returns the callback function address for an interrupt if one has been registered. If a + * callback function has not been registered then an error is returned and nothing is stored to the callback address. + */ +bsp_int_err_t R_BSP_InterruptRead (bsp_int_src_t vector, bsp_int_cb_t * callback) +{ + bsp_int_err_t err; + + err = BSP_INT_SUCCESS; + + /* Check for valid address. */ + if (((uint32_t)g_bsp_vectors[vector] == (uint32_t)NULL) || ((uint32_t)g_bsp_vectors[vector] == (uint32_t)FIT_NO_FUNC)) + { + err = BSP_INT_ERR_NO_REGISTERED_CALLBACK; + } + else + { + *callback = g_bsp_vectors[vector]; + } + + return err; +} /* End of function R_BSP_InterruptRead() */ + +/********************************************************************************************************************** + * Function Name: R_BSP_InterruptControl + ******************************************************************************************************************//** + * @brief Controls various interrupt operations. + * @param[in] vector Which interrupt to control for.\n + * If the interrupt control commands is the BSP_INT_CMD_FIT_INTERRUPT_ENABLE or the BSP_INT_CMD_FIT_INTERRUPT_DISABLE + * commands, set BSP_INT_SRC_EMPTY to "vector" because no arguments are used. + * @param[in] cmd Interrupt control command. + * @param[in,out] pdata Pointer to the argument for each interrupt control command. Typecasted to void*. See typedef + * defines of bsp_int_ctrl_t. \n + * Most of the interrupt control commands do not need the argument and take FIT_NO_PTR for + * this parameter. If the interrupt control command is the BSP_INT_CMD_GROUP_INTERRUPT_ENABLE command, set the + * interrupt priority level for group interrupts as the argument. If the interrupt control command is the + * BSP_INT_CMD_FIT_INTERRUPT_DISABLE command, set the address of a variable for saving the current processor interrupt + * priority level in the argument. If the interrupt control command is the BSP_INT_CMD_FIT_INTERRUPT_ENABLE command, + * set the address of a variable used in the BSP_INT_CMD_FIT_INTERRUPT_DISABLE command. + * @retval BSP_INT_SUCCESS Successful. + * @retval BSP_INT_ERR_NO_REGISTERED_CALLBACK No valid callback has been registered for this interrupt source. + * @retval BSP_INT_ERR_INVALID_ARG The command passed is invalid. + * @retval BSP_INT_ERR_UNSUPPORTED This processing is not supported. + * @retval BSP_INT_ERR_GROUP_STILL_ENABLED Group interrupt request remains enabled. + * @retval BSP_INT_ERR_INVALID_IPL Illegal IPL value input. + * @details This function controls the interrupt callback function call and enabling/disabling interrupts such as bus + * error interrupt, floating-point exception, NMI pin interrupt, and group interrupts, and enabling/disabling + * interrupts by controlling the Processor Interrupt Priority Level. When BSP_INT_CMD_GROUP_INTERRUPT_ENABLE is set as + * the interrupt control command, the interrupt request (IER) for group interrupts is enabled and also the interrupt + * priority level is set. The interrupt priority level set must be higher than the current level. When + * BSP_INT_CMD_GROUP_INTERRUPT_DISABLE is set as the interrupt control command, the interrupt request (IER) for group + * interrupts is disabled. Note that the interrupt request (IER) for group interrupts cannot be disabled as long as + * all interrupt requests (GEN) caused by grouped interrupt sources are disabled. When + * BSP_INT_CMD_FIT_INTERRUPT_DISABLE is set as the interrupt control command, the current processor interrupt priority + * level (IPL) is saved to the address specified by pdata as an argument, and disables interrupts by controlling the + * IPL. The value of IPL to be set is the value of BSP_CFG_FIT_IPL_MAX. When BSP_INT_CMD_FIT_INTERRUPT_ENABLE is set + * as the interrupt control command, the interrupt is enabled by setting the value stored in the address specified by + * pdata to IPL. These two commands are valid only in supervisor mode. When BSP_INT_CMD_FIT_INTERRUPT_DISABLE and + * BSP_INT_CMD_FIT_INTERRUPT_ENABLE commands are executed in user mode, Controlling IPL is not executed and an error + * code BSP_INT_ERR_UNSUPPORTED is returned. + * @note BSP_INT_CMD_FIT_INTERRUPT_DISABLE and BSP_INT_CMD_FIT_INTERRUPT_ENABLE commands can be used to secure + * atomicity of critical sections. However, these commands are valid only in supervisor mode. When these commands are + * executed in user mode, atomicity is not to secure.\n + * See Section 5.15 in the application note for more information. + */ +bsp_int_err_t R_BSP_InterruptControl (bsp_int_src_t vector, bsp_int_cmd_t cmd, void * pdata) +{ + bsp_int_err_t err; + bsp_int_cb_args_t cb_args; + + err = BSP_INT_SUCCESS; + +#ifdef BSP_MCU_GROUP_INTERRUPT + /* nothing */ +#else + /* This code is only used to remove compiler info messages about these parameters not being used. */ + INTERNAL_NOT_USED(pdata); +#endif + + switch (cmd) + { + case (BSP_INT_CMD_CALL_CALLBACK): + + /* Casting is valid because it matches the type to the right side or argument. */ + if (((uint32_t)g_bsp_vectors[vector] != (uint32_t)NULL) && ((uint32_t)g_bsp_vectors[vector] != (uint32_t)FIT_NO_FUNC)) + { + /* Fill in callback info. */ + cb_args.vector = vector; + + g_bsp_vectors[vector](&cb_args); + } + else + { + err = BSP_INT_ERR_NO_REGISTERED_CALLBACK; + } + break; + + case (BSP_INT_CMD_INTERRUPT_ENABLE): + err = bsp_interrupt_enable_disable(vector, true); + break; + + case (BSP_INT_CMD_INTERRUPT_DISABLE): + err = bsp_interrupt_enable_disable(vector, false); + break; + +#ifdef BSP_MCU_GROUP_INTERRUPT + case (BSP_INT_CMD_GROUP_INTERRUPT_ENABLE): + + /* Casting is valid because it matches the type to the right side or argument. */ + if(((uint32_t)NULL != (uint32_t)pdata) && ((uint32_t)FIT_NO_FUNC != (uint32_t)pdata)) + { + /* Casting is valid because it matches the type to the right side or argument. */ + err = bsp_gr_int_enable_disable(vector, true, ((bsp_int_ctrl_t *)pdata)->ipl); + } + else + { + err = BSP_INT_ERR_INVALID_ARG; + } + break; + + case (BSP_INT_CMD_GROUP_INTERRUPT_DISABLE): + err = bsp_gr_int_enable_disable(vector, false, 0); + break; +#endif + + case (BSP_INT_CMD_FIT_INTERRUPT_ENABLE): + + /* Casting is valid because it matches the type to the right side or argument. */ + err = bsp_fit_interrupts_control(true, (bsp_int_ctrl_t *)pdata); + break; + + case (BSP_INT_CMD_FIT_INTERRUPT_DISABLE): + + /* Casting is valid because it matches the type to the right side or argument. */ + err = bsp_fit_interrupts_control(false, (bsp_int_ctrl_t *)pdata); + break; + + default: + err = BSP_INT_ERR_INVALID_ARG; + break; + } + + return err; +} /* End of function R_BSP_InterruptControl() */ + +/*********************************************************************************************************************** +* Function Name: bsp_fit_interrupts_control +* Description : +* Arguments : enable - +* Whether to enable or disable the interrupt. +* pdata - +* Pointer to variable for saves ipl or restore ipl. +* Return Value : BSP_INT_SUCCESS - +* Interrupt enabled or disabled. +* BSP_INT_ERR_INVALID_ARG - +* Invalid argument input. +* BSP_INT_ERR_INVALID_IPL - +* Invalid IPL input. +* BSP_INT_ERR_UNSUPPORTED - +* This processing is not supported. (Executed in user mode.) +***********************************************************************************************************************/ +static bsp_int_err_t bsp_fit_interrupts_control (bool enable, bsp_int_ctrl_t * pdata) +{ + bsp_int_err_t err; + uint32_t pmode; + bool ret; + uint32_t ipl_value; + + /* Casting is valid because it matches the type to the right side or argument. */ + if(((uint32_t)NULL != (uint32_t)pdata) && ((uint32_t)FIT_NO_FUNC != (uint32_t)pdata)) + { + /* Read current processor mode. */ + pmode = (R_BSP_GET_PSW() & 0x00100000); + + /* Check current processor mode. */ + if (0 == pmode) + { + err = BSP_INT_SUCCESS; + + if (true == enable) + { + ipl_value = pdata->ipl; + } + else + { + /* Get the current Processor Interrupt Priority Level (IPL) and save IPL value. */ + pdata->ipl = R_BSP_CpuInterruptLevelRead(); + + /* Set IPL to the maximum value to disable all interrupts, + * so the scheduler can not be scheduled in critical region. + * Note: Please set this macro more than IPR for other FIT module interrupts. */ + ipl_value = BSP_CFG_FIT_IPL_MAX; + } + + if (pdata->ipl < BSP_CFG_FIT_IPL_MAX) + { + ret = R_BSP_CpuInterruptLevelWrite(ipl_value); + if (false == ret) + { + err = BSP_INT_ERR_INVALID_IPL; + } + } + else + { + err = BSP_INT_ERR_INVALID_IPL; + } + } + else + { + err = BSP_INT_ERR_UNSUPPORTED; + } + } + else + { + err = BSP_INT_ERR_INVALID_ARG; + } + + return err; +} /* End of function bsp_fit_interrupts_control() */ + +#ifdef BSP_MCU_GROUP_INTERRUPT +/*********************************************************************************************************************** +* Function Name: bsp_gr_int_enable_disable +* Description : Either enables or disables a group interrupt. If a group interrupt is called multiple times to be +* enabled then it will use the highest given IPL. A group interrupt will only be disabled when all +* interrupt sources for that group are already disabled. +* Arguments : vector - +* An interrupt source inside the group that is to be enabled/disabled. +* enable - +* Whether to enable or disable the interrupt. +* ipl - +* If enabling a group interrupt, what IPL to use. +* Return Value : BSP_INT_SUCCESS - +* Interrupt enabled or disabled. +* BSP_INT_ERR_INVALID_ARG - +* Invalid IPL or vector +* BSP_INT_ERR_GROUP_STILL_ENABLED - +* Not all group interrupts were disabled so group interrupt was not disabled. +***********************************************************************************************************************/ +static bsp_int_err_t bsp_gr_int_enable_disable (bsp_int_src_t vector, bool enable, uint32_t ipl) +{ + bsp_int_err_t err = BSP_INT_SUCCESS; + +#if BSP_CFG_PARAM_CHECKING_ENABLE == 1 + /* If interrupt is going to be enabled, verify that IPL is valid. */ + if ((true == enable) && ((BSP_MCU_IPL_MIN == ipl) || (ipl > BSP_MCU_IPL_MAX))) + { + return BSP_INT_ERR_INVALID_ARG; + } +#endif + + if ((vector > BSP_INT_SRC_GR_INT_IE0_TOP) && (vector < BSP_INT_SRC_GR_INT_BE0_TOP)) + { + /* Group IE0. */ +#ifdef BSP_MCU_GROUP_INTERRUPT_IE0 + if (true == enable) + { + R_BSP_InterruptRequestDisable(VECT(ICU, GROUPIE0)); + + /* Casting is valid because it matches the type to the right side or argument. */ + IR(ICU, GROUPIE0) = 0; + + /* Casting is valid because it matches the type to the right side or argument. */ + IPR(ICU, GROUPIE0) = (uint8_t)((ipl > IPR(ICU, GROUPIE0)) ? ipl : IPR(ICU, GROUPIE0)); + R_BSP_InterruptRequestEnable(VECT(ICU, GROUPIE0)); + } + else + { + /* Check to make sure all interrupt sources are already disabled for this group. */ + if (0 == ICU.GENIE0.LONG) + { + R_BSP_InterruptRequestDisable(VECT(ICU, GROUPIE0)); + + /* Casting is valid because it matches the type to the right side or argument. */ + IPR(ICU, GROUPIE0) = 0; + } + else + { + err = BSP_INT_ERR_GROUP_STILL_ENABLED; + } + } +#else /* BSP_MCU_GROUP_INTERRUPT_IE0 */ + err = BSP_INT_ERR_INVALID_ARG; +#endif /* BSP_MCU_GROUP_INTERRUPT_IE0 */ + } + else if ((vector > BSP_INT_SRC_GR_INT_BE0_TOP) && (vector < BSP_INT_SRC_GR_INT_BL0_TOP)) + { + /* Group BE0. */ +#ifdef BSP_MCU_GROUP_INTERRUPT_BE0 + if (true == enable) + { + R_BSP_InterruptRequestDisable(VECT(ICU, GROUPBE0)); + + /* Casting is valid because it matches the type to the right side or argument. */ + IR(ICU, GROUPBE0) = 0; + + /* Casting is valid because it matches the type to the right side or argument. */ + IPR(ICU, GROUPBE0) = (uint8_t)((ipl > IPR(ICU, GROUPBE0)) ? ipl : IPR(ICU, GROUPBE0)); + R_BSP_InterruptRequestEnable(VECT(ICU, GROUPBE0)); + } + else + { + /* Check to make sure all interrupt sources are already disabled for this group. */ + if (0 == ICU.GENBE0.LONG) + { + R_BSP_InterruptRequestDisable(VECT(ICU, GROUPBE0)); + + /* Casting is valid because it matches the type to the right side or argument. */ + IPR(ICU, GROUPBE0) = 0; + } + else + { + err = BSP_INT_ERR_GROUP_STILL_ENABLED; + } + } +#else /* BSP_MCU_GROUP_INTERRUPT_BE0 */ + err = BSP_INT_ERR_INVALID_ARG; +#endif /* BSP_MCU_GROUP_INTERRUPT_BE0 */ + } + else if ((vector > BSP_INT_SRC_GR_INT_BL0_TOP) && (vector < BSP_INT_SRC_GR_INT_BL1_TOP)) + { + /* Group BL0. */ +#ifdef BSP_MCU_GROUP_INTERRUPT_BL0 + if (true == enable) + { + R_BSP_InterruptRequestDisable(VECT(ICU, GROUPBL0)); + + /* Casting is valid because it matches the type to the right side or argument. */ + IR(ICU, GROUPBL0) = 0; + + /* Casting is valid because it matches the type to the right side or argument. */ + IPR(ICU, GROUPBL0) = (uint8_t)((ipl > IPR(ICU, GROUPBL0)) ? ipl : IPR(ICU, GROUPBL0)); + R_BSP_InterruptRequestEnable(VECT(ICU, GROUPBL0)); + } + else + { + /* Check to make sure all interrupt sources are already disabled for this group. */ + if (0 == ICU.GENBL0.LONG) + { + R_BSP_InterruptRequestDisable(VECT(ICU, GROUPBL0)); + + /* Casting is valid because it matches the type to the right side or argument. */ + IPR(ICU, GROUPBL0) = 0; + } + else + { + err = BSP_INT_ERR_GROUP_STILL_ENABLED; + } + } +#else /* BSP_MCU_GROUP_INTERRUPT_BL0 */ + err = BSP_INT_ERR_INVALID_ARG; +#endif /* BSP_MCU_GROUP_INTERRUPT_BL0 */ + } + else if ((vector > BSP_INT_SRC_GR_INT_BL1_TOP) && (vector < BSP_INT_SRC_GR_INT_BL2_TOP)) + { + /* Group BL1. */ +#ifdef BSP_MCU_GROUP_INTERRUPT_BL1 + if (true == enable) + { + R_BSP_InterruptRequestDisable(VECT(ICU, GROUPBL1)); + + /* Casting is valid because it matches the type to the right side or argument. */ + IR(ICU, GROUPBL1) = 0; + + /* Casting is valid because it matches the type to the right side or argument. */ + IPR(ICU, GROUPBL1) = (uint8_t)((ipl > IPR(ICU, GROUPBL1)) ? ipl : IPR(ICU, GROUPBL1)); + R_BSP_InterruptRequestEnable(VECT(ICU, GROUPBL1)); + } + else + { + /* Check to make sure all interrupt sources are already disabled for this group. */ + if (0 == ICU.GENBL1.LONG) + { + R_BSP_InterruptRequestDisable(VECT(ICU, GROUPBL1)); + + /* Casting is valid because it matches the type to the right side or argument. */ + IPR(ICU, GROUPBL1) = 0; + } + else + { + err = BSP_INT_ERR_GROUP_STILL_ENABLED; + } + } +#else /* BSP_MCU_GROUP_INTERRUPT_BL1 */ + err = BSP_INT_ERR_INVALID_ARG; +#endif /* BSP_MCU_GROUP_INTERRUPT_BL1 */ + } + else if ((vector > BSP_INT_SRC_GR_INT_BL2_TOP) && (vector < BSP_INT_SRC_GR_INT_AL0_TOP)) + { + /* Group BL2. */ +#ifdef BSP_MCU_GROUP_INTERRUPT_BL2 + if (true == enable) + { + R_BSP_InterruptRequestDisable(VECT(ICU, GROUPBL2)); + + /* Casting is valid because it matches the type to the right side or argument. */ + IR(ICU, GROUPBL2) = 0; + + /* Casting is valid because it matches the type to the right side or argument. */ + IPR(ICU, GROUPBL2) = (uint8_t)((ipl > IPR(ICU, GROUPBL2)) ? ipl : IPR(ICU, GROUPBL2)); + R_BSP_InterruptRequestEnable(VECT(ICU, GROUPBL2)); + } + else + { + /* Check to make sure all interrupt sources are already disabled for this group. */ + if (0 == ICU.GENBL2.LONG) + { + R_BSP_InterruptRequestDisable(VECT(ICU, GROUPBL2)); + + /* Casting is valid because it matches the type to the right side or argument. */ + IPR(ICU, GROUPBL2) = 0; + } + else + { + err = BSP_INT_ERR_GROUP_STILL_ENABLED; + } + } +#else /* BSP_MCU_GROUP_INTERRUPT_BL2 */ + err = BSP_INT_ERR_INVALID_ARG; +#endif /* BSP_MCU_GROUP_INTERRUPT_BL2 */ + } + else if ((vector > BSP_INT_SRC_GR_INT_AL0_TOP) && (vector < BSP_INT_SRC_GR_INT_AL1_TOP)) + { + /* Group AL0. */ +#ifdef BSP_MCU_GROUP_INTERRUPT_AL0 + if (true == enable) + { + R_BSP_InterruptRequestDisable(VECT(ICU, GROUPAL0)); + + /* Casting is valid because it matches the type to the right side or argument. */ + IR(ICU, GROUPAL0) = 0; + + /* Casting is valid because it matches the type to the right side or argument. */ + IPR(ICU, GROUPAL0) = (uint8_t)((ipl > IPR(ICU, GROUPAL0)) ? ipl : IPR(ICU, GROUPAL0)); + R_BSP_InterruptRequestEnable(VECT(ICU, GROUPAL0)); + } + else + { + /* Check to make sure all interrupt sources are already disabled for this group. */ + if (0 == ICU.GENAL0.LONG) + { + R_BSP_InterruptRequestDisable(VECT(ICU, GROUPAL0)); + + /* Casting is valid because it matches the type to the right side or argument. */ + IPR(ICU, GROUPAL0) = 0; + } + else + { + err = BSP_INT_ERR_GROUP_STILL_ENABLED; + } + } +#else /* BSP_MCU_GROUP_INTERRUPT_AL0 */ + err = BSP_INT_ERR_INVALID_ARG; +#endif /* BSP_MCU_GROUP_INTERRUPT_AL0 */ + } + else if ((vector > BSP_INT_SRC_GR_INT_AL1_TOP) && (vector < BSP_INT_SRC_GR_INT_END)) + { + /* Group AL1. */ +#ifdef BSP_MCU_GROUP_INTERRUPT_AL1 + if (true == enable) + { + R_BSP_InterruptRequestDisable(VECT(ICU, GROUPAL1)); + + /* Casting is valid because it matches the type to the right side or argument. */ + IR(ICU, GROUPAL1) = 0; + + /* Casting is valid because it matches the type to the right side or argument. */ + IPR(ICU, GROUPAL1) = (uint8_t)((ipl > IPR(ICU, GROUPAL1)) ? ipl : IPR(ICU, GROUPAL1)); + R_BSP_InterruptRequestEnable(VECT(ICU, GROUPAL1)); + } + else + { + /* Check to make sure all interrupt sources are already disabled for this group. */ + if (0 == ICU.GENAL1.LONG) + { + R_BSP_InterruptRequestDisable(VECT(ICU, GROUPAL1)); + + /* Casting is valid because it matches the type to the right side or argument. */ + IPR(ICU, GROUPAL1) = 0; + } + else + { + err = BSP_INT_ERR_GROUP_STILL_ENABLED; + } + } +#else /* BSP_MCU_GROUP_INTERRUPT_AL1 */ + err = BSP_INT_ERR_INVALID_ARG; +#endif /* BSP_MCU_GROUP_INTERRUPT_AL1 */ + } + else + { + /* Vector given was not part of a group. */ + err = BSP_INT_ERR_INVALID_ARG; + } + + return err; +} /* End of function bsp_gr_int_enable_disable() */ +#endif /* BSP_MCU_GROUP_INTERRUPT */ + +/* When using the user startup program, disable the following code. */ +#if BSP_CFG_STARTUP_DISABLE == 0 + +#ifdef BSP_MCU_EXCEP_SUPERVISOR_INST_ISR +/*********************************************************************************************************************** +* Function name: excep_supervisor_inst_isr +* Description : Supervisor Instruction Violation ISR +* Arguments : none +* Return Value : none +***********************************************************************************************************************/ +R_BSP_ATTRIB_INTERRUPT void excep_supervisor_inst_isr(void) +{ + /* If user has registered a callback for this exception then call it. */ + R_BSP_InterruptControl(BSP_INT_SRC_EXC_SUPERVISOR_INSTR, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); +} /* End of function excep_supervisor_inst_isr() */ +#endif + +#ifdef BSP_MCU_EXCEP_ACCESS_ISR +/*********************************************************************************************************************** +* Function name: excep_access_isr +* Description : Access exception ISR +* Arguments : none +* Return Value : none +***********************************************************************************************************************/ +R_BSP_ATTRIB_INTERRUPT void excep_access_isr(void) +{ + /* If user has registered a callback for this exception then call it. */ + R_BSP_InterruptControl(BSP_INT_SRC_EXC_ACCESS, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); +} /* End of function excep_access_isr() */ +#endif + +#ifdef BSP_MCU_EXCEP_UNDEFINED_INST_ISR +/*********************************************************************************************************************** +* Function name: excep_undefined_inst_isr +* Description : Undefined instruction exception ISR +* Arguments : none +* Return Value : none +***********************************************************************************************************************/ +R_BSP_ATTRIB_INTERRUPT void excep_undefined_inst_isr(void) +{ + /* If user has registered a callback for this exception then call it. */ + R_BSP_InterruptControl(BSP_INT_SRC_EXC_UNDEFINED_INSTR, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); +} /* End of function excep_undefined_inst_isr() */ +#endif + +#ifdef BSP_MCU_EXCEP_FLOATING_POINT_ISR +/*********************************************************************************************************************** +* Function name: excep_floating_point_isr +* Description : Floating point exception ISR +* Arguments : none +* Return Value : none +***********************************************************************************************************************/ +R_BSP_ATTRIB_INTERRUPT void excep_floating_point_isr(void) +{ +#ifdef __FPU + /* Used for reading FPSW register. */ + uint32_t tmp_fpsw; +#endif + + /* If user has registered a callback for this exception then call it. */ + R_BSP_InterruptControl(BSP_INT_SRC_EXC_FPU, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + +#ifdef __FPU + /* Get current FPSW. */ + tmp_fpsw = (uint32_t)R_BSP_GET_FPSW(); + + /* Clear only the FPU exception flags. */ + R_BSP_SET_FPSW(tmp_fpsw & ((uint32_t)~BSP_PRV_FPU_CAUSE_FLAGS)); +#endif +} /* End of function excep_floating_point_isr() */ +#endif + +#ifdef BSP_MCU_EXCEP_ADDRESS_ISR +/*********************************************************************************************************************** +* Function name: excep_address_isr +* Description : Address exception ISR +* Arguments : none +* Return Value : none +* Note : This function is supported by only CCRX and GCC. +***********************************************************************************************************************/ +R_BSP_ATTRIB_INTERRUPT void excep_address_isr(void) +{ + /* If user has registered a callback for this exception then call it. */ + R_BSP_InterruptControl(BSP_INT_SRC_EXC_ADDRESS, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); +} /* End of function excep_address_isr() */ +#endif + +#ifdef BSP_MCU_NON_MASKABLE_ISR +/*********************************************************************************************************************** +* Function name: non_maskable_isr +* Description : Non-maskable interrupt ISR +* Arguments : none +* Return Value : none +***********************************************************************************************************************/ +R_BSP_ATTRIB_INTERRUPT void non_maskable_isr(void) +{ + /* Determine what is the cause of this interrupt. */ + +#ifdef BSP_MCU_NMI_EXC_NMI_PIN + /* EXC_NMI_PIN */ + if ((1 == ICU.NMISR.BIT.NMIST) && (1 == ICU.NMIER.BIT.NMIEN)) + { + /* NMI pin interrupt is requested. */ + R_BSP_InterruptControl(BSP_INT_SRC_EXC_NMI_PIN, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + + /* Clear NMI pin interrupt flag. */ + ICU.NMICLR.BIT.NMICLR = 1; + } +#endif + +#ifdef BSP_MCU_NMI_OSC_STOP_DETECT + /* OSC_STOP_DETECT */ + if ((1 == ICU.NMISR.BIT.OSTST) && (1 == ICU.NMIER.BIT.OSTEN)) + { + /* Oscillation stop detection interrupt is requested. */ + R_BSP_InterruptControl(BSP_INT_SRC_OSC_STOP_DETECT, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + + /* Clear oscillation stop detect flag. */ + ICU.NMICLR.BIT.OSTCLR = 1; + } +#endif + +#ifdef BSP_MCU_NMI_WDT_ERROR + /* WDT_ERROR */ + if ((1 == ICU.NMISR.BIT.WDTST) && (1 == ICU.NMIER.BIT.WDTEN)) + { + /* WDT underflow/refresh error interrupt is requested. */ + R_BSP_InterruptControl(BSP_INT_SRC_WDT_ERROR, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + + /* Clear WDT flag. */ + ICU.NMICLR.BIT.WDTCLR = 1; + } +#endif + +#ifdef BSP_MCU_NMI_LVD + /* LVD */ + if ((1 == ICU.NMISR.BIT.LVDST) && (1 == ICU.NMIER.BIT.LVDEN)) + { + /* Voltage monitoring 1 interrupt is requested. */ + R_BSP_InterruptControl(BSP_INT_SRC_LVD1, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + } +#endif + +#ifdef BSP_MCU_NMI_IWDT_ERROR + /* IWDT_ERROR */ + if ((1 == ICU.NMISR.BIT.IWDTST) && (1 == ICU.NMIER.BIT.IWDTEN)) + { + /* IWDT underflow/refresh error interrupt is requested. */ + R_BSP_InterruptControl(BSP_INT_SRC_IWDT_ERROR, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + + /* Clear IWDT flag. */ + ICU.NMICLR.BIT.IWDTCLR = 1; + } +#endif + +#ifdef BSP_MCU_NMI_LVD1 + /* LVD1 */ + if ((1 == ICU.NMISR.BIT.LVD1ST) && (1 == ICU.NMIER.BIT.LVD1EN)) + { + /* Voltage monitoring 1 interrupt is requested. */ + R_BSP_InterruptControl(BSP_INT_SRC_LVD1, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + + /* Clear LVD1 flag. */ + ICU.NMICLR.BIT.LVD1CLR = 1; + } +#endif + +#ifdef BSP_MCU_NMI_LVD2 + /* LVD2 */ + if ((1 == ICU.NMISR.BIT.LVD2ST) && (1 == ICU.NMIER.BIT.LVD2EN)) + { + /* Voltage monitoring 1 interrupt is requested. */ + R_BSP_InterruptControl(BSP_INT_SRC_LVD2, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + + /* Clear LVD2 flag. */ + ICU.NMICLR.BIT.LVD2CLR = 1; + } +#endif + +#ifdef BSP_MCU_NMI_VBATT + /* VBATT */ + if ((1 == ICU.NMISR.BIT.VBATST) && (1 == ICU.NMIER.BIT.VBATEN)) + { + /* VBATT monitoring interrupt is requested. */ + R_BSP_InterruptControl(BSP_INT_SRC_VBATT, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + + /* Clear LVD2 flag. */ + ICU.NMICLR.BIT.VBATCLR = 1; + } +#endif + +#ifdef BSP_MCU_NMI_ECCRAM + /* ECCRAM */ + if ((1 == ICU.NMISR.BIT.ECCRAMST) && (1 == ICU.NMIER.BIT.ECCRAMEN)) + { + if(1 == ECCRAM.ECCRAM1STS.BIT.ECC1ERR) + { + /* ECCRAM Error interrupt is requested. */ + R_BSP_InterruptControl(BSP_INT_SRC_ECCRAM_1BIT, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + + /* Clear ECCRAM flags. */ + ECCRAM.ECCRAM1STS.BIT.ECC1ERR = 0; + } + + if(1 == ECCRAM.ECCRAM2STS.BIT.ECC2ERR) + { + /* ECCRAM Error interrupt is requested. */ + R_BSP_InterruptControl(BSP_INT_SRC_ECCRAM_2BIT, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + + /* Clear ECCRAM flags. */ + ECCRAM.ECCRAM2STS.BIT.ECC2ERR = 0; + } + } +#endif + +#ifdef BSP_MCU_NMI_RAM + /* RAM */ + if ((1 == ICU.NMISR.BIT.RAMST) && (1 == ICU.NMIER.BIT.RAMEN)) + { + /* Casting is valid because it matches the type to the right side or argument. */ + if(1 == RAM.RAMSTS.BIT.RAMERR) + { + /* RAM Error interrupt is requested. */ + R_BSP_InterruptControl(BSP_INT_SRC_RAM, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + + /* Clear RAM flags. */ + RAM.RAMSTS.BIT.RAMERR = 0; + } + #ifdef BSP_MCU_NMI_RAM_EXRAM + + /* Casting is valid because it matches the type to the right side or argument. */ + if(1 == RAM.EXRAMSTS.BIT.EXRAMERR) + { + /* Expansion RAM Error interrupt is requested. */ + R_BSP_InterruptControl(BSP_INT_SRC_EXRAM, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + + /* Clear Expansion RAM flags. */ + RAM.EXRAMSTS.BIT.EXRAMERR = 0; + } + #endif /* BSP_MCU_NMI_RAM_EXRAM */ + + #ifdef BSP_MCU_NMI_RAM_ECCRAM + + /* Casting is valid because it matches the type to the right side or argument. */ + if(1 == RAM.ECCRAM1STS.BIT.ECC1ERR) + { + /* ECCRAM Error interrupt is requested. */ + R_BSP_InterruptControl(BSP_INT_SRC_ECCRAM_1BIT, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + + /* Clear ECCRAM flags. */ + RAM.ECCRAM1STS.BIT.ECC1ERR = 0; + } + + /* Casting is valid because it matches the type to the right side or argument. */ + if(1 == RAM.ECCRAM2STS.BIT.ECC2ERR) + { + /* ECCRAM Error interrupt is requested. */ + R_BSP_InterruptControl(BSP_INT_SRC_ECCRAM_2BIT, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + + /* Clear ECCRAM flags. */ + RAM.ECCRAM2STS.BIT.ECC2ERR = 0; + } + #endif /* BSP_MCU_NMI_RAM_ECCRAM */ + } +#endif /* BSP_MCU_NMI_RAM */ + +#ifdef BSP_MCU_NMI_EXNMI + /* EXNMI */ + if ((1 == ICU.NMISR.BIT.EXNMIST) && (1 == ICU.NMIER.BIT.EXNMIEN)) + { + #ifdef BSP_MCU_NMI_EXNMI_RAM + + /* Casting is valid because it matches the type to the right side or argument. */ + if ((1 == ICU.EXNMISR.BIT.RAMST) && (1 == ICU.EXNMIER.BIT.RAMEN)) + { + + /* Casting is valid because it matches the type to the right side or argument. */ + if(1 == RAM.RAMSTS.BIT.RAMERR) + { + /* RAM Error interrupt is requested. */ + R_BSP_InterruptControl(BSP_INT_SRC_RAM, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + + /* Clear RAM flags. */ + RAM.RAMSTS.BIT.RAMERR = 0; + } + #ifdef BSP_MCU_NMI_EXNMI_RAM_EXRAM + + /* Casting is valid because it matches the type to the right side or argument. */ + if(1 == RAM.EXRAMSTS.BIT.EXRAMERR) + { + /* Expansion RAM Error interrupt is requested. */ + R_BSP_InterruptControl(BSP_INT_SRC_EXRAM, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + + /* Clear Expansion RAM flags. */ + RAM.EXRAMSTS.BIT.EXRAMERR = 0; + } + #endif /* BSP_MCU_NMI_EXNMI_RAM_EXRAM */ + + #ifdef BSP_MCU_NMI_EXNMI_RAM_ECCRAM + + /* Casting is valid because it matches the type to the right side or argument. */ + if(1 == ECCRAM.ECCRAM1STS.BIT.ECC1ERR) + { + /* ECCRAM Error interrupt is requested. */ + R_BSP_InterruptControl(BSP_INT_SRC_ECCRAM_1BIT, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + + /* Clear ECCRAM flags. */ + ECCRAM.ECCRAM1STS.BIT.ECC1ERR = 0; + } + + /* Casting is valid because it matches the type to the right side or argument. */ + if(1 == ECCRAM.ECCRAM2STS.BIT.ECC2ERR) + { + /* ECCRAM Error interrupt is requested. */ + R_BSP_InterruptControl(BSP_INT_SRC_ECCRAM_2BIT, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + + /* Clear ECCRAM flags. */ + ECCRAM.ECCRAM2STS.BIT.ECC2ERR = 0; + } + #endif /* BSP_MCU_NMI_EXNMI_RAM_ECCRAM */ + } + #endif /* BSP_MCU_NMI_EXNMI_RAM */ + + #ifdef BSP_MCU_NMI_EXNMI_DPFPUEX + + /* Casting is valid because it matches the type to the right side or argument. */ + if ((1 == ICU.EXNMISR.BIT.DPFPUST) && (1 == ICU.EXNMIER.BIT.DPFPUEN)) + { + /* Double-Precision Floating-Point Exception interrupt is requested. */ + R_BSP_InterruptControl(BSP_INT_SRC_DPFPUEX, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); + + /* Clear DPFPUST flag. */ + ICU.EXNMICLR.BIT.DPFPUCLR = 1; + } + #endif /* BSP_MCU_NMI_EXNMI_DPFPUEX */ + } +#endif /* BSP_MCU_NMI_EXNMI */ + + /* WAIT_LOOP */ + while(1) + { + /* Infinite loop. Return from Non-maskable interrupt handlling routine is prohibited. + Never use the non-maskable interrupt with an attempt to return to the program that was being executed at + the time of interrupt generation after the exception handling routine is ended. + */ + R_BSP_NOP(); + } +} /* End of function non_maskable_isr() */ +#endif /* BSP_MCU_NON_MASKABLE_ISR */ + +#ifdef BSP_MCU_UNDEFINED_INTERRUPT_SOURCE_ISR +/*********************************************************************************************************************** +* Function name: undefined_interrupt_source_isr +* Description : All undefined interrupt vectors point to this function. +* Set a breakpoint in this function to determine which source is creating unwanted interrupts. +* Arguments : none +* Return Value : none +***********************************************************************************************************************/ +R_BSP_ATTRIB_INTERRUPT void undefined_interrupt_source_isr(void) +{ + /* If user has registered a callback for this exception then call it. */ + R_BSP_InterruptControl(BSP_INT_SRC_UNDEFINED_INTERRUPT, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); +} /* End of function undefined_interrupt_source_isr() */ +#endif + +#ifdef BSP_MCU_BUS_ERROR_ISR +/*********************************************************************************************************************** +* Function name: bus_error_isr +* Description : This interrupt will fire if the user tries +* to access code or data from one of the reserved areas in the memory map, including the areas covered +* by disabled chip selects. A nop() statement is included here as a convenient place to set a breakpoint +* during debugging and development, and further handling should be added by the user for their +* application. +* Arguments : none +* Return value : none +***********************************************************************************************************************/ +R_BSP_ATTRIB_INTERRUPT void bus_error_isr (void) +{ + /* Clear the bus error */ + BSC.BERCLR.BIT.STSCLR = 1; + + /* + To find the address that was accessed when the bus error occurred, read the register BSC.BERSR2.WORD. + The upper 13 bits of this register contain the upper 13-bits of the offending address (in 512K byte units) + */ + + /* If user has registered a callback for this exception then call it. */ + R_BSP_InterruptControl(BSP_INT_SRC_BUS_ERROR, BSP_INT_CMD_CALL_CALLBACK, FIT_NO_PTR); +} /* End of function bus_error_isr() */ +#endif + +#endif /* BSP_CFG_STARTUP_DISABLE == 0 */ + diff --git a/drivers/rx/rdp/src/r_bsp/mcu/all/r_bsp_interrupts.h b/drivers/rx/rdp/src/r_bsp/mcu/all/r_bsp_interrupts.h new file mode 100644 index 00000000..2e2e54dc --- /dev/null +++ b/drivers/rx/rdp/src/r_bsp/mcu/all/r_bsp_interrupts.h @@ -0,0 +1,87 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 - 2024 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_bsp_interrupts.h +* Description : This module allows for callbacks to be registered for certain interrupts. +* And handle exception interrupts. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 28.02.2019 1.00 First Release +* : 18.05.2021 1.01 Added definition for Address exceptions. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "platform.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef INTERRUPTS_H +#define INTERRUPTS_H + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ +void R_BSP_InterruptRequestEnable(uint32_t vector); +void R_BSP_InterruptRequestDisable(uint32_t vector); +bsp_int_err_t R_BSP_InterruptWrite(bsp_int_src_t vector, bsp_int_cb_t callback); +bsp_int_err_t R_BSP_InterruptRead(bsp_int_src_t vector, bsp_int_cb_t * callback); +bsp_int_err_t R_BSP_InterruptControl(bsp_int_src_t vector, bsp_int_cmd_t cmd, void * pdata); + +void bsp_interrupt_open(void); //r_bsp internal function. DO NOT CALL. + +#ifdef BSP_MCU_EXCEP_SUPERVISOR_INST_ISR +R_BSP_PRAGMA_INTERRUPT_FUNCTION(excep_supervisor_inst_isr) +#endif +#ifdef BSP_MCU_EXCEP_ACCESS_ISR +R_BSP_PRAGMA_INTERRUPT_FUNCTION(excep_access_isr) +#endif +#ifdef BSP_MCU_EXCEP_UNDEFINED_INST_ISR +R_BSP_PRAGMA_INTERRUPT_FUNCTION(excep_undefined_inst_isr) +#endif +#ifdef BSP_MCU_EXCEP_FLOATING_POINT_ISR +R_BSP_PRAGMA_INTERRUPT_FUNCTION(excep_floating_point_isr) +#endif +#ifdef BSP_MCU_EXCEP_ADDRESS_ISR +R_BSP_PRAGMA_INTERRUPT_FUNCTION(excep_address_isr) +#endif +#ifdef BSP_MCU_NON_MASKABLE_ISR +R_BSP_PRAGMA_INTERRUPT_FUNCTION(non_maskable_isr) +#endif +#ifdef BSP_MCU_UNDEFINED_INTERRUPT_SOURCE_ISR +R_BSP_PRAGMA_INTERRUPT_DEFAULT(undefined_interrupt_source_isr) +#endif +#ifdef BSP_MCU_BUS_ERROR_ISR +R_BSP_PRAGMA_INTERRUPT(bus_error_isr, VECT(BSC,BUSERR)) +#endif + +#endif /* End of multiple inclusion prevention macro */ + diff --git a/drivers/rx/rdp/src/r_bsp/mcu/all/r_rx_compiler.h b/drivers/rx/rdp/src/r_bsp/mcu/all/r_rx_compiler.h new file mode 100644 index 00000000..72baa54b --- /dev/null +++ b/drivers/rx/rdp/src/r_bsp/mcu/all/r_rx_compiler.h @@ -0,0 +1,1648 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 - 2024 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_rx_compiler.h +* Description : This is a file for integrating the definitions of different functions for each compilers. +* Replace different functions for each compiler. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 28.02.2019 1.00 First Release +* : 08.10.2019 1.01 Modified definition of __RX_DPFPU_INSNS__ to __RX_DFPU_INSNS__ for GNUC. +* Modified definition of TFU for GNUC. +* Modified comment of TFU for ICCRX. +* Added include of r_bsp_config.h. +* Changed the following definitions for added support of Renesas RTOS(RI600V4 or RI600PX). +* - R_BSP_SECNAME_INTVECTTBL +* - R_BSP_SECNAME_EXCEPTVECTTBL +* - R_BSP_SECNAME_FIXEDVECTTBL +* - R_BSP_PRAGMA_INTERRUPT +* - R_BSP_PRAGMA_STATIC_INTERRUPT +* - R_BSP_PRAGMA_INTERRUPT_FUNCTION +* - R_BSP_ATTRIB_STATIC_INTERRUPT +* - R_BSP_PRAGMA_INTERRUPT_DEFAULT +* - R_BSP_PRAGMA_STATIC_INTERRUPT_DEFAULT +* Changed the following definitions to definition without __no_init for ICCRX so that +* there is no warning when the initial value is specified. +* - _R_BSP_ATTRIB_SECTION_CHANGE_C1 +* - _R_BSP_ATTRIB_SECTION_CHANGE_C2 +* - _R_BSP_ATTRIB_SECTION_CHANGE_C4 +* - _R_BSP_ATTRIB_SECTION_CHANGE_C8 +* - _R_BSP_ATTRIB_SECTION_CHANGE_D1 +* - _R_BSP_ATTRIB_SECTION_CHANGE_D2 +* - _R_BSP_ATTRIB_SECTION_CHANGE_D4 +* - _R_BSP_ATTRIB_SECTION_CHANGE_D8 +* : 17.12.2019 1.02 Modified the comment of description. +* : 20.11.2020 1.03 Changed to suppress the warning that occurs when the warning level is raised in +* the IAR compiler. +* : 18.05.2021 1.04 Added definition for Address exceptions. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_bsp_common.h" +#include "r_bsp_config.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef R_RX_COMPILER_H +#define R_RX_COMPILER_H + +/* ========== Check Compiler ========== */ +#if defined(__CCRX__) + /* supported */ +#elif defined(__GNUC__) + /* supported */ +#elif defined(__ICCRX__) + /* supported */ +#else + #error "Unrecognized compiler" +#endif + + +/* ========== Macros ========== */ +#if defined(__CCRX__) + +/* #define __RX 1 */ /* This is automatically defined by CCRX. */ +/* #define __LIT 1 */ /* This is automatically defined by CCRX. */ +/* #define __BIG 1 */ /* This is automatically defined by CCRX. */ +/* #define __FPU 1 */ /* This is automatically defined by CCRX. */ +/* #define __RXV1 1 */ /* This is automatically defined by CCRX. */ +/* #define __RXV2 1 */ /* This is automatically defined by CCRX. */ +/* #define __RXV3 1 */ /* This is automatically defined by CCRX. */ +/* #define __TFU 1 */ /* This is automatically defined by CCRX. */ +/* #define __DPFPU 1 */ /* This is automatically defined by CCRX. */ + +#elif defined(__GNUC__) + +#if !defined(__RX) +#define __RX 1 +#endif + +#if defined(__RX_LITTLE_ENDIAN__) +#if !defined(__LIT) +#define __LIT 1 +#endif +#elif defined(__RX_BIG_ENDIAN__) +#if !defined(__BIG) +#define __BIG 1 +#endif +#endif + +#if defined(__RX_FPU_INSNS__) +#if !defined(__FPU) +#define __FPU 1 +#endif +#endif + +#if defined(__RXv1__) +#if !defined(__RXV1) +#define __RXV1 1 +#endif +#endif + +#if defined(__RXv2__) +#if !defined(__RXV2) +#define __RXV2 1 +#endif +#endif + +#if defined(__RXv3__) +#if !defined(__RXV3) +#define __RXV3 1 +#endif +#endif + +/* #define __TFU 1 */ /* This is automatically defined by GNUC. */ + +#if defined(__RX_DFPU_INSNS__) +#if !defined(__DPFPU) +#define __DPFPU 1 +#endif +#endif + +#elif defined(__ICCRX__) + +#if !defined(__RX) +#define __RX 1 +#endif + +/* #define __LIT 1 */ /* This is automatically defined by ICCRX. */ +/* #define __BIG 1 */ /* This is automatically defined by ICCRX. */ +/* #define __FPU 1 */ /* This is automatically defined by ICCRX. */ +/* #define __RXV1 1 */ /* This is automatically defined by ICCRX. */ +/* #define __RXV2 1 */ /* This is automatically defined by ICCRX. */ +/* #define __RXV3 1 */ /* This is automatically defined by ICCRX. */ +/* #define __TFU 1 */ /* This is automatically defined by ICCRX. */ +/* #define __DPFPU 1 */ /* Not yet supported. */ + +#endif + + +/* ========== Keywords ========== */ +#if !(defined(__CCRX__) && defined(__cplusplus)) +#define R_BSP_PRAGMA(...) _Pragma(#__VA_ARGS__) +#else +/* CC-RX' C++ mode does not support Pragma operator and variadic macros */ +#define R_BSP_PRAGMA(x) +#endif + +#if defined(__CCRX__) + +#define R_BSP_VOLATILE_EVENACCESS volatile __evenaccess +#define R_BSP_EVENACCESS __evenaccess +#define R_BSP_EVENACCESS_SFR __evenaccess +#define R_BSP_VOLATILE_SFR volatile +#define R_BSP_SFR /* none */ + +#elif defined(__GNUC__) + +#define R_BSP_VOLATILE_EVENACCESS volatile +#define R_BSP_EVENACCESS /* none */ +#define R_BSP_EVENACCESS_SFR /* none */ +#define R_BSP_VOLATILE_SFR volatile +#define R_BSP_SFR /* none */ + +#elif defined(__ICCRX__) + +#define R_BSP_VOLATILE_EVENACCESS volatile +#define R_BSP_EVENACCESS volatile +#define R_BSP_EVENACCESS_SFR __sfr +#define R_BSP_VOLATILE_SFR volatile __sfr +#define R_BSP_SFR __sfr + +#endif + + +/* ========== Sections ========== */ + +/* ---------- Operators ---------- */ +#if defined(__CCRX__) + +#define R_BSP_SECTOP(name) __sectop(#name) +#define R_BSP_SECEND(name) __secend(#name) +#define R_BSP_SECSIZE(name) __secsize(#name) + +#define R_BSP_SECTION_OPERATORS_INIT(name) /* none */ + +#elif defined(__GNUC__) + +#define R_BSP_SECTOP(name) ((void *)name##_start) +#define R_BSP_SECEND(name) ((void *)name##_end) +#define R_BSP_SECSIZE(name) ((size_t)((uint8_t *)R_BSP_SECEND(name) - (uint8_t *)R_BSP_SECTOP(name))) + +#define R_BSP_SECTION_OPERATORS_INIT(name) extern uint8_t name##_start[], name##_end[]; + +#elif defined(__ICCRX__) + +#define R_BSP_SECTOP(name) __section_begin(#name) +#define R_BSP_SECEND(name) __section_end(#name) +#define R_BSP_SECSIZE(name) __section_size(#name) + +#define R_BSP_SECTION_OPERATORS_INIT(name) R_BSP_PRAGMA(section = #name); + +#endif + +/* ---------- Names ---------- */ +#if defined(__CCRX__) + +#if BSP_CFG_RTOS_USED == 4 /* Renesas RI600V4 & RI600PX */ +#define R_BSP_SECNAME_INTVECTTBL "INTERRUPT_VECTOR" +#else /* BSP_CFG_RTOS_USED != 4 */ +#define R_BSP_SECNAME_INTVECTTBL "C$VECT" +#endif /* BSP_CFG_RTOS_USED */ + +#if defined(__RXV2) || defined(__RXV3) +#if BSP_CFG_RTOS_USED == 4 /* Renesas RI600V4 & RI600PX */ +#define R_BSP_SECNAME_EXCEPTVECTTBL "FIX_INTERRUPT_VECTOR" +#else /* BSP_CFG_RTOS_USED != 4 */ +#define R_BSP_SECNAME_EXCEPTVECTTBL "EXCEPTVECT" +#endif /* BSP_CFG_RTOS_USED */ +#define R_BSP_SECNAME_RESETVECT "RESETVECT" +#else /* __RXV1 */ +#if BSP_CFG_RTOS_USED == 4 /* Renesas RI600V4 & RI600PX */ +#define R_BSP_SECNAME_FIXEDVECTTBL "FIX_INTERRUPT_VECTOR" +#else /* BSP_CFG_RTOS_USED != 4 */ +#define R_BSP_SECNAME_FIXEDVECTTBL "FIXEDVECT" +#endif /* BSP_CFG_RTOS_USED */ +#endif /* defined(__RXV2) || defined(__RXV3) */ +#define R_BSP_SECNAME_UBSETTINGS "UBSETTINGS" + +#elif defined(__GNUC__) + +#define R_BSP_SECNAME_INTVECTTBL ".rvectors" +#if defined(__RXV2) || defined(__RXV3) +#define R_BSP_SECNAME_EXCEPTVECTTBL ".exvectors" +#define R_BSP_SECNAME_RESETVECT ".fvectors" +#else +#define R_BSP_SECNAME_FIXEDVECTTBL ".fvectors" +#endif +#define R_BSP_SECNAME_UBSETTINGS ".ubsettings" + +#elif defined(__ICCRX__) + +#define R_BSP_SECNAME_INTVECTTBL ".inttable" +#if defined(__RXV2) || defined(__RXV3) +#define R_BSP_SECNAME_EXCEPTVECTTBL ".exceptvect" +#define R_BSP_SECNAME_RESETVECT ".resetvect" +#else +#define R_BSP_SECNAME_FIXEDVECTTBL ".exceptvect" +#endif +#define R_BSP_SECNAME_UBSETTINGS ".ubsettings" + +#endif + +/* ---------- Addresses ---------- */ +#if defined(__CCRX__) + +#define R_BSP_SECTOP_INTVECTTBL __sectop(R_BSP_SECNAME_INTVECTTBL) +#if defined(__RXV2) || defined(__RXV3) +#define R_BSP_SECTOP_EXCEPTVECTTBL __sectop(R_BSP_SECNAME_EXCEPTVECTTBL) +#endif + +#elif defined(__GNUC__) + +#define R_BSP_SECTOP_INTVECTTBL ((void *)rvectors_start) +extern void * const rvectors_start[]; +#if defined(__RXV2) || defined(__RXV3) +#define R_BSP_SECTOP_EXCEPTVECTTBL ((void *)exvectors_start) +extern void * const exvectors_start[]; +#endif + +#elif defined(__ICCRX__) + +#define R_BSP_SECTOP_INTVECTTBL /* none */ +#if defined(__RXV2) || defined(__RXV3) +#define R_BSP_SECTOP_EXCEPTVECTTBL /* none */ +#endif + +#endif + + +/* ========== #pragma Directive ========== */ + +/* ---------- Stack Size ---------- */ +#if defined(__CCRX__) + +#define R_BSP_PRAGMA_STACKSIZE_SI(_size) _R_BSP_PRAGMA_STACKSIZE_SI(_size) /* _size means '(size)' */ +#define _R_BSP_PRAGMA_STACKSIZE_SI(_size) __R_BSP_PRAGMA_STACKSIZE_SI##_size +#define __R_BSP_PRAGMA_STACKSIZE_SI(size) R_BSP_PRAGMA(stacksize si=size) +#define R_BSP_PRAGMA_STACKSIZE_SU(_size) _R_BSP_PRAGMA_STACKSIZE_SU(_size) /* _size means '(size)' */ +#define _R_BSP_PRAGMA_STACKSIZE_SU(_size) __R_BSP_PRAGMA_STACKSIZE_SU##_size +#define __R_BSP_PRAGMA_STACKSIZE_SU(size) R_BSP_PRAGMA(stacksize su=size) + +#elif defined(__GNUC__) + +#define R_BSP_PRAGMA_STACKSIZE_SI(size) static uint8_t istack_area[size] __attribute__((section(".r_bsp_istack"), used)); +#define R_BSP_PRAGMA_STACKSIZE_SU(size) static uint8_t ustack_area[size] __attribute__((section(".r_bsp_ustack"), used)); + +#elif defined(__ICCRX__) + +#define R_BSP_PRAGMA_STACKSIZE_SI(size) /* none */ +#define R_BSP_PRAGMA_STACKSIZE_SU(size) /* none */ + +#endif + +/* ---------- Section Switch (part1) ---------- */ +#if defined(__CCRX__) + +#define R_BSP_ATTRIB_SECTION_CHANGE_UBSETTINGS R_BSP_PRAGMA(section C UBSETTINGS) +#if defined(__RXV2) || defined(__RXV3) +#define R_BSP_ATTRIB_SECTION_CHANGE_EXCEPTVECT R_BSP_PRAGMA(section C EXCEPTVECT) +#define R_BSP_ATTRIB_SECTION_CHANGE_RESETVECT R_BSP_PRAGMA(section C RESETVECT) +#else +#define R_BSP_ATTRIB_SECTION_CHANGE_FIXEDVECT R_BSP_PRAGMA(section C FIXEDVECT) +#endif + +#elif defined(__GNUC__) + +#define R_BSP_ATTRIB_SECTION_CHANGE_UBSETTINGS __attribute__((section(R_BSP_SECNAME_UBSETTINGS))) +#if defined(__RXV2) || defined(__RXV3) +#define R_BSP_ATTRIB_SECTION_CHANGE_EXCEPTVECT __attribute__((section(R_BSP_SECNAME_EXCEPTVECTTBL))) +#define R_BSP_ATTRIB_SECTION_CHANGE_RESETVECT __attribute__((section(R_BSP_SECNAME_RESETVECT))) +#else +#define R_BSP_ATTRIB_SECTION_CHANGE_FIXEDVECT __attribute__((section(R_BSP_SECNAME_FIXEDVECTTBL))) +#endif + +#elif defined(__ICCRX__) + +#define R_BSP_ATTRIB_SECTION_CHANGE_UBSETTINGS R_BSP_PRAGMA(location=R_BSP_SECNAME_UBSETTINGS) +#if defined(__RXV2) || defined(__RXV3) +#define R_BSP_ATTRIB_SECTION_CHANGE_EXCEPTVECT /* none */ +#define R_BSP_ATTRIB_SECTION_CHANGE_RESETVECT /* none */ +#else +#define R_BSP_ATTRIB_SECTION_CHANGE_FIXEDVECT /* none */ +#endif +#endif + +/* ---------- Section Switch (part2) ---------- */ +#if defined(__CCRX__) + +#define __R_BSP_ATTRIB_SECTION_CHANGE_V(type, section_name) R_BSP_PRAGMA(section type section_name) +#define __R_BSP_ATTRIB_SECTION_CHANGE_F(type, section_name) R_BSP_PRAGMA(section type section_name) + +#define _R_BSP_ATTRIB_SECTION_CHANGE_B1(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(B, B##section_tag) /* The CC-RX adds postfix '_1' automatically */ +#define _R_BSP_ATTRIB_SECTION_CHANGE_B2(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(B, B##section_tag) /* The CC-RX adds postfix '_2' automatically */ +#define _R_BSP_ATTRIB_SECTION_CHANGE_B4(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(B, B##section_tag) /* The CC-RX does not add postfix '_4' */ +#define _R_BSP_ATTRIB_SECTION_CHANGE_B8(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(B, B##section_tag) /* The CC-RX adds postfix '_8' automatically */ +#define _R_BSP_ATTRIB_SECTION_CHANGE_C1(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(C, C##section_tag) /* The CC-RX adds postfix '_1' automatically */ +#define _R_BSP_ATTRIB_SECTION_CHANGE_C2(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(C, C##section_tag) /* The CC-RX adds postfix '_2' automatically */ +#define _R_BSP_ATTRIB_SECTION_CHANGE_C4(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(C, C##section_tag) /* The CC-RX does not add postfix '_4' */ +#define _R_BSP_ATTRIB_SECTION_CHANGE_C8(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(C, C##section_tag) /* The CC-RX adds postfix '_8' automatically */ +#define _R_BSP_ATTRIB_SECTION_CHANGE_D1(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(D, D##section_tag) /* The CC-RX adds postfix '_1' automatically */ +#define _R_BSP_ATTRIB_SECTION_CHANGE_D2(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(D, D##section_tag) /* The CC-RX adds postfix '_2' automatically */ +#define _R_BSP_ATTRIB_SECTION_CHANGE_D4(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(D, D##section_tag) /* The CC-RX does not add postfix '_4' */ +#define _R_BSP_ATTRIB_SECTION_CHANGE_D8(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(D, D##section_tag) /* The CC-RX adds postfix '_8' automatically */ +#define _R_BSP_ATTRIB_SECTION_CHANGE_P(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_F(P, P##section_tag) + +#if !defined(__cplusplus) +#define R_BSP_ATTRIB_SECTION_CHANGE(type, section_tag, ...) _R_BSP_ATTRIB_SECTION_CHANGE_##type##__VA_ARGS__(section_tag) +#else +/* CC-RX' C++ mode does not support variadic macros */ +#define R_BSP_ATTRIB_SECTION_CHANGE(type, section_tag, align) _R_BSP_ATTRIB_SECTION_CHANGE_##type##align(section_tag) +#endif + +#define R_BSP_ATTRIB_SECTION_CHANGE_END R_BSP_PRAGMA(section) + +#elif defined(__GNUC__) + +#define __R_BSP_ATTRIB_SECTION_CHANGE_V(section_name) __attribute__((section(#section_name))) +#define __R_BSP_ATTRIB_SECTION_CHANGE_F(section_name) __attribute__((section(#section_name))) + +#define _R_BSP_ATTRIB_SECTION_CHANGE_B1(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(B##section_tag##_1) +#define _R_BSP_ATTRIB_SECTION_CHANGE_B2(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(B##section_tag##_2) +#define _R_BSP_ATTRIB_SECTION_CHANGE_B4(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(B##section_tag) /* No postfix '_4' because the CC-RX does not add it */ +#define _R_BSP_ATTRIB_SECTION_CHANGE_B8(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(B##section_tag##_8) +#define _R_BSP_ATTRIB_SECTION_CHANGE_C1(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(C##section_tag##_1) +#define _R_BSP_ATTRIB_SECTION_CHANGE_C2(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(C##section_tag##_2) +#define _R_BSP_ATTRIB_SECTION_CHANGE_C4(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(C##section_tag) /* No postfix '_4' because the CC-RX does not add it */ +#define _R_BSP_ATTRIB_SECTION_CHANGE_C8(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(C##section_tag##_8) +#define _R_BSP_ATTRIB_SECTION_CHANGE_D1(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(D##section_tag##_1) +#define _R_BSP_ATTRIB_SECTION_CHANGE_D2(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(D##section_tag##_2) +#define _R_BSP_ATTRIB_SECTION_CHANGE_D4(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(D##section_tag) /* No postfix '_4' because the CC-RX does not add it */ +#define _R_BSP_ATTRIB_SECTION_CHANGE_D8(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(D##section_tag##_8) +#define _R_BSP_ATTRIB_SECTION_CHANGE_P(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_F(P##section_tag) + +#define R_BSP_ATTRIB_SECTION_CHANGE(type, section_tag, ...) _R_BSP_ATTRIB_SECTION_CHANGE_##type##__VA_ARGS__(section_tag) +#define R_BSP_ATTRIB_SECTION_CHANGE_END /* none */ + +#elif defined(__ICCRX__) + +#define __R_BSP_ATTRIB_SECTION_CHANGE_V(section_name) R_BSP_PRAGMA(location=#section_name)\ + __no_init +#define __R_BSP_ATTRIB_SECTION_CHANGE_F(section_name) R_BSP_PRAGMA(location=#section_name) + +#define _R_BSP_ATTRIB_SECTION_CHANGE_B1(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(B##section_tag##_1) +#define _R_BSP_ATTRIB_SECTION_CHANGE_B2(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(B##section_tag##_2) +#define _R_BSP_ATTRIB_SECTION_CHANGE_B4(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(B##section_tag) /* No postfix '_4' because the CC-RX does not add it */ +#define _R_BSP_ATTRIB_SECTION_CHANGE_B8(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_V(B##section_tag##_8) +#define _R_BSP_ATTRIB_SECTION_CHANGE_C1(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_F(C##section_tag##_1) +#define _R_BSP_ATTRIB_SECTION_CHANGE_C2(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_F(C##section_tag##_2) +#define _R_BSP_ATTRIB_SECTION_CHANGE_C4(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_F(C##section_tag) /* No postfix '_4' because the CC-RX does not add it */ +#define _R_BSP_ATTRIB_SECTION_CHANGE_C8(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_F(C##section_tag##_8) +#define _R_BSP_ATTRIB_SECTION_CHANGE_D1(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_F(D##section_tag##_1) +#define _R_BSP_ATTRIB_SECTION_CHANGE_D2(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_F(D##section_tag##_2) +#define _R_BSP_ATTRIB_SECTION_CHANGE_D4(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_F(D##section_tag) /* No postfix '_4' because the CC-RX does not add it */ +#define _R_BSP_ATTRIB_SECTION_CHANGE_D8(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_F(D##section_tag##_8) +#define _R_BSP_ATTRIB_SECTION_CHANGE_P(section_tag) __R_BSP_ATTRIB_SECTION_CHANGE_F(P##section_tag) + +#define R_BSP_ATTRIB_SECTION_CHANGE(type, section_tag, ...) _R_BSP_ATTRIB_SECTION_CHANGE_##type##__VA_ARGS__(section_tag) +#define R_BSP_ATTRIB_SECTION_CHANGE_END /* none */ + +#endif + +/* ---------- Interrupt Function Creation ---------- */ +#if defined(__CCRX__) + +/* Standard */ +#if BSP_CFG_RTOS_USED == 4 /* Renesas RI600V4 & RI600PX */ +#define R_BSP_PRAGMA_INTERRUPT(function_name, vector) extern void function_name(void); + +#define R_BSP_PRAGMA_STATIC_INTERRUPT(function_name, vector) void function_name(void); + +#define R_BSP_PRAGMA_INTERRUPT_FUNCTION(function_name) extern void function_name(void); + +#else /* BSP_CFG_RTOS_USED != 4*/ +#define R_BSP_PRAGMA_INTERRUPT(function_name, vector) R_BSP_PRAGMA(interrupt function_name(vect=vector))\ + extern void function_name(void); +#define R_BSP_PRAGMA_STATIC_INTERRUPT(function_name, vector) R_BSP_PRAGMA(interrupt function_name(vect=vector))\ + static void function_name(void); + +#define R_BSP_PRAGMA_INTERRUPT_FUNCTION(function_name) R_BSP_PRAGMA(interrupt function_name)\ + extern void function_name(void); +#endif /* BSP_CFG_RTOS_USED */ + +#define R_BSP_PRAGMA_STATIC_INTERRUPT_FUNCTION(function_name) R_BSP_PRAGMA(interrupt function_name)\ + static void function_name(void); + +#define R_BSP_ATTRIB_INTERRUPT extern /* only this one because of no corresponding keyword */ + +#if BSP_CFG_RTOS_USED == 4 /* Renesas RI600V4 & RI600PX */ +#define R_BSP_ATTRIB_STATIC_INTERRUPT +#else /* BSP_CFG_RTOS_USED !=4 */ +#define R_BSP_ATTRIB_STATIC_INTERRUPT static /* only this one because of no corresponding keyword */ +#endif /* BSP_CFG_RTOS_USED */ + +/* Fast */ +#define R_BSP_PRAGMA_FAST_INTERRUPT(function_name, vector) R_BSP_PRAGMA(interrupt function_name(vect=vector, fint))\ + extern void function_name(void); +#define R_BSP_PRAGMA_STATIC_FAST_INTERRUPT(function_name, vector) R_BSP_PRAGMA(interrupt function_name(vect=vector, fint))\ + static void function_name(void); + +#define R_BSP_PRAGMA_FAST_INTERRUPT_FUNCTION(function_name) R_BSP_PRAGMA(interrupt function_name(fint))\ + extern void function_name(void); +#define R_BSP_PRAGMA_STATIC_FAST_INTERRUPT_FUNCTION(function_name) R_BSP_PRAGMA(interrupt function_name(fint))\ + static void function_name(void); + +#define R_BSP_ATTRIB_FAST_INTERRUPT extern /* only this one because of no corresponding keyword */ +#define R_BSP_ATTRIB_STATIC_FAST_INTERRUPT static /* only this one because of no corresponding keyword */ + +/* Default */ +#if BSP_CFG_RTOS_USED == 4 /* Renesas RI600V4 & RI600PX */ +#define R_BSP_PRAGMA_INTERRUPT_DEFAULT(function_name) extern void function_name(void); + +#define R_BSP_PRAGMA_STATIC_INTERRUPT_DEFAULT(function_name) void function_name(void); +#else /* BSP_CFG_RTOS_USED != 4 */ +#define R_BSP_PRAGMA_INTERRUPT_DEFAULT(function_name) R_BSP_PRAGMA(interrupt function_name)\ + extern void function_name(void); + +#define R_BSP_PRAGMA_STATIC_INTERRUPT_DEFAULT(function_name) R_BSP_PRAGMA(interrupt function_name)\ + static void function_name(void); +#endif /* BSP_CFG_RTOS_USED */ + +#elif defined(__GNUC__) + +/* Standard */ +#define R_BSP_PRAGMA_INTERRUPT(function_name, vector) extern void function_name(void) __attribute__((interrupt(R_BSP_SECNAME_INTVECTTBL, vector))); +#define R_BSP_PRAGMA_STATIC_INTERRUPT(function_name, vector) static void function_name(void) __attribute__((interrupt(R_BSP_SECNAME_INTVECTTBL, vector), used)); + +#define R_BSP_PRAGMA_INTERRUPT_FUNCTION(function_name) extern void function_name(void) __attribute__((interrupt)); +#define R_BSP_PRAGMA_STATIC_INTERRUPT_FUNCTION(function_name) static void function_name(void) __attribute__((interrupt, used)); + +#define R_BSP_ATTRIB_INTERRUPT extern /* only this one because __attribute__((interrupt)) prevents GNURX from generating vector */ +#define R_BSP_ATTRIB_STATIC_INTERRUPT static /* only this one because __attribute__((interrupt, used)) prevents GNURX from generating vector */ + +/* Fast */ +#define R_BSP_PRAGMA_FAST_INTERRUPT(function_name, vector) extern void function_name(void) __attribute__((interrupt(R_BSP_SECNAME_INTVECTTBL, vector))) \ + __attribute__((fast_interrupt)); +#define R_BSP_PRAGMA_STATIC_FAST_INTERRUPT(function_name, vector) static void function_name(void) __attribute__((interrupt(R_BSP_SECNAME_INTVECTTBL, vector), used)) \ + __attribute__((fast_interrupt, used)); + +#define R_BSP_PRAGMA_FAST_INTERRUPT_FUNCTION(function_name) extern void function_name(void) __attribute__((fast_interrupt)); +#define R_BSP_PRAGMA_STATIC_FAST_INTERRUPT_FUNCTION(function_name) static void function_name(void) __attribute__((fast_interrupt, used)); + +#define R_BSP_ATTRIB_FAST_INTERRUPT extern /* __attribute__((interrupt(fast))) Not necessary, + but Don't forget a R_BSP_PRAGMA_FAST_INTERRUPT() declaration */ +#define R_BSP_ATTRIB_STATIC_FAST_INTERRUPT static /* __attribute__((interrupt(fast)), used) Not necessary, + but Don't forget a R_BSP_PRAGMA_STATIC_FAST_INTERRUPT() declaration */ + +/* Default */ +#define R_BSP_PRAGMA_INTERRUPT_DEFAULT(function_name) extern void function_name(void) __attribute__((interrupt(R_BSP_SECNAME_INTVECTTBL, "$default"))); +#define R_BSP_PRAGMA_STATIC_INTERRUPT_DEFAULT(function_name) static void function_name(void) __attribute__((interrupt(R_BSP_SECNAME_INTVECTTBL, "$default"), used)); + +#elif defined(__ICCRX__) + +/* Standard */ +#define R_BSP_PRAGMA_INTERRUPT(function_name, vect) R_BSP_PRAGMA(vector=vect)\ + extern __interrupt void function_name(void); +#define R_BSP_PRAGMA_STATIC_INTERRUPT(function_name, vect) R_BSP_PRAGMA(vector=vect)\ + static __interrupt void function_name(void); + +#define R_BSP_PRAGMA_INTERRUPT_FUNCTION(function_name) extern __interrupt void function_name(void); +#define R_BSP_PRAGMA_STATIC_INTERRUPT_FUNCTION(function_name) static __interrupt void function_name(void); + +#define R_BSP_ATTRIB_INTERRUPT extern __interrupt /* ICCRX requires __interrupt not only at a function declaration but also at a function definition */ +#define R_BSP_ATTRIB_STATIC_INTERRUPT static __interrupt /* ICCRX requires __interrupt not only at a function declaration but also at a function definition */ + +/* Fast */ +#define R_BSP_PRAGMA_FAST_INTERRUPT(function_name, vect) R_BSP_PRAGMA(vector=vect)\ + extern __fast_interrupt void function_name(void); +#define R_BSP_PRAGMA_STATIC_FAST_INTERRUPT(function_name, vect) R_BSP_PRAGMA(vector=vect)\ + static __fast_interrupt void function_name(void); + +#define R_BSP_PRAGMA_FAST_INTERRUPT_FUNCTION(function_name) extern __fast_interrupt void function_name(void); +#define R_BSP_PRAGMA_STATIC_FAST_INTERRUPT_FUNCTION(function_name) static __fast_interrupt void function_name(void); + +#define R_BSP_ATTRIB_FAST_INTERRUPT extern __fast_interrupt /* ICCRX requires __interrupt not only at a function declaration but also at a function definition */ +#define R_BSP_ATTRIB_STATIC_FAST_INTERRUPT static __fast_interrupt /* ICCRX requires __interrupt not only at a function declaration but also at a function definition */ + +/* Default */ +#define R_BSP_PRAGMA_INTERRUPT_DEFAULT(function_name) extern __interrupt void function_name(void); +#define R_BSP_PRAGMA_STATIC_INTERRUPT_DEFAULT(function_name) static __interrupt void function_name(void); + +#endif + +/* ---------- Inline Expansion of Function ---------- */ +#if defined(__CCRX__) + +#define R_BSP_PRAGMA_INLINE(function_name) R_BSP_PRAGMA(inline function_name)\ + extern +#define R_BSP_PRAGMA_STATIC_INLINE(function_name) R_BSP_PRAGMA(inline function_name)\ + static + +#elif defined(__GNUC__) + +#define R_BSP_PRAGMA_INLINE(function_name) inline extern __attribute__((always_inline)) +#define R_BSP_PRAGMA_STATIC_INLINE(function_name) inline static __attribute__((always_inline)) + +#elif defined(__ICCRX__) + +#define R_BSP_PRAGMA_INLINE(function_name) R_BSP_PRAGMA(inline=forced)\ + extern +#define R_BSP_PRAGMA_STATIC_INLINE(function_name) R_BSP_PRAGMA(inline=forced)\ + static + +#endif + +/* ---------- Inline Expansion of Assembly-Language Function (part1) ---------- */ +#if defined(__CCRX__) + +#define R_BSP_PRAGMA_INLINE_ASM(function_name) R_BSP_PRAGMA(inline_asm function_name)\ + extern +#define R_BSP_PRAGMA_STATIC_INLINE_ASM(function_name) R_BSP_PRAGMA(inline_asm function_name)\ + static + +#define R_BSP_ATTRIB_INLINE_ASM extern /* only this one because of no corresponding keyword */ +#define R_BSP_ATTRIB_STATIC_INLINE_ASM static /* only this one because of no corresponding keyword */ + +#elif defined(__GNUC__) + +/* Using inline assembler without operands and clobbered resources is dangerous but using it with them is too difficult. */ + +#define R_BSP_PRAGMA_INLINE_ASM(function_name) extern __attribute__((naked, noinline)) +#define R_BSP_PRAGMA_STATIC_INLINE_ASM(function_name) static __attribute__((naked, noinline)) + +#define R_BSP_ATTRIB_INLINE_ASM extern /* only this one because of no corresponding keyword */ +#define R_BSP_ATTRIB_STATIC_INLINE_ASM static /* only this one because of no corresponding keyword */ + +#elif defined(__ICCRX__) + +/* Using inline assembler without operands and clobbered resources is dangerous but using it with them is too difficult. */ + +#define R_BSP_PRAGMA_INLINE_ASM(function_name) R_BSP_PRAGMA(inline=never)\ + extern +#define R_BSP_PRAGMA_STATIC_INLINE_ASM(function_name) R_BSP_PRAGMA(inline=never)\ + static + +#define R_BSP_ATTRIB_INLINE_ASM extern /* ICCRX requires __task not only at a function declaration but also at a function definition */ +#define R_BSP_ATTRIB_STATIC_INLINE_ASM static /* ICCRX requires __task not only at a function declaration but also at a function definition */ + +#endif + +/* ---------- Inline Expansion of Assembly-Language Function (part2) ---------- */ +#if defined(__CDT_PARSER__) + +#define R_BSP_ASM(...) /* none */ +#define R_BSP_ASM_LAB_NEXT(n) /* none */ +#define R_BSP_ASM_LAB_PREV(n) /* none */ +#define R_BSP_ASM_LAB(n_colon) /* none */ +#define R_BSP_ASM_BEGIN /* none */ +#define R_BSP_ASM_END /* none */ + +#else + +#if defined(__CCRX__) + +#if !defined(__cplusplus) +#define R_BSP_ASM(...) __VA_ARGS__ +#else +/* CC-RX' C++ mode does not support variadic macros */ +#endif +#define R_BSP_ASM_LAB_NEXT(n) ?+ +#define R_BSP_ASM_LAB_PREV(n) ?- +#define R_BSP_ASM_LAB(n_colon) R_BSP_ASM(?:) +#define R_BSP_ASM_BEGIN /* none */ +#define R_BSP_ASM_END /* none */ + +#elif defined(__GNUC__) + +#define _R_BSP_ASM(...) #__VA_ARGS__ +#define R_BSP_ASM(...) _R_BSP_ASM(__VA_ARGS__\n) +#define R_BSP_ASM_LAB_NEXT(n) ?+ +#define R_BSP_ASM_LAB_PREV(n) ?- +#define R_BSP_ASM_LAB(n_colon) R_BSP_ASM(?:) +#define R_BSP_ASM_BEGIN __asm__ volatile ( +#define R_BSP_ASM_END R_BSP_ASM(rts)); + +#elif defined(__ICCRX__) + +#define _R_BSP_ASM(...) #__VA_ARGS__ "\n" +#define R_BSP_ASM(...) _R_BSP_ASM(__VA_ARGS__) +#define R_BSP_ASM_LAB_NEXT(n) _lab##n +#define R_BSP_ASM_LAB_PREV(n) _lab##n +#define R_BSP_ASM_LAB(n_colon) R_BSP_ASM(_lab##n_colon) +#define R_BSP_ASM_BEGIN R_BSP_PRAGMA(diag_suppress = Pa174)\ + R_BSP_PRAGMA(diag_suppress = Pe010)\ + __asm volatile( +#define R_BSP_ASM_END );\ + R_BSP_PRAGMA(diag_default = Pe010)\ + R_BSP_PRAGMA(diag_default = Pa174) + +#endif + +#endif /* defined(__CDT_PARSER__) */ + +/* ---------- Inline Expansion of Assembly-Language Function (part3) ---------- */ +#if defined(__CCRX__) + +#define R_BSP_ASM_INTERNAL_USED(p) /* no way */ +#define R_BSP_ASM_INTERNAL_NOT_USED(p) /* no way */ + +#elif defined(__GNUC__) + +#define R_BSP_ASM_INTERNAL_USED(p) ((void)(p)); +#define R_BSP_ASM_INTERNAL_NOT_USED(p) ((void)(p)); + +#elif defined(__ICCRX__) + +#define R_BSP_ASM_INTERNAL_USED(p) ((void)(p)); +#define R_BSP_ASM_INTERNAL_NOT_USED(p) ((void)(p)); + +#endif + +/* ---------- Bit Field Order Specification ---------- */ + +/* ---------- bit_order=left ---------- */ +#if defined(__CCRX__) + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27, bf28, bf29, \ + bf30, bf31)\ +struct {\ +R_BSP_PRAGMA(bit_order left)\ + struct {\ + bf0;\ + bf1;\ + bf2;\ + bf3;\ + bf4;\ + bf5;\ + bf6;\ + bf7;\ + bf8;\ + bf9;\ + bf10;\ + bf11;\ + bf12;\ + bf13;\ + bf14;\ + bf15;\ + bf16;\ + bf17;\ + bf18;\ + bf19;\ + bf20;\ + bf21;\ + bf22;\ + bf23;\ + bf24;\ + bf25;\ + bf26;\ + bf27;\ + bf28;\ + bf29;\ + bf30;\ + bf31;\ + };\ +R_BSP_PRAGMA(bit_order)\ +} + +#elif defined(__GNUC__) + +#if defined(__LIT) + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27, bf28, bf29, \ + bf30, bf31)\ +struct {\ + bf31;\ + bf30;\ + bf29;\ + bf28;\ + bf27;\ + bf26;\ + bf25;\ + bf24;\ + bf23;\ + bf22;\ + bf21;\ + bf20;\ + bf19;\ + bf18;\ + bf17;\ + bf16;\ + bf15;\ + bf14;\ + bf13;\ + bf12;\ + bf11;\ + bf10;\ + bf9;\ + bf8;\ + bf7;\ + bf6;\ + bf5;\ + bf4;\ + bf3;\ + bf2;\ + bf1;\ + bf0;\ +} + +#else /* defined(__LIT) */ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27, bf28, bf29, \ + bf30, bf31)\ +struct {\ + bf0;\ + bf1;\ + bf2;\ + bf3;\ + bf4;\ + bf5;\ + bf6;\ + bf7;\ + bf8;\ + bf9;\ + bf10;\ + bf11;\ + bf12;\ + bf13;\ + bf14;\ + bf15;\ + bf16;\ + bf17;\ + bf18;\ + bf19;\ + bf20;\ + bf21;\ + bf22;\ + bf23;\ + bf24;\ + bf25;\ + bf26;\ + bf27;\ + bf28;\ + bf29;\ + bf30;\ + bf31;\ +} + +#endif /* defined(__LIT) */ + +#elif defined(__ICCRX__) + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27, bf28, bf29, \ + bf30, bf31)\ +struct {\ +R_BSP_PRAGMA(bitfields=reversed_disjoint_types)\ + struct {\ + bf0;\ + bf1;\ + bf2;\ + bf3;\ + bf4;\ + bf5;\ + bf6;\ + bf7;\ + bf8;\ + bf9;\ + bf10;\ + bf11;\ + bf12;\ + bf13;\ + bf14;\ + bf15;\ + bf16;\ + bf17;\ + bf18;\ + bf19;\ + bf20;\ + bf21;\ + bf22;\ + bf23;\ + bf24;\ + bf25;\ + bf26;\ + bf27;\ + bf28;\ + bf29;\ + bf30;\ + bf31;\ + };\ +R_BSP_PRAGMA(bitfields=default)\ +} + +#endif /* defined(__ICCRX__) */ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_1(bf0)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_2(bf0, bf1)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_3(bf0, bf1, bf2)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_4(bf0, bf1, bf2, bf3)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_5(bf0, bf1, bf2, bf3, bf4)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_6(bf0, bf1, bf2, bf3, bf4, bf5)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_7(bf0, bf1, bf2, bf3, bf4, bf5, bf6)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_8(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_9(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_10(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_11(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_12(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_13(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_14(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_15(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_16(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_17(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_18(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_19(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_20(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_21(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_22(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, bf21, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_23(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, bf21, bf22, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_24(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_25(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \ + bf24, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_26(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24, bf25)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \ + bf24, bf25, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_27(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24, bf25, bf26)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \ + bf24, bf25, bf26, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_28(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \ + bf24, bf25, bf26, bf27, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_29(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27, bf28)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \ + bf24, bf25, bf26, bf27, bf28, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_30(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27, bf28, bf29)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \ + bf24, bf25, bf26, bf27, bf28, bf29, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_31(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27, bf28, bf29, \ + bf30)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \ + bf24, bf25, bf26, bf27, bf28, bf29, bf30, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT_32(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27, bf28, bf29, \ + bf30, bf31)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_LEFT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \ + bf24, bf25, bf26, bf27, bf28, bf29, bf30, bf31) \ + +/* ---------- bit_order=right ---------- */ +#if defined(__CCRX__) + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27, bf28, bf29, \ + bf30, bf31)\ +struct {\ +R_BSP_PRAGMA(bit_order right)\ + struct {\ + bf0;\ + bf1;\ + bf2;\ + bf3;\ + bf4;\ + bf5;\ + bf6;\ + bf7;\ + bf8;\ + bf9;\ + bf10;\ + bf11;\ + bf12;\ + bf13;\ + bf14;\ + bf15;\ + bf16;\ + bf17;\ + bf18;\ + bf19;\ + bf20;\ + bf21;\ + bf22;\ + bf23;\ + bf24;\ + bf25;\ + bf26;\ + bf27;\ + bf28;\ + bf29;\ + bf30;\ + bf31;\ + };\ +R_BSP_PRAGMA(bit_order)\ +} + +#elif defined(__GNUC__) + +#if defined(__LIT) + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27, bf28, bf29, \ + bf30, bf31)\ +struct {\ + bf0;\ + bf1;\ + bf2;\ + bf3;\ + bf4;\ + bf5;\ + bf6;\ + bf7;\ + bf8;\ + bf9;\ + bf10;\ + bf11;\ + bf12;\ + bf13;\ + bf14;\ + bf15;\ + bf16;\ + bf17;\ + bf18;\ + bf19;\ + bf20;\ + bf21;\ + bf22;\ + bf23;\ + bf24;\ + bf25;\ + bf26;\ + bf27;\ + bf28;\ + bf29;\ + bf30;\ + bf31;\ +} + +#else /* defined(__LIT) */ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27, bf28, bf29, \ + bf30, bf31)\ +struct {\ + bf31;\ + bf30;\ + bf29;\ + bf28;\ + bf27;\ + bf26;\ + bf25;\ + bf24;\ + bf23;\ + bf22;\ + bf21;\ + bf20;\ + bf19;\ + bf18;\ + bf17;\ + bf16;\ + bf15;\ + bf14;\ + bf13;\ + bf12;\ + bf11;\ + bf10;\ + bf9;\ + bf8;\ + bf7;\ + bf6;\ + bf5;\ + bf4;\ + bf3;\ + bf2;\ + bf1;\ + bf0;\ +} + +#endif /* defined(__LIT) */ + +#elif defined(__ICCRX__) + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27, bf28, bf29, \ + bf30, bf31)\ +struct {\ +R_BSP_PRAGMA(bitfields=disjoint_types)\ + struct {\ + bf0;\ + bf1;\ + bf2;\ + bf3;\ + bf4;\ + bf5;\ + bf6;\ + bf7;\ + bf8;\ + bf9;\ + bf10;\ + bf11;\ + bf12;\ + bf13;\ + bf14;\ + bf15;\ + bf16;\ + bf17;\ + bf18;\ + bf19;\ + bf20;\ + bf21;\ + bf22;\ + bf23;\ + bf24;\ + bf25;\ + bf26;\ + bf27;\ + bf28;\ + bf29;\ + bf30;\ + bf31;\ + };\ +R_BSP_PRAGMA(bitfields=default)\ +} + +#endif /* defined(__ICCRX__) */ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_1(bf0)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_2(bf0, bf1)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_3(bf0, bf1, bf2)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_4(bf0, bf1, bf2, bf3)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_5(bf0, bf1, bf2, bf3, bf4)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_6(bf0, bf1, bf2, bf3, bf4, bf5)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_7(bf0, bf1, bf2, bf3, bf4, bf5, bf6)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_8(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_9(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_10(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_11(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_12(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_13(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_14(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_15(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_16(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_17(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_18(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_19(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_20(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_21(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, uint8_t :0, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_22(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, bf21, uint8_t :0, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_23(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, bf21, bf22, uint8_t :0, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_24(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \ + uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_25(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \ + bf24, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_26(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24, bf25)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \ + bf24, bf25, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_27(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24, bf25, bf26)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \ + bf24, bf25, bf26, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_28(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \ + bf24, bf25, bf26, bf27, uint8_t :0, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_29(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27, bf28)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \ + bf24, bf25, bf26, bf27, bf28, uint8_t :0, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_30(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27, bf28, bf29)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \ + bf24, bf25, bf26, bf27, bf28, bf29, uint8_t :0, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_31(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27, bf28, bf29, \ + bf30)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \ + bf24, bf25, bf26, bf27, bf28, bf29, bf30, uint8_t :0) \ + +#define R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT_32(bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8, bf9, \ + bf10, bf11, bf12, bf13, bf14, bf15, bf16, bf17, bf18, bf19, \ + bf20, bf21, bf22, bf23, bf24, bf25, bf26, bf27, bf28, bf29, \ + bf30, bf31)\ + R_BSP_ATTRIB_STRUCT_BIT_ORDER_RIGHT( \ + bf0, bf1, bf2, bf3, bf4, bf5, bf6, bf7, \ + bf8, bf9, bf10, bf11, bf12, bf13, bf14, bf15, \ + bf16, bf17, bf18, bf19, bf20, bf21, bf22, bf23, \ + bf24, bf25, bf26, bf27, bf28, bf29, bf30, bf31) \ + +/* ---------- Alignment Value Specification for Structure Members and Class Members ---------- */ +#if defined(__CCRX__) + +#define R_BSP_PRAGMA_PACK R_BSP_PRAGMA(pack) +#define R_BSP_PRAGMA_UNPACK R_BSP_PRAGMA(unpack) +#define R_BSP_PRAGMA_PACKOPTION R_BSP_PRAGMA(packoption) + +#elif defined(__GNUC__) + +#define R_BSP_PRAGMA_PACK R_BSP_PRAGMA(pack(1)) +#define R_BSP_PRAGMA_UNPACK R_BSP_PRAGMA(pack(4)) +#define R_BSP_PRAGMA_PACKOPTION R_BSP_PRAGMA(pack()) + +#elif defined(__ICCRX__) + +#define R_BSP_PRAGMA_PACK R_BSP_PRAGMA(pack(1)) +#define R_BSP_PRAGMA_UNPACK R_BSP_PRAGMA(pack(4)) +#define R_BSP_PRAGMA_PACKOPTION R_BSP_PRAGMA(pack()) + +#endif + +/* ========== Rename Functions ========== */ + +#if defined(__CCRX__) + +#define R_BSP_POR_FUNCTION(name) extern void name(void) +#define R_BSP_POWER_ON_RESET_FUNCTION PowerON_Reset_PC +#define R_BSP_STARTUP_FUNCTION PowerON_Reset_PC + +#define R_BSP_UB_POR_FUNCTION(name) extern void name(void) +#define R_BSP_UB_POWER_ON_RESET_FUNCTION PowerON_Reset_PC + +#define R_BSP_MAIN_FUNCTION main + +/* #define _INITSCT */ +/* #define excep_supervisor_inst_isr */ +/* #define excep_access_isr */ +/* #define excep_undefined_inst_isr */ +/* #define excep_floating_point_isr */ +/* #define non_maskable_isr */ +/* #define undefined_interrupt_source_isr */ +/* #define excep_address_isr */ + +#elif defined(__GNUC__) + +#define R_BSP_POR_FUNCTION(name) extern void name(void) +#define R_BSP_POWER_ON_RESET_FUNCTION PowerON_Reset_PC +#define R_BSP_STARTUP_FUNCTION PowerON_Reset_PC_Prg + +#define R_BSP_UB_POR_FUNCTION(name) extern void name(void) +#define R_BSP_UB_POWER_ON_RESET_FUNCTION PowerON_Reset_PC + +#define R_BSP_MAIN_FUNCTION main + +/* #define _INITSCT */ +/* #define excep_supervisor_inst_isr */ +/* #define excep_access_isr */ +/* #define excep_undefined_inst_isr */ +/* #define excep_floating_point_isr */ +/* #define non_maskable_isr */ +/* #define undefined_interrupt_source_isr */ +/* #define excep_address_isr */ + +#elif defined(__ICCRX__) + +#define R_BSP_POR_FUNCTION(name) extern int name(void) +#define R_BSP_POWER_ON_RESET_FUNCTION _iar_program_start +#define R_BSP_STARTUP_FUNCTION __low_level_init + +#define R_BSP_UB_POR_FUNCTION(name) extern int name(void) +#define R_BSP_UB_POWER_ON_RESET_FUNCTION _iar_program_start + +#define R_BSP_MAIN_FUNCTION _iar_main_call + +#define _INITSCT __iar_data_init2 +#define excep_supervisor_inst_isr __privileged_handler +#define excep_access_isr __excep_access_inst +#define excep_undefined_inst_isr __undefined_handler +#define excep_floating_point_isr _float_placeholder +#define non_maskable_isr __NMI_handler +#define undefined_interrupt_source_isr __undefined_interrupt_source_handler +#define excep_address_isr __excep_address_inst + +#endif + +#endif /* R_RX_COMPILER_H */ + diff --git a/drivers/rx/rdp/src/r_bsp/mcu/all/r_rx_intrinsic_functions.c b/drivers/rx/rdp/src/r_bsp/mcu/all/r_rx_intrinsic_functions.c new file mode 100644 index 00000000..b2eca8eb --- /dev/null +++ b/drivers/rx/rdp/src/r_bsp/mcu/all/r_rx_intrinsic_functions.c @@ -0,0 +1,1254 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 - 2024 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_rx_intrinsic_functions.c +* Description : Defines built-in functions that are in CCRX but not in the GCC and IAR compiler. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 28.02.2019 1.00 First Release +* : 26.07.2019 1.01 Fixed the below functions. +* - R_BSP_MulAndAccOperation_2byte +* - R_BSP_MulAndAccOperation_FixedPoint1 +* - R_BSP_MulAndAccOperation_FixedPoint2 +* Added the below functions. +* - R_BSP_CalcSine_Cosine +* - R_BSP_CalcAtan_SquareRoot +* : 31.07.2019 1.02 Modified the compile condition of the below functions. +* - R_BSP_InitTFU +* - R_BSP_CalcSine_Cosine +* - R_BSP_CalcAtan_SquareRoot +* : 10.12.2019 1.03 Fixed the below functions. +* - R_BSP_MulAndAccOperation_2byte +* - R_BSP_MulAndAccOperation_FixedPoint1 +* - R_BSP_MulAndAccOperation_FixedPoint2 +* : 17.12.2019 1.04 Modified the comment of description. +* : 28.02.2023 1.05 Added the below functions. +* - R_BSP_CalcSine_Cosine_Fpn +* - R_BSP_CalcSine_Fpn +* - R_BSP_CalcCosine_Fpn +* - R_BSP_CalcAtan_SquareRoot_Fpn +* - R_BSP_CalcAtan_Fpn +* - R_BSP_CalcSquareRoot_Fpn +* - bsp_calc_sine_fsp +* - bsp_calc_cosine_fsp +* - bsp_calc_atan_fsp +* - bsp_calc_squareroot_fsp +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_rx_compiler.h" +#include "r_rx_intrinsic_functions.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ +R_BSP_ATTRIB_STATIC_INLINE_ASM void bsp_get_bpsw(uint32_t *data); +R_BSP_ATTRIB_STATIC_INLINE_ASM void bsp_get_bpc(uint32_t *data); +#ifdef BSP_MCU_EXCEPTION_TABLE +R_BSP_ATTRIB_STATIC_INLINE_ASM void bsp_get_extb(uint32_t *data); +#endif /* BSP_MCU_EXCEPTION_TABLE */ +R_BSP_ATTRIB_STATIC_INLINE_ASM void bsp_move_from_acc_hi_long(uint32_t *data); +R_BSP_ATTRIB_STATIC_INLINE_ASM void bsp_move_from_acc_mi_long(uint32_t *data); +#ifdef BSP_MCU_DOUBLE_PRECISION_FLOATING_POINT +#ifdef __DPFPU +R_BSP_ATTRIB_STATIC_INLINE_ASM void bsp_get_dpsw(uint32_t *data); +R_BSP_ATTRIB_STATIC_INLINE_ASM void bsp_get_decnt(uint32_t *data); +R_BSP_ATTRIB_STATIC_INLINE_ASM void bsp_get_depc(uint32_t *ret); +#endif /* __DPFPU */ +#endif /* BSP_MCU_DOUBLE_PRECISION_FLOATING_POINT */ +#ifdef BSP_MCU_TRIGONOMETRIC +#ifdef __TFU +#if BSP_MCU_TFU_VERSION == 2 +R_BSP_ATTRIB_STATIC_INLINE_ASM void bsp_calc_sine_fsp(int32_t *ret, int32_t fx); +R_BSP_ATTRIB_STATIC_INLINE_ASM void bsp_calc_cosine_fsp(int32_t *ret, int32_t fx); +R_BSP_ATTRIB_STATIC_INLINE_ASM void bsp_calc_atan_fsp(int32_t *ret, int32_t y, int32_t x); +R_BSP_ATTRIB_STATIC_INLINE_ASM void bsp_calc_squareroot_fsp(int32_t *ret, int32_t y, int32_t x); +#endif /* BSP_MCU_TFU_VERSION == 2 */ +#endif /* __TFU */ +#endif /* BSP_MCU_TRIGONOMETRIC */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_Max +* Description : Selects the greater of two input values. +* Arguments : data1 - Input value 1. +* data2 - Input value 2. +* Return Value : The greater value of data1 and data2. +***********************************************************************************************************************/ +#if defined(__GNUC__) +signed long R_BSP_Max(signed long data1, signed long data2) +{ + return (data1 > data2)? data1 : data2; +} +#endif /* defined(__GNUC__) */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_Min +* Description : Selects the smaller of two input values. +* Arguments : data1 - Input value 1. +* data2 - Input value 2. +* Return Value : The smaller value of data1 and data2. +***********************************************************************************************************************/ +#if defined(__GNUC__) +signed long R_BSP_Min(signed long data1, signed long data2) +{ + return (data1 < data2)? data1 : data2; +} +#endif /* defined(__GNUC__) */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_MulAndAccOperation_B +* Description : Performs a multiply-and-accumulate operation with the initial value specified by init, the number of +* multiply-and-accumulate operations specified by count, and the start addresses of values to be +* multiplied specified by addr1 and addr2. +* Arguments : init - Initial value. +* count - Count of multiply-and-accumulate operations. +* *addr1 - Start address of values 1 to be multiplied. +* *addr2 - Start address of values 2 to be multiplied. +* Return Value : result - Lower 64 bits of the init + S(data1[n] * data2[n]) result. (n=0, 1, ..., const-1) +***********************************************************************************************************************/ +#if defined(__GNUC__) +long long R_BSP_MulAndAccOperation_B(long long init, unsigned long count, signed char *addr1, signed char *addr2) +{ + long long result = init; + unsigned long index; + for(index = 0; index < count; index++) + { + result += addr1[index] * addr2[index]; + } + return result; +} +#endif /* defined(__GNUC__) */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_MulAndAccOperation_W +* Description : Performs a multiply-and-accumulate operation with the initial value specified by init, the number of +* multiply-and-accumulate operations specified by count, and the start addresses of values to be +* multiplied specified by addr1 and addr2. +* Arguments : init - Initial value. +* count - Count of multiply-and-accumulate operations. +* *addr1 - Start address of values 1 to be multiplied. +* *addr2 - Start address of values 2 to be multiplied. +* Return Value : result - Lower 64 bits of the init + S(data1[n] * data2[n]) result. (n=0, 1, ..., const-1) +***********************************************************************************************************************/ +#if defined(__GNUC__) +long long R_BSP_MulAndAccOperation_W(long long init, unsigned long count, short *addr1, short *addr2) +{ + long long result = init; + unsigned long index; + for(index = 0; index < count; index++) + { + result += addr1[index] * addr2[index]; + } + return result; +} +#endif /* defined(__GNUC__) */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_MulAndAccOperation_L +* Description : Performs a multiply-and-accumulate operation with the initial value specified by init, the number of +* multiply-and-accumulate operations specified by count, and the start addresses of values to be +* multiplied specified by addr1 and addr2. +* Arguments : init - Initial value. +* count - Count of multiply-and-accumulate operations. +* *addr1 - Start address of values 1 to be multiplied. +* *addr2 - Start address of values 2 to be multiplied. +* Return Value : result - Lower 64 bits of the init + S(data1[n] * data2[n]) result. (n=0, 1, ..., const-1) +***********************************************************************************************************************/ +#if defined(__GNUC__) +long long R_BSP_MulAndAccOperation_L(long long init, unsigned long count, long *addr1, long *addr2) +{ + long long result = init; + unsigned long index; + for(index = 0; index < count; index++) + { + result += addr1[index] * addr2[index]; + } + return result; +} +#endif /* defined(__GNUC__) */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_RotateLeftWithCarry +* Description : Rotates data including the C flag to left by one bit. +* The bit pushed out of the operand is set to the C flag. +* Arguments : data - Data to be rotated to left. +* Return Value : data - Result of 1-bit left rotation of data including the C flag. +***********************************************************************************************************************/ +#if defined(__GNUC__) +unsigned long R_BSP_RotateLeftWithCarry(unsigned long data) +{ + __asm("rolc %0":"=r"(data) : "r"(data):); + return data; +} +#endif /* defined(__GNUC__) */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_RotateRightWithCarry +* Description : Rotates data including the C flag to right by one bit. +* The bit pushed out of the operand is set to the C flag. +* Arguments : data - Data to be rotated to right. +* Return Value : data - Result of 1-bit right rotation of data including the C flag. +***********************************************************************************************************************/ +#if defined(__GNUC__) +unsigned long R_BSP_RotateRightWithCarry(unsigned long data) +{ + __asm("rorc %0":"=r"(data) : "r"(data):); + return data; +} +#endif /* defined(__GNUC__) */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_RotateLeft +* Description : Rotates data to left by the specified number of bits. +* The bit pushed out of the operand is set to the C flag. +* Arguments : data - Data to be rotated to left. +* num - Number of bits to be rotated. +* Return Value : data - Result of num-bit left rotation of data. +***********************************************************************************************************************/ +#if defined(__GNUC__) +unsigned long R_BSP_RotateLeft(unsigned long data, unsigned long num) +{ + __asm("rotl %1, %0":"=r"(data) : "r"(num),"0"(data) :); + return data; +} +#endif /* defined(__GNUC__) */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_RotateRight +* Description : Rotates data to right by the specified number of bits. +* The bit pushed out of the operand is set to the C flag. +* Arguments : data - Data to be rotated to right. +* num - Number of bits to be rotated. +* Return Value : result - Result of num-bit right rotation of data. +***********************************************************************************************************************/ +#if defined(__GNUC__) +unsigned long R_BSP_RotateRight(unsigned long data, unsigned long num) +{ + __asm("rotr %1, %0":"=r"(data) : "r"(num),"0"(data) :); + return data; +} +#endif /* defined(__GNUC__) */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_SignedMultiplication +* Description : Performs signed multiplication of significant 64 bits. +* Arguments : data 1 - Input value 1. +* data 2 - Input value 2. +* Return Value : Result of signed multiplication. (signed 64-bit value) +***********************************************************************************************************************/ +#if defined(__GNUC__) || defined(__ICCRX__) +signed long long R_BSP_SignedMultiplication(signed long data1, signed long data2) +{ + return ((signed long long)data1) * ((signed long long)data2); +} +#endif /* defined(__GNUC__) || defined(__ICCRX__) */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_UnsignedMultiplication +* Description : Performs unsigned multiplication of significant 64 bits. +* Arguments : data 1 - Input value 1. +* data 2 - Input value 2. +* Return Value : Result of unsigned multiplication. (unsigned 64-bit value) +***********************************************************************************************************************/ +#if defined(__GNUC__) || defined(__ICCRX__) +unsigned long long R_BSP_UnsignedMultiplication(unsigned long data1, unsigned long data2) +{ + return ((unsigned long long)data1) * ((unsigned long long)data2); +} +#endif /* defined(__GNUC__) || defined(__ICCRX__) */ + +/*********************************************************************************************************************** +* Function name: R_BSP_ChangeToUserMode +* Description : Switches to user mode. The PSW will be changed as following. +* Before Execution After Execution +* PSW.PM PSW.U PSW.PM PSW.U +* 0 (supervisor mode) 0 (interrupt stack) --> 1 (user mode) 1 (user stack) +* 0 (supervisor mode) 1 (user stack) --> 1 (user mode) 1 (user stack) +* 1 (user mode) 1 (user stack) --> NO CHANGE +* 1 (user mode) 0 (interrupt stack)) <== N/A +* Arguments : none +* Return value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_INLINE_ASM(R_BSP_ChangeToUserMode) +void R_BSP_ChangeToUserMode(void) +{ + R_BSP_ASM_BEGIN + R_BSP_ASM(;_R_BSP_Change_PSW_PM_to_UserMode: ) + R_BSP_ASM( PUSH.L R1 ; push the R1 value ) + R_BSP_ASM( MVFC PSW, R1 ; get the current PSW value ) + R_BSP_ASM( BTST #20, R1 ; check PSW.PM ) + R_BSP_ASM( BNE.B R_BSP_ASM_LAB_NEXT(0);_psw_pm_is_user_mode ) + R_BSP_ASM(;_psw_pm_is_supervisor_mode: ) + R_BSP_ASM( BSET #20, R1 ; change PM = 0(Supervisor Mode) --> 1(User Mode) ) + R_BSP_ASM( PUSH.L R2 ; push the R2 value ) + R_BSP_ASM( MOV.L R0, R2 ; move the current SP value to the R2 value ) + R_BSP_ASM( XCHG 8[R2].L, R1 ; exchange the value of R2 destination address and the R1 value ) + R_BSP_ASM( ; (exchange the return address value of caller and the PSW value) ) + R_BSP_ASM( XCHG 4[R2].L, R1 ; exchange the value of R2 destination address and the R1 value ) + R_BSP_ASM( ; (exchange the R1 value of stack and the return address value of caller) ) + R_BSP_ASM( POP R2 ; pop the R2 value of stack ) + R_BSP_ASM( RTE ) + R_BSP_ASM_LAB(0:;_psw_pm_is_user_mode: ) + R_BSP_ASM( POP R1 ; pop the R1 value of stack ) + R_BSP_ASM( ;RTS ) + R_BSP_ASM_END +} /* End of function R_BSP_ChangeToUserMode() */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_SetACC +* Description : Sets a value to ACC. +* Arguments : data - Value to be set to ACC. +* Return Value : none +***********************************************************************************************************************/ +#if defined(__GNUC__) || defined(__ICCRX__) +void R_BSP_SetACC(signed long long data) +{ +#if defined(__GNUC__) + __builtin_rx_mvtachi(data >> 32); + __builtin_rx_mvtaclo(data & 0xFFFFFFFF); +#elif defined(__ICCRX__) + int32_t data_hi; + int32_t data_lo; + + data_hi = (int32_t)(data >> 32); + data_lo = (int32_t)(data & 0x00000000FFFFFFFF); + + R_BSP_MoveToAccHiLong(data_hi); + R_BSP_MoveToAccLoLong(data_lo); +#endif /* defined(__GNUC__) || defined(__ICCRX__) */ +} +#endif /* defined(__GNUC__) || defined(__ICCRX__) */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_GetACC +* Description : Refers to the ACC value. +* Arguments : none +* Return Value : result - ACC value. +***********************************************************************************************************************/ +#if defined(__GNUC__) || defined(__ICCRX__) +signed long long R_BSP_GetACC(void) +{ +#if defined(__GNUC__) + signed long long result = ((signed long long)__builtin_rx_mvfachi()) << 32; + result |= (((signed long long)__builtin_rx_mvfacmi()) << 16) & 0xFFFF0000; + return result; +#elif defined(__ICCRX__) + int64_t result; + + result = ((int64_t)R_BSP_MoveFromAccHiLong()) << 32; + result |= (((int64_t)R_BSP_MoveFromAccMiLong()) << 16) & 0xFFFF0000; + + return result; +#endif /* defined(__GNUC__) || defined(__ICCRX__) */ +} +#endif /* defined(__GNUC__) || defined(__ICCRX__) */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_MulAndAccOperation_2byte +* Description : Performs a multiply-and-accumulate operation between data of two bytes each and returns the result as +* four bytes. The multiply-and-accumulate operation is executed with DSP functional instructions (MULLO, +* MACLO, and MACHI). Data in the middle of the multiply-and-accumulate operation is retained in ACC as +* 48-bit data. After all multiply-and-accumulate operations have finished, the contents of ACC are +* fetched by the MVFACMI instruction and used as the return value of the intrinsic function. +* Arguments : data1 - Start address of values 1 to be multiplied. +* data2 - Start address of values 2 to be multiplied. +* count - Count of multiply-and-accumulate operations. +* Return Value : S(data1[n] * data2[n]) result. +***********************************************************************************************************************/ +#if defined(__GNUC__) +long R_BSP_MulAndAccOperation_2byte(short* data1, short* data2, unsigned long count) +{ + register signed long *ldata1 = (signed long *)data1; + register signed long *ldata2 = (signed long *)data2; + /* this is much more then an "intrinsic", no inline asm because of loop */ + /* will implement this.. interesting function as described in ccrx manual */ + __builtin_rx_mullo(0, 0); + while (count > 1) + { + __builtin_rx_maclo(*ldata1, *ldata2); + __builtin_rx_machi(*ldata1, *ldata2); + ldata1++; + ldata2++; + count -= 2; + } + if (count != 0) __builtin_rx_maclo(*(short*)ldata1, *(short*)ldata2); + return __builtin_rx_mvfacmi(); +} +#endif /* defined(__GNUC__) */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_MulAndAccOperation_FixedPoint1 +* Description : Performs a multiply-and-accumulate operation between data of two bytes each and returns the result as +* two bytes. The multiply-and-accumulate operation is executed with DSP functional instructions (MULLO, +* MACLO, and MACHI). Data in the middle of the multiply-and-accumulate operation is retained in ACC as +* 48-bit data. After all multiply-and-accumulate operations have finished, rounding is applied to the +* multiply-and-accumulate operation result of ACC. +* The macw1 function performs rounding with the "RACW #1" instruction. +* Arguments : data1 - Start address of values 1 to be multiplied. +* data2 - Start address of values 2 to be multiplied. +* count - Count of multiply-and-accumulate operations. +* Return Value : Value obtained by rounding the multiply-and-accumulate operation result with the RACW instruction. +***********************************************************************************************************************/ +#if defined(__GNUC__) +short R_BSP_MulAndAccOperation_FixedPoint1(short* data1, short* data2, unsigned long count) +{ + register signed long *ldata1 = (signed long *)data1; + register signed long *ldata2 = (signed long *)data2; + /* this is much more then an "intrinsic", no inline asm because of loop */ + /* will implement this.. interesting function as described in ccrx manual */ + __builtin_rx_mullo(0, 0); + while (count > 1) + { + __builtin_rx_maclo(*ldata1, *ldata2); + __builtin_rx_machi(*ldata1, *ldata2); + ldata1++; + ldata2++; + count -= 2; + } + if (count != 0) __builtin_rx_maclo(*(short*)ldata1, *(short*)ldata2); + __builtin_rx_racw(1); + return __builtin_rx_mvfachi(); +} +#endif /* defined(__GNUC__) */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_MulAndAccOperation_FixedPoint2 +* Description : Performs a multiply-and-accumulate operation between data of two bytes each and returns the result as +* two bytes. The multiply-and-accumulate operation is executed with DSP functional instructions (MULLO, +* MACLO, and MACHI). Data in the middle of the multiply-and-accumulate operation is retained in ACC as +* 48-bit data. After all multiply-and-accumulate operations have finished, rounding is applied to the +* multiply-and-accumulate operation result of ACC. +* the macw2 function performs rounding with the "RACW #2" instruction. +* Arguments : data1 - Start address of values 1 to be multiplied. +* data2 - Start address of values 2 to be multiplied. +* count - Count of multiply-and-accumulate operations. +* Return Value : Value obtained by rounding the multiply-and-accumulate operation result with the RACW instruction. +***********************************************************************************************************************/ +#if defined(__GNUC__) +short R_BSP_MulAndAccOperation_FixedPoint2(short* data1, short* data2, unsigned long count) +{ + register signed long *ldata1 = (signed long *)data1; + register signed long *ldata2 = (signed long *)data2; + /* this is much more then an "intrinsic", no inline asm because of loop */ + /* will implement this.. interesting function as described in ccrx manual */ + __builtin_rx_mullo(0, 0); + while (count > 1) + { + __builtin_rx_maclo(*ldata1, *ldata2); + __builtin_rx_machi(*ldata1, *ldata2); + ldata1++; + ldata2++; + count -= 2; + } + if (count != 0) __builtin_rx_maclo(*(short*)ldata1, *(short*)ldata2); + __builtin_rx_racw(2); + return __builtin_rx_mvfachi(); +} +#endif /* defined(__GNUC__) */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_SetBPSW +* Description : Sets a value to BPSW. +* Arguments : data - Value to be set. +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_INLINE_ASM(R_BSP_SetBPSW) +void R_BSP_SetBPSW(uint32_t data) +{ + R_BSP_ASM_INTERNAL_USED(data) + + R_BSP_ASM_BEGIN + R_BSP_ASM( MVTC R1, BPSW ) + R_BSP_ASM_END +} /* End of function R_BSP_SetBPSW() */ + +/*********************************************************************************************************************** +* Function Name: bsp_get_bpsw +* Description : Refers to the BPSW value. +* Arguments : ret - Return value address. +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_STATIC_INLINE_ASM(bsp_get_bpsw) +void bsp_get_bpsw(uint32_t *ret) +{ + R_BSP_ASM_INTERNAL_USED(ret) + + R_BSP_ASM_BEGIN + R_BSP_ASM( PUSH.L R2 ) + R_BSP_ASM( MVFC BPSW, R2 ) + R_BSP_ASM( MOV.L R2, [R1] ) + R_BSP_ASM( POP R2 ) + R_BSP_ASM_END +} /* End of function bsp_get_bpsw() */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_GetBPSW +* Description : Refers to the BPSW value. +* Arguments : none +* Return Value : BPSW value. +* Note : This function exists to avoid code analysis errors. Because, when inline assembler function has +* a return value, the error of "No return, in function returning non-void" occurs. +***********************************************************************************************************************/ +uint32_t R_BSP_GetBPSW(void) +{ + uint32_t ret; + + /* Casting is valid because it matches the type to the right side or argument. */ + bsp_get_bpsw((uint32_t *)&ret); + return ret; +} /* End of function R_BSP_GetBPSW() */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_SetBPC +* Description : Sets a value to BPC. +* Arguments : data - Value to be set. +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_INLINE_ASM(R_BSP_SetBPC) +void R_BSP_SetBPC(void *data) +{ + R_BSP_ASM_INTERNAL_USED(data) + + R_BSP_ASM_BEGIN + R_BSP_ASM( MVTC R1, BPC ) + R_BSP_ASM_END +} /* End of function R_BSP_SetBPC() */ + +/*********************************************************************************************************************** +* Function Name: bsp_get_bpc +* Description : Refers to the BPC value. +* Arguments : ret - Return value address. +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_STATIC_INLINE_ASM(bsp_get_bpc) +void bsp_get_bpc(uint32_t *ret) +{ + R_BSP_ASM_INTERNAL_USED(ret) + + R_BSP_ASM_BEGIN + R_BSP_ASM( PUSH.L R2 ) + R_BSP_ASM( MVFC BPC, R2 ) + R_BSP_ASM( MOV.L R2, [R1] ) + R_BSP_ASM( POP R2 ) + R_BSP_ASM_END +} /* End of function bsp_get_bpc() */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_GetBPC +* Description : Refers to the BPC value. +* Arguments : none +* Return Value : BPC value +* Note : This function exists to avoid code analysis errors. Because, when inline assembler function has +* a return value, the error of "No return, in function returning non-void" occurs. +***********************************************************************************************************************/ +void *R_BSP_GetBPC(void) +{ + uint32_t ret; + + /* Casting is valid because it matches the type to the right side or argument. */ + bsp_get_bpc((uint32_t *)&ret); + + /* Casting is valid because it matches the type to the right side or return. */ + return (void *)ret; +} /* End of function R_BSP_GetBPC() */ + +#ifdef BSP_MCU_EXCEPTION_TABLE +/*********************************************************************************************************************** +* Function Name: R_BSP_SetEXTB +* Description : Sets a value for EXTB. +* Arguments : data - Value to be set. +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_INLINE_ASM(R_BSP_SetEXTB) +void R_BSP_SetEXTB(void *data) +{ + R_BSP_ASM_INTERNAL_USED(data) + + R_BSP_ASM_BEGIN + R_BSP_ASM( MVTC R1, EXTB ) + R_BSP_ASM_END +} /* End of function R_BSP_SetEXTB() */ + +/*********************************************************************************************************************** +* Function Name: bsp_get_extb +* Description : Refers to the EXTB value. +* Arguments : ret - Return value address. +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_STATIC_INLINE_ASM(bsp_get_extb) +void bsp_get_extb(uint32_t *ret) +{ + R_BSP_ASM_INTERNAL_USED(ret) + + R_BSP_ASM_BEGIN + R_BSP_ASM( PUSH.L R2 ) + R_BSP_ASM( MVFC EXTB, R2 ) + R_BSP_ASM( MOV.L R2, [R1] ) + R_BSP_ASM( POP R2 ) + R_BSP_ASM_END +} /* End of function bsp_get_extb() */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_GetEXTB +* Description : Refers to the EXTB value. +* Arguments : none +* Return Value : EXTB value. +* Note : This function exists to avoid code analysis errors. Because, when inline assembler function has +* a return value, the error of "No return, in function returning non-void" occurs. +***********************************************************************************************************************/ +void *R_BSP_GetEXTB(void) +{ + uint32_t ret; + + /* Casting is valid because it matches the type to the right side or argument. */ + bsp_get_extb((uint32_t *)&ret); + + /* Casting is valid because it matches the type to the right side or return. */ + return (void *)ret; +} /* End of function R_BSP_GetEXTB() */ +#endif /* BSP_MCU_EXCEPTION_TABLE */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_MoveToAccHiLong +* Description : This function moves the contents of src to the higher-order 32 bits of the accumulator. +* Arguments : data - Input value. +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_INLINE_ASM(R_BSP_MoveToAccHiLong) +void R_BSP_MoveToAccHiLong(int32_t data) +{ + R_BSP_ASM_INTERNAL_USED(data) + + R_BSP_ASM_BEGIN + R_BSP_ASM( MVTACHI R1 ) + R_BSP_ASM_END +} /* End of function R_BSP_MoveToAccHiLong() */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_MoveToAccLoLong +* Description : This function moves the contents of src to the lower-order 32 bits of the accumulator. +* Arguments : data - Input value. +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_INLINE_ASM(R_BSP_MoveToAccLoLong) +void R_BSP_MoveToAccLoLong(int32_t data) +{ + R_BSP_ASM_INTERNAL_USED(data) + + R_BSP_ASM_BEGIN + R_BSP_ASM( MVTACLO R1 ) + R_BSP_ASM_END +} /* End of function R_BSP_MoveToAccLoLong() */ + +/*********************************************************************************************************************** +* Function Name: bsp_move_from_acc_hi_long +* Description : This function moves the higher-order 32 bits of the accumulator to dest. +* Arguments : ret - Return value address. +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_STATIC_INLINE_ASM(bsp_move_from_acc_hi_long) +void bsp_move_from_acc_hi_long(uint32_t *ret) +{ + R_BSP_ASM_INTERNAL_USED(ret) + + R_BSP_ASM_BEGIN + R_BSP_ASM( PUSH.L R2 ) + R_BSP_ASM( MVFACHI R2 ) + R_BSP_ASM( MOV.L R2, [R1] ) + R_BSP_ASM( POP R2 ) + R_BSP_ASM_END +} /* End of function bsp_move_from_acc_hi_long() */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_MoveFromAccHiLong +* Description : This function moves the higher-order 32 bits of the accumulator to dest. +* Arguments : none +* Return Value : The higher-order 32 bits of the accumulator. +* Note : This function exists to avoid code analysis errors. Because, when inline assembler function has +* a return value, the error of "No return, in function returning non-void" occurs. +***********************************************************************************************************************/ +int32_t R_BSP_MoveFromAccHiLong(void) +{ + int32_t ret; + + /* Casting is valid because it matches the type to the right side or argument. */ + bsp_move_from_acc_hi_long((uint32_t *)&ret); + return ret; +} /* End of function R_BSP_MoveFromAccHiLong() */ + +/*********************************************************************************************************************** +* Function Name: bsp_move_from_acc_mi_long +* Description : This function moves the contents of bits 47 to 16 of the accumulator to dest. +* Arguments : ret - Return value address. +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_STATIC_INLINE_ASM(bsp_move_from_acc_mi_long) +void bsp_move_from_acc_mi_long(uint32_t *ret) +{ + R_BSP_ASM_INTERNAL_USED(ret) + + R_BSP_ASM_BEGIN + R_BSP_ASM( PUSH.L R2 ) + R_BSP_ASM( MVFACMI R2 ) + R_BSP_ASM( MOV.L R2, [R1] ) + R_BSP_ASM( POP R2 ) + R_BSP_ASM_END +} /* End of function bsp_move_from_acc_mi_long() */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_MoveFromAccMiLong +* Description : This function moves the contents of bits 47 to 16 of the accumulator to dest. +* Arguments : none +* Return Value : The contents of bits 47 to 16 of the accumulator. +* Note : This function exists to avoid code analysis errors. Because, when inline assembler function has +* a return value, the error of "No return, in function returning non-void" occurs. +***********************************************************************************************************************/ +int32_t R_BSP_MoveFromAccMiLong(void) +{ + int32_t ret; + + /* Casting is valid because it matches the type to the right side or argument. */ + bsp_move_from_acc_mi_long((uint32_t *)&ret); + return ret; +} /* End of function R_BSP_MoveFromAccMiLong() */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_BitSet +* Description : Sets the specified one bit in the specified 1-byte area to 1. +* Arguments : data - Address of the target 1-byte area +* bit - Position of the bit to be manipulated +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_INLINE_ASM(R_BSP_BitSet) +void R_BSP_BitSet(uint8_t *data, uint32_t bit) +{ + R_BSP_ASM_INTERNAL_USED(data) + R_BSP_ASM_INTERNAL_USED(bit) + + R_BSP_ASM_BEGIN + R_BSP_ASM( BSET R2, [R1] ) + R_BSP_ASM_END +} /* End of function R_BSP_BitSet() */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_BitClear +* Description : Sets the specified one bit in the specified 1-byte area to 0. +* Arguments : data - Address of the target 1-byte area +* bit - Position of the bit to be manipulated +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_INLINE_ASM(R_BSP_BitClear) +void R_BSP_BitClear(uint8_t *data, uint32_t bit) +{ + R_BSP_ASM_INTERNAL_USED(data) + R_BSP_ASM_INTERNAL_USED(bit) + + R_BSP_ASM_BEGIN + R_BSP_ASM( BCLR R2, [R1] ) + R_BSP_ASM_END +} /* End of function R_BSP_BitClear() */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_BitReverse +* Description : Reverses the value of the specified one bit in the specified 1-byte area. +* Arguments : data - Address of the target 1-byte area +* bit - Position of the bit to be manipulated +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_INLINE_ASM(R_BSP_BitReverse) +void R_BSP_BitReverse(uint8_t *data, uint32_t bit) +{ + R_BSP_ASM_INTERNAL_USED(data) + R_BSP_ASM_INTERNAL_USED(bit) + + R_BSP_ASM_BEGIN + R_BSP_ASM( BNOT R2, [R1] ) + R_BSP_ASM_END +} /* End of function R_BSP_BitReverse() */ + +#ifdef BSP_MCU_DOUBLE_PRECISION_FLOATING_POINT +#ifdef __DPFPU +/*********************************************************************************************************************** +* Function Name: R_BSP_SetDPSW +* Description : Sets a value to DPSW. +* Arguments : data - Value to be set. +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_INLINE_ASM(R_BSP_SetDPSW) +void R_BSP_SetDPSW(uint32_t data) +{ + R_BSP_ASM_INTERNAL_USED(data) + + R_BSP_ASM_BEGIN + R_BSP_ASM( MVTDC R1, DPSW ) + R_BSP_ASM_END +} /* End of function R_BSP_SetDPSW() */ + +/*********************************************************************************************************************** +* Function Name: bsp_get_dpsw +* Description : Refers to the DPSW value. +* Arguments : ret - Return value address. +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_STATIC_INLINE_ASM(bsp_get_dpsw) +void bsp_get_dpsw(uint32_t *ret) +{ + R_BSP_ASM_INTERNAL_USED(ret) + + R_BSP_ASM_BEGIN + R_BSP_ASM( PUSH.L R2 ) + R_BSP_ASM( MVFDC DPSW, R2 ) + R_BSP_ASM( MOV.L R2, [R1] ) + R_BSP_ASM( POP R2 ) + R_BSP_ASM_END +} /* End of function bsp_get_dpsw() */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_GetDPSW +* Description : Refers to the DPSW value. +* Arguments : none +* Return Value : DPSW value. +* Note : This function exists to avoid code analysis errors. Because, when inline assembler function has +* a return value, the error of "No return, in function returning non-void" occurs. +***********************************************************************************************************************/ +uint32_t R_BSP_GetDPSW(void) +{ + uint32_t ret; + + /* Casting is valid because it matches the type to the right side or argument. */ + bsp_get_dpsw((uint32_t *)&ret); + return ret; +} /* End of function R_BSP_GetDPSW() */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_SetDECNT +* Description : Sets a value to DECNT. +* Arguments : data - Value to be set. +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_INLINE_ASM(R_BSP_SetDECNT) +void R_BSP_SetDECNT(uint32_t data) +{ + R_BSP_ASM_INTERNAL_USED(data) + + R_BSP_ASM_BEGIN + R_BSP_ASM( MVTDC R1, DECNT ) + R_BSP_ASM_END +} /* End of function R_BSP_SetDECNT() */ + +/*********************************************************************************************************************** +* Function Name: bsp_get_decnt +* Description : Refers to the DECNT value. +* Arguments : ret - Return value address. +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_STATIC_INLINE_ASM(bsp_get_decnt) +void bsp_get_decnt(uint32_t *ret) +{ + R_BSP_ASM_INTERNAL_USED(ret) + + R_BSP_ASM_BEGIN + R_BSP_ASM( PUSH.L R2 ) + R_BSP_ASM( MVFDC DECNT, R2 ) + R_BSP_ASM( MOV.L R2, [R1] ) + R_BSP_ASM( POP R2 ) + R_BSP_ASM_END +} /* End of function bsp_get_decnt() */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_GetDECNT +* Description : Refers to the DECNT value. +* Arguments : none +* Return Value : DECNT value. +* Note : This function exists to avoid code analysis errors. Because, when inline assembler function has +* a return value, the error of "No return, in function returning non-void" occurs. +***********************************************************************************************************************/ +uint32_t R_BSP_GetDECNT(void) +{ + uint32_t ret; + + /* Casting is valid because it matches the type to the right side or argument. */ + bsp_get_decnt((uint32_t *)&ret); + return ret; +} /* End of function R_BSP_GetDECNT() */ + +/*********************************************************************************************************************** +* Function Name: bsp_get_depc +* Description : Refers to the DEPC value. +* Arguments : ret - Return value address. +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_STATIC_INLINE_ASM(bsp_get_depc) +void bsp_get_depc(uint32_t *ret) +{ + R_BSP_ASM_INTERNAL_USED(ret) + + R_BSP_ASM_BEGIN + R_BSP_ASM( PUSH.L R2 ) + R_BSP_ASM( MVFDC DEPC, R2 ) + R_BSP_ASM( MOV.L R2, [R1] ) + R_BSP_ASM( POP R2 ) + R_BSP_ASM_END +} /* End of function bsp_get_decnt() */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_GetDEPC +* Description : Refers to the DEPC value. +* Arguments : none +* Return Value : DEPC value. +* Note : This function exists to avoid code analysis errors. Because, when inline assembler function has +* a return value, the error of "No return, in function returning non-void" occurs. +***********************************************************************************************************************/ +void *R_BSP_GetDEPC(void) +{ + uint32_t ret; + + /* Casting is valid because it matches the type to the right side or argument. */ + bsp_get_depc((uint32_t *)&ret); + return (void *)ret; +} /* End of function R_BSP_GetDECNT() */ +#endif /* __DPFPU */ +#endif /* BSP_MCU_DOUBLE_PRECISION_FLOATING_POINT */ + +#ifdef BSP_MCU_TRIGONOMETRIC +#ifdef __TFU +#if BSP_MCU_TFU_VERSION == 1 +/*********************************************************************************************************************** +* Function Name: R_BSP_InitTFU +* Description : Initialize arithmetic unit for trigonometric functions. +* Arguments : none +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_INLINE_ASM(R_BSP_InitTFU) +void R_BSP_InitTFU(void) +{ + R_BSP_ASM_BEGIN + R_BSP_ASM( PUSH.L R1 ) + R_BSP_ASM( MOV.L #81400H, R1 ) + R_BSP_ASM( MOV.B #7, [R1] ) + R_BSP_ASM( MOV.B #7, 1[R1] ) + R_BSP_ASM( POP R1 ) + R_BSP_ASM_END +} /* End of function R_BSP_InitTFU() */ +#endif +#ifdef __FPU +/*********************************************************************************************************************** +* Function Name: R_BSP_CalcSine_Cosine +* Description : Uses the trigonometric function unit to calculate the sine and cosine of an angle at the same time +* (single precision). +* Arguments : f - Value in radians from which to calculate the sine and cosine +* : sin - Address for storing the result of the sine operation +* : cos - Address for storing the result of the cosine operation +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_INLINE_ASM(R_BSP_CalcSine_Cosine) +void R_BSP_CalcSine_Cosine(float f, float *sin, float *cos) +{ + R_BSP_ASM_BEGIN + R_BSP_ASM( PUSH.L R4 ) + R_BSP_ASM( MOV.L #81410H, R4 ) + R_BSP_ASM( MOV.L R1, 4[R4] ) + R_BSP_ASM( MOV.L 4[R4], [R2] ) + R_BSP_ASM( MOV.L [R4], [R3] ) + R_BSP_ASM( POP R4 ) + R_BSP_ASM_END +} /* End of function R_BSP_CalcSine_Cosine() */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_CalcAtan_SquareRoot +* Description : Uses the trigonometric function unit to calculate the arc tangent of x and y and the square root of +* the sum of squares of these values at the same time (single precision). +* Arguments : y - Coordinate y (the numerator of the tangent) +* x - Coordinate x (the denominator of the tangent) +* atan2 - Address for storing the result of the arc tangent operation for y/x +* hypot - Address for storing the result of the square root of the sum of squares of x and y +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_INLINE_ASM(R_BSP_CalcAtan_SquareRoot) +void R_BSP_CalcAtan_SquareRoot(float y, float x, float *atan2, float *hypot) +{ + R_BSP_ASM_INTERNAL_USED(y) + R_BSP_ASM_INTERNAL_USED(x) + R_BSP_ASM_INTERNAL_USED(atan2) + R_BSP_ASM_INTERNAL_USED(hypot) + + R_BSP_ASM_BEGIN + R_BSP_ASM( PUSHM R5-R6 ) + R_BSP_ASM( MOV.L #81418H, R5 ) + R_BSP_ASM( MOV.L R2, [R5] ) + R_BSP_ASM( MOV.L R1, 4[R5] ) + R_BSP_ASM( MOV.L 4[R5], [R3] ) + R_BSP_ASM( MOV.L [R5], R6 ) + R_BSP_ASM( FMUL #3F1B74EEH, R6 ) + R_BSP_ASM( MOV.L R6, [R4] ) + R_BSP_ASM( POPM R5-R6 ) + R_BSP_ASM_END +} /* End of function R_BSP_CalcAtan_SquareRoot() */ +#endif /* __FPU */ + +#if BSP_MCU_TFU_VERSION == 2 + +/*********************************************************************************************************************** +* Function Name: R_BSP_CalcSine_Cosine_Fpn +* Description : Uses the trigonometric function unit to calculate the sine and cosine of an angle. +* (fixed-point numbers) +* Arguments : f - Value in radians from which to calculate the sine and cosine +* : sin - Address for storing the result of the sine operation +* : cos - Address for storing the result of the cosine operation +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_INLINE_ASM(R_BSP_CalcSine_Cosine_Fpn) +void R_BSP_CalcSine_Cosine_Fpn(int32_t f, int32_t *sin, int32_t *cos) +{ + R_BSP_ASM_INTERNAL_USED(f) + R_BSP_ASM_INTERNAL_USED(sin) + R_BSP_ASM_INTERNAL_USED(cos) + + R_BSP_ASM_BEGIN + R_BSP_ASM( PUSH.L R4 ) + R_BSP_ASM( PUSH.L R14 ) + R_BSP_ASM( MOV.L #81420H, R4 ) + R_BSP_ASM( MOV.L R1, 4[R4] ) + R_BSP_ASM( MOV.L 4[R4], R1 ) + R_BSP_ASM( MOV.L [R4], R14 ) + R_BSP_ASM( MOV.L R1, [R2] ) + R_BSP_ASM( MOV.L R14, [R3] ) + R_BSP_ASM( POP R4 ) + R_BSP_ASM( POP R14 ) + R_BSP_ASM_END +} /* End of function R_BSP_CalcSine_Cosine_Fpn() */ + +/*********************************************************************************************************************** +* Function Name: bsp_calc_sine_fsp +* Description : Uses the trigonometric function unit to calculate the sine of an angle. +* (fixed-point numbers) +* Arguments : ret - Return value address. +* fx - Value in radians from which to calculate the sine +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_STATIC_INLINE_ASM(bsp_calc_sine_fsp) +void bsp_calc_sine_fsp(int32_t *ret, int32_t fx) +{ + R_BSP_ASM_INTERNAL_USED(ret) + R_BSP_ASM_INTERNAL_USED(fx) + + R_BSP_ASM_BEGIN + R_BSP_ASM( PUSH.L R14 ) + R_BSP_ASM( MOV.L #81424H, R14 ) + R_BSP_ASM( MOV.L R2, [R14] ) + R_BSP_ASM( MOV.L [R14], [R1] ) + R_BSP_ASM( POP R14 ) + R_BSP_ASM_END +} /* End of function bsp_calc_sine_fsp() */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_CalcSine_Fpn +* Description : Uses the trigonometric function unit to calculate the sine of an angle. +* (fixed-point numbers) +* Arguments : fx - Value in radians from which to calculate the sine +* Return Value : Sine calculation result +***********************************************************************************************************************/ +int32_t R_BSP_CalcSine_Fpn(int32_t fx) +{ + int32_t ret; + + bsp_calc_sine_fsp((int32_t *)&ret, fx); + + return ret; +} /* End of function R_BSP_CalcSine_Fpn() */ + +/*********************************************************************************************************************** +* Function Name: bsp_calc_cosine_fsp +* Description : Uses the trigonometric function unit to calculate the cosine of an angle. +* (fixed-point numbers) +* Arguments : ret - Return value address. +* fx - Value in radians from which to calculate the cosine +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_STATIC_INLINE_ASM(bsp_calc_cosine_fsp) +void bsp_calc_cosine_fsp(int32_t *ret, int32_t fx) +{ + R_BSP_ASM_INTERNAL_USED(ret) + R_BSP_ASM_INTERNAL_USED(fx) + + R_BSP_ASM_BEGIN + R_BSP_ASM( PUSH.L R3 ) + R_BSP_ASM( MOV.L #81420H, R3 ) + R_BSP_ASM( MOV.L R2, 4[R3] ) + R_BSP_ASM( MOV.L [R3], [R1] ) + R_BSP_ASM( POP R3 ) + R_BSP_ASM_END +} /* End of function bsp_calc_cosine_fsp() */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_CalcCosine_Fpn +* Description : Uses the trigonometric function unit to calculate the cosine of an angle. +* (fixed-point numbers) +* Arguments : fx - Value in radians from which to calculate the cosine +* Return Value : Cosine calculation result +***********************************************************************************************************************/ +int32_t R_BSP_CalcCosine_Fpn(int32_t fx) +{ + int32_t ret; + + bsp_calc_cosine_fsp((int32_t *)&ret, fx); + + return ret; +} /* End of function R_BSP_CalcCosine_Fpn() */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_CalcAtan_SquareRoot_Fpn +* Description : Uses the trigonometric function unit to calculate the arc tangent of x and y and the square root of +* the sum of squares of these values. (fixed-point numbers) +* Arguments : y - Coordinate y (the numerator of the tangent) +* x - Coordinate x (the denominator of the tangent) +* atan2 - Address for storing the result of the arc tangent operation for y/x +* hypot - Address for storing the result of the square root of the sum of squares of x and y +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_INLINE_ASM(R_BSP_CalcAtan_SquareRoot_Fpn) +void R_BSP_CalcAtan_SquareRoot_Fpn(int32_t y, int32_t x, int32_t *atan2, int32_t *hypot) +{ + R_BSP_ASM_INTERNAL_USED(y) + R_BSP_ASM_INTERNAL_USED(x) + R_BSP_ASM_INTERNAL_USED(atan2) + R_BSP_ASM_INTERNAL_USED(hypot) + + R_BSP_ASM_BEGIN + R_BSP_ASM( PUSH.L R5 ) + R_BSP_ASM( PUSH.L R14 ) + R_BSP_ASM( PUSH.L R15 ) + R_BSP_ASM( MOV.L R4, R14 ) + R_BSP_ASM( MOV.L #81428H, R15 ) + R_BSP_ASM( MOV.L R2, [R15] ) + R_BSP_ASM( MOV.L #9B74EDA8H, R4 ) + R_BSP_ASM( MOV.L R1, 4[R15] ) + R_BSP_ASM( EMULU [R15].L, R4 ) + R_BSP_ASM( MOV.L 4[R15], [R3] ) + R_BSP_ASM( MOV.L R5, [R14] ) + R_BSP_ASM( POP R15 ) + R_BSP_ASM( POP R14 ) + R_BSP_ASM( POP R5 ) + R_BSP_ASM_END +} /* End of function R_BSP_CalcAtan_SquareRoot_Fpn() */ + +/*********************************************************************************************************************** +* Function Name: bsp_calc_atan_fsp +* Description : Uses the trigonometric function unit to calculate the arc tangent of x and y. (fixed-point numbers) +* Arguments : ret - Return value address. +* y - Coordinate y (the numerator of the tangent) +* x - Coordinate x (the denominator of the tangent) +* Return Value : none +***********************************************************************************************************************/ +R_BSP_PRAGMA_STATIC_INLINE_ASM(bsp_calc_atan_fsp) +void bsp_calc_atan_fsp(int32_t *ret, int32_t y, int32_t x) +{ + R_BSP_ASM_INTERNAL_USED(ret) + R_BSP_ASM_INTERNAL_USED(y) + R_BSP_ASM_INTERNAL_USED(x) + + R_BSP_ASM_BEGIN + R_BSP_ASM( PUSH.L R14 ) + R_BSP_ASM( MOV.L #81428H, R14 ) + R_BSP_ASM( MOV.L R3, [R14+] ) + R_BSP_ASM( MOV.L R2, [R14] ) + R_BSP_ASM( MOV.L [R14], [R1] ) + R_BSP_ASM( POP R14 ) + R_BSP_ASM_END +} /* End of function bsp_calc_atan_fsp() */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_CalcAtan_Fpn +* Description : Uses the trigonometric function unit to calculate the arc tangent of x and y. (fixed-point numbers) +* Arguments : y - Coordinate y (the numerator of the tangent) +* x - Coordinate x (the denominator of the tangent) +* Return Value : Arc tangent calculation result +***********************************************************************************************************************/ +int32_t R_BSP_CalcAtan_Fpn(int32_t y, int32_t x) +{ + int32_t ret; + + bsp_calc_atan_fsp((int32_t *)&ret, y, x); + + return ret; +} /* End of function R_BSP_CalcAtan_Fpn() */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_CalcSquareRoot_fpn +* Description : Uses the trigonometric function unit to calculate the square root of the +* sum of squares of x and y. (fixed-point numbers) +* Arguments : ret - Return value address. +* y - Coordinate y (the numerator of the tangent) +* x - Coordinate x (the denominator of the tangent) +* Return Value : Result of calculation of the square root of the sum of squares of x and y. +***********************************************************************************************************************/ +R_BSP_PRAGMA_STATIC_INLINE_ASM(bsp_calc_squareroot_fsp) +void bsp_calc_squareroot_fsp(int32_t *ret, int32_t y, int32_t x) +{ + R_BSP_ASM_INTERNAL_USED(ret) + R_BSP_ASM_INTERNAL_USED(y) + R_BSP_ASM_INTERNAL_USED(x) + + R_BSP_ASM_BEGIN + R_BSP_ASM( PUSHM R4-R5 ) + R_BSP_ASM( MOV.L #81428H, R5 ) + R_BSP_ASM( MOV.L R2, [R5] ) + R_BSP_ASM( MOV.L #9B74EDA8H, R4 ) + R_BSP_ASM( MOV.L R3, 4[R5] ) + R_BSP_ASM( EMULU [R5].L, R4 ) + R_BSP_ASM( MOV.L R5, [R1] ) + R_BSP_ASM( POPM R4-R5 ) + R_BSP_ASM_END +} /* End of function bsp_calc_squareroot_fsp() */ + +/*********************************************************************************************************************** +* Function Name: R_BSP_CalcSquareRoot_fpn +* Description : Uses the trigonometric function unit to calculate the square root of the +* sum of squares of x and y. (fixed-point numbers) +* Arguments : y - Coordinate y (the numerator of the tangent) +* x - Coordinate x (the denominator of the tangent) +* Return Value : Result of calculation of the square root of the sum of squares of x and y. +***********************************************************************************************************************/ +int32_t R_BSP_CalcSquareRoot_Fpn(int32_t y, int32_t x) +{ + int32_t ret; + + bsp_calc_squareroot_fsp((int32_t *)&ret, y, x); + + return ret; +} /* End of function R_BSP_CalcSquareRoot_Fpn() */ +#endif /* BSP_MCU_TFU_VERSION == 2 */ +#endif /* __TFU */ +#endif /* BSP_MCU_TRIGONOMETRIC */ + diff --git a/drivers/rx/rdp/src/r_bsp/mcu/all/r_rx_intrinsic_functions.h b/drivers/rx/rdp/src/r_bsp/mcu/all/r_rx_intrinsic_functions.h new file mode 100644 index 00000000..d866dffa --- /dev/null +++ b/drivers/rx/rdp/src/r_bsp/mcu/all/r_rx_intrinsic_functions.h @@ -0,0 +1,991 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 - 2024 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_rx_intrinsic_functions.h +* Description : This is a file for integrating the definitions of built-in functions that differ for each compilers. +* Replace different functions for each compiler. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 28.02.2019 1.00 First Release +* : 26.07.2019 1.10 Added the following function. +* - R_BSP_SINCOSF +* - R_BSP_ATAN2HYPOTF +* - R_BSP_CalcSine_Cosine +* - R_BSP_CalcAtan_SquareRoot +* : 31.07.2019 1.11 Modified the compile condition of the below functions. +* - R_BSP_InitTFU +* - R_BSP_CalcSine_Cosine +* - R_BSP_CalcAtan_SquareRoot +* : 08.10.2019 1.12 Modified the followind definition of intrinsic function of TFU for ICCRX. +* - R_BSP_INIT_TFU +* - R_BSP_SINCOSF +* - R_BSP_ATAN2HYPOTF +* : 17.12.2019 1.13 Modified the comment of description. +* : 28.02.2023 1.14 Modified the comment. +* Added the following function. +* - R_BSP_SINCOSFX +* - R_BSP_SINFX +* - R_BSP_COSFX +* - R_BSP_ATAN2HYPOTFX +* - R_BSP_ATAN2FX +* - R_BSP_HYPOTFX +* - R_BSP_CalcSine_Cosine_Fpn +* - R_BSP_CalcSine_Fpn +* - R_BSP_CalcCosine_Fpn +* - R_BSP_CalcAtan_SquareRoot_Fpn +* - R_BSP_CalcAtan_Fpn +* - R_BSP_CalcSquareRoot_Fpn +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "platform.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef R_RX_INTRINSIC_FUNCTIONS_H +#define R_RX_INTRINSIC_FUNCTIONS_H + +/* ---------- Maximum value and minimum value ---------- */ +#if defined(__CCRX__) + +/* signed long max(signed long data1, signed long data2) */ +#define R_BSP_MAX(x, y) max((signed long)(x), (signed long)(y)) +/* signed long min(signed long data1, signed long data2) */ +#define R_BSP_MIN(x, y) min((signed long)(x), (signed long)(y)) + +#elif defined(__GNUC__) + +/* signed long R_BSP_Max(signed long data1, signed long data2) (This macro uses API function of BSP.) */ +#define R_BSP_MAX(x, y) R_BSP_Max((signed long)(x), (signed long)(y)) +/* signed long R_BSP_Min(signed long data1, signed long data2) (This macro uses API function of BSP.) */ +#define R_BSP_MIN(x, y) R_BSP_Min((signed long)(x), (signed long)(y)) + +#elif defined(__ICCRX__) + +/* signed long __MAX(signed long, signed long) */ +#define R_BSP_MAX(x, y) __MAX((signed long)(x), (signed long)(y)) +/* signed long __MIN(signed long, signed long) */ +#define R_BSP_MIN(x, y) __MIN((signed long)(x), (signed long)(y)) + +#endif + +/* ---------- Byte switch ---------- */ +#if defined(__CCRX__) + +/* unsigned long revl(unsigned long data) */ +#define R_BSP_REVL(x) revl((unsigned long)(x)) +/* unsigned long revw(unsigned long data) */ +#define R_BSP_REVW(x) revw((unsigned long)(x)) + +#elif defined(__GNUC__) + +/* uint32_t __builtin_bswap32(uint32_t x) */ +#define R_BSP_REVL(x) __builtin_bswap32((uint32_t)(x)) +/* int __builtin_rx_revw(int) */ +#define R_BSP_REVW(x) (unsigned long)__builtin_rx_revw((int)(x)) + +#elif defined(__ICCRX__) + +/* unsigned long __REVL(unsigned long) */ +#define R_BSP_REVL(x) __REVL((unsigned long)(x)) +/* unsigned long __REVW(unsigned long) */ +#define R_BSP_REVW(x) __REVW((unsigned long)(x)) + +#endif + +/* ---------- Data Exchange ---------- */ +#if defined(__CCRX__) + +/* void xchg(signed long *data1, signed long *data2) */ +#define R_BSP_EXCHANGE(x, y) xchg((signed long *)(x), (signed long *)(y)) + +#elif defined(__GNUC__) + +/* void __builtin_rx_xchg (int *, int *) */ +#define R_BSP_EXCHANGE(x, y) __builtin_rx_xchg((int *)(x), (int *)(y)) + +#elif defined(__ICCRX__) + +/* void _builtin_xchg(signed long *, signed long *) */ +#define R_BSP_EXCHANGE(x, y) _builtin_xchg((signed long *)(x), (signed long *)(y)) + +#endif + +/* ---------- Multiply-and-accumulate operation ---------- */ +#if defined(__CCRX__) + +/* long long rmpab(long long init, unsigned long count, signed char *addr1, signed char *addr2) */ +#define R_BSP_RMPAB(w, x, y, z) rmpab((long long)(w), (unsigned long)(x), (signed char *)(y), (signed char *)(z)) +/* long long rmpaw(long long init, unsigned long count, short *addr1, short *addr2) */ +#define R_BSP_RMPAW(w, x, y, z) rmpaw((long long)(w), (unsigned long)(x), (short *)(y), (short *)(z)) +/* long long rmpal(long long init, unsigned long count, long *addr1, long *addr2) */ +#define R_BSP_RMPAL(w, x, y, z) rmpal((long long)(w), (unsigned long)(x), (long *)(y), (long *)(z)) + +#elif defined(__GNUC__) + +/* long long R_BSP_MulAndAccOperation_B(long long init, unsigned long count, signed char *addr1, signed char *addr2) + (This macro uses API function of BSP.) */ +#define R_BSP_RMPAB(w, x, y, z) R_BSP_MulAndAccOperation_B((long long)(w), (unsigned long)(x), (signed char *)(y), (signed char *)(z)) +/* long long R_BSP_MulAndAccOperation_W(long long init, unsigned long count, short *addr1, short *addr2) + (This macro uses API function of BSP.) */ +#define R_BSP_RMPAW(w, x, y, z) R_BSP_MulAndAccOperation_W((long long)(w), (unsigned long)(x), (short *)(y), (short *)(z)) +/* long long R_BSP_MulAndAccOperation_L(long long init, unsigned long count, long *addr1, long *addr2) + (This macro uses API function of BSP.) */ +#define R_BSP_RMPAL(w, x, y, z) R_BSP_MulAndAccOperation_L((long long)(w), (unsigned long)(x), (long *)(y), (long *)(z)) + +#elif defined(__ICCRX__) + +/* long long rmpab(long long init, unsigned long count, signed char *addr1, signed char *addr2) */ +#define R_BSP_RMPAB(w, x, y, z) rmpab((long long)(w), (unsigned long)(x), (signed char *)(y), (signed char *)(z)) +/* long long rmpaw(long long init, unsigned long count, short *addr1, short *addr2) */ +#define R_BSP_RMPAW(w, x, y, z) rmpaw((long long)(w), (unsigned long)(x), (short *)(y), (short *)(z)) +/* long long rmpal(long long init, unsigned long count, long *addr1, long *addr2) */ +#define R_BSP_RMPAL(w, x, y, z) rmpal((long long)(w), (unsigned long)(x), (long *)(y), (long *)(z)) + +#endif + +/* ---------- Rotation ---------- */ +#if defined(__CCRX__) + +/* unsigned long rolc(unsigned long data) */ +#define R_BSP_ROLC(x) rolc((unsigned long)(x)) +/* unsigned long rorc(unsigned long data) */ +#define R_BSP_RORC(x) rorc((unsigned long)(x)) +/* unsigned long rotl(unsigned long data, unsigned long num) */ +#define R_BSP_ROTL(x, y) rotl((unsigned long)(x), (unsigned long)(y)) +/* unsigned long rotr (unsigned long data, unsigned long num) */ +#define R_BSP_ROTR(x, y) rotr((unsigned long)(x), (unsigned long)(y)) + +#elif defined(__GNUC__) + +/* unsigned long R_BSP_RotateLeftWithCarry(unsigned long data) (This macro uses API function of BSP.) */ +#define R_BSP_ROLC(x) R_BSP_RotateLeftWithCarry((unsigned long)(x)) +/* unsigned long R_BSP_RotateRightWithCarry(unsigned long data) (This macro uses API function of BSP.) */ +#define R_BSP_RORC(x) R_BSP_RotateRightWithCarry((unsigned long)(x)) +/* unsigned long R_BSP_RotateLeft(unsigned long data, unsigned long num) (This macro uses API function of BSP.) */ +#define R_BSP_ROTL(x, y) R_BSP_RotateLeft((unsigned long)(x), (unsigned long)(y)) +/* unsigned long R_BSP_RotateRight (unsigned long data, unsigned long num) (This macro uses API function of BSP.) */ +#define R_BSP_ROTR(x, y) R_BSP_RotateRight((unsigned long)(x), (unsigned long)(y)) + +#elif defined(__ICCRX__) + +/* unsigned long __ROLC(unsigned long) */ +#define R_BSP_ROLC(x) __ROLC((unsigned long)(x)) +/* unsigned long __RORC(unsigned long) */ +#define R_BSP_RORC(x) __RORC((unsigned long)(x)) +/* unsigned long __ROTL(unsigned long, unsigned long) */ +#define R_BSP_ROTL(x, y) __ROTL((unsigned long)(y), (unsigned long)(x)) +/* unsigned long __ROTR(unsigned long, unsigned long) */ +#define R_BSP_ROTR(x, y) __ROTR((unsigned long)(y), (unsigned long)(x)) + +#endif + +/* ---------- Special Instructions ---------- */ +#if defined(__CCRX__) + +/* void brk(void) */ +#define R_BSP_BRK() brk() +/* void int_exception(signed long num) */ +#define R_BSP_INT(x) int_exception((signed long)(x)) +/* void wait(void) */ +#define R_BSP_WAIT() wait() +/* void nop(void) */ +#define R_BSP_NOP() nop() + +#elif defined(__GNUC__) + +/* void __builtin_rx_brk (void) */ +#define R_BSP_BRK() __builtin_rx_brk() +/* void __builtin_rx_int (int) */ +#define R_BSP_INT(x) __builtin_rx_int((int)(x)) +/* void __builtin_rx_wait (void) */ +#define R_BSP_WAIT() __builtin_rx_wait() +/* __asm("nop") */ +#define R_BSP_NOP() __asm("nop") + +#elif defined(__ICCRX__) + +/* void __break(void) */ +#define R_BSP_BRK() __break() +/* void __software_interrupt(unsigned char) */ +#define R_BSP_INT(x) __software_interrupt((unsigned char)(x)) +/* void __wait_for_interrupt(void) */ +#define R_BSP_WAIT() __wait_for_interrupt() +/* void __no_operation(void) */ +#define R_BSP_NOP() __no_operation() + +#endif + +/* ---------- Processor interrupt priority level (IPL) ---------- */ +#if defined(__CCRX__) + +/* void set_ipl(signed long level) */ +#define R_BSP_SET_IPL(x) set_ipl((signed long)(x)) +/* unsigned char get_ipl(void) */ +#define R_BSP_GET_IPL() get_ipl() + +#elif defined(__GNUC__) + +/* void __builtin_rx_mvtipl (int) */ +#define R_BSP_SET_IPL(x) __builtin_rx_mvtipl((int)(x)) +/* uint32_t R_BSP_CpuInterruptLevelRead (void) (This macro uses API function of BSP.) */ +#define R_BSP_GET_IPL() (unsigned char)R_BSP_CpuInterruptLevelRead() + +#elif defined(__ICCRX__) + +/* void __set_interrupt_level(__ilevel_t) */ +#define R_BSP_SET_IPL(x) __set_interrupt_level((__ilevel_t)(x)) +/* __ilevel_t __get_interrupt_level(void) */ +#define R_BSP_GET_IPL() (unsigned char)__get_interrupt_level() + +#endif + +/* ---------- Processor status word (PSW) ---------- */ +#if defined(__CCRX__) + +/* void set_psw(unsigned long data) */ +#define R_BSP_SET_PSW(x) set_psw((unsigned long)(x)) +/* unsigned long get_psw(void) */ +#define R_BSP_GET_PSW() get_psw() + +#elif defined(__GNUC__) + +/* void __builtin_rx_mvtc (int reg, int val) */ +#define R_BSP_SET_PSW(x) __builtin_rx_mvtc(0x0, (int)(x)) +/* int __builtin_rx_mvfc (int) */ +#define R_BSP_GET_PSW() (unsigned long)__builtin_rx_mvfc(0x0) + +#elif defined(__ICCRX__) + +/* void __set_PSW_register(unsigned long) */ +#define R_BSP_SET_PSW(x) __set_PSW_register((unsigned long)(x)) +/* unsigned long __get_PSW_register(void) */ +#define R_BSP_GET_PSW() __get_PSW_register() + +#endif + +/* ---------- Floating-point status word (FPSW) ---------- */ +#ifdef __FPU +#if defined(__CCRX__) + +/* void set_fpsw(unsigned long data) */ +#define R_BSP_SET_FPSW(x) set_fpsw((unsigned long)(x)) +/* unsigned long get_fpsw(void) */ +#define R_BSP_GET_FPSW() get_fpsw() + +#elif defined(__GNUC__) + +/* void __builtin_rx_mvtc (int reg, int val) */ +#define R_BSP_SET_FPSW(x) __builtin_rx_mvtc(0x3, (int)(x)) +/* int __builtin_rx_mvfc (int) */ +#define R_BSP_GET_FPSW() (unsigned long)__builtin_rx_mvfc(0x3) + +#elif defined(__ICCRX__) + +/* void __set_FPSW_register(unsigned long) */ +#define R_BSP_SET_FPSW(x) __set_FPSW_register((unsigned long)(x)) +/* unsigned long __get_FPSW_register(void) */ +#define R_BSP_GET_FPSW() __get_FPSW_register() + +#endif +#endif + +/* ---------- User Stack Pointer (USP) ---------- */ +#if defined(__CCRX__) + +/* void set_usp(void *data) */ +#define R_BSP_SET_USP(x) set_usp((void *)(x)) +/* void *get_usp(void) */ +#define R_BSP_GET_USP() get_usp() + +#elif defined(__GNUC__) + +/* void __builtin_rx_mvtc (int reg, int val) */ +#define R_BSP_SET_USP(x) __builtin_rx_mvtc(0x2, (int)(x)) +/* int __builtin_rx_mvfc (int) */ +#define R_BSP_GET_USP() (void *)__builtin_rx_mvfc(0x2) + +#elif defined(__ICCRX__) + +/* void __set_USP_register(unsigned long) */ +#define R_BSP_SET_USP(x) __set_USP_register((unsigned long)(x)) +/* unsigned long __get_USP_register(void) */ +#define R_BSP_GET_USP() (void *)__get_USP_register() + +#endif + +/* ---------- Interrupt Stack Pointer (ISP) ---------- */ +#if defined(__CCRX__) + +/* void set_isp(void *data) */ +#define R_BSP_SET_ISP(x) set_isp((void *)(x)) +/* void *get_isp(void) */ +#define R_BSP_GET_ISP() get_isp() + +#elif defined(__GNUC__) + +/* void __builtin_rx_mvtc (int reg, int val) */ +#define R_BSP_SET_ISP(x) __builtin_rx_mvtc(0xA, (int)(x)) +/* int __builtin_rx_mvfc (int) */ +#define R_BSP_GET_ISP() (void *)__builtin_rx_mvfc(0xA) + +#elif defined(__ICCRX__) + +/* void __set_ISP_register(unsigned long) */ +#define R_BSP_SET_ISP(x) __set_ISP_register((unsigned long)(x)) +/* unsigned long __get_ISP_register(void) */ +#define R_BSP_GET_ISP() (void *)__get_ISP_register() + +#endif + +/* ---------- Interrupt Table Register (INTB) ---------- */ +#if defined(__CCRX__) + +/* void set_intb(void *data) */ +#define R_BSP_SET_INTB(x) set_intb((void *)(x)) +/* void *get_intb(void) */ +#define R_BSP_GET_INTB() get_intb() + +#elif defined(__GNUC__) + +/* void __builtin_rx_mvtc (int reg, int val) */ +#define R_BSP_SET_INTB(x) __builtin_rx_mvtc(0xC, (int)(x)) +/* int __builtin_rx_mvfc (int) */ +#define R_BSP_GET_INTB() (void *)__builtin_rx_mvfc(0xC) + +#elif defined(__ICCRX__) + +/* void __set_interrupt_table(unsigned long address) */ +#define R_BSP_SET_INTB(x) __set_interrupt_table((unsigned long)(x)) +/* unsigned long __get_interrupt_table(void); */ +#define R_BSP_GET_INTB() (void *)__get_interrupt_table() + +#endif + +/* ---------- Backup PSW (BPSW) ---------- */ +#if defined(__CCRX__) + +/* void set_bpsw(unsigned long data) */ +#define R_BSP_SET_BPSW(x) set_bpsw((unsigned long)(x)) +/* unsigned long get_bpsw(void) */ +#define R_BSP_GET_BPSW() get_bpsw() + +#elif defined(__GNUC__) + +/* void __builtin_rx_mvtc (int reg, int val) */ +#define R_BSP_SET_BPSW(x) __builtin_rx_mvtc(0x8, (int)(x)) +/* int __builtin_rx_mvfc (int) */ +#define R_BSP_GET_BPSW() (unsigned long)__builtin_rx_mvfc(0x8) + +#elif defined(__ICCRX__) + +/* void R_BSP_SetBPSW(uint32_t data) (This macro uses API function of BSP.) */ +#define R_BSP_SET_BPSW(x) R_BSP_SetBPSW((uint32_t)(x)) +/* uint32_t R_BSP_GetBPSW(void) (This macro uses API function of BSP.) */ +#define R_BSP_GET_BPSW() R_BSP_GetBPSW() + +#endif + +/* ---------- Backup PC (BPC) ---------- */ +#if defined(__CCRX__) + +/* void set_bpc(void *data) */ +#define R_BSP_SET_BPC(x) set_bpc((void *)(x)) +/* void *get_bpc(void) */ +#define R_BSP_GET_BPC() get_bpc() + +#elif defined(__GNUC__) + +/* void __builtin_rx_mvtc (int reg, int val) */ +#define R_BSP_SET_BPC(x) __builtin_rx_mvtc(0x9, (int)(x)) +/* int __builtin_rx_mvfc (int) */ +#define R_BSP_GET_BPC() (void *)__builtin_rx_mvfc(0x9) + +#elif defined(__ICCRX__) + +/* void R_BSP_SetBPC(void * data) (This macro uses API function of BSP.) */ +#define R_BSP_SET_BPC(x) R_BSP_SetBPC((void *)(x)) +/* void *R_BSP_GetBPC(void) (This macro uses API function of BSP.) */ +#define R_BSP_GET_BPC() R_BSP_GetBPC() + +#endif + +/* ---------- Fast Interrupt Vector Register (FINTV) ---------- */ +#if defined(__CCRX__) + +/* void set_fintv(void *data) */ +#define R_BSP_SET_FINTV(x) set_fintv((void *)(x)) +/* void *get_fintv(void) */ +#define R_BSP_GET_FINTV() get_fintv() + +#elif defined(__GNUC__) + +/* void __builtin_rx_mvtc (int reg, int val) */ +#define R_BSP_SET_FINTV(x) __builtin_rx_mvtc(0xB, (int)(x)) +/* int __builtin_rx_mvfc (int) */ +#define R_BSP_GET_FINTV() (void *)__builtin_rx_mvfc(0xB) + +#elif defined(__ICCRX__) + +/* void __set_FINTV_register(__fast_int_f) */ +#define R_BSP_SET_FINTV(x) __set_FINTV_register((__fast_int_f)(x)) +/* __fast_int_f __get_FINTV_register(void) */ +#define R_BSP_GET_FINTV() (void *)__get_FINTV_register() + +#endif + +/* ---------- Significant 64-bit multiplication ---------- */ +#if defined(__CCRX__) + +/* signed long long emul(signed long data1, signed long data2) */ +#define R_BSP_EMUL(x, y) emul((signed long)(x), (signed long)(y)) +/* unsigned long long emulu(unsigned long data1, unsigned long data2) */ +#define R_BSP_EMULU(x, y) emulu((unsigned long)(x), (unsigned long)(y)) + +#elif defined(__GNUC__) + +/* signed long long R_BSP_SignedMultiplication(signed long data1, signed long data2) + (This macro uses API function of BSP.) */ +#define R_BSP_EMUL(x, y) R_BSP_SignedMultiplication((signed long)(x), (signed long)(y)) +/* unsigned long long R_BSP_UnsignedMultiplication(unsigned long data1, unsigned long data2) + (This macro uses API function of BSP.) */ +#define R_BSP_EMULU(x, y) R_BSP_UnsignedMultiplication((unsigned long)(x), (unsigned long)(y)) + +#elif defined(__ICCRX__) + +/* signed long long R_BSP_SignedMultiplication(signed long data1, signed long data2) + (This macro uses API function of BSP.) */ +#define R_BSP_EMUL(x, y) R_BSP_SignedMultiplication((signed long)(x), (signed long)(y)) +/* unsigned long long R_BSP_UnsignedMultiplication(unsigned long data1, unsigned long data2) + (This macro uses API function of BSP.) */ +#define R_BSP_EMULU(x, y) R_BSP_UnsignedMultiplication((unsigned long)(x), (unsigned long)(y)) + +#endif + +/* ---------- Processor mode (PM) ---------- */ +#if defined(__CCRX__) + +/* void chg_pmusr(void) */ +#define R_BSP_CHG_PMUSR() chg_pmusr() + +#elif defined(__GNUC__) + +/* void R_BSP_ChangeToUserMode(void) (This macro uses API function of BSP.) */ +#define R_BSP_CHG_PMUSR() R_BSP_ChangeToUserMode() + +#elif defined(__ICCRX__) + +/* void R_BSP_ChangeToUserMode(void) (This macro uses API function of BSP.) */ +#define R_BSP_CHG_PMUSR() R_BSP_ChangeToUserMode() + +#endif + +/* ---------- Accumulator (ACC) ---------- */ +#if defined(__CCRX__) + +/* void set_acc(signed long long data) */ +#define R_BSP_SET_ACC(x) set_acc((signed long long)(x)) +/* signed long long get_acc(void) */ +#define R_BSP_GET_ACC() get_acc() + +#elif defined(__GNUC__) + +/* void R_BSP_SetACC(signed long long data) (This macro uses API function of BSP.) */ +#define R_BSP_SET_ACC(x) R_BSP_SetACC((signed long long)(x)) +/* signed long long R_BSP_GetACC(void) (This macro uses API function of BSP.) */ +#define R_BSP_GET_ACC() R_BSP_GetACC() + +#elif defined(__ICCRX__) + +/* void R_BSP_SetACC(signed long long data) (This macro uses API function of BSP.) */ +#define R_BSP_SET_ACC(x) R_BSP_SetACC((signed long long)(x)) +/* signed long long R_BSP_GetACC(void) (This macro uses API function of BSP.) */ +#define R_BSP_GET_ACC() R_BSP_GetACC() + +#endif + +/* ---------- Control of the interrupt enable bits ---------- */ +#if defined(__CCRX__) + +/* void setpsw_i(void) */ +#define R_BSP_SETPSW_I() setpsw_i() +/* void clrpsw_i(void) */ +#define R_BSP_CLRPSW_I() clrpsw_i() + +#elif defined(__GNUC__) + +/* void __builtin_rx_setpsw (int) */ +#define R_BSP_SETPSW_I() __builtin_rx_setpsw('I') +/* void __builtin_rx_clrpsw (int) */ +#define R_BSP_CLRPSW_I() __builtin_rx_clrpsw('I') + +#elif defined(__ICCRX__) + +/* void __enable_interrupt(void) */ +#define R_BSP_SETPSW_I() __enable_interrupt() +/* void __disable_interrupt(void) */ +#define R_BSP_CLRPSW_I() __disable_interrupt() + +#endif + +/* ---------- Multiply-and-accumulate operation ---------- */ +#if defined(__CCRX__) + +/* long macl(short *data1, short *data2, unsigned long count) */ +#define R_BSP_MACL(x, y, z) macl((short *)(x), (short *)(y), (unsigned long)(z)) +/* short macw1(short *data1, short *data2, unsigned long count) */ +#define R_BSP_MACW1(x, y, z) macw1((short *)(x), (short *)(y), (unsigned long)(z)) +/* short macw2(short *data1, short *data2, unsigned long count) */ +#define R_BSP_MACW2(x, y, z) macw2((short *)(x), (short *)(y), (unsigned long)(z)) + +#elif defined(__GNUC__) + +/* long R_BSP_MulAndAccOperation_2byte(short *data1, short *data2, unsigned long count) + (This macro uses API function of BSP.) */ +#define R_BSP_MACL(x, y, z) R_BSP_MulAndAccOperation_2byte((short *)(x), (short *)(y), (unsigned long)(z)) +/* short R_BSP_MulAndAccOperation_FixedPoint1(short *data1, short *data2, unsigned long count) + (This macro uses API function of BSP.) */ +#define R_BSP_MACW1(x, y, z) R_BSP_MulAndAccOperation_FixedPoint1((short *)(x), (short *)(y), (unsigned long)(z)) +/* short R_BSP_MulAndAccOperation_FixedPoint2(short *data1, short *data2, unsigned long count) + (This macro uses API function of BSP.) */ +#define R_BSP_MACW2(x, y, z) R_BSP_MulAndAccOperation_FixedPoint2((short *)(x), (short *)(y), (unsigned long)(z)) + +#elif defined(__ICCRX__) + +/* long __macl(short * data1, short * data2, unsigned long count) */ +#define R_BSP_MACL(x, y, z) __macl((short *)(x), (short *)(y), (unsigned long)(z)) +/* short __macw1(short * data1, short * data2, unsigned long count) */ +#define R_BSP_MACW1(x, y, z) __macw1((short *)(x), (short *)(y), (unsigned long)(z)) +/* short __macw2(short * data1, short * data2, unsigned long count) */ +#define R_BSP_MACW2(x, y, z) __macw2((short *)(x), (short *)(y), (unsigned long)(z)) + +#endif + +/* ---------- Exception Table Register (EXTB) ---------- */ +#ifdef BSP_MCU_EXCEPTION_TABLE +#if defined(__CCRX__) + +/* void set_extb(void *data) */ +#define R_BSP_SET_EXTB(x) set_extb((void *)(x)) +/* void *get_extb(void) */ +#define R_BSP_GET_EXTB() get_extb() + +#elif defined(__GNUC__) + +/* void __builtin_rx_mvtc (int reg, int val) */ +#define R_BSP_SET_EXTB(x) __builtin_rx_mvtc(0xD, (int)(x)) +/* int __builtin_rx_mvfc (int) */ +#define R_BSP_GET_EXTB() (void *)__builtin_rx_mvfc(0xD) + +#elif defined(__ICCRX__) + +/* void R_BSP_SetEXTB(void * data) (This macro uses API function of BSP.) */ +#define R_BSP_SET_EXTB(x) R_BSP_SetEXTB((void *)(x)) +/* void *R_BSP_GetEXTB(void) (This macro uses API function of BSP.) */ +#define R_BSP_GET_EXTB() R_BSP_GetEXTB() + +#endif +#endif + +/* ---------- Bit Manipulation ---------- */ +#if defined(__CCRX__) + +/* void __bclr(unsigned char *data, unsigned long bit) */ +#define R_BSP_BIT_CLEAR(x, y) __bclr((unsigned char *)(x), (unsigned long)(y)) +/* void __bset(unsigned char *data, unsigned long bit) */ +#define R_BSP_BIT_SET(x, y) __bset((unsigned char *)(x), (unsigned long)(y)) +/* void __bnot(unsigned char *data, unsigned long bit) */ +#define R_BSP_BIT_REVERSE(x, y) __bnot((unsigned char *)(x), (unsigned long)(y)) + +#elif defined(__GNUC__) + +/* void R_BSP_BitClear(uint8_t *data, uint32_t bit) (This macro uses API function of BSP.) */ +#define R_BSP_BIT_CLEAR(x, y) R_BSP_BitClear((uint8_t *)(x), (uint32_t)(y)) +/* void R_BSP_BitSet(uint8_t *data, uint32_t bit) (This macro uses API function of BSP.) */ +#define R_BSP_BIT_SET(x, y) R_BSP_BitSet((uint8_t *)(x), (uint32_t)(y)) +/* void R_BSP_BitReverse(uint8_t *data, uint32_t bit) (This macro uses API function of BSP.) */ +#define R_BSP_BIT_REVERSE(x, y) R_BSP_BitReverse((uint8_t *)(x), (uint32_t)(y)) + +#elif defined(__ICCRX__) + +/* void R_BSP_BitClear(uint8_t *data, uint32_t bit) (This macro uses API function of BSP.) */ +#define R_BSP_BIT_CLEAR(x, y) R_BSP_BitClear((uint8_t *)(x), (uint32_t)(y)) +/* void R_BSP_BitSet(uint8_t *data, uint32_t bit) (This macro uses API function of BSP.) */ +#define R_BSP_BIT_SET(x, y) R_BSP_BitSet((uint8_t *)(x), (uint32_t)(y)) +/* void R_BSP_BitReverse(uint8_t *data, uint32_t bit) (This macro uses API function of BSP.) */ +#define R_BSP_BIT_REVERSE(x, y) R_BSP_BitReverse((uint8_t *)(x), (uint32_t)(y)) + +#endif + +#ifdef BSP_MCU_DOUBLE_PRECISION_FLOATING_POINT +#ifdef __DPFPU +/* ---------- Double-Precision Floating-Point Status Word (DPSW) ---------- */ +#if defined(__CCRX__) + +/* void set_dpsw(unsigned long data) */ +#define R_BSP_SET_DPSW(x) __set_dpsw((unsigned long)(x)) +/* unsigned long get_dpsw(void) */ +#define R_BSP_GET_DPSW() __get_dpsw() + +#elif defined(__GNUC__) + +/* void R_BSP_SetDPSW(uint32_t data) (This macro uses API function of BSP.) */ +#define R_BSP_SET_DPSW(x) R_BSP_SetDPSW((uint32_t)(x)) +/* uint32_t R_BSP_GetDPSW(void) (This macro uses API function of BSP.) */ +#define R_BSP_GET_DPSW() R_BSP_GetDPSW() + +#elif defined(__ICCRX__) + +/* void R_BSP_SetDPSW(uint32_t data) (This macro uses API function of BSP.) */ +#define R_BSP_SET_DPSW(x) R_BSP_SetDPSW((uint32_t)(x)) +/* uint32_t R_BSP_GetDPSW(void) (This macro uses API function of BSP.) */ +#define R_BSP_GET_DPSW() R_BSP_GetDPSW() + +#endif + +/* ---------- Double-precision floating-point exception handling operation control register (DECNT) ---------- */ +#if defined(__CCRX__) + +/* void __set_decnt(unsigned long data) */ +#define R_BSP_SET_DECNT(x) __set_decnt((unsigned long)(x)) +/* unsigned long __get_decnt(void) */ +#define R_BSP_GET_DECNT() __get_decnt() + +#elif defined(__GNUC__) + +/* void R_BSP_SetDECNT(uint32_t data) (This macro uses API function of BSP.) */ +#define R_BSP_SET_DECNT(x) R_BSP_SetDECNT((uint32_t)(x)) +/* uint32_t R_BSP_GetDECNT(void) (This macro uses API function of BSP.) */ +#define R_BSP_GET_DECNT() R_BSP_GetDECNT() + +#elif defined(__ICCRX__) + +/* void R_BSP_SetDECNT(uint32_t data) (This macro uses API function of BSP.) */ +#define R_BSP_SET_DECNT(x) R_BSP_SetDECNT((uint32_t)(x)) +/* uint32_t R_BSP_GetDECNT(void) (This macro uses API function of BSP.) */ +#define R_BSP_GET_DECNT() R_BSP_GetDECNT() + +#endif + +/* ---------- Double-precision floating-point exception program counter (DEPC) ---------- */ +#if defined(__CCRX__) + +/* void *__get_depc(void) */ +#define R_BSP_GET_DEPC() __get_depc() + +#elif defined(__GNUC__) + +/* void *R_BSP_GetDEPC(void) (This macro uses API function of BSP.) */ +#define R_BSP_GET_DEPC() R_BSP_GetDEPC() + +#elif defined(__ICCRX__) + +/* void *R_BSP_GetDEPC(void) (This macro uses API function of BSP.) */ +#define R_BSP_GET_DEPC() R_BSP_GetDEPC() + +#endif +#endif /* __DPFPU */ +#endif /* BSP_MCU_DOUBLE_PRECISION_FLOATING_POINT */ + +/* ---------- Initializes the trigonometric function unit. ---------- */ +#ifdef BSP_MCU_TRIGONOMETRIC +#if BSP_MCU_TFU_VERSION == 1 +#if defined(__CCRX__) + +/* void __init_tfu(void) */ +#define R_BSP_INIT_TFU() __init_tfu() + +#elif defined(__GNUC__) + +/* void R_BSP_InitTFU(void) (This macro uses API function of BSP.) */ +#define R_BSP_INIT_TFU() R_BSP_InitTFU() + +#elif defined(__ICCRX__) + +/* Invalid for ICCRX. + Because the initilaze function of TFU is called automatically when the TFU function is called. */ +#define R_BSP_INIT_TFU() +#endif /* BSP_MCU_TFU_VERSION == 1 */ +#endif + +/* ---------- Uses the trigonometric function unit to calculate the sine and cosine of an angle at the same time. + (single precision) ---------- */ +#if defined(__CCRX__) + +/* void __sincosf(float f, float *sin, float *cos) */ +#define R_BSP_SINCOSF(x, y, z) __sincosf((float)(x), (float *)(y), (float *)(z)) + +#elif defined(__GNUC__) + +/* void R_BSP_CalcSine_Cosine(float f, float *sin, float *cos) (This macro uses API function of BSP.) */ +#define R_BSP_SINCOSF(x, y, z) R_BSP_CalcSine_Cosine((float)(x), (float *)(y), (float *)(z)) + +#elif defined(__ICCRX__) + +/* void __sincosf(float _F, float *dstSin, float *dstCos) */ +#define R_BSP_SINCOSF(x, y, z) __sincosf((float)(x), (float *)(y), (float *)(z)) + +#endif + +/* ---------- Uses the trigonometric function unit to calculate the arc tangent of x and y and the square root of the + sum of squares of these values at the same time. (single precision) ---------- */ +#if defined(__CCRX__) + +/* void __atan2hypotf(float y, float x, float *atan2, float *hypot) */ +#define R_BSP_ATAN2HYPOTF(w, x, y, z) __atan2hypotf((float)(w), (float)(x), (float *)(y), (float *)(z)) + +#elif defined(__GNUC__) + +/* void R_BSP_CalcAtan_SquareRoot(float y, float x, float *atan2, float *hypot) + (This macro uses API function of BSP.) */ +#define R_BSP_ATAN2HYPOTF(w, x, y, z) R_BSP_CalcAtan_SquareRoot((float)(w), (float)(x), (float *)(y), (float *)(z)) + +#elif defined(__ICCRX__) + +/* void __atan2hypotf(float _Y, float _X, float *dstAtan2, float *dstHypot) */ +#define R_BSP_ATAN2HYPOTF(w, x, y, z) __atan2hypotf((float)(w), (float)(x), (float *)(y), (float *)(z)) + +#endif + +#if BSP_MCU_TFU_VERSION == 2 +/* ---------- Uses the trigonometric function unit to calculate the sine and cosine of an angle. + (fixed-point numbers) ---------- */ +#if defined(__CCRX__) + +#if __RENESAS_VERSION__ >= 0x03050000 +/* void __sincosfx(signed long fx, signed long *sin, signed long *cos) */ +#define R_BSP_SINCOSFX(x, y, z) __sincosfx((int32_t)(x), (int32_t *)(y), (int32_t *)(z)) +#else +#define R_BSP_SINCOSFX(x, y, z) +#endif + +#elif defined(__GNUC__) + +/* void R_BSP_CalcSine_Cosine_Fpn(int32_t fx, int32_t *sin, int32_t *cos) (This macro uses API function of BSP.) */ +#define R_BSP_SINCOSFX(x, y, z) R_BSP_CalcSine_Cosine_Fpn((int32_t)(x), (int32_t *)(y), (int32_t *)(z)) + +#elif defined(__ICCRX__) + +/* void R_BSP_CalcSine_Cosine_Fpn(int32_t fx, int32_t *sin, int32_t *cos) (This macro uses API function of BSP.) */ +#define R_BSP_SINCOSFX(x, y, z) R_BSP_CalcSine_Cosine_Fpn((int32_t)(x), (int32_t *)(y), (int32_t *)(z)) + +#endif + +/* ---------- Uses the trigonometric function unit to calculate the sine of an angle. (fixed-point numbers) + ---------- */ +#if defined(__CCRX__) + +#if __RENESAS_VERSION__ >= 0x03050000 +/* signed long __sinfx(signed long fx) */ +#define R_BSP_SINFX(x) __sinfx((int32_t)(x)) +#else +#define R_BSP_SINFX(x) +#endif + +#elif defined(__GNUC__) + +/* int32_t R_BSP_CalcSine_Fpn(int32_t fx) (This macro uses API function of BSP.) */ +#define R_BSP_SINFX(x) R_BSP_CalcSine_Fpn((int32_t)(x)) + +#elif defined(__ICCRX__) + +/* int32_t R_BSP_CalcSine_Fpn(int32_t fx) (This macro uses API function of BSP.) */ +#define R_BSP_SINFX(x) R_BSP_CalcSine_Fpn((int32_t)(x)) + +#endif + +/* ---------- Uses the trigonometric function unit to calculate the cosine of an angle. (fixed-point numbers) + ---------- */ +#if defined(__CCRX__) + +#if __RENESAS_VERSION__ >= 0x03050000 +/* signed long __cosfx(signed long fx) */ +#define R_BSP_COSFX(x) __cosfx((int32_t)(x)) +#else +#define R_BSP_COSFX(x) +#endif + +#elif defined(__GNUC__) + +/* int32_t R_BSP_CalcCosine_Fpn(int32_t fx) (This macro uses API function of BSP.) */ +#define R_BSP_COSFX(x) R_BSP_CalcCosine_Fpn((int32_t)(x)) + +#elif defined(__ICCRX__) + +/* int32_t R_BSP_CalcCosine_Fpn(int32_t fx) (This macro uses API function of BSP.) */ +#define R_BSP_COSFX(x) R_BSP_CalcCosine_Fpn((int32_t)(x)) + +#endif + +/* ---------- Uses the trigonometric function unit to calculate the arc tangent of x and y and the square root of the + sum of squares of these values. (fixed-point numbers) ---------- */ +#if defined(__CCRX__) + +#if __RENESAS_VERSION__ >= 0x03050000 +/* __atan2hypotfx(signed long y, signed long x, signed long *atan2, signed long *hypot) */ +#define R_BSP_ATAN2HYPOTFX(w, x, y, z) __atan2hypotfx((int32_t)(w), (int32_t)(x), (int32_t *)(y), (int32_t *)(z)) +#else +#define R_BSP_ATAN2HYPOTFX(w, x, y, z) +#endif + +#elif defined(__GNUC__) + +/* void R_BSP_CalcAtan_SquareRoot_Fpn(int32_t y, int32_t x, int32_t *atan2, int32_t *hypot) + (This macro uses API function of BSP.) */ +#define R_BSP_ATAN2HYPOTFX(w, x, y, z) R_BSP_CalcAtan_SquareRoot_Fpn((int32_t)(w), (int32_t)(x), (int32_t *)(y), (int32_t *)(z)) + +#elif defined(__ICCRX__) + +/* void R_BSP_CalcAtan_SquareRoot_Fpn(int32_t y, int32_t x, int32_t *atan2, int32_t *hypot) + (This macro uses API function of BSP.) */ +#define R_BSP_ATAN2HYPOTFX(w, x, y, z) R_BSP_CalcAtan_SquareRoot_Fpn((int32_t)(w), (int32_t)(x), (int32_t *)(y), (int32_t *)(z)) + +#endif + +/* ---------- Uses the trigonometric function unit to calculate the arc tangent of x and y. (fixed-point numbers) + ---------- */ +#if defined(__CCRX__) + +#if __RENESAS_VERSION__ >= 0x03050000 +/* signed long __atan2fx(signed long y, signed long x) */ +#define R_BSP_ATAN2FX(x, y) __atan2fx((int32_t)(x), (int32_t)(y)) +#else +#define R_BSP_ATAN2FX(x, y) +#endif + +#elif defined(__GNUC__) + +/* int32_t R_BSP_CalcAtan_Fpn(int32_t y, int32_t x) (This macro uses API function of BSP.) */ +#define R_BSP_ATAN2FX(x, y) R_BSP_CalcAtan_Fpn((int32_t)(x), (int32_t)(y)) + +#elif defined(__ICCRX__) + +/* int32_t R_BSP_CalcAtan_Fpn(int32_t y, int32_t x) (This macro uses API function of BSP.) */ +#define R_BSP_ATAN2FX(x, y) R_BSP_CalcAtan_Fpn((int32_t)(x), (int32_t)(y)) + +#endif + +/* ---------- Uses the trigonometric function unit to calculate the square root of the + sum of squares of x and y. (fixed-point numbers) ---------- */ +#if defined(__CCRX__) + +#if __RENESAS_VERSION__ >= 0x03050000 +/* signed long __hypotfx(signed long x, signed long y) */ +#define R_BSP_HYPOTFX(x, y) __hypotfx((int32_t)(x), (int32_t)(y)) +#else +#define R_BSP_HYPOTFX(x, y) +#endif + +#elif defined(__GNUC__) + +/* int32_t R_BSP_CalcSquareRoot_Fpn(int32_t x, int32_t y) (This macro uses API function of BSP.) */ +#define R_BSP_HYPOTFX(x, y) R_BSP_CalcSquareRoot_Fpn((int32_t)(x), (int32_t)(y)) + +#elif defined(__ICCRX__) + +/* int32_t R_BSP_CalcSquareRoot_Fpn(int32_t x, int32_t y) (This macro uses API function of BSP.) */ +#define R_BSP_HYPOTFX(x, y) R_BSP_CalcSquareRoot_Fpn((int32_t)(x), (int32_t)(y)) + +#endif + +#endif /* BSP_MCU_TFU_VERSION == 2 */ +#endif /* BSP_MCU_TRIGONOMETRIC */ + +/*********************************************************************************************************************** +Exported global variables +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ +#if defined(__GNUC__) +signed long R_BSP_Max(signed long data1, signed long data2); +signed long R_BSP_Min(signed long data1, signed long data2); +long long R_BSP_MulAndAccOperation_B(long long init, unsigned long count, signed char *addr1, signed char *addr2); +long long R_BSP_MulAndAccOperation_W(long long init, unsigned long count, short *addr1, short *addr2); +long long R_BSP_MulAndAccOperation_L(long long init, unsigned long count, long *addr1, long *addr2); +unsigned long R_BSP_RotateLeftWithCarry(unsigned long data); +unsigned long R_BSP_RotateRightWithCarry(unsigned long data); +unsigned long R_BSP_RotateLeft(unsigned long data, unsigned long num); +unsigned long R_BSP_RotateRight(unsigned long data, unsigned long num); +long R_BSP_MulAndAccOperation_2byte(short* data1, short* data2, unsigned long count); +short R_BSP_MulAndAccOperation_FixedPoint1(short* data1, short* data2, unsigned long count); +short R_BSP_MulAndAccOperation_FixedPoint2(short* data1, short* data2, unsigned long count); +#endif /* defined(__GNUC__) */ + +#if defined(__GNUC__) || defined(__ICCRX__) +signed long long R_BSP_SignedMultiplication(signed long data1, signed long data2); +unsigned long long R_BSP_UnsignedMultiplication(unsigned long data1, unsigned long data2); +void R_BSP_SetACC(signed long long data); +signed long long R_BSP_GetACC(void); +#endif /* defined(__GNUC__) || defined(__ICCRX__) */ + +R_BSP_ATTRIB_INLINE_ASM void R_BSP_ChangeToUserMode(void); +R_BSP_ATTRIB_INLINE_ASM void R_BSP_SetBPSW(uint32_t data); +uint32_t R_BSP_GetBPSW(void); +R_BSP_ATTRIB_INLINE_ASM void R_BSP_SetBPC(void * data); +void *R_BSP_GetBPC(void); +#ifdef BSP_MCU_EXCEPTION_TABLE +R_BSP_ATTRIB_INLINE_ASM void R_BSP_SetEXTB(void * data); +void *R_BSP_GetEXTB(void); +#endif /* BSP_MCU_EXCEPTION_TABLE */ +R_BSP_ATTRIB_INLINE_ASM void R_BSP_BitSet(uint8_t *data, uint32_t bit); +R_BSP_ATTRIB_INLINE_ASM void R_BSP_BitClear(uint8_t *data, uint32_t bit); +R_BSP_ATTRIB_INLINE_ASM void R_BSP_BitReverse(uint8_t *data, uint32_t bit); +R_BSP_ATTRIB_INLINE_ASM void R_BSP_MoveToAccHiLong(int32_t data); +R_BSP_ATTRIB_INLINE_ASM void R_BSP_MoveToAccLoLong(int32_t data); +int32_t R_BSP_MoveFromAccHiLong(void); +int32_t R_BSP_MoveFromAccMiLong(void); +#ifdef BSP_MCU_DOUBLE_PRECISION_FLOATING_POINT +#ifdef __DPFPU +R_BSP_ATTRIB_INLINE_ASM void R_BSP_SetDPSW(uint32_t data); +uint32_t R_BSP_GetDPSW(void); +R_BSP_ATTRIB_INLINE_ASM void R_BSP_SetDECNT(uint32_t data); +uint32_t R_BSP_GetDECNT(void); +void *R_BSP_GetDEPC(void); +#endif +#endif +#ifdef BSP_MCU_TRIGONOMETRIC +#ifdef __TFU +#if BSP_MCU_TFU_VERSION == 1 +R_BSP_ATTRIB_INLINE_ASM void R_BSP_InitTFU(void); +#endif /* BSP_MCU_TFU_VERSION == 1 */ +#ifdef __FPU +R_BSP_ATTRIB_INLINE_ASM void R_BSP_CalcSine_Cosine(float f, float *sin, float *cos); +R_BSP_ATTRIB_INLINE_ASM void R_BSP_CalcAtan_SquareRoot(float y, float x, float *atan2, float *hypot); +#endif /* __FPU */ +#if BSP_MCU_TFU_VERSION == 2 +R_BSP_ATTRIB_INLINE_ASM void R_BSP_CalcSine_Cosine_Fpn(int32_t f, int32_t *sin, int32_t *cos); +int32_t R_BSP_CalcSine_Fpn(int32_t fx); +int32_t R_BSP_CalcCosine_Fpn(int32_t fx); +R_BSP_ATTRIB_INLINE_ASM void R_BSP_CalcAtan_SquareRoot_Fpn(int32_t y, int32_t x, int32_t *atan2, int32_t *hypot); +int32_t R_BSP_CalcAtan_Fpn(int32_t y, int32_t x); +int32_t R_BSP_CalcSquareRoot_Fpn(int32_t y, int32_t x); +#endif /* BSP_MCU_TFU_VERSION == 2 */ +#endif /* __TFU */ +#endif + +/* End of multiple inclusion prevention macro */ +#endif /* R_RX_INTRINSIC_FUNCTIONS_H */ + diff --git a/drivers/rx/rdp/src/r_bsp/mcu/rx130/mcu_clocks.c b/drivers/rx/rdp/src/r_bsp/mcu/rx130/mcu_clocks.c new file mode 100644 index 00000000..dac45768 --- /dev/null +++ b/drivers/rx/rdp/src/r_bsp/mcu/rx130/mcu_clocks.c @@ -0,0 +1,887 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 - 2024 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : mcu_clocks.c +* Description : Contains clock specific routines +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 01.12.2015 1.00 First Release +* : 28.02.2019 2.00 Added clock setup. +* Fixed cast of get_iclk_freq_hz function. +* Fixed coding style. +* Renamed following macro definitions. +* - BSP_PRV_CKSEL_LOCO +* - BSP_PRV_CKSEL_HOCO +* - BSP_PRV_CKSEL_MAIN_OSC +* - BSP_PRV_CKSEL_SUBCLOCK +* - BSP_PRV_CKSEL_PLL +* - BSP_PRV_SUB_CLK_SOSCCR +* - BSP_PRV_SUB_CLK_SOSCCR +* - BSP_PRV_NORMALIZE_X10 +* Deleted the error check of BSP_CFG_CLOCK_SOURCE in the clock_source_select function. +* : 17.12.2019 2.01 Deleted the unused variables of clock_source_select function and +* lpt_clock_source_select function. +* Fixed warning of clock_source_select function with IAR compiler. +* : 14.02.2020 2.02 Fixed warning of clock_source_select function with CCRX and IAR compiler. +* : 29.01.2021 2.03 Fixed the initialization settings of sub-clock for Technical Update Information +* (TN-RX*-A0238B). +* : 30.11.2021 3.00 Added the following macro definition. +* - BSP_PRV_PLL_CLK_OPERATING +* Changed compile switch of clock settings by the following new macro definitions. +* - BSP_CFG_MAIN_CLOCK_OSCILLATE_ENABLE +* - BSP_CFG_SUB_CLOCK_OSCILLATE_ENABLE +* - BSP_CFG_HOCO_OSCILLATE_ENABLE +* - BSP_CFG_LOCO_OSCILLATE_ENABLE +* - BSP_PRV_PLL_CLK_OPERATING +* Deleted the macro definition of BSP_PRV_SUB_CLK_SOSCCR. +* Added the setting of the IWDT-Dedicated On-Chip Oscillator in operating_frequency_set +* function. +* Deleted the process of oscillating the IWDT-Dedicated On-Chip Oscillator from +* lpt_clock_source_select function. +* Added the bsp_clkout_initial_configure function. +* Added the setting of the HOCO trimming register. +* Added comments for when use simulator. +* Added version check of smart configurator. +* : 22.04.2022 3.01 Deleted version check of smart configurator. +* : 21.11.2023 3.02 Added compile switch of BSP_CFG_BOOTLOADER_PROJECT. +* Added the bsp_mcu_clock_reset_bootloader function. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "platform.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +#define BSP_PRV_CKSEL_LOCO (0x0) +#define BSP_PRV_CKSEL_HOCO (0x1) +#define BSP_PRV_CKSEL_MAIN_OSC (0x2) +#define BSP_PRV_CKSEL_SUBCLOCK (0x3) +#define BSP_PRV_CKSEL_PLL (0x4) + +#define BSP_PRV_NORMALIZE_X10 (10) /* used to avoid floating point arithmetic */ + +/* This macro runs or stops the PLL circuit. + If the following conditions are satisfied, PLL circuit will operate. + 1. System clock source is PLL circuit. + 2. Clock output enable and clock output source is PLL circuit. + */ +#if (BSP_CFG_CLOCK_SOURCE == 4) \ + || ((BSP_CFG_CLKOUT_OUTPUT == 1) && (BSP_CFG_CLKOUT_SOURCE == 4)) + #define BSP_PRV_PLL_CLK_OPERATING (1) /* PLL circuit is operating. */ +#else /* PLL is not used as clock source. */ + #define BSP_PRV_PLL_CLK_OPERATING (0) /* PLL circuit is stopped. */ +#endif + +#if BSP_CFG_BOOTLOADER_PROJECT == 1 +/* Enable the following macro definitions in the bootloader project. */ +#define BSP_PRV_SCKCR_RESET_VALUE (0x33000303) +#define BSP_PRV_SCKCR3_RESET_VALUE (0x0000) +#define BSP_PRV_PLLCR_RESET_VALUE (0x0f00) +#define BSP_PRV_PLLCR2_RESET_VALUE (0x01) +#define BSP_PRV_MOSCCR_RESET_VALUE (0x01) +#define BSP_PRV_MOSCWTCR_RESET_VALUE (0x04) +#define BSP_PRV_MOFCR_RESET_VALUE (0x00) +#define BSP_PRV_OPCCR_RESET_VALUE (0x02) +#endif /* BSP_CFG_BOOTLOADER_PROJECT == 1 */ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ +/* When using the user startup program, disable the following code. */ +#if BSP_CFG_STARTUP_DISABLE == 0 +static void operating_frequency_set(void); +static void clock_source_select(void); +#if BSP_CFG_BOOTLOADER_PROJECT == 0 +/* Disable the following functions in the bootloader project. */ +static void lpt_clock_source_select(void); +#if BSP_CFG_CLKOUT_OUTPUT != 0 +/* CLKOUT initial configuration function declaration */ +static void bsp_clkout_initial_configure(void); +#endif /* BSP_CFG_CLKOUT_OUTPUT != 0 */ +#endif /* BSP_CFG_BOOTLOADER_PROJECT == 0 */ +#endif /* BSP_CFG_STARTUP_DISABLE == 0 */ + +/*********************************************************************************************************************** +* Function Name: get_iclk_freq_hz +* Description : Return the current ICLK frequency in Hz. Called by R_BSP_GetIClkFreqHz(). +* The system clock source can be changed at any time via SYSTEM.SCKCR3.BIT.CKSEL, so in order to +* determine the ICLK frequency we need to first find the current system clock source and then, +* in some cases where the clock source can be configured for multiple frequencies, calculate the +* frequency at which it is currently running. +* Arguments : None +* Return Value : uint32_t - the iclk frequency in Hz +***********************************************************************************************************************/ +uint32_t get_iclk_freq_hz(void) +{ + uint32_t sys_clock_src_freq; + uint32_t pll_multiplier; + + /* Casting is valid because it matches the type to the retern value. */ + uint8_t cksel = (uint8_t)SYSTEM.SCKCR3.BIT.CKSEL; + + switch (cksel) + { + case BSP_PRV_CKSEL_LOCO: + sys_clock_src_freq = BSP_LOCO_HZ; + break; + + case BSP_PRV_CKSEL_HOCO: + sys_clock_src_freq = BSP_HOCO_HZ; + break; + + case BSP_PRV_CKSEL_MAIN_OSC: + sys_clock_src_freq = BSP_CFG_XTAL_HZ; + break; + + case BSP_PRV_CKSEL_SUBCLOCK: + sys_clock_src_freq = BSP_SUB_CLOCK_HZ; + break; + + case BSP_PRV_CKSEL_PLL: + + /* Casting is valid because it matches the type to the retern value. */ + pll_multiplier = ((((uint32_t)(SYSTEM.PLLCR.BIT.STC + 1)) * BSP_PRV_NORMALIZE_X10) / 2); + + /* Casting is valid because it matches the type to the retern value. */ + sys_clock_src_freq = ((BSP_CFG_XTAL_HZ / (((uint32_t)(1 << SYSTEM.PLLCR.BIT.PLIDIV)) * BSP_PRV_NORMALIZE_X10)) * pll_multiplier); + break; + + default: + + /* Should never arrive here. Use the Main OSC freq as a default... */ + sys_clock_src_freq = BSP_CFG_XTAL_HZ; + break; + } + + /* Finally, divide the system clock source frequency by the currently set ICLK divider to get the ICLK frequency */ + return (sys_clock_src_freq / (uint32_t)(1 << SYSTEM.SCKCR.BIT.ICK)); +} /* End of function get_iclk_freq_hz() */ + +/* When using the user startup program, disable the following code. */ +#if BSP_CFG_STARTUP_DISABLE == 0 + +/*********************************************************************************************************************** +* Function name: mcu_clock_setup +* Description : Contains clock functions called at device restart. +* Arguments : none +* Return value : none +***********************************************************************************************************************/ +void mcu_clock_setup(void) +{ + /* Switch to high-speed operation */ + operating_frequency_set(); +#if BSP_CFG_BOOTLOADER_PROJECT == 0 +/* Disable the following functions in the bootloader project. */ + lpt_clock_source_select(); + +#if BSP_CFG_CLKOUT_OUTPUT != 0 + bsp_clkout_initial_configure(); +#endif /* BSP_CFG_CLKOUT_OUTPUT != 0 */ +#endif /* BSP_CFG_BOOTLOADER_PROJECT == 0 */ +} /* End of function mcu_clock_setup() */ + +/*********************************************************************************************************************** +* Function name: operating_frequency_set +* Description : Configures the clock settings for each of the device clocks +* Arguments : none +* Return value : none +***********************************************************************************************************************/ +static void operating_frequency_set (void) +{ + /* Used for constructing value to write to SCKCR, and SCKCR3 registers. */ + uint32_t tmp_clock = 0; + + /* Protect off. */ + SYSTEM.PRCR.WORD = 0xA50F; + + /* Select the clock based upon user's choice. */ + clock_source_select(); + + /* Figure out setting for FCK bits. */ +#if BSP_CFG_FCK_DIV == 1 + /* Do nothing since FCK bits should be 0. */ +#elif BSP_CFG_FCK_DIV == 2 + tmp_clock |= 0x10000000; +#elif BSP_CFG_FCK_DIV == 4 + tmp_clock |= 0x20000000; +#elif BSP_CFG_FCK_DIV == 8 + tmp_clock |= 0x30000000; +#elif BSP_CFG_FCK_DIV == 16 + tmp_clock |= 0x40000000; +#elif BSP_CFG_FCK_DIV == 32 + tmp_clock |= 0x50000000; +#elif BSP_CFG_FCK_DIV == 64 + tmp_clock |= 0x60000000; +#else + #error "Error! Invalid setting for BSP_CFG_FCK_DIV in r_bsp_config.h" +#endif + + /* Figure out setting for ICK bits. */ +#if BSP_CFG_ICK_DIV == 1 + /* Do nothing since ICK bits should be 0. */ +#elif BSP_CFG_ICK_DIV == 2 + tmp_clock |= 0x01000000; +#elif BSP_CFG_ICK_DIV == 4 + tmp_clock |= 0x02000000; +#elif BSP_CFG_ICK_DIV == 8 + tmp_clock |= 0x03000000; +#elif BSP_CFG_ICK_DIV == 16 + tmp_clock |= 0x04000000; +#elif BSP_CFG_ICK_DIV == 32 + tmp_clock |= 0x05000000; +#elif BSP_CFG_ICK_DIV == 64 + tmp_clock |= 0x06000000; +#else + #error "Error! Invalid setting for BSP_CFG_ICK_DIV in r_bsp_config.h" +#endif + + /* Figure out setting for PCKB bits. */ +#if BSP_CFG_PCKB_DIV == 1 + /* Do nothing since PCKB bits should be 0. */ +#elif BSP_CFG_PCKB_DIV == 2 + tmp_clock |= 0x00000100; +#elif BSP_CFG_PCKB_DIV == 4 + tmp_clock |= 0x00000200; +#elif BSP_CFG_PCKB_DIV == 8 + tmp_clock |= 0x00000300; +#elif BSP_CFG_PCKB_DIV == 16 + tmp_clock |= 0x00000400; +#elif BSP_CFG_PCKB_DIV == 32 + tmp_clock |= 0x00000500; +#elif BSP_CFG_PCKB_DIV == 64 + tmp_clock |= 0x00000600; +#else + #error "Error! Invalid setting for BSP_CFG_PCKB_DIV in r_bsp_config.h" +#endif + + /* Figure out setting for PCKD bits. */ +#if BSP_CFG_PCKD_DIV == 1 + /* Do nothing since PCKD bits should be 0. */ +#elif BSP_CFG_PCKD_DIV == 2 + tmp_clock |= 0x00000001; +#elif BSP_CFG_PCKD_DIV == 4 + tmp_clock |= 0x00000002; +#elif BSP_CFG_PCKD_DIV == 8 + tmp_clock |= 0x00000003; +#elif BSP_CFG_PCKD_DIV == 16 + tmp_clock |= 0x00000004; +#elif BSP_CFG_PCKD_DIV == 32 + tmp_clock |= 0x00000005; +#elif BSP_CFG_PCKD_DIV == 64 + tmp_clock |= 0x00000006; +#else + #error "Error! Invalid setting for BSP_CFG_PCKD_DIV in r_bsp_config.h" +#endif + + /* Set SCKCR register. */ + SYSTEM.SCKCR.LONG = tmp_clock; + + /* Dummy read and compare. cf."5. I/O Registers", "(2) Notes on writing to I/O registers" in User's manual. + This is done to ensure that the register has been written before the next register access. The RX has a + pipeline architecture so the next instruction could be executed before the previous write had finished. + */ + if(tmp_clock == SYSTEM.SCKCR.LONG) + { + R_BSP_NOP(); + } + + /* Choose clock source. Default for r_bsp_config.h is PLL. */ + tmp_clock = ((uint16_t)BSP_CFG_CLOCK_SOURCE) << 8; + + /* Casting is valid because it matches the type to the retern value. */ + SYSTEM.SCKCR3.WORD = (uint16_t)tmp_clock; + + /* Dummy read and compare. cf."5. I/O Registers", "(2) Notes on writing to I/O registers" in User's manual. + This is done to ensure that the register has been written before the next register access. The RX has a + pipeline architecture so the next instruction could be executed before the previous write had finished. + */ + if((uint16_t)tmp_clock == SYSTEM.SCKCR3.WORD) + { + R_BSP_NOP(); + } + +#if BSP_CFG_BOOTLOADER_PROJECT == 0 +/* Disable the following functions in the bootloader project. */ +#if BSP_CFG_IWDT_CLOCK_OSCILLATE_ENABLE == 1 + /* IWDT clock is stopped after reset. Oscillate the IWDT. */ + SYSTEM.ILOCOCR.BIT.ILCSTP = 0; + + /* Wait processing for the IWDT clock oscillation stabilization (50us) */ + R_BSP_SoftwareDelay((uint32_t)50, BSP_DELAY_MICROSECS); +#endif + +#if BSP_CFG_LOCO_OSCILLATE_ENABLE == 0 + /* We can now turn LOCO off since it is not going to be used. */ + SYSTEM.LOCOCR.BYTE = 0x01; + + /* Wait for five the LOCO cycles */ + /* 5 count of LOCO : (1000000/3440000)*5 = 1.453488us + 1.45 + 2 = 3.45us ("+2" is overhead cycle) */ + R_BSP_SoftwareDelay((uint32_t)4, BSP_DELAY_MICROSECS); +#endif +#endif /* BSP_CFG_BOOTLOADER_PROJECT == 0 */ + + /* Protect on. */ + SYSTEM.PRCR.WORD = 0xA500; +} /* End of function operating_frequency_set() */ + +/*********************************************************************************************************************** +* Function name: clock_source_select +* Description : Enables and disables clocks as chosen by the user. If a clock other than LOCO or HOCO is already +* running when this function is called then that usually means a bootloader was run beforehand and set +* up the clocks already. +* Arguments : none +* Return value : none +***********************************************************************************************************************/ +static void clock_source_select (void) +{ +#if BSP_CFG_BOOTLOADER_PROJECT == 0 + /* Disable the following valiable in the bootloader project. */ +#if (BSP_CFG_SUB_CLOCK_OSCILLATE_ENABLE == 1) || (BSP_CFG_RTC_ENABLE == 1) + uint8_t tmp; +#endif /* (BSP_CFG_SUB_CLOCK_OSCILLATE_ENABLE == 1) || (BSP_CFG_RTC_ENABLE == 1) */ +#endif /* BSP_CFG_BOOTLOADER_PROJECT == 0 */ + + /* Set to High-speed operating mode if ICLK is > 12MHz. */ + if (BSP_ICLK_HZ > BSP_MIDDLE_SPEED_MAX_FREQUENCY) + { + /* WAIT_LOOP */ + while(1 == SYSTEM.OPCCR.BIT.OPCMTSF) + { + /* Wait for transition to finish. */ + R_BSP_NOP(); + } + + /* set to high-speed mode */ + SYSTEM.OPCCR.BYTE = 0x00; + + /* WAIT_LOOP */ + while(1 == SYSTEM.OPCCR.BIT.OPCMTSF) + { + /* Wait for transition to finish. */ + R_BSP_NOP(); + } + } + + /* At this time the MCU is still running on the 4MHz LOCO. */ + +#if BSP_CFG_HOCO_OSCILLATE_ENABLE == 1 + /* HOCO is chosen. Start it operating if it is not already operating. */ + if (1 == SYSTEM.HOCOCR.BIT.HCSTP) + { + #if BSP_CFG_HOCO_TRIMMING_ENABLE == 1 + /* Set the frequency trimming value for the HOCO. */ + SYSTEM.HOCOTRR0.BYTE = (0x3F & BSP_CFG_HOCO_TRIMMING_REG_VALUE); + #endif + + /* HOCO is chosen. Start it operating. */ + SYSTEM.HOCOCR.BYTE = 0x00; + + /* Dummy read and compare. cf."5. I/O Registers", "(2) Notes on writing to I/O registers" in User's manual. + This is done to ensure that the register has been written before the next register access. The RX has a + pipeline architecture so the next instruction could be executed before the previous write had finished. + */ + if(0x00 == SYSTEM.HOCOCR.BYTE) + { + R_BSP_NOP(); + } + + /* WAIT_LOOP */ + while(0 == SYSTEM.OSCOVFSR.BIT.HCOVF) + { + /* The delay period needed is to make sure that the HOCO has stabilized. + If you use simulator, the flag is not set to 1, resulting in an infinite loop. */ + R_BSP_NOP(); + } + } +#endif /* BSP_CFG_HOCO_OSCILLATE_ENABLE == 1 */ + +#if BSP_CFG_MAIN_CLOCK_OSCILLATE_ENABLE == 1 + /* Set the oscillation source of the main clock oscillator. */ + SYSTEM.MOFCR.BIT.MOSEL = BSP_CFG_MAIN_CLOCK_SOURCE; + + /* If the main oscillator is > 10MHz, and VCC is >= 2.4V then the main clock oscillator + forced oscillation control register (MOFCR) must be changed. */ + if ((BSP_CFG_MCU_VCC_MV >= 2400) && (BSP_CFG_XTAL_HZ >= 10000000)) + { + /* 10 - 20MHz. */ + SYSTEM.MOFCR.BIT.MODRV21 = 1; + } + else + { + /* 1 - 10MHz. */ + SYSTEM.MOFCR.BIT.MODRV21 = 0; + } + + /* Set the oscillation stabilization wait time of the main clock oscillator. */ +#if BSP_CFG_MAIN_CLOCK_SOURCE == 0 /* Resonator */ + SYSTEM.MOSCWTCR.BYTE = BSP_CFG_MOSC_WAIT_TIME; +#elif BSP_CFG_MAIN_CLOCK_SOURCE == 1 /* External oscillator input */ + SYSTEM.MOSCWTCR.BYTE = 0x00; +#else + #error "Error! Invalid setting for BSP_CFG_MAIN_CLOCK_SOURCE in r_bsp_config.h" +#endif + + /* Set the main clock to operating. */ + SYSTEM.MOSCCR.BYTE = 0x00; + + /* WAIT_LOOP */ + while (0 == SYSTEM.OSCOVFSR.BIT.MOOVF) + { + /* Make sure clock has stabilized. + If you use simulator, the flag is not set to 1, resulting in an infinite loop. */ + R_BSP_NOP(); + } + +#endif /* BSP_CFG_MAIN_CLOCK_OSCILLATE_ENABLE == 1 */ + +#if BSP_CFG_BOOTLOADER_PROJECT == 0 +/* Disable the following functions in the bootloader project. */ + /* Sub-clock setting. */ + + /* Cold start setting */ + if (0 == SYSTEM.RSTSR1.BIT.CWSF) + { + + /* SOSCCR - Sub-Clock Oscillator Control Register + b7:b1 Reserved - The write value should be 0. + b0 SOSTP - Sub-clock oscillator Stop - Sub-clock oscillator is stopped. */ + SYSTEM.SOSCCR.BYTE = 0x01; + + /* WAIT_LOOP */ + while (0x01 != SYSTEM.SOSCCR.BYTE) + { + /* wait for bit to change */ + R_BSP_NOP(); + } + + /* RCR3 - RTC Control Register 3 + b7:b4 Reserved - The write value should be 0. + b3:b1 RTCDV - Sub-clock oscillator Drive Ability Control. + b0 RTCEN - Sub-clock oscillator is stopped. */ + RTC.RCR3.BIT.RTCEN = 0; + + /* WAIT_LOOP */ + while (0 != RTC.RCR3.BIT.RTCEN) + { + /* wait for bit to change */ + R_BSP_NOP(); + } + +#if (BSP_CFG_SUB_CLOCK_OSCILLATE_ENABLE == 1) || (BSP_CFG_RTC_ENABLE == 1) + /* Wait for 5 sub-clock cycles (153us): measurement result is approx. 176us */ + R_BSP_SoftwareDelay(176, BSP_DELAY_MICROSECS); /* 153us * 4.56 / 4.00 (LOCO max) */ + + /* Set the drive capacity of the sub-clock oscillator */ + #if (BSP_CFG_SOSC_DRV_CAP == 0) /* Standard CL */ + tmp = 0x06; + #elif (BSP_CFG_SOSC_DRV_CAP == 1) /* Low CL */ + tmp = 0x01; + #else + #error "Error! Invalid setting for BSP_CFG_SOSC_DRV_CAP in r_bsp_config.h" + #endif + + /* Set the Sub-Clock Oscillator Drive Capacity Control. */ + RTC.RCR3.BIT.RTCDV = tmp; + + /* WAIT_LOOP */ + while (tmp != RTC.RCR3.BIT.RTCDV) + { + /* wait for bits to change */ + R_BSP_NOP(); + } +#endif /* (BSP_CFG_SUB_CLOCK_OSCILLATE_ENABLE == 1) || (BSP_CFG_RTC_ENABLE == 1) */ + +#if BSP_CFG_SUB_CLOCK_OSCILLATE_ENABLE == 1 + /* Operate the Sub-clock oscillator */ + SYSTEM.SOSCCR.BYTE = 0x00; + + /* WAIT_LOOP */ + while (0x00 != SYSTEM.SOSCCR.BYTE) + { + /* wait for bit to change */ + R_BSP_NOP(); + } + + /* Wait for the oscillation stabilization time of the sub-clock. */ + R_BSP_SoftwareDelay(BSP_CFG_SOSC_WAIT_TIME, BSP_DELAY_MILLISECS); +#endif + +#if BSP_CFG_RTC_ENABLE == 1 + /* ---- Operate the sub-clock oscillator ---- */ + RTC.RCR3.BIT.RTCEN = 0x01; + + /* WAIT_LOOP */ + while (0x01 != RTC.RCR3.BIT.RTCEN) + { + /* wait for bit to change */ + R_BSP_NOP(); + } +#endif + +#if (BSP_CFG_SUB_CLOCK_OSCILLATE_ENABLE == 0) && (BSP_CFG_RTC_ENABLE == 1) + /* Wait for the oscillation stabilization time of the sub-clock. */ + R_BSP_SoftwareDelay(BSP_CFG_SOSC_WAIT_TIME, BSP_DELAY_MILLISECS); +#endif + +#if (BSP_CFG_SUB_CLOCK_OSCILLATE_ENABLE == 1) || (BSP_CFG_RTC_ENABLE == 1) + /* Wait for six the sub-clock cycles */ + /* 6 count of sub-clock : (1000000/32768)*6=183.10546875us + In the case of LOCO frequency is 264kHz : 183.10546875/(1000000/264000)=48.33984375cycle + (48.33984375+2)*(1000000/240000)=209.7493489583333us ("+2" is overhead cycle) */ + R_BSP_SoftwareDelay((uint32_t)210, BSP_DELAY_MICROSECS); +#endif + +#if (BSP_CFG_SUB_CLOCK_OSCILLATE_ENABLE == 1) && (BSP_CFG_RTC_ENABLE == 0) + /* Stop prescaler and counter */ + /* RCR2 - RTC Control Register 2 + b7 CNTMD - Count Mode Select - The calendar count mode. + b6 HR24 - Hours Mode - The RTC operates in 24-hour mode. + b5 AADJP - Automatic Adjustment Period Select - The RADJ.ADJ[5:0] setting value is adjusted from + the count value of the prescaler every 10 seconds. + b4 AADJE - Automatic Adjustment Enable - Automatic adjustment is enabled. + b3 RTCOE - RTCOUT Output Enable - RTCOUT output enabled. + b2 ADJ30 - 30-Second Adjustment - 30-second adjustment is executed. + b1 RESET - RTC Software Reset - The prescaler and the target registers for RTC software reset are initialized. + b0 START - start - Prescaler is stopped. */ + RTC.RCR2.BYTE &= 0x7E; + + /* WAIT_LOOP */ + while (0 != RTC.RCR2.BIT.START) + { + /* Confirm that the written value can be read correctly. */ + R_BSP_NOP(); + } + + /* WAIT_LOOP */ + while (0 != RTC.RCR2.BIT.CNTMD) + { + /* Confirm that the written value can be read correctly. */ + R_BSP_NOP(); + } + + /* RTC Software Reset */ + RTC.RCR2.BIT.RESET = 1; + + /* WAIT_LOOP */ + while (0 != RTC.RCR2.BIT.RESET) + { + /* Confirm that the written value can be read correctly. + If you use simulator, the flag is not set to 0, resulting in an infinite loop. */ + R_BSP_NOP(); + } + + /* An alarm interrupt request is disabled */ + /* RCR1 - RTC Control Register 1 + b7:b4 PES - Periodic Interrupt Select - These bits specify the period for the periodic interrupt. + b3 RTCOS - RTCOUT Output Select - RTCOUT outputs 1 Hz. + b2 PIE - Periodic Interrupt Enable - A periodic interrupt request is disabled. + b1 CIE - Carry Interrupt Enable - A carry interrupt request is disabled. + b0 AIE - Alarm Interrupt Enable - An alarm interrupt request is disabled. */ + RTC.RCR1.BYTE &= 0xF8; + + /* WAIT_LOOP */ + while (0 != (0x07 & RTC.RCR1.BYTE)) + { + /* Confirm that the written value can be read correctly. */ + R_BSP_NOP(); + } +#endif /* (BSP_CFG_SUB_CLOCK_OSCILLATE_ENABLE == 1) && (BSP_CFG_RTC_ENABLE == 0) */ + } + /* Warm start setting */ + else + { +#if BSP_CFG_SUB_CLOCK_OSCILLATE_ENABLE == 0 + /* SOSCCR - Sub-Clock Oscillator Control Register + b7:b1 Reserved - The write value should be 0. + b0 SOSTP - Sub-clock oscillator Stop - Sub-clock oscillator is stopped. */ + SYSTEM.SOSCCR.BYTE = 0x01; + + /* WAIT_LOOP */ + while (0x01 != SYSTEM.SOSCCR.BYTE) + { + /* wait for bit to change */ + R_BSP_NOP(); + } +#endif + } +#endif /* BSP_CFG_BOOTLOADER_PROJECT == 0 */ + +#if BSP_PRV_PLL_CLK_OPERATING == 1 + /* PLL is chosen. Start it operating if it is not already. Must start main clock as well since PLL uses it. */ + + /* Set PLL Input Divisor. */ + SYSTEM.PLLCR.BIT.PLIDIV = BSP_CFG_PLL_DIV >> 1; + + /* Set PLL Multiplier. */ + SYSTEM.PLLCR.BIT.STC = (BSP_CFG_PLL_MUL * 2) - 1; + + /* Set the PLL to operating. */ + SYSTEM.PLLCR2.BYTE = 0x00; + + /* WAIT_LOOP */ + while (0 == SYSTEM.OSCOVFSR.BIT.PLOVF) + { + /* Make sure clock has stabilized. + If you use simulator, the flag is not set to 1, resulting in an infinite loop. */ + R_BSP_NOP(); + } +#endif + + /* LOCO is saved for last since it is what is running by default out of reset. This means you do not want to turn + it off until another clock has been enabled and is ready to use. */ +#if BSP_CFG_LOCO_OSCILLATE_ENABLE == 1 + /* LOCO is chosen. This is the default out of reset. */ +#else + /* LOCO is not chosen but it cannot be turned off yet since it is still being used. */ +#endif +} /* End of function clock_source_select() */ + +#if BSP_CFG_BOOTLOADER_PROJECT == 0 + /* Disable the following functions in the bootloader project. */ +/*********************************************************************************************************************** +* Function name: lpt_clock_source_select +* Description : Enables clock sources for the lpt (if not already done) as chosen by the user. +* Arguments : none +* Return value : none +***********************************************************************************************************************/ +static void lpt_clock_source_select (void) +{ + /* Protect off. */ + SYSTEM.PRCR.WORD = 0xA50F; + + /* INITIALIZE AND SELECT LPT CLOCK SOURCE */ + +#if (BSP_CFG_LPT_CLOCK_SOURCE == 0) || (BSP_CFG_LPT_CLOCK_SOURCE == 2) + /* Sub-clock or None is chosen. */ + /* sub-clock oscillator already initialized in clock_source_select() */ + +#elif (BSP_CFG_LPT_CLOCK_SOURCE == 1) + /* Controls whether to stop the IWDT counter in a low power consumption state. + IWDTCSTPR - IWDT Count Stop Control Register + b7 SLCSTP - Sleep Mode Count Stop Control - Count stop is disabled. + b6:b1 Reserved - These bits are read as 0. Writing to these bits has no effect. */ + IWDT.IWDTCSTPR.BIT.SLCSTP = 0; +#endif + + /* Enable protect bit */ + SYSTEM.PRCR.WORD = 0xA500; +} /* End of function lpt_clock_source_select() */ + +#if BSP_CFG_CLKOUT_OUTPUT != 0 +/*********************************************************************************************************************** +* Function name: bsp_clkout_initial_configure +* Description : Configures the CLKOUT initial settings +* Arguments : none +* Return value : none +***********************************************************************************************************************/ +static void bsp_clkout_initial_configure(void) +{ + /* Protect off. */ + SYSTEM.PRCR.WORD = 0xA50B; + + /* Set the CLKOUT Output Divisor Select. */ + SYSTEM.CKOCR.BIT.CKODIV = BSP_CFG_CLKOUT_DIV; + + /* Set the CLKOUT Output Source Select. */ + SYSTEM.CKOCR.BIT.CKOSEL = BSP_CFG_CLKOUT_SOURCE; +#if BSP_CFG_CLKOUT_OUTPUT == 1 + + /* Set the CLKOUT Output Stop Control. */ + SYSTEM.CKOCR.BIT.CKOSTP = 0; +#elif BSP_CFG_CLKOUT_OUTPUT == 0 + /* do nothing */ +#else + #error "Error! Invalid setting for BSP_CFG_CLKOUT_OUTPUT in r_bsp_config.h" +#endif + /* Protect on. */ + SYSTEM.PRCR.WORD = 0xA500; +} /* End of function bsp_clkout_initial_configure() */ +#endif /* BSP_CFG_CLKOUT_OUTPUT != 0 */ +#endif /* BSP_CFG_BOOTLOADER_PROJECT == 0 */ + +#if BSP_CFG_BOOTLOADER_PROJECT == 1 +/*********************************************************************************************************************** +* Function name: bsp_mcu_clock_reset_bootloader +* Description : Returns the MCU clock settings to the reset state. The system clock returns to LOCO. PLL circuit will +* stop. Main clock will stop. +* Arguments : none +* Return value : none +* Note : Enable this functions in the bootloader project. This function for bootloader only. +***********************************************************************************************************************/ +void bsp_mcu_clock_reset_bootloader (void) +{ + /* Protect off. */ + SYSTEM.PRCR.WORD = 0xA503; + + /* Is not Clock source LOCO? */ + if(BSP_PRV_SCKCR3_RESET_VALUE != SYSTEM.SCKCR3.WORD) + { + /* Reset clock source. Change to LOCO. */ + SYSTEM.SCKCR3.WORD = BSP_PRV_SCKCR3_RESET_VALUE; + + /* Dummy read and compare. cf."5. I/O Registers", "(2) Notes on writing to I/O registers" in User's manual. + This is done to ensure that the register has been written before the next register access. The RX has a + pipeline architecture so the next instruction could be executed before the previous write had finished. + */ + if(BSP_PRV_SCKCR3_RESET_VALUE == SYSTEM.SCKCR3.WORD) + { + R_BSP_NOP(); + } + } + + /* Is not SCKCR reset value? */ + if(BSP_PRV_SCKCR_RESET_VALUE != SYSTEM.SCKCR.LONG) + { + /* Reset SCKCR register. */ + SYSTEM.SCKCR.LONG = BSP_PRV_SCKCR_RESET_VALUE; + + /* Dummy read and compare. cf."5. I/O Registers", "(2) Notes on writing to I/O registers" in User's manual. + This is done to ensure that the register has been written before the next register access. The RX has a + pipeline architecture so the next instruction could be executed before the previous write had finished. + */ + if(BSP_PRV_SCKCR_RESET_VALUE == SYSTEM.SCKCR.LONG) + { + R_BSP_NOP(); + } + } + +#if BSP_PRV_PLL_CLK_OPERATING == 1 + /* PLL operating? */ + if(BSP_PRV_PLLCR2_RESET_VALUE != SYSTEM.PLLCR2.BYTE) + { + /* Stop PLL. */ + SYSTEM.PLLCR2.BYTE = BSP_PRV_PLLCR2_RESET_VALUE; + + /* WAIT_LOOP */ + while(1 == SYSTEM.OSCOVFSR.BIT.PLOVF) + { + /* The delay period needed is to make sure that the PLL has stabilized. + If you use simulator, the flag is not set to 1, resulting in an infinite loop. */ + R_BSP_NOP(); + } + } + + /* Is not PLLCR reset value? */ + if(BSP_PRV_PLLCR_RESET_VALUE != SYSTEM.PLLCR.WORD) + { + /* Reset PLL. */ + SYSTEM.PLLCR.WORD = BSP_PRV_PLLCR_RESET_VALUE; + } +#endif /* BSP_PRV_PLL_CLK_OPERATING == 1 */ + +#if BSP_CFG_MAIN_CLOCK_OSCILLATE_ENABLE == 1 + /* main clock operating? */ + if(BSP_PRV_MOSCCR_RESET_VALUE != SYSTEM.MOSCCR.BYTE) + { + /* Stop the main clock. */ + SYSTEM.MOSCCR.BYTE = BSP_PRV_MOSCCR_RESET_VALUE; + + /* Dummy read and compare. cf."5. I/O Registers", "(2) Notes on writing to I/O registers" in User's manual. + This is done to ensure that the register has been written before the next register access. The RX has a + pipeline architecture so the next instruction could be executed before the previous write had finished. + */ + if(BSP_PRV_MOSCCR_RESET_VALUE == SYSTEM.MOSCCR.BYTE) + { + R_BSP_NOP(); + } + + /* WAIT_LOOP */ + while(1 == SYSTEM.OSCOVFSR.BIT.MOOVF) + { + /* The delay period needed is to make sure that the Main clock has stabilized. + If you use simulator, the flag is not set to 1, resulting in an infinite loop. */ + R_BSP_NOP(); + } + } + + /* Is not MOSCWTCR reset value? */ + if(BSP_PRV_MOSCWTCR_RESET_VALUE != SYSTEM.MOSCWTCR.BYTE) + { + /* Reset MOSCWTCR */ + SYSTEM.MOSCWTCR.BYTE = BSP_PRV_MOSCWTCR_RESET_VALUE; + + /* Dummy read and compare. cf."5. I/O Registers", "(2) Notes on writing to I/O registers" in User's manual. + This is done to ensure that the register has been written before the next register access. The RX has a + pipeline architecture so the next instruction could be executed before the previous write had finished. + */ + if(BSP_PRV_MOSCWTCR_RESET_VALUE == SYSTEM.MOSCWTCR.BYTE) + { + R_BSP_NOP(); + } + } + + /* Is not MOFCR reset value? */ + if(BSP_PRV_MOFCR_RESET_VALUE != SYSTEM.MOFCR.BYTE) + { + /* Reset MOFCR */ + SYSTEM.MOFCR.BYTE = BSP_PRV_MOFCR_RESET_VALUE; + + /* Dummy read and compare. cf."5. I/O Registers", "(2) Notes on writing to I/O registers" in User's manual. + This is done to ensure that the register has been written before the next register access. The RX has a + pipeline architecture so the next instruction could be executed before the previous write had finished. + */ + if(BSP_PRV_MOFCR_RESET_VALUE == SYSTEM.MOFCR.BYTE) + { + R_BSP_NOP(); + } + } +#endif /* BSP_CFG_MAIN_CLOCK_OSCILLATE_ENABLE == 1 */ + + /* Initialization of other clock-related registers. */ + /* Is not OPCCR reset value? */ + if(BSP_PRV_OPCCR_RESET_VALUE != SYSTEM.OPCCR.BYTE) + { + /* WAIT_LOOP */ + while(1 == SYSTEM.OPCCR.BIT.OPCMTSF) + { + /* Wait for transition to finish. */ + R_BSP_NOP(); + } + + /* Reset OPCCR register. */ + SYSTEM.OPCCR.BYTE = BSP_PRV_OPCCR_RESET_VALUE; + + /* WAIT_LOOP */ + while(1 == SYSTEM.OPCCR.BIT.OPCMTSF) + { + /* Wait for transition to finish. */ + R_BSP_NOP(); + } + } + + /* Protect on. */ + SYSTEM.PRCR.WORD = 0xA500; +} /* End of function bsp_mcu_clock_reset_bootloader() */ +#endif /* BSP_CFG_BOOTLOADER_PROJECT == 1 */ + +#endif /* BSP_CFG_STARTUP_DISABLE == 0 */ + diff --git a/drivers/rx/rdp/src/r_bsp/mcu/rx130/mcu_clocks.h b/drivers/rx/rdp/src/r_bsp/mcu/rx130/mcu_clocks.h new file mode 100644 index 00000000..8a64c561 --- /dev/null +++ b/drivers/rx/rdp/src/r_bsp/mcu/rx130/mcu_clocks.h @@ -0,0 +1,57 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 - 2024 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : mcu_clocks.h +* Description : Contains clock specific routines. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 28.02.2019 1.00 First Release +* : 21.11.2023 1.01 Added definition of bsp_mcu_clock_reset_bootloader function. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef MCU_CLOCKS_H +#define MCU_CLOCKS_H + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ +uint32_t get_iclk_freq_hz(void); +void mcu_clock_setup(void); + +#if BSP_CFG_BOOTLOADER_PROJECT == 1 +/* Enable the following functions in the bootloader project. */ +void bsp_mcu_clock_reset_bootloader(void); +#endif /* BSP_CFG_BOOTLOADER_PROJECT == 1 */ + +/* End of multiple inclusion prevention macro */ +#endif + diff --git a/drivers/rx/rdp/src/r_bsp/mcu/rx130/mcu_info.h b/drivers/rx/rdp/src/r_bsp/mcu/rx130/mcu_info.h new file mode 100644 index 00000000..b7be568c --- /dev/null +++ b/drivers/rx/rdp/src/r_bsp/mcu/rx130/mcu_info.h @@ -0,0 +1,219 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 - 2024 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : mcu_info.h +* Device(s) : RX130 +* Description : Information about the MCU. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 01.12.2015 1.00 First release +* : 01.10.2016 1.01 Added the following macro definition. +* - BSP_LPTSRCCLK_HZ +* : 15.05.2017 1.02 Added the following macro definition. +* - BSP_MCU_RX130_512KB +* - BSP_PACKAGE_LFQFP100 +* - BSP_ILOCO_HZ +* Added the following setting. +* - Setting of 100 pins. +* - Setting of 512-Kbyte ROM capacity. +* - Setting of 384-Kbyte ROM capacity. +* - Setting of 256-Kbyte ROM capacity. +* : 01.11.2017 2.00 Added definition not select clock for LPT clock source. +* : 28.02.2019 3.00 Added macro definition of MCU functions. +* Added the following macro definition. +* - BSP_MCU_CPU_VERSION +* - CPU_CYCLES_PER_LOOP +* Fixed coding style. +* : 30.11.2021 3.01 Deleted the compile switch for BSP_CFG_MCU_PART_SERIES and BSP_CFG_MCU_PART_GROUP. +* : 22.04.2022 3.02 Added version check of smart configurator. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +/* Gets MCU configuration information. */ +#include "r_bsp_config.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef MCU_INFO +#define MCU_INFO + +#if BSP_CFG_CONFIGURATOR_VERSION < 2120 + /* The following macros are updated to invalid value by Smart configurator if you are using Smart Configurator for + RX V2.11.0 (equivalent to e2 studio 2021-10) or earlier version. + - BSP_CFG_MCU_PART_GROUP, BSP_CFG_MCU_PART_SERIES + The following macros are not updated by Smart configurator if you are using Smart Configurator for RX V2.11.0 + (equivalent to e2 studio 2021-10) or earlier version. + - BSP_CFG_MAIN_CLOCK_OSCILLATE_ENABLE, BSP_CFG_HOCO_OSCILLATE_ENABLE, BSP_CFG_LOCO_OSCILLATE_ENABLE, + BSP_CFG_IWDT_CLOCK_OSCILLATE_ENABLE, BSP_CFG_CPLUSPLUS + Please update Smart configurator to Smart Configurator for RX V2.12.0 (equivalent to e2 studio 2022-01) or + later version. + */ + #error "To use this version of BSP, you need to upgrade Smart configurator. Please upgrade Smart configurator. If you don't use Smart Configurator, please change value of BSP_CFG_CONFIGURATOR_VERSION in r_bsp_config.h." +#endif + +/* MCU CPU Version */ +#define BSP_MCU_CPU_VERSION (1) + +/* CPU cycles. Known number of RXv1 CPU cycles required to execute the delay_wait() loop */ +#define CPU_CYCLES_PER_LOOP (5) + +/* MCU Series. */ +#define BSP_MCU_SERIES_RX100 (1) + +/* This macro means that this MCU is part of the RX13x collection of MCUs (i.e. RX130). */ +#define BSP_MCU_RX13_ALL (1) + +/* MCU Group name. */ +#define BSP_MCU_RX130 (1) +#if (BSP_CFG_MCU_PART_MEMORY_SIZE == 0x6) || (BSP_CFG_MCU_PART_MEMORY_SIZE == 0x7) || \ + (BSP_CFG_MCU_PART_MEMORY_SIZE == 0x8) || (BSP_CFG_MCU_PART_PACKAGE == 0x5) + #define BSP_MCU_RX130_512KB (1) +#endif + +/* Package. */ +#if BSP_CFG_MCU_PART_PACKAGE == 0x5 + #define BSP_PACKAGE_LFQFP100 (1) + #define BSP_PACKAGE_PINS (100) +#elif BSP_CFG_MCU_PART_PACKAGE == 0xB + #define BSP_PACKAGE_LFQFP80 (1) + #define BSP_PACKAGE_PINS (80) +#elif BSP_CFG_MCU_PART_PACKAGE == 0x0 + #define BSP_PACKAGE_LFQFP64 (1) + #define BSP_PACKAGE_PINS (64) +#elif BSP_CFG_MCU_PART_PACKAGE == 0x1 + #define BSP_PACKAGE_LQFP64 (1) + #define BSP_PACKAGE_PINS (64) +#elif BSP_CFG_MCU_PART_PACKAGE == 0x3 + #define BSP_PACKAGE_LFQFP48 (1) + #define BSP_PACKAGE_PINS (48) +#elif BSP_CFG_MCU_PART_PACKAGE == 0x4 + #define BSP_PACKAGE_HWQFN48 (1) + #define BSP_PACKAGE_PINS (48) +#else + #error "ERROR - BSP_CFG_MCU_PART_PACKAGE - Unknown package chosen in r_bsp_config.h" +#endif + +/* Memory size of your MCU. */ +#if BSP_CFG_MCU_PART_MEMORY_SIZE == 0x3 + #define BSP_ROM_SIZE_BYTES (65536L) + #define BSP_RAM_SIZE_BYTES (10240) + #define BSP_DATA_FLASH_SIZE_BYTES (8192) +#elif BSP_CFG_MCU_PART_MEMORY_SIZE == 0x5 + #define BSP_ROM_SIZE_BYTES (131072L) + #define BSP_RAM_SIZE_BYTES (16384) + #define BSP_DATA_FLASH_SIZE_BYTES (8192) +#elif BSP_CFG_MCU_PART_MEMORY_SIZE == 0x6 + #define BSP_ROM_SIZE_BYTES (262144L) + #define BSP_RAM_SIZE_BYTES (32768) + #define BSP_DATA_FLASH_SIZE_BYTES (8192) +#elif BSP_CFG_MCU_PART_MEMORY_SIZE == 0x7 + #define BSP_ROM_SIZE_BYTES (393216L) + #define BSP_RAM_SIZE_BYTES (49152) + #define BSP_DATA_FLASH_SIZE_BYTES (8192) +#elif BSP_CFG_MCU_PART_MEMORY_SIZE == 0x8 + #define BSP_ROM_SIZE_BYTES (524288L) + #define BSP_RAM_SIZE_BYTES (49152) + #define BSP_DATA_FLASH_SIZE_BYTES (8192) +#else + #error "ERROR - BSP_CFG_MCU_PART_MEMORY_SIZE - Unknown memory size chosen in r_bsp_config.h" +#endif + +/* These macros define clock speeds for fixed speed clocks. */ +#define BSP_LOCO_HZ (4000000) +#define BSP_HOCO_HZ (32000000) +#define BSP_SUB_CLOCK_HZ (32768) +#define BSP_ILOCO_HZ (15000) + +/* Clock source select (CKSEL). + 0 = Low Speed On-Chip Oscillator (LOCO) + 1 = High Speed On-Chip Oscillator (HOCO) + 2 = Main Clock Oscillator + 3 = Sub-Clock Oscillator + 4 = PLL Circuit +*/ +#if BSP_CFG_CLOCK_SOURCE == 0 + #define BSP_SELECTED_CLOCK_HZ (BSP_LOCO_HZ) +#elif BSP_CFG_CLOCK_SOURCE == 1 + #define BSP_SELECTED_CLOCK_HZ (BSP_HOCO_HZ) +#elif BSP_CFG_CLOCK_SOURCE == 2 + #define BSP_SELECTED_CLOCK_HZ (BSP_CFG_XTAL_HZ) +#elif BSP_CFG_CLOCK_SOURCE == 3 + #define BSP_SELECTED_CLOCK_HZ (BSP_SUB_CLOCK_HZ) +#elif BSP_CFG_CLOCK_SOURCE == 4 + #define BSP_SELECTED_CLOCK_HZ ((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) +#else + #error "ERROR - BSP_CFG_CLOCK_SOURCE - Unknown clock source chosen in r_bsp_config.h" +#endif + +/* LPT clock speed in Hz */ +#if BSP_CFG_LPT_CLOCK_SOURCE == 0 + #define BSP_LPTSRCCLK_HZ (BSP_SUB_CLOCK_HZ) +#elif BSP_CFG_LPT_CLOCK_SOURCE == 1 + #define BSP_LPTSRCCLK_HZ (BSP_ILOCO_HZ) /* IWDTCLK typical frequency */ +#elif BSP_CFG_LPT_CLOCK_SOURCE == 2 + /* LPT none use */ +#else + #error "ERROR - BSP_CFG_LPT_CLOCK_SOURCE - Unknown lpt clock source chosen in r_bsp_config.h" +#endif + +/* System clock speed in Hz. */ +#define BSP_ICLK_HZ (BSP_SELECTED_CLOCK_HZ / BSP_CFG_ICK_DIV) +/* Peripheral Module Clock B speed in Hz. */ +#define BSP_PCLKB_HZ (BSP_SELECTED_CLOCK_HZ / BSP_CFG_PCKB_DIV) +/* Peripheral Module Clock D speed in Hz. */ +#define BSP_PCLKD_HZ (BSP_SELECTED_CLOCK_HZ / BSP_CFG_PCKD_DIV) +/* FlashIF clock speed in Hz. */ +#define BSP_FCLK_HZ (BSP_SELECTED_CLOCK_HZ / BSP_CFG_FCK_DIV) + +/* Null argument definitions. */ +#define FIT_NO_FUNC ((void (*)(void *))0x10000000) /* Reserved space on RX */ +#define FIT_NO_PTR ((void *)0x10000000) /* Reserved space on RX */ + +/* Mininum and maximum IPL levels available for this MCU. */ +#define BSP_MCU_IPL_MAX (0xF) +#define BSP_MCU_IPL_MIN (0) + +/* Maximum frequency on Middle-speed operating mode. */ +#define BSP_MIDDLE_SPEED_MAX_FREQUENCY (12000000) + +/* MCU functions */ +#define BSP_MCU_REGISTER_WRITE_PROTECTION +#define BSP_MCU_RCPC_PRC0 +#define BSP_MCU_RCPC_PRC1 +#define BSP_MCU_RCPC_PRC2 +#define BSP_MCU_RCPC_PRC3 +#define BSP_MCU_EXCEP_SUPERVISOR_INST_ISR +#define BSP_MCU_EXCEP_UNDEFINED_INST_ISR +#define BSP_MCU_NON_MASKABLE_ISR +#define BSP_MCU_UNDEFINED_INTERRUPT_SOURCE_ISR +#define BSP_MCU_BUS_ERROR_ISR + +#define BSP_MCU_NMI_EXC_NMI_PIN +#define BSP_MCU_NMI_OSC_STOP_DETECT +#define BSP_MCU_NMI_IWDT_ERROR +#define BSP_MCU_NMI_LVD1 +#define BSP_MCU_NMI_LVD2 + +#endif /* MCU_INFO */ + diff --git a/drivers/rx/rdp/src/r_bsp/mcu/rx130/mcu_init.c b/drivers/rx/rdp/src/r_bsp/mcu/rx130/mcu_init.c new file mode 100644 index 00000000..5002caf2 --- /dev/null +++ b/drivers/rx/rdp/src/r_bsp/mcu/rx130/mcu_init.c @@ -0,0 +1,168 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 - 2024 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : mcu_init.c +* Description : Performs initialization common to all MCUs in this Group +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 01.12.2015 1.00 First Release +* : 15.05.2017 1.01 Added port setting of 100 pins. +* : 28.02.2019 1.02 Fixed coding style. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +/* Get specifics on this MCU. */ +#include "platform.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* RX MCUs come in different packages and different pin counts. For MCUs that do not have the maximum number of pins + * for their group (e.g. MCU with 100 pins when maximum is 144 pins) these 'non-existent' pins that are not bonded out + * need to be initialized to save power. The macros below define the non-existent pins on each port for smaller + * pin count MCUs. If a pin is non-existent then its value is set to a 1. These values are then ORed into the + * direction registers to set non-existent pins as outputs which can help save power. + */ +#if BSP_PACKAGE_PINS == 100 + #define BSP_PRV_PORT0_NE_PIN_MASK (0x07) /* Missing pins: P00 P01 P02 */ + #define BSP_PRV_PORT1_NE_PIN_MASK (0x03) /* Missing pins: P10 P11 */ + #define BSP_PRV_PORT2_NE_PIN_MASK (0x00) /* Missing pins: None */ + #define BSP_PRV_PORT3_NE_PIN_MASK (0x00) /* Missing pins: None */ + #define BSP_PRV_PORT4_NE_PIN_MASK (0x00) /* Missing pins: None */ + #define BSP_PRV_PORT5_NE_PIN_MASK (0xC0) /* Missing pins: P56 P57 */ + #define BSP_PRV_PORTA_NE_PIN_MASK (0x00) /* Missing pins: None */ + #define BSP_PRV_PORTB_NE_PIN_MASK (0x00) /* Missing pins: None */ + #define BSP_PRV_PORTC_NE_PIN_MASK (0x00) /* Missing pins: None */ + #define BSP_PRV_PORTD_NE_PIN_MASK (0x00) /* Missing pins: None */ + #define BSP_PRV_PORTE_NE_PIN_MASK (0x00) /* Missing pins: None */ + #define BSP_PRV_PORTH_NE_PIN_MASK (0xF0) /* Missing pins: PH4 PH5 PH6 PH7 */ + #define BSP_PRV_PORTJ_NE_PIN_MASK (0x35) /* Missing pins: PJ0 PJ2 PJ4 PJ5 */ +#elif BSP_PACKAGE_PINS == 80 + #define BSP_PRV_PORT0_NE_PIN_MASK (0x07) /* Missing pins: P00 P01 P02 */ + #define BSP_PRV_PORT1_NE_PIN_MASK (0x03) /* Missing pins: P10 P11 */ + #define BSP_PRV_PORT2_NE_PIN_MASK (0x3C) /* Missing pins: P22 P23 P24 P25 */ + #define BSP_PRV_PORT3_NE_PIN_MASK (0x08) /* Missing pins: P33 */ + #define BSP_PRV_PORT4_NE_PIN_MASK (0x00) /* Missing pins: None */ + #define BSP_PRV_PORT5_NE_PIN_MASK (0xCF) /* Missing pins: P50 P51 P52 P53 P56 P57 */ + #define BSP_PRV_PORTA_NE_PIN_MASK (0x80) /* Missing pins: PA7 */ + #define BSP_PRV_PORTB_NE_PIN_MASK (0x00) /* Missing pins: None */ + #define BSP_PRV_PORTC_NE_PIN_MASK (0x03) /* Missing pins: PC0 PC1 */ + #define BSP_PRV_PORTD_NE_PIN_MASK (0xF8) /* Missing pins: PD3 PD4 PD5 PD6 PD7 */ + #define BSP_PRV_PORTE_NE_PIN_MASK (0xC0) /* Missing pins: PE6 PE7 */ + #define BSP_PRV_PORTH_NE_PIN_MASK (0xF0) /* Missing pins: PH4 PH5 PH6 PH7 */ + #define BSP_PRV_PORTJ_NE_PIN_MASK (0x3D) /* Missing pins: PJ0 PJ2 PJ3 PJ4 PJ5 */ +#elif BSP_PACKAGE_PINS == 64 + #define BSP_PRV_PORT0_NE_PIN_MASK (0xD7) /* Missing pins: P00 P01 P02 P04 P06 P07 */ + #define BSP_PRV_PORT1_NE_PIN_MASK (0x0F) /* Missing pins: P10 P11 P12 P13 */ + #define BSP_PRV_PORT2_NE_PIN_MASK (0x3F) /* Missing pins: P20 P21 P22 P23 P24 P25 */ + #define BSP_PRV_PORT3_NE_PIN_MASK (0x18) /* Missing pins: P33 P34 */ + #define BSP_PRV_PORT4_NE_PIN_MASK (0x00) /* Missing pins: None */ + #define BSP_PRV_PORT5_NE_PIN_MASK (0xCF) /* Missing pins: P50 P51 P52 P53 P56 P57 */ + #define BSP_PRV_PORTA_NE_PIN_MASK (0xA4) /* Missing pins: PA2 PA5 PA7 */ + #define BSP_PRV_PORTB_NE_PIN_MASK (0x14) /* Missing pins: PB2 PB4 */ + #define BSP_PRV_PORTC_NE_PIN_MASK (0x03) /* Missing pins: PC0 PC1 */ + #define BSP_PRV_PORTD_NE_PIN_MASK (0xFF) /* Missing pins: PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 */ + #define BSP_PRV_PORTE_NE_PIN_MASK (0xC0) /* Missing pins: PE6 PE7 */ + #define BSP_PRV_PORTH_NE_PIN_MASK (0xF0) /* Missing pins: PH4 PH5 PH6 PH7 */ + #define BSP_PRV_PORTJ_NE_PIN_MASK (0x3F) /* Missing pins: PJ0 PJ1 PJ2 PJ3 PJ4 PJ5 */ +#elif BSP_PACKAGE_PINS == 48 + #define BSP_PRV_PORT0_NE_PIN_MASK (0xFF) /* Missing pins: P00 P01 P02 P03 P04 P05 P06 P07 */ + #define BSP_PRV_PORT1_NE_PIN_MASK (0x0F) /* Missing pins: P10 P11 P12 P13 */ + #define BSP_PRV_PORT2_NE_PIN_MASK (0x3F) /* Missing pins: P20 P21 P22 P23 P24 P25 */ + #define BSP_PRV_PORT3_NE_PIN_MASK (0x1C) /* Missing pins: P32 P33 P34 */ + #define BSP_PRV_PORT4_NE_PIN_MASK (0x18) /* Missing pins: P43 P44 */ + #define BSP_PRV_PORT5_NE_PIN_MASK (0xFF) /* Missing pins: P50 P51 P52 P53 P54 P55 P56 P57 */ + #define BSP_PRV_PORTA_NE_PIN_MASK (0xA5) /* Missing pins: PA0 PA2 PA5 PA7 */ + #define BSP_PRV_PORTB_NE_PIN_MASK (0xD4) /* Missing pins: PB2 PB4 PB6 PB7 */ + #define BSP_PRV_PORTC_NE_PIN_MASK (0x0F) /* Missing pins: PC0 PC1 PC2 PC3 */ + #define BSP_PRV_PORTD_NE_PIN_MASK (0xFF) /* Missing pins: PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 */ + #define BSP_PRV_PORTE_NE_PIN_MASK (0xE1) /* Missing pins: PE0 PE5 PE6 PE7 */ + #define BSP_PRV_PORTH_NE_PIN_MASK (0xF0) /* Missing pins: PH4 PH5 PH6 PH7 */ + #define BSP_PRV_PORTJ_NE_PIN_MASK (0x3F) /* Missing pins: PJ0 PJ1 PJ2 PJ3 PJ4 PJ5 */ +#else + #error "ERROR - This package is not defined in mcu_init.c" +#endif + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* Function Name: bsp_non_existent_port_init +* Description : For MCUs that do not have the 'non-existent' pins for their group (e.g. MCU with 100 pins when +* maximum is 144 pins) these 'non-existent' pins that are not bonded out need to be initialized to save +* power. +* Arguments : none +* Return Value : none +***********************************************************************************************************************/ +void bsp_non_existent_port_init (void) +{ + /* OR in missing pin masks from above. */ + + /* Set PORT0.PDR */ + PORT0.PDR.BYTE |= BSP_PRV_PORT0_NE_PIN_MASK; + + /* Set PORT1.PDR */ + PORT1.PDR.BYTE |= BSP_PRV_PORT1_NE_PIN_MASK; + + /* Set PORT2.PDR */ + PORT2.PDR.BYTE |= BSP_PRV_PORT2_NE_PIN_MASK; + + /* Set PORT3.PDR */ + PORT3.PDR.BYTE |= BSP_PRV_PORT3_NE_PIN_MASK; + + /* Set PORT4.PDR */ + PORT4.PDR.BYTE |= BSP_PRV_PORT4_NE_PIN_MASK; + + /* Set PORT5.PDR */ + PORT5.PDR.BYTE |= BSP_PRV_PORT5_NE_PIN_MASK; + + /* Set PORTA.PDR */ + PORTA.PDR.BYTE |= BSP_PRV_PORTA_NE_PIN_MASK; + + /* Set PORTB.PDR */ + PORTB.PDR.BYTE |= BSP_PRV_PORTB_NE_PIN_MASK; + + /* Set PORTC.PDR */ + PORTC.PDR.BYTE |= BSP_PRV_PORTC_NE_PIN_MASK; + + /* Set PORTD.PDR */ + PORTD.PDR.BYTE |= BSP_PRV_PORTD_NE_PIN_MASK; + + /* Set PORTE.PDR */ + PORTE.PDR.BYTE |= BSP_PRV_PORTE_NE_PIN_MASK; + + /* Set PORTH.PDR */ + PORTH.PDR.BYTE |= BSP_PRV_PORTH_NE_PIN_MASK; + + /* Set PORTJ.PDR */ + PORTJ.PDR.BYTE |= BSP_PRV_PORTJ_NE_PIN_MASK; +} /* End of function bsp_non_existent_port_init() */ + diff --git a/drivers/rx/rdp/src/r_bsp/mcu/rx130/mcu_init.h b/drivers/rx/rdp/src/r_bsp/mcu/rx130/mcu_init.h new file mode 100644 index 00000000..85b9f086 --- /dev/null +++ b/drivers/rx/rdp/src/r_bsp/mcu/rx130/mcu_init.h @@ -0,0 +1,50 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 - 2024 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : mcu_init.h +* Description : Performs initialization common to all MCUs in this Group +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 01.12.2015 1.00 First release +* : 28.02.2019 1.01 Fixed coding style. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef MCU_INIT_H +#define MCU_INIT_H + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ +void bsp_non_existent_port_init(void); //r_bsp internal function. DO NOT CALL. + +#endif /* MCU_INIT_H */ + diff --git a/drivers/rx/rdp/src/r_bsp/mcu/rx130/mcu_interrupts.c b/drivers/rx/rdp/src/r_bsp/mcu/rx130/mcu_interrupts.c new file mode 100644 index 00000000..26d1eab6 --- /dev/null +++ b/drivers/rx/rdp/src/r_bsp/mcu/rx130/mcu_interrupts.c @@ -0,0 +1,207 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 - 2024 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : mcu_interrupts.c +* Description : This module is the control of the interrupt enable. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 01.12.2015 1.00 First Release +* : 15.05.2017 1.01 Added the following setting to bsp_int_err_t bsp_interrupt_enable_disable function. +* - BSC.BEREN.BIT.TOEN. +* : 27.07.2018 1.02 Added the comment to for statement. +* : 28.02.2019 2.00 Deleted the following functions. +* (The following functions moved to the common file (r_bsp_interrupts.c).) +* - bsp_interrupt_open +* - R_BSP_InterruptWrite +* - R_BSP_InterruptRead +* - R_BSP_InterruptControl +* Deleted the following definition. +* (The following definition moved to the common file (r_bsp_common.h).) +* - INTERNAL_NOT_USED(p) +* Replaced the setting of IEN bit. +* Fixed coding style. +* : 21.11.2023 2.01 Added timeout detection processing to bus error processing. +* Added processing to control only illegal address access detection to bus error +* processing. +* Added processing to control only timeout detection to bus error processing. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +/* Access to r_bsp. */ +#include "platform.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* Function Name: bsp_interrupt_enable_disable +* Description : Either enables or disables an interrupt. +* Arguments : vector - +* Which vector to enable or disable. +* enable - +* Whether to enable or disable the interrupt. +* Return Value : BSP_INT_SUCCESS - +* Interrupt enabled or disabled. +* BSP_INT_ERR_UNSUPPORTED - +* API does not support enabling/disabling for this vector. +***********************************************************************************************************************/ +bsp_int_err_t bsp_interrupt_enable_disable (bsp_int_src_t vector, bool enable) +{ + bsp_int_err_t err = BSP_INT_SUCCESS; + + switch (vector) + { + case (BSP_INT_SRC_BUS_ERROR): + if (true == enable) + { + /* Enable the bus error interrupt to catch accesses to illegal/reserved areas of memory */ + /* Clear any pending interrupts */ + IR(BSC,BUSERR) = 0; + + /* Make this the highest priority interrupt (adjust as necessary for your application */ + IPR(BSC,BUSERR) = 0x0F; + + /* Enable the interrupt in the ICU*/ + R_BSP_InterruptRequestEnable(VECT(BSC,BUSERR)); + + /* Enable illegal address interrupt in the BSC */ + BSC.BEREN.BIT.IGAEN = 1; + + /* Enable timeout detection enable. */ + BSC.BEREN.BIT.TOEN = 1; + } + else + { + /* Disable the bus error interrupt. */ + /* Disable the interrupt in the ICU*/ + R_BSP_InterruptRequestDisable(VECT(BSC,BUSERR)); + + /* Disable illegal address interrupt in the BSC */ + BSC.BEREN.BIT.IGAEN = 0; + + /* Disable timeout detection enable. */ + BSC.BEREN.BIT.TOEN = 0; + } + break; + + case (BSP_INT_SRC_BUS_ERROR_ILLEGAL_ACCESS): + if (true == enable) + { + /* Check the bus error monitoring status. */ + if (0 == BSC.BEREN.BYTE) + { + /* Enable the bus error interrupt to catch accesses to illegal/reserved areas of memory */ + /* Clear any pending interrupts */ + IR(BSC,BUSERR) = 0; + + /* Make this the highest priority interrupt (adjust as necessary for your application */ + IPR(BSC,BUSERR) = 0x0F; + + /* Enable the interrupt in the ICU. */ + R_BSP_InterruptRequestEnable(VECT(BSC,BUSERR)); + } + + /* Enable illegal address interrupt in the BSC */ + BSC.BEREN.BIT.IGAEN = 1; + } + else + { + /* Disable illegal address interrupt in the BSC */ + BSC.BEREN.BIT.IGAEN = 0; + + /* Check the bus error monitoring status. */ + if (0 == BSC.BEREN.BYTE) + { + /* Disable the bus error interrupt in the ICU. */ + R_BSP_InterruptRequestDisable(VECT(BSC,BUSERR)); + } + } + break; + + case (BSP_INT_SRC_BUS_ERROR_TIMEOUT): + if (true == enable) + { + /* Check the bus error monitoring status. */ + if (0 == BSC.BEREN.BYTE) + { + /* Enable the bus error interrupt to catch accesses to illegal/reserved areas of memory */ + /* Clear any pending interrupts */ + IR(BSC,BUSERR) = 0; + + /* Make this the highest priority interrupt (adjust as necessary for your application */ + IPR(BSC,BUSERR) = 0x0F; + + /* Enable the interrupt in the ICU. */ + R_BSP_InterruptRequestEnable(VECT(BSC,BUSERR)); + } + + /* Enable timeout detection enable. */ + BSC.BEREN.BIT.TOEN = 1; + } + else + { + /* Disable timeout detection enable. */ + BSC.BEREN.BIT.TOEN = 0; + + /* Check the bus error monitoring status. */ + if (0 == BSC.BEREN.BYTE) + { + /* Disable the bus error interrupt in the ICU. */ + R_BSP_InterruptRequestDisable(VECT(BSC,BUSERR)); + } + } + break; + + case (BSP_INT_SRC_EXC_NMI_PIN): + if (true == enable) + { + /* Enable NMI pin interrupt (cannot undo!) */ + ICU.NMIER.BIT.NMIEN = 1; + } + else + { + /* NMI pin interrupts cannot be disabled after being enabled. */ + err = BSP_INT_ERR_UNSUPPORTED; + } + break; + + default: + err = BSP_INT_ERR_UNSUPPORTED; + break; + } + + return err; +} /* End of function bsp_interrupt_enable_disable() */ + diff --git a/drivers/rx/rdp/src/r_bsp/mcu/rx130/mcu_interrupts.h b/drivers/rx/rdp/src/r_bsp/mcu/rx130/mcu_interrupts.h new file mode 100644 index 00000000..9c62931e --- /dev/null +++ b/drivers/rx/rdp/src/r_bsp/mcu/rx130/mcu_interrupts.h @@ -0,0 +1,129 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 - 2024 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : mcu_interrupts.h +* Description : This module is the control of the interrupt enable. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 01.12.2015 1.00 First Release +* : 28.02.2019 2.00 Added the following prototype declaration. +* - bsp_interrupt_enable_disable +* Deleted the following prototype declarations. +* (The following prototype declarations moved to the common file (r_bsp_interrupts.h).) +* - bsp_interrupt_open +* - R_BSP_InterruptWrite +* - R_BSP_InterruptRead +* - R_BSP_InterruptControl +* Fixed coding style. +* : 26.07.2019 2.10 Added the following command. +* - BSP_INT_CMD_FIT_INTERRUPT_ENABLE +* - BSP_INT_CMD_FIT_INTERRUPT_DISABLE +* Added the following error code. +* - BSP_INT_ERR_INVALID_IPL +* Added union of bsp_int_ctrl_t. +* Added the following enumeration constant. +* - BSP_INT_SRC_EMPTY +* : 21.11.2023 2.11 Added the following enumeration constant. +* - BSP_INT_SRC_BUS_ERROR_ILLEGAL_ACCESS +* - BSP_INT_SRC_BUS_ERROR_TIMEOUT +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef MCU_INTERRUPTS_H +#define MCU_INTERRUPTS_H + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ +/* Available return codes. */ +typedef enum +{ + BSP_INT_SUCCESS = 0, + BSP_INT_ERR_NO_REGISTERED_CALLBACK, /* There is not a registered callback for this interrupt source */ + BSP_INT_ERR_INVALID_ARG, /* Illegal argument input */ + BSP_INT_ERR_UNSUPPORTED, /* Operation is not supported by this API */ + BSP_INT_ERR_INVALID_IPL /* Illegal IPL value input */ +} bsp_int_err_t; + +/* Available interrupts to register a callback for. */ +typedef enum +{ + BSP_INT_SRC_EXC_SUPERVISOR_INSTR = 0, /* Occurs when privileged instruction is executed in User Mode */ + BSP_INT_SRC_EXC_UNDEFINED_INSTR, /* Occurs when MCU encounters an unknown instruction */ + BSP_INT_SRC_EXC_NMI_PIN, /* NMI Pin interrupt */ + BSP_INT_SRC_OSC_STOP_DETECT, /* Oscillation stop is detected */ + BSP_INT_SRC_IWDT_ERROR, /* IWDT underflow/refresh error has occurred */ + BSP_INT_SRC_LVD1, /* Voltage monitoring 1 interrupt */ + BSP_INT_SRC_LVD2, /* Voltage monitoring 2 interrupt */ + BSP_INT_SRC_UNDEFINED_INTERRUPT, /* Interrupt has triggered for a vector that user did not write a handler. */ + BSP_INT_SRC_BUS_ERROR, /* Bus error: illegal address access or timeout */ + BSP_INT_SRC_BUS_ERROR_ILLEGAL_ACCESS, /* Bus error: illegal address access. Use this when you want to set only Illegal address access detection. */ + BSP_INT_SRC_BUS_ERROR_TIMEOUT, /* Bus error: timeout. Use this when you want to set only Bus timeout detection. */ + BSP_INT_SRC_EMPTY, + BSP_INT_SRC_TOTAL_ITEMS /* DO NOT MODIFY! This is used for sizing the interrupt callback array. */ +} bsp_int_src_t; + +/* Available commands for R_BSP_InterruptControl() function. */ +typedef enum +{ + BSP_INT_CMD_CALL_CALLBACK = 0, /* Calls registered callback function if one exists */ + BSP_INT_CMD_INTERRUPT_ENABLE, /* Enables a given interrupt (Available for NMI pin and Bus Error) */ + BSP_INT_CMD_INTERRUPT_DISABLE, /* Disables a given interrupt (Available for Bus Error) */ + BSP_INT_CMD_FIT_INTERRUPT_ENABLE, /* Enables interrupt by control of IPL. */ + BSP_INT_CMD_FIT_INTERRUPT_DISABLE /* Disables interrupt by control of IPL. */ +} bsp_int_cmd_t; + +/* Type to be used for pdata argument in Control function. */ +typedef union +{ + uint32_t ipl; /* Used at the following times. + - When enabling an interrupt to set that interrupt's priority level + by BSP_INT_CMD_GROUP_INTERRUPT_ENABLE command. + - When disabling an interrupt to save that interrupt's priority level + by BSP_INT_CMD_FIT_INTERRUPT_DISABLE command. + - When enabling an interrupt to set that interrupt's priority level + by BSP_INT_CMD_FIT_INTERRUPT_ENABLE command. */ +} bsp_int_ctrl_t; + +/* Easy to use typedef for callback functions. */ +typedef void (*bsp_int_cb_t)(void *); + +/* This structure is the common one that is passed as the 'void *' argument to callback functions when an + * exception occurs. + */ +typedef struct +{ + bsp_int_src_t vector; /* Which vector caused this interrupt */ +} bsp_int_cb_args_t; + +/*********************************************************************************************************************** +Exported global variables +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ +bsp_int_err_t bsp_interrupt_enable_disable(bsp_int_src_t vector, bool enable); + +#endif /* MCU_INTERRUPTS_H */ + diff --git a/drivers/rx/rdp/src/r_bsp/mcu/rx130/register_access/gnuc/iodefine.h b/drivers/rx/rdp/src/r_bsp/mcu/rx130/register_access/gnuc/iodefine.h new file mode 100644 index 00000000..b821eeb0 --- /dev/null +++ b/drivers/rx/rdp/src/r_bsp/mcu/rx130/register_access/gnuc/iodefine.h @@ -0,0 +1,11700 @@ +/********************************************************************************************************************** + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No + * other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all + * applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM + * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES + * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO + * THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of + * this software. By using this software, you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * + * Copyright (C) 2020 - 2024 Renesas Electronics Corporation. All rights reserved. + *********************************************************************************************************************/ +/********************************************************************************* +* +* Device : RX/RX100/RX130 +* +* File Name : iodefine.h +* +* Abstract : Definition of I/O Register. +* +* History : 0.5 (2015-06-30) [Hardware Manual Revision : 0.50] +* : 1.0 (2015-10-05) [Hardware Manual Revision : 1.00] +* : 2.0 (2017-04-17) [Hardware Manual Revision : 2.00] +* : 2.0A (2023-03-03) [Hardware Manual Revision : 2.00] +* +* NOTE : THIS IS A TYPICAL EXAMPLE. +* +* Copyright (C) 2023 (2015 - 2017) Renesas Electronics Corporation. +* +*********************************************************************************/ +/********************************************************************************/ +/* */ +/* DESCRIPTION : Definition of ICU Register */ +/* CPU TYPE : RX130 */ +/* */ +/* Usage : IR,DTCER,IER,IPR of ICU Register */ +/* The following IR, DTCE, IEN, IPR macro functions simplify usage. */ +/* The bit access operation is "Bit_Name(interrupt source,name)". */ +/* A part of the name can be omitted. */ +/* for example : */ +/* IR(MTU0,TGIA0) = 0; expands to : */ +/* ICU.IR[114].BIT.IR = 0; */ +/* */ +/* DTCE(ICU,IRQ0) = 1; expands to : */ +/* ICU.DTCER[64].BIT.DTCE = 1; */ +/* */ +/* IEN(CMT0,CMI0) = 1; expands to : */ +/* ICU.IER[0x03].BIT.IEN4 = 1; */ +/* */ +/* IPR(MTU1,TGIA1) = 2; expands to : */ +/* IPR(MTU1,TGI ) = 2; // TGIA1,TGIB1 share IPR level. */ +/* ICU.IPR[121].BIT.IPR = 2; */ +/* */ +/* IPR(SCI0,ERI0) = 3; expands to : */ +/* IPR(SCI0, ) = 3; // SCI0 uses single IPR for all sources. */ +/* ICU.IPR[214].BIT.IPR = 3; */ +/* */ +/* Usage : #pragma interrupt Function_Identifier(vect=**) */ +/* The number of vector is "(interrupt source, name)". */ +/* for example : */ +/* #pragma interrupt INT_IRQ0(vect=VECT(ICU,IRQ0)) expands to : */ +/* #pragma interrupt INT_IRQ0(vect=64) */ +/* #pragma interrupt INT_CMT0_CMI0(vect=VECT(CMT0,CMI0)) expands to : */ +/* #pragma interrupt INT_CMT0_CMI0(vect=28) */ +/* #pragma interrupt INT_MTU0_TGIA0(vect=VECT(MTU0,TGIA0)) expands to : */ +/* #pragma interrupt INT_MTU0_TGIA0(vect=114) */ +/* */ +/* Usage : MSTPCRA,MSTPCRB,MSTPCRC of SYSTEM Register */ +/* The bit access operation is "MSTP(name)". */ +/* The name that can be used is a macro name defined with "iodefine.h". */ +/* for example : */ +/* MSTP(TMR2) = 0; // TMR2,TMR3,TMR23 expands to : */ +/* SYSTEM.MSTPCRA.BIT.MSTPA4 = 0; */ +/* MSTP(SCI0) = 0; // SCI0,SMCI0 expands to : */ +/* SYSTEM.MSTPCRB.BIT.MSTPB31 = 0; */ +/* MSTP(MTU4) = 0; // MTU,MTU0,MTU1,MTU2,MTU3,MTU4,MTU5 expands to : */ +/* SYSTEM.MSTPCRA.BIT.MSTPA9 = 0; */ +/* */ +/* */ +/********************************************************************************/ +#ifndef __RX130IODEFINE_HEADER__ +#define __RX130IODEFINE_HEADER__ + +#pragma pack(4) + +struct st_bsc { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char STSCLR : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char STSCLR : 1; +#endif + } BIT; + } BERCLR; + char wk0[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IGAEN : 1; + unsigned char TOEN : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char TOEN : 1; + unsigned char IGAEN : 1; +#endif + } BIT; + } BEREN; + char wk1[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IA : 1; + unsigned char TO : 1; + unsigned char : 2; + unsigned char MST : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char MST : 3; + unsigned char : 2; + unsigned char TO : 1; + unsigned char IA : 1; +#endif + } BIT; + } BERSR1; + char wk2[1]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 3; + unsigned short ADDR : 13; +#else + unsigned short ADDR : 13; + unsigned short : 3; +#endif + } BIT; + } BERSR2; + char wk3[4]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short BPRA : 2; + unsigned short BPRO : 2; + unsigned short BPIB : 2; + unsigned short BPGB : 2; + unsigned short : 2; + unsigned short BPFB : 2; + unsigned short : 4; +#else + unsigned short : 4; + unsigned short BPFB : 2; + unsigned short : 2; + unsigned short BPGB : 2; + unsigned short BPIB : 2; + unsigned short BPRO : 2; + unsigned short BPRA : 2; +#endif + } BIT; + } BUSPRI; +}; + +struct st_cac { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CFME : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char CFME : 1; +#endif + } BIT; + } CACR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CACREFE : 1; + unsigned char FMCS : 3; + unsigned char TCSS : 2; + unsigned char EDGES : 2; +#else + unsigned char EDGES : 2; + unsigned char TCSS : 2; + unsigned char FMCS : 3; + unsigned char CACREFE : 1; +#endif + } BIT; + } CACR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char RPS : 1; + unsigned char RSCS : 3; + unsigned char RCDS : 2; + unsigned char DFS : 2; +#else + unsigned char DFS : 2; + unsigned char RCDS : 2; + unsigned char RSCS : 3; + unsigned char RPS : 1; +#endif + } BIT; + } CACR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char FERRIE : 1; + unsigned char MENDIE : 1; + unsigned char OVFIE : 1; + unsigned char : 1; + unsigned char FERRFCL : 1; + unsigned char MENDFCL : 1; + unsigned char OVFFCL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char OVFFCL : 1; + unsigned char MENDFCL : 1; + unsigned char FERRFCL : 1; + unsigned char : 1; + unsigned char OVFIE : 1; + unsigned char MENDIE : 1; + unsigned char FERRIE : 1; +#endif + } BIT; + } CAICR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char FERRF : 1; + unsigned char MENDF : 1; + unsigned char OVFF : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char OVFF : 1; + unsigned char MENDF : 1; + unsigned char FERRF : 1; +#endif + } BIT; + } CASTR; + char wk0[1]; + unsigned short CAULVR; + unsigned short CALLVR; + unsigned short CACNTBR; +}; + +struct st_cmpb { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CPB0INI : 1; + unsigned char : 3; + unsigned char CPB1INI : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char CPB1INI : 1; + unsigned char : 3; + unsigned char CPB0INI : 1; +#endif + } BIT; + } CPBCNT1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CPB0WCP : 1; + unsigned char : 3; + unsigned char CPB1WCP : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char CPB1WCP : 1; + unsigned char : 3; + unsigned char CPB0WCP : 1; +#endif + } BIT; + } CPBCNT2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 3; + unsigned char CPB0OUT : 1; + unsigned char : 3; + unsigned char CPB1OUT : 1; +#else + unsigned char CPB1OUT : 1; + unsigned char : 3; + unsigned char CPB0OUT : 1; + unsigned char : 3; +#endif + } BIT; + } CPBFLG; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CPB0INTEN : 1; + unsigned char CPB0INTEG : 1; + unsigned char CPB0INTPL : 1; + unsigned char : 1; + unsigned char CPB1INTEN : 1; + unsigned char CPB1INTEG : 1; + unsigned char CPB1INTPL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char CPB1INTPL : 1; + unsigned char CPB1INTEG : 1; + unsigned char CPB1INTEN : 1; + unsigned char : 1; + unsigned char CPB0INTPL : 1; + unsigned char CPB0INTEG : 1; + unsigned char CPB0INTEN : 1; +#endif + } BIT; + } CPBINT; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CPB0FEN : 1; + unsigned char : 1; + unsigned char CPB0F : 2; + unsigned char CPB1FEN : 1; + unsigned char : 1; + unsigned char CPB1F : 2; +#else + unsigned char CPB1F : 2; + unsigned char : 1; + unsigned char CPB1FEN : 1; + unsigned char CPB0F : 2; + unsigned char : 1; + unsigned char CPB0FEN : 1; +#endif + } BIT; + } CPBF; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CPBSPDMD : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char CPBSPDMD : 1; +#endif + } BIT; + } CPBMD; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CPB0VRF : 1; + unsigned char : 3; + unsigned char CPB1VRF : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char CPB1VRF : 1; + unsigned char : 3; + unsigned char CPB0VRF : 1; +#endif + } BIT; + } CPBREF; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CPB0OE : 1; + unsigned char CPB0OP : 1; + unsigned char : 2; + unsigned char CPB1OE : 1; + unsigned char CPB1OP : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char CPB1OP : 1; + unsigned char CPB1OE : 1; + unsigned char : 2; + unsigned char CPB0OP : 1; + unsigned char CPB0OE : 1; +#endif + } BIT; + } CPBOCR; +}; + +struct st_cmt { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short STR0 : 1; + unsigned short STR1 : 1; + unsigned short : 14; +#else + unsigned short : 14; + unsigned short STR1 : 1; + unsigned short STR0 : 1; +#endif + } BIT; + } CMSTR0; +}; + +struct st_cmt0 { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CKS : 2; + unsigned short : 4; + unsigned short CMIE : 1; + unsigned short : 9; +#else + unsigned short : 9; + unsigned short CMIE : 1; + unsigned short : 4; + unsigned short CKS : 2; +#endif + } BIT; + } CMCR; + unsigned short CMCNT; + unsigned short CMCOR; +}; + +struct st_crc { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char GPS : 2; + unsigned char LMS : 1; + unsigned char : 4; + unsigned char DORCLR : 1; +#else + unsigned char DORCLR : 1; + unsigned char : 4; + unsigned char LMS : 1; + unsigned char GPS : 2; +#endif + } BIT; + } CRCCR; + unsigned char CRCDIR; + unsigned short CRCDOR; +}; + +struct st_ctsu { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CTSUSTRT : 1; + unsigned char CTSUCAP : 1; + unsigned char CTSUSNZ : 1; + unsigned char CTSUIOC : 1; + unsigned char CTSUINIT : 1; + unsigned char : 2; + unsigned char CTSUTXVSEL : 1; +#else + unsigned char CTSUTXVSEL : 1; + unsigned char : 2; + unsigned char CTSUINIT : 1; + unsigned char CTSUIOC : 1; + unsigned char CTSUSNZ : 1; + unsigned char CTSUCAP : 1; + unsigned char CTSUSTRT : 1; +#endif + } BIT; + } CTSUCR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CTSUPON : 1; + unsigned char CTSUCSW : 1; + unsigned char CTSUATUNE0 : 1; + unsigned char CTSUATUNE1 : 1; + unsigned char CTSUCLK : 2; + unsigned char CTSUMD : 2; +#else + unsigned char CTSUMD : 2; + unsigned char CTSUCLK : 2; + unsigned char CTSUATUNE1 : 1; + unsigned char CTSUATUNE0 : 1; + unsigned char CTSUCSW : 1; + unsigned char CTSUPON : 1; +#endif + } BIT; + } CTSUCR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CTSUPRRATIO : 4; + unsigned char CTSUPRMODE : 2; + unsigned char CTSUSOFF : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char CTSUSOFF : 1; + unsigned char CTSUPRMODE : 2; + unsigned char CTSUPRRATIO : 4; +#endif + } BIT; + } CTSUSDPRS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CTSUSST : 8; +#else + unsigned char CTSUSST : 8; +#endif + } BIT; + } CTSUSST; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CTSUMCH0 : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char CTSUMCH0 : 6; +#endif + } BIT; + } CTSUMCH0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CTSUMCH1 : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char CTSUMCH1 : 6; +#endif + } BIT; + } CTSUMCH1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CTSUCHAC00 : 1; + unsigned char CTSUCHAC01 : 1; + unsigned char CTSUCHAC02 : 1; + unsigned char CTSUCHAC03 : 1; + unsigned char CTSUCHAC04 : 1; + unsigned char CTSUCHAC05 : 1; + unsigned char CTSUCHAC06 : 1; + unsigned char CTSUCHAC07 : 1; +#else + unsigned char CTSUCHAC07 : 1; + unsigned char CTSUCHAC06 : 1; + unsigned char CTSUCHAC05 : 1; + unsigned char CTSUCHAC04 : 1; + unsigned char CTSUCHAC03 : 1; + unsigned char CTSUCHAC02 : 1; + unsigned char CTSUCHAC01 : 1; + unsigned char CTSUCHAC00 : 1; +#endif + } BIT; + } CTSUCHAC0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CTSUCHAC10 : 1; + unsigned char CTSUCHAC11 : 1; + unsigned char CTSUCHAC12 : 1; + unsigned char CTSUCHAC13 : 1; + unsigned char CTSUCHAC14 : 1; + unsigned char CTSUCHAC15 : 1; + unsigned char CTSUCHAC16 : 1; + unsigned char CTSUCHAC17 : 1; +#else + unsigned char CTSUCHAC17 : 1; + unsigned char CTSUCHAC16 : 1; + unsigned char CTSUCHAC15 : 1; + unsigned char CTSUCHAC14 : 1; + unsigned char CTSUCHAC13 : 1; + unsigned char CTSUCHAC12 : 1; + unsigned char CTSUCHAC11 : 1; + unsigned char CTSUCHAC10 : 1; +#endif + } BIT; + } CTSUCHAC1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CTSUCHAC20 : 1; + unsigned char CTSUCHAC21 : 1; + unsigned char CTSUCHAC22 : 1; + unsigned char CTSUCHAC23 : 1; + unsigned char CTSUCHAC24 : 1; + unsigned char CTSUCHAC25 : 1; + unsigned char CTSUCHAC26 : 1; + unsigned char CTSUCHAC27 : 1; +#else + unsigned char CTSUCHAC27 : 1; + unsigned char CTSUCHAC26 : 1; + unsigned char CTSUCHAC25 : 1; + unsigned char CTSUCHAC24 : 1; + unsigned char CTSUCHAC23 : 1; + unsigned char CTSUCHAC22 : 1; + unsigned char CTSUCHAC21 : 1; + unsigned char CTSUCHAC20 : 1; +#endif + } BIT; + } CTSUCHAC2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CTSUCHAC30 : 1; + unsigned char CTSUCHAC31 : 1; + unsigned char CTSUCHAC32 : 1; + unsigned char CTSUCHAC33 : 1; + unsigned char CTSUCHAC34 : 1; + unsigned char CTSUCHAC35 : 1; + unsigned char CTSUCHAC36 : 1; + unsigned char CTSUCHAC37 : 1; +#else + unsigned char CTSUCHAC37 : 1; + unsigned char CTSUCHAC36 : 1; + unsigned char CTSUCHAC35 : 1; + unsigned char CTSUCHAC34 : 1; + unsigned char CTSUCHAC33 : 1; + unsigned char CTSUCHAC32 : 1; + unsigned char CTSUCHAC31 : 1; + unsigned char CTSUCHAC30 : 1; +#endif + } BIT; + } CTSUCHAC3; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CTSUCHAC40 : 1; + unsigned char CTSUCHAC41 : 1; + unsigned char CTSUCHAC42 : 1; + unsigned char CTSUCHAC43 : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char CTSUCHAC43 : 1; + unsigned char CTSUCHAC42 : 1; + unsigned char CTSUCHAC41 : 1; + unsigned char CTSUCHAC40 : 1; +#endif + } BIT; + } CTSUCHAC4; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CTSUCHTRC00 : 1; + unsigned char CTSUCHTRC01 : 1; + unsigned char CTSUCHTRC02 : 1; + unsigned char CTSUCHTRC03 : 1; + unsigned char CTSUCHTRC04 : 1; + unsigned char CTSUCHTRC05 : 1; + unsigned char CTSUCHTRC06 : 1; + unsigned char CTSUCHTRC07 : 1; +#else + unsigned char CTSUCHTRC07 : 1; + unsigned char CTSUCHTRC06 : 1; + unsigned char CTSUCHTRC05 : 1; + unsigned char CTSUCHTRC04 : 1; + unsigned char CTSUCHTRC03 : 1; + unsigned char CTSUCHTRC02 : 1; + unsigned char CTSUCHTRC01 : 1; + unsigned char CTSUCHTRC00 : 1; +#endif + } BIT; + } CTSUCHTRC0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CTSUCHTRC10 : 1; + unsigned char CTSUCHTRC11 : 1; + unsigned char CTSUCHTRC12 : 1; + unsigned char CTSUCHTRC13 : 1; + unsigned char CTSUCHTRC14 : 1; + unsigned char CTSUCHTRC15 : 1; + unsigned char CTSUCHTRC16 : 1; + unsigned char CTSUCHTRC17 : 1; +#else + unsigned char CTSUCHTRC17 : 1; + unsigned char CTSUCHTRC16 : 1; + unsigned char CTSUCHTRC15 : 1; + unsigned char CTSUCHTRC14 : 1; + unsigned char CTSUCHTRC13 : 1; + unsigned char CTSUCHTRC12 : 1; + unsigned char CTSUCHTRC11 : 1; + unsigned char CTSUCHTRC10 : 1; +#endif + } BIT; + } CTSUCHTRC1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CTSUCHTRC20 : 1; + unsigned char CTSUCHTRC21 : 1; + unsigned char CTSUCHTRC22 : 1; + unsigned char CTSUCHTRC23 : 1; + unsigned char CTSUCHTRC24 : 1; + unsigned char CTSUCHTRC25 : 1; + unsigned char CTSUCHTRC26 : 1; + unsigned char CTSUCHTRC27 : 1; +#else + unsigned char CTSUCHTRC27 : 1; + unsigned char CTSUCHTRC26 : 1; + unsigned char CTSUCHTRC25 : 1; + unsigned char CTSUCHTRC24 : 1; + unsigned char CTSUCHTRC23 : 1; + unsigned char CTSUCHTRC22 : 1; + unsigned char CTSUCHTRC21 : 1; + unsigned char CTSUCHTRC20 : 1; +#endif + } BIT; + } CTSUCHTRC2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CTSUCHTRC30 : 1; + unsigned char CTSUCHTRC31 : 1; + unsigned char CTSUCHTRC32 : 1; + unsigned char CTSUCHTRC33 : 1; + unsigned char CTSUCHTRC34 : 1; + unsigned char CTSUCHTRC35 : 1; + unsigned char CTSUCHTRC36 : 1; + unsigned char CTSUCHTRC37 : 1; +#else + unsigned char CTSUCHTRC37 : 1; + unsigned char CTSUCHTRC36 : 1; + unsigned char CTSUCHTRC35 : 1; + unsigned char CTSUCHTRC34 : 1; + unsigned char CTSUCHTRC33 : 1; + unsigned char CTSUCHTRC32 : 1; + unsigned char CTSUCHTRC31 : 1; + unsigned char CTSUCHTRC30 : 1; +#endif + } BIT; + } CTSUCHTRC3; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CTSUCHTRC40 : 1; + unsigned char CTSUCHTRC41 : 1; + unsigned char CTSUCHTRC42 : 1; + unsigned char CTSUCHTRC43 : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char CTSUCHTRC43 : 1; + unsigned char CTSUCHTRC42 : 1; + unsigned char CTSUCHTRC41 : 1; + unsigned char CTSUCHTRC40 : 1; +#endif + } BIT; + } CTSUCHTRC4; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CTSUSSMOD : 2; + unsigned char : 2; + unsigned char CTSUSSCNT : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char CTSUSSCNT : 2; + unsigned char : 2; + unsigned char CTSUSSMOD : 2; +#endif + } BIT; + } CTSUDCLKC; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CTSUSTC : 3; + unsigned char : 1; + unsigned char CTSUDTSR : 1; + unsigned char CTSUSOVF : 1; + unsigned char CTSUROVF : 1; + unsigned char CTSUPS : 1; +#else + unsigned char CTSUPS : 1; + unsigned char CTSUROVF : 1; + unsigned char CTSUSOVF : 1; + unsigned char CTSUDTSR : 1; + unsigned char : 1; + unsigned char CTSUSTC : 3; +#endif + } BIT; + } CTSUST; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 8; + unsigned short CTSUSSDIV : 4; + unsigned short : 4; +#else + unsigned short : 4; + unsigned short CTSUSSDIV : 4; + unsigned short : 8; +#endif + } BIT; + } CTSUSSC; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CTSUSO : 10; + unsigned short CTSUSNUM : 6; +#else + unsigned short CTSUSNUM : 6; + unsigned short CTSUSO : 10; +#endif + } BIT; + } CTSUSO0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CTSURICOA : 8; + unsigned short CTSUSDPA : 5; + unsigned short CTSUICOG : 2; + unsigned short : 1; +#else + unsigned short : 1; + unsigned short CTSUICOG : 2; + unsigned short CTSUSDPA : 5; + unsigned short CTSURICOA : 8; +#endif + } BIT; + } CTSUSO1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CTSUSC : 16; +#else + unsigned short CTSUSC : 16; +#endif + } BIT; + } CTSUSC; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CTSURC : 16; +#else + unsigned short CTSURC : 16; +#endif + } BIT; + } CTSURC; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CTSUSPMD : 2; + unsigned short CTSUTSOD : 1; + unsigned short CTSUDRV : 1; + unsigned short : 2; + unsigned short CTSUCLKSEL1 : 1; + unsigned short CTSUTSOC : 1; + unsigned short : 7; + unsigned short CTSUICOMP : 1; +#else + unsigned short CTSUICOMP : 1; + unsigned short : 7; + unsigned short CTSUTSOC : 1; + unsigned short CTSUCLKSEL1 : 1; + unsigned short : 2; + unsigned short CTSUDRV : 1; + unsigned short CTSUTSOD : 1; + unsigned short CTSUSPMD : 2; +#endif + } BIT; + } CTSUERRS; + char wk0[7730848]; + unsigned char CTSUTRMR; +}; + +struct st_da { + unsigned short DADR0; + unsigned short DADR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char DAOE0 : 1; + unsigned char DAOE1 : 1; +#else + unsigned char DAOE1 : 1; + unsigned char DAOE0 : 1; + unsigned char : 6; +#endif + } BIT; + } DACR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char DPSEL : 1; +#else + unsigned char DPSEL : 1; + unsigned char : 7; +#endif + } BIT; + } DADPR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char DAADST : 1; +#else + unsigned char DAADST : 1; + unsigned char : 7; +#endif + } BIT; + } DAADSCR; +}; + +struct st_doc { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OMS : 2; + unsigned char DCSEL : 1; + unsigned char : 1; + unsigned char DOPCIE : 1; + unsigned char DOPCF : 1; + unsigned char DOPCFCL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char DOPCFCL : 1; + unsigned char DOPCF : 1; + unsigned char DOPCIE : 1; + unsigned char : 1; + unsigned char DCSEL : 1; + unsigned char OMS : 2; +#endif + } BIT; + } DOCR; + char wk0[1]; + unsigned short DODIR; + unsigned short DODSR; +}; + +struct st_dtc { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 4; + unsigned char RRS : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char RRS : 1; + unsigned char : 4; +#endif + } BIT; + } DTCCR; + char wk0[3]; + void *DTCVBR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SHORT : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char SHORT : 1; +#endif + } BIT; + } DTCADMOD; + char wk1[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DTCST : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char DTCST : 1; +#endif + } BIT; + } DTCST; + char wk2[1]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short VECN : 8; + unsigned short : 7; + unsigned short ACT : 1; +#else + unsigned short ACT : 1; + unsigned short : 7; + unsigned short VECN : 8; +#endif + } BIT; + } DTCSTS; +}; + +struct st_elc { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char ELCON : 1; +#else + unsigned char ELCON : 1; + unsigned char : 7; +#endif + } BIT; + } ELCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR[26]; + char wk0[4]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 2; + unsigned char MTU1MD : 2; + unsigned char MTU2MD : 2; + unsigned char MTU3MD : 2; +#else + unsigned char MTU3MD : 2; + unsigned char MTU2MD : 2; + unsigned char MTU1MD : 2; + unsigned char : 2; +#endif + } BIT; + } ELOPA; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MTU4MD : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char MTU4MD : 2; +#endif + } BIT; + } ELOPB; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 2; + unsigned char CMT1MD : 2; + unsigned char LPTMD : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char LPTMD : 2; + unsigned char CMT1MD : 2; + unsigned char : 2; +#endif + } BIT; + } ELOPC; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TMR0MD : 2; + unsigned char : 2; + unsigned char TMR2MD : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char TMR2MD : 2; + unsigned char : 2; + unsigned char TMR0MD : 2; +#endif + } BIT; + } ELOPD; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PGR0 : 1; + unsigned char PGR1 : 1; + unsigned char PGR2 : 1; + unsigned char PGR3 : 1; + unsigned char PGR4 : 1; + unsigned char PGR5 : 1; + unsigned char PGR6 : 1; + unsigned char PGR7 : 1; +#else + unsigned char PGR7 : 1; + unsigned char PGR6 : 1; + unsigned char PGR5 : 1; + unsigned char PGR4 : 1; + unsigned char PGR3 : 1; + unsigned char PGR2 : 1; + unsigned char PGR1 : 1; + unsigned char PGR0 : 1; +#endif + } BIT; + } PGR1; + char wk1[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PGCI : 2; + unsigned char PGCOVE : 1; + unsigned char : 1; + unsigned char PGCO : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char PGCO : 3; + unsigned char : 1; + unsigned char PGCOVE : 1; + unsigned char PGCI : 2; +#endif + } BIT; + } PGC1; + char wk2[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PDBF0 : 1; + unsigned char PDBF1 : 1; + unsigned char PDBF2 : 1; + unsigned char PDBF3 : 1; + unsigned char PDBF4 : 1; + unsigned char PDBF5 : 1; + unsigned char PDBF6 : 1; + unsigned char PDBF7 : 1; +#else + unsigned char PDBF7 : 1; + unsigned char PDBF6 : 1; + unsigned char PDBF5 : 1; + unsigned char PDBF4 : 1; + unsigned char PDBF3 : 1; + unsigned char PDBF2 : 1; + unsigned char PDBF1 : 1; + unsigned char PDBF0 : 1; +#endif + } BIT; + } PDBF1; + char wk3[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSB : 3; + unsigned char PSP : 2; + unsigned char PSM : 2; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char PSM : 2; + unsigned char PSP : 2; + unsigned char PSB : 3; +#endif + } BIT; + } PEL0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSB : 3; + unsigned char PSP : 2; + unsigned char PSM : 2; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char PSM : 2; + unsigned char PSP : 2; + unsigned char PSB : 3; +#endif + } BIT; + } PEL1; + char wk4[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SEG : 1; + unsigned char : 5; + unsigned char WE : 1; + unsigned char WI : 1; +#else + unsigned char WI : 1; + unsigned char WE : 1; + unsigned char : 5; + unsigned char SEG : 1; +#endif + } BIT; + } ELSEGR; +}; + +struct st_flash { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DFLEN : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char DFLEN : 1; +#endif + } BIT; + } DFLCTL; + char wk0[31]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 8; + unsigned short SASMF : 1; + unsigned short : 7; +#else + unsigned short : 7; + unsigned short SASMF : 1; + unsigned short : 8; +#endif + } BIT; + } FSCMR; + unsigned short FAWSMR; + unsigned short FAWEMR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PCKA : 5; + unsigned char : 1; + unsigned char SAS : 2; +#else + unsigned char SAS : 2; + unsigned char : 1; + unsigned char PCKA : 5; +#endif + } BIT; + } FISR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CMD : 3; + unsigned char : 4; + unsigned char OPST : 1; +#else + unsigned char OPST : 1; + unsigned char : 4; + unsigned char CMD : 3; +#endif + } BIT; + } FEXCR; + unsigned short FEAML; + unsigned char FEAMH; + char wk1[5]; + unsigned char FPR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PERR : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char PERR : 1; +#endif + } BIT; + } FPSR; + unsigned short FRBL; + unsigned short FRBH; + char wk2[16058]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 1; + unsigned char FMS0 : 1; + unsigned char : 1; + unsigned char RPDIS : 1; + unsigned char FMS1 : 1; + unsigned char : 1; + unsigned char LVPE : 1; + unsigned char FMS2 : 1; +#else + unsigned char FMS2 : 1; + unsigned char LVPE : 1; + unsigned char : 1; + unsigned char FMS1 : 1; + unsigned char RPDIS : 1; + unsigned char : 1; + unsigned char FMS0 : 1; + unsigned char : 1; +#endif + } BIT; + } FPMCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char EXS : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char EXS : 1; +#endif + } BIT; + } FASR; + unsigned short FSARL; + unsigned char FSARH; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CMD : 4; + unsigned char DRC : 1; + unsigned char : 1; + unsigned char STOP : 1; + unsigned char OPST : 1; +#else + unsigned char OPST : 1; + unsigned char STOP : 1; + unsigned char : 1; + unsigned char DRC : 1; + unsigned char CMD : 4; +#endif + } BIT; + } FCR; + unsigned short FEARL; + unsigned char FEARH; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char FRESET : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char FRESET : 1; +#endif + } BIT; + } FRESETR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ERERR : 1; + unsigned char PRGERR : 1; + unsigned char : 1; + unsigned char BCERR : 1; + unsigned char ILGLERR : 1; + unsigned char EILGLERR : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char EILGLERR : 1; + unsigned char ILGLERR : 1; + unsigned char BCERR : 1; + unsigned char : 1; + unsigned char PRGERR : 1; + unsigned char ERERR : 1; +#endif + } BIT; + } FSTATR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 1; + unsigned char DRRDY : 1; + unsigned char : 4; + unsigned char FRDY : 1; + unsigned char EXRDY : 1; +#else + unsigned char EXRDY : 1; + unsigned char FRDY : 1; + unsigned char : 4; + unsigned char DRRDY : 1; + unsigned char : 1; +#endif + } BIT; + } FSTATR1; + unsigned short FWBL; + unsigned short FWBH; + char wk3[34]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short FENTRY0 : 1; + unsigned short : 6; + unsigned short FENTRYD : 1; + unsigned short FEKEY : 8; +#else + unsigned short FEKEY : 8; + unsigned short FENTRYD : 1; + unsigned short : 6; + unsigned short FENTRY0 : 1; +#endif + } BIT; + } FENTRYR; +}; + +struct st_icu { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IR : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char IR : 1; +#endif + } BIT; + } IR[250]; + char wk0[6]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DTCE : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char DTCE : 1; +#endif + } BIT; + } DTCER[249]; + char wk1[7]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IEN0 : 1; + unsigned char IEN1 : 1; + unsigned char IEN2 : 1; + unsigned char IEN3 : 1; + unsigned char IEN4 : 1; + unsigned char IEN5 : 1; + unsigned char IEN6 : 1; + unsigned char IEN7 : 1; +#else + unsigned char IEN7 : 1; + unsigned char IEN6 : 1; + unsigned char IEN5 : 1; + unsigned char IEN4 : 1; + unsigned char IEN3 : 1; + unsigned char IEN2 : 1; + unsigned char IEN1 : 1; + unsigned char IEN0 : 1; +#endif + } BIT; + } IER[32]; + char wk2[192]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SWINT : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char SWINT : 1; +#endif + } BIT; + } SWINTR; + char wk3[15]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short FVCT : 8; + unsigned short : 7; + unsigned short FIEN : 1; +#else + unsigned short FIEN : 1; + unsigned short : 7; + unsigned short FVCT : 8; +#endif + } BIT; + } FIR; + char wk4[14]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IPR : 4; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char IPR : 4; +#endif + } BIT; + } IPR[250]; + char wk5[262]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 2; + unsigned char IRQMD : 2; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char IRQMD : 2; + unsigned char : 2; +#endif + } BIT; + } IRQCR[8]; + char wk6[8]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char FLTEN0 : 1; + unsigned char FLTEN1 : 1; + unsigned char FLTEN2 : 1; + unsigned char FLTEN3 : 1; + unsigned char FLTEN4 : 1; + unsigned char FLTEN5 : 1; + unsigned char FLTEN6 : 1; + unsigned char FLTEN7 : 1; +#else + unsigned char FLTEN7 : 1; + unsigned char FLTEN6 : 1; + unsigned char FLTEN5 : 1; + unsigned char FLTEN4 : 1; + unsigned char FLTEN3 : 1; + unsigned char FLTEN2 : 1; + unsigned char FLTEN1 : 1; + unsigned char FLTEN0 : 1; +#endif + } BIT; + } IRQFLTE0; + char wk7[3]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short FCLKSEL0 : 2; + unsigned short FCLKSEL1 : 2; + unsigned short FCLKSEL2 : 2; + unsigned short FCLKSEL3 : 2; + unsigned short FCLKSEL4 : 2; + unsigned short FCLKSEL5 : 2; + unsigned short FCLKSEL6 : 2; + unsigned short FCLKSEL7 : 2; +#else + unsigned short FCLKSEL7 : 2; + unsigned short FCLKSEL6 : 2; + unsigned short FCLKSEL5 : 2; + unsigned short FCLKSEL4 : 2; + unsigned short FCLKSEL3 : 2; + unsigned short FCLKSEL2 : 2; + unsigned short FCLKSEL1 : 2; + unsigned short FCLKSEL0 : 2; +#endif + } BIT; + } IRQFLTC0; + char wk8[106]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NMIST : 1; + unsigned char OSTST : 1; + unsigned char : 1; + unsigned char IWDTST : 1; + unsigned char LVD1ST : 1; + unsigned char LVD2ST : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char LVD2ST : 1; + unsigned char LVD1ST : 1; + unsigned char IWDTST : 1; + unsigned char : 1; + unsigned char OSTST : 1; + unsigned char NMIST : 1; +#endif + } BIT; + } NMISR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NMIEN : 1; + unsigned char OSTEN : 1; + unsigned char : 1; + unsigned char IWDTEN : 1; + unsigned char LVD1EN : 1; + unsigned char LVD2EN : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char LVD2EN : 1; + unsigned char LVD1EN : 1; + unsigned char IWDTEN : 1; + unsigned char : 1; + unsigned char OSTEN : 1; + unsigned char NMIEN : 1; +#endif + } BIT; + } NMIER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NMICLR : 1; + unsigned char OSTCLR : 1; + unsigned char : 1; + unsigned char IWDTCLR : 1; + unsigned char LVD1CLR : 1; + unsigned char LVD2CLR : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char LVD2CLR : 1; + unsigned char LVD1CLR : 1; + unsigned char IWDTCLR : 1; + unsigned char : 1; + unsigned char OSTCLR : 1; + unsigned char NMICLR : 1; +#endif + } BIT; + } NMICLR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 3; + unsigned char NMIMD : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char NMIMD : 1; + unsigned char : 3; +#endif + } BIT; + } NMICR; + char wk9[12]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFLTEN : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char NFLTEN : 1; +#endif + } BIT; + } NMIFLTE; + char wk10[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFCLKSEL : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char NFCLKSEL : 2; +#endif + } BIT; + } NMIFLTC; +}; + +struct st_iwdt { + unsigned char IWDTRR; + char wk0[1]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TOPS : 2; + unsigned short : 2; + unsigned short CKS : 4; + unsigned short RPES : 2; + unsigned short : 2; + unsigned short RPSS : 2; + unsigned short : 2; +#else + unsigned short : 2; + unsigned short RPSS : 2; + unsigned short : 2; + unsigned short RPES : 2; + unsigned short CKS : 4; + unsigned short : 2; + unsigned short TOPS : 2; +#endif + } BIT; + } IWDTCR; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CNTVAL : 14; + unsigned short UNDFF : 1; + unsigned short REFEF : 1; +#else + unsigned short REFEF : 1; + unsigned short UNDFF : 1; + unsigned short CNTVAL : 14; +#endif + } BIT; + } IWDTSR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char RSTIRQS : 1; +#else + unsigned char RSTIRQS : 1; + unsigned char : 7; +#endif + } BIT; + } IWDTRCR; + char wk1[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char SLCSTP : 1; +#else + unsigned char SLCSTP : 1; + unsigned char : 7; +#endif + } BIT; + } IWDTCSTPR; +}; + +struct st_lpt { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LPCNTPSSEL : 3; + unsigned char : 1; + unsigned char LPCNTCKSEL : 1; + unsigned char : 1; + unsigned char LPCMRE0 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char LPCMRE0 : 1; + unsigned char : 1; + unsigned char LPCNTCKSEL : 1; + unsigned char : 1; + unsigned char LPCNTPSSEL : 3; +#endif + } BIT; + } LPTCR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LPCNTSTP : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char LPCNTSTP : 1; +#endif + } BIT; + } LPTCR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LPCNTEN : 1; + unsigned char LPCNTRST : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char LPCNTRST : 1; + unsigned char LPCNTEN : 1; +#endif + } BIT; + } LPTCR3; + char wk0[1]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short LPCNTPRD : 16; +#else + unsigned short LPCNTPRD : 16; +#endif + } BIT; + } LPTPRD; + char wk1[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short LPCMR0 : 16; +#else + unsigned short LPCMR0 : 16; +#endif + } BIT; + } LPCMR0; + char wk2[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 15; + unsigned short LPWKUPEN : 1; +#else + unsigned short LPWKUPEN : 1; + unsigned short : 15; +#endif + } BIT; + } LPWUCR; +}; + +struct st_mpc { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char PFSWE : 1; + unsigned char B0WI : 1; +#else + unsigned char B0WI : 1; + unsigned char PFSWE : 1; + unsigned char : 6; +#endif + } BIT; + } PWPR; + char wk0[35]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 7; +#endif + } BIT; + } P03PFS; + char wk1[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 7; +#endif + } BIT; + } P05PFS; + char wk2[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } P07PFS; + char wk3[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } P12PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } P13PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } P14PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } P15PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } P16PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } P17PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } P20PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } P21PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } P22PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } P23PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } P24PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } P25PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } P26PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } P27PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } P30PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } P31PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } P32PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } P33PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } P34PFS; + char wk4[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 7; +#endif + } BIT; + } P40PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 7; +#endif + } BIT; + } P41PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 7; +#endif + } BIT; + } P42PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 7; +#endif + } BIT; + } P43PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 7; +#endif + } BIT; + } P44PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 7; +#endif + } BIT; + } P45PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 7; +#endif + } BIT; + } P46PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 7; +#endif + } BIT; + } P47PFS; + char wk5[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } P51PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } P52PFS; + char wk6[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } P54PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } P55PFS; + char wk7[34]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PA0PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PA1PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PA2PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PA3PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PA4PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PA5PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PA6PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PA7PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PB0PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PB1PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PB2PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PB3PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PB4PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PB5PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PB6PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PB7PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PC0PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PC1PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PC2PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PC3PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PC4PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PC5PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PC6PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PC7PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PD0PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PD1PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PD2PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PD3PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PD4PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PD5PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PD6PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PD7PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 2; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 2; + unsigned char PSEL : 5; +#endif + } BIT; + } PE0PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 2; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 2; + unsigned char PSEL : 5; +#endif + } BIT; + } PE1PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PE2PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 2; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 2; + unsigned char PSEL : 5; +#endif + } BIT; + } PE3PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 2; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 2; + unsigned char PSEL : 5; +#endif + } BIT; + } PE4PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PE5PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 6; +#endif + } BIT; + } PE6PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 6; +#endif + } BIT; + } PE7PFS; + char wk8[16]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PH0PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PH1PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PH2PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PH3PFS; + char wk9[5]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PJ1PFS; + char wk10[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PJ3PFS; + char wk11[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 7; +#endif + } BIT; + } PJ6PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 7; +#endif + } BIT; + } PJ7PFS; +}; + +struct st_mtu { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OE3B : 1; + unsigned char OE4A : 1; + unsigned char OE4B : 1; + unsigned char OE3D : 1; + unsigned char OE4C : 1; + unsigned char OE4D : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char OE4D : 1; + unsigned char OE4C : 1; + unsigned char OE3D : 1; + unsigned char OE4B : 1; + unsigned char OE4A : 1; + unsigned char OE3B : 1; +#endif + } BIT; + } TOER; + char wk0[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char UF : 1; + unsigned char VF : 1; + unsigned char WF : 1; + unsigned char FB : 1; + unsigned char P : 1; + unsigned char N : 1; + unsigned char BDC : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char BDC : 1; + unsigned char N : 1; + unsigned char P : 1; + unsigned char FB : 1; + unsigned char WF : 1; + unsigned char VF : 1; + unsigned char UF : 1; +#endif + } BIT; + } TGCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OLSP : 1; + unsigned char OLSN : 1; + unsigned char TOCS : 1; + unsigned char TOCL : 1; + unsigned char : 2; + unsigned char PSYE : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char PSYE : 1; + unsigned char : 2; + unsigned char TOCL : 1; + unsigned char TOCS : 1; + unsigned char OLSN : 1; + unsigned char OLSP : 1; +#endif + } BIT; + } TOCR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OLS1P : 1; + unsigned char OLS1N : 1; + unsigned char OLS2P : 1; + unsigned char OLS2N : 1; + unsigned char OLS3P : 1; + unsigned char OLS3N : 1; + unsigned char BF : 2; +#else + unsigned char BF : 2; + unsigned char OLS3N : 1; + unsigned char OLS3P : 1; + unsigned char OLS2N : 1; + unsigned char OLS2P : 1; + unsigned char OLS1N : 1; + unsigned char OLS1P : 1; +#endif + } BIT; + } TOCR2; + char wk1[4]; + unsigned short TCDR; + unsigned short TDDR; + char wk2[8]; + unsigned short TCNTS; + unsigned short TCBR; + char wk3[12]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char T4VCOR : 3; + unsigned char T4VEN : 1; + unsigned char T3ACOR : 3; + unsigned char T3AEN : 1; +#else + unsigned char T3AEN : 1; + unsigned char T3ACOR : 3; + unsigned char T4VEN : 1; + unsigned char T4VCOR : 3; +#endif + } BIT; + } TITCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char T4VCNT : 3; + unsigned char : 1; + unsigned char T3ACNT : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char T3ACNT : 3; + unsigned char : 1; + unsigned char T4VCNT : 3; +#endif + } BIT; + } TITCNT; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BTE : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char BTE : 2; +#endif + } BIT; + } TBTER; + char wk4[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TDER : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char TDER : 1; +#endif + } BIT; + } TDER; + char wk5[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OLS1P : 1; + unsigned char OLS1N : 1; + unsigned char OLS2P : 1; + unsigned char OLS2N : 1; + unsigned char OLS3P : 1; + unsigned char OLS3N : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char OLS3N : 1; + unsigned char OLS3P : 1; + unsigned char OLS2N : 1; + unsigned char OLS2P : 1; + unsigned char OLS1N : 1; + unsigned char OLS1P : 1; +#endif + } BIT; + } TOLBR; + char wk6[41]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char WRE : 1; + unsigned char : 6; + unsigned char CCE : 1; +#else + unsigned char CCE : 1; + unsigned char : 6; + unsigned char WRE : 1; +#endif + } BIT; + } TWCR; + char wk7[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CST0 : 1; + unsigned char CST1 : 1; + unsigned char CST2 : 1; + unsigned char : 3; + unsigned char CST3 : 1; + unsigned char CST4 : 1; +#else + unsigned char CST4 : 1; + unsigned char CST3 : 1; + unsigned char : 3; + unsigned char CST2 : 1; + unsigned char CST1 : 1; + unsigned char CST0 : 1; +#endif + } BIT; + } TSTR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SYNC0 : 1; + unsigned char SYNC1 : 1; + unsigned char SYNC2 : 1; + unsigned char : 3; + unsigned char SYNC3 : 1; + unsigned char SYNC4 : 1; +#else + unsigned char SYNC4 : 1; + unsigned char SYNC3 : 1; + unsigned char : 3; + unsigned char SYNC2 : 1; + unsigned char SYNC1 : 1; + unsigned char SYNC0 : 1; +#endif + } BIT; + } TSYR; + char wk8[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char RWE : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char RWE : 1; +#endif + } BIT; + } TRWER; +}; + +struct st_mtu0 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char NFCEN : 1; + unsigned char NFDEN : 1; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char NFDEN : 1; + unsigned char NFCEN : 1; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif + } BIT; + } NFCR; + char wk0[111]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 3; + unsigned char CKEG : 2; + unsigned char CCLR : 3; +#else + unsigned char CCLR : 3; + unsigned char CKEG : 2; + unsigned char TPSC : 3; +#endif + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MD : 4; + unsigned char BFA : 1; + unsigned char BFB : 1; + unsigned char BFE : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char BFE : 1; + unsigned char BFB : 1; + unsigned char BFA : 1; + unsigned char MD : 4; +#endif + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOA : 4; + unsigned char IOB : 4; +#else + unsigned char IOB : 4; + unsigned char IOA : 4; +#endif + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOC : 4; + unsigned char IOD : 4; +#else + unsigned char IOD : 4; + unsigned char IOC : 4; +#endif + } BIT; + } TIORL; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEA : 1; + unsigned char TGIEB : 1; + unsigned char TGIEC : 1; + unsigned char TGIED : 1; + unsigned char TCIEV : 1; + unsigned char : 2; + unsigned char TTGE : 1; +#else + unsigned char TTGE : 1; + unsigned char : 2; + unsigned char TCIEV : 1; + unsigned char TGIED : 1; + unsigned char TGIEC : 1; + unsigned char TGIEB : 1; + unsigned char TGIEA : 1; +#endif + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char TCFD : 1; +#else + unsigned char TCFD : 1; + unsigned char : 7; +#endif + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; + unsigned short TGRC; + unsigned short TGRD; + char wk1[16]; + unsigned short TGRE; + unsigned short TGRF; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEE : 1; + unsigned char TGIEF : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char TGIEF : 1; + unsigned char TGIEE : 1; +#endif + } BIT; + } TIER2; + char wk2[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TTSA : 1; + unsigned char TTSB : 1; + unsigned char TTSE : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char TTSE : 1; + unsigned char TTSB : 1; + unsigned char TTSA : 1; +#endif + } BIT; + } TBTM; +}; + +struct st_mtu1 { + char wk0[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char NFCEN : 1; + unsigned char NFDEN : 1; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char NFDEN : 1; + unsigned char NFCEN : 1; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif + } BIT; + } NFCR; + char wk1[238]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 3; + unsigned char CKEG : 2; + unsigned char CCLR : 2; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char CCLR : 2; + unsigned char CKEG : 2; + unsigned char TPSC : 3; +#endif + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MD : 4; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char MD : 4; +#endif + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOA : 4; + unsigned char IOB : 4; +#else + unsigned char IOB : 4; + unsigned char IOA : 4; +#endif + } BIT; + } TIOR; + char wk2[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEA : 1; + unsigned char TGIEB : 1; + unsigned char : 2; + unsigned char TCIEV : 1; + unsigned char TCIEU : 1; + unsigned char : 1; + unsigned char TTGE : 1; +#else + unsigned char TTGE : 1; + unsigned char : 1; + unsigned char TCIEU : 1; + unsigned char TCIEV : 1; + unsigned char : 2; + unsigned char TGIEB : 1; + unsigned char TGIEA : 1; +#endif + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char TCFD : 1; +#else + unsigned char TCFD : 1; + unsigned char : 7; +#endif + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; + char wk3[4]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char I1AE : 1; + unsigned char I1BE : 1; + unsigned char I2AE : 1; + unsigned char I2BE : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char I2BE : 1; + unsigned char I2AE : 1; + unsigned char I1BE : 1; + unsigned char I1AE : 1; +#endif + } BIT; + } TICCR; +}; + +struct st_mtu2 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char NFCEN : 1; + unsigned char NFDEN : 1; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char NFDEN : 1; + unsigned char NFCEN : 1; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif + } BIT; + } NFCR; + char wk0[365]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 3; + unsigned char CKEG : 2; + unsigned char CCLR : 2; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char CCLR : 2; + unsigned char CKEG : 2; + unsigned char TPSC : 3; +#endif + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MD : 4; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char MD : 4; +#endif + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOA : 4; + unsigned char IOB : 4; +#else + unsigned char IOB : 4; + unsigned char IOA : 4; +#endif + } BIT; + } TIOR; + char wk1[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEA : 1; + unsigned char TGIEB : 1; + unsigned char : 2; + unsigned char TCIEV : 1; + unsigned char TCIEU : 1; + unsigned char : 1; + unsigned char TTGE : 1; +#else + unsigned char TTGE : 1; + unsigned char : 1; + unsigned char TCIEU : 1; + unsigned char TCIEV : 1; + unsigned char : 2; + unsigned char TGIEB : 1; + unsigned char TGIEA : 1; +#endif + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char TCFD : 1; +#else + unsigned char TCFD : 1; + unsigned char : 7; +#endif + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; +}; + +struct st_mtu3 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 3; + unsigned char CKEG : 2; + unsigned char CCLR : 3; +#else + unsigned char CCLR : 3; + unsigned char CKEG : 2; + unsigned char TPSC : 3; +#endif + } BIT; + } TCR; + char wk0[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MD : 4; + unsigned char BFA : 1; + unsigned char BFB : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char BFB : 1; + unsigned char BFA : 1; + unsigned char MD : 4; +#endif + } BIT; + } TMDR; + char wk1[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOA : 4; + unsigned char IOB : 4; +#else + unsigned char IOB : 4; + unsigned char IOA : 4; +#endif + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOC : 4; + unsigned char IOD : 4; +#else + unsigned char IOD : 4; + unsigned char IOC : 4; +#endif + } BIT; + } TIORL; + char wk2[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEA : 1; + unsigned char TGIEB : 1; + unsigned char TGIEC : 1; + unsigned char TGIED : 1; + unsigned char TCIEV : 1; + unsigned char : 2; + unsigned char TTGE : 1; +#else + unsigned char TTGE : 1; + unsigned char : 2; + unsigned char TCIEV : 1; + unsigned char TGIED : 1; + unsigned char TGIEC : 1; + unsigned char TGIEB : 1; + unsigned char TGIEA : 1; +#endif + } BIT; + } TIER; + char wk3[7]; + unsigned short TCNT; + char wk4[6]; + unsigned short TGRA; + unsigned short TGRB; + char wk5[8]; + unsigned short TGRC; + unsigned short TGRD; + char wk6[4]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char TCFD : 1; +#else + unsigned char TCFD : 1; + unsigned char : 7; +#endif + } BIT; + } TSR; + char wk7[11]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TTSA : 1; + unsigned char TTSB : 1; + unsigned char TTSE : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char TTSE : 1; + unsigned char TTSB : 1; + unsigned char TTSA : 1; +#endif + } BIT; + } TBTM; + char wk8[90]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char NFCEN : 1; + unsigned char NFDEN : 1; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char NFDEN : 1; + unsigned char NFCEN : 1; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif + } BIT; + } NFCR; +}; + +struct st_mtu4 { + char wk0[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 3; + unsigned char CKEG : 2; + unsigned char CCLR : 3; +#else + unsigned char CCLR : 3; + unsigned char CKEG : 2; + unsigned char TPSC : 3; +#endif + } BIT; + } TCR; + char wk1[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MD : 4; + unsigned char BFA : 1; + unsigned char BFB : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char BFB : 1; + unsigned char BFA : 1; + unsigned char MD : 4; +#endif + } BIT; + } TMDR; + char wk2[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOA : 4; + unsigned char IOB : 4; +#else + unsigned char IOB : 4; + unsigned char IOA : 4; +#endif + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOC : 4; + unsigned char IOD : 4; +#else + unsigned char IOD : 4; + unsigned char IOC : 4; +#endif + } BIT; + } TIORL; + char wk3[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEA : 1; + unsigned char TGIEB : 1; + unsigned char TGIEC : 1; + unsigned char TGIED : 1; + unsigned char TCIEV : 1; + unsigned char : 1; + unsigned char TTGE2 : 1; + unsigned char TTGE : 1; +#else + unsigned char TTGE : 1; + unsigned char TTGE2 : 1; + unsigned char : 1; + unsigned char TCIEV : 1; + unsigned char TGIED : 1; + unsigned char TGIEC : 1; + unsigned char TGIEB : 1; + unsigned char TGIEA : 1; +#endif + } BIT; + } TIER; + char wk4[8]; + unsigned short TCNT; + char wk5[8]; + unsigned short TGRA; + unsigned short TGRB; + char wk6[8]; + unsigned short TGRC; + unsigned short TGRD; + char wk7[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char TCFD : 1; +#else + unsigned char TCFD : 1; + unsigned char : 7; +#endif + } BIT; + } TSR; + char wk8[11]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TTSA : 1; + unsigned char TTSB : 1; + unsigned char TTSE : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char TTSE : 1; + unsigned char TTSB : 1; + unsigned char TTSA : 1; +#endif + } BIT; + } TBTM; + char wk9[6]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ITB4VE : 1; + unsigned short ITB3AE : 1; + unsigned short ITA4VE : 1; + unsigned short ITA3AE : 1; + unsigned short DT4BE : 1; + unsigned short UT4BE : 1; + unsigned short DT4AE : 1; + unsigned short UT4AE : 1; + unsigned short : 6; + unsigned short BF : 2; +#else + unsigned short BF : 2; + unsigned short : 6; + unsigned short UT4AE : 1; + unsigned short DT4AE : 1; + unsigned short UT4BE : 1; + unsigned short DT4BE : 1; + unsigned short ITA3AE : 1; + unsigned short ITA4VE : 1; + unsigned short ITB3AE : 1; + unsigned short ITB4VE : 1; +#endif + } BIT; + } TADCR; + char wk10[2]; + unsigned short TADCORA; + unsigned short TADCORB; + unsigned short TADCOBRA; + unsigned short TADCOBRB; + char wk11[72]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char NFCEN : 1; + unsigned char NFDEN : 1; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char NFDEN : 1; + unsigned char NFCEN : 1; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif + } BIT; + } NFCR; +}; + +struct st_mtu5 { + char wk0[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFUEN : 1; + unsigned char NFVEN : 1; + unsigned char NFWEN : 1; + unsigned char : 1; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char : 1; + unsigned char NFWEN : 1; + unsigned char NFVEN : 1; + unsigned char NFUEN : 1; +#endif + } BIT; + } NFCR; + char wk1[490]; + unsigned short TCNTU; + unsigned short TGRU; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char TPSC : 2; +#endif + } BIT; + } TCRU; + char wk2[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOC : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char IOC : 5; +#endif + } BIT; + } TIORU; + char wk3[9]; + unsigned short TCNTV; + unsigned short TGRV; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char TPSC : 2; +#endif + } BIT; + } TCRV; + char wk4[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOC : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char IOC : 5; +#endif + } BIT; + } TIORV; + char wk5[9]; + unsigned short TCNTW; + unsigned short TGRW; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char TPSC : 2; +#endif + } BIT; + } TCRW; + char wk6[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOC : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char IOC : 5; +#endif + } BIT; + } TIORW; + char wk7[11]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIE5W : 1; + unsigned char TGIE5V : 1; + unsigned char TGIE5U : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char TGIE5U : 1; + unsigned char TGIE5V : 1; + unsigned char TGIE5W : 1; +#endif + } BIT; + } TIER; + char wk8[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CSTW5 : 1; + unsigned char CSTV5 : 1; + unsigned char CSTU5 : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char CSTU5 : 1; + unsigned char CSTV5 : 1; + unsigned char CSTW5 : 1; +#endif + } BIT; + } TSTR; + char wk9[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CMPCLR5W : 1; + unsigned char CMPCLR5V : 1; + unsigned char CMPCLR5U : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char CMPCLR5U : 1; + unsigned char CMPCLR5V : 1; + unsigned char CMPCLR5W : 1; +#endif + } BIT; + } TCNTCMPCLR; +}; + +struct st_poe { + union { + unsigned short WORD; + struct { + unsigned char H; + unsigned char L; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short POE0M : 2; + unsigned short POE1M : 2; + unsigned short POE2M : 2; + unsigned short POE3M : 2; + unsigned short PIE1 : 1; + unsigned short : 3; + unsigned short POE0F : 1; + unsigned short POE1F : 1; + unsigned short POE2F : 1; + unsigned short POE3F : 1; +#else + unsigned short POE3F : 1; + unsigned short POE2F : 1; + unsigned short POE1F : 1; + unsigned short POE0F : 1; + unsigned short : 3; + unsigned short PIE1 : 1; + unsigned short POE3M : 2; + unsigned short POE2M : 2; + unsigned short POE1M : 2; + unsigned short POE0M : 2; +#endif + } BIT; + } ICSR1; + union { + unsigned short WORD; + struct { + unsigned char H; + unsigned char L; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 8; + unsigned short OIE1 : 1; + unsigned short OCE1 : 1; + unsigned short : 5; + unsigned short OSF1 : 1; +#else + unsigned short OSF1 : 1; + unsigned short : 5; + unsigned short OCE1 : 1; + unsigned short OIE1 : 1; + unsigned short : 8; +#endif + } BIT; + } OCSR1; + char wk0[4]; + union { + unsigned short WORD; + struct { + unsigned char H; + unsigned char L; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short POE8M : 2; + unsigned short : 6; + unsigned short PIE2 : 1; + unsigned short POE8E : 1; + unsigned short : 2; + unsigned short POE8F : 1; + unsigned short : 3; +#else + unsigned short : 3; + unsigned short POE8F : 1; + unsigned short : 2; + unsigned short POE8E : 1; + unsigned short PIE2 : 1; + unsigned short : 6; + unsigned short POE8M : 2; +#endif + } BIT; + } ICSR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CH34HIZ : 1; + unsigned char CH0HIZ : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char CH0HIZ : 1; + unsigned char CH34HIZ : 1; +#endif + } BIT; + } SPOER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PE0ZE : 1; + unsigned char PE1ZE : 1; + unsigned char PE2ZE : 1; + unsigned char PE3ZE : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char PE3ZE : 1; + unsigned char PE2ZE : 1; + unsigned char PE1ZE : 1; + unsigned char PE0ZE : 1; +#endif + } BIT; + } POECR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 4; + unsigned char P3CZEA : 1; + unsigned char P2CZEA : 1; + unsigned char P1CZEA : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char P1CZEA : 1; + unsigned char P2CZEA : 1; + unsigned char P3CZEA : 1; + unsigned char : 4; +#endif + } BIT; + } POECR2; + char wk1[1]; + union { + unsigned short WORD; + struct { + unsigned char H; + unsigned char L; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 1; + unsigned short : 8; + unsigned short OSTSTE : 1; + unsigned short : 2; + unsigned short OSTSTF : 1; + unsigned short : 3; +#else + unsigned short : 3; + unsigned short OSTSTF : 1; + unsigned short : 2; + unsigned short OSTSTE : 1; + unsigned short : 8; + unsigned short : 1; +#endif + } BIT; + } ICSR3; +}; + +struct st_port { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL0 : 1; + unsigned char PSEL1 : 1; + unsigned char : 1; + unsigned char PSEL3 : 1; + unsigned char : 1; + unsigned char PSEL5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL5 : 1; + unsigned char : 1; + unsigned char PSEL3 : 1; + unsigned char : 1; + unsigned char PSEL1 : 1; + unsigned char PSEL0 : 1; +#endif + } BIT; + } PSRB; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char PSEL6 : 1; + unsigned char PSEL7 : 1; +#else + unsigned char PSEL7 : 1; + unsigned char PSEL6 : 1; + unsigned char : 6; +#endif + } BIT; + } PSRA; +}; + +struct st_port0 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 3; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char : 3; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 3; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char : 3; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 3; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char : 3; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 3; + unsigned char B3 : 1; + unsigned char : 1; + unsigned char B5 : 1; + unsigned char : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char : 1; + unsigned char B5 : 1; + unsigned char : 1; + unsigned char B3 : 1; + unsigned char : 3; +#endif + } BIT; + } PMR; + char wk3[95]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 3; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char : 3; +#endif + } BIT; + } PCR; +}; + +struct st_port1 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 2; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char : 2; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 2; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char : 2; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 2; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char : 2; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 2; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char : 2; +#endif + } BIT; + } PMR; + char wk3[32]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 4; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 4; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR1; + char wk4[61]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 2; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char : 2; +#endif + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 2; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char : 2; +#endif + } BIT; + } DSCR; +}; + +struct st_port2 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[33]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 4; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 4; +#endif + } BIT; + } ODR1; + char wk4[60]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } DSCR; +}; + +struct st_port3 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[34]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 3; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 3; + unsigned char B0 : 1; +#endif + } BIT; + } ODR1; + char wk4[59]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } DSCR; +}; + +struct st_port4 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[95]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; +}; + +struct st_port5 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char : 1; +#endif + } BIT; + } PMR; + char wk3[95]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; + char wk4[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } DSCR; +}; + +struct st_porta { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[41]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR1; + char wk4[52]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } DSCR; +}; + +struct st_portb { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[42]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR1; + char wk4[51]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } DSCR; +}; + +struct st_portc { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[43]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR1; + char wk4[50]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } DSCR; +}; + +struct st_portd { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[44]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + char wk4[50]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } DSCR; +}; + +struct st_porte { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[45]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + char wk4[49]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } DSCR; +}; + +struct st_porth { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[95]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; + char wk4[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } DSCR; +}; + +struct st_portj { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 1; + unsigned char B1 : 1; + unsigned char : 1; + unsigned char B3 : 1; + unsigned char : 2; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char : 2; + unsigned char B3 : 1; + unsigned char : 1; + unsigned char B1 : 1; + unsigned char : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 1; + unsigned char B1 : 1; + unsigned char : 1; + unsigned char B3 : 1; + unsigned char : 2; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char : 2; + unsigned char B3 : 1; + unsigned char : 1; + unsigned char B1 : 1; + unsigned char : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 1; + unsigned char B1 : 1; + unsigned char : 1; + unsigned char B3 : 1; + unsigned char : 2; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char : 2; + unsigned char B3 : 1; + unsigned char : 1; + unsigned char B1 : 1; + unsigned char : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 1; + unsigned char B1 : 1; + unsigned char : 1; + unsigned char B3 : 1; + unsigned char : 2; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char : 2; + unsigned char B3 : 1; + unsigned char : 1; + unsigned char B1 : 1; + unsigned char : 1; +#endif + } BIT; + } PMR; + char wk3[49]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 6; +#endif + } BIT; + } ODR0; + char wk4[45]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 1; + unsigned char B1 : 1; + unsigned char : 1; + unsigned char B3 : 1; + unsigned char : 2; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char : 2; + unsigned char B3 : 1; + unsigned char : 1; + unsigned char B1 : 1; + unsigned char : 1; +#endif + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 1; + unsigned char B1 : 1; + unsigned char : 1; + unsigned char B3 : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char B3 : 1; + unsigned char : 1; + unsigned char B1 : 1; + unsigned char : 1; +#endif + } BIT; + } DSCR; +}; + +struct st_remc { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ENFLG : 1; + unsigned char INV : 1; + unsigned char FIL : 1; + unsigned char INFLG : 1; + unsigned char EC : 1; + unsigned char : 1; + unsigned char FILSEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char FILSEL : 1; + unsigned char : 1; + unsigned char EC : 1; + unsigned char INFLG : 1; + unsigned char FIL : 1; + unsigned char INV : 1; + unsigned char ENFLG : 1; +#endif + } BIT; + } REMCON0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TYP : 2; + unsigned char EN : 1; + unsigned char CSRC : 4; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char CSRC : 4; + unsigned char EN : 1; + unsigned char TYP : 2; +#endif + } BIT; + } REMCON1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CPFLG : 1; + unsigned char REFLG : 1; + unsigned char DRFLG : 1; + unsigned char BFULFLG : 1; + unsigned char HDFLG : 1; + unsigned char D0FLG : 1; + unsigned char D1FLG : 1; + unsigned char SDFLG : 1; +#else + unsigned char SDFLG : 1; + unsigned char D1FLG : 1; + unsigned char D0FLG : 1; + unsigned char HDFLG : 1; + unsigned char BFULFLG : 1; + unsigned char DRFLG : 1; + unsigned char REFLG : 1; + unsigned char CPFLG : 1; +#endif + } BIT; + } REMSTS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CPINT : 1; + unsigned char REINT : 1; + unsigned char DRINT : 1; + unsigned char BFULINT : 1; + unsigned char HDINT : 1; + unsigned char DINT : 1; + unsigned char : 1; + unsigned char SDINT : 1; +#else + unsigned char SDINT : 1; + unsigned char : 1; + unsigned char DINT : 1; + unsigned char HDINT : 1; + unsigned char BFULINT : 1; + unsigned char DRINT : 1; + unsigned char REINT : 1; + unsigned char CPINT : 1; +#endif + } BIT; + } REMINT; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CPN : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char CPN : 3; +#endif + } BIT; + } REMCPC; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CPD : 8; +#else + unsigned char CPD : 8; +#endif + } BIT; + } REMCPD; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short HDPMIN : 11; + unsigned short : 5; +#else + unsigned short : 5; + unsigned short HDPMIN : 11; +#endif + } BIT; + } HDPMIN; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short HDPMAX : 11; + unsigned short : 5; +#else + unsigned short : 5; + unsigned short HDPMAX : 11; +#endif + } BIT; + } HDPMAX; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char D0PMIN : 8; +#else + unsigned char D0PMIN : 8; +#endif + } BIT; + } D0PMIN; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char D0PMAX : 8; +#else + unsigned char D0PMAX : 8; +#endif + } BIT; + } D0PMAX; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char D1PMIN : 8; +#else + unsigned char D1PMIN : 8; +#endif + } BIT; + } D1PMIN; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char D1PMAX : 8; +#else + unsigned char D1PMAX : 8; +#endif + } BIT; + } D1PMAX; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short SDPMIN : 11; + unsigned short : 5; +#else + unsigned short : 5; + unsigned short SDPMIN : 11; +#endif + } BIT; + } SDPMIN; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short SDPMAX : 11; + unsigned short : 5; +#else + unsigned short : 5; + unsigned short SDPMAX : 11; +#endif + } BIT; + } SDPMAX; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PE : 11; + unsigned short : 5; +#else + unsigned short : 5; + unsigned short PE : 11; +#endif + } BIT; + } REMPE; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LPCE : 1; + unsigned char DNFSL : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char DNFSL : 1; + unsigned char LPCE : 1; +#endif + } BIT; + } REMSTC; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char RBIT : 7; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char RBIT : 7; +#endif + } BIT; + } REMRBIT; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DAT0 : 8; +#else + unsigned char DAT0 : 8; +#endif + } BIT; + } REMDAT0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DAT1 : 8; +#else + unsigned char DAT1 : 8; +#endif + } BIT; + } REMDAT1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DAT2 : 8; +#else + unsigned char DAT2 : 8; +#endif + } BIT; + } REMDAT2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DAT3 : 8; +#else + unsigned char DAT3 : 8; +#endif + } BIT; + } REMDAT3; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DAT4 : 8; +#else + unsigned char DAT4 : 8; +#endif + } BIT; + } REMDAT4; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DAT5 : 8; +#else + unsigned char DAT5 : 8; +#endif + } BIT; + } REMDAT5; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DAT6 : 8; +#else + unsigned char DAT6 : 8; +#endif + } BIT; + } REMDAT6; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DAT7 : 8; +#else + unsigned char DAT7 : 8; +#endif + } BIT; + } REMDAT7; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TIM : 11; + unsigned short : 5; +#else + unsigned short : 5; + unsigned short TIM : 11; +#endif + } BIT; + } REMTIM; +}; + +struct st_remcom { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char HOSE : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char HOSE : 1; +#endif + } BIT; + } HOSCR; +}; + +struct st_riic { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SDAI : 1; + unsigned char SCLI : 1; + unsigned char SDAO : 1; + unsigned char SCLO : 1; + unsigned char SOWP : 1; + unsigned char CLO : 1; + unsigned char IICRST : 1; + unsigned char ICE : 1; +#else + unsigned char ICE : 1; + unsigned char IICRST : 1; + unsigned char CLO : 1; + unsigned char SOWP : 1; + unsigned char SCLO : 1; + unsigned char SDAO : 1; + unsigned char SCLI : 1; + unsigned char SDAI : 1; +#endif + } BIT; + } ICCR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 1; + unsigned char ST : 1; + unsigned char RS : 1; + unsigned char SP : 1; + unsigned char : 1; + unsigned char TRS : 1; + unsigned char MST : 1; + unsigned char BBSY : 1; +#else + unsigned char BBSY : 1; + unsigned char MST : 1; + unsigned char TRS : 1; + unsigned char : 1; + unsigned char SP : 1; + unsigned char RS : 1; + unsigned char ST : 1; + unsigned char : 1; +#endif + } BIT; + } ICCR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BC : 3; + unsigned char BCWP : 1; + unsigned char CKS : 3; + unsigned char MTWP : 1; +#else + unsigned char MTWP : 1; + unsigned char CKS : 3; + unsigned char BCWP : 1; + unsigned char BC : 3; +#endif + } BIT; + } ICMR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TMOS : 1; + unsigned char TMOL : 1; + unsigned char TMOH : 1; + unsigned char : 1; + unsigned char SDDL : 3; + unsigned char DLCS : 1; +#else + unsigned char DLCS : 1; + unsigned char SDDL : 3; + unsigned char : 1; + unsigned char TMOH : 1; + unsigned char TMOL : 1; + unsigned char TMOS : 1; +#endif + } BIT; + } ICMR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NF : 2; + unsigned char ACKBR : 1; + unsigned char ACKBT : 1; + unsigned char ACKWP : 1; + unsigned char RDRFS : 1; + unsigned char WAIT : 1; + unsigned char SMBS : 1; +#else + unsigned char SMBS : 1; + unsigned char WAIT : 1; + unsigned char RDRFS : 1; + unsigned char ACKWP : 1; + unsigned char ACKBT : 1; + unsigned char ACKBR : 1; + unsigned char NF : 2; +#endif + } BIT; + } ICMR3; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TMOE : 1; + unsigned char MALE : 1; + unsigned char NALE : 1; + unsigned char SALE : 1; + unsigned char NACKE : 1; + unsigned char NFE : 1; + unsigned char SCLE : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char SCLE : 1; + unsigned char NFE : 1; + unsigned char NACKE : 1; + unsigned char SALE : 1; + unsigned char NALE : 1; + unsigned char MALE : 1; + unsigned char TMOE : 1; +#endif + } BIT; + } ICFER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SAR0E : 1; + unsigned char SAR1E : 1; + unsigned char SAR2E : 1; + unsigned char GCAE : 1; + unsigned char : 1; + unsigned char DIDE : 1; + unsigned char : 1; + unsigned char HOAE : 1; +#else + unsigned char HOAE : 1; + unsigned char : 1; + unsigned char DIDE : 1; + unsigned char : 1; + unsigned char GCAE : 1; + unsigned char SAR2E : 1; + unsigned char SAR1E : 1; + unsigned char SAR0E : 1; +#endif + } BIT; + } ICSER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TMOIE : 1; + unsigned char ALIE : 1; + unsigned char STIE : 1; + unsigned char SPIE : 1; + unsigned char NAKIE : 1; + unsigned char RIE : 1; + unsigned char TEIE : 1; + unsigned char TIE : 1; +#else + unsigned char TIE : 1; + unsigned char TEIE : 1; + unsigned char RIE : 1; + unsigned char NAKIE : 1; + unsigned char SPIE : 1; + unsigned char STIE : 1; + unsigned char ALIE : 1; + unsigned char TMOIE : 1; +#endif + } BIT; + } ICIER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char AAS0 : 1; + unsigned char AAS1 : 1; + unsigned char AAS2 : 1; + unsigned char GCA : 1; + unsigned char : 1; + unsigned char DID : 1; + unsigned char : 1; + unsigned char HOA : 1; +#else + unsigned char HOA : 1; + unsigned char : 1; + unsigned char DID : 1; + unsigned char : 1; + unsigned char GCA : 1; + unsigned char AAS2 : 1; + unsigned char AAS1 : 1; + unsigned char AAS0 : 1; +#endif + } BIT; + } ICSR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TMOF : 1; + unsigned char AL : 1; + unsigned char START : 1; + unsigned char STOP : 1; + unsigned char NACKF : 1; + unsigned char RDRF : 1; + unsigned char TEND : 1; + unsigned char TDRE : 1; +#else + unsigned char TDRE : 1; + unsigned char TEND : 1; + unsigned char RDRF : 1; + unsigned char NACKF : 1; + unsigned char STOP : 1; + unsigned char START : 1; + unsigned char AL : 1; + unsigned char TMOF : 1; +#endif + } BIT; + } ICSR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SVA0 : 1; + unsigned char SVA : 7; +#else + unsigned char SVA : 7; + unsigned char SVA0 : 1; +#endif + } BIT; + } SARL0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char FS : 1; + unsigned char SVA : 2; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SVA : 2; + unsigned char FS : 1; +#endif + } BIT; + } SARU0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SVA0 : 1; + unsigned char SVA : 7; +#else + unsigned char SVA : 7; + unsigned char SVA0 : 1; +#endif + } BIT; + } SARL1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char FS : 1; + unsigned char SVA : 2; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SVA : 2; + unsigned char FS : 1; +#endif + } BIT; + } SARU1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SVA0 : 1; + unsigned char SVA : 7; +#else + unsigned char SVA : 7; + unsigned char SVA0 : 1; +#endif + } BIT; + } SARL2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char FS : 1; + unsigned char SVA : 2; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SVA : 2; + unsigned char FS : 1; +#endif + } BIT; + } SARU2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BRL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char BRL : 5; +#endif + } BIT; + } ICBRL; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BRH : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char BRH : 5; +#endif + } BIT; + } ICBRH; + unsigned char ICDRT; + unsigned char ICDRR; +}; + +struct st_rspi { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SPMS : 1; + unsigned char TXMD : 1; + unsigned char MODFEN : 1; + unsigned char MSTR : 1; + unsigned char SPEIE : 1; + unsigned char SPTIE : 1; + unsigned char SPE : 1; + unsigned char SPRIE : 1; +#else + unsigned char SPRIE : 1; + unsigned char SPE : 1; + unsigned char SPTIE : 1; + unsigned char SPEIE : 1; + unsigned char MSTR : 1; + unsigned char MODFEN : 1; + unsigned char TXMD : 1; + unsigned char SPMS : 1; +#endif + } BIT; + } SPCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SSL0P : 1; + unsigned char SSL1P : 1; + unsigned char SSL2P : 1; + unsigned char SSL3P : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char SSL3P : 1; + unsigned char SSL2P : 1; + unsigned char SSL1P : 1; + unsigned char SSL0P : 1; +#endif + } BIT; + } SSLP; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SPLP : 1; + unsigned char SPLP2 : 1; + unsigned char : 2; + unsigned char MOIFV : 1; + unsigned char MOIFE : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char MOIFE : 1; + unsigned char MOIFV : 1; + unsigned char : 2; + unsigned char SPLP2 : 1; + unsigned char SPLP : 1; +#endif + } BIT; + } SPPCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OVRF : 1; + unsigned char IDLNF : 1; + unsigned char MODF : 1; + unsigned char PERF : 1; + unsigned char : 1; + unsigned char SPTEF : 1; + unsigned char : 1; + unsigned char SPRF : 1; +#else + unsigned char SPRF : 1; + unsigned char : 1; + unsigned char SPTEF : 1; + unsigned char : 1; + unsigned char PERF : 1; + unsigned char MODF : 1; + unsigned char IDLNF : 1; + unsigned char OVRF : 1; +#endif + } BIT; + } SPSR; + union { + unsigned long LONG; + struct { + unsigned short H; + } WORD; + } SPDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SPSLN : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SPSLN : 3; +#endif + } BIT; + } SPSCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SPCP : 3; + unsigned char : 1; + unsigned char SPECM : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char SPECM : 3; + unsigned char : 1; + unsigned char SPCP : 3; +#endif + } BIT; + } SPSSR; + unsigned char SPBR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SPFC : 2; + unsigned char : 2; + unsigned char SPRDTD : 1; + unsigned char SPLW : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char SPLW : 1; + unsigned char SPRDTD : 1; + unsigned char : 2; + unsigned char SPFC : 2; +#endif + } BIT; + } SPDCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SCKDL : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SCKDL : 3; +#endif + } BIT; + } SPCKD; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLNDL : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SLNDL : 3; +#endif + } BIT; + } SSLND; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SPNDL : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SPNDL : 3; +#endif + } BIT; + } SPND; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SPPE : 1; + unsigned char SPOE : 1; + unsigned char SPIIE : 1; + unsigned char PTE : 1; + unsigned char SCKASE : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char SCKASE : 1; + unsigned char PTE : 1; + unsigned char SPIIE : 1; + unsigned char SPOE : 1; + unsigned char SPPE : 1; +#endif + } BIT; + } SPCR2; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CPHA : 1; + unsigned short CPOL : 1; + unsigned short BRDV : 2; + unsigned short SSLA : 3; + unsigned short SSLKP : 1; + unsigned short SPB : 4; + unsigned short LSBF : 1; + unsigned short SPNDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SCKDEN : 1; +#else + unsigned short SCKDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SPNDEN : 1; + unsigned short LSBF : 1; + unsigned short SPB : 4; + unsigned short SSLKP : 1; + unsigned short SSLA : 3; + unsigned short BRDV : 2; + unsigned short CPOL : 1; + unsigned short CPHA : 1; +#endif + } BIT; + } SPCMD0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CPHA : 1; + unsigned short CPOL : 1; + unsigned short BRDV : 2; + unsigned short SSLA : 3; + unsigned short SSLKP : 1; + unsigned short SPB : 4; + unsigned short LSBF : 1; + unsigned short SPNDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SCKDEN : 1; +#else + unsigned short SCKDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SPNDEN : 1; + unsigned short LSBF : 1; + unsigned short SPB : 4; + unsigned short SSLKP : 1; + unsigned short SSLA : 3; + unsigned short BRDV : 2; + unsigned short CPOL : 1; + unsigned short CPHA : 1; +#endif + } BIT; + } SPCMD1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CPHA : 1; + unsigned short CPOL : 1; + unsigned short BRDV : 2; + unsigned short SSLA : 3; + unsigned short SSLKP : 1; + unsigned short SPB : 4; + unsigned short LSBF : 1; + unsigned short SPNDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SCKDEN : 1; +#else + unsigned short SCKDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SPNDEN : 1; + unsigned short LSBF : 1; + unsigned short SPB : 4; + unsigned short SSLKP : 1; + unsigned short SSLA : 3; + unsigned short BRDV : 2; + unsigned short CPOL : 1; + unsigned short CPHA : 1; +#endif + } BIT; + } SPCMD2; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CPHA : 1; + unsigned short CPOL : 1; + unsigned short BRDV : 2; + unsigned short SSLA : 3; + unsigned short SSLKP : 1; + unsigned short SPB : 4; + unsigned short LSBF : 1; + unsigned short SPNDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SCKDEN : 1; +#else + unsigned short SCKDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SPNDEN : 1; + unsigned short LSBF : 1; + unsigned short SPB : 4; + unsigned short SSLKP : 1; + unsigned short SSLA : 3; + unsigned short BRDV : 2; + unsigned short CPOL : 1; + unsigned short CPHA : 1; +#endif + } BIT; + } SPCMD3; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CPHA : 1; + unsigned short CPOL : 1; + unsigned short BRDV : 2; + unsigned short SSLA : 3; + unsigned short SSLKP : 1; + unsigned short SPB : 4; + unsigned short LSBF : 1; + unsigned short SPNDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SCKDEN : 1; +#else + unsigned short SCKDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SPNDEN : 1; + unsigned short LSBF : 1; + unsigned short SPB : 4; + unsigned short SSLKP : 1; + unsigned short SSLA : 3; + unsigned short BRDV : 2; + unsigned short CPOL : 1; + unsigned short CPHA : 1; +#endif + } BIT; + } SPCMD4; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CPHA : 1; + unsigned short CPOL : 1; + unsigned short BRDV : 2; + unsigned short SSLA : 3; + unsigned short SSLKP : 1; + unsigned short SPB : 4; + unsigned short LSBF : 1; + unsigned short SPNDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SCKDEN : 1; +#else + unsigned short SCKDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SPNDEN : 1; + unsigned short LSBF : 1; + unsigned short SPB : 4; + unsigned short SSLKP : 1; + unsigned short SSLA : 3; + unsigned short BRDV : 2; + unsigned short CPOL : 1; + unsigned short CPHA : 1; +#endif + } BIT; + } SPCMD5; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CPHA : 1; + unsigned short CPOL : 1; + unsigned short BRDV : 2; + unsigned short SSLA : 3; + unsigned short SSLKP : 1; + unsigned short SPB : 4; + unsigned short LSBF : 1; + unsigned short SPNDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SCKDEN : 1; +#else + unsigned short SCKDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SPNDEN : 1; + unsigned short LSBF : 1; + unsigned short SPB : 4; + unsigned short SSLKP : 1; + unsigned short SSLA : 3; + unsigned short BRDV : 2; + unsigned short CPOL : 1; + unsigned short CPHA : 1; +#endif + } BIT; + } SPCMD6; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CPHA : 1; + unsigned short CPOL : 1; + unsigned short BRDV : 2; + unsigned short SSLA : 3; + unsigned short SSLKP : 1; + unsigned short SPB : 4; + unsigned short LSBF : 1; + unsigned short SPNDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SCKDEN : 1; +#else + unsigned short SCKDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SPNDEN : 1; + unsigned short LSBF : 1; + unsigned short SPB : 4; + unsigned short SSLKP : 1; + unsigned short SSLA : 3; + unsigned short BRDV : 2; + unsigned short CPOL : 1; + unsigned short CPHA : 1; +#endif + } BIT; + } SPCMD7; +}; + +struct st_rtc { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char F64HZ : 1; + unsigned char F32HZ : 1; + unsigned char F16HZ : 1; + unsigned char F8HZ : 1; + unsigned char F4HZ : 1; + unsigned char F2HZ : 1; + unsigned char F1HZ : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char F1HZ : 1; + unsigned char F2HZ : 1; + unsigned char F4HZ : 1; + unsigned char F8HZ : 1; + unsigned char F16HZ : 1; + unsigned char F32HZ : 1; + unsigned char F64HZ : 1; +#endif + } BIT; + } R64CNT; + char wk0[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SEC1 : 4; + unsigned char SEC10 : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char SEC10 : 3; + unsigned char SEC1 : 4; +#endif + } BIT; + } RSECCNT; + char wk1[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MIN1 : 4; + unsigned char MIN10 : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char MIN10 : 3; + unsigned char MIN1 : 4; +#endif + } BIT; + } RMINCNT; + char wk2[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char HR1 : 4; + unsigned char HR10 : 2; + unsigned char PM : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char PM : 1; + unsigned char HR10 : 2; + unsigned char HR1 : 4; +#endif + } BIT; + } RHRCNT; + char wk3[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DAYW : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char DAYW : 3; +#endif + } BIT; + } RWKCNT; + char wk4[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DATE1 : 4; + unsigned char DATE10 : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char DATE10 : 2; + unsigned char DATE1 : 4; +#endif + } BIT; + } RDAYCNT; + char wk5[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MON1 : 4; + unsigned char MON10 : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char MON10 : 1; + unsigned char MON1 : 4; +#endif + } BIT; + } RMONCNT; + char wk6[1]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short YR1 : 4; + unsigned short YR10 : 4; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short YR10 : 4; + unsigned short YR1 : 4; +#endif + } BIT; + } RYRCNT; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SEC1 : 4; + unsigned char SEC10 : 3; + unsigned char ENB : 1; +#else + unsigned char ENB : 1; + unsigned char SEC10 : 3; + unsigned char SEC1 : 4; +#endif + } BIT; + } RSECAR; + char wk7[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MIN1 : 4; + unsigned char MIN10 : 3; + unsigned char ENB : 1; +#else + unsigned char ENB : 1; + unsigned char MIN10 : 3; + unsigned char MIN1 : 4; +#endif + } BIT; + } RMINAR; + char wk8[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char HR1 : 4; + unsigned char HR10 : 2; + unsigned char PM : 1; + unsigned char ENB : 1; +#else + unsigned char ENB : 1; + unsigned char PM : 1; + unsigned char HR10 : 2; + unsigned char HR1 : 4; +#endif + } BIT; + } RHRAR; + char wk9[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DAYW : 3; + unsigned char : 4; + unsigned char ENB : 1; +#else + unsigned char ENB : 1; + unsigned char : 4; + unsigned char DAYW : 3; +#endif + } BIT; + } RWKAR; + char wk10[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DATE1 : 4; + unsigned char DATE10 : 2; + unsigned char : 1; + unsigned char ENB : 1; +#else + unsigned char ENB : 1; + unsigned char : 1; + unsigned char DATE10 : 2; + unsigned char DATE1 : 4; +#endif + } BIT; + } RDAYAR; + char wk11[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MON1 : 4; + unsigned char MON10 : 1; + unsigned char : 2; + unsigned char ENB : 1; +#else + unsigned char ENB : 1; + unsigned char : 2; + unsigned char MON10 : 1; + unsigned char MON1 : 4; +#endif + } BIT; + } RMONAR; + char wk12[1]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short YR1 : 4; + unsigned short YR10 : 4; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short YR10 : 4; + unsigned short YR1 : 4; +#endif + } BIT; + } RYRAR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char ENB : 1; +#else + unsigned char ENB : 1; + unsigned char : 7; +#endif + } BIT; + } RYRAREN; + char wk13[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char AIE : 1; + unsigned char CIE : 1; + unsigned char PIE : 1; + unsigned char RTCOS : 1; + unsigned char PES : 4; +#else + unsigned char PES : 4; + unsigned char RTCOS : 1; + unsigned char PIE : 1; + unsigned char CIE : 1; + unsigned char AIE : 1; +#endif + } BIT; + } RCR1; + char wk14[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char START : 1; + unsigned char RESET : 1; + unsigned char ADJ30 : 1; + unsigned char RTCOE : 1; + unsigned char AADJE : 1; + unsigned char AADJP : 1; + unsigned char HR24 : 1; + unsigned char CNTMD : 1; +#else + unsigned char CNTMD : 1; + unsigned char HR24 : 1; + unsigned char AADJP : 1; + unsigned char AADJE : 1; + unsigned char RTCOE : 1; + unsigned char ADJ30 : 1; + unsigned char RESET : 1; + unsigned char START : 1; +#endif + } BIT; + } RCR2; + char wk15[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char RTCEN : 1; + unsigned char RTCDV : 3; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char RTCDV : 3; + unsigned char RTCEN : 1; +#endif + } BIT; + } RCR3; + char wk16[7]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ADJ : 6; + unsigned char PMADJ : 2; +#else + unsigned char PMADJ : 2; + unsigned char ADJ : 6; +#endif + } BIT; + } RADJ; +}; + +struct st_rtcb { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNT : 8; +#else + unsigned char BCNT : 8; +#endif + } BIT; + } BCNT0; + char wk0[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNT : 8; +#else + unsigned char BCNT : 8; +#endif + } BIT; + } BCNT1; + char wk1[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNT : 8; +#else + unsigned char BCNT : 8; +#endif + } BIT; + } BCNT2; + char wk2[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNT : 8; +#else + unsigned char BCNT : 8; +#endif + } BIT; + } BCNT3; + char wk3[7]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNTAR : 8; +#else + unsigned char BCNTAR : 8; +#endif + } BIT; + } BCNT0AR; + char wk4[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNTAR : 8; +#else + unsigned char BCNTAR : 8; +#endif + } BIT; + } BCNT1AR; + char wk5[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNTAR : 8; +#else + unsigned char BCNTAR : 8; +#endif + } BIT; + } BCNT2AR; + char wk6[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNTAR : 8; +#else + unsigned char BCNTAR : 8; +#endif + } BIT; + } BCNT3AR; + char wk7[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ENB : 8; +#else + unsigned char ENB : 8; +#endif + } BIT; + } BCNT0AER; + char wk8[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ENB : 8; +#else + unsigned char ENB : 8; +#endif + } BIT; + } BCNT1AER; + char wk9[1]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ENB : 8; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short ENB : 8; +#endif + } BIT; + } BCNT2AER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ENB : 8; +#else + unsigned char ENB : 8; +#endif + } BIT; + } BCNT3AER; +}; + +struct st_s12ad { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short DBLANS : 5; + unsigned short : 1; + unsigned short GBADIE : 1; + unsigned short DBLE : 1; + unsigned short EXTRG : 1; + unsigned short TRGE : 1; + unsigned short ADHSC : 1; + unsigned short : 1; + unsigned short ADIE : 1; + unsigned short ADCS : 2; + unsigned short ADST : 1; +#else + unsigned short ADST : 1; + unsigned short ADCS : 2; + unsigned short ADIE : 1; + unsigned short : 1; + unsigned short ADHSC : 1; + unsigned short TRGE : 1; + unsigned short EXTRG : 1; + unsigned short DBLE : 1; + unsigned short GBADIE : 1; + unsigned short : 1; + unsigned short DBLANS : 5; +#endif + } BIT; + } ADCSR; + char wk0[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ANSA000 : 1; + unsigned short ANSA001 : 1; + unsigned short ANSA002 : 1; + unsigned short ANSA003 : 1; + unsigned short ANSA004 : 1; + unsigned short ANSA005 : 1; + unsigned short ANSA006 : 1; + unsigned short ANSA007 : 1; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short ANSA007 : 1; + unsigned short ANSA006 : 1; + unsigned short ANSA005 : 1; + unsigned short ANSA004 : 1; + unsigned short ANSA003 : 1; + unsigned short ANSA002 : 1; + unsigned short ANSA001 : 1; + unsigned short ANSA000 : 1; +#endif + } BIT; + } ADANSA0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ANSA100 : 1; + unsigned short ANSA101 : 1; + unsigned short ANSA102 : 1; + unsigned short ANSA103 : 1; + unsigned short ANSA104 : 1; + unsigned short ANSA105 : 1; + unsigned short ANSA106 : 1; + unsigned short ANSA107 : 1; + unsigned short ANSA108 : 1; + unsigned short ANSA109 : 1; + unsigned short ANSA110 : 1; + unsigned short ANSA111 : 1; + unsigned short ANSA112 : 1; + unsigned short ANSA113 : 1; + unsigned short ANSA114 : 1; + unsigned short ANSA115 : 1; +#else + unsigned short ANSA115 : 1; + unsigned short ANSA114 : 1; + unsigned short ANSA113 : 1; + unsigned short ANSA112 : 1; + unsigned short ANSA111 : 1; + unsigned short ANSA110 : 1; + unsigned short ANSA109 : 1; + unsigned short ANSA108 : 1; + unsigned short ANSA107 : 1; + unsigned short ANSA106 : 1; + unsigned short ANSA105 : 1; + unsigned short ANSA104 : 1; + unsigned short ANSA103 : 1; + unsigned short ANSA102 : 1; + unsigned short ANSA101 : 1; + unsigned short ANSA100 : 1; +#endif + } BIT; + } ADANSA1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ADS000 : 1; + unsigned short ADS001 : 1; + unsigned short ADS002 : 1; + unsigned short ADS003 : 1; + unsigned short ADS004 : 1; + unsigned short ADS005 : 1; + unsigned short ADS006 : 1; + unsigned short ADS007 : 1; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short ADS007 : 1; + unsigned short ADS006 : 1; + unsigned short ADS005 : 1; + unsigned short ADS004 : 1; + unsigned short ADS003 : 1; + unsigned short ADS002 : 1; + unsigned short ADS001 : 1; + unsigned short ADS000 : 1; +#endif + } BIT; + } ADADS0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ADS100 : 1; + unsigned short ADS101 : 1; + unsigned short ADS102 : 1; + unsigned short ADS103 : 1; + unsigned short ADS104 : 1; + unsigned short ADS105 : 1; + unsigned short ADS106 : 1; + unsigned short ADS107 : 1; + unsigned short ADS108 : 1; + unsigned short ADS109 : 1; + unsigned short ADS110 : 1; + unsigned short ADS111 : 1; + unsigned short ADS112 : 1; + unsigned short ADS113 : 1; + unsigned short ADS114 : 1; + unsigned short ADS115 : 1; +#else + unsigned short ADS115 : 1; + unsigned short ADS114 : 1; + unsigned short ADS113 : 1; + unsigned short ADS112 : 1; + unsigned short ADS111 : 1; + unsigned short ADS110 : 1; + unsigned short ADS109 : 1; + unsigned short ADS108 : 1; + unsigned short ADS107 : 1; + unsigned short ADS106 : 1; + unsigned short ADS105 : 1; + unsigned short ADS104 : 1; + unsigned short ADS103 : 1; + unsigned short ADS102 : 1; + unsigned short ADS101 : 1; + unsigned short ADS100 : 1; +#endif + } BIT; + } ADADS1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ADC : 3; + unsigned char : 4; + unsigned char AVEE : 1; +#else + unsigned char AVEE : 1; + unsigned char : 4; + unsigned char ADC : 3; +#endif + } BIT; + } ADADC; + char wk1[1]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 5; + unsigned short ACE : 1; + unsigned short : 2; + unsigned short DIAGVAL : 2; + unsigned short DIAGLD : 1; + unsigned short DIAGM : 1; + unsigned short : 3; + unsigned short ADRFMT : 1; +#else + unsigned short ADRFMT : 1; + unsigned short : 3; + unsigned short DIAGM : 1; + unsigned short DIAGLD : 1; + unsigned short DIAGVAL : 2; + unsigned short : 2; + unsigned short ACE : 1; + unsigned short : 5; +#endif + } BIT; + } ADCER; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TRSB : 6; + unsigned short : 2; + unsigned short TRSA : 6; + unsigned short : 2; +#else + unsigned short : 2; + unsigned short TRSA : 6; + unsigned short : 2; + unsigned short TRSB : 6; +#endif + } BIT; + } ADSTRGR; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TSSAD : 1; + unsigned short OCSAD : 1; + unsigned short : 6; + unsigned short TSSA : 1; + unsigned short OCSA : 1; + unsigned short : 6; +#else + unsigned short : 6; + unsigned short OCSA : 1; + unsigned short TSSA : 1; + unsigned short : 6; + unsigned short OCSAD : 1; + unsigned short TSSAD : 1; +#endif + } BIT; + } ADEXICR; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ANSB000 : 1; + unsigned short ANSB001 : 1; + unsigned short ANSB002 : 1; + unsigned short ANSB003 : 1; + unsigned short ANSB004 : 1; + unsigned short ANSB005 : 1; + unsigned short ANSB006 : 1; + unsigned short ANSB007 : 1; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short ANSB007 : 1; + unsigned short ANSB006 : 1; + unsigned short ANSB005 : 1; + unsigned short ANSB004 : 1; + unsigned short ANSB003 : 1; + unsigned short ANSB002 : 1; + unsigned short ANSB001 : 1; + unsigned short ANSB000 : 1; +#endif + } BIT; + } ADANSB0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ANSB100 : 1; + unsigned short ANSB101 : 1; + unsigned short ANSB102 : 1; + unsigned short ANSB103 : 1; + unsigned short ANSB104 : 1; + unsigned short ANSB105 : 1; + unsigned short ANSB106 : 1; + unsigned short ANSB107 : 1; + unsigned short ANSB108 : 1; + unsigned short ANSB109 : 1; + unsigned short ANSB110 : 1; + unsigned short ANSB111 : 1; + unsigned short ANSB112 : 1; + unsigned short ANSB113 : 1; + unsigned short ANSB114 : 1; + unsigned short ANSB115 : 1; +#else + unsigned short ANSB115 : 1; + unsigned short ANSB114 : 1; + unsigned short ANSB113 : 1; + unsigned short ANSB112 : 1; + unsigned short ANSB111 : 1; + unsigned short ANSB110 : 1; + unsigned short ANSB109 : 1; + unsigned short ANSB108 : 1; + unsigned short ANSB107 : 1; + unsigned short ANSB106 : 1; + unsigned short ANSB105 : 1; + unsigned short ANSB104 : 1; + unsigned short ANSB103 : 1; + unsigned short ANSB102 : 1; + unsigned short ANSB101 : 1; + unsigned short ANSB100 : 1; +#endif + } BIT; + } ADANSB1; + unsigned short ADDBLDR; + unsigned short ADTSDR; + unsigned short ADOCDR; + union { + unsigned short WORD; + union { + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short AD : 12; + unsigned short : 2; + unsigned short DIAGST : 2; +#else + unsigned short DIAGST : 2; + unsigned short : 2; + unsigned short AD : 12; +#endif + } RIGHT; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short DIAGST : 2; + unsigned short : 2; + unsigned short AD : 12; +#else + unsigned short AD : 12; + unsigned short : 2; + unsigned short DIAGST : 2; +#endif + } LEFT; + } BIT; + } ADRD; + unsigned short ADDR0; + unsigned short ADDR1; + unsigned short ADDR2; + unsigned short ADDR3; + unsigned short ADDR4; + unsigned short ADDR5; + unsigned short ADDR6; + unsigned short ADDR7; + char wk2[16]; + unsigned short ADDR16; + unsigned short ADDR17; + unsigned short ADDR18; + unsigned short ADDR19; + unsigned short ADDR20; + unsigned short ADDR21; + unsigned short ADDR22; + unsigned short ADDR23; + unsigned short ADDR24; + unsigned short ADDR25; + unsigned short ADDR26; + unsigned short ADDR27; + unsigned short ADDR28; + unsigned short ADDR29; + unsigned short ADDR30; + unsigned short ADDR31; + char wk3[26]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ADNDIS : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char ADNDIS : 5; +#endif + } BIT; + } ADDISCR; + char wk4[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELCC : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char ELCC : 2; +#endif + } BIT; + } ADELCCR; + char wk5[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PGS : 1; + unsigned short GBRSCN : 1; + unsigned short : 13; + unsigned short GBRP : 1; +#else + unsigned short GBRP : 1; + unsigned short : 13; + unsigned short GBRSCN : 1; + unsigned short PGS : 1; +#endif + } BIT; + } ADGSPCR; + char wk6[8]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char HVSEL : 2; + unsigned char : 2; + unsigned char LVSEL : 1; + unsigned char : 2; + unsigned char ADSLP : 1; +#else + unsigned char ADSLP : 1; + unsigned char : 2; + unsigned char LVSEL : 1; + unsigned char : 2; + unsigned char HVSEL : 2; +#endif + } BIT; + } ADHVREFCNT; + char wk7[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MONCOMB : 1; + unsigned char : 3; + unsigned char MONCMPA : 1; + unsigned char MONCMPB : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char MONCMPB : 1; + unsigned char MONCMPA : 1; + unsigned char : 3; + unsigned char MONCOMB : 1; +#endif + } BIT; + } ADWINMON; + char wk8[3]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMPAB : 2; + unsigned short : 7; + unsigned short CMPBE : 1; + unsigned short : 1; + unsigned short CMPAE : 1; + unsigned short : 2; + unsigned short WCMPE : 1; + unsigned short : 1; +#else + unsigned short : 1; + unsigned short WCMPE : 1; + unsigned short : 2; + unsigned short CMPAE : 1; + unsigned short : 1; + unsigned short CMPBE : 1; + unsigned short : 7; + unsigned short CMPAB : 2; +#endif + } BIT; + } ADCMPCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CMPTSA : 1; + unsigned char CMPOCA : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char CMPOCA : 1; + unsigned char CMPTSA : 1; +#endif + } BIT; + } ADCMPANSER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CMPLTSA : 1; + unsigned char CMPLOCA : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char CMPLOCA : 1; + unsigned char CMPLTSA : 1; +#endif + } BIT; + } ADCMPLER; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMPCHA000 : 1; + unsigned short CMPCHA001 : 1; + unsigned short CMPCHA002 : 1; + unsigned short CMPCHA003 : 1; + unsigned short CMPCHA004 : 1; + unsigned short CMPCHA005 : 1; + unsigned short CMPCHA006 : 1; + unsigned short CMPCHA007 : 1; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short CMPCHA007 : 1; + unsigned short CMPCHA006 : 1; + unsigned short CMPCHA005 : 1; + unsigned short CMPCHA004 : 1; + unsigned short CMPCHA003 : 1; + unsigned short CMPCHA002 : 1; + unsigned short CMPCHA001 : 1; + unsigned short CMPCHA000 : 1; +#endif + } BIT; + } ADCMPANSR0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMPCHA100 : 1; + unsigned short CMPCHA101 : 1; + unsigned short CMPCHA102 : 1; + unsigned short CMPCHA103 : 1; + unsigned short CMPCHA104 : 1; + unsigned short CMPCHA105 : 1; + unsigned short CMPCHA106 : 1; + unsigned short CMPCHA107 : 1; + unsigned short CMPCHA108 : 1; + unsigned short CMPCHA109 : 1; + unsigned short CMPCHA110 : 1; + unsigned short CMPCHA111 : 1; + unsigned short CMPCHA112 : 1; + unsigned short CMPCHA113 : 1; + unsigned short CMPCHA114 : 1; + unsigned short CMPCHA115 : 1; +#else + unsigned short CMPCHA115 : 1; + unsigned short CMPCHA114 : 1; + unsigned short CMPCHA113 : 1; + unsigned short CMPCHA112 : 1; + unsigned short CMPCHA111 : 1; + unsigned short CMPCHA110 : 1; + unsigned short CMPCHA109 : 1; + unsigned short CMPCHA108 : 1; + unsigned short CMPCHA107 : 1; + unsigned short CMPCHA106 : 1; + unsigned short CMPCHA105 : 1; + unsigned short CMPCHA104 : 1; + unsigned short CMPCHA103 : 1; + unsigned short CMPCHA102 : 1; + unsigned short CMPCHA101 : 1; + unsigned short CMPCHA100 : 1; +#endif + } BIT; + } ADCMPANSR1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMPLCHA000 : 1; + unsigned short CMPLCHA001 : 1; + unsigned short CMPLCHA002 : 1; + unsigned short CMPLCHA003 : 1; + unsigned short CMPLCHA004 : 1; + unsigned short CMPLCHA005 : 1; + unsigned short CMPLCHA006 : 1; + unsigned short CMPLCHA007 : 1; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short CMPLCHA007 : 1; + unsigned short CMPLCHA006 : 1; + unsigned short CMPLCHA005 : 1; + unsigned short CMPLCHA004 : 1; + unsigned short CMPLCHA003 : 1; + unsigned short CMPLCHA002 : 1; + unsigned short CMPLCHA001 : 1; + unsigned short CMPLCHA000 : 1; +#endif + } BIT; + } ADCMPLR0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMPLCHA100 : 1; + unsigned short CMPLCHA101 : 1; + unsigned short CMPLCHA102 : 1; + unsigned short CMPLCHA103 : 1; + unsigned short CMPLCHA104 : 1; + unsigned short CMPLCHA105 : 1; + unsigned short CMPLCHA106 : 1; + unsigned short CMPLCHA107 : 1; + unsigned short CMPLCHA108 : 1; + unsigned short CMPLCHA109 : 1; + unsigned short CMPLCHA110 : 1; + unsigned short CMPLCHA111 : 1; + unsigned short CMPLCHA112 : 1; + unsigned short CMPLCHA113 : 1; + unsigned short CMPLCHA114 : 1; + unsigned short CMPLCHA115 : 1; +#else + unsigned short CMPLCHA115 : 1; + unsigned short CMPLCHA114 : 1; + unsigned short CMPLCHA113 : 1; + unsigned short CMPLCHA112 : 1; + unsigned short CMPLCHA111 : 1; + unsigned short CMPLCHA110 : 1; + unsigned short CMPLCHA109 : 1; + unsigned short CMPLCHA108 : 1; + unsigned short CMPLCHA107 : 1; + unsigned short CMPLCHA106 : 1; + unsigned short CMPLCHA105 : 1; + unsigned short CMPLCHA104 : 1; + unsigned short CMPLCHA103 : 1; + unsigned short CMPLCHA102 : 1; + unsigned short CMPLCHA101 : 1; + unsigned short CMPLCHA100 : 1; +#endif + } BIT; + } ADCMPLR1; + unsigned short ADCMPDR0; + unsigned short ADCMPDR1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMPSTCHA000 : 1; + unsigned short CMPSTCHA001 : 1; + unsigned short CMPSTCHA002 : 1; + unsigned short CMPSTCHA003 : 1; + unsigned short CMPSTCHA004 : 1; + unsigned short CMPSTCHA005 : 1; + unsigned short CMPSTCHA006 : 1; + unsigned short CMPSTCHA007 : 1; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short CMPSTCHA007 : 1; + unsigned short CMPSTCHA006 : 1; + unsigned short CMPSTCHA005 : 1; + unsigned short CMPSTCHA004 : 1; + unsigned short CMPSTCHA003 : 1; + unsigned short CMPSTCHA002 : 1; + unsigned short CMPSTCHA001 : 1; + unsigned short CMPSTCHA000 : 1; +#endif + } BIT; + } ADCMPSR0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMPSTCHA100 : 1; + unsigned short CMPSTCHA101 : 1; + unsigned short CMPSTCHA102 : 1; + unsigned short CMPSTCHA103 : 1; + unsigned short CMPSTCHA104 : 1; + unsigned short CMPSTCHA105 : 1; + unsigned short CMPSTCHA106 : 1; + unsigned short CMPSTCHA107 : 1; + unsigned short CMPSTCHA108 : 1; + unsigned short CMPSTCHA109 : 1; + unsigned short CMPSTCHA110 : 1; + unsigned short CMPSTCHA111 : 1; + unsigned short CMPSTCHA112 : 1; + unsigned short CMPSTCHA113 : 1; + unsigned short CMPSTCHA114 : 1; + unsigned short CMPSTCHA115 : 1; +#else + unsigned short CMPSTCHA115 : 1; + unsigned short CMPSTCHA114 : 1; + unsigned short CMPSTCHA113 : 1; + unsigned short CMPSTCHA112 : 1; + unsigned short CMPSTCHA111 : 1; + unsigned short CMPSTCHA110 : 1; + unsigned short CMPSTCHA109 : 1; + unsigned short CMPSTCHA108 : 1; + unsigned short CMPSTCHA107 : 1; + unsigned short CMPSTCHA106 : 1; + unsigned short CMPSTCHA105 : 1; + unsigned short CMPSTCHA104 : 1; + unsigned short CMPSTCHA103 : 1; + unsigned short CMPSTCHA102 : 1; + unsigned short CMPSTCHA101 : 1; + unsigned short CMPSTCHA100 : 1; +#endif + } BIT; + } ADCMPSR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CMPSTTSA : 1; + unsigned char CMPSTOCA : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char CMPSTOCA : 1; + unsigned char CMPSTTSA : 1; +#endif + } BIT; + } ADCMPSER; + char wk9[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CMPCHB : 6; + unsigned char : 1; + unsigned char CMPLB : 1; +#else + unsigned char CMPLB : 1; + unsigned char : 1; + unsigned char CMPCHB : 6; +#endif + } BIT; + } ADCMPBNSR; + char wk10[1]; + unsigned short ADWINLLB; + unsigned short ADWINULB; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CMPSTB : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char CMPSTB : 1; +#endif + } BIT; + } ADCMPBSR; + char wk11[3]; + unsigned short ADBUF0; + unsigned short ADBUF1; + unsigned short ADBUF2; + unsigned short ADBUF3; + unsigned short ADBUF4; + unsigned short ADBUF5; + unsigned short ADBUF6; + unsigned short ADBUF7; + unsigned short ADBUF8; + unsigned short ADBUF9; + unsigned short ADBUF10; + unsigned short ADBUF11; + unsigned short ADBUF12; + unsigned short ADBUF13; + unsigned short ADBUF14; + unsigned short ADBUF15; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BUFEN : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char BUFEN : 1; +#endif + } BIT; + } ADBUFEN; + char wk12[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BUFPTR : 4; + unsigned char PTROVF : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PTROVF : 1; + unsigned char BUFPTR : 4; +#endif + } BIT; + } ADBUFPTR; + char wk13[10]; + unsigned char ADSSTRL; + unsigned char ADSSTRT; + unsigned char ADSSTRO; + unsigned char ADSSTR0; + unsigned char ADSSTR1; + unsigned char ADSSTR2; + unsigned char ADSSTR3; + unsigned char ADSSTR4; + unsigned char ADSSTR5; + unsigned char ADSSTR6; + unsigned char ADSSTR7; +}; + +struct st_sci0 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKS : 2; + unsigned char MP : 1; + unsigned char STOP : 1; + unsigned char PM : 1; + unsigned char PE : 1; + unsigned char CHR : 1; + unsigned char CM : 1; +#else + unsigned char CM : 1; + unsigned char CHR : 1; + unsigned char PE : 1; + unsigned char PM : 1; + unsigned char STOP : 1; + unsigned char MP : 1; + unsigned char CKS : 2; +#endif + } BIT; + } SMR; + unsigned char BRR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKE : 2; + unsigned char TEIE : 1; + unsigned char MPIE : 1; + unsigned char RE : 1; + unsigned char TE : 1; + unsigned char RIE : 1; + unsigned char TIE : 1; +#else + unsigned char TIE : 1; + unsigned char RIE : 1; + unsigned char TE : 1; + unsigned char RE : 1; + unsigned char MPIE : 1; + unsigned char TEIE : 1; + unsigned char CKE : 2; +#endif + } BIT; + } SCR; + unsigned char TDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MPBT : 1; + unsigned char MPB : 1; + unsigned char TEND : 1; + unsigned char PER : 1; + unsigned char FER : 1; + unsigned char ORER : 1; + unsigned char RDRF : 1; + unsigned char TDRE : 1; +#else + unsigned char TDRE : 1; + unsigned char RDRF : 1; + unsigned char ORER : 1; + unsigned char FER : 1; + unsigned char PER : 1; + unsigned char TEND : 1; + unsigned char MPB : 1; + unsigned char MPBT : 1; +#endif + } BIT; + } SSR; + unsigned char RDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SMIF : 1; + unsigned char : 1; + unsigned char SINV : 1; + unsigned char SDIR : 1; + unsigned char CHR1 : 1; + unsigned char : 2; + unsigned char BCP2 : 1; +#else + unsigned char BCP2 : 1; + unsigned char : 2; + unsigned char CHR1 : 1; + unsigned char SDIR : 1; + unsigned char SINV : 1; + unsigned char : 1; + unsigned char SMIF : 1; +#endif + } BIT; + } SCMR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ACS0 : 1; + unsigned char : 1; + unsigned char BRME : 1; + unsigned char : 1; + unsigned char ABCS : 1; + unsigned char NFEN : 1; + unsigned char BGDM : 1; + unsigned char RXDESEL : 1; +#else + unsigned char RXDESEL : 1; + unsigned char BGDM : 1; + unsigned char NFEN : 1; + unsigned char ABCS : 1; + unsigned char : 1; + unsigned char BRME : 1; + unsigned char : 1; + unsigned char ACS0 : 1; +#endif + } BIT; + } SEMR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFCS : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char NFCS : 3; +#endif + } BIT; + } SNFR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICM : 1; + unsigned char : 2; + unsigned char IICDL : 5; +#else + unsigned char IICDL : 5; + unsigned char : 2; + unsigned char IICM : 1; +#endif + } BIT; + } SIMR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICINTM : 1; + unsigned char IICCSC : 1; + unsigned char : 3; + unsigned char IICACKT : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char IICACKT : 1; + unsigned char : 3; + unsigned char IICCSC : 1; + unsigned char IICINTM : 1; +#endif + } BIT; + } SIMR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICSTAREQ : 1; + unsigned char IICRSTAREQ : 1; + unsigned char IICSTPREQ : 1; + unsigned char IICSTIF : 1; + unsigned char IICSDAS : 2; + unsigned char IICSCLS : 2; +#else + unsigned char IICSCLS : 2; + unsigned char IICSDAS : 2; + unsigned char IICSTIF : 1; + unsigned char IICSTPREQ : 1; + unsigned char IICRSTAREQ : 1; + unsigned char IICSTAREQ : 1; +#endif + } BIT; + } SIMR3; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICACKR : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char IICACKR : 1; +#endif + } BIT; + } SISR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SSE : 1; + unsigned char CTSE : 1; + unsigned char MSS : 1; + unsigned char : 1; + unsigned char MFF : 1; + unsigned char : 1; + unsigned char CKPOL : 1; + unsigned char CKPH : 1; +#else + unsigned char CKPH : 1; + unsigned char CKPOL : 1; + unsigned char : 1; + unsigned char MFF : 1; + unsigned char : 1; + unsigned char MSS : 1; + unsigned char CTSE : 1; + unsigned char SSE : 1; +#endif + } BIT; + } SPMR; + union { + unsigned short WORD; + struct { + unsigned char TDRH; + unsigned char TDRL; + } BYTE; + } TDRHL; + union { + unsigned short WORD; + struct { + unsigned char RDRH; + unsigned char RDRL; + } BYTE; + } RDRHL; + unsigned char MDDR; +}; + +struct st_sci12 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKS : 2; + unsigned char MP : 1; + unsigned char STOP : 1; + unsigned char PM : 1; + unsigned char PE : 1; + unsigned char CHR : 1; + unsigned char CM : 1; +#else + unsigned char CM : 1; + unsigned char CHR : 1; + unsigned char PE : 1; + unsigned char PM : 1; + unsigned char STOP : 1; + unsigned char MP : 1; + unsigned char CKS : 2; +#endif + } BIT; + } SMR; + unsigned char BRR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKE : 2; + unsigned char TEIE : 1; + unsigned char MPIE : 1; + unsigned char RE : 1; + unsigned char TE : 1; + unsigned char RIE : 1; + unsigned char TIE : 1; +#else + unsigned char TIE : 1; + unsigned char RIE : 1; + unsigned char TE : 1; + unsigned char RE : 1; + unsigned char MPIE : 1; + unsigned char TEIE : 1; + unsigned char CKE : 2; +#endif + } BIT; + } SCR; + unsigned char TDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MPBT : 1; + unsigned char MPB : 1; + unsigned char TEND : 1; + unsigned char PER : 1; + unsigned char FER : 1; + unsigned char ORER : 1; + unsigned char RDRF : 1; + unsigned char TDRE : 1; +#else + unsigned char TDRE : 1; + unsigned char RDRF : 1; + unsigned char ORER : 1; + unsigned char FER : 1; + unsigned char PER : 1; + unsigned char TEND : 1; + unsigned char MPB : 1; + unsigned char MPBT : 1; +#endif + } BIT; + } SSR; + unsigned char RDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SMIF : 1; + unsigned char : 1; + unsigned char SINV : 1; + unsigned char SDIR : 1; + unsigned char CHR1 : 1; + unsigned char : 2; + unsigned char BCP2 : 1; +#else + unsigned char BCP2 : 1; + unsigned char : 2; + unsigned char CHR1 : 1; + unsigned char SDIR : 1; + unsigned char SINV : 1; + unsigned char : 1; + unsigned char SMIF : 1; +#endif + } BIT; + } SCMR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ACS0 : 1; + unsigned char : 1; + unsigned char BRME : 1; + unsigned char : 1; + unsigned char ABCS : 1; + unsigned char NFEN : 1; + unsigned char BGDM : 1; + unsigned char RXDESEL : 1; +#else + unsigned char RXDESEL : 1; + unsigned char BGDM : 1; + unsigned char NFEN : 1; + unsigned char ABCS : 1; + unsigned char : 1; + unsigned char BRME : 1; + unsigned char : 1; + unsigned char ACS0 : 1; +#endif + } BIT; + } SEMR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFCS : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char NFCS : 3; +#endif + } BIT; + } SNFR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICM : 1; + unsigned char : 2; + unsigned char IICDL : 5; +#else + unsigned char IICDL : 5; + unsigned char : 2; + unsigned char IICM : 1; +#endif + } BIT; + } SIMR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICINTM : 1; + unsigned char IICCSC : 1; + unsigned char : 3; + unsigned char IICACKT : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char IICACKT : 1; + unsigned char : 3; + unsigned char IICCSC : 1; + unsigned char IICINTM : 1; +#endif + } BIT; + } SIMR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICSTAREQ : 1; + unsigned char IICRSTAREQ : 1; + unsigned char IICSTPREQ : 1; + unsigned char IICSTIF : 1; + unsigned char IICSDAS : 2; + unsigned char IICSCLS : 2; +#else + unsigned char IICSCLS : 2; + unsigned char IICSDAS : 2; + unsigned char IICSTIF : 1; + unsigned char IICSTPREQ : 1; + unsigned char IICRSTAREQ : 1; + unsigned char IICSTAREQ : 1; +#endif + } BIT; + } SIMR3; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICACKR : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char IICACKR : 1; +#endif + } BIT; + } SISR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SSE : 1; + unsigned char CTSE : 1; + unsigned char MSS : 1; + unsigned char : 1; + unsigned char MFF : 1; + unsigned char : 1; + unsigned char CKPOL : 1; + unsigned char CKPH : 1; +#else + unsigned char CKPH : 1; + unsigned char CKPOL : 1; + unsigned char : 1; + unsigned char MFF : 1; + unsigned char : 1; + unsigned char MSS : 1; + unsigned char CTSE : 1; + unsigned char SSE : 1; +#endif + } BIT; + } SPMR; + union { + unsigned short WORD; + struct { + unsigned char TDRH; + unsigned char TDRL; + } BYTE; + } TDRHL; + union { + unsigned short WORD; + struct { + unsigned char RDRH; + unsigned char RDRL; + } BYTE; + } RDRHL; + unsigned char MDDR; + char wk0[13]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ESME : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char ESME : 1; +#endif + } BIT; + } ESMER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 1; + unsigned char SFSF : 1; + unsigned char RXDSF : 1; + unsigned char BRME : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char BRME : 1; + unsigned char RXDSF : 1; + unsigned char SFSF : 1; + unsigned char : 1; +#endif + } BIT; + } CR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BFE : 1; + unsigned char CF0RE : 1; + unsigned char CF1DS : 2; + unsigned char PIBE : 1; + unsigned char PIBS : 3; +#else + unsigned char PIBS : 3; + unsigned char PIBE : 1; + unsigned char CF1DS : 2; + unsigned char CF0RE : 1; + unsigned char BFE : 1; +#endif + } BIT; + } CR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DFCS : 3; + unsigned char : 1; + unsigned char BCCS : 2; + unsigned char RTS : 2; +#else + unsigned char RTS : 2; + unsigned char BCCS : 2; + unsigned char : 1; + unsigned char DFCS : 3; +#endif + } BIT; + } CR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SDST : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char SDST : 1; +#endif + } BIT; + } CR3; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TXDXPS : 1; + unsigned char RXDXPS : 1; + unsigned char : 2; + unsigned char SHARPS : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char SHARPS : 1; + unsigned char : 2; + unsigned char RXDXPS : 1; + unsigned char TXDXPS : 1; +#endif + } BIT; + } PCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BFDIE : 1; + unsigned char CF0MIE : 1; + unsigned char CF1MIE : 1; + unsigned char PIBDIE : 1; + unsigned char BCDIE : 1; + unsigned char AEDIE : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char AEDIE : 1; + unsigned char BCDIE : 1; + unsigned char PIBDIE : 1; + unsigned char CF1MIE : 1; + unsigned char CF0MIE : 1; + unsigned char BFDIE : 1; +#endif + } BIT; + } ICR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BFDF : 1; + unsigned char CF0MF : 1; + unsigned char CF1MF : 1; + unsigned char PIBDF : 1; + unsigned char BCDF : 1; + unsigned char AEDF : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char AEDF : 1; + unsigned char BCDF : 1; + unsigned char PIBDF : 1; + unsigned char CF1MF : 1; + unsigned char CF0MF : 1; + unsigned char BFDF : 1; +#endif + } BIT; + } STR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BFDCL : 1; + unsigned char CF0MCL : 1; + unsigned char CF1MCL : 1; + unsigned char PIBDCL : 1; + unsigned char BCDCL : 1; + unsigned char AEDCL : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char AEDCL : 1; + unsigned char BCDCL : 1; + unsigned char PIBDCL : 1; + unsigned char CF1MCL : 1; + unsigned char CF0MCL : 1; + unsigned char BFDCL : 1; +#endif + } BIT; + } STCR; + unsigned char CF0DR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CF0CE0 : 1; + unsigned char CF0CE1 : 1; + unsigned char CF0CE2 : 1; + unsigned char CF0CE3 : 1; + unsigned char CF0CE4 : 1; + unsigned char CF0CE5 : 1; + unsigned char CF0CE6 : 1; + unsigned char CF0CE7 : 1; +#else + unsigned char CF0CE7 : 1; + unsigned char CF0CE6 : 1; + unsigned char CF0CE5 : 1; + unsigned char CF0CE4 : 1; + unsigned char CF0CE3 : 1; + unsigned char CF0CE2 : 1; + unsigned char CF0CE1 : 1; + unsigned char CF0CE0 : 1; +#endif + } BIT; + } CF0CR; + unsigned char CF0RR; + unsigned char PCF1DR; + unsigned char SCF1DR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CF1CE0 : 1; + unsigned char CF1CE1 : 1; + unsigned char CF1CE2 : 1; + unsigned char CF1CE3 : 1; + unsigned char CF1CE4 : 1; + unsigned char CF1CE5 : 1; + unsigned char CF1CE6 : 1; + unsigned char CF1CE7 : 1; +#else + unsigned char CF1CE7 : 1; + unsigned char CF1CE6 : 1; + unsigned char CF1CE5 : 1; + unsigned char CF1CE4 : 1; + unsigned char CF1CE3 : 1; + unsigned char CF1CE2 : 1; + unsigned char CF1CE1 : 1; + unsigned char CF1CE0 : 1; +#endif + } BIT; + } CF1CR; + unsigned char CF1RR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TCST : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char TCST : 1; +#endif + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TOMS : 2; + unsigned char : 1; + unsigned char TWRC : 1; + unsigned char TCSS : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char TCSS : 3; + unsigned char TWRC : 1; + unsigned char : 1; + unsigned char TOMS : 2; +#endif + } BIT; + } TMR; + unsigned char TPRE; + unsigned char TCNT; +}; + +struct st_smci { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKS : 2; + unsigned char BCP : 2; + unsigned char PM : 1; + unsigned char PE : 1; + unsigned char BLK : 1; + unsigned char GM : 1; +#else + unsigned char GM : 1; + unsigned char BLK : 1; + unsigned char PE : 1; + unsigned char PM : 1; + unsigned char BCP : 2; + unsigned char CKS : 2; +#endif + } BIT; + } SMR; + unsigned char BRR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKE : 2; + unsigned char TEIE : 1; + unsigned char MPIE : 1; + unsigned char RE : 1; + unsigned char TE : 1; + unsigned char RIE : 1; + unsigned char TIE : 1; +#else + unsigned char TIE : 1; + unsigned char RIE : 1; + unsigned char TE : 1; + unsigned char RE : 1; + unsigned char MPIE : 1; + unsigned char TEIE : 1; + unsigned char CKE : 2; +#endif + } BIT; + } SCR; + unsigned char TDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MPBT : 1; + unsigned char MPB : 1; + unsigned char TEND : 1; + unsigned char PER : 1; + unsigned char ERS : 1; + unsigned char ORER : 1; + unsigned char RDRF : 1; + unsigned char TDRE : 1; +#else + unsigned char TDRE : 1; + unsigned char RDRF : 1; + unsigned char ORER : 1; + unsigned char ERS : 1; + unsigned char PER : 1; + unsigned char TEND : 1; + unsigned char MPB : 1; + unsigned char MPBT : 1; +#endif + } BIT; + } SSR; + unsigned char RDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SMIF : 1; + unsigned char : 1; + unsigned char SINV : 1; + unsigned char SDIR : 1; + unsigned char CHR1 : 1; + unsigned char : 2; + unsigned char BCP2 : 1; +#else + unsigned char BCP2 : 1; + unsigned char : 2; + unsigned char CHR1 : 1; + unsigned char SDIR : 1; + unsigned char SINV : 1; + unsigned char : 1; + unsigned char SMIF : 1; +#endif + } BIT; + } SCMR; + char wk0[7]; + union { + unsigned short WORD; + struct { + unsigned char TDRH; + unsigned char TDRL; + } BYTE; + } TDRHL; + union { + unsigned short WORD; + struct { + unsigned char RDRH; + unsigned char RDRL; + } BYTE; + } RDRHL; + unsigned char MDDR; +}; + +struct st_smci1 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKS : 2; + unsigned char BCP : 2; + unsigned char PM : 1; + unsigned char PE : 1; + unsigned char BLK : 1; + unsigned char GM : 1; +#else + unsigned char GM : 1; + unsigned char BLK : 1; + unsigned char PE : 1; + unsigned char PM : 1; + unsigned char BCP : 2; + unsigned char CKS : 2; +#endif + } BIT; + } SMR; + unsigned char BRR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKE : 2; + unsigned char TEIE : 1; + unsigned char MPIE : 1; + unsigned char RE : 1; + unsigned char TE : 1; + unsigned char RIE : 1; + unsigned char TIE : 1; +#else + unsigned char TIE : 1; + unsigned char RIE : 1; + unsigned char TE : 1; + unsigned char RE : 1; + unsigned char MPIE : 1; + unsigned char TEIE : 1; + unsigned char CKE : 2; +#endif + } BIT; + } SCR; + unsigned char TDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MPBT : 1; + unsigned char MPB : 1; + unsigned char TEND : 1; + unsigned char PER : 1; + unsigned char ERS : 1; + unsigned char ORER : 1; + unsigned char RDRF : 1; + unsigned char TDRE : 1; +#else + unsigned char TDRE : 1; + unsigned char RDRF : 1; + unsigned char ORER : 1; + unsigned char ERS : 1; + unsigned char PER : 1; + unsigned char TEND : 1; + unsigned char MPB : 1; + unsigned char MPBT : 1; +#endif + } BIT; + } SSR; + unsigned char RDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SMIF : 1; + unsigned char : 1; + unsigned char SINV : 1; + unsigned char SDIR : 1; + unsigned char CHR1 : 1; + unsigned char : 2; + unsigned char BCP2 : 1; +#else + unsigned char BCP2 : 1; + unsigned char : 2; + unsigned char CHR1 : 1; + unsigned char SDIR : 1; + unsigned char SINV : 1; + unsigned char : 1; + unsigned char SMIF : 1; +#endif + } BIT; + } SCMR; + char wk0[7]; + union { + unsigned short WORD; + struct { + unsigned char TDRH; + unsigned char TDRL; + } BYTE; + } TDRHL; + union { + unsigned short WORD; + struct { + unsigned char RDRH; + unsigned char RDRL; + } BYTE; + } RDRHL; + unsigned char MDDR; +}; + +struct st_system { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short MD : 1; + unsigned short : 15; +#else + unsigned short : 15; + unsigned short MD : 1; +#endif + } BIT; + } MDMONR; + char wk0[6]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RAME : 1; + unsigned short : 15; +#else + unsigned short : 15; + unsigned short RAME : 1; +#endif + } BIT; + } SYSCR1; + char wk1[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 15; + unsigned short SSBY : 1; +#else + unsigned short SSBY : 1; + unsigned short : 15; +#endif + } BIT; + } SBYCR; + char wk2[2]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 4; + unsigned long MSTPA4 : 1; + unsigned long MSTPA5 : 1; + unsigned long : 3; + unsigned long MSTPA9 : 1; + unsigned long : 5; + unsigned long MSTPA15 : 1; + unsigned long : 1; + unsigned long MSTPA17 : 1; + unsigned long : 1; + unsigned long MSTPA19 : 1; + unsigned long : 8; + unsigned long MSTPA28 : 1; + unsigned long : 3; +#else + unsigned long : 3; + unsigned long MSTPA28 : 1; + unsigned long : 8; + unsigned long MSTPA19 : 1; + unsigned long : 1; + unsigned long MSTPA17 : 1; + unsigned long : 1; + unsigned long MSTPA15 : 1; + unsigned long : 5; + unsigned long MSTPA9 : 1; + unsigned long : 3; + unsigned long MSTPA5 : 1; + unsigned long MSTPA4 : 1; + unsigned long : 4; +#endif + } BIT; + } MSTPCRA; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 4; + unsigned long MSTPB4 : 1; + unsigned long : 1; + unsigned long MSTPB6 : 1; + unsigned long : 2; + unsigned long MSTPB9 : 1; + unsigned long MSTPB10 : 1; + unsigned long : 6; + unsigned long MSTPB17 : 1; + unsigned long : 3; + unsigned long MSTPB21 : 1; + unsigned long : 1; + unsigned long MSTPB23 : 1; + unsigned long : 1; + unsigned long MSTPB25 : 1; + unsigned long MSTPB26 : 1; + unsigned long : 3; + unsigned long MSTPB30 : 1; + unsigned long MSTPB31 : 1; +#else + unsigned long MSTPB31 : 1; + unsigned long MSTPB30 : 1; + unsigned long : 3; + unsigned long MSTPB26 : 1; + unsigned long MSTPB25 : 1; + unsigned long : 1; + unsigned long MSTPB23 : 1; + unsigned long : 1; + unsigned long MSTPB21 : 1; + unsigned long : 3; + unsigned long MSTPB17 : 1; + unsigned long : 6; + unsigned long MSTPB10 : 1; + unsigned long MSTPB9 : 1; + unsigned long : 2; + unsigned long MSTPB6 : 1; + unsigned long : 1; + unsigned long MSTPB4 : 1; + unsigned long : 4; +#endif + } BIT; + } MSTPCRB; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MSTPC0 : 1; + unsigned long : 18; + unsigned long MSTPC19 : 1; + unsigned long : 6; + unsigned long MSTPC26 : 1; + unsigned long MSTPC27 : 1; + unsigned long MSTPC28 : 1; + unsigned long MSTPC29 : 1; + unsigned long : 1; + unsigned long DSLPE : 1; +#else + unsigned long DSLPE : 1; + unsigned long : 1; + unsigned long MSTPC29 : 1; + unsigned long MSTPC28 : 1; + unsigned long MSTPC27 : 1; + unsigned long MSTPC26 : 1; + unsigned long : 6; + unsigned long MSTPC19 : 1; + unsigned long : 18; + unsigned long MSTPC0 : 1; +#endif + } BIT; + } MSTPCRC; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 10; + unsigned long MSTPD10 : 1; + unsigned long : 21; +#else + unsigned long : 21; + unsigned long MSTPD10 : 1; + unsigned long : 10; +#endif + } BIT; + } MSTPCRD; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long PCKD : 4; + unsigned long : 4; + unsigned long PCKB : 4; + unsigned long : 12; + unsigned long ICK : 4; + unsigned long FCK : 4; +#else + unsigned long FCK : 4; + unsigned long ICK : 4; + unsigned long : 12; + unsigned long PCKB : 4; + unsigned long : 4; + unsigned long PCKD : 4; +#endif + } BIT; + } SCKCR; + char wk3[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 8; + unsigned short CKSEL : 3; + unsigned short : 5; +#else + unsigned short : 5; + unsigned short CKSEL : 3; + unsigned short : 8; +#endif + } BIT; + } SCKCR3; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PLIDIV : 2; + unsigned short : 6; + unsigned short STC : 6; + unsigned short : 2; +#else + unsigned short : 2; + unsigned short STC : 6; + unsigned short : 6; + unsigned short PLIDIV : 2; +#endif + } BIT; + } PLLCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PLLEN : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char PLLEN : 1; +#endif + } BIT; + } PLLCR2; + char wk4[7]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MOSTP : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char MOSTP : 1; +#endif + } BIT; + } MOSCCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SOSTP : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char SOSTP : 1; +#endif + } BIT; + } SOSCCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LCSTP : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char LCSTP : 1; +#endif + } BIT; + } LOCOCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ILCSTP : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char ILCSTP : 1; +#endif + } BIT; + } ILOCOCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char HCSTP : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char HCSTP : 1; +#endif + } BIT; + } HOCOCR; + char wk5[5]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MOOVF : 1; + unsigned char : 1; + unsigned char PLOVF : 1; + unsigned char HCOVF : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char HCOVF : 1; + unsigned char PLOVF : 1; + unsigned char : 1; + unsigned char MOOVF : 1; +#endif + } BIT; + } OSCOVFSR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char HOFXIN : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char HOFXIN : 1; +#endif + } BIT; + } HOFCR; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 8; + unsigned short CKOSEL : 4; + unsigned short CKODIV : 3; + unsigned short CKOSTP : 1; +#else + unsigned short CKOSTP : 1; + unsigned short CKODIV : 3; + unsigned short CKOSEL : 4; + unsigned short : 8; +#endif + } BIT; + } CKOCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OSTDIE : 1; + unsigned char : 6; + unsigned char OSTDE : 1; +#else + unsigned char OSTDE : 1; + unsigned char : 6; + unsigned char OSTDIE : 1; +#endif + } BIT; + } OSTDCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OSTDF : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char OSTDF : 1; +#endif + } BIT; + } OSTDSR; + char wk6[30]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LOCOTRD : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char LOCOTRD : 5; +#endif + } BIT; + } LOCOTRR; + char wk7[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ILOCOTRD : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char ILOCOTRD : 5; +#endif + } BIT; + } ILOCOTRR; + char wk8[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char HOCOTRD : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char HOCOTRD : 6; +#endif + } BIT; + } HOCOTRR0; + char wk9[55]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OPCM : 3; + unsigned char : 1; + unsigned char OPCMTSF : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char OPCMTSF : 1; + unsigned char : 1; + unsigned char OPCM : 3; +#endif + } BIT; + } OPCCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char RSTCKSEL : 3; + unsigned char : 4; + unsigned char RSTCKEN : 1; +#else + unsigned char RSTCKEN : 1; + unsigned char : 4; + unsigned char RSTCKSEL : 3; +#endif + } BIT; + } RSTCKCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MSTS : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char MSTS : 5; +#endif + } BIT; + } MOSCWTCR; + char wk10[7]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SOPCM : 1; + unsigned char : 3; + unsigned char SOPCMTSF : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char SOPCMTSF : 1; + unsigned char : 3; + unsigned char SOPCM : 1; +#endif + } BIT; + } SOPCCR; + char wk11[21]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IWDTRF : 1; + unsigned char : 1; + unsigned char SWRF : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SWRF : 1; + unsigned char : 1; + unsigned char IWDTRF : 1; +#endif + } BIT; + } RSTSR2; + char wk12[1]; + unsigned short SWRR; + char wk13[28]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LVD1IDTSEL : 2; + unsigned char LVD1IRQSEL : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char LVD1IRQSEL : 1; + unsigned char LVD1IDTSEL : 2; +#endif + } BIT; + } LVD1CR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LVD1DET : 1; + unsigned char LVD1MON : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char LVD1MON : 1; + unsigned char LVD1DET : 1; +#endif + } BIT; + } LVD1SR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LVD2IDTSEL : 2; + unsigned char LVD2IRQSEL : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char LVD2IRQSEL : 1; + unsigned char LVD2IDTSEL : 2; +#endif + } BIT; + } LVD2CR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LVD2DET : 1; + unsigned char LVD2MON : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char LVD2MON : 1; + unsigned char LVD2DET : 1; +#endif + } BIT; + } LVD2SR; + char wk14[794]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PRC0 : 1; + unsigned short PRC1 : 1; + unsigned short PRC2 : 1; + unsigned short PRC3 : 1; + unsigned short : 4; + unsigned short PRKEY : 8; +#else + unsigned short PRKEY : 8; + unsigned short : 4; + unsigned short PRC3 : 1; + unsigned short PRC2 : 1; + unsigned short PRC1 : 1; + unsigned short PRC0 : 1; +#endif + } BIT; + } PRCR; + char wk15[48784]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PORF : 1; + unsigned char LVD0RF : 1; + unsigned char LVD1RF : 1; + unsigned char LVD2RF : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char LVD2RF : 1; + unsigned char LVD1RF : 1; + unsigned char LVD0RF : 1; + unsigned char PORF : 1; +#endif + } BIT; + } RSTSR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CWSF : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char CWSF : 1; +#endif + } BIT; + } RSTSR1; + char wk16[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 5; + unsigned char MODRV21 : 1; + unsigned char MOSEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char MOSEL : 1; + unsigned char MODRV21 : 1; + unsigned char : 5; +#endif + } BIT; + } MOFCR; + char wk17[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 3; + unsigned char EXVCCINP2 : 1; + unsigned char : 1; + unsigned char LVD1E : 1; + unsigned char LVD2E : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char LVD2E : 1; + unsigned char LVD1E : 1; + unsigned char : 1; + unsigned char EXVCCINP2 : 1; + unsigned char : 3; +#endif + } BIT; + } LVCMPCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LVD1LVL : 4; + unsigned char LVD2LVL : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char LVD2LVL : 2; + unsigned char LVD1LVL : 4; +#endif + } BIT; + } LVDLVLR; + char wk18[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LVD1RIE : 1; + unsigned char : 1; + unsigned char LVD1CMPE : 1; + unsigned char : 3; + unsigned char LVD1RI : 1; + unsigned char LVD1RN : 1; +#else + unsigned char LVD1RN : 1; + unsigned char LVD1RI : 1; + unsigned char : 3; + unsigned char LVD1CMPE : 1; + unsigned char : 1; + unsigned char LVD1RIE : 1; +#endif + } BIT; + } LVD1CR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LVD2RIE : 1; + unsigned char : 1; + unsigned char LVD2CMPE : 1; + unsigned char : 3; + unsigned char LVD2RI : 1; + unsigned char LVD2RN : 1; +#else + unsigned char LVD2RN : 1; + unsigned char LVD2RI : 1; + unsigned char : 3; + unsigned char LVD2CMPE : 1; + unsigned char : 1; + unsigned char LVD2RIE : 1; +#endif + } BIT; + } LVD2CR0; +}; + +struct st_temps { + unsigned char TSCDRL; + unsigned char TSCDRH; +}; + +struct st_tmr0 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 3; + unsigned char CCLR : 2; + unsigned char OVIE : 1; + unsigned char CMIEA : 1; + unsigned char CMIEB : 1; +#else + unsigned char CMIEB : 1; + unsigned char CMIEA : 1; + unsigned char OVIE : 1; + unsigned char CCLR : 2; + unsigned char : 3; +#endif + } BIT; + } TCR; + char wk0[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OSA : 2; + unsigned char OSB : 2; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char OSB : 2; + unsigned char OSA : 2; +#endif + } BIT; + } TCSR; + char wk1[1]; + unsigned char TCORA; + char wk2[1]; + unsigned char TCORB; + char wk3[1]; + unsigned char TCNT; + char wk4[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKS : 3; + unsigned char CSS : 2; + unsigned char : 2; + unsigned char TMRIS : 1; +#else + unsigned char TMRIS : 1; + unsigned char : 2; + unsigned char CSS : 2; + unsigned char CKS : 3; +#endif + } BIT; + } TCCR; + char wk5[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TCS : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char TCS : 1; +#endif + } BIT; + } TCSTR; +}; + +struct st_tmr1 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 3; + unsigned char CCLR : 2; + unsigned char OVIE : 1; + unsigned char CMIEA : 1; + unsigned char CMIEB : 1; +#else + unsigned char CMIEB : 1; + unsigned char CMIEA : 1; + unsigned char OVIE : 1; + unsigned char CCLR : 2; + unsigned char : 3; +#endif + } BIT; + } TCR; + char wk0[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OSA : 2; + unsigned char OSB : 2; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char OSB : 2; + unsigned char OSA : 2; +#endif + } BIT; + } TCSR; + char wk1[1]; + unsigned char TCORA; + char wk2[1]; + unsigned char TCORB; + char wk3[1]; + unsigned char TCNT; + char wk4[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKS : 3; + unsigned char CSS : 2; + unsigned char : 2; + unsigned char TMRIS : 1; +#else + unsigned char TMRIS : 1; + unsigned char : 2; + unsigned char CSS : 2; + unsigned char CKS : 3; +#endif + } BIT; + } TCCR; +}; + +struct st_tmr01 { + unsigned short TCORA; + unsigned short TCORB; + unsigned short TCNT; + unsigned short TCCR; +}; + +enum enum_ir { +IR_BSC_BUSERR=16,IR_FCU_FRDYI=23, +IR_ICU_SWINT=27, +IR_CMT0_CMI0, +IR_CMT1_CMI1, +IR_CAC_FERRF=32,IR_CAC_MENDF,IR_CAC_OVFF, +IR_RSPI0_SPEI0=44,IR_RSPI0_SPRI0,IR_RSPI0_SPTI0,IR_RSPI0_SPII0, +IR_DOC_DOPCF=57, +IR_CMPB_CMPB0,IR_CMPB_CMPB1, +IR_CTSU_CTSUWR,IR_CTSU_CTSURD,IR_CTSU_CTSUFN, +IR_RTC_CUP, +IR_ICU_IRQ0,IR_ICU_IRQ1,IR_ICU_IRQ2,IR_ICU_IRQ3,IR_ICU_IRQ4,IR_ICU_IRQ5,IR_ICU_IRQ6,IR_ICU_IRQ7, +IR_ELC_ELSR8I=80, +IR_LVD_LVD1=88,IR_LVD_LVD2, +IR_RTC_ALM=92,IR_RTC_PRD, +IR_REMC0_REMCI0, +IR_REMC1_REMCI1, +IR_S12AD_S12ADI0=102,IR_S12AD_GBADI, +IR_ELC_ELSR18I=106, +IR_MTU0_TGIA0=114,IR_MTU0_TGIB0,IR_MTU0_TGIC0,IR_MTU0_TGID0,IR_MTU0_TCIV0,IR_MTU0_TGIE0,IR_MTU0_TGIF0, +IR_MTU1_TGIA1,IR_MTU1_TGIB1,IR_MTU1_TCIV1,IR_MTU1_TCIU1, +IR_MTU2_TGIA2,IR_MTU2_TGIB2,IR_MTU2_TCIV2,IR_MTU2_TCIU2, +IR_MTU3_TGIA3,IR_MTU3_TGIB3,IR_MTU3_TGIC3,IR_MTU3_TGID3,IR_MTU3_TCIV3, +IR_MTU4_TGIA4,IR_MTU4_TGIB4,IR_MTU4_TGIC4,IR_MTU4_TGID4,IR_MTU4_TCIV4, +IR_MTU5_TGIU5,IR_MTU5_TGIV5,IR_MTU5_TGIW5, +IR_POE_OEI1=170,IR_POE_OEI2, +IR_TMR0_CMIA0=174,IR_TMR0_CMIB0,IR_TMR0_OVI0, +IR_TMR1_CMIA1,IR_TMR1_CMIB1,IR_TMR1_OVI1, +IR_TMR2_CMIA2,IR_TMR2_CMIB2,IR_TMR2_OVI2, +IR_TMR3_CMIA3,IR_TMR3_CMIB3,IR_TMR3_OVI3, +IR_SCI0_ERI0=214,IR_SCI0_RXI0,IR_SCI0_TXI0,IR_SCI0_TEI0, +IR_SCI1_ERI1,IR_SCI1_RXI1,IR_SCI1_TXI1,IR_SCI1_TEI1, +IR_SCI5_ERI5,IR_SCI5_RXI5,IR_SCI5_TXI5,IR_SCI5_TEI5, +IR_SCI6_ERI6,IR_SCI6_RXI6,IR_SCI6_TXI6,IR_SCI6_TEI6, +IR_SCI8_ERI8,IR_SCI8_RXI8,IR_SCI8_TXI8,IR_SCI8_TEI8, +IR_SCI9_ERI9,IR_SCI9_RXI9,IR_SCI9_TXI9,IR_SCI9_TEI9, +IR_SCI12_ERI12,IR_SCI12_RXI12,IR_SCI12_TXI12,IR_SCI12_TEI12,IR_SCI12_SCIX0,IR_SCI12_SCIX1,IR_SCI12_SCIX2,IR_SCI12_SCIX3, +IR_RIIC0_EEI0,IR_RIIC0_RXI0,IR_RIIC0_TXI0,IR_RIIC0_TEI0 +}; + +enum enum_dtce { +DTCE_ICU_SWINT=27, +DTCE_CMT0_CMI0, +DTCE_CMT1_CMI1, +DTCE_RSPI0_SPRI0=45,DTCE_RSPI0_SPTI0, +DTCE_CMPB_CMPB0=58,DTCE_CMPB_CMPB1, +DTCE_CTSU_CTSUWR,DTCE_CTSU_CTSURD, +DTCE_ICU_IRQ0=64,DTCE_ICU_IRQ1,DTCE_ICU_IRQ2,DTCE_ICU_IRQ3,DTCE_ICU_IRQ4,DTCE_ICU_IRQ5,DTCE_ICU_IRQ6,DTCE_ICU_IRQ7, +DTCE_S12AD_S12ADI0=102,DTCE_S12AD_GBADI, +DTCE_ELC_ELSR18I=106, +DTCE_MTU0_TGIA0=114,DTCE_MTU0_TGIB0,DTCE_MTU0_TGIC0,DTCE_MTU0_TGID0, +DTCE_MTU1_TGIA1=121,DTCE_MTU1_TGIB1, +DTCE_MTU2_TGIA2=125,DTCE_MTU2_TGIB2, +DTCE_MTU3_TGIA3=129,DTCE_MTU3_TGIB3,DTCE_MTU3_TGIC3,DTCE_MTU3_TGID3, +DTCE_MTU4_TGIA4=134,DTCE_MTU4_TGIB4,DTCE_MTU4_TGIC4,DTCE_MTU4_TGID4,DTCE_MTU4_TCIV4, +DTCE_MTU5_TGIU5,DTCE_MTU5_TGIV5,DTCE_MTU5_TGIW5, +DTCE_TMR0_CMIA0=174,DTCE_TMR0_CMIB0, +DTCE_TMR1_CMIA1=177,DTCE_TMR1_CMIB1, +DTCE_TMR2_CMIA2=180,DTCE_TMR2_CMIB2, +DTCE_TMR3_CMIA3=183,DTCE_TMR3_CMIB3, +DTCE_SCI0_RXI0=215,DTCE_SCI0_TXI0, +DTCE_SCI1_RXI1=219,DTCE_SCI1_TXI1, +DTCE_SCI5_RXI5=223,DTCE_SCI5_TXI5, +DTCE_SCI6_RXI6=227,DTCE_SCI6_TXI6, +DTCE_SCI8_RXI8=231,DTCE_SCI8_TXI8, +DTCE_SCI9_RXI9=235,DTCE_SCI9_TXI9, +DTCE_SCI12_RXI12=239,DTCE_SCI12_TXI12, +DTCE_RIIC0_RXI0=247,DTCE_RIIC0_TXI0 +}; + +enum enum_ier { +IER_BSC_BUSERR=0x02, +IER_FCU_FRDYI=0x02, +IER_ICU_SWINT=0x03, +IER_CMT0_CMI0=0x03, +IER_CMT1_CMI1=0x03, +IER_CAC_FERRF=0x04,IER_CAC_MENDF=0x04,IER_CAC_OVFF=0x04, +IER_RSPI0_SPEI0=0x05,IER_RSPI0_SPRI0=0x05,IER_RSPI0_SPTI0=0x05,IER_RSPI0_SPII0=0x05, +IER_DOC_DOPCF=0x07, +IER_CMPB_CMPB0=0x07,IER_CMPB_CMPB1=0x07, +IER_CTSU_CTSUWR=0x07,IER_CTSU_CTSURD=0x07,IER_CTSU_CTSUFN=0x07, +IER_RTC_CUP=0x07, +IER_ICU_IRQ0=0x08,IER_ICU_IRQ1=0x08,IER_ICU_IRQ2=0x08,IER_ICU_IRQ3=0x08,IER_ICU_IRQ4=0x08,IER_ICU_IRQ5=0x08,IER_ICU_IRQ6=0x08,IER_ICU_IRQ7=0x08, +IER_ELC_ELSR8I=0x0A, +IER_LVD_LVD1=0x0B,IER_LVD_LVD2=0x0B, +IER_RTC_ALM=0x0B,IER_RTC_PRD=0x0B, +IER_REMC0_REMCI0=0x0B, +IER_REMC1_REMCI1=0x0B, +IER_S12AD_S12ADI0=0x0C,IER_S12AD_GBADI=0x0C, +IER_ELC_ELSR18I=0x0D, +IER_MTU0_TGIA0=0x0E,IER_MTU0_TGIB0=0x0E,IER_MTU0_TGIC0=0x0E,IER_MTU0_TGID0=0x0E,IER_MTU0_TCIV0=0x0E,IER_MTU0_TGIE0=0x0E,IER_MTU0_TGIF0=0x0F, +IER_MTU1_TGIA1=0x0F,IER_MTU1_TGIB1=0x0F,IER_MTU1_TCIV1=0x0F,IER_MTU1_TCIU1=0x0F, +IER_MTU2_TGIA2=0x0F,IER_MTU2_TGIB2=0x0F,IER_MTU2_TCIV2=0x0F,IER_MTU2_TCIU2=0x10, +IER_MTU3_TGIA3=0x10,IER_MTU3_TGIB3=0x10,IER_MTU3_TGIC3=0x10,IER_MTU3_TGID3=0x10,IER_MTU3_TCIV3=0x10, +IER_MTU4_TGIA4=0x10,IER_MTU4_TGIB4=0x10,IER_MTU4_TGIC4=0x11,IER_MTU4_TGID4=0x11,IER_MTU4_TCIV4=0x11, +IER_MTU5_TGIU5=0x11,IER_MTU5_TGIV5=0x11,IER_MTU5_TGIW5=0x11, +IER_POE_OEI1=0x15,IER_POE_OEI2=0x15, +IER_TMR0_CMIA0=0x15,IER_TMR0_CMIB0=0x15,IER_TMR0_OVI0=0x16, +IER_TMR1_CMIA1=0x16,IER_TMR1_CMIB1=0x16,IER_TMR1_OVI1=0x16, +IER_TMR2_CMIA2=0x16,IER_TMR2_CMIB2=0x16,IER_TMR2_OVI2=0x16, +IER_TMR3_CMIA3=0x16,IER_TMR3_CMIB3=0x17,IER_TMR3_OVI3=0x17, +IER_SCI0_ERI0=0x1A,IER_SCI0_RXI0=0x1A,IER_SCI0_TXI0=0x1B,IER_SCI0_TEI0=0x1B, +IER_SCI1_ERI1=0x1B,IER_SCI1_RXI1=0x1B,IER_SCI1_TXI1=0x1B,IER_SCI1_TEI1=0x1B, +IER_SCI5_ERI5=0x1B,IER_SCI5_RXI5=0x1B,IER_SCI5_TXI5=0x1C,IER_SCI5_TEI5=0x1C, +IER_SCI6_ERI6=0x1C,IER_SCI6_RXI6=0x1C,IER_SCI6_TXI6=0x1C,IER_SCI6_TEI6=0x1C, +IER_SCI8_ERI8=0x1C,IER_SCI8_RXI8=0x1C,IER_SCI8_TXI8=0x1D,IER_SCI8_TEI8=0x1D, +IER_SCI9_ERI9=0x1D,IER_SCI9_RXI9=0x1D,IER_SCI9_TXI9=0x1D,IER_SCI9_TEI9=0x1D, +IER_SCI12_ERI12=0x1D,IER_SCI12_RXI12=0x1D,IER_SCI12_TXI12=0x1E,IER_SCI12_TEI12=0x1E,IER_SCI12_SCIX0=0x1E,IER_SCI12_SCIX1=0x1E,IER_SCI12_SCIX2=0x1E,IER_SCI12_SCIX3=0x1E, +IER_RIIC0_EEI0=0x1E,IER_RIIC0_RXI0=0x1E,IER_RIIC0_TXI0=0x1F,IER_RIIC0_TEI0=0x1F +}; + +enum enum_ipr { +IPR_BSC_BUSERR=0, +IPR_FCU_FRDYI=2, +IPR_ICU_SWINT=3, +IPR_CMT0_CMI0=4, +IPR_CMT1_CMI1=5, +IPR_CAC_FERRF=32,IPR_CAC_MENDF=33,IPR_CAC_OVFF=34, +IPR_RSPI0_SPEI0=44,IPR_RSPI0_SPRI0=44,IPR_RSPI0_SPTI0=44,IPR_RSPI0_SPII0=44, +IPR_DOC_DOPCF=57, +IPR_CMPB_CMPB0=58,IPR_CMPB_CMPB1=59, +IPR_CTSU_CTSUWR=60,IPR_CTSU_CTSURD=60,IPR_CTSU_CTSUFN=60, +IPR_RTC_CUP=63, +IPR_ICU_IRQ0=64,IPR_ICU_IRQ1=65,IPR_ICU_IRQ2=66,IPR_ICU_IRQ3=67,IPR_ICU_IRQ4=68,IPR_ICU_IRQ5=69,IPR_ICU_IRQ6=70,IPR_ICU_IRQ7=71, +IPR_ELC_ELSR8I=80, +IPR_LVD_LVD1=88,IPR_LVD_LVD2=89, +IPR_RTC_ALM=92,IPR_RTC_PRD=93, +IPR_REMC0_REMCI0=94, +IPR_REMC1_REMCI1=95, +IPR_S12AD_S12ADI0=102,IPR_S12AD_GBADI=103, +IPR_ELC_ELSR18I=106, +IPR_MTU0_TGIA0=114,IPR_MTU0_TGIB0=114,IPR_MTU0_TGIC0=114,IPR_MTU0_TGID0=114,IPR_MTU0_TCIV0=118,IPR_MTU0_TGIE0=118,IPR_MTU0_TGIF0=118, +IPR_MTU1_TGIA1=121,IPR_MTU1_TGIB1=121,IPR_MTU1_TCIV1=123,IPR_MTU1_TCIU1=123, +IPR_MTU2_TGIA2=125,IPR_MTU2_TGIB2=125,IPR_MTU2_TCIV2=127,IPR_MTU2_TCIU2=127, +IPR_MTU3_TGIA3=129,IPR_MTU3_TGIB3=129,IPR_MTU3_TGIC3=129,IPR_MTU3_TGID3=129,IPR_MTU3_TCIV3=133, +IPR_MTU4_TGIA4=134,IPR_MTU4_TGIB4=134,IPR_MTU4_TGIC4=134,IPR_MTU4_TGID4=134,IPR_MTU4_TCIV4=138, +IPR_MTU5_TGIU5=139,IPR_MTU5_TGIV5=139,IPR_MTU5_TGIW5=139, +IPR_POE_OEI1=170,IPR_POE_OEI2=171, +IPR_TMR0_CMIA0=174,IPR_TMR0_CMIB0=174,IPR_TMR0_OVI0=174, +IPR_TMR1_CMIA1=177,IPR_TMR1_CMIB1=177,IPR_TMR1_OVI1=177, +IPR_TMR2_CMIA2=180,IPR_TMR2_CMIB2=180,IPR_TMR2_OVI2=180, +IPR_TMR3_CMIA3=183,IPR_TMR3_CMIB3=183,IPR_TMR3_OVI3=183, +IPR_SCI0_ERI0=214,IPR_SCI0_RXI0=214,IPR_SCI0_TXI0=214,IPR_SCI0_TEI0=214, +IPR_SCI1_ERI1=218,IPR_SCI1_RXI1=218,IPR_SCI1_TXI1=218,IPR_SCI1_TEI1=218, +IPR_SCI5_ERI5=222,IPR_SCI5_RXI5=222,IPR_SCI5_TXI5=222,IPR_SCI5_TEI5=222, +IPR_SCI6_ERI6=226,IPR_SCI6_RXI6=226,IPR_SCI6_TXI6=226,IPR_SCI6_TEI6=226, +IPR_SCI8_ERI8=230,IPR_SCI8_RXI8=230,IPR_SCI8_TXI8=230,IPR_SCI8_TEI8=230, +IPR_SCI9_ERI9=234,IPR_SCI9_RXI9=234,IPR_SCI9_TXI9=234,IPR_SCI9_TEI9=234, +IPR_SCI12_ERI12=238,IPR_SCI12_RXI12=238,IPR_SCI12_TXI12=238,IPR_SCI12_TEI12=238,IPR_SCI12_SCIX0=242,IPR_SCI12_SCIX1=243,IPR_SCI12_SCIX2=244,IPR_SCI12_SCIX3=245, +IPR_RIIC0_EEI0=246,IPR_RIIC0_RXI0=247,IPR_RIIC0_TXI0=248,IPR_RIIC0_TEI0=249, +IPR_BSC_=0, +IPR_FCU_=2, +IPR_CMT0_=4, +IPR_CMT1_=5, +IPR_RSPI0_=44, +IPR_DOC_=57, +IPR_CTSU_=60, +IPR_REMC0_=94, +IPR_REMC1_=95, +IPR_MTU1_TGI=121, +IPR_MTU1_TCI=123, +IPR_MTU2_TGI=125, +IPR_MTU2_TCI=127, +IPR_MTU3_TGI=129, +IPR_MTU4_TGI=134, +IPR_MTU5_=139, +IPR_MTU5_TGI=139, +IPR_TMR0_=174, +IPR_TMR1_=177, +IPR_TMR2_=180, +IPR_TMR3_=183, +IPR_SCI0_=214, +IPR_SCI1_=218, +IPR_SCI5_=222, +IPR_SCI6_=226, +IPR_SCI8_=230, +IPR_SCI9_=234 +}; + +#define IEN_BSC_BUSERR IEN0 +#define IEN_FCU_FRDYI IEN7 +#define IEN_ICU_SWINT IEN3 +#define IEN_CMT0_CMI0 IEN4 +#define IEN_CMT1_CMI1 IEN5 +#define IEN_CAC_FERRF IEN0 +#define IEN_CAC_MENDF IEN1 +#define IEN_CAC_OVFF IEN2 +#define IEN_RSPI0_SPEI0 IEN4 +#define IEN_RSPI0_SPRI0 IEN5 +#define IEN_RSPI0_SPTI0 IEN6 +#define IEN_RSPI0_SPII0 IEN7 +#define IEN_DOC_DOPCF IEN1 +#define IEN_CMPB_CMPB0 IEN2 +#define IEN_CMPB_CMPB1 IEN3 +#define IEN_CTSU_CTSUWR IEN4 +#define IEN_CTSU_CTSURD IEN5 +#define IEN_CTSU_CTSUFN IEN6 +#define IEN_RTC_CUP IEN7 +#define IEN_ICU_IRQ0 IEN0 +#define IEN_ICU_IRQ1 IEN1 +#define IEN_ICU_IRQ2 IEN2 +#define IEN_ICU_IRQ3 IEN3 +#define IEN_ICU_IRQ4 IEN4 +#define IEN_ICU_IRQ5 IEN5 +#define IEN_ICU_IRQ6 IEN6 +#define IEN_ICU_IRQ7 IEN7 +#define IEN_ELC_ELSR8I IEN0 +#define IEN_LVD_LVD1 IEN0 +#define IEN_LVD_LVD2 IEN1 +#define IEN_RTC_ALM IEN4 +#define IEN_RTC_PRD IEN5 +#define IEN_REMC0_REMCI0 IEN6 +#define IEN_REMC1_REMCI1 IEN7 +#define IEN_S12AD_S12ADI0 IEN6 +#define IEN_S12AD_GBADI IEN7 +#define IEN_ELC_ELSR18I IEN2 +#define IEN_MTU0_TGIA0 IEN2 +#define IEN_MTU0_TGIB0 IEN3 +#define IEN_MTU0_TGIC0 IEN4 +#define IEN_MTU0_TGID0 IEN5 +#define IEN_MTU0_TCIV0 IEN6 +#define IEN_MTU0_TGIE0 IEN7 +#define IEN_MTU0_TGIF0 IEN0 +#define IEN_MTU1_TGIA1 IEN1 +#define IEN_MTU1_TGIB1 IEN2 +#define IEN_MTU1_TCIV1 IEN3 +#define IEN_MTU1_TCIU1 IEN4 +#define IEN_MTU2_TGIA2 IEN5 +#define IEN_MTU2_TGIB2 IEN6 +#define IEN_MTU2_TCIV2 IEN7 +#define IEN_MTU2_TCIU2 IEN0 +#define IEN_MTU3_TGIA3 IEN1 +#define IEN_MTU3_TGIB3 IEN2 +#define IEN_MTU3_TGIC3 IEN3 +#define IEN_MTU3_TGID3 IEN4 +#define IEN_MTU3_TCIV3 IEN5 +#define IEN_MTU4_TGIA4 IEN6 +#define IEN_MTU4_TGIB4 IEN7 +#define IEN_MTU4_TGIC4 IEN0 +#define IEN_MTU4_TGID4 IEN1 +#define IEN_MTU4_TCIV4 IEN2 +#define IEN_MTU5_TGIU5 IEN3 +#define IEN_MTU5_TGIV5 IEN4 +#define IEN_MTU5_TGIW5 IEN5 +#define IEN_POE_OEI1 IEN2 +#define IEN_POE_OEI2 IEN3 +#define IEN_TMR0_CMIA0 IEN6 +#define IEN_TMR0_CMIB0 IEN7 +#define IEN_TMR0_OVI0 IEN0 +#define IEN_TMR1_CMIA1 IEN1 +#define IEN_TMR1_CMIB1 IEN2 +#define IEN_TMR1_OVI1 IEN3 +#define IEN_TMR2_CMIA2 IEN4 +#define IEN_TMR2_CMIB2 IEN5 +#define IEN_TMR2_OVI2 IEN6 +#define IEN_TMR3_CMIA3 IEN7 +#define IEN_TMR3_CMIB3 IEN0 +#define IEN_TMR3_OVI3 IEN1 +#define IEN_SCI0_ERI0 IEN6 +#define IEN_SCI0_RXI0 IEN7 +#define IEN_SCI0_TXI0 IEN0 +#define IEN_SCI0_TEI0 IEN1 +#define IEN_SCI1_ERI1 IEN2 +#define IEN_SCI1_RXI1 IEN3 +#define IEN_SCI1_TXI1 IEN4 +#define IEN_SCI1_TEI1 IEN5 +#define IEN_SCI5_ERI5 IEN6 +#define IEN_SCI5_RXI5 IEN7 +#define IEN_SCI5_TXI5 IEN0 +#define IEN_SCI5_TEI5 IEN1 +#define IEN_SCI6_ERI6 IEN2 +#define IEN_SCI6_RXI6 IEN3 +#define IEN_SCI6_TXI6 IEN4 +#define IEN_SCI6_TEI6 IEN5 +#define IEN_SCI8_ERI8 IEN6 +#define IEN_SCI8_RXI8 IEN7 +#define IEN_SCI8_TXI8 IEN0 +#define IEN_SCI8_TEI8 IEN1 +#define IEN_SCI9_ERI9 IEN2 +#define IEN_SCI9_RXI9 IEN3 +#define IEN_SCI9_TXI9 IEN4 +#define IEN_SCI9_TEI9 IEN5 +#define IEN_SCI12_ERI12 IEN6 +#define IEN_SCI12_RXI12 IEN7 +#define IEN_SCI12_TXI12 IEN0 +#define IEN_SCI12_TEI12 IEN1 +#define IEN_SCI12_SCIX0 IEN2 +#define IEN_SCI12_SCIX1 IEN3 +#define IEN_SCI12_SCIX2 IEN4 +#define IEN_SCI12_SCIX3 IEN5 +#define IEN_RIIC0_EEI0 IEN6 +#define IEN_RIIC0_RXI0 IEN7 +#define IEN_RIIC0_TXI0 IEN0 +#define IEN_RIIC0_TEI0 IEN1 + +#define VECT_BSC_BUSERR 16 +#define VECT_FCU_FRDYI 23 +#define VECT_ICU_SWINT 27 +#define VECT_CMT0_CMI0 28 +#define VECT_CMT1_CMI1 29 +#define VECT_CAC_FERRF 32 +#define VECT_CAC_MENDF 33 +#define VECT_CAC_OVFF 34 +#define VECT_RSPI0_SPEI0 44 +#define VECT_RSPI0_SPRI0 45 +#define VECT_RSPI0_SPTI0 46 +#define VECT_RSPI0_SPII0 47 +#define VECT_DOC_DOPCF 57 +#define VECT_CMPB_CMPB0 58 +#define VECT_CMPB_CMPB1 59 +#define VECT_CTSU_CTSUWR 60 +#define VECT_CTSU_CTSURD 61 +#define VECT_CTSU_CTSUFN 62 +#define VECT_RTC_CUP 63 +#define VECT_ICU_IRQ0 64 +#define VECT_ICU_IRQ1 65 +#define VECT_ICU_IRQ2 66 +#define VECT_ICU_IRQ3 67 +#define VECT_ICU_IRQ4 68 +#define VECT_ICU_IRQ5 69 +#define VECT_ICU_IRQ6 70 +#define VECT_ICU_IRQ7 71 +#define VECT_ELC_ELSR8I 80 +#define VECT_LVD_LVD1 88 +#define VECT_LVD_LVD2 89 +#define VECT_RTC_ALM 92 +#define VECT_RTC_PRD 93 +#define VECT_REMC0_REMCI0 94 +#define VECT_REMC1_REMCI1 95 +#define VECT_S12AD_S12ADI0 102 +#define VECT_S12AD_GBADI 103 +#define VECT_ELC_ELSR18I 106 +#define VECT_MTU0_TGIA0 114 +#define VECT_MTU0_TGIB0 115 +#define VECT_MTU0_TGIC0 116 +#define VECT_MTU0_TGID0 117 +#define VECT_MTU0_TCIV0 118 +#define VECT_MTU0_TGIE0 119 +#define VECT_MTU0_TGIF0 120 +#define VECT_MTU1_TGIA1 121 +#define VECT_MTU1_TGIB1 122 +#define VECT_MTU1_TCIV1 123 +#define VECT_MTU1_TCIU1 124 +#define VECT_MTU2_TGIA2 125 +#define VECT_MTU2_TGIB2 126 +#define VECT_MTU2_TCIV2 127 +#define VECT_MTU2_TCIU2 128 +#define VECT_MTU3_TGIA3 129 +#define VECT_MTU3_TGIB3 130 +#define VECT_MTU3_TGIC3 131 +#define VECT_MTU3_TGID3 132 +#define VECT_MTU3_TCIV3 133 +#define VECT_MTU4_TGIA4 134 +#define VECT_MTU4_TGIB4 135 +#define VECT_MTU4_TGIC4 136 +#define VECT_MTU4_TGID4 137 +#define VECT_MTU4_TCIV4 138 +#define VECT_MTU5_TGIU5 139 +#define VECT_MTU5_TGIV5 140 +#define VECT_MTU5_TGIW5 141 +#define VECT_POE_OEI1 170 +#define VECT_POE_OEI2 171 +#define VECT_TMR0_CMIA0 174 +#define VECT_TMR0_CMIB0 175 +#define VECT_TMR0_OVI0 176 +#define VECT_TMR1_CMIA1 177 +#define VECT_TMR1_CMIB1 178 +#define VECT_TMR1_OVI1 179 +#define VECT_TMR2_CMIA2 180 +#define VECT_TMR2_CMIB2 181 +#define VECT_TMR2_OVI2 182 +#define VECT_TMR3_CMIA3 183 +#define VECT_TMR3_CMIB3 184 +#define VECT_TMR3_OVI3 185 +#define VECT_SCI0_ERI0 214 +#define VECT_SCI0_RXI0 215 +#define VECT_SCI0_TXI0 216 +#define VECT_SCI0_TEI0 217 +#define VECT_SCI1_ERI1 218 +#define VECT_SCI1_RXI1 219 +#define VECT_SCI1_TXI1 220 +#define VECT_SCI1_TEI1 221 +#define VECT_SCI5_ERI5 222 +#define VECT_SCI5_RXI5 223 +#define VECT_SCI5_TXI5 224 +#define VECT_SCI5_TEI5 225 +#define VECT_SCI6_ERI6 226 +#define VECT_SCI6_RXI6 227 +#define VECT_SCI6_TXI6 228 +#define VECT_SCI6_TEI6 229 +#define VECT_SCI8_ERI8 230 +#define VECT_SCI8_RXI8 231 +#define VECT_SCI8_TXI8 232 +#define VECT_SCI8_TEI8 233 +#define VECT_SCI9_ERI9 234 +#define VECT_SCI9_RXI9 235 +#define VECT_SCI9_TXI9 236 +#define VECT_SCI9_TEI9 237 +#define VECT_SCI12_ERI12 238 +#define VECT_SCI12_RXI12 239 +#define VECT_SCI12_TXI12 240 +#define VECT_SCI12_TEI12 241 +#define VECT_SCI12_SCIX0 242 +#define VECT_SCI12_SCIX1 243 +#define VECT_SCI12_SCIX2 244 +#define VECT_SCI12_SCIX3 245 +#define VECT_RIIC0_EEI0 246 +#define VECT_RIIC0_RXI0 247 +#define VECT_RIIC0_TXI0 248 +#define VECT_RIIC0_TEI0 249 + +#define MSTP_DTC SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DA SYSTEM.MSTPCRA.BIT.MSTPA19 +#define MSTP_S12AD SYSTEM.MSTPCRA.BIT.MSTPA17 +#define MSTP_CMT SYSTEM.MSTPCRA.BIT.MSTPA15 +#define MSTP_CMT0 SYSTEM.MSTPCRA.BIT.MSTPA15 +#define MSTP_CMT1 SYSTEM.MSTPCRA.BIT.MSTPA15 +#define MSTP_MTU SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU0 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU1 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU2 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU3 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU4 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU5 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_TMR0 SYSTEM.MSTPCRA.BIT.MSTPA5 +#define MSTP_TMR1 SYSTEM.MSTPCRA.BIT.MSTPA5 +#define MSTP_TMR01 SYSTEM.MSTPCRA.BIT.MSTPA5 +#define MSTP_TMR2 SYSTEM.MSTPCRA.BIT.MSTPA4 +#define MSTP_TMR3 SYSTEM.MSTPCRA.BIT.MSTPA4 +#define MSTP_TMR23 SYSTEM.MSTPCRA.BIT.MSTPA4 +#define MSTP_SCI0 SYSTEM.MSTPCRB.BIT.MSTPB31 +#define MSTP_SMCI0 SYSTEM.MSTPCRB.BIT.MSTPB31 +#define MSTP_SCI1 SYSTEM.MSTPCRB.BIT.MSTPB30 +#define MSTP_SMCI1 SYSTEM.MSTPCRB.BIT.MSTPB30 +#define MSTP_SCI5 SYSTEM.MSTPCRB.BIT.MSTPB26 +#define MSTP_SMCI5 SYSTEM.MSTPCRB.BIT.MSTPB26 +#define MSTP_SCI6 SYSTEM.MSTPCRB.BIT.MSTPB25 +#define MSTP_SMCI6 SYSTEM.MSTPCRB.BIT.MSTPB25 +#define MSTP_CRC SYSTEM.MSTPCRB.BIT.MSTPB23 +#define MSTP_RIIC0 SYSTEM.MSTPCRB.BIT.MSTPB21 +#define MSTP_RSPI0 SYSTEM.MSTPCRB.BIT.MSTPB17 +#define MSTP_CMPB SYSTEM.MSTPCRB.BIT.MSTPB10 +#define MSTP_ELC SYSTEM.MSTPCRB.BIT.MSTPB9 +#define MSTP_DOC SYSTEM.MSTPCRB.BIT.MSTPB6 +#define MSTP_SCI12 SYSTEM.MSTPCRB.BIT.MSTPB4 +#define MSTP_SMCI12 SYSTEM.MSTPCRB.BIT.MSTPB4 +#define MSTP_REMC0 SYSTEM.MSTPCRC.BIT.MSTPC29 +#define MSTP_REMC1 SYSTEM.MSTPCRC.BIT.MSTPC28 +#define MSTP_SCI8 SYSTEM.MSTPCRC.BIT.MSTPC27 +#define MSTP_SMCI8 SYSTEM.MSTPCRC.BIT.MSTPC27 +#define MSTP_SCI9 SYSTEM.MSTPCRC.BIT.MSTPC26 +#define MSTP_SMCI9 SYSTEM.MSTPCRC.BIT.MSTPC26 +#define MSTP_CAC SYSTEM.MSTPCRC.BIT.MSTPC19 +#define MSTP_RAM0 SYSTEM.MSTPCRC.BIT.MSTPC0 +#define MSTP_CTSU SYSTEM.MSTPCRD.BIT.MSTPD10 + +#define __IR( x ) ICU.IR[ IR ## x ].BIT.IR +#define _IR( x ) __IR( x ) +#define IR( x , y ) _IR( _ ## x ## _ ## y ) +#define __DTCE( x ) ICU.DTCER[ DTCE ## x ].BIT.DTCE +#define _DTCE( x ) __DTCE( x ) +#define DTCE( x , y ) _DTCE( _ ## x ## _ ## y ) +#define __IEN( x ) ICU.IER[ IER ## x ].BIT.IEN ## x +#define _IEN( x ) __IEN( x ) +#define IEN( x , y ) _IEN( _ ## x ## _ ## y ) +#define __IPR( x ) ICU.IPR[ IPR ## x ].BIT.IPR +#define _IPR( x ) __IPR( x ) +#define IPR( x , y ) _IPR( _ ## x ## _ ## y ) +#define __VECT( x ) VECT ## x +#define _VECT( x ) __VECT( x ) +#define VECT( x , y ) _VECT( _ ## x ## _ ## y ) +#define __MSTP( x ) MSTP ## x +#define _MSTP( x ) __MSTP( x ) +#define MSTP( x ) _MSTP( _ ## x ) + +#define BSC (*(volatile struct st_bsc *)0x81300) +#define CAC (*(volatile struct st_cac *)0x8B000) +#define CMPB (*(volatile struct st_cmpb *)0x8C580) +#define CMT (*(volatile struct st_cmt *)0x88000) +#define CMT0 (*(volatile struct st_cmt0 *)0x88002) +#define CMT1 (*(volatile struct st_cmt0 *)0x88008) +#define CRC (*(volatile struct st_crc *)0x88280) +#define CTSU (*(volatile struct st_ctsu *)0xA0900) +#define DA (*(volatile struct st_da *)0x880C0) +#define DOC (*(volatile struct st_doc *)0x8B080) +#define DTC (*(volatile struct st_dtc *)0x82400) +#define ELC (*(volatile struct st_elc *)0x8B100) +#define FLASH (*(volatile struct st_flash *)0x7FC090) +#define ICU (*(volatile struct st_icu *)0x87000) +#define IWDT (*(volatile struct st_iwdt *)0x88030) +#define LPT (*(volatile struct st_lpt *)0x800B0) +#define MPC (*(volatile struct st_mpc *)0x8C11F) +#define MTU (*(volatile struct st_mtu *)0x8860A) +#define MTU0 (*(volatile struct st_mtu0 *)0x88690) +#define MTU1 (*(volatile struct st_mtu1 *)0x88690) +#define MTU2 (*(volatile struct st_mtu2 *)0x88692) +#define MTU3 (*(volatile struct st_mtu3 *)0x88600) +#define MTU4 (*(volatile struct st_mtu4 *)0x88600) +#define MTU5 (*(volatile struct st_mtu5 *)0x88694) +#define POE (*(volatile struct st_poe *)0x88900) +#define PORT (*(volatile struct st_port *)0x8C120) +#define PORT0 (*(volatile struct st_port0 *)0x8C000) +#define PORT1 (*(volatile struct st_port1 *)0x8C001) +#define PORT2 (*(volatile struct st_port2 *)0x8C002) +#define PORT3 (*(volatile struct st_port3 *)0x8C003) +#define PORT4 (*(volatile struct st_port4 *)0x8C004) +#define PORT5 (*(volatile struct st_port5 *)0x8C005) +#define PORTA (*(volatile struct st_porta *)0x8C00A) +#define PORTB (*(volatile struct st_portb *)0x8C00B) +#define PORTC (*(volatile struct st_portc *)0x8C00C) +#define PORTD (*(volatile struct st_portd *)0x8C00D) +#define PORTE (*(volatile struct st_porte *)0x8C00E) +#define PORTH (*(volatile struct st_porth *)0x8C011) +#define PORTJ (*(volatile struct st_portj *)0x8C012) +#define REMC0 (*(volatile struct st_remc *)0xA0B00) +#define REMC1 (*(volatile struct st_remc *)0xA0B80) +#define REMCOM (*(volatile struct st_remcom *)0xA0C00) +#define RIIC0 (*(volatile struct st_riic *)0x88300) +#define RSPI0 (*(volatile struct st_rspi *)0x88380) +#define RTC (*(volatile struct st_rtc *)0x8C400) +#define RTCB (*(volatile struct st_rtcb *)0x8C402) +#define S12AD (*(volatile struct st_s12ad *)0x89000) +#define SCI0 (*(volatile struct st_sci0 *)0x8A000) +#define SCI1 (*(volatile struct st_sci0 *)0x8A020) +#define SCI5 (*(volatile struct st_sci0 *)0x8A0A0) +#define SCI6 (*(volatile struct st_sci0 *)0x8A0C0) +#define SCI8 (*(volatile struct st_sci0 *)0x8A100) +#define SCI9 (*(volatile struct st_sci0 *)0x8A120) +#define SCI12 (*(volatile struct st_sci12 *)0x8B300) +#define SMCI0 (*(volatile struct st_smci *)0x8A000) +#define SMCI1 (*(volatile struct st_smci1 *)0x8A020) +#define SMCI5 (*(volatile struct st_smci *)0x8A0A0) +#define SMCI6 (*(volatile struct st_smci1 *)0x8A0C0) +#define SMCI8 (*(volatile struct st_smci *)0x8A100) +#define SMCI9 (*(volatile struct st_smci1 *)0x8A120) +#define SMCI12 (*(volatile struct st_smci1 *)0x8B300) +#define SYSTEM (*(volatile struct st_system *)0x80000) +#define TEMPS (*(volatile struct st_temps *)0x7FC0AC) +#define TMR0 (*(volatile struct st_tmr0 *)0x88200) +#define TMR1 (*(volatile struct st_tmr1 *)0x88201) +#define TMR2 (*(volatile struct st_tmr0 *)0x88210) +#define TMR3 (*(volatile struct st_tmr1 *)0x88211) +#define TMR01 (*(volatile struct st_tmr01 *)0x88204) +#define TMR23 (*(volatile struct st_tmr01 *)0x88214) + +#pragma pack() +#endif diff --git a/drivers/rx/rdp/src/r_bsp/mcu/rx130/vecttbl.c b/drivers/rx/rdp/src/r_bsp/mcu/rx130/vecttbl.c new file mode 100644 index 00000000..c0bf0383 --- /dev/null +++ b/drivers/rx/rdp/src/r_bsp/mcu/rx130/vecttbl.c @@ -0,0 +1,132 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 - 2024 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : vecttbl.c +* Device(s) : RX130 +* Description : Definition of the fixed vector table and option setting memory. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 01.12.2015 1.00 First Release +* : 15.05.2017 1.01 Deleted unnecessary comments. +* : 01.11.2017 2.00 Added the bsp startup module disable function. +* : 28.02.2019 3.00 Deleted exception functions. +* (Exception functions moved to the common file (r_bsp_interrupts.c).) +* Added support for GNUC and ICCRX. +* Fixed coding style. +* : 08.10.2019 3.01 Changed for added support of Renesas RTOS (RI600V4 or RI600PX). +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +/* BSP configuration. */ +#include "platform.h" + +/* When using the user startup program, disable the following code. */ +#if BSP_CFG_STARTUP_DISABLE == 0 + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ +R_BSP_POR_FUNCTION(R_BSP_POWER_ON_RESET_FUNCTION); + +/*********************************************************************************************************************** +* The following array fills in the endian and option function select registers, and the fixed vector table +* bytes. +***********************************************************************************************************************/ +#ifdef __BIG + #define BSP_PRV_MDE_VALUE (0xfffffff8) /* big */ +#else + #define BSP_PRV_MDE_VALUE (0xffffffff) /* little */ +#endif + +#if defined(__ICCRX__) + +#pragma public_equ = "__MDES", BSP_PRV_MDE_VALUE +#pragma public_equ = "__OFS1", BSP_CFG_OFS1_REG_VALUE +#pragma public_equ = "__OFS0", BSP_CFG_OFS0_REG_VALUE +#pragma public_equ = "__ID_BYTES_1_4", BSP_CFG_ID_CODE_LONG_1 +#pragma public_equ = "__ID_BYTES_5_8", BSP_CFG_ID_CODE_LONG_2 +#pragma public_equ = "__ID_BYTES_9_12", BSP_CFG_ID_CODE_LONG_3 +#pragma public_equ = "__ID_BYTES_13_16", BSP_CFG_ID_CODE_LONG_4 + +#endif /* defined(__ICCRX__) */ + +#if BSP_CFG_RTOS_USED == 4 /* Renesas RI600V4 & RI600PX */ + /* System configurator generates the ritble.src as interrupt & exception vector tables. */ +#else /* BSP_CFG_RTOS_USED!=4 */ + +#if defined(__CCRX__) || defined(__GNUC__) +R_BSP_ATTRIB_SECTION_CHANGE_FIXEDVECT void * const Fixed_Vectors[] = +{ + /* The Endian select register (MDE), Option function select register 1 (OFS1), and Option function select + register 0 (OFS0) are located in User ROM. */ + (void *)BSP_PRV_MDE_VALUE, /* 0xffffff80 - MDE */ + (void *)0xFFFFFFFF, /* 0xffffff84 - Reserved */ + (void *)BSP_CFG_OFS1_REG_VALUE, /* 0xffffff88 - OFS1 */ + (void *)BSP_CFG_OFS0_REG_VALUE, /* 0xffffff8c - OFS0 */ + + /* 0xffffff90 through 0xffffffaf: Reserved area */ + (void *)0xFFFFFFFF, /* 0xffffff90 - Reserved */ + (void *)0xFFFFFFFF, /* 0xffffff94 - Reserved */ + (void *)0xFFFFFFFF, /* 0xffffff98 - Reserved */ + (void *)0xFFFFFFFF, /* 0xffffff9c - Reserved */ + + /* 0xffffffa0 through 0xffffffaf: ID Code Protection. The ID code is specified using macros in r_bsp_config.h. */ + (void *) BSP_CFG_ID_CODE_LONG_1, /* 0xffffffa0 - Control code and ID code */ + (void *) BSP_CFG_ID_CODE_LONG_2, /* 0xffffffa4 - ID code (cont.) */ + (void *) BSP_CFG_ID_CODE_LONG_3, /* 0xffffffa8 - ID code (cont.) */ + (void *) BSP_CFG_ID_CODE_LONG_4, /* 0xffffffac - ID code (cont.) */ + + /* 0xffffffb0 through 0xffffffcf: Reserved area */ + (void *) 0xFFFFFFFF, /* 0xffffffb0 - Reserved */ + (void *) 0xFFFFFFFF, /* 0xffffffb4 - Reserved */ + (void *) 0xFFFFFFFF, /* 0xffffffb8 - Reserved */ + (void *) 0xFFFFFFFF, /* 0xffffffbc - Reserved */ + (void *) 0xFFFFFFFF, /* 0xffffffc0 - Reserved */ + (void *) 0xFFFFFFFF, /* 0xffffffc4 - Reserved */ + (void *) 0xFFFFFFFF, /* 0xffffffc8 - Reserved */ + (void *) 0xFFFFFFFF, /* 0xffffffcc - Reserved */ + + /* Fixed vector table */ + (void *) excep_supervisor_inst_isr, /* 0xffffffd0 Exception(Supervisor Instruction) */ + (void *) undefined_interrupt_source_isr, /* 0xffffffd4 Reserved */ + (void *) undefined_interrupt_source_isr, /* 0xffffffd8 Reserved */ + (void *) excep_undefined_inst_isr, /* 0xffffffdc Exception(Undefined Instruction) */ + (void *) undefined_interrupt_source_isr, /* 0xffffffe0 Reserved */ + (void *) undefined_interrupt_source_isr, /* 0xffffffe4 Reserved */ + (void *) undefined_interrupt_source_isr, /* 0xffffffe8 Reserved */ + (void *) undefined_interrupt_source_isr, /* 0xffffffec Reserved */ + (void *) undefined_interrupt_source_isr, /* 0xfffffff0 Reserved */ + (void *) undefined_interrupt_source_isr, /* 0xfffffff4 Reserved */ + (void *) non_maskable_isr, /* 0xfffffff8 NMI */ + (void *) R_BSP_POWER_ON_RESET_FUNCTION /* 0xfffffffc RESET */ +}; +R_BSP_ATTRIB_SECTION_CHANGE_END +#endif /* defined(__CCRX__), defined(__GNUC__) */ + +#endif/* BSP_CFG_RTOS_USED */ + +#endif /* BSP_CFG_STARTUP_DISABLE == 0 */ + diff --git a/drivers/rx/rdp/src/r_bsp/mcu/rx130/vecttbl.h b/drivers/rx/rdp/src/r_bsp/mcu/rx130/vecttbl.h new file mode 100644 index 00000000..7d41f7ec --- /dev/null +++ b/drivers/rx/rdp/src/r_bsp/mcu/rx130/vecttbl.h @@ -0,0 +1,49 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 - 2024 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : vecttbl.h +* Description : Has function prototypes for exception callback functions. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 01.12.2015 1.00 First release +* 28.02.2019 1.01 Fixed coding style. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef VECTTBL_HEADER_INC +#define VECTTBL_HEADER_INC + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ + +#endif /* VECTTBL_HEADER_INC */ + diff --git a/drivers/rx/rdp/src/r_bsp/platform.h b/drivers/rx/rdp/src/r_bsp/platform.h new file mode 100644 index 00000000..f89abe1a --- /dev/null +++ b/drivers/rx/rdp/src/r_bsp/platform.h @@ -0,0 +1,246 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2011 - 2024 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : platform.h +* Description : The user chooses which MCU and board they are developing for in this file. If the board you are using +* is not listed below, please add your own or use the default 'User Board'. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 30.11.2011 1.00 First Release +* : 13.01.2012 1.10 Moved from having platform defined using macro definition, to having platform defined +* by choosing an include path. This makes this file simpler and cleans up the issue +* where HEW shows all header files for all platforms under 'Dependencies'. +* : 14.02.2012 1.20 Added RX210 BSP. +* : 18.04.2012 1.30 Updated to v0.70 of FIT S/W Spec and v0.20 of FIT r_bsp Spec. This includes adding +* locking.c and locking.h in board folders. Also, r_bsp can now be configured through +* r_bsp_config.h. +* : 26.06.2012 1.40 Added new options such as exception callbacks and the ability to choose your MCU using +* its part number in r_bsp_config.h. Moved mcu_info.h to the 'mcu' folder. Made an effort +* to remove any extra files that the user would need to touch. Removed the flash_options.c +* file and put its contents in vecttbl.c. +* : 17.07.2012 1.50 Fixed bug with exception callback function names. Added BCLK_OUTPUT and SDCLK_OUTPUT +* macro options in r_bsp_config.h. Added some extra code to handle exceptions in +* vecttbl.c. Added vecttbl.h so that user has prototypes for exception callbacks. +* : 09.08.2012 1.60 Added IO_LIB_ENABLE macro to r_bsp_config_reference.h. +* : 14.11.2012 1.70 Added RSKRX62G, RSKRX63T, and RSKRX111 support. +* : 28.11.2012 2.00 Updated to be compliant with v1.00 r_bsp specification. +* : 21.01.2013 2.10 Added RSKRX63T_144PIN support. +* : 10.05.2013 2.20 Added new packages and memory variants to RX210. All iodefine.h files have been updated +* to latest revisions. On reset, all MCUs will now initialize non-bonded out pins to +* reduce current draw. r_bsp_common.c and .h files were added to support functionality +* common to all BSPs. cpu.c and cpu.h files were added to all MCU groups to support +* CPU functions such as enabling/disabling interrupts, setting the IPL, and controlling +* register protection. mcu_init.c and mcu_init.h were add to all MCU groups to support +* initialization functions that are common to a MCU group such as non-bonded pin init. +* Choosing MCU endian has been removed from r_bsp_config.h and is now automatically +* set based on compiler macros. RX-C, IAR, and GCC endian macros are supported. RX210 +* now has support for choosing HOCO frequency. All r_bsp_config.h files now have macro +* for defining Vcc which is needed by some FIT modules. IRQ locks were added for all +* MCU groups. BSP_PACKAGE_PINS macro was added to mcu_info.h which defines number of pins +* for the currently chosen package. RX111 and RX210 now have the option of using the +* r_cgc_rx module for clock management based on BSP_CFG_USE_CGC_MODULE macro in +* r_bsp_config.h. +* : 31.05.2013 2.21 Added latest iodefine.h files for RX111 (v0.9a), RX630 (v1,50a), and RX63N (v1.60). Also +* added 'doc' folder to root of r_bsp. Currently the only the document in there is the +* preliminary version of the r_bsp User's Manual. For RX210, the ability to choose chip +* version C was added to its r_bsp_config.h file. +* : 01.07.2013 2.30 Removed RSPI pin setup in RSKRX111 which caused excess current draw in low power +* modes. Changed FIT_NO_PTR and FIT_NO_FUNC macros to 0x10000000 which works for all +* RX MCUs. Added ability for user to use 1 or 2 stacks for RX MCUs. Added new interrupt +* handling features which allows for interrupt callback registration. This feature allows +* all interrupts that map to the NMI vector to be used and replaces the static callback +* definitions that were in r_bsp_config.h previously. RX111 information has been updated +* according to v1.00 HW manual. This includes support for 40-pin packages. All compiler +* messages and warnings for lowsrc.c have been cleaned up. Non-existent port init has +* been moved to end of hardware_setup() to ensure user does not overwrite the settings. +* Added blank lines between clock macros in r_bsp_config.h to aid in readability. Added +* '(void *)' cast to FIT_NO_PTR to remove compiler warnings. All r_bsp.h files now include +* r_bsp_common.h which has common includes (stdint.h, stddef.h, & stdbool.h) and uses +* r_typedefs.h when C99 is not available. RX111 and RX210 MCUs have the option of using +* the r_cgc_rx module for clock management. When this is used, the clock info macros in +* mcu_info.h (e.g. BSP_ICLK_HZ) will now make calls to the r_cgc_rx module instead of +* providing static info. For debug console output, lowlvl.src was replaced by lowlvl.c +* (assembly converted to C source). +* : 10.02.2014 2.40 Added support for the RSKRX110, RPBRX111, RSKRX220, and HSBRX21AP. Made sure +* in hwsetup.c files that the PMR registers are set after the MPC registers. Replaced +* use of stdint.h, stdbool.h, and stddef.h with platform.h to remove compiler warnings. +* Removed includes for machine.h since it is compiler specific and replaced with +* platform.h. Fixed bug in resetprg.c for many boards where LOCO was not being turned off +* when it was not being used. RX100 code now uses the oscillation stabilization flags +* instead of SW delay loop. Changed size_t to unsigned long. Defined PRC2 in register +* protection section for RX111. Fixed bug in non-existent pin setup for RX111. No +* platform is chosen by default (used to be the RSKRX111). This makes it easier to +* understand the problem when you build a new project and have not selected your platform. +* : 24.03.2014 2.50 Added support for the RSKRX64M. +* : 16.06.2014 2.60 Added version control for r_bsp_config.h Two user callback functions may now be +* configured allowing callbacks from PowerON_Reset_PC() for warm start detection. +* Stdio charget() and charput() functions may now be redirected to user defined functions. +* Added support for RSKRX631 and RDKRX631. +* : 05.08.2014 2.70 Added support for RSKRX113. +* : 29.09.2014 2.80 Added support for RSKRX71M. +* : 22.12.2014 2.90 Added support for RSKRX231. +* : 30.09.2015 3.00 Added support for RSSKRX23T and RSKRX23T. +* : 30.09.2015 3.01 Fix for RSKRX231 and RSKRX23T(RSSKRX23T). +* : 01.12.2015 3.10 Added support for RSKRX130. +* : 01.02.2016 3.20 Added support for RSKRX24T. +* : 29.02.2016 3.30 Added support for RSKRX230. +* : 01.10.2016 3.40 Added support for RSKRX65N. +* : 22.08.2016 3.50 Added support for RSKRX24U. +* : 15.05.2017 3.60 Added support for RSKRX65N-2MB. +* Added support for GENERIC_RX65N. +* Added support for RSKRX130-512KB. +* : 01.11.2017 3.70 Added support for GENERIC_RX130. +* Added support for GENERIC_RX110. +* Added support for GENERIC_RX111. +* Added support for GENERIC_RX113. +* Added support for GENERIC_RX230. +* Added support for GENERIC_RX231. +* Added support for GENERIC_RX23T. +* Added support for GENERIC_RX24T. +* Added support for GENERIC_RX24U. +* Added support for GENERIC_RX64M. +* Added support for GENERIC_RX71M. +* Added support for ENVISIONRX65N. +* : 01.11.2017 3.71 Corrected typo in Rev3.70 BSP. +* : 01.07.2018 3.80 Added support for TARGETBOARDRX65N. +* Added support for TARGETBOARDRX231. +* Added support for TARGETBOARDRX130. +* : 27.07.2018 3.90 Added support for GENERIC_RX66T. +* Deleted the below board folders, since other boards can all be substituted with +* GENERIC_RXxxx. +* - RSKRX64M, RSKRX65N, RSKRX65N_2MB, TARGETBOARDRX65N, ENVISIONRX65N, RSKRX71M, +* RSKRX230, RSKRX231, TARGETBOARDRX231, RSKRX110, RSKRX111, RPBRX111, RSKRX113, +* RSKRX130, RSKRX130_512KB, and TARGETBOARDRX130 +* : 31.10.2018 4.00 Added support for GENERIC_RX72T. +* Deleted the below board folders, since other boards can all be substituted with +* GENERIC_RXxxx. +* - RSSKRX23T, RSKRX23T, RSKRX24T, and RSKRX24U +* : 28.02.2019 5.00 Deleted the below board folders. +* - RSKRX610, RSKRX62N, RSKRX62T, RSKRX62G, RDKRX62N, RSKRX630, RSKRX631, RSKRX63T_64PIN, +* RSKRX63T_144PIN, RDKRX63N, RDKRX631, RSKRX210, HSBRX21AP and RSKRX220 +* : 29.03.2019 5.10 Added support for GENERIC_RX23W. +* : 08.04.2019 5.20 Added support for GENERIC_RX72M. +* : 26.07.2019 5.30 Added support for GENERIC_RX13T. +* : 31.07.2019 5.40 Added support for GENERIC_RX23E-A. +* : 08.10.2019 5.50 Added support for GENERIC_RX72N, and GENERIC_RX66N. +* Deleted the board folders of RSKRX63N. +* : 18.05.2021 6.11 Added support for GENERIC_RX671. +* : 30.06.2021 6.20 Added support for GENERIC_RX140. +* : 22.04.2022 7.20 Added support for GENERIC_RX660. +* : 28.02.2023 7.30 Added support for GENERIC_RX26T. +* : 10.03.2023 7.40 Added support for GENERIC_RX23E-B. +***********************************************************************************************************************/ + +/* Multiple inclusion prevention macro */ +#ifndef PLATFORM_H +#define PLATFORM_H + +/*********************************************************************************************************************** +DEFINE YOUR SYSTEM - UNCOMMENT THE INCLUDE PATH FOR THE PLATFORM YOU ARE USING. +***********************************************************************************************************************/ +/* GENERIC_RX64M */ +//#include "./board/generic_rx64m/r_bsp.h" + +/* GENERIC_RX65N */ +//#include "./board/generic_rx65n/r_bsp.h" + +/* GENERIC_RX660 */ +//#include "./board/generic_rx660/r_bsp.h" + +/* GENERIC_RX66N */ +//#include "./board/generic_rx66n/r_bsp.h" + +/* GENERIC_RX66T */ +//#include "./board/generic_rx66t/r_bsp.h" + +/* GENERIC_RX671 */ +//#include "./board/generic_rx671/r_bsp.h" + +/* GENERIC_RX71M */ +//#include "./board/generic_rx71m/r_bsp.h" + +/* GENERIC_RX72M */ +//#include "./board/generic_rx72m/r_bsp.h" + +/* GENERIC_RX72N */ +//#include "./board/generic_rx72n/r_bsp.h" + +/* GENERIC_RX72T */ +//#include "./board/generic_rx72t/r_bsp.h" + +/* GENERIC_RX230 */ +//#include "./board/generic_rx230/r_bsp.h" + +/* GENERIC_RX231 */ +//#include "./board/generic_rx231/r_bsp.h" + +/* GENERIC_RX23E-A */ +//#include "./board/generic_rx23e-a/r_bsp.h" + +/* GENERIC_RX23E-B */ +//#include "./board/generic_rx23e-b/r_bsp.h" + +/* GENERIC_RX23T */ +//#include "./board/generic_rx23t/r_bsp.h" + +/* GENERIC_RX23W */ +//#include "./board/generic_rx23w/r_bsp.h" + +/* GENERIC_RX24T */ +//#include "./board/generic_rx24t/r_bsp.h" + +/* GENERIC_RX24U */ +//#include "./board/generic_rx24u/r_bsp.h" + +/* GENERIC_RX26T */ +//#include "./board/generic_rx26t/r_bsp.h" + +/* GENERIC_RX111 */ +//#include "./board/generic_rx111/r_bsp.h" + +/* GENERIC_RX110 */ +//#include "./board/generic_rx110/r_bsp.h" + +/* GENERIC_RX113 */ +//#include "./board/generic_rx113/r_bsp.h" + +/* GENERIC_RX130 */ +#if defined(CONFIG_SOC_SERIES_RX130) +#include "./board/generic_rx130/r_bsp.h" +#endif + +/* GENERIC_RX13T */ +//#include "./board/generic_rx13t/r_bsp.h" + +/* GENERIC_RX140 */ +//#include "./board/generic_rx140/r_bsp.h" + +/* User Board - Define your own board here. */ +//#include "./board/user/r_bsp.h" + +/*********************************************************************************************************************** +MAKE SURE AT LEAST ONE PLATFORM WAS DEFINED - DO NOT EDIT BELOW THIS POINT +***********************************************************************************************************************/ +#ifndef PLATFORM_DEFINED +#error "Error - No platform defined in platform.h!" +#endif + +#endif /* PLATFORM_H */ + diff --git a/zephyr/CMakeLists.txt b/zephyr/CMakeLists.txt index a6156c37..36a6b1e8 100644 --- a/zephyr/CMakeLists.txt +++ b/zephyr/CMakeLists.txt @@ -1,3 +1,4 @@ # SPDX-License-Identifier: Apache-2.0 add_subdirectory_ifdef(CONFIG_HAS_RENESAS_RA_FSP ra) +add_subdirectory_ifdef(CONFIG_HAS_RENESAS_RX_RDP rx) diff --git a/zephyr/rx/CMakeLists.txt b/zephyr/rx/CMakeLists.txt new file mode 100644 index 00000000..aea84aff --- /dev/null +++ b/zephyr/rx/CMakeLists.txt @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: Apache-2.0 + +add_subdirectory(rdp_cfg) diff --git a/zephyr/rx/rdp_cfg/CMakeLists.txt b/zephyr/rx/rdp_cfg/CMakeLists.txt new file mode 100644 index 00000000..7ab7531b --- /dev/null +++ b/zephyr/rx/rdp_cfg/CMakeLists.txt @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(r_config) +zephyr_include_directories(r_config/${CONFIG_SOC_SERIES}) diff --git a/zephyr/rx/rdp_cfg/r_config/rx130/r_bsp_config.h b/zephyr/rx/rdp_cfg/r_config/rx130/r_bsp_config.h new file mode 100644 index 00000000..c0571640 --- /dev/null +++ b/zephyr/rx/rdp_cfg/r_config/rx130/r_bsp_config.h @@ -0,0 +1,686 @@ +/* + * Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* Generated configuration header file - do not edit */ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2017 - 2024 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_bsp_config_reference.h +* Device(s) : RX130 +* Description : The file r_bsp_config.h is used to configure your BSP. r_bsp_config.h should be included +* somewhere in your package so that the r_bsp code has access to it. This file (r_bsp_config_reference.h) +* is just a reference file that the user can use to make their own r_bsp_config.h file. +************************************************************************************************************************ +* History : DD.MM.YYYY Version Description +* : 15.05.2017 1.00 First release +* : 01.11.2017 2.00 Added the following macro definition. +* - BSP_CFG_STARTUP_DISABLE +* Added definition not selecting clock to BSP_CFG_LPT_CLOCK_SOURCE. +* Changed The default value to 2 for BSP_CFG_LPT_CLOCK_SOURCE. +* : 01.07.2018 1.02 Added the following macro definition. +* - BSP_CFG_CONFIGURATOR_SELECT +* : 27.07.2018 1.03 Added the following macro definition. +* - BSP_CFG_FIT_IPL_MAX +* : 28.02.2019 2.00 Added the following macro definition. +* - BSP_CFG_MAIN_CLOCK_SOURCE +* - BSP_CFG_MOSC_WAIT_TIME +* - BSP_CFG_RTC_ENABLE +* - BSP_CFG_SOSC_DRV_CAP +* - BSP_CFG_SOSC_WAIT_TIME +* Modified comments of the following macro definition. +* - BSP_CFG_RTOS_USED +* Added support for GNUC and ICCRX. +* Fixed coding style. +* Changed the default value of the following macro definition. +* - BSP_CFG_MOSC_WAIT_TIME - Changed the default value from 0x06 to 0x04. +* : 23.07.2019 2.01 Modified comments of the following macro definition. +* - BSP_CFG_RTOS_USED : The value '1'(FreeRTOS is used.) is available. +* Added the following macro definition. +* - BSP_CFG_RTOS_SYSTEM_TIMER +* : 08.10.2019 2.02 Added the following macro definition. +* - BSP_CFG_SWINT_UNIT1_ENABLE +* - BSP_CFG_SWINT_TASK_BUFFER_NUMBER +* - BSP_CFG_SWINT_IPR_INITIAL_VALUE +* Modified comment for added support of Renesas RTOS (RI600V4 or RI600PX). +* Added the following macro definition. +* - BSP_CFG_RENESAS_RTOS_USED +* : 29.01.2021 2.03 Added the following macro definition. +* - BSP_CFG_SCI_UART_TERMINAL_ENABLE +* - BSP_CFG_SCI_UART_TERMINAL_CHANNEL +* - BSP_CFG_SCI_UART_TERMINAL_BITRATE +* - BSP_CFG_SCI_UART_TERMINAL_INTERRUPT_PRIORITY +* : 26.02.2021 2.04 Added a comment for Azure RTOS to BSP_CFG_RTOS_USED. +* : 30.11.2021 3.00 Added the following macro definitions. +* - BSP_CFG_MAIN_CLOCK_OSCILLATE_ENABLE +* - BSP_CFG_SUB_CLOCK_OSCILLATE_ENABLE +* - BSP_CFG_HOCO_OSCILLATE_ENABLE +* - BSP_CFG_LOCO_OSCILLATE_ENABLE +* - BSP_CFG_IWDT_CLOCK_OSCILLATE_ENABLE +* - BSP_CFG_CLKOUT_SOURCE +* - BSP_CFG_CLKOUT_DIV +* - BSP_CFG_CLKOUT_OUTPUT +* - BSP_CFG_HOCO_TRIMMING_ENABLE +* - BSP_CFG_HOCO_TRIMMING_REG_VALUE +* - BSP_CFG_CONFIGURATOR_VERSION +* - BSP_CFG_CPLUSPLUS +* Changed initial value of the following macro definitions. +* - BSP_CFG_MCU_PART_GROUP +* - BSP_CFG_MCU_PART_SERIES +* : 11.02.2022 3.01 Changed initial value of the following macro definitions. +* - BSP_CFG_SWINT_UNIT1_ENABLE +* : 28.02.2023 3.02 Modified comment. +* : 21.11.2023 3.03 Added the following macro definitions. +* - BSP_CFG_BUS_PRIORITY_INITIALIZE_ENABLE +* - BSP_CFG_MEMORY_BUS1_PRIORITY +* - BSP_CFG_MEMORY_BUS2_PRIORITY +* - BSP_CFG_INTERNAL_PERIPHERAL_BUS1_PRIORITY +* - BSP_CFG_INTERNAL_PERIPHERAL_BUS2_3_PRIORITY +* - BSP_CFG_INTERNAL_PERIPHERAL_BUS6_PRIORITY +* - BSP_CFG_BOOTLOADER_PROJECT +***********************************************************************************************************************/ + +#include +#include +#include +#include "mcu_clocks.h" + +#ifndef R_BSP_CONFIG_REF_HEADER_FILE +#define R_BSP_CONFIG_REF_HEADER_FILE + +/*********************************************************************************************************************** +Configuration Options +***********************************************************************************************************************/ + +/* NOTE: + The default settings are the same as when using RSKRX130-512KB. + Change to the settings for the user board. +*/ + +/* Start up select + 0 = Enable BSP startup program. + 1 = Disable BSP startup program. (e.g. Using user startup program.) + NOTE: This setting is available only when using CCRX. */ +#define BSP_CFG_STARTUP_DISABLE (0) + +/* Enter the product part number for your MCU. This information will be used to obtain information about your MCU such + as package and memory size. + To help parse this information, the part number will be defined using multiple macros. + R 5 F 51 30 8 A D FP - - + | | | | | | | | | | | Macro Name Description + | | | | | | | | | | |_not used = Production identification code + | | | | | | | | | |____not used = Packing, Terminal material + | | | | | | | | |_______BSP_CFG_MCU_PART_PACKAGE = Package type, number of pins, and pin pitch + | | | | | | | |_________not used = Operating temperature + | | | | | | |___________not used = Blank + | | | | | |_____________BSP_CFG_MCU_PART_MEMORY_SIZE = ROM, RAM, and Data Flash Capacity + | | | | |________________BSP_CFG_MCU_PART_GROUP = Group name + | | | |___________________BSP_CFG_MCU_PART_SERIES = Series name + | | |_____________________BSP_CFG_MCU_PART_MEMORY_TYPE = Type of memory (Flash) + | |_______________________not used = Renesas MCU + |_________________________not used = Renesas semiconductor product. + */ + +/* Package type. Set the macro definition based on values below: + Character(s) = Value for macro = Package Type/Number of Pins/Pin Pitch + FP = 0x5 = LFQFP/100/0.50 + FN = 0xB = LFQFP/80/0.50 + FM = 0x0 = LFQFP/64/0.50 + FK = 0x1 = LQFP/64/0.80 + FL = 0x3 = LFQFP/48/0.50 + NE = 0x4 = HWQFN/48/0.50 +*/ +#define BSP_CFG_MCU_PART_PACKAGE (0x5) /* Generated value. Do not edit this manually */ + +/* ROM, RAM, and Data Flash Capacity. + Character(s) = Value for macro = ROM Size/Ram Size/Data Flash Size + 8 = 0x8 = 512KB/48KB/8KB + 7 = 0x7 = 384KB/48KB/8KB + 6 = 0x6 = 256KB/32KB/8KB + 5 = 0x5 = 128KB/16KB/8KB + 3 = 0x3 = 64KB/10KB/8KB +*/ +#define BSP_CFG_MCU_PART_MEMORY_SIZE (0x8) /* Generated value. Do not edit this manually */ + +/* Group name. + Character(s) = Description + 30 = RX130 Group +*/ +#define BSP_CFG_MCU_PART_GROUP "RX130" /* Generated value. Do not edit this manually */ + +/* Series name. + Character(s) = Description + 51 = RX100 Series +*/ +#define BSP_CFG_MCU_PART_SERIES "RX100" /* Generated value. Do not edit this manually */ + +/* Memory type. + Character(s) = Value for macro = Description + F = 0x0 = Flash memory version +*/ +#define BSP_CFG_MCU_PART_MEMORY_TYPE (0x0) /* Generated value. Do not edit this manually */ + +/* Whether to use 1 stack or 2. RX MCUs have the ability to use 2 stacks: an interrupt stack and a user stack. + * When using 2 stacks the user stack will be used during normal user code. When an interrupt occurs the CPU + * will automatically shift to using the interrupt stack. Having 2 stacks can make it easier to figure out how + * much stack space to allocate since the user does not have to worry about always having enough room on the + * user stack for if-and-when an interrupt occurs. Some users will not want 2 stacks though because it is not + * needed in all applications and can lead to wasted RAM (i.e. space in between stacks that is not used). + * If only 1 stack is used then the interrupt stack is the one that will be used. If 1 stack is chosen then + * the user may want to remove the 'SU' section from the linker sections to remove any linker warnings. + * + * 0 = Use 1 stack. Disable user stack. User stack size set below will be ignored. + * 1 = Use 2 stacks. User stack and interrupt stack will both be used. + * NOTE: This setting is available only when using CCRX and GNUC. + * This is invalid when using Renesas RTOS with CCRX. + */ +#define BSP_CFG_USER_STACK_ENABLE (1) + +/* If only 1 stack is chosen using BSP_CFG_USER_STACK_ENABLE then no RAM will be allocated for the user stack. */ +#if BSP_CFG_USER_STACK_ENABLE == 1 +/* User Stack size in bytes. + * NOTE: This setting is available only when using CCRX and GNUC. + * This is invalid when using Renesas RTOS with CCRX. */ +#define BSP_CFG_USTACK_BYTES (0x400) +#endif + +/* Interrupt Stack size in bytes. + NOTE: This setting is available only when using CCRX and GNUC. */ +#define BSP_CFG_ISTACK_BYTES (0x100) + +/* Heap size in bytes. + To disable the heap you must follow these steps: + 1) Set this macro (BSP_CFG_HEAP_BYTES) to 0. + 2) Set the macro BSP_CFG_IO_LIB_ENABLE to 0. + 3) Disable stdio from being built into the project library. This is done by going into the Renesas RX Toolchain + settings and choosing the Standard Library section. After that choose 'Contents' in e2 studio. + This will present a list of modules that can be included. Uncheck the box for stdio.h. + NOTE: This setting is available only when using CCRX and GNUC. */ +#define BSP_CFG_HEAP_BYTES (0x400) + +/* Initializes C input & output library functions. + 0 = Disable I/O library initialization in resetprg.c. If you are not using stdio then use this value. + 1 = Enable I/O library initialization in resetprg.c. This is default and needed if you are using stdio. + NOTE: This setting is available only when using CCRX. */ +#define BSP_CFG_IO_LIB_ENABLE (0) + +/* If desired the user may redirect the stdio charget() and/or charput() functions to their own respective functions + by enabling below and providing and replacing the my_sw_... function names with the names of their own functions. */ +#define BSP_CFG_USER_CHARGET_ENABLED (0) +#define BSP_CFG_USER_CHARGET_FUNCTION my_sw_charget_function + +#define BSP_CFG_USER_CHARPUT_ENABLED (0) +#define BSP_CFG_USER_CHARPUT_FUNCTION my_sw_charput_function + +/* After reset MCU will operate in Supervisor mode. To switch to User mode, set this macro to '1'. For more information + on the differences between these 2 modes see the CPU >> Processor Mode section of your MCU's hardware manual. + 0 = Stay in Supervisor mode. + 1 = Switch to User mode. + NOTE: This is invalid when using Renesas RTOS with CCRX. +*/ +#define BSP_CFG_RUN_IN_USER_MODE (0) + +/* Set your desired ID code. NOTE, leave at the default (all 0xFF's) if you do not wish to use an ID code. If you set + this value and program it into the MCU then you will need to remember the ID code because the debugger will ask for + it when trying to connect. Note that the E1/E20 will ignore the ID code when programming the MCU during debugging. + If you set this value and then forget it then you can clear the ID code by connecting up in serial boot mode using + FDT. The ID Code is 16 bytes long. The macro below define the ID Code in 4-byte sections. */ +/* Lowest 4-byte section, address 0xFFFFFFA0. From MSB to LSB: Control Code, ID code 1, ID code 2, ID code 3. */ +#define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF) +/* 2nd ID Code section, address 0xFFFFFFA4. From MSB to LSB: ID code 4, ID code 5, ID code 6, ID code 7. */ +#define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF) +/* 3rd ID Code section, address 0xFFFFFFA8. From MSB to LSB: ID code 8, ID code 9, ID code 10, ID code 11. */ +#define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF) +/* 4th ID Code section, address 0xFFFFFFAC. From MSB to LSB: ID code 12, ID code 13, ID code 14, ID code 15. */ +#define BSP_CFG_ID_CODE_LONG_4 (0xFFFFFFFF) + +/* Select whether to oscillate the Main Clock Oscillator. + 0 = Stop Oscillating the Main Clock. + 1 = Enable oscillating the Main Clock. (default) +*/ +#define BSP_CFG_MAIN_CLOCK_OSCILLATE_ENABLE DT_NODE_HAS_STATUS(DT_NODELABEL(xtal), okay) + +/* Select whether to oscillate the Sub Clock Oscillator. + 0 = Stop Oscillating the Sub Clock. (default) + 1 = Enable Oscillating the Sub Clock. +*/ +#define BSP_CFG_SUB_CLOCK_OSCILLATE_ENABLE DT_NODE_HAS_STATUS(DT_NODELABEL(subclk), okay) + +/* Select whether to oscillate the High Speed On-Chip Oscillator (HOCO). + 0 = Stop Oscillating the HOCO. (default) + 1 = Enable Oscillating the HOCO. +*/ +#define BSP_CFG_HOCO_OSCILLATE_ENABLE DT_NODE_HAS_STATUS(DT_NODELABEL(hoco), okay) + +/* Select whether to oscillate the Low Speed On-Chip Oscillator (LOCO). + 0 = Stop Oscillating the LOCO. (default) + 1 = Enable Oscillating the LOCO. +*/ +#define BSP_CFG_LOCO_OSCILLATE_ENABLE DT_NODE_HAS_STATUS(DT_NODELABEL(loco), okay) + +/* Select whether to oscillate the IWDT-Dedicated On-Chip Oscillator (IWDT). + 0 = Stop Oscillating the IWDT Clock. (default) + 1 = Enable Oscillating the IWDT Clock. +*/ +#define BSP_CFG_IWDT_CLOCK_OSCILLATE_ENABLE DT_NODE_HAS_STATUS(DT_NODELABEL(iwdtlsclk), okay) + +/* Clock source select (CKSEL). + 0 = Low Speed On-Chip Oscillator (LOCO) + 1 = High Speed On-Chip Oscillator (HOCO) + 2 = Main Clock Oscillator + 3 = Sub-Clock Oscillator + 4 = PLL Circuit +*/ +#define BSP_CFG_CLOCK_SOURCE RX_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(pclkblock))) + +/* LPT (Low Power Timer) Clock source select (LPTCR1.LPCNTCKSEL) + 0 = Sub-clock + 1 = IWDT + 2 = LPT non use +*/ +#define BSP_CFG_LPT_CLOCK_SOURCE RX_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(lptclk), mosel, 2) + +/* Main clock Oscillator Switching (MOSEL). + 0 = Resonator + 1 = External clock input +*/ +#define BSP_CFG_MAIN_CLOCK_SOURCE RX_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(xtal), mosel, 0) + +/* Configure clock source of clock output(CLKOUT) pin (CKOSEL). + Available clock sources: + 0 = LOCO + 1 = HOCO + 2 = Main clock oscillator (default) + 3 = Sub-clock oscillator + 4 = PLL circuit + */ +#define BSP_CFG_CLKOUT_SOURCE RX_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(clkout))) + +/* The sub-clock oscillation control for using the RTC. + When '1' is selected, the registers related to RTC are initialized and the sub-clock oscillator is operated. + 0 = The RTC is not to be used. + 1 = The RTC is to be used. +*/ +#define BSP_CFG_RTC_ENABLE DT_NODE_HAS_STATUS(DT_NODELABEL(rtcsclk), okay) + +/* Sub-Clock Oscillator Drive Capacity Control (RTCDV). + 0 = Drive capacity for standard CL. (default) + 1 = Drive capacity for low CL. +*/ +#define BSP_CFG_SOSC_DRV_CAP RX_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(subclk), drive_capacity, 0) + +/* Clock configuration options. + The input clock frequency is specified and then the system clocks are set by specifying the multipliers used. The + multiplier settings are used to set the clock registers in resetprg.c. If a 8MHz clock is used and the + ICLK is 32MHz, PCLKB is 32MHz, FCLK is 32MHz, PCLKD is 32MHz then the + settings would be: + + BSP_CFG_XTAL_HZ = 8000000 + BSP_CFG_PLL_DIV = 2 (divide by 2) + BSP_CFG_PLL_MUL = 8 (4MHz x 8 = 32MHz) + BSP_CFG_ICK_DIV = 1 : System Clock (ICLK) = + (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_ICK_DIV) = 32MHz + BSP_CFG_PCKB_DIV = 1 : Peripheral Clock B (PCLKB) = + (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_PCKB_DIV) = 32MHz + BSP_CFG_PCKD_DIV = 1 : Peripheral Clock D (PCLKD) = + (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_PCKD_DIV) = 32MHz + BSP_CFG_FCK_DIV = 1 : Flash IF Clock (FCLK) = + (((BSP_CFG_XTAL_HZ/BSP_CFG_PLL_DIV) * BSP_CFG_PLL_MUL) / BSP_CFG_FCK_DIV) = 32MHz +*/ +/* Input clock frequency in Hz (XTAL or EXTAL). */ +#define BSP_CFG_XTAL_HZ RX_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(xtal), clock_frequency, 0) + +/* PLL Input Frequency Divider Select (PLIDIV). + Available divisors = /1 (no division), /2, /4 +*/ +#define BSP_CFG_PLL_DIV RX_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll), div, 2) + +/* PLL Frequency Multiplication Factor Select (STC). + Available multipliers = x4, x4.5, x5, x5.5, x6, x6.5, x7, x7.5, x8 +*/ + +#define BSP_CFG_PLL_MUL ((DT_PROP_BY_IDX(DT_NODELABEL(pll), mul, 0)) + \ + ((DT_PROP_BY_IDX(DT_NODELABEL(pll), mul, 1)) / (10.0))) + +/* System Clock Divider (ICK). + Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64 +*/ +#define BSP_CFG_ICK_DIV RX_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(iclk), div, 1) + +/* Peripheral Module Clock B Divider (PCKB). + Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64 +*/ +#define BSP_CFG_PCKB_DIV RX_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pclkb), div, 1) + +/* Peripheral Module Clock D Divider (PCKD). + Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64 +*/ +#define BSP_CFG_PCKD_DIV RX_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pclkd), div, 1) + +/* Flash IF Clock Divider (FCK). + Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64 +*/ +#define BSP_CFG_FCK_DIV RX_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(fclk), div, 1) + +/* CLKOUT Output Frequency Division Ratio Select. (CKODIV) + Values + 0 = x1/1 (default) + 1 = x1/2 + 2 = x1/4 + 3 = x1/8 + 4 = x1/16 + */ +#define BSP_CFG_CLKOUT_DIV RX_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(clkout), div, 1) + +/* Configure clock output(CLKOUT) pin (CKOSTP). + Values + 0 = CLKOUT pin output stopped. (Fixed to the low level) (default) + 1 = CLKOUT pin output enabled. + */ +#define BSP_CFG_CLKOUT_OUTPUT DT_NODE_HAS_STATUS(DT_NODELABEL(clkout), okay) + +/* Main Clock Oscillator Wait Time (MOSCWTCR). + Set these bits to select the oscillation stabilization wait time of the main clock oscillator. + Set the main clock oscillation stabilization time to longer than or equal to the stabilization + time recommended by the oscillator manufacturer. When the main clock is externally input, + set these bits to 00000b because the oscillation stabilization time is not required. + + 00000b: Wait time = 2 cycles (0.5 us) + 00001b: Wait time = 1024 cycles (256 us) + 00010b: Wait time = 2048 cycles (512 us) + 00011b: Wait time = 4096 cycles (1.024 ms) + 00100b: Wait time = 8192 cycles (2.048 ms) + 00101b: Wait time = 16384 cycles (4.096 ms) + 00110b: Wait time = 32768 cycles (8.192 ms) + 00111b: Wait time = 65536 cycles (16.384 ms) + Settings other than above are prohibited. + Wait time when LOCO = 4.0 MHz (0.25 us, TYP.) +*/ +#define BSP_CFG_MOSC_WAIT_TIME RX_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(xtal), stabilization_time, 4) + +/* Select whether to initialize the HOCO trimming register. + 0 = Disable reset the HOCO trimming register in the initial setting process. + 1 = Enable reset the HOCO trimming register in the initial setting process. + Note: The trimming value is adjusted at shipment on the specified conditions and the value after a reset varies + with the chips. When re-writing the HOCO trimming register, enable this macro definition. +*/ +#define BSP_CFG_HOCO_TRIMMING_ENABLE (0) + +/* Set the frequency trimming value for the HOCO. + 0(Frequency: Low) - 63(Frequency: High) + Note: The trimming value is adjusted at shipment on the specified conditions and the value after a reset varies + with the chips. When re-writing the HOCO trimming register, set this macro definition. +*/ +#define BSP_CFG_HOCO_TRIMMING_REG_VALUE (0) + +/* Sub-Clock Oscillator Wait Time (Use R_BSP_SoftwareDelay). + Setting delay unit is in milliseconds. +*/ +#define BSP_CFG_SOSC_WAIT_TIME (1482) + +/* Configure IWDT settings. + OFS0 - Option Function Select Register 0 + b31:b15 Reserved (set to 1) + b14 IWDTSLCSTP - IWDT Sleep Mode Count Stop Control - (0=can't stop count, 1=stop w/some low power modes) + b13 Reserved (set to 1) + b12 IWDTRSTIRQS - IWDT Reset Interrupt Request - What to do on underflow (0=take interrupt, 1=reset MCU) + b11:b10 IWDTRPSS - IWDT Window Start Position Select - (0=25%, 1=50%, 2=75%, 3=100%,don't use) + b9:b8 IWDTRPES - IWDT Window End Position Select - (0=75%, 1=50%, 2=25%, 3=0%,don't use) + b7:b4 IWDTCKS - IWDT Clock Frequency Division Ratio - (0=none, 2=/16, 3 = /32, 4=/64, 0xF=/128, 5=/256) + b3:b2 IWDTTOPS - IWDT Timeout Period Select - (0=128 cycles, 1=512, 2=1024, 3=2048) + b1 IWDTSTRT - IWDT Start Mode Select - (0=auto-start after reset, 1=halt after reset) + b0 Reserved (set to 1) + NOTE: When the IWDT-dedicated on-chip oscillator is used as the clock source for the low-power timer, + set the OFS0.IWDTSLCSTP + bit to 0 (counting stop is disabled) in IWDT auto-start mode operation. + Default value is 0xFFFFFFFF. +*/ +#define BSP_CFG_OFS0_REG_VALUE (0xFFFFFFFF) /* Generated value. Do not edit this manually */ + +/* Configure whether voltage detection 1 circuit and HOCO are enabled after reset. + OFS1 - Option Function Select Register 1 + b31:b9 Reserved (set to 1) + b8 HOCOEN - Enable/disable HOCO oscillation after a reset (0=enable, 1=disable) + b7:b4 Reserved (set to 1) + b3 FASTSTUP - Power-On Fast Startup Time (0=fast startup, 1=normal) + b2 LVDAS - Voltage Detection 0 Circuit Start (0=enable, 1=disable) + b1:b0 VDSEL - Voltage Detection 0 Level Select + 0 0: 3.84 V + 0 1: 2.82 V + 1 0: 2.51 V + 1 1: 1.90 V + Default value is 0xFFFFFFFF. +*/ +#define BSP_CFG_OFS1_REG_VALUE (0xFFFFFFFF) /* Generated value. Do not edit this manually */ + +/* This macro lets other modules no if a RTOS is being used. + 0 = RTOS is not used. + 1 = FreeRTOS is used. + 2 = embOS is used.(This is not available.) + 3 = MicroC_OS is used.(This is not available.) + 4 = Renesas ITRON OS (RI600V4 or RI600PX) is used. + 5 = Azure RTOS is used. +*/ +#define BSP_CFG_RTOS_USED (0) + +/* This macro is used to select which Renesas ITRON OS. + 0 = RI600V4 is used. + 1 = RI600PX is used. +*/ +#define BSP_CFG_RENESAS_RTOS_USED (0) + +/* This macro is used to select which CMT channel used for system timer of RTOS. + * The setting of this macro is only valid if the macro BSP_CFG_RTOS_USED is set to a value other than 0. */ +#if BSP_CFG_RTOS_USED != 0 +/* Setting value. + * 0 = CMT channel 0 used for system timer of RTOS (recommended to be used for RTOS). + * 1 = CMT channel 1 used for system timer of RTOS. + * 2 = CMT channel 2 used for system timer of RTOS. + * 3 = CMT channel 3 used for system timer of RTOS. + * Others = Invalid. + * NOTE: This is invalid when using Renesas RTOS with CCRX. + */ +#define BSP_CFG_RTOS_SYSTEM_TIMER (0) +#endif + +/* By default modules will use global locks found in mcu_locks.c. If the user is using a RTOS and would rather use its + locking mechanisms then they can change this macro. + NOTE: If '1' is chosen for this macro then the user must also change the next macro 'BSP_CFG_USER_LOCKING_TYPE'. + 0 = Use default locking (non-RTOS) + 1 = Use user defined locking mechanism. +*/ +#define BSP_CFG_USER_LOCKING_ENABLED (0) + +/* If the user decides to use their own locking mechanism with FIT modules then they will need to redefine the typedef + that is used for the locks. If the user is using a RTOS then they would likely redefine the typedef to be + a semaphore/mutex type of their RTOS. Use the macro below to set the type that will be used for the locks. + NOTE: If BSP_CFG_USER_LOCKING_ENABLED == 0 then this typedef is ignored. + NOTE: Do not surround the type with parentheses '(' ')'. +*/ +#define BSP_CFG_USER_LOCKING_TYPE bsp_lock_t + +/* If the user decides to use their own locking mechanism with FIT modules then they will need to define the functions + that will handle the locking and unlocking. These functions should be defined below. + If BSP_CFG_USER_LOCKING_ENABLED is != 0: + R_BSP_HardwareLock(mcu_lock_t hw_index) will call BSP_CFG_USER_LOCKING_HW_LOCK_FUNCTION(mcu_lock_t hw_index) + R_BSP_HardwareUnlock(mcu_lock_t hw_index) will call BSP_CFG_USER_LOCKING_HW_UNLOCK_FUNCTION(mcu_lock_t hw_index) + NOTE:With these functions the index into the array holding the global hardware locks is passed as the parameter. + R_BSP_SoftwareLock(BSP_CFG_USER_LOCKING_TYPE * plock) will call + BSP_CFG_USER_LOCKING_SW_LOCK_FUNCTION(BSP_CFG_USER_LOCKING_TYPE * plock) + R_BSP_SoftwareUnlock(BSP_CFG_USER_LOCKING_TYPE * plock) will call + BSP_CFG_USER_LOCKING_SW_UNLOCK_FUNCTION(BSP_CFG_USER_LOCKING_TYPE * plock) + NOTE:With these functions the actual address of the lock to use is passed as the parameter. + NOTE: These functions must return a boolean. If lock was obtained or released successfully then return true. Else, + return false. + NOTE: If BSP_CFG_USER_LOCKING_ENABLED == 0 then this typedef is ignored. + NOTE: Do not surround the type with parentheses '(' ')'. +*/ +#define BSP_CFG_USER_LOCKING_HW_LOCK_FUNCTION my_hw_locking_function +#define BSP_CFG_USER_LOCKING_HW_UNLOCK_FUNCTION my_hw_unlocking_function +#define BSP_CFG_USER_LOCKING_SW_LOCK_FUNCTION my_sw_locking_function +#define BSP_CFG_USER_LOCKING_SW_UNLOCK_FUNCTION my_sw_unlocking_function + +/* If the user would like to determine if a warm start reset has occurred, then they may enable one or more of the + following callback definitions AND provide a call back function name for the respective callback + function (to be defined by the user). Setting BSP_CFG_USER_WARM_START_CALLBACK_PRE_INITC_ENABLED = 1 will result + in a callback to the user defined my_sw_warmstart_prec_function just prior to the initialization of the C + runtime environment by resetprg. + Setting BSP_CFG_USER_WARM_START_CALLBACK_POST_INITC_ENABLED = 1 will result in a callback to the user defined + my_sw_warmstart_postc_function just after the initialization of the C runtime environment by resetprg. +*/ +#define BSP_CFG_USER_WARM_START_CALLBACK_PRE_INITC_ENABLED (0) +#define BSP_CFG_USER_WARM_START_PRE_C_FUNCTION my_sw_warmstart_prec_function + +#define BSP_CFG_USER_WARM_START_CALLBACK_POST_INITC_ENABLED (0) +#define BSP_CFG_USER_WARM_START_POST_C_FUNCTION my_sw_warmstart_postc_function + +/* By default FIT modules will check input parameters to be valid. This is helpful during development but some users + will want to disable this for production code. The reason for this would be to save execution time and code space. + This macro is a global setting for enabling or disabling parameter checking. Each FIT module will also have its + own local macro for this same purpose. By default the local macros will take the global value from here though + they can be overridden. Therefore, the local setting has priority over this global setting. Disabling parameter + checking should only used when inputs are known to be good and the increase in speed or decrease in code space is + needed. + 0 = Global setting for parameter checking is disabled. + 1 = Global setting for parameter checking is enabled (Default). +*/ +#define BSP_CFG_PARAM_CHECKING_ENABLE (1) + +/* This macro is used to define the voltage that is supplied to the MCU (Vcc). This macro is defined in millivolts. This + macro does not actually change anything on the MCU. Some FIT modules need this information so it is defined here. */ +#define BSP_CFG_MCU_VCC_MV (3300) /* Generated value. Do not edit this manually */ + +/* Allow initialization of auto-generated peripheral initialization code by Smart Configurator tool. + When not using the Smart Configurator, set the value of BSP_CFG_CONFIGURATOR_SELECT to 0. + 0 = Disabled (default) + 1 = Smart Configurator initialization code used +*/ +#define BSP_CFG_CONFIGURATOR_SELECT (1) /* Generated value. Do not edit this manually */ + +/* Version number of Smart Configurator. + This macro definition is updated by Smart Configurator. +*/ +#define BSP_CFG_CONFIGURATOR_VERSION (2210) /* Generated value. Do not edit this manually */ + +/* For some BSP functions, it is necessary to ensure that, while these functions are executing, interrupts from other + FIT modules do not occur. By controlling the IPL, these functions disable interrupts that are at or below the + specified interrupt priority level. + This macro sets the IPL. Range is 0x0 - 0xF. + Please set this macro more than IPR for other FIT module interrupts. + The default value is 0xF (maximum value). + Don't change if there is no special processing with higher priority than all fit modules. +*/ +#define BSP_CFG_FIT_IPL_MAX (0xF) + +/* Software Interrupt (SWINT). + 0 = Software interrupt is not used. + 1 = Software interrupt is used. + NOTE: When this macro is set to 1, the software interrupt is initialized in bsp startup routine. +*/ +#define BSP_CFG_SWINT_UNIT1_ENABLE (0) + +/* Software Interrupt Task Buffer Number. + For software interrupt, this value is number of buffering user tasks. + So user can increase this value if user system would have many software interrupt tasks + and user system has enough buffer. This value requires 9 byte per task. + NOTE: This setting is common to all units. It can not be set individually. + The maximum value is 254. +*/ +#define BSP_CFG_SWINT_TASK_BUFFER_NUMBER (8) + +/* Initial value of the software interrupt priority. + For software interrupt, this value is interrupt priority. Range is 0x0 - 0xF. + NOTE: This setting is common to all units. It can not be set individually. + Please be careful that this setting is the initial value of the interrupt priority register(IPR). + It is possible to dynamically change the IPR. +*/ +#define BSP_CFG_SWINT_IPR_INITIAL_VALUE (0x1) + +/* This macro is used for serial terminal on the board selected by smart configurator. + 0 = SCI UART Terminal is disabled. + 1 = SCI UART Terminal is enabled. +*/ +#define BSP_CFG_SCI_UART_TERMINAL_ENABLE (0) + +/* This macro is channel number for serial terminal. +*/ +#define BSP_CFG_SCI_UART_TERMINAL_CHANNEL (1) + +/* This macro is bit-rate for serial terminal. +*/ +#define BSP_CFG_SCI_UART_TERMINAL_BITRATE (115200) + +/* This macro is interrupt priority for serial terminal. + 0(low) - 15(high) +*/ +#define BSP_CFG_SCI_UART_TERMINAL_INTERRUPT_PRIORITY (15) + +/* This macro is used for C++ project and updated by Smart Configurator. + 0 = This project is a C project.(Not a C++ project). + 1 = This project is a C++ project. +*/ +#define BSP_CFG_CPLUSPLUS (0) /* Generated value. Do not edit this manually */ + +/* Select whether to enable bus priority initialization. + 0 = Bus priority initialization is disabled. + 1 = Bus priority initialization is enabled. +*/ +#define BSP_CFG_BUS_PRIORITY_INITIALIZE_ENABLE (0) + +/* Select the priority order for memory bus 1 (RAM). + 0 = The order of priority is fixed. + 1 = The order of priority is toggled. +*/ +#define BSP_CFG_MEMORY_BUS1_PRIORITY (0) + +/* Select the priority order for memory bus 2 (ROM). + 0 = The order of priority is fixed. + 1 = The order of priority is toggled. +*/ +#define BSP_CFG_MEMORY_BUS2_PRIORITY (0) + +/* Select the priority order for internal peripheral bus 1. + 0 = The order of priority is fixed. + 1 = The order of priority is toggled. +*/ +#define BSP_CFG_INTERNAL_PERIPHERAL_BUS1_PRIORITY (0) + +/* Select the priority order for internal peripheral buses 2 and 3. + 0 = The order of priority is fixed. + 1 = The order of priority is toggled. +*/ +#define BSP_CFG_INTERNAL_PERIPHERAL_BUS2_3_PRIORITY (0) + +/* Select the priority order for internal peripheral bus 6. + 0 = The order of priority is fixed. + 1 = The order of priority is toggled. +*/ +#define BSP_CFG_INTERNAL_PERIPHERAL_BUS6_PRIORITY (0) + +/* Select whether it is bootloader project. + 0 = This project isn't a bootloader project. + 1 = This project is a bootloader project. + NOTE: Not normally used. Set this to "1" only in the bootloader project. +*/ +#define BSP_CFG_BOOTLOADER_PROJECT (0) + +#endif /* R_BSP_CONFIG_REF_HEADER_FILE */ + From 378e3b5eba4b072d77c61d8a5ceaa2665fc1e1d6 Mon Sep 17 00:00:00 2001 From: Phi Tran Date: Tue, 10 Sep 2024 17:58:03 +0700 Subject: [PATCH 2/9] drivers: gpio: Initial support gpio driver on RSK_RX130_512KB Initial commit for GPIO driver support on board using RX130 MCUs Signed-off-by: Phi Tran --- drivers/rx/CMakeLists.txt | 14 +- .../rdp/src/r_bsp/board/generic_rx130/r_bsp.h | 3 + drivers/rx/rdp/src/r_bsp/mcu/all/r_bsp_cpu.c | 794 +++++++++++++ .../r_bsp/mcu/all/r_bsp_software_interrupt.c | 1054 +++++++++++++++++ .../r_bsp/mcu/all/r_bsp_software_interrupt.h | 138 +++ .../rx/rdp/src/r_bsp/mcu/rx130/mcu_locks.h | 152 +++ .../rx/rdp/src/r_bsp/mcu/rx130/r_bsp_cpu.h | 98 ++ drivers/rx/rdp/src/r_gpio_rx/r_gpio_rx_if.h | 297 +++++ drivers/rx/rdp/src/r_gpio_rx/src/r_gpio_rx.c | 579 +++++++++ .../src/targets/rx130/r_gpio_rx130.c | 280 +++++ .../src/targets/rx130/r_gpio_rx130.h | 499 ++++++++ zephyr/rx/rdp_cfg/r_config/r_gpio_rx_config.h | 47 + 12 files changed, 3954 insertions(+), 1 deletion(-) create mode 100644 drivers/rx/rdp/src/r_bsp/mcu/all/r_bsp_cpu.c create mode 100644 drivers/rx/rdp/src/r_bsp/mcu/all/r_bsp_software_interrupt.c create mode 100644 drivers/rx/rdp/src/r_bsp/mcu/all/r_bsp_software_interrupt.h create mode 100644 drivers/rx/rdp/src/r_bsp/mcu/rx130/mcu_locks.h create mode 100644 drivers/rx/rdp/src/r_bsp/mcu/rx130/r_bsp_cpu.h create mode 100644 drivers/rx/rdp/src/r_gpio_rx/r_gpio_rx_if.h create mode 100644 drivers/rx/rdp/src/r_gpio_rx/src/r_gpio_rx.c create mode 100644 drivers/rx/rdp/src/r_gpio_rx/src/targets/rx130/r_gpio_rx130.c create mode 100644 drivers/rx/rdp/src/r_gpio_rx/src/targets/rx130/r_gpio_rx130.h create mode 100644 zephyr/rx/rdp_cfg/r_config/r_gpio_rx_config.h diff --git a/drivers/rx/CMakeLists.txt b/drivers/rx/CMakeLists.txt index 3e9b6e4e..cd7221cb 100644 --- a/drivers/rx/CMakeLists.txt +++ b/drivers/rx/CMakeLists.txt @@ -2,8 +2,8 @@ set(include_dirs rdp_cfg - rdp_cfg/r_config rdp/src/r_bsp + rdp_cfg/r_config rdp/src/r_bsp/mcu rdp/src/r_bsp/mcu/all rdp/src/r_bsp/mcu/${CONFIG_SOC_SERIES} @@ -12,11 +12,23 @@ set(include_dirs set(srcs rdp/src/r_bsp/mcu/all/r_bsp_common.c + rdp/src/r_bsp/mcu/all/r_bsp_cpu.c + rdp/src/r_bsp/mcu/all/r_bsp_interrupts.c + rdp/src/r_bsp/mcu/all/r_bsp_software_interrupt.c + rdp/src/r_bsp/mcu/all/r_rx_intrinsic_functions.c rdp/src/r_bsp/mcu/${CONFIG_SOC_SERIES}/mcu_clocks.c rdp/src/r_bsp/mcu/${CONFIG_SOC_SERIES}/mcu_init.c + rdp/src/r_bsp/mcu/${CONFIG_SOC_SERIES}/mcu_interrupts.c ) zephyr_include_directories(${include_dirs}) zephyr_library_sources(${srcs}) # Optional build base on feature configuration +if(CONFIG_USE_RX_RDP_GPIO) + zephyr_library_sources( + rdp/src/r_gpio_rx/src/r_gpio_rx.c + rdp/src/r_gpio_rx/src/targets/${CONFIG_SOC_SERIES}/r_gpio_${CONFIG_SOC_SERIES}.c + ) + zephyr_include_directories(rdp/src/r_gpio_rx) +endif() diff --git a/drivers/rx/rdp/src/r_bsp/board/generic_rx130/r_bsp.h b/drivers/rx/rdp/src/r_bsp/board/generic_rx130/r_bsp.h index 37f5004d..41a5ad9f 100644 --- a/drivers/rx/rdp/src/r_bsp/board/generic_rx130/r_bsp.h +++ b/drivers/rx/rdp/src/r_bsp/board/generic_rx130/r_bsp.h @@ -68,13 +68,16 @@ INCLUDE APPROPRIATE MCU AND BOARD FILES #elif defined(__ICCRX__) #include "register_access/iccrx/iodefine.h" #endif /* defined(__CCRX__), defined(__GNUC__), defined(__ICCRX__) */ +#include "r_bsp_cpu.h" #include "mcu_clocks.h" #include "mcu_info.h" #include "mcu_init.h" #include "mcu_interrupts.h" +#include "mcu_locks.h" #include "vecttbl.h" #include "r_bsp_interrupts.h" +#include "r_bsp_software_interrupt.h" #include "r_rx_intrinsic_functions.h" diff --git a/drivers/rx/rdp/src/r_bsp/mcu/all/r_bsp_cpu.c b/drivers/rx/rdp/src/r_bsp/mcu/all/r_bsp_cpu.c new file mode 100644 index 00000000..d916b93f --- /dev/null +++ b/drivers/rx/rdp/src/r_bsp/mcu/all/r_bsp_cpu.c @@ -0,0 +1,794 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013 - 2024 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_bsp_cpu.c +* Description : This module implements CPU specific functions. An example is enabling/disabling interrupts. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 28.02.2019 3.00 Merged processing of all devices. +* Added support for GNUC and ICCRX. +* Fixed coding style. +* : 26.07.2019 3.10 Added the API function(R_BSP_SoftwareReset). +* Modified comment of API function to Doxygen style. +* Added the vbatt_voltage_stability_wait function. +* Modified the following functions. +* - R_BSP_RegisterProtectEnable +* - R_BSP_RegisterProtectDisable +* : 31.07.2019 3.11 Deleted the compile condition for R_BSP_SoftwareReset. +* : 08.10.2019 3.12 Changed the following functions. +* - R_BSP_InterruptsDisable +* - R_BSP_InterruptsEnable +* - R_BSP_CpuInterruptLevelWrite +* : 10.12.2019 3.13 Modified the following functions. +* - R_BSP_RegisterProtectEnable +* - R_BSP_RegisterProtectDisable +* : 22.04.2022 3.14 Modified the following functions. +* - R_BSP_VoltageLevelSetting +* : 28.02.2023 3.15 Modified comment. +* : 21.11.2023 3.16 Added the following macro definitions. +* - BSP_PRV_BUSPRI_BPRA_TOGGLE +* - BSP_PRV_BUSPRI_BPRO_TOGGLE +* - BSP_PRV_BUSPRI_BPIB_TOGGLE +* - BSP_PRV_BUSPRI_BPGB_TOGGLE +* - BSP_PRV_BUSPRI_BPHB_TOGGLE +* - BSP_PRV_BUSPRI_BPFB_TOGGLE +* - BSP_PRV_BUSPRI_BPEB_TOGGLE +* - BSP_PRV_BUSPRI_BPXB_TOGGLE +* Added bsp_bus_priority_initialize function. +**********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +/* Platform support. */ +#include "platform.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +#ifdef BSP_MCU_REGISTER_WRITE_PROTECTION +/* Key code for writing PRCR register. */ +#define BSP_PRV_PRCR_KEY (0xA500) +#endif + +#ifdef BSP_MCU_VOLTAGE_LEVEL_SETTING +#ifdef BSP_MCU_VOLTAGE_LEVEL_SETTING_USB +/* The macro definition for combinations where settings of USBVON bit conflict. */ +#define BSP_PRV_USBVON_CONFLICT (BSP_VOL_USB_POWEROFF | BSP_VOL_USB_POWERON) + +/* Bit number of VOLSR register. */ +#define BSP_PRV_VOLSR_USBVON_BIT_NUM (2) +#endif /* BSP_MCU_VOLTAGE_LEVEL_SETTING_USB */ + +#ifdef BSP_MCU_VOLTAGE_LEVEL_SETTING_AD +/* The macro definition for combinations where settings of PGAVLS bit conflict. */ +#define BSP_PRV_PGAVLS_CONFLICT (BSP_VOL_AD_NEGATIVE_VOLTAGE_INPUT | BSP_VOL_AD_NEGATIVE_VOLTAGE_NOINPUT) + +/* Bit number of VOLSR register. */ +#define BSP_PRV_VOLSR_PGAVLS_BIT_NUM (6) +#endif /* BSP_MCU_VOLTAGE_LEVEL_SETTING_AD */ + +#ifdef BSP_MCU_VOLTAGE_LEVEL_SETTING_RIIC +/* The macro definition for combinations where settings of RICVLS bit conflict. */ +#define BSP_PRV_RICVLS_CONFLICT (BSP_VOL_RIIC_4_5V_OROVER | BSP_VOL_RIIC_UNDER_4_5V) +/* Bit number of VOLSR register. */ +#define BSP_PRV_VOLSR_RICVLS_BIT_NUM (7) +#endif /* BSP_MCU_VOLTAGE_LEVEL_SETTING_RIIC */ +#endif /* BSP_MCU_VOLTAGE_LEVEL_SETTING */ + +#if BSP_CFG_BUS_PRIORITY_INITIALIZE_ENABLE == 1 +#define BSP_PRV_BUSPRI_BPRA_TOGGLE (0x0001) +#define BSP_PRV_BUSPRI_BPRO_TOGGLE (0x0004) +#define BSP_PRV_BUSPRI_BPIB_TOGGLE (0x0010) +#define BSP_PRV_BUSPRI_BPGB_TOGGLE (0x0040) +#define BSP_PRV_BUSPRI_BPHB_TOGGLE (0x0100) +#define BSP_PRV_BUSPRI_BPFB_TOGGLE (0x0400) +#define BSP_PRV_BUSPRI_BPEB_TOGGLE (0x1000) +#define BSP_PRV_BUSPRI_BPXB_TOGGLE (0x4000) +#endif /* BSP_CFG_BUS_PRIORITY_INITIALIZE_ENABLE == 1 */ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ +#ifdef BSP_MCU_REGISTER_WRITE_PROTECTION +/* Used for holding reference counters for protection bits. */ +static volatile uint16_t s_protect_counters[BSP_REG_PROTECT_TOTAL_ITEMS]; + +/* Masks for setting or clearing the PRCR register. Use -1 for size because PWPR in MPC is used differently. */ +static const uint16_t s_prcr_masks[BSP_REG_PROTECT_TOTAL_ITEMS-1] = +{ +#ifdef BSP_MCU_RCPC_PRC0 + 0x0001, /* PRC0. */ +#endif +#ifdef BSP_MCU_RCPC_PRC1 + 0x0002, /* PRC1. */ +#endif +#ifdef BSP_MCU_RCPC_PRC2 + 0x0004, /* PRC2. */ +#endif +#ifdef BSP_MCU_RCPC_PRC3 + 0x0008, /* PRC3. */ +#endif +}; +#endif + +/********************************************************************************************************************** + * Function Name: R_BSP_InterruptsDisable + ******************************************************************************************************************//** + * @brief Globally disables interrupts. + * @details This function globally disables interrupts. This is performed by clearing the 'I' bit in the CPU's + * Processor Status Word (PSW) register. + * @note The 'I' bit of the PSW can only be modified when in Supervisor Mode. If the CPU is in User Mode and this + * function is called, this function does nothing. + */ +void R_BSP_InterruptsDisable (void) +{ + uint32_t pmode; + + /* Read current processor mode. */ + pmode = (R_BSP_GET_PSW() & 0x00100000); + + /* Check current processor mode. */ + if (0 == pmode) + { + /* Use the compiler intrinsic function to clear the I flag. */ + R_BSP_CLRPSW_I(); + } + +} /* End of function R_BSP_InterruptsDisable() */ + +/********************************************************************************************************************** + * Function Name: R_BSP_InterruptsEnable + ******************************************************************************************************************//** + * @brief Globally enable interrupts. + * @details This function globally enables interrupts. This is performed by setting the 'I' bit in the CPU's Processor + * Status Word (PSW) register. + * @note The 'I' bit of the PSW can only be modified when in Supervisor Mode. If the CPU is in User Mode and this + * function is called, this function does nothing. + */ +void R_BSP_InterruptsEnable (void) +{ + uint32_t pmode; + + /* Read current processor mode. */ + pmode = (R_BSP_GET_PSW() & 0x00100000); + + /* Check current processor mode. */ + if (0 == pmode) + { + /* Use the compiler intrinsic function to set the I flag. */ + R_BSP_SETPSW_I(); + } + +} /* End of function R_BSP_InterruptsEnable() */ + +/********************************************************************************************************************** + * Function Name: R_BSP_CpuInterruptLevelRead + ******************************************************************************************************************//** + * @brief Reads the CPU's Interrupt Priority Level. + * @return The CPU's Interrupt Priority Level. + * @details This function reads the CPU's Interrupt Priority Level. This level is stored in the IPL bits of the + * Processor Status Word (PSW) register. + */ +uint32_t R_BSP_CpuInterruptLevelRead (void) +{ + /* Use the compiler intrinsic function to read the CPU IPL. */ + uint32_t psw_value; + + /* Casting is valid because it matches the type to the right side or argument. */ + psw_value = (uint32_t)R_BSP_GET_PSW(); + psw_value = psw_value & 0x0f000000; + psw_value = psw_value >> 24; + + return psw_value; +} /* End of function R_BSP_CpuInterruptLevelRead() */ + +/********************************************************************************************************************** + * Function Name: R_BSP_CpuInterruptLevelWrite + ******************************************************************************************************************//** + * @brief Writes the CPU's Interrupt Priority Level. + * @param[in] level The level to write to the CPU's IPL. + * @retval true Successful, CPU's IPL has been written. + * @retval false Failure, provided 'level' has invalid IPL value or called when the CPU is in User Mode. + * @details This function writes the CPU's Interrupt Priority Level. This level is stored in the IPL bits of the + * Processor Status Word (PSW) register. This function does check to make sure that the IPL being written is valid. + * The maximum and minimum valid settings for the CPU IPL are defined in mcu_info.h using the BSP_MCU_IPL_MAX and + * BSP_MCU_IPL_MIN macros. + * @note The CPU's IPL can only be modified by the user when in Supervisor Mode. If the CPU is in User Mode and this + * function is called, this function does not control IPL and return false. + */ +bool R_BSP_CpuInterruptLevelWrite (uint32_t level) +{ + bool ret; + uint32_t pmode; + + /* The R_BSP_SET_IPL() function use the MVTIPL instruction. + The MVTIPL instruction needs to set an immediate value to src. */ + + ret = false; + + /* Read current processor mode. */ + pmode = (R_BSP_GET_PSW() & 0x00100000); + + /* Check current processor mode. */ + if (0 == pmode) + { + ret = true; + + /* Use the compiler intrinsic function to set the CPU IPL. */ + switch (level) + { + case (0): + + /* IPL = 0 */ + R_BSP_SET_IPL(0); + break; + + case (1): + + /* IPL = 1 */ + R_BSP_SET_IPL(1); + break; + + case (2): + + /* IPL = 2 */ + R_BSP_SET_IPL(2); + break; + + case (3): + + /* IPL = 3 */ + R_BSP_SET_IPL(3); + break; + + case (4): + + /* IPL = 4 */ + R_BSP_SET_IPL(4); + break; + + case (5): + + /* IPL = 5 */ + R_BSP_SET_IPL(5); + break; + + case (6): + + /* IPL = 6 */ + R_BSP_SET_IPL(6); + break; + + case (7): + + /* IPL = 7 */ + R_BSP_SET_IPL(7); + break; + + #if 7 < BSP_MCU_IPL_MAX + case (8): + + /* IPL = 8 */ + R_BSP_SET_IPL(8); + break; + + case (9): + + /* IPL = 9 */ + R_BSP_SET_IPL(9); + break; + + case (10): + + /* IPL = 10 */ + R_BSP_SET_IPL(10); + break; + + case (11): + + /* IPL = 11 */ + R_BSP_SET_IPL(11); + break; + + case (12): + + /* IPL = 12 */ + R_BSP_SET_IPL(12); + break; + + case (13): + + /* IPL = 13 */ + R_BSP_SET_IPL(13); + break; + + case (14): + + /* IPL = 14 */ + R_BSP_SET_IPL(14); + break; + + case (15): + + /* IPL = 15 */ + R_BSP_SET_IPL(15); + break; + #endif /* BSP_MCU_IPL_MAX */ + + default: + ret = false; + break; + } + } + + return ret; +} /* End of function R_BSP_CpuInterruptLevelWrite() */ + +/********************************************************************************************************************** + * Function Name: R_BSP_RegisterProtectEnable + ******************************************************************************************************************//** + * @brief Enables write protection for selected registers. + * @param[in] regs_to_protect Which registers to enable write protection for. + * @details This function enables write protection for the input registers. Only certain MCU registers have the + * ability to be write protected. To see which registers are available to be protected by this function look at the + * bsp_reg_protect_t enum in r_bsp_cpu.h for your MCU. + * This function, and R_BSP_RegisterProtectDisable(), use counters for each entry in the bsp_reg_protect_t enum so + * that users can call these functions multiple times without problem. This function uses the interrupt disable / + * enable function by controlling the Processor Interrupt Priority Level (IPL) of the R_BSP_InterruptControl function, + * because counter control is the critical section. If the function is executed while the processor mode is supervisor + * mode, interrupts that are at or below the specified interrupt priority level will be disabled by controlling the + * IPL. If the function is executed while the processor mode is user mode, the IPL controlling does not execute. An + * example of why this is needed is shown below in the Special Notes section below. + * @note + * (1) About why counters are needed. \n + * See Section 5.7 in the application note for details.\n + * (2) Notes on user mode \n + * The R_BSP_InterruptControl function used to secure atomicity in the critical section of the counter control with + * this function is valid only in supervisor mode. When this function is executed in user mode, the + * R_BSP_InterruptControl function is executed but atomicity is not to secure. + */ +void R_BSP_RegisterProtectEnable (bsp_reg_protect_t regs_to_protect) +{ +#ifdef BSP_MCU_REGISTER_WRITE_PROTECTION + bsp_int_ctrl_t int_ctrl; + + /* Set IPL to the maximum value to disable all interrupts, + * so the scheduler can not be scheduled in critical region. + * Note: Please set this macro more than IPR for other FIT module interrupts. */ + R_BSP_InterruptControl(BSP_INT_SRC_EMPTY, BSP_INT_CMD_FIT_INTERRUPT_DISABLE, &int_ctrl); + + /* Is it safe to disable write access? */ + if (0 != s_protect_counters[regs_to_protect]) + { + /* Decrement the protect counter */ + s_protect_counters[regs_to_protect]--; + } + + /* Is it safe to disable write access? */ + if (0 == s_protect_counters[regs_to_protect]) + { + if (BSP_REG_PROTECT_MPC != regs_to_protect) + { + /* Enable protection using PRCR register. */ + /* When writing to the PRCR register the upper 8-bits must be the correct key. Set lower bits to 0 to + disable writes. + b15:b8 PRKEY - Write 0xA5 to upper byte to enable writing to lower byte + b7:b4 Reserved (set to 0) + b3 PRC3 - Please check the user's manual. + b2 PRC2 - Please check the user's manual. + b1 PRC1 - Please check the user's manual. + b0 PRC0 - Please check the user's manual. + */ + SYSTEM.PRCR.WORD = (uint16_t)((SYSTEM.PRCR.WORD | BSP_PRV_PRCR_KEY) & (~s_prcr_masks[regs_to_protect])); + } + else + { + /* Enable protection for MPC using PWPR register. */ + /* Enable writing of PFSWE bit. It could be assumed that the B0WI bit is still cleared from a call to + protection disable function, but it is written here to make sure that the PFSWE bit always gets + cleared. */ + MPC.PWPR.BIT.B0WI = 0; + + /* Disable writing to PFS registers. */ + MPC.PWPR.BIT.PFSWE = 0; + + /* Disable writing of PFSWE bit. */ + MPC.PWPR.BIT.B0WI = 1; + } + } + + /* Restore the IPL. */ + R_BSP_InterruptControl(BSP_INT_SRC_EMPTY, BSP_INT_CMD_FIT_INTERRUPT_ENABLE, &int_ctrl); + +#else /* BSP_MCU_REGISTER_WRITE_PROTECTION */ + /* No registers to protect. */ + /* This code is only used to remove compiler info messages about this parameter not being used. */ + INTERNAL_NOT_USED(regs_to_protect); +#endif /* BSP_MCU_REGISTER_WRITE_PROTECTION */ +} /* End of function R_BSP_RegisterProtectEnable() */ + +/********************************************************************************************************************** + * Function Name: R_BSP_RegisterProtectDisable + ******************************************************************************************************************//** + * @brief Disables write protection for selected registers. + * @param[in] regs_to_unprotect Which registers to disable write protection for. + * @details This function disables write protection for the input registers. Only certain MCU registers have the + * ability to be write protected. To see which registers are available to be protected by this function look at the + * bsp_reg_protect_t enum in r_bsp_cpu.h for your MCU. + * This function, and R_BSP_RegisterProtectEnable(), use counters for each entry in the bsp_reg_protect_t enum so that + * users can call these functions multiple times without problem. This function uses the interrupt disable / + * enable function by controlling the Processor Interrupt Priority Level (IPL) of the R_BSP_InterruptControl function, + * because counter control is the critical section. If the function is executed while the processor mode is supervisor + * mode, interrupts that are at or below the specified interrupt priority level will be disabled by controlling the + * IPL. If the function is executed while the processor mode is user mode, the IPL controlling does not execute. + * @note The R_BSP_InterruptControl function used to secure atomicity in the critical section of the counter control + * with this function is valid only in supervisor mode. When this function is executed in user mode, the + * R_BSP_InterruptControl function is executed but atomicity is not to secure. + */ +void R_BSP_RegisterProtectDisable (bsp_reg_protect_t regs_to_unprotect) +{ +#ifdef BSP_MCU_REGISTER_WRITE_PROTECTION + bsp_int_ctrl_t int_ctrl; + + /* Set IPL to the maximum value to disable all interrupts, + * so the scheduler can not be scheduled in critical region. + * Note: Please set this macro more than IPR for other FIT module interrupts. */ + R_BSP_InterruptControl(BSP_INT_SRC_EMPTY, BSP_INT_CMD_FIT_INTERRUPT_DISABLE, &int_ctrl); + + /* If this is first entry then disable protection. */ + if (0 == s_protect_counters[regs_to_unprotect]) + { + if (BSP_REG_PROTECT_MPC != regs_to_unprotect) + { + /* Enable protection using PRCR register. */ + /* When writing to the PRCR register the upper 8-bits must be the correct key. + Set lower bits to 1 to enable writes. + b15:b8 PRKEY - Write 0xA5 to upper byte to enable writing to lower byte + b7:b4 Reserved (set to 0) + b3 PRC3 - Please check the user's manual. + b2 PRC2 - Please check the user's manual. + b1 PRC1 - Please check the user's manual. + b0 PRC0 - Please check the user's manual. + */ + SYSTEM.PRCR.WORD = (uint16_t)((SYSTEM.PRCR.WORD | BSP_PRV_PRCR_KEY) | s_prcr_masks[regs_to_unprotect]); + } + else + { + /* Disable protection for MPC using PWPR register. */ + /* Enable writing of PFSWE bit. */ + MPC.PWPR.BIT.B0WI = 0; + + /* Enable writing to PFS registers. */ + MPC.PWPR.BIT.PFSWE = 1; + } + } + + /* Increment the protect counter */ + s_protect_counters[regs_to_unprotect]++; + + /* Restore the IPL. */ + R_BSP_InterruptControl(BSP_INT_SRC_EMPTY, BSP_INT_CMD_FIT_INTERRUPT_ENABLE, &int_ctrl); + +#else /* BSP_MCU_REGISTER_WRITE_PROTECTION */ + /* No registers to protect. */ + /* This code is only used to remove compiler info messages about this parameter not being used. */ + INTERNAL_NOT_USED(regs_to_unprotect); +#endif /* BSP_MCU_REGISTER_WRITE_PROTECTION */ +} /* End of function R_BSP_RegisterProtectDisable() */ + +#ifdef BSP_MCU_VOLTAGE_LEVEL_SETTING +/********************************************************************************************************************** + * Function Name: R_BSP_VoltageLevelSetting + ******************************************************************************************************************//** + * @brief This API function is used excessively with the RX26T, RX660, RX66T and RX72T. It makes settings to the + * voltage level setting register (VOLSR) that are necessary in order to use the USB, AD, and RIIC peripheral modules. + * Call this function only when it is necessary to change the register settings. + * @param[in] ctrl_ptn Register Setting Patterns + * The following setting patterns cannot be selected at the same time. + * When specifying more than one pattern at the same time, use the "|" (OR) operator. + * - BSP_VOL_USB_POWEROFF and BSP_VOL_USB_POWERON + * - BSP_VOL_AD_NEGATIVE_VOLTAGE_INPUT and BSP_VOL_AD_NEGATIVE_VOLTAGE_NOINPUT + * - BSP_VOL_RIIC_4_5V_OROVER and BSP_VOL_RIIC_UNDER_4_5V + * + * BSP_VOL_USB_POWEROFF: Updates the USBVON bit to 0. + * + * BSP_VOL_USB_POWERON: Updates the USBVON bit to 1. + * + * BSP_VOL_AD_NEGATIVE_VOLTAGE_INPUT: Updates the PGAVLS bit to 0. + * + * BSP_VOL_AD_NEGATIVE_VOLTAGE_NOINPUT: Updates the PGAVLS bit to 1. + * + * BSP_VOL_RIIC_4_5V_OROVER: Updates the RICVLS bit to 0. + * + * BSP_VOL_RIIC_UNDER_4_5V: Updates the RICVLS bit to 1. + * @retval true Processing completed, register successfully updated. + * @retval false The function was called under the following conditions, so the register setting was not updated. + * - Setting patterns that cannot be selected at the same time were selected. + * - A setting pattern related to the USB was selected when the USB was not in the module stop state. + * - A setting pattern related to the AD was selected when the AD was not in the module stop state. + * - A setting pattern related to the RIIC was selected when the RIIC was not in the module stop state. + * @details This function initializes the voltage level setting register (VOLSR), which is necessary in order to use + * the USB, AD and RIIC peripheral modules. When specifying a setting pattern related to the USB, call this function + * before the USB is released from the module stop state. When specifying a setting pattern related to the AD, call + * this function before the AD (unit 0 and unit 1) is released from the module stop state. When specifying a setting + * pattern related to the RIIC, call this function before the RIIC is released from the module stop state. If the + * function is called with a setting pattern related to the USB specified after the USB is released from the module + * stop state, the function returns "false" as the return value and does not update the register settings. If the + * function is called with a setting pattern related to the AD specified after the AD (unit 0 and unit 1) is released + * from the module stop state, the function returns "false" as the return value and does not update the register + * settings. Finally, if the function is called with a setting pattern related to the RIIC specified after the RIIC is + * released from the module stop state, the function returns "false" as the return value and does not update the + * register settings. + */ +bool R_BSP_VoltageLevelSetting (uint8_t ctrl_ptn) +{ + uint8_t *p_volsr_addr; + +#if BSP_CFG_PARAM_CHECKING_ENABLE == 1 + /* ---- CHECK ARGUMENTS ---- */ +#ifdef BSP_MCU_VOLTAGE_LEVEL_SETTING_USB + if (BSP_PRV_USBVON_CONFLICT == (ctrl_ptn & BSP_PRV_USBVON_CONFLICT)) + { + return false; + } +#endif /* BSP_MCU_VOLTAGE_LEVEL_SETTING_USB */ + +#ifdef BSP_MCU_VOLTAGE_LEVEL_SETTING_AD + if (BSP_PRV_PGAVLS_CONFLICT == (ctrl_ptn & BSP_PRV_PGAVLS_CONFLICT)) + { + return false; + } +#endif /* BSP_MCU_VOLTAGE_LEVEL_SETTING_AD */ + +#ifdef BSP_MCU_VOLTAGE_LEVEL_SETTING_RIIC + if (BSP_PRV_RICVLS_CONFLICT == (ctrl_ptn & BSP_PRV_RICVLS_CONFLICT)) + { + return false; + } +#endif /* BSP_MCU_VOLTAGE_LEVEL_SETTING_RIIC */ +#endif /* BSP_CFG_PARAM_CHECKING_ENABLE == 1 */ + +#ifdef BSP_MCU_VOLTAGE_LEVEL_SETTING_USB + /* Check USB module stop state. */ + if(0 != (ctrl_ptn & BSP_PRV_USBVON_CONFLICT)) + { + /* Casting is valid because it matches the type to the right side or argument. */ + if(0 == MSTP(USB0)) + { + return false; + } + } +#endif /* BSP_MCU_VOLTAGE_LEVEL_SETTING_USB */ + +#ifdef BSP_MCU_VOLTAGE_LEVEL_SETTING_AD + /* Check AD module stop state. */ + if(0 != (ctrl_ptn & BSP_PRV_PGAVLS_CONFLICT)) + { + /* Casting is valid because it matches the type to the right side or argument. */ + if((0 == MSTP(S12AD)) || (0 == MSTP(S12AD1))) + { + return false; + } + } +#endif /* BSP_MCU_VOLTAGE_LEVEL_SETTING_AD */ + +#ifdef BSP_MCU_VOLTAGE_LEVEL_SETTING_RIIC + /* Check RIIC module stop state. */ + if(0 != (ctrl_ptn & BSP_PRV_RICVLS_CONFLICT)) + { + /* Casting is valid because it matches the type to the right side or argument. */ +#ifdef RIIC0 + if(0 == MSTP(RIIC0)) + { + return false; + } +#endif + +#ifdef RIIC2 + if(0 == MSTP(RIIC2)) + { + return false; + } +#endif + } +#endif /* BSP_MCU_VOLTAGE_LEVEL_SETTING_RIIC */ + + /* Protect off. */ + SYSTEM.PRCR.WORD = 0xA502; + + /* Casting is valid because it matches the type to the right side or argument. */ + p_volsr_addr = (uint8_t *)&SYSTEM.VOLSR.BYTE; + +#ifdef BSP_MCU_VOLTAGE_LEVEL_SETTING_RIIC + /* Updated the RICVLS bit. */ + if(0 != (ctrl_ptn & BSP_VOL_RIIC_UNDER_4_5V)) + { + R_BSP_BIT_SET(p_volsr_addr, BSP_PRV_VOLSR_RICVLS_BIT_NUM); + } + + if(0 != (ctrl_ptn & BSP_VOL_RIIC_4_5V_OROVER)) + { + R_BSP_BIT_CLEAR(p_volsr_addr, BSP_PRV_VOLSR_RICVLS_BIT_NUM); + } +#endif /* BSP_MCU_VOLTAGE_LEVEL_SETTING_RIIC */ + +#ifdef BSP_MCU_VOLTAGE_LEVEL_SETTING_AD + /* Updated the PGAVLS bit. */ + if(0 != (ctrl_ptn & BSP_VOL_AD_NEGATIVE_VOLTAGE_NOINPUT)) + { + R_BSP_BIT_SET(p_volsr_addr, BSP_PRV_VOLSR_PGAVLS_BIT_NUM); + } + + if(0 != (ctrl_ptn & BSP_VOL_AD_NEGATIVE_VOLTAGE_INPUT)) + { + R_BSP_BIT_CLEAR(p_volsr_addr, BSP_PRV_VOLSR_PGAVLS_BIT_NUM); + } +#endif /* BSP_MCU_VOLTAGE_LEVEL_SETTING_AD */ + +#ifdef BSP_MCU_VOLTAGE_LEVEL_SETTING_USB + /* Updated the USBVON bit. */ + if(0 != (ctrl_ptn & BSP_VOL_USB_POWERON)) + { + R_BSP_BIT_SET(p_volsr_addr, BSP_PRV_VOLSR_USBVON_BIT_NUM); + } + + if(0 != (ctrl_ptn & BSP_VOL_USB_POWEROFF)) + { + R_BSP_BIT_CLEAR(p_volsr_addr, BSP_PRV_VOLSR_USBVON_BIT_NUM); + } +#endif /* BSP_MCU_VOLTAGE_LEVEL_SETTING_USB */ + + /* Protect on. */ + SYSTEM.PRCR.WORD = 0xA500; + + return true; +} /* End of function R_BSP_VoltageLevelSetting() */ +#endif /* BSP_MCU_VOLTAGE_LEVEL_SETTING */ + +/********************************************************************************************************************** + * Function Name: R_BSP_SoftwareReset + ******************************************************************************************************************//** + * @details Reset the MCU by Software Reset. + */ +void R_BSP_SoftwareReset(void) +{ +#ifdef BSP_MCU_REGISTER_WRITE_PROTECTION + /* Protect off. */ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_LPC_CGC_SWR); +#endif + + /* Resets the MCU. */ + SYSTEM.SWRR = 0xA501; + + /* WAIT_LOOP */ + while(1) + { + R_BSP_NOP(); + } +} /* End of function R_BSP_SoftwareReset() */ + +/*********************************************************************************************************************** +* Function Name: bsp_register_protect_open +* Description : Initializes variables needed for register protection functionality. +* Arguments : none +* Return Value : none +***********************************************************************************************************************/ +void bsp_register_protect_open (void) +{ +#ifdef BSP_MCU_REGISTER_WRITE_PROTECTION + uint32_t i; + + /* Initialize reference counters to 0. */ + /* WAIT_LOOP */ + for (i = 0; i < BSP_REG_PROTECT_TOTAL_ITEMS; i++) + { + s_protect_counters[i] = 0; + } +#else + /* No registers to protect. */ +#endif +} /* End of function bsp_register_protect_open() */ + +/*********************************************************************************************************************** +* Function Name: bsp_ram_initialize +* Description : Initialize ram variable. +* Arguments : none +* Return Value : none +***********************************************************************************************************************/ +void bsp_ram_initialize (void) +{ + uint32_t i; + + /* Initialize g_bsp_Locks to 0. */ + /* WAIT_LOOP */ + for (i = 0; i < BSP_NUM_LOCKS; i++) + { + g_bsp_Locks[i].lock = 0; + } +} /* End of function bsp_ram_initialize() */ + +#if BSP_CFG_BUS_PRIORITY_INITIALIZE_ENABLE == 1 +/*********************************************************************************************************************** +* Function Name: bsp_bus_priority_initialize +* Description : Initialize bus priority. +* Arguments : none +* Return Value : none +***********************************************************************************************************************/ +void bsp_bus_priority_initialize (void) +{ + uint16_t tmp_priority = 0; + +#if (defined(BSP_CFG_MEMORY_BUS1_PRIORITY) && (BSP_CFG_MEMORY_BUS1_PRIORITY == 1)) || \ + (defined(BSP_CFG_MEMORY_BUS1_3_PRIORITY) && (BSP_CFG_MEMORY_BUS1_3_PRIORITY == 1)) + /* Specify the value to be set to the BPRA bit. */ + tmp_priority |= BSP_PRV_BUSPRI_BPRA_TOGGLE; +#endif + +#if (defined(BSP_CFG_MEMORY_BUS2_PRIORITY) && (BSP_CFG_MEMORY_BUS2_PRIORITY == 1)) + /* Specify the value to be set to the BPRO bit. */ + tmp_priority |= BSP_PRV_BUSPRI_BPRO_TOGGLE; +#endif + +#if (defined(BSP_CFG_INTERNAL_PERIPHERAL_BUS1_PRIORITY) && (BSP_CFG_INTERNAL_PERIPHERAL_BUS1_PRIORITY == 1)) + /* Specify the value to be set to the BPIB bit. */ + tmp_priority |= BSP_PRV_BUSPRI_BPIB_TOGGLE; +#endif + +#if (defined(BSP_CFG_INTERNAL_PERIPHERAL_BUS2_PRIORITY) && (BSP_CFG_INTERNAL_PERIPHERAL_BUS2_PRIORITY == 1)) || \ + (defined(BSP_CFG_INTERNAL_PERIPHERAL_BUS2_3_PRIORITY) && (BSP_CFG_INTERNAL_PERIPHERAL_BUS2_3_PRIORITY == 1)) + /* Specify the value to be set to the BPGB bit. */ + tmp_priority |= BSP_PRV_BUSPRI_BPGB_TOGGLE; +#endif + +#if (defined(BSP_CFG_INTERNAL_PERIPHERAL_BUS4_PRIORITY) && (BSP_CFG_INTERNAL_PERIPHERAL_BUS4_PRIORITY == 1)) || \ + (defined(BSP_CFG_INTERNAL_PERIPHERAL_BUS4_5_PRIORITY) && (BSP_CFG_INTERNAL_PERIPHERAL_BUS4_5_PRIORITY == 1)) + /* Specify the value to be set to the BPHB bit. */ + tmp_priority |= BSP_PRV_BUSPRI_BPHB_TOGGLE; +#endif + +#if (defined(BSP_CFG_INTERNAL_PERIPHERAL_BUS6_PRIORITY) && (BSP_CFG_INTERNAL_PERIPHERAL_BUS6_PRIORITY == 1)) + /* Specify the value to be set to the BPFB bit. */ + tmp_priority |= BSP_PRV_BUSPRI_BPFB_TOGGLE; +#endif + +#if (defined(BSP_CFG_EXTERNAL_BUS_PRIORITY) && (BSP_CFG_EXTERNAL_BUS_PRIORITY == 1)) + /* Specify the value to be set to the BPEB bit. */ + tmp_priority |= BSP_PRV_BUSPRI_BPEB_TOGGLE; +#endif + +#if (defined(BSP_CFG_INTERNAL_EXPANSION_BUS_PRIORITY) && (BSP_CFG_INTERNAL_EXPANSION_BUS_PRIORITY == 1)) + /* Specify the value to be set to the BPEB bit. */ + tmp_priority |= BSP_PRV_BUSPRI_BPXB_TOGGLE; +#endif + + /* Set the bus priority. */ + BSC.BUSPRI.WORD = tmp_priority; +} /* End of function bsp_bus_priority_initialize() */ +#endif /* BSP_CFG_BUS_PRIORITY_INITIALIZE_ENABLE == 1 */ + diff --git a/drivers/rx/rdp/src/r_bsp/mcu/all/r_bsp_software_interrupt.c b/drivers/rx/rdp/src/r_bsp/mcu/all/r_bsp_software_interrupt.c new file mode 100644 index 00000000..f70027c3 --- /dev/null +++ b/drivers/rx/rdp/src/r_bsp/mcu/all/r_bsp_software_interrupt.c @@ -0,0 +1,1054 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 - 2024 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_bsp_software_interrupt.c +* Description : This module implements software interrupt specific functions. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 08.10.2019 1.00 First Release +* : 10.12.2019 1.01 Modified comment. +* : 18.05.2021 1.02 Modified bsp_swint_clear_task function and bsp_swint_clear_all_task function. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "platform.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +#define BSP_PRV_SWINT_TASK_BUFFER_MAX (BSP_CFG_SWINT_TASK_BUFFER_NUMBER + 1) +#define BSP_PRV_SWINT_ACCESS_ACCEPTATION (1) +#define BSP_PRV_SWINT_ACCESS_REJECTION (0) +#define BSP_PRV_SWINT_ENABLE_NESTED_INTERRUPT (1) +#define BSP_PRV_SWINT_DISABLE_NESTED_INTERRUPT (0) + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ +#if (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) || \ + (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) + +st_bsp_swint_access_control_t g_bsp_swint_access_ctrl[BSP_SWINT_UNIT_MAX]; + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ +/* Interrupt functions */ +#if (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) +R_BSP_PRAGMA_STATIC_INTERRUPT(bsp_swint_isr, VECT(ICU, SWINT)) +#endif /* (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) */ +#if (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) +R_BSP_PRAGMA_STATIC_INTERRUPT(bsp_swint2_isr, VECT(ICU, SWINT2)) +#endif /* (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) */ + +/* Functions */ +static void bsp_swint_get_interrupt_information(e_bsp_swint_unit_t unit, void * const p_args); +static void bsp_swint_enable_interrupt(e_bsp_swint_unit_t unit); +static void bsp_swint_disable_interrupt(e_bsp_swint_unit_t unit); +static e_bsp_swint_err_t bsp_swint_set_interrupt_priority(e_bsp_swint_unit_t unit, void * const p_args); +static void bsp_swint_set_interrupt_request(e_bsp_swint_unit_t unit); +static void bsp_swint_clear_interrupt_request(e_bsp_swint_unit_t unit); +static void bsp_swint_enable_nested_interrupt(e_bsp_swint_unit_t unit); +static void bsp_swint_disable_nested_interrupt(e_bsp_swint_unit_t unit); +static e_bsp_swint_err_t bsp_swint_clear_task(e_bsp_swint_unit_t unit, void * const p_args); +static e_bsp_swint_err_t bsp_swint_clear_all_task(e_bsp_swint_unit_t unit); +static void bsp_swint_get_all_task_status(e_bsp_swint_unit_t unit, void * const p_args); +static bool bsp_swint_get_access_control(e_bsp_swint_unit_t unit, st_bsp_swint_access_control_t * const p_args); +static bool bsp_swint_release_access_control(e_bsp_swint_unit_t unit, st_bsp_swint_access_control_t * const p_args); +static void bsp_swint_execute_task(e_bsp_swint_unit_t unit); +static void bsp_swint_dummy_task(void * p_dummy_context); + +/* Variables */ +static st_bsp_swint_task_t s_bsp_swint_task[BSP_SWINT_UNIT_MAX][BSP_PRV_SWINT_TASK_BUFFER_MAX]; +static uint8_t s_bsp_swint_buf_used[BSP_SWINT_UNIT_MAX]; +static uint8_t s_bsp_swint_buf_top[BSP_SWINT_UNIT_MAX]; +static uint8_t s_bsp_swint_buf_bottom[BSP_SWINT_UNIT_MAX]; +static uint8_t s_bsp_swint_nested_int_status[BSP_SWINT_UNIT_MAX]; + +/********************************************************************************************************************** + * Function Name: R_BSP_SoftwareInterruptOpen + ******************************************************************************************************************//** + * @brief This function initializes software interrupts. + * @param[in] unit Software interrupt unit + * @retval BSP_SWINT_SUCCESS Success. + * @retval BSP_SWINT_ERR_INVALID_UNIT Invalid unit specified. + * @retval BSP_SWINT_ERR_ALREADY_OPEN Failed to lock hardware. + * @details This function locks the hardware, resets the access control status, clears the interrupt request (IR), + * initializes the interrupt priority level (IPR), enables nested-interrupt status, initializes the task buffer, and + * enables interrupts (IEN). + * @note This function is available only when use of software interrupts is enabled in a configuration macro. + * This function is called automatically at BSP startup when the value of BSP_CFG_SWINT_UNITn_ENABLE in r_bsp_config.h + * is 1. + */ +e_bsp_swint_err_t R_BSP_SoftwareInterruptOpen(e_bsp_swint_unit_t unit) +{ + bool lock_ret; + e_bsp_swint_err_t swint_ret; + uint8_t buf_num; + uint8_t swint_ipr; + + swint_ret = BSP_SWINT_SUCCESS; + + switch (unit) + { + /* Hardware Lock */ +#if (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) + case BSP_SWINT_UNIT1: + lock_ret = R_BSP_HardwareLock(BSP_LOCK_SWINT); + break; +#endif /* (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) */ + +#if (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) + case BSP_SWINT_UNIT2: + lock_ret = R_BSP_HardwareLock(BSP_LOCK_SWINT2); + break; +#endif /* (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) */ + + default: + swint_ret = BSP_SWINT_ERR_INVALID_UNIT; + break; + } + + if (BSP_SWINT_SUCCESS == swint_ret) + { + if (true == lock_ret) + { + /* Reset Access Control Status */ + g_bsp_swint_access_ctrl[unit].status = BSP_PRV_SWINT_ACCESS_ACCEPTATION; + + /* Disable Interrupt(IEN) */ + R_BSP_SoftwareInterruptControl(unit, BSP_SWINT_CMD_DISABLE_INTERRUPT, FIT_NO_PTR); + + /* Clear Interrupt Request(IR) */ + R_BSP_SoftwareInterruptControl(unit, BSP_SWINT_CMD_CLEAR_INTERRUPT_REQUEST, FIT_NO_PTR); + + /* Set Interrupt Priority(IPR) */ + swint_ipr = BSP_CFG_SWINT_IPR_INITIAL_VALUE; + R_BSP_SoftwareInterruptControl(unit, BSP_SWINT_CMD_SET_INTERRUPT_PRIORITY, &swint_ipr); + + /* Set Multiple Interrupt Status */ + s_bsp_swint_nested_int_status[unit] = BSP_PRV_SWINT_ENABLE_NESTED_INTERRUPT; + + /* Clear Task Buffer */ + for (buf_num = 0; buf_num < BSP_PRV_SWINT_TASK_BUFFER_MAX; buf_num++) + { + s_bsp_swint_task[unit][buf_num].status = BSP_SWINT_TASK_STATUS_NO_REQUEST; + s_bsp_swint_task[unit][buf_num].p_taskAddr = bsp_swint_dummy_task; + s_bsp_swint_task[unit][buf_num].p_context = FIT_NO_PTR; + } + + /* Reset Task Buffer Position */ + s_bsp_swint_buf_top[unit] = 0; + s_bsp_swint_buf_bottom[unit] = 0; + s_bsp_swint_buf_used[unit] = 0; + + /* Enable Interrupt(IEN) */ + R_BSP_SoftwareInterruptControl(unit, BSP_SWINT_CMD_ENABLE_INTERRUPT, FIT_NO_PTR); + } + else + { + swint_ret = BSP_SWINT_ERR_ALREADY_OPEN; + } + } + + return swint_ret; +} /* End of function R_BSP_SoftwareInterruptOpen() */ + +/********************************************************************************************************************** + * Function Name: R_BSP_SoftwareInterruptClose + ******************************************************************************************************************//** + * @brief This function terminates software interrupts. + * @param[in] unit Software interrupt unit + * @retval BSP_SWINT_SUCCESS Success. + * @retval BSP_SWINT_ERR_INVALID_UNIT Invalid unit specified. + * @retval BSP_SWINT_ERR_ALREADY_OPEN Failed to lock hardware. + * @details This function unlocks the hardware, disables interrupts (IEN), clears the interrupt request (IR), + * initializes the task buffer, and disables nested-interrupt status. + * @note This function is available only when use of software interrupts is enabled in a configuration macro. Use this + * function after the R_BSP_SoftwareInterruptOpen function has run.\n + * If the R_BSP_SoftwareInterruptSetTask function or software interrupt function (bsp_swint_execute_task) is acquiring + * acces control rights and an interrupt is generated and this function is called within the interrupt, the task + * buffer may not be controlled correctly. If this function is used in an interrupt, clear the all task by the + * R_BSP_SoftwareInterruptControl function with the BSP_SWINT_CMD_CLEAR_ALL_TASK command before call this function. + */ +e_bsp_swint_err_t R_BSP_SoftwareInterruptClose(e_bsp_swint_unit_t unit) +{ + bool lock_ret; + e_bsp_swint_err_t swint_ret; + uint8_t buf_num; + + /* Check Unit */ + if (BSP_SWINT_UNIT_MAX > unit) + { + /* Disable Interrupt(IEN) */ + R_BSP_SoftwareInterruptControl(unit, BSP_SWINT_CMD_DISABLE_INTERRUPT, FIT_NO_PTR); + + /* Clear Interrupt Request(IR) */ + R_BSP_SoftwareInterruptControl(unit, BSP_SWINT_CMD_CLEAR_INTERRUPT_REQUEST, FIT_NO_PTR); + + /* Clear Task Buffer */ + for (buf_num = 0; buf_num < BSP_PRV_SWINT_TASK_BUFFER_MAX; buf_num++) + { + s_bsp_swint_task[unit][buf_num].status = BSP_SWINT_TASK_STATUS_NO_REQUEST; + s_bsp_swint_task[unit][buf_num].p_taskAddr = bsp_swint_dummy_task; + s_bsp_swint_task[unit][buf_num].p_context = FIT_NO_PTR; + } + + /* Reset Task Buffer Position */ + s_bsp_swint_buf_top[unit] = 0; + s_bsp_swint_buf_bottom[unit] = 0; + s_bsp_swint_buf_used[unit] = 0; + + /* Clear Multiple Interrupt Status */ + s_bsp_swint_nested_int_status[unit] = BSP_PRV_SWINT_DISABLE_NESTED_INTERRUPT; + + switch (unit) + { + /* Hardware Lock */ +#if (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) + case BSP_SWINT_UNIT1: + lock_ret = R_BSP_HardwareUnlock(BSP_LOCK_SWINT); + break; +#endif /* (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) */ + +#if (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) + case BSP_SWINT_UNIT2: + lock_ret = R_BSP_HardwareUnlock(BSP_LOCK_SWINT2); + break; +#endif /* (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) */ + + default: + + /* Do nothing. */ + break; + } + + if (true == lock_ret) + { + swint_ret = BSP_SWINT_SUCCESS; + } + else + { + swint_ret = BSP_SWINT_ERR_NOT_CLOSED; + } + } + else + { + swint_ret = BSP_SWINT_ERR_INVALID_UNIT; + } + + return swint_ret; +} /* End of function R_BSP_SoftwareInterruptClose() */ + +/********************************************************************************************************************** + * Function Name: R_BSP_SoftwareInterruptSetTask + ******************************************************************************************************************//** + * @brief This function sets a task in the software interrupt task buffer. + * @param[in] unit Software interrupt unit + * @param[in] set_task Software interrupt task + * @retval BSP_SWINT_SUCCESS Success. + * @retval BSP_SWINT_ERR_INVALID_UNIT Invalid unit specified. + * @retval BSP_SWINT_ERR_INVALID_TASK Invalid task pointer specified. + * @retval BSP_SWINT_ERR_FULL_BUFFER Task buffer full. + * @retval BSP_SWINT_ERR_ACCESS_REJECTION Failed to obtain access control right. + * @details This function sets the task specified by an argument in the software interrupt task buffer. After setting + * the task, the software interrupt occurs. If the task buffer is full, the task is not set. + * @note This function is available only when use of software interrupts is enabled in a configuration macro. Use this + * function after the R_BSP_SoftwareInterruptOpen function has run.\n + * If the access control right cannot be obtained, provide a wait period and then call this function again. It is not + * possible to obtain the access control right during interrupt processing if the interrupt is generated in a state + * where other processing has the access control right. For this reason a deadlock will occur if polling is used in + * the interrupt processing to obtain the access control right. + */ +e_bsp_swint_err_t R_BSP_SoftwareInterruptSetTask(e_bsp_swint_unit_t unit, st_bsp_swint_task_t set_task) +{ + e_bsp_swint_err_t ret; + st_bsp_swint_access_control_t access_control; + + /* Check Unit */ + if (BSP_SWINT_UNIT_MAX > unit) + { + /* Get Access Control */ + access_control.status = BSP_PRV_SWINT_ACCESS_REJECTION; + if (true == bsp_swint_get_access_control(unit, &access_control)) + { + /* Casting is valid because it matches the type to the right side or argument. */ + if (((uint32_t)FIT_NO_FUNC == (uint32_t)set_task.p_taskAddr) || ((uint32_t)NULL == (uint32_t)set_task.p_taskAddr)) + { + ret = BSP_SWINT_ERR_INVALID_TASK; + } + else if (BSP_CFG_SWINT_TASK_BUFFER_NUMBER <= s_bsp_swint_buf_used[unit]) + { + ret = BSP_SWINT_ERR_FULL_BUFFER; + } + else + { + if (BSP_CFG_SWINT_TASK_BUFFER_NUMBER <= s_bsp_swint_buf_top[unit]) + { + s_bsp_swint_buf_top[unit] = 0; + } + else + { + s_bsp_swint_buf_top[unit]++; + } + + s_bsp_swint_buf_used[unit]++; + + /* Set Task Buffer */ + s_bsp_swint_task[unit][s_bsp_swint_buf_top[unit]].status = BSP_SWINT_TASK_STATUS_REQUESTED; + s_bsp_swint_task[unit][s_bsp_swint_buf_top[unit]].p_taskAddr = set_task.p_taskAddr; + s_bsp_swint_task[unit][s_bsp_swint_buf_top[unit]].p_context = set_task.p_context; + + ret = BSP_SWINT_SUCCESS; + } + + /* Release Access Control */ + bsp_swint_release_access_control(unit, &access_control); + + /* Set Interrupt Request(IR) */ + R_BSP_SoftwareInterruptControl(unit, BSP_SWINT_CMD_SET_INTERRUPT_REQUEST, FIT_NO_PTR); + } + else + { + ret = BSP_SWINT_ERR_ACCESS_REJECTION; + } + } + else + { + ret = BSP_SWINT_ERR_INVALID_UNIT; + } + + return ret; +} /* End of function R_BSP_SoftwareInterruptSetTask() */ + +/*********************************************************************************************************************** +* Function Name: bsp_swint_get_interrupt_information +* Description : Get the software interrupt information. +* Arguments : unit - Unit number of software interrupt. +* p_args - Pointer of setting parameter. +* Return Value : None. +***********************************************************************************************************************/ +static void bsp_swint_get_interrupt_information(e_bsp_swint_unit_t unit, void * const p_args) +{ + st_bsp_swint_int_info_t *p_swint_int_info; + + /* Casting is valid because it matches the type of the void type argument to the left. */ + p_swint_int_info = (st_bsp_swint_int_info_t *)p_args; + + switch (unit) + { + /* Get Interrupt Information */ +#if (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) + case BSP_SWINT_UNIT1: + p_swint_int_info->ipr = IPR(ICU, SWINT); + p_swint_int_info->ien = IEN(ICU, SWINT); + p_swint_int_info->ir = IR(ICU, SWINT); + p_swint_int_info->nested_int = s_bsp_swint_nested_int_status[unit]; + break; +#endif /* (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) */ + +#if (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) + case BSP_SWINT_UNIT2: + p_swint_int_info->ipr = IPR(ICU, SWINT2); + p_swint_int_info->ien = IEN(ICU, SWINT2); + p_swint_int_info->ir = IR(ICU, SWINT2); + p_swint_int_info->nested_int = s_bsp_swint_nested_int_status[unit]; + break; +#endif /* (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) */ + + default: + + /* Do nothing. */ + break; + } +} /* End of function bsp_swint_get_interrupt_information() */ + +/*********************************************************************************************************************** +* Function Name: bsp_swint_enable_interrupt +* Description : Enable interrupt. (Set the IEN bit.) +* Arguments : unit - Unit number of software interrupt. +* Return Value : None. +***********************************************************************************************************************/ +static void bsp_swint_enable_interrupt(e_bsp_swint_unit_t unit) +{ + switch (unit) + { + /* Enable Interrupt */ +#if (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) + case BSP_SWINT_UNIT1: + R_BSP_InterruptRequestEnable(VECT(ICU, SWINT)); + break; +#endif /* (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) */ + +#if (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) + case BSP_SWINT_UNIT2: + R_BSP_InterruptRequestEnable(VECT(ICU, SWINT2)); + break; +#endif /* (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) */ + + default: + + /* Do nothing. */ + break; + } +} /* End of function bsp_swint_enable_interrupt() */ + +/*********************************************************************************************************************** +* Function Name: bsp_swint_disable_interrupt +* Description : Disable interrupt. (Clear the IEN bit.) +* Arguments : unit - Unit number of software interrupt. +* Return Value : None. +***********************************************************************************************************************/ +static void bsp_swint_disable_interrupt(e_bsp_swint_unit_t unit) +{ + switch (unit) + { + /* Disable Interrupt */ +#if (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) + case BSP_SWINT_UNIT1: + R_BSP_InterruptRequestDisable(VECT(ICU, SWINT)); + break; +#endif /* (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) */ + +#if (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) + case BSP_SWINT_UNIT2: + R_BSP_InterruptRequestDisable(VECT(ICU, SWINT2)); + break; +#endif /* (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) */ + + default: + + /* Do nothing. */ + break; + } +} /* End of function bsp_swint_disable_interrupt() */ + +/*********************************************************************************************************************** +* Function Name: bsp_swint_set_interrupt_priority +* Description : Set interrupt priority. (Set the IPR register.) +* Arguments : unit - Unit number of software interrupt. +* p_args - Pointer of setting parameter. +* Return Value : BSP_SWINT_SUCCESS - Operation successful. +* BSP_SWINT_ERR_INVALID_IPR - Overflow interrupt priority. +***********************************************************************************************************************/ +static e_bsp_swint_err_t bsp_swint_set_interrupt_priority(e_bsp_swint_unit_t unit, void * const p_args) +{ + e_bsp_swint_err_t ret; + uint8_t *p_swint_ipr; + uint8_t ien; + bsp_int_ctrl_t int_ctrl; + + /* Casting is valid because it matches the type of the void type argument to the left. */ + p_swint_ipr = (uint8_t *)p_args; + + /* Check Interrupt Priority */ + if (BSP_MCU_IPL_MAX < (*p_swint_ipr)) + { + ret = BSP_SWINT_ERR_INVALID_IPR; + } + else + { + /* Set IPL to the maximum value to disable all interrupts*/ + R_BSP_InterruptControl(BSP_INT_SRC_EMPTY, BSP_INT_CMD_FIT_INTERRUPT_DISABLE, &int_ctrl); + + switch (unit) + { + /* Set Interrupt Priority */ +#if (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) + case BSP_SWINT_UNIT1: + ien = IEN(ICU, SWINT); + R_BSP_InterruptRequestDisable(VECT(ICU, SWINT)); + + /* Casting is valid because it matches the type to the left side. */ + IPR(ICU, SWINT) = (uint8_t)*p_swint_ipr; + + if (1 == ien) + { + R_BSP_InterruptRequestEnable(VECT(ICU, SWINT)); + } + break; +#endif /* (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) */ + +#if (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) + case BSP_SWINT_UNIT2: + ien = IEN(ICU, SWINT2); + R_BSP_InterruptRequestDisable(VECT(ICU, SWINT2)); + + /* Casting is valid because it matches the type to the left side. */ + IPR(ICU, SWINT2) = (uint8_t)*p_swint_ipr; + + if (1 == ien) + { + R_BSP_InterruptRequestEnable(VECT(ICU, SWINT2)); + } + break; +#endif /* (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) */ + + default: + + /* Do nothing. */ + break; + } + + /* Restore the IPL */ + R_BSP_InterruptControl(BSP_INT_SRC_EMPTY, BSP_INT_CMD_FIT_INTERRUPT_ENABLE, &int_ctrl); + + ret = BSP_SWINT_SUCCESS; + } + + return ret; +} /* End of function bsp_swint_set_interrupt_priority() */ + +/*********************************************************************************************************************** +* Function Name: bsp_swint_set_interrupt_request +* Description : Set interrupt request. (Set the SWINTR register.) +* Arguments : unit - Unit number of software interrupt. +* Return Value : None. +***********************************************************************************************************************/ +static void bsp_swint_set_interrupt_request(e_bsp_swint_unit_t unit) +{ + switch (unit) + { + /* Set Interrupt Request */ +#if (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) + case BSP_SWINT_UNIT1: + ICU.SWINTR.BIT.SWINT = 1; + break; +#endif /* (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) */ + +#if (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) + case BSP_SWINT_UNIT2: + ICU.SWINT2R.BIT.SWINT2 = 1; + break; +#endif /* (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) */ + + default: + + /* Do nothing. */ + break; + } +} /* End of function bsp_swint_set_interrupt_request() */ + +/*********************************************************************************************************************** +* Function Name: bsp_swint_clear_interrupt_request +* Description : Clear interrupt request. (Clear the IR bit.) +* Arguments : unit - Unit number of software interrupt. +* Return Value : None. +***********************************************************************************************************************/ +static void bsp_swint_clear_interrupt_request(e_bsp_swint_unit_t unit) +{ + switch (unit) + { + /* Clear Interrupt Request */ +#if (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) + case BSP_SWINT_UNIT1: + IR(ICU, SWINT) = 0; + break; +#endif /* (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) */ + +#if (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) + case BSP_SWINT_UNIT2: + IR(ICU, SWINT2) = 0; + break; +#endif /* (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) */ + + default: + + /* Do nothing. */ + break; + } +} /* End of function bsp_swint_clear_interrupt_request() */ + +/*********************************************************************************************************************** +* Function Name: bsp_swint_enable_nested_interrupt +* Description : Set nested interrupt status. +* Arguments : unit - Unit number of software interrupt. +* Return Value : None. +***********************************************************************************************************************/ +static void bsp_swint_enable_nested_interrupt(e_bsp_swint_unit_t unit) +{ + /* Set Multiple Interrupt Status */ + s_bsp_swint_nested_int_status[unit] = BSP_PRV_SWINT_ENABLE_NESTED_INTERRUPT; +} /* End of function bsp_swint_enable_nested_interrupt() */ + +/*********************************************************************************************************************** +* Function Name: bsp_swint_disable_nested_interrupt +* Description : Clear nested interrupt status. +* Arguments : unit - Unit number of software interrupt. +* Return Value : None. +***********************************************************************************************************************/ +static void bsp_swint_disable_nested_interrupt(e_bsp_swint_unit_t unit) +{ + /* Clear Multiple Interrupt Status */ + s_bsp_swint_nested_int_status[unit] = BSP_PRV_SWINT_DISABLE_NESTED_INTERRUPT; +} /* End of function bsp_swint_disable_nested_interrupt() */ + +/*********************************************************************************************************************** +* Function Name: bsp_swint_clear_task +* Description : Clear the task of software interrupt in the buffer. +* Arguments : unit - Unit number of software interrupt. +* p_args - Pointer of setting parameter. +* Return Value : BSP_SWINT_SUCCESS - Operation successful. +* BSP_SWINT_ERR_ACCESS_REJECTION - Failed to get access. +* BSP_SWINT_ERR_TASK_EXECUTING - Accessed during task execution. +* BSP_SWINT_ERR_INVALID_BUFFER_NUMBER - Set invalid buffer number. +***********************************************************************************************************************/ +static e_bsp_swint_err_t bsp_swint_clear_task(e_bsp_swint_unit_t unit, void * const p_args) +{ + e_bsp_swint_err_t ret; + st_bsp_swint_task_buffer_t *p_swint_task_buffer; + st_bsp_swint_access_control_t access_control; + + /* Get Access Control */ + access_control.status = BSP_PRV_SWINT_ACCESS_REJECTION; + if (true == bsp_swint_get_access_control(unit, &access_control)) + { + /* Casting is valid because it matches the type of the void type argument to the left. */ + p_swint_task_buffer = (st_bsp_swint_task_buffer_t *)p_args; + + if (BSP_PRV_SWINT_TASK_BUFFER_MAX > p_swint_task_buffer->number) + { + /* Clear Task Buffer */ + if (BSP_SWINT_TASK_STATUS_EXECUTING != s_bsp_swint_task[unit][p_swint_task_buffer->number].status) + { + s_bsp_swint_task[unit][p_swint_task_buffer->number].status = BSP_SWINT_TASK_STATUS_NO_REQUEST; + s_bsp_swint_task[unit][p_swint_task_buffer->number].p_taskAddr = bsp_swint_dummy_task; + s_bsp_swint_task[unit][p_swint_task_buffer->number].p_context = FIT_NO_PTR; + ret = BSP_SWINT_SUCCESS; + } + else + { + ret = BSP_SWINT_ERR_TASK_EXECUTING; + } + } + else + { + ret = BSP_SWINT_ERR_INVALID_BUFFER_NUMBER; + } + + /* Release Access Control */ + bsp_swint_release_access_control(unit, &access_control); + + /* Set Interrupt Request(IR) + * If a software interrupt is generated while this function has the access control right, the software + * interrupt cannot obtain the access control right and interrupt processing ends with the task remaining + * unexecuted. For this reason, after returning from a software interrupt the interrupt request is cleared + * regardless of whether a task has been set in the task buffer. To avoid it, setting of the interrupt + * request occurs in this timing. + */ + bsp_swint_set_interrupt_request(unit); + } + else + { + ret = BSP_SWINT_ERR_ACCESS_REJECTION; + } + + return ret; +} /* End of function bsp_swint_clear_task() */ + +/*********************************************************************************************************************** +* Function Name: bsp_swint_clear_all_task +* Description : Clear the all task of software interrupt in the buffer. +* Arguments : unit - Unit number of software interrupt. +* Return Value : BSP_SWINT_SUCCESS - Operation successful. +* BSP_SWINT_ERR_ACCESS_REJECTION - Failed to get access. +* BSP_SWINT_ERR_TASK_EXECUTING - Accessed during task execution. +***********************************************************************************************************************/ +static e_bsp_swint_err_t bsp_swint_clear_all_task(e_bsp_swint_unit_t unit) +{ + e_bsp_swint_err_t ret; + uint8_t buf_num; + st_bsp_swint_access_control_t access_control; + + /* Get Access Control */ + access_control.status = BSP_PRV_SWINT_ACCESS_REJECTION; + if (true == bsp_swint_get_access_control(unit, &access_control)) + { + ret = BSP_SWINT_SUCCESS; + + /* Check Task Status */ + for (buf_num = 0; buf_num < BSP_PRV_SWINT_TASK_BUFFER_MAX; buf_num++) + { + if (BSP_SWINT_TASK_STATUS_EXECUTING == s_bsp_swint_task[unit][buf_num].status) + { + ret = BSP_SWINT_ERR_TASK_EXECUTING; + break; + } + } + + if (BSP_SWINT_SUCCESS == ret) + { + /* Clear ALL Task Buffer */ + for (buf_num = 0; buf_num < BSP_PRV_SWINT_TASK_BUFFER_MAX; buf_num++) + { + s_bsp_swint_task[unit][buf_num].status = BSP_SWINT_TASK_STATUS_NO_REQUEST; + s_bsp_swint_task[unit][buf_num].p_taskAddr = bsp_swint_dummy_task; + s_bsp_swint_task[unit][buf_num].p_context = FIT_NO_PTR; + } + + /* Reset Task Buffer Position */ + s_bsp_swint_buf_top[unit] = 0; + s_bsp_swint_buf_bottom[unit] = 0; + s_bsp_swint_buf_used[unit] = 0; + + /* Release Access Control */ + bsp_swint_release_access_control(unit, &access_control); + } + else + { + /* Release Access Control */ + bsp_swint_release_access_control(unit, &access_control); + + /* Set Interrupt Request(IR) + * If a software interrupt is generated while this function has the access control right, the software + * interrupt cannot obtain the access control right and interrupt processing ends with the task remaining + * unexecuted. For this reason, after returning from a software interrupt the interrupt request is cleared + * regardless of whether a task has been set in the task buffer. To avoid it, setting of the interrupt + * request occurs in this timing. + */ + bsp_swint_set_interrupt_request(unit); + } + } + else + { + ret = BSP_SWINT_ERR_ACCESS_REJECTION; + } + + return ret; +} /* End of function bsp_swint_clear_all_task() */ + +/*********************************************************************************************************************** +* Function Name: bsp_swint_get_all_task_status +* Description : Get the task status of software interrupt. +* Arguments : unit - Unit number of software interrupt. +* p_args - Pointer of setting parameter. +* Return Value : None. +***********************************************************************************************************************/ +static void bsp_swint_get_all_task_status(e_bsp_swint_unit_t unit, void * const p_args) +{ + uint8_t buf_num; + st_bsp_swint_task_t *p_swint_task; + + /* Casting is valid because it matches the type of the void type argument to the left. */ + p_swint_task = (st_bsp_swint_task_t *)p_args; + + /* Clear Task Status */ + for (buf_num = 0; buf_num < BSP_PRV_SWINT_TASK_BUFFER_MAX; buf_num++) + { + p_swint_task->status = s_bsp_swint_task[unit][buf_num].status; + p_swint_task->p_taskAddr = s_bsp_swint_task[unit][buf_num].p_taskAddr; + p_swint_task->p_context = s_bsp_swint_task[unit][buf_num].p_context; + p_swint_task++; + } +} /* End of function bsp_swint_get_all_task_status() */ + +/********************************************************************************************************************** + * Function Name: R_BSP_SoftwareInterruptControl + ******************************************************************************************************************//** + * @brief This function controls software interrupts. + * @param[in] unit Software interrupt unit + * @param[in] cmd Software interrupt control command + * @param[in, out] p_args Pointer to arguments for software interrupt control commands. Set the argument type to match + * each software interrupt control command. For commands that do not require arguments, use the setting FIT_NO_PTR. + * @retval BSP_SWINT_SUCCESS Success. + * @retval BSP_SWINT_ERR_INVALID_UNIT Invalid unit specified. + * @retval BSP_SWINT_ERR_INVALID_IPR Invalid interrupt priority level specified. + * @retval BSP_SWINT_ERR_INVALID_CMD Invalid command specified. + * @retval BSP_SWINT_ERR_INVALID_BUFFER_NUMBER Invalid task buffer number specified. + * @retval BSP_SWINT_ERR_TASK_EXECUTING Attempt to manipulate a task that is running. + * @retval BSP_SWINT_ERR_ACCESS_REJECTION Failed to obtain access control right. + * @details This function performs software interrupt control in response to commands. Refer the application note for + * the operation of each command. + * @note This function is available only when use of software interrupts is enabled in a configuration macro. Use this + * function after the R_BSP_SoftwareInterruptOpen function has run.\n + * Do not change the interrupt priority level (IPR) while a software interrupt is being processed.\n + * When the BSP_SWINT_CMD_SET_INTERRUPT_PRIORITY command is run, interrupts are disabled temporarily in order to set + * the interrupt priority level (IPR).\n + * If the access control right cannot be obtained, provide a wait period and then call this function again. It is not + * possible to obtain the access control right during interrupt processing if the interrupt is generated in a state + * where other processing has the access control right. For this reason a deadlock will occur if polling is used in + * the interrupt processing to obtain the access control right.\n + * If a software interrupt is generated while this function has the access control right, the software interrupt + * cannot obtain the access control right and interrupt processing ends with the task remaining unexecuted. For this + * reason, after returning from a software interrupt the interrupt request is cleared regardless of whether a task has + * been set in the task buffer. To avoid this, setting of the interrupt request occurs at the end of the processing of + * the BSP_SWINT_CMD_CLEAR_TASK and BSP_SWINT_CMD_CLEAR_ALL_TASK commands. Nevertheless, since all task buffers are + * cleared when processing of the BSP_SWINT_CMD_CLEAR_ALL_TASK command completes successfully, the interrupt request + * is not set. + */ +e_bsp_swint_err_t R_BSP_SoftwareInterruptControl(e_bsp_swint_unit_t unit, e_bsp_swint_cmd_t const cmd, void * const p_args) +{ + e_bsp_swint_err_t ret; + uint8_t *p_swint_buf_num; + + /* Check Unit */ + if (BSP_SWINT_UNIT_MAX > unit) + { + ret = BSP_SWINT_SUCCESS; + + /* Execute Command */ + switch (cmd) + { + case BSP_SWINT_CMD_GET_INTERRUPT_INFORMATION: + bsp_swint_get_interrupt_information(unit, p_args); + break; + + case BSP_SWINT_CMD_ENABLE_INTERRUPT: + bsp_swint_enable_interrupt(unit); + break; + + case BSP_SWINT_CMD_DISABLE_INTERRUPT: + bsp_swint_disable_interrupt(unit); + break; + + case BSP_SWINT_CMD_SET_INTERRUPT_PRIORITY: + ret = bsp_swint_set_interrupt_priority(unit, p_args); + break; + + case BSP_SWINT_CMD_SET_INTERRUPT_REQUEST: + bsp_swint_set_interrupt_request(unit); + break; + + case BSP_SWINT_CMD_CLEAR_INTERRUPT_REQUEST: + bsp_swint_clear_interrupt_request(unit); + break; + + case BSP_SWINT_CMD_ENABLE_NESTED_INTERRUPT: + bsp_swint_enable_nested_interrupt(unit); + break; + + case BSP_SWINT_CMD_DISABLE_NESTED_INTERRUPT: + bsp_swint_disable_nested_interrupt(unit); + break; + + case BSP_SWINT_CMD_CLEAR_TASK: + ret = bsp_swint_clear_task(unit, p_args); + break; + + case BSP_SWINT_CMD_CLEAR_ALL_TASK: + ret = bsp_swint_clear_all_task(unit); + break; + + case BSP_SWINT_CMD_GET_ALL_TASK_STATUS: + bsp_swint_get_all_task_status(unit, p_args); + break; + + case BSP_SWINT_CMD_GET_USED_BUFFER: + + /* Casting is valid because it matches the type of the void type argument to the left. */ + p_swint_buf_num = (uint8_t *)p_args; + + /* Casting is valid because it matches the type to the left side. */ + *p_swint_buf_num = (uint8_t)s_bsp_swint_buf_used[unit]; + break; + + case BSP_SWINT_CMD_GET_UNUSED_BUFFER: + + /* Casting is valid because it matches the type of the void type argument to the left. */ + p_swint_buf_num = (uint8_t *)p_args; + + /* Casting is valid because it matches the type to the left side. */ + *p_swint_buf_num = (uint8_t)(BSP_CFG_SWINT_TASK_BUFFER_NUMBER - s_bsp_swint_buf_used[unit]); + break; + + default: + ret = BSP_SWINT_ERR_INVALID_CMD; + break; + } + } + else + { + ret = BSP_SWINT_ERR_INVALID_UNIT; + } + + return ret; +} /* End of function R_BSP_SoftwareInterruptControl() */ + +/*********************************************************************************************************************** +* Function Name: bsp_swint_get_access_control +* Description : Get access of software interrupt. +* Arguments : unit - Unit number of software interrupt. +* p_args - Pointer of setting parameter. +* Return Value : true - Get access. +* false - Failed to get access. +***********************************************************************************************************************/ +static bool bsp_swint_get_access_control(e_bsp_swint_unit_t unit, st_bsp_swint_access_control_t * const p_args) +{ + bool ret; + + /* Get Access */ + R_BSP_EXCHANGE(&g_bsp_swint_access_ctrl[unit].status, &p_args->status); + + if (BSP_PRV_SWINT_ACCESS_ACCEPTATION == p_args->status) + { + ret = true; + } + else + { + ret = false; + } + + return ret; +} /* End of function bsp_swint_get_access_control() */ + +/*********************************************************************************************************************** +* Function Name: bsp_swint_release_access_control +* Description : Release access of software interrupt. +* Arguments : unit - Unit number of software interrupt. +* p_args - Pointer of setting parameter. +* Return Value : true - Release access. +* false - Failed to release access. +***********************************************************************************************************************/ +static bool bsp_swint_release_access_control(e_bsp_swint_unit_t unit, st_bsp_swint_access_control_t * const p_args) +{ + bool ret; + + /* Release access */ + R_BSP_EXCHANGE(&g_bsp_swint_access_ctrl[unit].status, &p_args->status); + + if (BSP_PRV_SWINT_ACCESS_ACCEPTATION == g_bsp_swint_access_ctrl[unit].status) + { + ret = true; + } + else + { + ret = false; + } + + return ret; +} /* End of function bsp_swint_release_access_control() */ + +/*********************************************************************************************************************** +* Function name: bsp_swint_dummy_task +* Description : Dummy task. +* Arguments : p_dummy_context - Dummy arguments. +* Return value : None. +***********************************************************************************************************************/ +static void bsp_swint_dummy_task(void * p_dummy_context) +{ + R_BSP_NOP(); +} /* End of function bsp_swint_dummy_task() */ + +/*********************************************************************************************************************** +* Function name: bsp_swint_execute_task +* Description : Execute task of software interrupt. +* Arguments : unit - Unit number of software interrupt. +* Return value : None. +***********************************************************************************************************************/ +static void bsp_swint_execute_task(e_bsp_swint_unit_t unit) +{ + st_bsp_swint_access_control_t access_control; + + /* Get Access Control */ + access_control.status = BSP_PRV_SWINT_ACCESS_REJECTION; + if (true == bsp_swint_get_access_control(unit, &access_control)) + { + /* Release Access Control */ + bsp_swint_release_access_control(unit, &access_control); + + /* Enable Multiple Interrupt */ + if (BSP_PRV_SWINT_ENABLE_NESTED_INTERRUPT == s_bsp_swint_nested_int_status[unit]) + { + R_BSP_InterruptsEnable(); + } + + /* Get Access Control */ + access_control.status = BSP_PRV_SWINT_ACCESS_REJECTION; + bsp_swint_get_access_control(unit, &access_control); + + /* WAIT_LOOP */ + while (0 != s_bsp_swint_buf_used[unit]) + { + if (BSP_CFG_SWINT_TASK_BUFFER_NUMBER <= s_bsp_swint_buf_bottom[unit]) + { + s_bsp_swint_buf_bottom[unit] = 0; + } + else + { + s_bsp_swint_buf_bottom[unit]++; + } + + if (BSP_SWINT_TASK_STATUS_REQUESTED == s_bsp_swint_task[unit][s_bsp_swint_buf_bottom[unit]].status) + { + /* Change Task Status to "EXECUTING" */ + s_bsp_swint_task[unit][s_bsp_swint_buf_bottom[unit]].status = BSP_SWINT_TASK_STATUS_EXECUTING; + + /* Release Access Control */ + bsp_swint_release_access_control(unit, &access_control); + + /* Execute Task */ + s_bsp_swint_task[unit][s_bsp_swint_buf_bottom[unit]].p_taskAddr(s_bsp_swint_task[unit][s_bsp_swint_buf_bottom[unit]].p_context); + + /* Get Access Control */ + access_control.status = BSP_PRV_SWINT_ACCESS_REJECTION; + bsp_swint_get_access_control(unit, &access_control); + + if (BSP_SWINT_TASK_STATUS_EXECUTING == s_bsp_swint_task[unit][s_bsp_swint_buf_bottom[unit]].status) + { + /* Change Task Status to "COMPLETED" */ + s_bsp_swint_task[unit][s_bsp_swint_buf_bottom[unit]].status = BSP_SWINT_TASK_STATUS_COMPLETED; + } + } + + if (0 != s_bsp_swint_buf_used[unit]) + { + s_bsp_swint_buf_used[unit]--; + } + } + + /* Release Access Control */ + bsp_swint_release_access_control(unit, &access_control); + } +} /* End of function bsp_swint_execute_task() */ + +#endif /* (BSP_CFG_SWINT_UNIT1_ENABLE == 1) || (BSP_CFG_SWINT_UNIT2_ENABLE == 1) */ + +#if (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) +/*********************************************************************************************************************** +* Function name: bsp_swint_isr +* Description : Software interrupt function. (Unit1) +* Arguments : None. +* Return value : None. +***********************************************************************************************************************/ +R_BSP_ATTRIB_STATIC_INTERRUPT void bsp_swint_isr(void) +{ + bsp_swint_execute_task(BSP_SWINT_UNIT1); +} /* End of function bsp_swint_isr() */ +#endif /* (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) */ + +#if (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) +/*********************************************************************************************************************** +* Function name: bsp_swint2_isr +* Description : Software interrupt function. (Unit2) +* Arguments : None. +* Return value : None. +***********************************************************************************************************************/ +R_BSP_ATTRIB_STATIC_INTERRUPT void bsp_swint2_isr(void) +{ + bsp_swint_execute_task(BSP_SWINT_UNIT2); +} /* End of function bsp_swint2_isr() */ +#endif /* (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) */ + diff --git a/drivers/rx/rdp/src/r_bsp/mcu/all/r_bsp_software_interrupt.h b/drivers/rx/rdp/src/r_bsp/mcu/all/r_bsp_software_interrupt.h new file mode 100644 index 00000000..8a752d22 --- /dev/null +++ b/drivers/rx/rdp/src/r_bsp/mcu/all/r_bsp_software_interrupt.h @@ -0,0 +1,138 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2019 - 2024 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_bsp_software_interrupt.h +* Description : This module implements software interrupt specific functions. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 08.10.2019 1.00 First Release +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "platform.h" + +/* Multiple inclusion prevention macro */ +#ifndef SOFTWARE_INTERRUPT_H +#define SOFTWARE_INTERRUPT_H + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ +#if (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) || \ + (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) + +typedef enum e_bsp_swint_unit +{ +#if (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) + BSP_SWINT_UNIT1, +#endif /* (defined(BSP_CFG_SWINT_UNIT1_ENABLE) && (BSP_CFG_SWINT_UNIT1_ENABLE == 1)) */ +#if (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) + BSP_SWINT_UNIT2, +#endif /* (defined(BSP_CFG_SWINT_UNIT2_ENABLE) && (BSP_CFG_SWINT_UNIT2_ENABLE == 1)) */ + BSP_SWINT_UNIT_MAX +} e_bsp_swint_unit_t; + +typedef enum e_bsp_swint_err +{ + BSP_SWINT_SUCCESS = 0, + BSP_SWINT_ERR_ALREADY_OPEN, + BSP_SWINT_ERR_NOT_CLOSED, + BSP_SWINT_ERR_INVALID_UNIT, + BSP_SWINT_ERR_INVALID_IPR, + BSP_SWINT_ERR_INVALID_CMD, + BSP_SWINT_ERR_INVALID_TASK, + BSP_SWINT_ERR_INVALID_BUFFER_NUMBER, + BSP_SWINT_ERR_TASK_EXECUTING, + BSP_SWINT_ERR_FULL_BUFFER, + BSP_SWINT_ERR_ACCESS_REJECTION +} e_bsp_swint_err_t; + +typedef enum e_bsp_swint_cmd +{ + BSP_SWINT_CMD_GET_INTERRUPT_INFORMATION = 0, + BSP_SWINT_CMD_ENABLE_INTERRUPT, + BSP_SWINT_CMD_DISABLE_INTERRUPT, + BSP_SWINT_CMD_SET_INTERRUPT_PRIORITY, + BSP_SWINT_CMD_SET_INTERRUPT_REQUEST, + BSP_SWINT_CMD_CLEAR_INTERRUPT_REQUEST, + BSP_SWINT_CMD_ENABLE_NESTED_INTERRUPT, + BSP_SWINT_CMD_DISABLE_NESTED_INTERRUPT, + BSP_SWINT_CMD_CLEAR_TASK, + BSP_SWINT_CMD_CLEAR_ALL_TASK, + BSP_SWINT_CMD_GET_ALL_TASK_STATUS, + BSP_SWINT_CMD_GET_USED_BUFFER, + BSP_SWINT_CMD_GET_UNUSED_BUFFER +} e_bsp_swint_cmd_t; + +typedef struct st_bsp_swint_int_info +{ + uint8_t ipr; + uint8_t ien; + uint8_t ir; + uint8_t nested_int; +} st_bsp_swint_int_info_t; + +typedef enum e_bsp_swint_task_status +{ + BSP_SWINT_TASK_STATUS_NO_REQUEST = 0, + BSP_SWINT_TASK_STATUS_REQUESTED, + BSP_SWINT_TASK_STATUS_EXECUTING, + BSP_SWINT_TASK_STATUS_COMPLETED +} e_bsp_swint_task_status_t; + +typedef struct st_bsp_swint_task +{ + e_bsp_swint_task_status_t status; + void (*p_taskAddr)(void *p_task_args); + void *p_context; +} st_bsp_swint_task_t; + +typedef struct st_bsp_swint_task_buffer +{ + uint8_t number; +} st_bsp_swint_task_buffer_t; + +typedef struct st_bsp_swint_access_control +{ + int32_t status; +} st_bsp_swint_access_control_t; + +/*********************************************************************************************************************** +Exported global variables +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ +e_bsp_swint_err_t R_BSP_SoftwareInterruptOpen(e_bsp_swint_unit_t unit); +e_bsp_swint_err_t R_BSP_SoftwareInterruptClose(e_bsp_swint_unit_t unit); +e_bsp_swint_err_t R_BSP_SoftwareInterruptSetTask(e_bsp_swint_unit_t unit, st_bsp_swint_task_t set_task); +e_bsp_swint_err_t R_BSP_SoftwareInterruptControl(e_bsp_swint_unit_t unit, e_bsp_swint_cmd_t const cmd, void * const p_args); + +#endif /* (BSP_CFG_SWINT_UNIT1_ENABLE == 1) || (BSP_CFG_SWINT_UNIT2_ENABLE == 1) */ + +#endif /* End of multiple inclusion prevention macro */ + diff --git a/drivers/rx/rdp/src/r_bsp/mcu/rx130/mcu_locks.h b/drivers/rx/rdp/src/r_bsp/mcu/rx130/mcu_locks.h new file mode 100644 index 00000000..291320bf --- /dev/null +++ b/drivers/rx/rdp/src/r_bsp/mcu/rx130/mcu_locks.h @@ -0,0 +1,152 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 - 2024 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : mcu_locks.h +* Device(s) : RX130 +* Description : This source file has 1 lock per MCU resource. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 01.12.2015 1.00 First release +* : 15.05.2017 1.01 Added the following enumeration constant. +* -BSP_LOCK_REMC0 +* -BSP_LOCK_REMC1 +* -BSP_LOCK_REMCOM +* -BSP_LOCK_SCI0 +* -BSP_LOCK_SCI8 +* -BSP_LOCK_SCI9 +* -BSP_LOCK_SMCI0 +* -BSP_LOCK_SMCI8 +* -BSP_LOCK_SMCI9 +* -BSP_LOCK_TEMPS +* : 28.02.2019 1.02 Deleted the following enumeration constant. +* - BSP_LOCK_SMCIx (x = 0, 1, 5, 6, 8, 9 and 12.) +* Fixed coding style. +* : 08.10.2019 1.03 Added the following enumeration constant. +* - BSP_LOCK_SWINT +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +/* Gets MCU configuration information. */ +#include "r_bsp_config.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef MCU_LOCKS_H +#define MCU_LOCKS_H + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ +/* This enum defines all of the available hardware locks for this MCU. If you delete an entry out of this list then you + will decrease the size of the locks array but will not be able to use that lock. For example, if your design is not + using CAN at all then you can safely remove the BSP_LOCK_CAN# entries below. */ +typedef enum +{ + BSP_LOCK_BSC = 0, + BSP_LOCK_CAC, + BSP_LOCK_CMPB, + BSP_LOCK_CMT, + BSP_LOCK_CMT0, + BSP_LOCK_CMT1, + BSP_LOCK_CRC, + BSP_LOCK_CTSU, + BSP_LOCK_DA, + BSP_LOCK_DOC, + BSP_LOCK_DTC, + BSP_LOCK_ELC, + BSP_LOCK_FLASH, + BSP_LOCK_ICU, + BSP_LOCK_IRQ0, + BSP_LOCK_IRQ1, + BSP_LOCK_IRQ2, + BSP_LOCK_IRQ3, + BSP_LOCK_IRQ4, + BSP_LOCK_IRQ5, + BSP_LOCK_IRQ6, + BSP_LOCK_IRQ7, + BSP_LOCK_IWDT, + BSP_LOCK_LPT, + BSP_LOCK_MPC, + BSP_LOCK_MTU, + BSP_LOCK_MTU0, + BSP_LOCK_MTU1, + BSP_LOCK_MTU2, + BSP_LOCK_MTU3, + BSP_LOCK_MTU4, + BSP_LOCK_MTU5, + BSP_LOCK_POE, + BSP_LOCK_REMC0, + BSP_LOCK_REMC1, + BSP_LOCK_REMCOM, + BSP_LOCK_RIIC0, + BSP_LOCK_RSPI0, + BSP_LOCK_RTC, + BSP_LOCK_RTCB, + BSP_LOCK_S12AD, + BSP_LOCK_SCI0, + BSP_LOCK_SCI1, + BSP_LOCK_SCI5, + BSP_LOCK_SCI6, + BSP_LOCK_SCI8, + BSP_LOCK_SCI9, + BSP_LOCK_SCI12, + BSP_LOCK_SYSTEM, + BSP_LOCK_TEMPS, + BSP_LOCK_TMR0, + BSP_LOCK_TMR1, + BSP_LOCK_TMR2, + BSP_LOCK_TMR3, + BSP_LOCK_TMR01, + BSP_LOCK_TMR23, + BSP_LOCK_SWINT, + BSP_NUM_LOCKS //This entry is not a valid lock. It is used for sizing g_bsp_Locks[] array below. Do not touch! +} mcu_lock_t; + +typedef struct +{ + /* The actual lock. int32_t is used because this is what the xchg() instruction takes as parameters. */ + int32_t lock; + + /* Could add a ID for locking and unlocking. In this could protect against any function being able to unlock. */ +} bsp_lock_t; + +/*********************************************************************************************************************** +Error checking +***********************************************************************************************************************/ +#if BSP_CFG_USER_LOCKING_ENABLED == 0 +#undef BSP_CFG_USER_LOCKING_TYPE +#define BSP_CFG_USER_LOCKING_TYPE bsp_lock_t +#else + #if !defined(BSP_CFG_USER_LOCKING_TYPE) + #error "R_BSP ERROR - If you are using your own locking mechanism then you must define BSP_CFG_USER_LOCKING_TYPE in r_bsp_config.h." + #endif +#endif + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ +extern BSP_CFG_USER_LOCKING_TYPE g_bsp_Locks[]; + +#endif /* MCU_LOCKS_H */ + diff --git a/drivers/rx/rdp/src/r_bsp/mcu/rx130/r_bsp_cpu.h b/drivers/rx/rdp/src/r_bsp/mcu/rx130/r_bsp_cpu.h new file mode 100644 index 00000000..563ca939 --- /dev/null +++ b/drivers/rx/rdp/src/r_bsp/mcu/rx130/r_bsp_cpu.h @@ -0,0 +1,98 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 - 2024 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_bsp_cpu.h +* Description : This module implements CPU specific functions. An example is enabling/disabling interrupts. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 01.12.2015 1.00 First Release +* : 15.05.2017 1.01 Changed comments of the following enumeration. +* - bsp_reg_protect_t +* : 28.02.2019 2.00 Added bsp_ram_initialize function. +* Fixed coding style. +* : 26.07.2019 2.01 Added R_BSP_SoftwareReset function. +* : 21.11.2023 2.02 Added bsp_bus_priority_initialize function. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef CPU_H +#define CPU_H + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ +/* The different types of registers that can be protected. */ +typedef enum +{ + /* PRC0 + Enables writing to the registers related to the clock generation circuit: SCKCR, SCKCR3, + PLLCR, PLLCR2, MOSCCR, SOSCCR, LOCOCR, ILOCOCR, HOCOCR, HOFCR, OSTDCR, OSTDSR, CKOCR, LOCOTRR, + ILOCOTRR, HOCOTRR0. */ + BSP_REG_PROTECT_CGC = 0, + + /* PRC1 + Enables writing to the registers related to operating modes, low power consumption, + the clock generation circuit, and software reset: SYSCR1, SBYCR, MSTPCRA, MSTPCRB, MSTPCRC, + MSTPCRD, OPCCR, RSTCKCR, SOPCCR, MOFCR, MOSCWTCR, SWRR. */ + BSP_REG_PROTECT_LPC_CGC_SWR, + + /* PRC2 + Enables writing to the registers related to the LPT: LPTCR1, LPTCR2, LPTCR3, LPTPRD, LPCMR0, LPWUCR. */ + BSP_REG_PROTECT_LPT, + + /* PRC3 + Enables writing to the registers related to the LVD: LVCMPCR, LVDLVLR, LVD1CR0, LVD1CR1, LVD1SR, LVD2CR0, + LVD2CR1, LVD2SR. */ + BSP_REG_PROTECT_LVD, + + /* MPC.PWPR + Enables writing to MPC's PFS registers. */ + BSP_REG_PROTECT_MPC, + + /* This entry is used for getting the number of enum items. This must be the last entry. DO NOT REMOVE THIS ENTRY!*/ + BSP_REG_PROTECT_TOTAL_ITEMS +} bsp_reg_protect_t; + +/*********************************************************************************************************************** +Exported global variables +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ +void R_BSP_InterruptsDisable(void); +void R_BSP_InterruptsEnable(void); +uint32_t R_BSP_CpuInterruptLevelRead(void); +bool R_BSP_CpuInterruptLevelWrite(uint32_t level); +void R_BSP_RegisterProtectEnable(bsp_reg_protect_t regs_to_protect); +void R_BSP_RegisterProtectDisable(bsp_reg_protect_t regs_to_unprotect); +void R_BSP_SoftwareReset(void); + +void bsp_register_protect_open(void); //r_bsp internal function. DO NOT CALL. +void bsp_ram_initialize(void); +#if BSP_CFG_BUS_PRIORITY_INITIALIZE_ENABLE == 1 +void bsp_bus_priority_initialize(void); +#endif + +#endif /* CPU_H */ + diff --git a/drivers/rx/rdp/src/r_gpio_rx/r_gpio_rx_if.h b/drivers/rx/rdp/src/r_gpio_rx/r_gpio_rx_if.h new file mode 100644 index 00000000..49a625de --- /dev/null +++ b/drivers/rx/rdp/src/r_gpio_rx/r_gpio_rx_if.h @@ -0,0 +1,297 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013-2024 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_gpio_rx_if.h +* Description : General Purpose I/O driver for RX MCUs. This interface file has everything the user needs to use this +* module. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 17.07.2013 1.00 First Release +* : 23.04.2014 1.20 Add support for RX63N, and RX110 +* : 28.05.2014 1.30 Add support for RX64M +* : 28.11.2014 1.40 Add support for RX113 +* : 02.09.2015 1.50 Add support for RX71M, increased the minor version number to 50. +* : Added GPIO_CMD_DSCR_DISABLE and GPIO_CMD_DSCR_ENABLE commands in gpio_cmd_t +* : 06.04.2015 1.60 Add support for RX231 +* : 30.09.2015 1.70 Add support for RX23T +* : 01.10.2015 1.80 Add support for RX130 +* : 01.12.2015 1.90 Add support for RX24T +* : 01.02.2016 2.00 Add support for RX230 +* : 15.06.2016 2.01 Added the demo of the RX64M group. +* : 01.10.2016 2.10 Add support for RX65N +* : 19.12.2016 2.20 Add support for RX24U, RX24T(512KB) +* : 21.07.2017 2.30 Add support for RX65N-2M, RX130-512KB +* : 31.10.2017 2.31 Added the demo for RX65N, RX65N-2M +* : 28.09.2018 2.40 Add support for RX66T +* : 16.11.2018 2.41 Added XML document number +* : 01.02.2019 2.50 Add support for RX72T, RX65N-64pin +* : 20.05.2019 3.00 Added support for GNUC and ICCRX. +* : 28.06.2019 3.10 Added support RX23W +* : 15.08.2019 3.20 Added support RX72M +* : 25.11.2019 3.30 Added support RX13T +* Removed support for Generation 1 devices. +* : 30.12.2019 3.40 Added support RX72N, RX66N +* : 31.03.2020 3.50 Added support for RX23E-A +* : 30.06.2020 3.60 Changed revision to reflect demo upgrade. +* : 15.01.2021 3.70 Removed PH7 for RX111, RX113. +* : 01.04.2021 3.80 Added support for RX23W 83pins +* : 01.04.2021 3.90 Added support for RX72M 144pins, 100pins +* : 07.04.2021 4.00 Added support for RX671. +* : 15.04.2021 4.10 Added support for RX140. +* : 13.09.2021 4.20 Added the demo for RX671. +* : 11.11.2021 4.30 Added support for RX140-256KB. +* : 14.03.2022 4.40 Added support for RX66T 48pins. +* : 31.03.2022 4.50 Added support for RX660. +* : 28.06.2022 4.60 Updated demo projects +* : 15.12.2022 4.70 Added P50 and P51 for RX66T and RX72T. +* Added PORTJ for RX110. +* Added PH7 for RX110 and RX111. +* Removed 112pins, 80pins, and 64pins package for RX72T. +* : 28.02.2023 4.80 Corrected PIN MASK value of PORTF and PORTJ for RX72N 145-pin and 144-pin. +* : 07.04.2023 4.90 Added support for RX26T. +* Fixed to comply with GSCE Coding Standards Rev.6.5.0. +* Updated P05 for RX671 64-pin and RX65N 64-pin. +* Updated P71 and P72 for RX671 145-pin and 144-pin. +* Updated PORT2, PORTB, and PORTD for RX66T 100-pin and RX72T 100-pin. +* Corrected PIN MASK value of PORT4 for RX110 40-pin. +* Corrected PIN MASK value of PORT4 for RX24T 64-pin. +* Corrected PIN MASK value of PORTF and PORTJ for RX66N 145-pin and 144-pin. +* Corrected PIN MASK value of PORT5 for RX66T 64-pin. +* Corrected the values of PORRT7, PORRT8, PORRT9, and PORRTJ +* in the g_gpio_open_drain_n_support structure for RX231. +* Corrected the values of PORRT5 in the g_gpio_pull_up_support and +* g_gpio_dscr_support structures for RX231. +* Corrected the value of PORRT3 in the g_gpio_open_drain_n_support, +* g_gpio_pull_up_support, and g_gpio_dscr_support structures for RX23T. +* Added P36 and P37 for RX23T 64-pin, 52-pin, and 48-pin. +* Corrected the value of GPIO_PORT_H_PIN_3 for RX660 144-pin, 100-pin, 80-pin, +* 64-pin, and 48-pin. +* Corrected the "Total of pins" for RX23T, RX24T, RX65N, and RX66T. +* Updated for RX65N (with products with 1 Mbyte of code flash memory or less) +* for the g_gpio_dscr_support and g_gpio_dscr2_support structures. +* Removed define PIN MASK is not provided for RX110, RX111, RX113, +* RX64M, RX65N, and RX71M. +* Removed common "gpio_port_t" structure and added "gpio_port_t" structure for RX110 +* 64-Pin, 48-Pin, 40-Pin, and 36-Pin. +* : 29.05.2023 5.00 Added support for RX23E-B. +***********************************************************************************************************************/ + +#ifndef GPIO_RX_INTERFACE_HEADER_FILE +#define GPIO_RX_INTERFACE_HEADER_FILE + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +/* Includes board and MCU related header files. */ +#include "platform.h" +/* Module configuration. */ +#include "r_gpio_rx_config.h" + +/* Include specifics for chosen MCU. Go to the header file for your MCU to see available ports and pins. */ +#if defined(BSP_MCU_RX113) + #include "./src/targets/rx113/r_gpio_rx113.h" +#elif defined(BSP_MCU_RX110) + #include "./src/targets/rx110/r_gpio_rx110.h" +#elif defined(BSP_MCU_RX111) + #include "./src/targets/rx111/r_gpio_rx111.h" +#elif defined(BSP_MCU_RX130) + #include "./src/targets/rx130/r_gpio_rx130.h" +#elif defined(BSP_MCU_RX13T) + #include "./src/targets/rx13t/r_gpio_rx13t.h" +#elif defined(BSP_MCU_RX140) + #include "./src/targets/rx140/r_gpio_rx140.h" +#elif defined(BSP_MCU_RX230) + #include "./src/targets/rx230/r_gpio_rx230.h" +#elif defined(BSP_MCU_RX231) + #include "./src/targets/rx231/r_gpio_rx231.h" +#elif defined(BSP_MCU_RX23T) + #include "./src/targets/rx23t/r_gpio_rx23t.h" +#elif defined(BSP_MCU_RX23W) + #include "./src/targets/rx23w/r_gpio_rx23w.h" +#elif defined(BSP_MCU_RX23E_A) + #include "./src/targets/rx23e-a/r_gpio_rx23e-a.h" +#elif defined(BSP_MCU_RX23E_B) + #include "./src/targets/rx23e-b/r_gpio_rx23e-b.h" +#elif defined(BSP_MCU_RX24T) + #include "./src/targets/rx24t/r_gpio_rx24t.h" +#elif defined(BSP_MCU_RX26T) + #include "./src/targets/rx26t/r_gpio_rx26t.h" +#elif defined(BSP_MCU_RX24U) + #include "./src/targets/rx24u/r_gpio_rx24u.h" +#elif defined(BSP_MCU_RX64M) + #include "./src/targets/rx64m/r_gpio_rx64m.h" +#elif defined(BSP_MCU_RX65N) + #include "./src/targets/rx65n/r_gpio_rx65n.h" +#elif defined(BSP_MCU_RX66T) + #include "./src/targets/rx66t/r_gpio_rx66t.h" +#elif defined(BSP_MCU_RX66N) + #include "./src/targets/rx66n/r_gpio_rx66n.h" +#elif defined(BSP_MCU_RX671) + #include "./src/targets/rx671/r_gpio_rx671.h" +#elif defined(BSP_MCU_RX660) + #include "./src/targets/rx660/r_gpio_rx660.h" +#elif defined(BSP_MCU_RX71M) + #include "./src/targets/rx71m/r_gpio_rx71m.h" +#elif defined(BSP_MCU_RX72T) + #include "./src/targets/rx72t/r_gpio_rx72t.h" +#elif defined(BSP_MCU_RX72M) + #include "./src/targets/rx72m/r_gpio_rx72m.h" +#elif defined(BSP_MCU_RX72N) + #include "./src/targets/rx72n/r_gpio_rx72n.h" +#else + #error "This MCU is not supported by the current r_gpio_rx module." +#endif + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +#if R_BSP_VERSION_MAJOR < 5 + #error "This module must use BSP module of Rev.5.00 or higher. Please use the BSP module of Rev.5.00 or higher." +#endif + +/* Version Number of API. */ +#define GPIO_RX_VERSION_MAJOR (5) +#define GPIO_RX_VERSION_MINOR (00) + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ +/* The gpio_port_t and gpio_port_pin_t enums are located in the 'targets' folder for each MCU. For example, to see + * these enums for a RX111 look at the following file: r_gpio_rx/src/targets/rx111/r_gpio_rx111.h + */ + +/* Levels that can be set and read for individual pins. */ +typedef enum +{ + GPIO_LEVEL_LOW = 0, + GPIO_LEVEL_HIGH +} gpio_level_t; + +/* Options that can be used with the R_GPIO_PortDirectionSet() and R_GPIO_PinDirectionSet() functions. */ +typedef enum +{ + GPIO_DIRECTION_INPUT = 0, + GPIO_DIRECTION_OUTPUT +} gpio_dir_t; + +/* Commands that can be used with the R_GPIO_PinControl() function. This list will vary depending on the MCU chosen. */ +typedef enum +{ + GPIO_CMD_OUT_CMOS = 0, + GPIO_CMD_OUT_OPEN_DRAIN_N_CHAN, + GPIO_CMD_OUT_OPEN_DRAIN_P_CHAN, + GPIO_CMD_IN_PULL_UP_DISABLE, + GPIO_CMD_IN_PULL_UP_ENABLE, + GPIO_CMD_ASSIGN_TO_PERIPHERAL, + GPIO_CMD_ASSIGN_TO_GPIO, + GPIO_CMD_DSCR_DISABLE, + GPIO_CMD_DSCR_ENABLE, + GPIO_CMD_DSCR2_DISABLE, + GPIO_CMD_DSCR2_ENABLE +} gpio_cmd_t; + +/* Function return type. */ +typedef enum +{ + GPIO_SUCCESS = 0, + GPIO_ERR_INVALID_MODE, // The mode specified cannot be applied to this pin + GPIO_ERR_INVALID_CMD // The input command is not supported +} gpio_err_t; + +/*********************************************************************************************************************** +Exported global variables +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ +/****************************************************************************** + * Function Name: R_GPIO_PortWrite + * Description : . + * Arguments : port + * : value + * Return Value : . + *****************************************************************************/ +void R_GPIO_PortWrite (gpio_port_t port, uint8_t value); + +/****************************************************************************** + * Function Name: R_GPIO_PortRead + * Description : . + * Argument : port + * Return Value : . + *****************************************************************************/ +uint8_t R_GPIO_PortRead (gpio_port_t port); + +/****************************************************************************** + * Function Name: R_GPIO_PortDirectionSet + * Description : . + * Arguments : port + * : dir + * : mask + * Return Value : . + *****************************************************************************/ +void R_GPIO_PortDirectionSet (gpio_port_t port, gpio_dir_t dir, uint8_t mask); + +/****************************************************************************** + * Function Name: R_GPIO_PinWrite + * Description : . + * Arguments : pin + * : level + * Return Value : . + *****************************************************************************/ +void R_GPIO_PinWrite (gpio_port_pin_t pin, gpio_level_t level); + +/****************************************************************************** + * Function Name: R_GPIO_PinRead + * Description : . + * Argument : pin + * Return Value : . + *****************************************************************************/ +gpio_level_t R_GPIO_PinRead (gpio_port_pin_t pin); + +/****************************************************************************** + * Function Name: R_GPIO_PinDirectionSet + * Description : . + * Arguments : pin + * : dir + * Return Value : . + *****************************************************************************/ +void R_GPIO_PinDirectionSet (gpio_port_pin_t pin, gpio_dir_t dir); + +/****************************************************************************** + * Function Name: R_GPIO_PinControl + * Description : . + * Arguments : pin + * : cmd + * Return Value : . + *****************************************************************************/ +gpio_err_t R_GPIO_PinControl (gpio_port_pin_t pin, gpio_cmd_t cmd); + +/****************************************************************************** + * Function Name: R_GPIO_GetVersion + * Description : . + * Return Value : . + *****************************************************************************/ +uint32_t R_GPIO_GetVersion (void); + +#endif /* GPIO_RX_INTERFACE_HEADER_FILE */ + + diff --git a/drivers/rx/rdp/src/r_gpio_rx/src/r_gpio_rx.c b/drivers/rx/rdp/src/r_gpio_rx/src/r_gpio_rx.c new file mode 100644 index 00000000..278dac71 --- /dev/null +++ b/drivers/rx/rdp/src/r_gpio_rx/src/r_gpio_rx.c @@ -0,0 +1,579 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013-2024 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_gpio_rx.c +* Description : General Purpose Input/Output driver for RX MCUs. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 17.07.2013 1.00 First Release +* : 21.11.2014 1.40 Added support for RX113 +* : 02.09.2015 1.50 Added support for RX71M +* : Modified R_GPIO_PinControl to accept GPIO_CMD_DSCR_ENABLE/_DISABLE commands. +* : 01.10.2016 2.10 Added support for RX65N +* : Modified R_GPIO_PinControl to accept GPIO_CMD_DSCR2_ENABLE/_DISABLE commands. +* : 19.12.2016 2.20 Added support for RX24U, RX24T(512KB) +* : 21.07.2017 2.30 Added support for RX65N-2M, RX130-512KB. +* : 28.09.2018 2.40 Added support for RX66T. +* Update according to GSCE Code Checker +* : 01.02.2019 2.50 Added support for RX72T, RX65N-64pin +* Update according to GSCE Code Checker +* : 20.05.2019 3.00 Added support for GNUC and ICCRX. +* : 28.06.2019 3.10 Added support RX23W +* : 15.08.2019 3.20 Added support RX72M +* : 25.11.2019 3.30 Added support RX13T +* Modified comment of API function to Doxygen style. +* : 30.12.2019 3.40 Added support RX72N, RX66N. +* : 15.04.2021 4.10 Updated Doxygen comment. +* : 11.11.2021 4.30 Update according to GSCE Code Checker 6.00 +* : 07.04.2023 4.90 Fixed to comply with GSCE Coding Standards Rev.6.5.0 +* : 29.05.2023 5.00 Fixed to comply with GSCE Coding Standards Rev.6.5.0 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +/* Includes board and MCU related header files. */ +#include "platform.h" +/* Public interface header file for this package. */ +#include "r_gpio_rx_if.h" +/* Configuration for this package. */ +#include "r_gpio_rx_config.h" + +/*********************************************************************************************************************** +* Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* Typedef definitions +***********************************************************************************************************************/ +/* Different pin output options. */ +typedef enum +{ + GPIO_PIN_OUT_CMOS = 0, + GPIO_PIN_OUT_OPEN_DRAIN_N_CHAN = 1, + GPIO_PIN_OUT_OPEN_DRAIN_P_CHAN = 2 +} gpio_pin_output_t; + +/*********************************************************************************************************************** +* Private global variables and functions +***********************************************************************************************************************/ +uint8_t volatile * gpio_port_addr_get (uint8_t volatile * base_addr, uint16_t index); +bool gpio_pin_function_check (uint8_t const * check_array, uint8_t port_number, uint8_t pin_number); +void gpio_set_output_type (gpio_port_pin_t pin, gpio_pin_output_t out_type); + +/*********************************************************************************************************************** +* Export global variables +***********************************************************************************************************************/ +#if (GPIO_CFG_PARAM_CHECKING_ENABLE == 1) + extern const uint8_t g_gpio_open_drain_n_support[]; + extern const uint8_t g_gpio_open_drain_p_support[]; + extern const uint8_t g_gpio_pull_up_support[]; + #if defined (GPIO_DSCR_IS_SUPPORTED) + extern const uint8_t g_gpio_dscr_support[]; + #endif + #if defined (GPIO_DSCR2_IS_SUPPORTED) + extern const uint8_t g_gpio_dscr2_support[]; + #endif +#endif + +/*********************************************************************************************************************** +* Function Name: R_GPIO_PortWrite +********************************************************************************************************************//** +* @brief This function writes the levels of all pins on a port. +* @param[in] port - Which port to write to. See Section 2.10.1, Ports. +* @param[in] value - The value to write to the port. Each bit corresponds to a pin on the port (e.g. bit 0 of value +* will be written to pin 0 on supplied port) +* @details The input value will be written to the specified port. Each bit in the value parameter corresponds to a pin +* on the port. For example, bit 7 of write value corresponds to pin 7, bit 6 corresponds to pin 6, and so forth. +* @note In the interest of performance, this function does not automatically check for non-existent pins when the +* port-wide write function is called. It is up to the user’s application to insure that only valid pins are written to. +* +*/ +void R_GPIO_PortWrite(gpio_port_t port, uint8_t value) +{ + uint8_t volatile * podr; + + /* PODR register addresses are incremental in memory starting with PORT0.PODR. Even if a port is not available + * on this MCU, the address is reserved. */ + /* Get register address. */ + podr = gpio_port_addr_get(GPIO_PRV_BASE_ADDR_OUTPUT, (uint16_t)port); + + /* Write to the selected port. */ + *podr = value; +} /* End of function R_GPIO_PortWrite */ + +/*********************************************************************************************************************** +* Function Name: R_GPIO_PortRead +********************************************************************************************************************//** +* @brief This function reads the levels of all pins on a port. +* @param[in] port - Which port to read. See Section 2.10.1, Ports. +* @return The value of the port. +* @details The specified port will be read, and the levels for all the pins will be returned. Each bit in the returned +* value corresponds to a pin on the port. For example, bit 7 of read value corresponds to pin 7, bit 6 corresponds to +* pin 6, and so forth. +*/ +uint8_t R_GPIO_PortRead(gpio_port_t port) +{ + /* PIDR register addresses are incremental in memory starting with PORT0.PIDR. Even if a port is not available + * on this MCU, the address is reserved. */ + + /* Read the selected port. */ + return (*gpio_port_addr_get(GPIO_PRV_BASE_ADDR_INPUT, (uint16_t)port)); +} /* End of function R_GPIO_PortRead */ + +/*********************************************************************************************************************** +* Function Name: R_GPIO_PortDirectionSet +********************************************************************************************************************//** +* @brief This function sets multiple pins on a port to inputs or outputs at once. +* @param[in] port - Which port to use. See Section 2.10.1, Ports. +* @param[in] dir - Which direction to use. See Section 2.10.5, Pin Direction. +* @param[in] mask - Mask of which pins to change. 1 = set direction, 0 = do not change. +* @details Multiple pins on a port can be set to inputs or outputs at once. Each bit in the mask parameter corresponds +* to a pin on the port. For example, bit 7 of mask corresponds to pin 7, bit 6 corresponds to pin 6, and so forth. +* If a bit is set to 1 then the corresponding pin will be changed to an input or output as specified by the dir +* parameter. If a bit is set to 0 then the direction of the pin will not be changed. +* @note This function does not allow the user to specify the use of special modes such as input pull-up resistors or +* open-drain outputs. To enable these modes use the R_GPIO_PinControl() function. +*/ +void R_GPIO_PortDirectionSet(gpio_port_t port, gpio_dir_t dir, uint8_t mask) +{ + uint8_t volatile * pdr; + + /* PDR register addresses are incremental in memory starting with PORT0.PDR. Even if a port is not available + * on this MCU, the address is reserved. */ + /* Get register address. */ + pdr = gpio_port_addr_get(GPIO_PRV_BASE_ADDR_DIRECTION, (uint16_t)port); + + /* Write to the selected register. & or | based on direction. */ + if (GPIO_DIRECTION_INPUT == dir) + { + /* Set value to port */ + *pdr = (uint8_t)((*pdr) & (~mask)); + } + else + { + /* Set value to port */ + *pdr = (uint8_t)((*pdr) | mask); + } +} /* End of function R_GPIO_PortDirectionSet */ + +/*********************************************************************************************************************** +* Function Name: R_GPIO_PinWrite +********************************************************************************************************************//** +* @brief This function sets the level of a pin. +* @param[in] pin - Which pin to use. See Section 2.10.2, Pins. +* @param[in] level - What level to set the pin to. +* @details Pins can either be set as high (‘1’) or low (‘0’). +*/ +void R_GPIO_PinWrite(gpio_port_pin_t pin, gpio_level_t level) +{ + uint8_t volatile * podr; + + /* PODR register addresses are incremental in memory starting with PORT0.PODR. Even if a port is not available + * on this MCU, the address is reserved. */ + /* Get register address. */ + podr = gpio_port_addr_get(GPIO_PRV_BASE_ADDR_OUTPUT, (uint16_t)pin); + + /* Write to the selected bit. & or | based on direction. */ + if (GPIO_LEVEL_LOW == level) + { + /* Set value to port */ + *podr = (uint8_t)((*podr) & (~(1 << (pin & 0x00FFu)))); + } + else + { + /* Set value to port */ + *podr = (uint8_t)((*podr) | (1 << (pin & 0x00FFu))); + } +} /* End of function R_GPIO_PinWrite */ + +/*********************************************************************************************************************** +* Function Name: R_GPIO_PinRead +********************************************************************************************************************//** +* @brief This function reads the level of a pin. +* @param[in] pin - Which pin to use. See Section 2.10.2, Pins. +* @return The level of the specified pin. +* @details The specified pin will be read and the level returned. +*/ +gpio_level_t R_GPIO_PinRead(gpio_port_pin_t pin) +{ + uint8_t volatile * pidr; + + /* PIDR register addresses are incremental in memory starting with PORT0.PODR. Even if a port is not available + * on this MCU, the address is reserved. */ + /* Get register address. */ + pidr = gpio_port_addr_get(GPIO_PRV_BASE_ADDR_INPUT, (uint16_t)pin); + + /* Mask to get the individual bit. */ + if (((*pidr) & (1 << (pin & 0x00FFu))) != 0) + { + return GPIO_LEVEL_HIGH; + } + else + { + return GPIO_LEVEL_LOW; + } +} /* End of function R_GPIO_PinRead */ + +/*********************************************************************************************************************** +* Function Name: R_GPIO_PinDirectionSet +********************************************************************************************************************//** +* @brief This function sets the direction (input/output) of a pin. +* @param[in] pin - Which pin to use. See Section 2.10.2, Pins. +* @param[in] dir - Which direction to use for this pin. See Section 2.10.5, Pin Direction. +* @details This function sets pins as inputs or outputs. For enabling other settings such as open-drain outputs or +* internal pull-ups see the R_GPIO_PinControl() function. +*/ +void R_GPIO_PinDirectionSet(gpio_port_pin_t pin, gpio_dir_t dir) +{ + uint8_t volatile * pdr; + + /* PDR register addresses are incremental in memory starting with PORT0.PDR. Even if a port is not available + * on this MCU, the address is reserved. */ + /* Get register address. */ + pdr = gpio_port_addr_get(GPIO_PRV_BASE_ADDR_DIRECTION, (uint16_t)pin); + + /* Write to the selected bit. & or | based on direction. */ + if (GPIO_DIRECTION_INPUT == dir) + { + /* Casting port address to uint8_t type + * and set value to port address */ + *pdr = (uint8_t)((*pdr) & (~(1 << (pin & 0x00FFu)))); + } + else + { + /* Casting port address to uint8_t type + * and set value to port address */ + *pdr = (uint8_t)((*pdr) | (1 << (pin & 0x00FFu))); + } +} /* End of function R_GPIO_PinDirectionSet */ + +/*********************************************************************************************************************** +* Function Name: R_GPIO_PinControl +********************************************************************************************************************//** +* @brief This function allows the user to control various settings of a pin. +* @param[in] pin -Which pin to use. See Section 2.10.2, Pins +* @param[in] cmd - Which command to execute for this pin. See Section 2.10.6, Control Commands for available commands. +* @retval [GPIO_SUCCESS] Successful; pin modified as specified by command. +* @retval [GPIO_ERR_INVALID_MODE] Error; this pin does not support the specified option. +* @retval [GPIO_ERR_INVALID_CMD] Error; the input command is not supported. +* @details Depending on the MCU, pins have various settings that can be configured other than the direction and +* output level. Some examples include enabling open-drain outputs, internal pull-ups, and changing drive capacity +* levels. These features vary per chip which means that the options for this function will also vary. +* @note User should not configure the DSCR bit corresponding to a pin whose drive capacity is fixed, otherwise +* GPIO_ERR_INVALID_MODE would be returned. +*/ +gpio_err_t R_GPIO_PinControl(gpio_port_pin_t pin, gpio_cmd_t cmd) +{ + gpio_err_t err; + uint8_t volatile * addr; + uint8_t pin_number; + +#if (GPIO_CFG_PARAM_CHECKING_ENABLE == 1) + uint8_t port_number; + + /* Get port number */ + port_number = (uint8_t)(pin >> 8); +#endif + + err = GPIO_SUCCESS; + + /* Get pin number */ + pin_number = (uint8_t)(pin & 0x00FFu); + + switch (cmd) + { + +#if defined (GPIO_DSCR_IS_SUPPORTED) + case GPIO_CMD_DSCR_ENABLE: + { +#if (GPIO_CFG_PARAM_CHECKING_ENABLE == 1) + if (false == gpio_pin_function_check(&g_gpio_dscr_support[0], port_number, pin_number)) + { + err = GPIO_ERR_INVALID_MODE; + break; + } +#endif + /* Get pin's address */ + addr = gpio_port_addr_get(GPIO_PRV_BASE_ADDR_DSCR, (uint16_t)pin); + + /* Get value at pin's address */ + *addr = (uint8_t)((*addr) | (1 << pin_number)); + break; + } + case GPIO_CMD_DSCR_DISABLE: + { +#if (GPIO_CFG_PARAM_CHECKING_ENABLE == 1) + if (false == gpio_pin_function_check(&g_gpio_dscr_support[0], port_number, pin_number)) + { + err = GPIO_ERR_INVALID_MODE; + break; + } +#endif + /* Get pin's address */ + addr = gpio_port_addr_get(GPIO_PRV_BASE_ADDR_DSCR, (uint16_t)pin); + + /* Get value at pin's address */ + *addr = (uint8_t)((*addr) & (~(1 << pin_number))); + break; + } +#endif /* defined GPIO_DSCR_IS_SUPPORTED */ +#if defined (GPIO_DSCR2_IS_SUPPORTED) + case GPIO_CMD_DSCR2_ENABLE: + { +#if (GPIO_CFG_PARAM_CHECKING_ENABLE == 1) + if (false == gpio_pin_function_check(&g_gpio_dscr2_support[0], port_number, pin_number)) + { + err = GPIO_ERR_INVALID_MODE; + break; + } +#endif + /* Get pin's address */ + addr = gpio_port_addr_get(GPIO_PRV_BASE_ADDR_DSCR2, (uint16_t)pin); + + /* Set value to pin */ + *addr = (uint8_t)((*addr) | (1 << pin_number)); + break; + } + + case GPIO_CMD_DSCR2_DISABLE: + { +#if (GPIO_CFG_PARAM_CHECKING_ENABLE == 1) + if (false == gpio_pin_function_check(&g_gpio_dscr2_support[0], port_number, pin_number)) + { + err = GPIO_ERR_INVALID_MODE; + break; + } +#endif + /* Get pin's address */ + addr = gpio_port_addr_get(GPIO_PRV_BASE_ADDR_DSCR2, (uint16_t)pin); + + /* Set value to pin */ + *addr = (uint8_t)((*addr) & (~(1 << pin_number))); + break; + } +#endif /* defined GPIO_DSCR2_IS_SUPPORTED */ + case GPIO_CMD_ASSIGN_TO_GPIO: + { + /* Get pin's address */ + addr = gpio_port_addr_get(GPIO_PRV_BASE_ADDR_MODE, (uint16_t)pin); + + /* Set value to pin */ + *addr = (uint8_t)((*addr) & (~(1 << pin_number))); + break; + } + + case GPIO_CMD_ASSIGN_TO_PERIPHERAL: + { + /* Get pin's address */ + addr = gpio_port_addr_get(GPIO_PRV_BASE_ADDR_MODE, (uint16_t)pin); + + /* Set value to pin */ + *addr = (uint8_t)((*addr) | (1 << pin_number)); + break; + } + + case GPIO_CMD_IN_PULL_UP_DISABLE: + { +#if (GPIO_CFG_PARAM_CHECKING_ENABLE == 1) + if (false == gpio_pin_function_check(&g_gpio_pull_up_support[0], port_number, pin_number)) + { + err = GPIO_ERR_INVALID_MODE; + break; + } +#endif + /* Get pin's address */ + addr = gpio_port_addr_get(GPIO_PRV_BASE_ADDR_PULL_UP, (uint16_t)pin); + + /* Set value to pin */ + *addr = (uint8_t)((*addr) & (~(1 << pin_number))); + break; + } + + case GPIO_CMD_IN_PULL_UP_ENABLE: + { +#if (GPIO_CFG_PARAM_CHECKING_ENABLE == 1) + if (false == gpio_pin_function_check(&g_gpio_pull_up_support[0], port_number, pin_number)) + { + err = GPIO_ERR_INVALID_MODE; + break; + } +#endif + /* Get pin's address */ + addr = gpio_port_addr_get(GPIO_PRV_BASE_ADDR_PULL_UP, (uint16_t)pin); + + /* Set value to pin */ + *addr = (uint8_t)((*addr) | (1 << pin_number)); + break; + } + + case GPIO_CMD_OUT_CMOS: + { + gpio_set_output_type(pin, GPIO_PIN_OUT_CMOS); + + break; + } + + case GPIO_CMD_OUT_OPEN_DRAIN_N_CHAN: + { +#if (GPIO_CFG_PARAM_CHECKING_ENABLE == 1) + if (false == gpio_pin_function_check(&g_gpio_open_drain_n_support[0], port_number, pin_number)) + { + err = GPIO_ERR_INVALID_MODE; + break; + } +#endif + + gpio_set_output_type(pin, GPIO_PIN_OUT_OPEN_DRAIN_N_CHAN); + + break; + } + case GPIO_CMD_OUT_OPEN_DRAIN_P_CHAN: + { +#if (GPIO_CFG_PARAM_CHECKING_ENABLE == 1) + if (false == gpio_pin_function_check(&g_gpio_open_drain_p_support[0], port_number, pin_number)) + { + err = GPIO_ERR_INVALID_MODE; + break; + } +#endif + gpio_set_output_type(pin, GPIO_PIN_OUT_OPEN_DRAIN_P_CHAN); + + break; + } + + default: + { + err = GPIO_ERR_INVALID_CMD; + break; + } + } + + return err; +} /* End of function R_GPIO_PinControl */ + +/*********************************************************************************************************************** +* Function Name: R_GPIO_GetVersion +********************************************************************************************************************//** +* @brief Returns the current version of this API. +* @return Version of this API. +* @details This function will return the version of the currently running API. The version number is encoded where +* the top 2 bytes are the major version number and the bottom 2 bytes are the minor version number. For example, +* Version 4.25 would be returned as 0x00040019. +*/ +uint32_t R_GPIO_GetVersion(void) +{ + /* These version macros are defined in r_gpio_rx_if.h. */ + return ((((uint32_t)GPIO_RX_VERSION_MAJOR) << 16) | (uint32_t)GPIO_RX_VERSION_MINOR); +} /* End of function R_GPIO_GetVersion */ + +/*********************************************************************************************************************** +* Function Name: gpio_port_addr_get +* Description : Get the address for a port register based on a base port register address. +* Arguments : base_addr - +* First port register of this type (e.g. &PORT0.PODR.BYTE) +* index - +* Index off the base. (e.g. for PORT4 it would be 0x0400) +* Return Value : Address of the register that was requested +***********************************************************************************************************************/ + +R_BSP_PRAGMA_INLINE (gpio_port_addr_get) +uint8_t volatile * gpio_port_addr_get(uint8_t volatile * base_addr, uint16_t index) +{ + /* Add port number to 'index' to correct register. */ + return (uint8_t volatile *)((((uint32_t)index >> 8) & 0x000000FFuL) + (uint32_t)base_addr); +} /* End of function gpio_port_addr_get */ + +#if (GPIO_CFG_PARAM_CHECKING_ENABLE == 1) +/*********************************************************************************************************************** +* Function Name: gpio_pin_function_check +* Description : Checks to see if a pin supports a certain function. +* Arguments : check_array - +* Which support array to use. +* port_number - +* Which port to use. +* pin_number - +* Which pin to use. +* Return Value : true - +* Functionality is supported on this pin. +* false - +* Functionality is not supported on this pin. +***********************************************************************************************************************/ +R_BSP_PRAGMA_INLINE (gpio_pin_function_check) +bool gpio_pin_function_check(uint8_t const * check_array, uint8_t port_number, uint8_t pin_number) +{ + if ((check_array[port_number] & (1 << pin_number)) != 0) + { + return true; + } + else + { + return false; + } +} /* End of function gpio_pin_function_check */ +#endif + +/*********************************************************************************************************************** +* Function Name: gpio_set_output_type +* Description : Configures pin output type (e.g. CMOS, open-drain) +* Arguments : pin - +* Which pin to change output type for +* out_type - +* What output type to use for this pin +* Return Value : None +***********************************************************************************************************************/ +void gpio_set_output_type(gpio_port_pin_t pin, gpio_pin_output_t out_type) +{ + uint8_t volatile * addr; + uint8_t pin_number; + uint8_t bit_offset; + + /* Get pin number */ + pin_number = (uint8_t)(pin & 0x00FFu); + + /* 'pin' is multiplied by 2 because the ODR0 and ODR1 registers are staggered. This means that PORT0.ODR0 + * and PORT1.ODR0 are separated by 2 bytes instead of 1 as with the other port registers. */ + addr = gpio_port_addr_get(GPIO_PRV_BASE_ADDR_OUT_TYPE, (uint16_t)(((uint16_t)pin) *2)); + + /* ODR bit fields are 2-bits a piece. This means bits 0-3 are in the 1st byte (ODR0) and bits 4-7 are in + * the 2nd byte (ODR1). + */ + if (pin_number > 3) + { + /* Bit field is in ODR1. Increment address by 1 for ODR1 register for this port. */ + addr += 1; + + /* Subtract 4 from pin number since pins 4-7 are stored in ODR1 which is an 8-bit register. + * Multiple pin number by 2 since each pin is represented by 2 bits. + */ + bit_offset = (uint8_t)((pin_number - 4) *2); + } + else + { + /* Multiple pin number by 2 since each pin is represented by 2 bits. */ + bit_offset = (uint8_t)(pin_number *2); + } + + /* Clear the bits we intend to change. */ + *addr = (uint8_t)((*addr) & (~(3 << bit_offset))); + + /* Set the bits again if needed. */ + *addr = (uint8_t)((*addr) | (((uint8_t)out_type) << bit_offset)); +} /* End of function gpio_set_output_type */ diff --git a/drivers/rx/rdp/src/r_gpio_rx/src/targets/rx130/r_gpio_rx130.c b/drivers/rx/rdp/src/r_gpio_rx/src/targets/rx130/r_gpio_rx130.c new file mode 100644 index 00000000..1cd457f7 --- /dev/null +++ b/drivers/rx/rdp/src/r_gpio_rx/src/targets/rx130/r_gpio_rx130.c @@ -0,0 +1,280 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015-2024 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_gpio_rx130.c +* Description : Data for r_gpio_rx driver specific to RX130. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 01.10.2015 1.00 First Release +* : 01.02.2016 2.00 Changed the value of "g_gpio_dscr_support" for PORTJ +* : 21.07.2017 2.30 Added support for RX130-512K +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +/* Includes board and MCU related header files. */ +#include "platform.h" + +#if defined(BSP_MCU_RX130) + +/* Public interface header file for this package. */ +#include "r_gpio_rx_if.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ +/* These arrays hold which pins have extra functionality. For example, not all pins have the option of enabling + * open-drain N-channel output instead of the default CMOS output. Each entry in the array corresponds to a port. + * Each bit in each entry corresponds to a pin on that port. If bit 3 of array entry [4] was set to 1 then that would + * mean that PORT 4 PIN 3 supported the feature that array represented. + * + * These arrays are only used when GPIO_CFG_PARAM_CHECKING_ENABLE is set to 1 (checking enabled). If you know that + * your code does not need to check the pins then you can set this macro to 0 and save a little execution time + * and ROM space. + * + * Note: These arrays are defined for the largest package part. For smaller packages where some pins do not exist, + * pin checking is filtered by the enumerated port_pin list for that package as defined in r_gpio_rx130.h. + */ + +#if (GPIO_CFG_PARAM_CHECKING_ENABLE == 1) + #if defined(BSP_MCU_RX130_512KB) //RX130-512K board support +const uint8_t g_gpio_cmos_support[GPIO_INFO_NUM_PORTS] = +{ + 0x00, //PORT0 None + 0xFC, //PORT1 P12 to P17 + 0xFF, //PORT2 P20 to P27 + 0xDF, //PORT3 P30 to P34, P36, P37 + 0x00, //PORT4 None + 0x00, //PORT5 None + 0x00, //PORT6 None + 0x00, //PORT7 None + 0x00, //PORT8 None + 0x00, //PORT9 None + 0xFF, //PORTA PA0 to PA7 + 0xFF, //PORTB PB0 to PB7 + 0xFF, //PORTC PC0 to PC7 + 0x0F, //PORTD PD0 to PD3 + 0x0F, //PORTE PE0 to PE3 + 0x00, //PORTF None + 0x00, //PORTG None + 0x00, //PORTH None + 0x08 //PORTJ PJ3 +}; + +const uint8_t g_gpio_open_drain_n_support[GPIO_INFO_NUM_PORTS] = +{ + 0x00, //PORT0 None + 0xFC, //PORT1 P12 to P17 + 0xCF, //PORT2 P20 to P23, P26, P27 + 0xDF, //PORT3 P30 to P34, P36, P37 + 0x00, //PORT4 None + 0x00, //PORT5 None + 0x00, //PORT6 None + 0x00, //PORT7 None + 0x00, //PORT8 None + 0x00, //PORT9 None + 0xFF, //PORTA PA0 to PA7 + 0xFF, //PORTB PB0 to PB7 + 0xFF, //PORTC PC0 to PC7 + 0x07, //PORTD PD0 to PD2 + 0x0F, //PORTE PE0 to PE3 + 0x00, //PORTF None + 0x00, //PORTG None + 0x00, //PORTH None + 0x08 //PORTJ PJ3 +}; + +const uint8_t g_gpio_open_drain_p_support[GPIO_INFO_NUM_PORTS] = +{ + 0x00, //PORT0 None + 0x00, //PORT1 None + 0x00, //PORT2 None + 0x00, //PORT3 None + 0x00, //PORT4 None + 0x00, //PORT5 None + 0x00, //PORT6 None + 0x00, //PORT7 None + 0x00, //PORT8 None + 0x00, //PORT9 None + 0x00, //PORTA None + 0x00, //PORTB None + 0x00, //PORTC None + 0x00, //PORTD None + 0x02, //PORTE PE1 + 0x00, //PORTF None + 0x00, //PORTG None + 0x00, //PORTH None + 0x00 //PORTJ None +}; + +const uint8_t g_gpio_pull_up_support[GPIO_INFO_NUM_PORTS] = +{ + 0xF8, //PORT0 P03 to P07 + 0xFC, //PORT1 P12 to P17 + 0xFF, //PORT2 P20 to P27 + 0xDF, //PORT3 P30 to P34, P36, P37 + 0xFF, //PORT4 P40 to P47 + 0x3F, //PORT5 P50 to P55 + 0x00, //PORT6 None + 0x00, //PORT7 None + 0x00, //PORT8 None + 0x00, //PORT9 None + 0xFF, //PORTA PA0 to PA7 + 0xFF, //PORTB PB0 to PB7 + 0xFF, //PORTC PC0 to PC7 + 0xFF, //PORTD PD0 to PD7 + 0xFF, //PORTE PE0 to PE7 + 0x00, //PORTF None + 0x00, //PORTG None + 0x0F, //PORTH PH0 to PH3 + 0xCA //PORTJ PJ1, PJ3, PJ6, PJ7 +}; + +const uint8_t g_gpio_dscr_support[GPIO_INFO_NUM_PORTS] = +{ + 0x00, //PORT0 None + 0xFC, //PORT1 P12 to P17 + 0xFF, //PORT2 P20 to P27 + 0x1F, //PORT3 P30 to P34 + 0x00, //PORT4 None + 0x3F, //PORT5 P50 to P55 + 0x00, //PORT6 None + 0x00, //PORT7 None + 0x00, //PORT8 None + 0x00, //PORT9 None + 0xFF, //PORTA PA0 to PA7 + 0xFF, //PORTB PB0 to PB7 + 0xFF, //PORTC PC0 to PC7 + 0xFF, //PORTD PD0 to PD7 + 0xFF, //PORTE PE0 to PE7 + 0x00, //PORTF None + 0x00, //PORTG None + 0x0F, //PORTH PH0 to PH3 + 0x0A, //PORTJ PJ1, PJ3 +}; + + #else //RX130 board support +const uint8_t g_gpio_open_drain_n_support[GPIO_INFO_NUM_PORTS] = +{ + 0x00, //PORT0 None + 0xFC, //PORT1 P12 to P17 + 0xC0, //PORT2 P26, P27 + 0xD7, //PORT3 P30 to P32, P34, P36, P37 + 0x00, //PORT4 None + 0x00, //PORT5 None + 0x00, //PORT6 None + 0x00, //PORT7 None + 0x00, //PORT8 None + 0x00, //PORT9 None + 0x7F, //PORTA PA0 to PA6 + 0x0F, //PORTB PB0 to PB3 + 0xFC, //PORTC PC2 to PC7 + 0x07, //PORTD PD0 to PD2 + 0x0F, //PORTE PE0 to PE3 + 0x00, //PORTF None + 0x00, //PORTG None + 0x00, //PORTH None + 0x00 //PORTJ None +}; + +const uint8_t g_gpio_open_drain_p_support[GPIO_INFO_NUM_PORTS] = +{ + 0x00, //PORT0 None + 0x00, //PORT1 None + 0x00, //PORT2 None + 0x00, //PORT3 None + 0x00, //PORT4 None + 0x00, //PORT5 None + 0x00, //PORT6 None + 0x00, //PORT7 None + 0x00, //PORT8 None + 0x00, //PORT9 None + 0x00, //PORTA None + 0x00, //PORTB None + 0x00, //PORTC None + 0x00, //PORTD None + 0x02, //PORTE PE1 + 0x00, //PORTF None + 0x00, //PORTG None + 0x00, //PORTH None + 0x00 //PORTJ None +}; + +const uint8_t g_gpio_pull_up_support[GPIO_INFO_NUM_PORTS] = +{ + 0xF8, //PORT0 P03 to P07 + 0xFC, //PORT1 P12 to P17 + 0xC3, //PORT2 P20, P21, P26, P27 + 0xD7, //PORT3 P30 to P32, P34, P36, P37 + 0xFF, //PORT4 P40 to P47 + 0x30, //PORT5 P54, P55 + 0x00, //PORT6 None + 0x00, //PORT7 None + 0x00, //PORT8 None + 0x00, //PORT9 None + 0x7F, //PORTA PA0 to PA6 + 0xFF, //PORTB PB0 to PB7 + 0xFC, //PORTC PC2 to PC7 + 0x07, //PORTD PD0 to PD2 + 0x3F, //PORTE PE0 to PE5 + 0x00, //PORTF None + 0x00, //PORTG None + 0x0F, //PORTH PH0 to PH3 + 0xC2 //PORTJ PJ1, PJ6, PJ7 +}; + +const uint8_t g_gpio_dscr_support[GPIO_INFO_NUM_PORTS] = +{ + 0x00, //PORT0 None + 0xFC, //PORT1 P12 to P17 + 0xC3, //PORT2 P20, P21, P26, P27 + 0x17, //PORT3 P30 to P32, P34 + 0x00, //PORT4 None + 0x30, //PORT5 P54, P55 + 0x00, //PORT6 None + 0x00, //PORT7 None + 0x00, //PORT8 None + 0x00, //PORT9 None + 0x7F, //PORTA PA0 to PA6 + 0xFF, //PORTB PB0 to PB7 + 0xFC, //PORTC PC2 to PC7 + 0x07, //PORTD PD0 to PD2 + 0x3F, //PORTE PE0 to PE5 + 0x00, //PORTF None + 0x00, //PORTG None + 0x0F, //PORTH PH0 to PH3 + 0x02, //PORTJ PJ1 +}; + + #endif + +#endif + +#endif + diff --git a/drivers/rx/rdp/src/r_gpio_rx/src/targets/rx130/r_gpio_rx130.h b/drivers/rx/rdp/src/r_gpio_rx/src/targets/rx130/r_gpio_rx130.h new file mode 100644 index 00000000..5bab99fb --- /dev/null +++ b/drivers/rx/rdp/src/r_gpio_rx/src/targets/rx130/r_gpio_rx130.h @@ -0,0 +1,499 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015-2024 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_gpio_rx130.h +* Description : Specifics for the r_gpio_rx driver for the RX130. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 01.10.2015 1.00 First Release +* : 21.07.2017 2.30 Added support for RX130-512K +***********************************************************************************************************************/ +#ifndef GPIO_RX130 +#define GPIO_RX130 + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +/* Includes board and MCU related header files. */ +#include "platform.h" +#if defined(BSP_MCU_RX130) //Prevents the compiler from finding multiple definitions of constant in this file. + +/* Configuration for this package. */ +#include "r_gpio_rx_config.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* General information about number of ports and pins on this device. */ +#define GPIO_INFO_NUM_PORTS (19) /* Includes PORTJ for proper indexing */ + +#if (BSP_PACKAGE_PINS == 100) + #define GPIO_INFO_NUM_PINS (89) +#elif (BSP_PACKAGE_PINS == 80) + #define GPIO_INFO_NUM_PINS (69) +#elif (BSP_PACKAGE_PINS == 64) + #define GPIO_INFO_NUM_PINS (53) +#elif (BSP_PACKAGE_PINS == 48) + #define GPIO_INFO_NUM_PINS (39) +#else + #error "r_gpio_rx does not have information about this RX130 package. Please update r_gpio_rx130.h" +#endif + +/* Base registers used for offsets on output data registers. */ +#define GPIO_PRV_BASE_ADDR_OUTPUT ((uint8_t volatile *)&PORT0.PODR.BYTE) +/* Base registers used for offsets on input data registers. */ +#define GPIO_PRV_BASE_ADDR_INPUT ((uint8_t volatile *)&PORT0.PIDR.BYTE) +/* Base registers used for offsets on direction registers. */ +#define GPIO_PRV_BASE_ADDR_DIRECTION ((uint8_t volatile *)&PORT0.PDR.BYTE) +/* Base registers used for offsets on mode registers. */ +#define GPIO_PRV_BASE_ADDR_MODE ((uint8_t volatile *)&PORT0.PMR.BYTE) +/* Base registers used for offsets on output type registers. */ +#define GPIO_PRV_BASE_ADDR_OUT_TYPE (((uint8_t volatile *)&PORT1.ODR0.BYTE)-2) +/* Base registers used for offsets on pull-up registers. */ +#define GPIO_PRV_BASE_ADDR_PULL_UP ((uint8_t volatile *)&PORT0.PCR.BYTE) +/* Base registers used for offsets on drive capacity control registers. */ +#define GPIO_PRV_BASE_ADDR_DSCR (((uint8_t volatile *)&PORT1.DSCR.BYTE)-1) + +#define GPIO_DSCR_IS_SUPPORTED //High-drive is supported for the RX130 + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +#if (BSP_PACKAGE_PINS == 100) +/* This enumerator has each available GPIO port on this MCU. This list will change depending on the MCU chosen. */ +typedef enum +{ + GPIO_PORT_0 = 0x0000, + GPIO_PORT_1 = 0x0100, + GPIO_PORT_2 = 0x0200, + GPIO_PORT_3 = 0x0300, + GPIO_PORT_4 = 0x0400, + GPIO_PORT_5 = 0x0500, + GPIO_PORT_A = 0x0A00, + GPIO_PORT_B = 0x0B00, + GPIO_PORT_C = 0x0C00, + GPIO_PORT_D = 0x0D00, + GPIO_PORT_E = 0x0E00, + GPIO_PORT_H = 0x1100, + GPIO_PORT_J = 0x1200 +} gpio_port_t; + +/* This enumerator has a bit mask for each available GPIO pin for the given port on this MCU. */ +typedef enum +{ + GPIO_PORT0_PIN_MASK = 0xF8, /* Available pins: P03 to P07 */ + GPIO_PORT1_PIN_MASK = 0xFC, /* Available pins: P12 to P17 */ + GPIO_PORT2_PIN_MASK = 0xFF, /* Available pins: P20 to P27 */ + GPIO_PORT3_PIN_MASK = 0xFF, /* Available pins: P30 to P37 */ + GPIO_PORT4_PIN_MASK = 0xFF, /* Available pins: P40 to P47 */ + GPIO_PORT5_PIN_MASK = 0x3F, /* Available pins: P50 to P55 */ + GPIO_PORTA_PIN_MASK = 0xFF, /* Available pins: PA0 to PA7 */ + GPIO_PORTB_PIN_MASK = 0xFF, /* Available pins: PB0 to PB7 */ + GPIO_PORTC_PIN_MASK = 0xFF, /* Available pins: PC0 to PC7 */ + GPIO_PORTD_PIN_MASK = 0xFF, /* Available pins: PD0 to PD7 */ + GPIO_PORTE_PIN_MASK = 0xFF, /* Available pins: PE0 to PE7 */ + GPIO_PORTH_PIN_MASK = 0x0F, /* Available pins: PH0 to PH3 */ + GPIO_PORTJ_PIN_MASK = 0xCA /* Available pins: PJ1, PJ3, PJ6, PJ7 */ +} gpio_pin_bit_mask_t; + +/* This enumerator has each available GPIO pin on this MCU. This list will change depending on the MCU chosen. */ +typedef enum +{ + GPIO_PORT_0_PIN_3 = 0x0003, + GPIO_PORT_0_PIN_4 = 0x0004, + GPIO_PORT_0_PIN_5 = 0x0005, + GPIO_PORT_0_PIN_6 = 0x0006, + GPIO_PORT_0_PIN_7 = 0x0007, + GPIO_PORT_1_PIN_2 = 0x0102, + GPIO_PORT_1_PIN_3 = 0x0103, + GPIO_PORT_1_PIN_4 = 0x0104, + GPIO_PORT_1_PIN_5 = 0x0105, + GPIO_PORT_1_PIN_6 = 0x0106, + GPIO_PORT_1_PIN_7 = 0x0107, + GPIO_PORT_2_PIN_0 = 0x0200, + GPIO_PORT_2_PIN_1 = 0x0201, + GPIO_PORT_2_PIN_2 = 0x0202, + GPIO_PORT_2_PIN_3 = 0x0203, + GPIO_PORT_2_PIN_4 = 0x0204, + GPIO_PORT_2_PIN_5 = 0x0205, + GPIO_PORT_2_PIN_6 = 0x0206, + GPIO_PORT_2_PIN_7 = 0x0207, + GPIO_PORT_3_PIN_0 = 0x0300, + GPIO_PORT_3_PIN_1 = 0x0301, + GPIO_PORT_3_PIN_2 = 0x0302, + GPIO_PORT_3_PIN_3 = 0x0303, + GPIO_PORT_3_PIN_4 = 0x0304, + GPIO_PORT_3_PIN_5 = 0x0305, + GPIO_PORT_3_PIN_6 = 0x0306, + GPIO_PORT_3_PIN_7 = 0x0307, + GPIO_PORT_4_PIN_0 = 0x0400, + GPIO_PORT_4_PIN_1 = 0x0401, + GPIO_PORT_4_PIN_2 = 0x0402, + GPIO_PORT_4_PIN_3 = 0x0403, + GPIO_PORT_4_PIN_4 = 0x0404, + GPIO_PORT_4_PIN_5 = 0x0405, + GPIO_PORT_4_PIN_6 = 0x0406, + GPIO_PORT_4_PIN_7 = 0x0407, + GPIO_PORT_5_PIN_0 = 0x0500, + GPIO_PORT_5_PIN_1 = 0x0501, + GPIO_PORT_5_PIN_2 = 0x0502, + GPIO_PORT_5_PIN_3 = 0x0503, + GPIO_PORT_5_PIN_4 = 0x0504, + GPIO_PORT_5_PIN_5 = 0x0505, + GPIO_PORT_A_PIN_0 = 0x0A00, + GPIO_PORT_A_PIN_1 = 0x0A01, + GPIO_PORT_A_PIN_2 = 0x0A02, + GPIO_PORT_A_PIN_3 = 0x0A03, + GPIO_PORT_A_PIN_4 = 0x0A04, + GPIO_PORT_A_PIN_5 = 0x0A05, + GPIO_PORT_A_PIN_6 = 0x0A06, + GPIO_PORT_A_PIN_7 = 0x0A07, + GPIO_PORT_B_PIN_0 = 0x0B00, + GPIO_PORT_B_PIN_1 = 0x0B01, + GPIO_PORT_B_PIN_2 = 0x0B02, + GPIO_PORT_B_PIN_3 = 0x0B03, + GPIO_PORT_B_PIN_4 = 0x0B04, + GPIO_PORT_B_PIN_5 = 0x0B05, + GPIO_PORT_B_PIN_6 = 0x0B06, + GPIO_PORT_B_PIN_7 = 0x0B07, + GPIO_PORT_C_PIN_0 = 0x0C00, + GPIO_PORT_C_PIN_1 = 0x0C01, + GPIO_PORT_C_PIN_2 = 0x0C02, + GPIO_PORT_C_PIN_3 = 0x0C03, + GPIO_PORT_C_PIN_4 = 0x0C04, + GPIO_PORT_C_PIN_5 = 0x0C05, + GPIO_PORT_C_PIN_6 = 0x0C06, + GPIO_PORT_C_PIN_7 = 0x0C07, + GPIO_PORT_D_PIN_0 = 0x0D00, + GPIO_PORT_D_PIN_1 = 0x0D01, + GPIO_PORT_D_PIN_2 = 0x0D02, + GPIO_PORT_D_PIN_3 = 0x0D03, + GPIO_PORT_D_PIN_4 = 0x0D04, + GPIO_PORT_D_PIN_5 = 0x0D05, + GPIO_PORT_D_PIN_6 = 0x0D06, + GPIO_PORT_D_PIN_7 = 0x0D07, + GPIO_PORT_E_PIN_0 = 0x0E00, + GPIO_PORT_E_PIN_1 = 0x0E01, + GPIO_PORT_E_PIN_2 = 0x0E02, + GPIO_PORT_E_PIN_3 = 0x0E03, + GPIO_PORT_E_PIN_4 = 0x0E04, + GPIO_PORT_E_PIN_5 = 0x0E05, + GPIO_PORT_E_PIN_6 = 0x0E06, + GPIO_PORT_E_PIN_7 = 0x0E07, + GPIO_PORT_H_PIN_0 = 0x1100, + GPIO_PORT_H_PIN_1 = 0x1101, + GPIO_PORT_H_PIN_2 = 0x1102, + GPIO_PORT_H_PIN_3 = 0x1103, + GPIO_PORT_J_PIN_1 = 0x1201, + GPIO_PORT_J_PIN_3 = 0x1203, + GPIO_PORT_J_PIN_6 = 0x1206, + GPIO_PORT_J_PIN_7 = 0x1207 +} gpio_port_pin_t; +#elif (BSP_PACKAGE_PINS == 80) +/* This enumerator has each available GPIO port on this MCU. This list will change depending on the MCU chosen. */ +typedef enum +{ + GPIO_PORT_0 = 0x0000, + GPIO_PORT_1 = 0x0100, + GPIO_PORT_2 = 0x0200, + GPIO_PORT_3 = 0x0300, + GPIO_PORT_4 = 0x0400, + GPIO_PORT_5 = 0x0500, + GPIO_PORT_A = 0x0A00, + GPIO_PORT_B = 0x0B00, + GPIO_PORT_C = 0x0C00, + GPIO_PORT_D = 0x0D00, + GPIO_PORT_E = 0x0E00, + GPIO_PORT_H = 0x1100, + GPIO_PORT_J = 0x1200 +} gpio_port_t; + +/* This enumerator has a bit mask for each available GPIO pin for the given port on this MCU. */ +typedef enum +{ + GPIO_PORT0_PIN_MASK = 0xF8, /* Available pins: P03 to P07 */ + GPIO_PORT1_PIN_MASK = 0xFC, /* Available pins: P12 to P17 */ + GPIO_PORT2_PIN_MASK = 0xC3, /* Available pins: P20, P21, P26, P27 */ + GPIO_PORT3_PIN_MASK = 0xF7, /* Available pins: P30 to P32, P34 to P37 */ + GPIO_PORT4_PIN_MASK = 0xFF, /* Available pins: P40 to P47 */ + GPIO_PORT5_PIN_MASK = 0x30, /* Available pins: P54, P55 */ + GPIO_PORTA_PIN_MASK = 0x7F, /* Available pins: PA0 to PA6 */ + GPIO_PORTB_PIN_MASK = 0xFF, /* Available pins: PB0 to PB7 */ + GPIO_PORTC_PIN_MASK = 0xFC, /* Available pins: PC2 to PC7 */ + GPIO_PORTD_PIN_MASK = 0x07, /* Available pins: PD0 to PD2 */ + GPIO_PORTE_PIN_MASK = 0x3F, /* Available pins: PE0 to PE5 */ + GPIO_PORTH_PIN_MASK = 0x0F, /* Available pins: PH0 to PH3 */ + GPIO_PORTJ_PIN_MASK = 0xC2 /* Available pins: PJ1, PJ6, PJ7 */ +} gpio_pin_bit_mask_t; + +/* This enumerator has each available GPIO pin on this MCU. This list will change depending on the MCU chosen. */ +typedef enum +{ + GPIO_PORT_0_PIN_3 = 0x0003, + GPIO_PORT_0_PIN_4 = 0x0004, + GPIO_PORT_0_PIN_5 = 0x0005, + GPIO_PORT_0_PIN_6 = 0x0006, + GPIO_PORT_0_PIN_7 = 0x0007, + GPIO_PORT_1_PIN_2 = 0x0102, + GPIO_PORT_1_PIN_3 = 0x0103, + GPIO_PORT_1_PIN_4 = 0x0104, + GPIO_PORT_1_PIN_5 = 0x0105, + GPIO_PORT_1_PIN_6 = 0x0106, + GPIO_PORT_1_PIN_7 = 0x0107, + GPIO_PORT_2_PIN_0 = 0x0200, + GPIO_PORT_2_PIN_1 = 0x0201, + GPIO_PORT_2_PIN_6 = 0x0206, + GPIO_PORT_2_PIN_7 = 0x0207, + GPIO_PORT_3_PIN_0 = 0x0300, + GPIO_PORT_3_PIN_1 = 0x0301, + GPIO_PORT_3_PIN_2 = 0x0302, + GPIO_PORT_3_PIN_4 = 0x0304, + GPIO_PORT_3_PIN_5 = 0x0305, + GPIO_PORT_3_PIN_6 = 0x0306, + GPIO_PORT_3_PIN_7 = 0x0307, + GPIO_PORT_4_PIN_0 = 0x0400, + GPIO_PORT_4_PIN_1 = 0x0401, + GPIO_PORT_4_PIN_2 = 0x0402, + GPIO_PORT_4_PIN_3 = 0x0403, + GPIO_PORT_4_PIN_4 = 0x0404, + GPIO_PORT_4_PIN_5 = 0x0405, + GPIO_PORT_4_PIN_6 = 0x0406, + GPIO_PORT_4_PIN_7 = 0x0407, + GPIO_PORT_5_PIN_4 = 0x0504, + GPIO_PORT_5_PIN_5 = 0x0505, + GPIO_PORT_A_PIN_0 = 0x0A00, + GPIO_PORT_A_PIN_1 = 0x0A01, + GPIO_PORT_A_PIN_2 = 0x0A02, + GPIO_PORT_A_PIN_3 = 0x0A03, + GPIO_PORT_A_PIN_4 = 0x0A04, + GPIO_PORT_A_PIN_5 = 0x0A05, + GPIO_PORT_A_PIN_6 = 0x0A06, + GPIO_PORT_B_PIN_0 = 0x0B00, + GPIO_PORT_B_PIN_1 = 0x0B01, + GPIO_PORT_B_PIN_2 = 0x0B02, + GPIO_PORT_B_PIN_3 = 0x0B03, + GPIO_PORT_B_PIN_4 = 0x0B04, + GPIO_PORT_B_PIN_5 = 0x0B05, + GPIO_PORT_B_PIN_6 = 0x0B06, + GPIO_PORT_B_PIN_7 = 0x0B07, + GPIO_PORT_C_PIN_2 = 0x0C02, + GPIO_PORT_C_PIN_3 = 0x0C03, + GPIO_PORT_C_PIN_4 = 0x0C04, + GPIO_PORT_C_PIN_5 = 0x0C05, + GPIO_PORT_C_PIN_6 = 0x0C06, + GPIO_PORT_C_PIN_7 = 0x0C07, + GPIO_PORT_D_PIN_0 = 0x0D00, + GPIO_PORT_D_PIN_1 = 0x0D01, + GPIO_PORT_D_PIN_2 = 0x0D02, + GPIO_PORT_E_PIN_0 = 0x0E00, + GPIO_PORT_E_PIN_1 = 0x0E01, + GPIO_PORT_E_PIN_2 = 0x0E02, + GPIO_PORT_E_PIN_3 = 0x0E03, + GPIO_PORT_E_PIN_4 = 0x0E04, + GPIO_PORT_E_PIN_5 = 0x0E05, + GPIO_PORT_H_PIN_0 = 0x1100, + GPIO_PORT_H_PIN_1 = 0x1101, + GPIO_PORT_H_PIN_2 = 0x1102, + GPIO_PORT_H_PIN_3 = 0x1103, + GPIO_PORT_J_PIN_1 = 0x1201, + GPIO_PORT_J_PIN_6 = 0x1206, + GPIO_PORT_J_PIN_7 = 0x1207 +} gpio_port_pin_t; + +#elif (BSP_PACKAGE_PINS == 64) +/* This enumerator has each available GPIO port on this MCU. This list will change depending on the MCU chosen. */ +typedef enum +{ + GPIO_PORT_0 = 0x0000, + GPIO_PORT_1 = 0x0100, + GPIO_PORT_2 = 0x0200, + GPIO_PORT_3 = 0x0300, + GPIO_PORT_4 = 0x0400, + GPIO_PORT_5 = 0x0500, + GPIO_PORT_A = 0x0A00, + GPIO_PORT_B = 0x0B00, + GPIO_PORT_C = 0x0C00, + GPIO_PORT_E = 0x0E00, + GPIO_PORT_H = 0x1100, + GPIO_PORT_J = 0x1200 +} gpio_port_t; + +/* This enumerator has a bit mask for each available GPIO pin for the given port on this MCU. */ +typedef enum +{ + GPIO_PORT0_PIN_MASK = 0x28, /* Available pins: P03, P05 */ + GPIO_PORT1_PIN_MASK = 0xF0, /* Available pins: P14 to P17 */ + GPIO_PORT2_PIN_MASK = 0xC0, /* Available pins: P26, P27 */ + GPIO_PORT3_PIN_MASK = 0xE7, /* Available pins: P30 to P32, P35 to P37 */ + GPIO_PORT4_PIN_MASK = 0xFF, /* Available pins: P40 to P47 */ + GPIO_PORT5_PIN_MASK = 0x30, /* Available pins: P54, P55 */ + GPIO_PORTA_PIN_MASK = 0x5B, /* Available pins: PA0, PA1, PA3, PA4, PA6 */ + GPIO_PORTB_PIN_MASK = 0xEB, /* Available pins: PB0, PB1, PB3, PB5 to PB7 */ + GPIO_PORTC_PIN_MASK = 0xFC, /* Available pins: PC2 to PC7 */ + GPIO_PORTE_PIN_MASK = 0x3F, /* Available pins: PE0 to PE5 */ + GPIO_PORTH_PIN_MASK = 0x0F, /* Available pins: PH0 to PH3 */ + GPIO_PORTJ_PIN_MASK = 0xC0 /* Available pins: PJ6, PJ7 */ +} gpio_pin_bit_mask_t; + +/* This enumerator has each available GPIO pin on this MCU. This list will change depending on the MCU chosen. */ +typedef enum +{ + GPIO_PORT_0_PIN_3 = 0x0003, + GPIO_PORT_0_PIN_5 = 0x0005, + GPIO_PORT_1_PIN_4 = 0x0104, + GPIO_PORT_1_PIN_5 = 0x0105, + GPIO_PORT_1_PIN_6 = 0x0106, + GPIO_PORT_1_PIN_7 = 0x0107, + GPIO_PORT_2_PIN_6 = 0x0206, + GPIO_PORT_2_PIN_7 = 0x0207, + GPIO_PORT_3_PIN_0 = 0x0300, + GPIO_PORT_3_PIN_1 = 0x0301, + GPIO_PORT_3_PIN_2 = 0x0302, + GPIO_PORT_3_PIN_5 = 0x0305, + GPIO_PORT_3_PIN_6 = 0x0306, + GPIO_PORT_3_PIN_7 = 0x0307, + GPIO_PORT_4_PIN_0 = 0x0400, + GPIO_PORT_4_PIN_1 = 0x0401, + GPIO_PORT_4_PIN_2 = 0x0402, + GPIO_PORT_4_PIN_3 = 0x0403, + GPIO_PORT_4_PIN_4 = 0x0404, + GPIO_PORT_4_PIN_5 = 0x0405, + GPIO_PORT_4_PIN_6 = 0x0406, + GPIO_PORT_4_PIN_7 = 0x0407, + GPIO_PORT_5_PIN_4 = 0x0504, + GPIO_PORT_5_PIN_5 = 0x0505, + GPIO_PORT_A_PIN_0 = 0x0A00, + GPIO_PORT_A_PIN_1 = 0x0A01, + GPIO_PORT_A_PIN_3 = 0x0A03, + GPIO_PORT_A_PIN_4 = 0x0A04, + GPIO_PORT_A_PIN_6 = 0x0A06, + GPIO_PORT_B_PIN_0 = 0x0B00, + GPIO_PORT_B_PIN_1 = 0x0B01, + GPIO_PORT_B_PIN_3 = 0x0B03, + GPIO_PORT_B_PIN_5 = 0x0B05, + GPIO_PORT_B_PIN_6 = 0x0B06, + GPIO_PORT_B_PIN_7 = 0x0B07, + GPIO_PORT_C_PIN_2 = 0x0C02, + GPIO_PORT_C_PIN_3 = 0x0C03, + GPIO_PORT_C_PIN_4 = 0x0C04, + GPIO_PORT_C_PIN_5 = 0x0C05, + GPIO_PORT_C_PIN_6 = 0x0C06, + GPIO_PORT_C_PIN_7 = 0x0C07, + GPIO_PORT_E_PIN_0 = 0x0E00, + GPIO_PORT_E_PIN_1 = 0x0E01, + GPIO_PORT_E_PIN_2 = 0x0E02, + GPIO_PORT_E_PIN_3 = 0x0E03, + GPIO_PORT_E_PIN_4 = 0x0E04, + GPIO_PORT_E_PIN_5 = 0x0E05, + GPIO_PORT_H_PIN_0 = 0x1100, + GPIO_PORT_H_PIN_1 = 0x1101, + GPIO_PORT_H_PIN_2 = 0x1102, + GPIO_PORT_H_PIN_3 = 0x1103, + GPIO_PORT_J_PIN_6 = 0x1206, + GPIO_PORT_J_PIN_7 = 0x1207 +} gpio_port_pin_t; + +#elif (BSP_PACKAGE_PINS == 48) +/* This enumerator has each available GPIO port on this MCU. This list will change depending on the MCU chosen. */ +typedef enum +{ + GPIO_PORT_1 = 0x0100, + GPIO_PORT_2 = 0x0200, + GPIO_PORT_3 = 0x0300, + GPIO_PORT_4 = 0x0400, + GPIO_PORT_A = 0x0A00, + GPIO_PORT_B = 0x0B00, + GPIO_PORT_C = 0x0C00, + GPIO_PORT_E = 0x0E00, + GPIO_PORT_H = 0x1100, + GPIO_PORT_J = 0x1200 +} gpio_port_t; + +/* This enumerator has a bit mask for each available GPIO pin for the given port on this MCU. */ +typedef enum +{ + GPIO_PORT1_PIN_MASK = 0xF0, /* Available pins: P14 to P17 */ + GPIO_PORT2_PIN_MASK = 0xC0, /* Available pins: P26, P27 */ + GPIO_PORT3_PIN_MASK = 0xE3, /* Available pins: P30, P31, P35 to P37 */ + GPIO_PORT4_PIN_MASK = 0xE7, /* Available pins: P40 to P42, P45 to P47 */ + GPIO_PORTA_PIN_MASK = 0x5A, /* Available pins: PA1, PA3, PA4, PA6 */ + GPIO_PORTB_PIN_MASK = 0x2B, /* Available pins: PB0, PB1, PB3, PB5 */ + GPIO_PORTC_PIN_MASK = 0xF0, /* Available pins: PC4 to PC7 */ + GPIO_PORTE_PIN_MASK = 0x1E, /* Available pins: PE1 to PE4 */ + GPIO_PORTH_PIN_MASK = 0x0F, /* Available pins: PH0 to PH3 */ + GPIO_PORTJ_PIN_MASK = 0xC0 /* Available pins: PJ6, PJ7 */ +} gpio_pin_bit_mask_t; + +/* This enumerator has each available GPIO pin on this MCU. This list will change depending on the MCU chosen. */ +typedef enum +{ + GPIO_PORT_1_PIN_4 = 0x0104, + GPIO_PORT_1_PIN_5 = 0x0105, + GPIO_PORT_1_PIN_6 = 0x0106, + GPIO_PORT_1_PIN_7 = 0x0107, + GPIO_PORT_2_PIN_6 = 0x0206, + GPIO_PORT_2_PIN_7 = 0x0207, + GPIO_PORT_3_PIN_0 = 0x0300, + GPIO_PORT_3_PIN_1 = 0x0301, + GPIO_PORT_3_PIN_5 = 0x0305, + GPIO_PORT_3_PIN_6 = 0x0306, + GPIO_PORT_3_PIN_7 = 0x0307, + GPIO_PORT_4_PIN_0 = 0x0400, + GPIO_PORT_4_PIN_1 = 0x0401, + GPIO_PORT_4_PIN_2 = 0x0402, + GPIO_PORT_4_PIN_5 = 0x0405, + GPIO_PORT_4_PIN_6 = 0x0406, + GPIO_PORT_4_PIN_7 = 0x0407, + GPIO_PORT_A_PIN_1 = 0x0A01, + GPIO_PORT_A_PIN_3 = 0x0A03, + GPIO_PORT_A_PIN_4 = 0x0A04, + GPIO_PORT_A_PIN_6 = 0x0A06, + GPIO_PORT_B_PIN_0 = 0x0B00, + GPIO_PORT_B_PIN_1 = 0x0B01, + GPIO_PORT_B_PIN_3 = 0x0B03, + GPIO_PORT_B_PIN_5 = 0x0B05, + GPIO_PORT_C_PIN_4 = 0x0C04, + GPIO_PORT_C_PIN_5 = 0x0C05, + GPIO_PORT_C_PIN_6 = 0x0C06, + GPIO_PORT_C_PIN_7 = 0x0C07, + GPIO_PORT_E_PIN_1 = 0x0E01, + GPIO_PORT_E_PIN_2 = 0x0E02, + GPIO_PORT_E_PIN_3 = 0x0E03, + GPIO_PORT_E_PIN_4 = 0x0E04, + GPIO_PORT_H_PIN_0 = 0x1100, + GPIO_PORT_H_PIN_1 = 0x1101, + GPIO_PORT_H_PIN_2 = 0x1102, + GPIO_PORT_H_PIN_3 = 0x1103, + GPIO_PORT_J_PIN_6 = 0x1206, + GPIO_PORT_J_PIN_7 = 0x1207 +} gpio_port_pin_t; +#endif + +/*********************************************************************************************************************** +Exported global variables +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ + +#endif /* BSP_MCU_RX130 */ +#endif /* GPIO_RX130 */ diff --git a/zephyr/rx/rdp_cfg/r_config/r_gpio_rx_config.h b/zephyr/rx/rdp_cfg/r_config/r_gpio_rx_config.h new file mode 100644 index 00000000..f3f9bfc3 --- /dev/null +++ b/zephyr/rx/rdp_cfg/r_config/r_gpio_rx_config.h @@ -0,0 +1,47 @@ +/* Generated configuration header file - do not edit */ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013 - 2024 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_gpio_rx_config.h +* Description : Configures the GPIO module. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 17.07.2013 1.00 First Release +***********************************************************************************************************************/ +#ifndef GPIO_RX_CONFIG_HEADER_FILE +#define GPIO_RX_CONFIG_HEADER_FILE + +/*********************************************************************************************************************** +Configuration Options +***********************************************************************************************************************/ +/* SPECIFY WHETHER TO INCLUDE CODE FOR API PARAMETER CHECKING + Available settings: + BSP_CFG_PARAM_CHECKING_ENABLE: + Utilizes the system default setting + 1: + Includes parameter checking + 0: + Compiles out parameter checking +*/ +#define GPIO_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#endif /* GPIO_RX_CONFIG_HEADER_FILE */ + + From 645987f8baf68251aa9fbf011620a149f2323944 Mon Sep 17 00:00:00 2001 From: Phi Tran Date: Tue, 10 Sep 2024 17:58:20 +0700 Subject: [PATCH 3/9] drivers: pinctrl: Initial support pinctrl driver on RSK_RX130_512KB Initial commit for PINCTRL driver support on board using RX130 MCUs Signed-off-by: Phi Tran --- drivers/rx/CMakeLists.txt | 7 + drivers/rx/rdp/src/r_mpc_rx/r_mpc_rx_if.h | 142 +++++++++++ drivers/rx/rdp/src/r_mpc_rx/src/r_mpc_rx.c | 225 ++++++++++++++++++ zephyr/rx/rdp_cfg/r_config/r_gpio_rx_config.h | 2 +- zephyr/rx/rdp_cfg/r_config/r_mpc_rx_config.h | 46 ++++ 5 files changed, 421 insertions(+), 1 deletion(-) create mode 100644 drivers/rx/rdp/src/r_mpc_rx/r_mpc_rx_if.h create mode 100644 drivers/rx/rdp/src/r_mpc_rx/src/r_mpc_rx.c create mode 100644 zephyr/rx/rdp_cfg/r_config/r_mpc_rx_config.h diff --git a/drivers/rx/CMakeLists.txt b/drivers/rx/CMakeLists.txt index cd7221cb..d376684f 100644 --- a/drivers/rx/CMakeLists.txt +++ b/drivers/rx/CMakeLists.txt @@ -32,3 +32,10 @@ if(CONFIG_USE_RX_RDP_GPIO) ) zephyr_include_directories(rdp/src/r_gpio_rx) endif() + +if(CONFIG_USE_RX_RDP_MPC) + zephyr_library_sources( + rdp/src/r_mpc_rx/src/r_mpc_rx.c + ) + zephyr_include_directories(rdp/src/r_mpc_rx) +endif() diff --git a/drivers/rx/rdp/src/r_mpc_rx/r_mpc_rx_if.h b/drivers/rx/rdp/src/r_mpc_rx/r_mpc_rx_if.h new file mode 100644 index 00000000..60d870cc --- /dev/null +++ b/drivers/rx/rdp/src/r_mpc_rx/r_mpc_rx_if.h @@ -0,0 +1,142 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013-2024 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_mpc_rx_if.h +* Description : Multi-Function Pin Controller (MPC) driver. This module uses pin definitions from the r_gpio_rx module +* to allow users to easily control pin functionality. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 17.07.2013 1.00 First Release +* : 24.04.2014 1.20 Replaced inclusion of stdint.h and stdbool.h with platform.h +* : 13.06.2014 1.30 Added support for RX64M +* : 04.12.2014 1.40 Added support for RX113 +* : 02.19.2015 1.50 Added support for RX71M +* : 29.04.2015 1.60 Added support for RX231 +* : 30.09.2015 1.70 Added support for RX23T +* : 01.10.2015 1.80 Added support for RX130 +* : 01.12.2015 1.90 Added support for RX24T +* : 01.02.2016 2.00 Added support for RX230 +* : 15.03.2016 2.10 Added support for RX65N +* : 19.12.2016 2.20 Added support for RX24U, RX24T(512KB) +* : 21.07.2017 2.30 Added support for the RX65N-2M, RX130-512KB. +*         : 31.10.2017 2.31    Added the demo for RX65N, RX65N-2M +* : 28.09.2018 2.40 Added support for RX66T +* : 16.11.2018 2.41 Added XML document number +* : 01.02.2019 2.50 Added support for RX72T, RX65N-64pin +* : 20.05.2019 3.00 Added support for GNUC and ICCRX. +* : 28.06.2019 3.10 Added support RX23W +* : 15.08.2019 3.20 Added support RX72M +* : 25.11.2019 3.30 Added support RX13T +* : 30.12.2019 3.40 Added support RX72N, RX66N +* : 31.03.2020 3.50 Added support RX23E-A +* : 30.06.2020 3.60 Changed revision to reflect demo upgrade. +* : 01.04.2021 3.70 Added support RX23W-83pins +* : 01.04.2021 3.80 Added support RX72M 144pins, 100pins. +* : 07.04.2021 3.90 Added support RX671. +* : 15.04.2021 4.00 Added support RX140. +* : 13.09.2021 4.10 Added the demo for RX671. +* : 11.11.2021 4.20 Added support for RX140-256KB. +* : 14.03.2022 4.30 Added support for RX66T 48pins. +* : 31.03.2022 4.40 Added support for RX660. +* : 28.06.2022 4.50 Updated demo projects. +* : 15.12.2022 4.60 Updated dependency module version. +* : 28.02.2023 4.70 Updated dependency module version. +* : 07.04.2023 4.80 Added support for RX26T. +* Fixed to comply with GSCE Coding Standards Rev.6.5.0 +* Updated dependency module version. +* : 29.05.2023 4.90 Added support for RX23E-B. +* Fixed to comply with GSCE Coding Standards Rev.6.5.0 +***********************************************************************************************************************/ + +#ifndef MPC_RX_INTERFACE_HEADER_FILE +#define MPC_RX_INTERFACE_HEADER_FILE + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +/* MCU specific platform support, and C lib includes. */ +#include "platform.h" +/* r_gpio_rx module is required for getting pin definitions. */ +#include "r_gpio_rx_if.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +#if R_BSP_VERSION_MAJOR < 5 + #error "This module must use BSP module of Rev.5.00 or higher. Please use the BSP module of Rev.5.00 or higher." +#endif + +/* Version Number of API. */ +#define MPC_RX_VERSION_MAJOR (4) +#define MPC_RX_VERSION_MINOR (90) + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ +/* Options for configuring the MPC register of a pin. To find valid settings for pin_function, refer to the + * Multi-Function Pin Controller (MPC) section of your MCU's hardware manual. Select the Pin Function Control Register + * for the port that your pin is on. On this page you will find a table with available functions for each pin on the + * selected port. */ +typedef struct +{ + uint8_t pin_function; // Assigns a peripheral function to this pin. + bool irq_enable; // Enables a pin to be used as an IRQ pin. + bool analog_enable; // Enables a pin to be used as an ADC input, DAC output, or for LVD (CMPA2) +} mpc_config_t; + +/* Function return type. */ +typedef enum +{ + MPC_SUCCESS = 0, + MPC_ERR_INVALID_CFG // The configuration specified cannot be applied to this pin +} mpc_err_t; + +/*********************************************************************************************************************** +Exported global functions (to be accessed by other files) +***********************************************************************************************************************/ +/****************************************************************************** + * Function Name: R_MPC_Write + * Description : . + * Arguments : pin + * : pconfig + * Return Value : . + *****************************************************************************/ +mpc_err_t R_MPC_Write (gpio_port_pin_t pin, mpc_config_t * pconfig); + +/****************************************************************************** + * Function Name: R_MPC_Read + * Description : . + * Arguments : pin + * : pconfig + * Return Value : . + *****************************************************************************/ +void R_MPC_Read (gpio_port_pin_t pin, mpc_config_t * pconfig); + +/****************************************************************************** + * Function Name: R_MPC_GetVersion + * Description : . + * Return Value : . + *****************************************************************************/ +uint32_t R_MPC_GetVersion (void); + +#endif /* MPC_RX_INTERFACE_HEADER_FILE */ + + diff --git a/drivers/rx/rdp/src/r_mpc_rx/src/r_mpc_rx.c b/drivers/rx/rdp/src/r_mpc_rx/src/r_mpc_rx.c new file mode 100644 index 00000000..0bcc7b78 --- /dev/null +++ b/drivers/rx/rdp/src/r_mpc_rx/src/r_mpc_rx.c @@ -0,0 +1,225 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013-2024 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_mpc_rx.c +* Description : Multi-Function Pin Controller (MPC) driver. This module uses pin definitions from the r_gpio_rx module +* to allow users to easily control pin functionality. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 17.07.2013 1.00 First Release +* : 24.04.2014 1.20 Changed method of calculating PFS base register to make it compatible with more MCUs +* : 13.06.2014 1.30 Removed unused pfs_reg_t typedef +* : 04.12.2014 1.40 Added support for RX113 +* : 19.12.2016 1.50 Added support for RX24U, RX24T(512KB) +* : 21.07.2017 2.30 Added support for RX65N-2M, RX130-512KB +* : 28.09.2018 2.40 Added support for RX66T +* Update according to GSCE Code Checker +* : 01.02.2019 2.50 Added support for RX72T, RX65N-64pin +* : 20.05.2019 3.00 Added support for GNUC and ICCRX. +* : 28.06.2019 3.10 Added support RX23W +* : 15.08.2019 3.20 Added support RX72M +* : 25.11.2019 3.30 Added support RX13T +* Modified comment of API function to Doxygen style +* : 30.12.2019 3.40 Added support RX72N, RX66N +* : 15.04.2021 4.00 Updated Doxygen comment. +* : 07.04.2023 4.80 Fixed to comply with GSCE Coding Standards Rev.6.5.0 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +/* Includes board and MCU related header files. */ +#include "platform.h" +/* Public interface header file for this package. */ +#include "r_mpc_rx_if.h" +/* Configuration for this package. */ +#include "r_mpc_rx_config.h" + +/*********************************************************************************************************************** +* Macro definitions +***********************************************************************************************************************/ +/* Base register of PFS used to calculate all PFS register addresses. This is constant for all supported MCUs */ +#define MPC_PRV_PFS_BASE_REG ((uint8_t volatile *)(&MPC.PWPR.BYTE+33)) + +/* Bit masks for PFS registers. */ +#define MPC_PRV_PFS_BIT_ASEL ((uint8_t)0x80) +#define MPC_PRV_PFS_BIT_ISEL ((uint8_t)0x40) +#define MPC_PRV_PFS_BIT_PSEL ((uint8_t)0x3F) + +/*********************************************************************************************************************** +* Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* Private global variables and functions +***********************************************************************************************************************/ +static uint8_t volatile * mpc_base_addr_get (uint8_t volatile * base_addr, uint16_t index); + +/*********************************************************************************************************************** +* Function Name: R_MPC_Read +********************************************************************************************************************//** +* @brief This function reads the function configuration of a pin. +* @param[in] pin - Which pin to read configuration information for. +* @param[in] pconfig - Pointer to structure where pin configuration information will be stored. See Section 2.10.1, MPC +* Pin Configuration. +* @details This function will read the configuration information for a pin and store it in a structure supplied by the +* user. +* @note None. +*/ +void R_MPC_Read(gpio_port_pin_t pin, mpc_config_t * pconfig) +{ + uint8_t volatile * pfs_reg; + + /* Get address of PFS register for this pin. */ + pfs_reg = mpc_base_addr_get(MPC_PRV_PFS_BASE_REG, (uint16_t)pin); + + /* Fill in pin info. */ + if (0 == ((*pfs_reg) & MPC_PRV_PFS_BIT_ASEL)) + { + pconfig->analog_enable = false; + } + else + { + pconfig->analog_enable = true; + } + + /* Fill in irq info */ + if (0 == ((*pfs_reg) & MPC_PRV_PFS_BIT_ISEL)) + { + pconfig->irq_enable = false; + } + else + { + pconfig->irq_enable = true; + } + + /* Fill in pin function info */ + pconfig->pin_function = (uint8_t)((*pfs_reg) & MPC_PRV_PFS_BIT_PSEL); +} /* End of function R_MPC_Read() */ + +/*********************************************************************************************************************** +* Function Name: R_MPC_Write +********************************************************************************************************************//** +* @brief This function sets the function of a pin. +* @param[in] pin - Which pin to configure. +* @param[in] pconfig - Pointer to structure with pin configuration information. See section 2.10.1, MPC Pin +* Configuration. +* @retval [MPC_SUCCESS] Successful; pin configured. +* @retval [MPC_ERR_INVALID_CFG] Error; invalid configuration input. +* @details This function will configure a pin based on the information in the mpc_config_t structure. Not all pins +* support the same functionality. For example, not all pins are able to be configured as analog pins for ADC or DAC use. +* Also, not all combinations of functionality are capable. For example, a pin cannot be configured as an analog pin and +* for peripheral use at the same time. +* To see what functions are available for a pin, refer to the Multi-Function Pin Controller (MPC) section of your MCU’s +* hardware manual. Select the Pin Function Control Register for the port that your pin is on. On this page you will +* find a table with available functions for each pin on the selected port. +* Which pin is to be configured by this function is defined using the gpio_port_pin_t type from the r_gpio_rx module. +* @note None. +*/ +mpc_err_t R_MPC_Write(gpio_port_pin_t pin, mpc_config_t * pconfig) +{ + uint8_t volatile * pfs_reg; + uint8_t write_value; + +#if (MPC_CFG_PARAM_CHECKING_ENABLE == 1) + if (true == pconfig->analog_enable) + { + if ((true == pconfig->irq_enable) || (0 != pconfig->pin_function)) + { + return MPC_ERR_INVALID_CFG; + } + } +#endif + + + /* Get address of PFS register for this pin. */ + pfs_reg = mpc_base_addr_get(MPC_PRV_PFS_BASE_REG, (uint16_t)pin); + + write_value = 0; + + /* Fill in pin info. */ + if (true == pconfig->analog_enable) + { + /* Fill in analog pin info */ + write_value = MPC_PRV_PFS_BIT_ASEL; + } + + if (true == pconfig->irq_enable) + { + /* Fill in irq info */ + write_value = (uint8_t)(write_value | MPC_PRV_PFS_BIT_ISEL); + } + + /* Fill in pin function info */ + write_value = (uint8_t)(write_value | (pconfig->pin_function & MPC_PRV_PFS_BIT_PSEL)); + + /* Enable writing to MPC registers. */ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_MPC); + + *pfs_reg = write_value; + + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_MPC); + + return MPC_SUCCESS; +} /* End of function R_MPC_Write() */ + +/*********************************************************************************************************************** +* Function Name: R_MPC_GetVersion +********************************************************************************************************************//** +* @brief Returns the current version of this API. +* @return Version of this API. +* @details This function will return the version of the currently running API. The version number is encoded where +* the top 2 bytes are the major version number and the bottom 2 bytes are the minor version number. For example, +* Version 4.25 would be returned as 0x00040019. +* @note None. +*/ +uint32_t R_MPC_GetVersion(void) +{ + /* These version macros are defined in r_mpc_rx_if.h. */ + return ((((uint32_t)MPC_RX_VERSION_MAJOR) << 16) | (uint32_t)MPC_RX_VERSION_MINOR); +} /* End of function R_MPC_GetVersion() */ + +/*********************************************************************************************************************** +* Function Name: mpc_base_addr_get +* Description : Get the address of a PFS register. +* Arguments : base_addr - +* First port register of this type (e.g. P00PFS) +* index - +* Index off the base. (e.g. for PORT4 it would be 0x0400) +* Return Value : Address of the register that was requested +***********************************************************************************************************************/ +R_BSP_PRAGMA_STATIC_INLINE(mpc_base_addr_get) +uint8_t volatile * mpc_base_addr_get(uint8_t volatile * base_addr, uint16_t index) +{ + uint32_t port_offset; + uint32_t pin_offset; + + /* Pin is the lower 8-bits of 'index' */ + pin_offset = (uint32_t)(index & 0x00FFu); + + /* Port is the upper 8-bits of 'index'. It is only being shifted by 5 because in the calculation the value is + * multiplied by 8 (which would result in a shift of 3 in the other direction). To save a couple of cycles + * the shift is adjusted here. */ + port_offset = (((uint32_t)index >> 5) & 0x000000FFuL); + + /* Add port and pin offset to 'index' to correct register. */ + return (uint8_t volatile *)(pin_offset + port_offset + (uint32_t)base_addr); +} /* End of function mpc_base_addr_get() */ + diff --git a/zephyr/rx/rdp_cfg/r_config/r_gpio_rx_config.h b/zephyr/rx/rdp_cfg/r_config/r_gpio_rx_config.h index f3f9bfc3..ff830d8d 100644 --- a/zephyr/rx/rdp_cfg/r_config/r_gpio_rx_config.h +++ b/zephyr/rx/rdp_cfg/r_config/r_gpio_rx_config.h @@ -15,7 +15,7 @@ * following link: * http://www.renesas.com/disclaimer * -* Copyright (C) 2013 - 2024 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2024 Renesas Electronics Corporation. All rights reserved. ***********************************************************************************************************************/ /*********************************************************************************************************************** * File Name : r_gpio_rx_config.h diff --git a/zephyr/rx/rdp_cfg/r_config/r_mpc_rx_config.h b/zephyr/rx/rdp_cfg/r_config/r_mpc_rx_config.h new file mode 100644 index 00000000..fdb17d02 --- /dev/null +++ b/zephyr/rx/rdp_cfg/r_config/r_mpc_rx_config.h @@ -0,0 +1,46 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013-2024 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_mpc_rx_config.h +* Description : Configuration options for the r_mpc_rx module. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 17.07.2013 1.00 First Release +***********************************************************************************************************************/ +#ifndef MPC_RX_CONFIG_HEADER_FILE +#define MPC_RX_CONFIG_HEADER_FILE + +/*********************************************************************************************************************** +Configuration Options +***********************************************************************************************************************/ +/* SPECIFY WHETHER TO INCLUDE CODE FOR API PARAMETER CHECKING + Available settings: + BSP_CFG_PARAM_CHECKING_ENABLE: + Utilizes the system default setting + 1: + Includes parameter checking + 0: + Compiles out parameter checking +*/ +#define MPC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#endif /* MPC_RX_CONFIG_HEADER_FILE */ + + From caf2e82244eb9d762b5d4f1cd6e7ad6cce5eb736 Mon Sep 17 00:00:00 2001 From: Sang Tran Date: Thu, 12 Sep 2024 18:18:09 +0700 Subject: [PATCH 4/9] hal: renesas: rx: Initial support sci driver on RSK_RX130_512KB Initial commit for SCI driver support on board using RX130 MCUs Signed-off-by: Sang Tran --- drivers/rx/CMakeLists.txt | 17 + drivers/rx/rdp/src/r_bsp/mcu/all/mcu_locks.c | 48 + drivers/rx/rdp/src/r_byteq/r_byteq_if.h | 109 + drivers/rx/rdp/src/r_byteq/src/r_byteq.c | 553 +++ .../rx/rdp/src/r_byteq/src/r_byteq_private.h | 58 + drivers/rx/rdp/src/r_pincfg/Pin.c | 128 + drivers/rx/rdp/src/r_pincfg/Pin.h | 83 + drivers/rx/rdp/src/r_pincfg/r_pinset.h | 33 + drivers/rx/rdp/src/r_pincfg/r_sci_rx_pinset.c | 183 + drivers/rx/rdp/src/r_pincfg/r_sci_rx_pinset.h | 46 + drivers/rx/rdp/src/r_sci_rx/r_sci_rx_if.h | 485 +++ drivers/rx/rdp/src/r_sci_rx/src/r_sci_rx.c | 3536 +++++++++++++++++ .../rx/rdp/src/r_sci_rx/src/r_sci_rx_dmaca.c | 1277 ++++++ .../rx/rdp/src/r_sci_rx/src/r_sci_rx_dmaca.h | 88 + .../rx/rdp/src/r_sci_rx/src/r_sci_rx_dtc.c | 561 +++ .../rx/rdp/src/r_sci_rx/src/r_sci_rx_dtc.h | 109 + .../rdp/src/r_sci_rx/src/r_sci_rx_platform.h | 105 + .../rdp/src/r_sci_rx/src/r_sci_rx_private.h | 311 ++ .../r_sci_rx/src/targets/rx130/r_sci_rx130.c | 1199 ++++++ .../src/targets/rx130/r_sci_rx130_data.c | 419 ++ .../src/targets/rx130/r_sci_rx130_private.h | 286 ++ zephyr/rx/rdp_cfg/r_config/r_byteq_config.h | 68 + .../rdp_cfg/r_config/rx130/r_sci_rx_config.h | 383 ++ 23 files changed, 10085 insertions(+) create mode 100644 drivers/rx/rdp/src/r_bsp/mcu/all/mcu_locks.c create mode 100644 drivers/rx/rdp/src/r_byteq/r_byteq_if.h create mode 100644 drivers/rx/rdp/src/r_byteq/src/r_byteq.c create mode 100644 drivers/rx/rdp/src/r_byteq/src/r_byteq_private.h create mode 100644 drivers/rx/rdp/src/r_pincfg/Pin.c create mode 100644 drivers/rx/rdp/src/r_pincfg/Pin.h create mode 100644 drivers/rx/rdp/src/r_pincfg/r_pinset.h create mode 100644 drivers/rx/rdp/src/r_pincfg/r_sci_rx_pinset.c create mode 100644 drivers/rx/rdp/src/r_pincfg/r_sci_rx_pinset.h create mode 100644 drivers/rx/rdp/src/r_sci_rx/r_sci_rx_if.h create mode 100644 drivers/rx/rdp/src/r_sci_rx/src/r_sci_rx.c create mode 100644 drivers/rx/rdp/src/r_sci_rx/src/r_sci_rx_dmaca.c create mode 100644 drivers/rx/rdp/src/r_sci_rx/src/r_sci_rx_dmaca.h create mode 100644 drivers/rx/rdp/src/r_sci_rx/src/r_sci_rx_dtc.c create mode 100644 drivers/rx/rdp/src/r_sci_rx/src/r_sci_rx_dtc.h create mode 100644 drivers/rx/rdp/src/r_sci_rx/src/r_sci_rx_platform.h create mode 100644 drivers/rx/rdp/src/r_sci_rx/src/r_sci_rx_private.h create mode 100644 drivers/rx/rdp/src/r_sci_rx/src/targets/rx130/r_sci_rx130.c create mode 100644 drivers/rx/rdp/src/r_sci_rx/src/targets/rx130/r_sci_rx130_data.c create mode 100644 drivers/rx/rdp/src/r_sci_rx/src/targets/rx130/r_sci_rx130_private.h create mode 100644 zephyr/rx/rdp_cfg/r_config/r_byteq_config.h create mode 100644 zephyr/rx/rdp_cfg/r_config/rx130/r_sci_rx_config.h diff --git a/drivers/rx/CMakeLists.txt b/drivers/rx/CMakeLists.txt index d376684f..7efd678b 100644 --- a/drivers/rx/CMakeLists.txt +++ b/drivers/rx/CMakeLists.txt @@ -6,6 +6,8 @@ set(include_dirs rdp_cfg/r_config rdp/src/r_bsp/mcu rdp/src/r_bsp/mcu/all + rdp/src/r_bsp/board + rdp/src/r_bsp/board/generic_${CONFIG_SOC_SERIES} rdp/src/r_bsp/mcu/${CONFIG_SOC_SERIES} rdp/src/r_bsp/mcu/${CONFIG_SOC_SERIES}/register_access/gnuc ) @@ -39,3 +41,18 @@ if(CONFIG_USE_RX_RDP_MPC) ) zephyr_include_directories(rdp/src/r_mpc_rx) endif() + +if(CONFIG_USE_RX_RDP_SCI_UART) + zephyr_include_directories(rdp/src/r_pincfg + rdp/src/r_byteq + rdp/src/r_byteq/src + rdp/src/r_sci_rx + rdp/src/r_sci_rx/src + rdp/src/r_sci_rx/src/targets/${CONFIG_SOC_SERIES} + ) + zephyr_library_sources(rdp/src/r_sci_rx/src/r_sci_rx.c + rdp/src/r_sci_rx/src/targets/${CONFIG_SOC_SERIES}/r_sci_${CONFIG_SOC_SERIES}.c + rdp/src/r_sci_rx/src/targets/${CONFIG_SOC_SERIES}/r_sci_${CONFIG_SOC_SERIES}_data.c + rdp/src/r_byteq/src/r_byteq.c + rdp/src/r_pincfg/r_sci_rx_pinset.c) +endif() diff --git a/drivers/rx/rdp/src/r_bsp/mcu/all/mcu_locks.c b/drivers/rx/rdp/src/r_bsp/mcu/all/mcu_locks.c new file mode 100644 index 00000000..39e8c5d3 --- /dev/null +++ b/drivers/rx/rdp/src/r_bsp/mcu/all/mcu_locks.c @@ -0,0 +1,48 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : mcu_locks.c +* Description : This source file has 1 lock per MCU resource. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 28.02.2019 2.00 Merged processing of all devices. +* Fixed coding style. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +/* Used for getting MCU information to accurately reflect available MCU resources. */ +#include "platform.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ +/* Below are locks for controlling access to MCU resources. */ +BSP_CFG_USER_LOCKING_TYPE g_bsp_Locks[BSP_NUM_LOCKS]; + diff --git a/drivers/rx/rdp/src/r_byteq/r_byteq_if.h b/drivers/rx/rdp/src/r_byteq/r_byteq_if.h new file mode 100644 index 00000000..df69a4c2 --- /dev/null +++ b/drivers/rx/rdp/src/r_byteq/r_byteq_if.h @@ -0,0 +1,109 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_byteq_if.h +* Description : Functions for using byte queues/circular buffers +************************************************************************************************************************ +* History : DD.MM.YYYY Version Description +* : 24.07.2013 1.00 Initial Release +* : 11.21.2014 1.20 Removed dependency to BSP +* : 01.22.2015 1.30 Updated version to 1.30 for RX71M release +* : 04.04.2015 1.40 Updated version to 1.40 for RX231 release +* : 30.09.2015 1.50 Added dependency to BSP +* : 29.01.2016 1.60 Updated version to 1.60 for correspondence to RX Family +* : 01.06.2018 1.70 Updated version to 1.70 +* : 03.12.2018 1.71 Updated version to 1.71 for update of xml file. +* : 07.02.2019 1.80 Updated version to 1.80. +* : 10.06.2020 1.81 Updated version to 1.81. +* : 30.11.2020 1.82 Updated version to 1.82 for e2studio 2020-10 support. +* : 31.03.2021 1.90 Updated for queue protection. +* : 29.10.2021 2.00 Updated for critical section protection in R_BYTEQ_Put, R_BYTEQ_Get functions. +* : 30.11.2022 2.10 Updated and added new demo project. +***********************************************************************************************************************/ + +#ifndef BYTEQ_IF_H +#define BYTEQ_IF_H + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "platform.h" +#include "r_byteq_config.h" +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Version Number of API. */ +#define BYTEQ_VERSION_MAJOR (2) +#define BYTEQ_VERSION_MINOR (10) + +#if ((BYTEQ_CFG_CRITICAL_SECTION == 1)||(BYTEQ_CFG_PROTECT_QUEUE == 1)) +#if (BSP_CFG_RUN_IN_USER_MODE == 1) + #error "Protect circular buffer must use in supervisor mode." +#endif +#endif + +/***************************************************************************** +Typedef definitions +******************************************************************************/ + +typedef enum e_byteq_err // BYTEQ API error codes +{ + BYTEQ_SUCCESS = 0, + BYTEQ_ERR_NULL_PTR, // received null ptr; missing required argument + BYTEQ_ERR_INVALID_ARG, // argument is not valid for parameter + BYTEQ_ERR_MALLOC_FAIL, // can't allocate memory for ctrl block; increase heap + BYTEQ_ERR_NO_MORE_CTRL_BLKS, // no more control blocks, increase BYTEQ_MAX_CTRL_BLKS + BYTEQ_ERR_QUEUE_FULL, // queue full; cannot add another byte + BYTEQ_ERR_QUEUE_EMPTY // queue empty; no byte to fetch +} byteq_err_t; + + +/* BYTE QUEUE HANDLE */ + +typedef struct st_byteq_ctrl * byteq_hdl_t; + + +/***************************************************************************** +Public Functions +******************************************************************************/ +byteq_err_t R_BYTEQ_Open(uint8_t * const p_buf, + uint16_t const size, + byteq_hdl_t * const p_hdl); + +byteq_err_t R_BYTEQ_Close(byteq_hdl_t const hdl); + +byteq_err_t R_BYTEQ_Put(byteq_hdl_t const hdl, + uint8_t const byte); + +byteq_err_t R_BYTEQ_Get(byteq_hdl_t const hdl, + uint8_t * const p_byte); + +byteq_err_t R_BYTEQ_Flush(byteq_hdl_t const hdl); + +byteq_err_t R_BYTEQ_Used(byteq_hdl_t const hdl, + uint16_t * const p_cnt); + +byteq_err_t R_BYTEQ_Unused(byteq_hdl_t const hdl, + uint16_t * const p_cnt); + +uint32_t R_BYTEQ_GetVersion(void); + + +#endif /* BYTEQ_IF_H */ + diff --git a/drivers/rx/rdp/src/r_byteq/src/r_byteq.c b/drivers/rx/rdp/src/r_byteq/src/r_byteq.c new file mode 100644 index 00000000..01ccca5c --- /dev/null +++ b/drivers/rx/rdp/src/r_byteq/src/r_byteq.c @@ -0,0 +1,553 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_byteq.c +* Description : Functions for using byte queues/circular buffers. +************************************************************************************************************************ +* History : DD.MM.YYYY Version Description +* : 24.07.2013 1.00 Initial Release +* : 11.21.2014 1.20 Removed dependency to BSP +* : 30.09.2015 1.50 Added dependency to BSP +* : 29.01.2016 1.60 Fixed the initial setting process in the R_LONGQ_Open function. +* Fixed a program according to the Renesas coding rules. +* : 01.06.2018 1.70 Added the comment to while statement. +* : 07.02.2019 1.80 Deleted the inline expansion of the R_BYTEQ_GetVersion function. +* : 10.06.2020 1.81 Modified comment of API function to Doxygen style. +* : 31.03.2021 1.90 Updated for queue protection in R_BYTEQ_Put, R_BYTEQ_Get, R_BYTEQ_Flush, +* R_BYTEQ_Used, R_BYTEQ_Unused functions. +* : 29.10.2021 2.00 Updated for critical section protection in R_BYTEQ_Put, R_BYTEQ_Get functions. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +/* Used functions of malloc() and the free() */ +#include + +/* Used the common type */ +#include "platform.h" + +/* Defines for BYTEQ support */ +#include "r_byteq_private.h" +#include "r_byteq_if.h" +#include "r_byteq_config.h" + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +/* QUEUE CONTROL BLOCK ALLOCATIONS */ + +#if (BYTEQ_CFG_USE_HEAP_FOR_CTRL_BLKS == 0) +static byteq_ctrl_t g_qcb[BYTEQ_CFG_MAX_CTRL_BLKS]; +#endif + + +/*********************************************************************************************************************** +* Function Name: R_BYTEQ_Open +*******************************************************************************************************************/ /** +* @brief This function allocates and initializes a queue control block for a +* buffer provided by the user. A queue handle is provided for use with +* other API functions. +* @param[in] p_buf Pointer to byte buffer. +* @param[in] size Buffer size in bytes. +* @param[in,out] p_hdl Pointer to a handle for queue (value set here) +* @retval BYTEQ_SUCCESS: Successful; queue initialized +* @retval BYTEQ_ERR_NULL_PTR: p_buf is NULL +* @retval BYTEQ_ERR_INVALID_ARG: Size is less than or equal to 1. +* @retval BYTEQ_ERR_MALLOC_FAIL: Cannot allocate control block. Increase heap size. +* @retval BYTEQ_ERR_NO_MORE_CTRL_BLKS: Cannot assign control block. Increase BYTEQ_MAX_CTRL_BLKS in config.h. +* @details This function allocates or assigns a queue control block for the +* buffer pointed to by \e p_buf. Initializes the queue to an empty state and provides a Handle to its control +* structure in \e p_hdl which is then used as a queue ID for the other API functions. +* @note None +*/ +byteq_err_t R_BYTEQ_Open(uint8_t * const p_buf, + uint16_t const size, + byteq_hdl_t * const p_hdl) +{ + byteq_ctrl_t *p_qcb = 0; +#if (BYTEQ_CFG_USE_HEAP_FOR_CTRL_BLKS == 0) + uint32_t i; + static bool qcb_init = false; +#endif + + /* CHECK ARGUMENTS */ + +#if (BYTEQ_CFG_PARAM_CHECKING_ENABLE == 1) + if (NULL == p_hdl) + { + return BYTEQ_ERR_INVALID_ARG; // return if invalid location + } + if (NULL == p_buf) + { + return BYTEQ_ERR_NULL_PTR; // return if no buffer pointer + } + if (size < 2) + { + return BYTEQ_ERR_INVALID_ARG; // return insufficient buffer size + } +#endif + + /* GET QUEUE CONTROL BLOCK */ + +#if BYTEQ_CFG_USE_HEAP_FOR_CTRL_BLKS + + /* allocate memory for a QCB */ + p_qcb = (byteq_ctrl_t *)malloc(sizeof(byteq_ctrl_t)); + if (NULL == p_qcb) + { + return BYTEQ_ERR_MALLOC_FAIL; + } +#else + /* if first Open call, mark all QCBs as being available */ + if (false == qcb_init) + { + /* WAIT_LOOP */ + for (i=0; i < BYTEQ_CFG_MAX_CTRL_BLKS; i++) + { + g_qcb[i].buffer = NULL; + } + qcb_init = true; + } + + /* locate first available QCB */ + /* WAIT_LOOP */ + for (i=0; i < BYTEQ_CFG_MAX_CTRL_BLKS; i++) + { + if (NULL == g_qcb[i].buffer) + { + p_qcb = &g_qcb[i]; + break; + } + } + + /* return error if none available */ + if (BYTEQ_CFG_MAX_CTRL_BLKS == i) + { + return BYTEQ_ERR_NO_MORE_CTRL_BLKS; + } +#endif + + + /* INITIALIZE QCB FIELDS */ + + p_qcb->buffer = p_buf; + p_qcb->size = size; + p_qcb->count = 0; + p_qcb->in_index = 0; + p_qcb->out_index = 0; + + + /* SET HANDLE */ + + *p_hdl = p_qcb; + return BYTEQ_SUCCESS; +} + + +/*********************************************************************************************************************** +* Function Name: R_BYTEQ_Put +*******************************************************************************************************************/ /** +* @brief This function adds a byte of data to the queue. +* @param[in,out] hdl Handle for queue. +* @param[in] byte Byte to add to queue. +* @retval BYTEQ_SUCCESS: Successful; byte added to queue +* @retval BYTEQ_ERR_NULL_PTR: hdl is NULL. +* @retval BYTEQ_ERR_QUEUE_FULL: Queue full; cannot add byte to queue. +* @details This function adds the contents of \e byte to the queue associated with \e hdl. +* @note None +*/ +byteq_err_t R_BYTEQ_Put(byteq_hdl_t const hdl, + uint8_t const byte) +{ +#if (BYTEQ_CFG_PARAM_CHECKING_ENABLE == 1) + if (NULL == hdl) + { + return BYTEQ_ERR_NULL_PTR; // return if no handle + } +#endif + + if (hdl->count >= hdl->size) + { + return BYTEQ_ERR_QUEUE_FULL; // return if queue is full + } + +#if ((BYTEQ_CFG_CRITICAL_SECTION == 1)||(BYTEQ_CFG_PROTECT_QUEUE == 1)) + uint32_t psw_bit_i_val; + /* Get current value bit I of PSW register. */ + psw_bit_i_val = (R_BSP_GET_PSW() & 0x00010000); +#endif + +#if (BYTEQ_CFG_CRITICAL_SECTION == 1) + if(0 != psw_bit_i_val) + { + R_BSP_InterruptsDisable(); + /* load byte into queue */ + hdl->buffer[hdl->in_index++] = byte; // add byte + R_BSP_InterruptsEnable(); + + R_BSP_InterruptsDisable(); + if (hdl->in_index >= hdl->size) // adjust index + { + hdl->in_index = 0; + } + R_BSP_InterruptsEnable(); + } + else + { + /* load byte into queue */ + hdl->buffer[hdl->in_index++] = byte; // add byte + if (hdl->in_index >= hdl->size) // adjust index + { + hdl->in_index = 0; + } + } +#else + /* load byte into queue */ + hdl->buffer[hdl->in_index++] = byte; // add byte + if (hdl->in_index >= hdl->size) // adjust index + { + hdl->in_index = 0; + } +#endif + +#if (BYTEQ_CFG_PROTECT_QUEUE == 1) + if(0 != psw_bit_i_val) + { + R_BSP_InterruptsDisable(); + hdl->count++; // adjust count + R_BSP_InterruptsEnable(); + } + else + { + hdl->count++; // adjust count + } +#else + hdl->count++; // adjust count +#endif + + return BYTEQ_SUCCESS; +} + + +/*********************************************************************************************************************** +* Function Name: R_BYTEQ_Get +*******************************************************************************************************************/ /** +* @brief This function removes a byte of data from the queue. +* @param[in,out] hdl Handle for queue. +* @param[in,out] p_byte Pointer to load byte to. +* @retval BYTEQ_SUCCESS: Successful; byte removed from queue +* @retval BYTEQ_ERR_NULL_PTR: hdl is NULL. +* @retval BYTEQ_ERR_INVALID_ARG: p_byte is NULL. +* @retval BYTEQ_ERR_QUEUE_EMPTY: Queue empty; no data available to fetch +* @details This function removes the oldest byte of data in the queue associated with \e hdl and loads it into the +* location pointed to by \e p_byte. +* @note None +*/ +byteq_err_t R_BYTEQ_Get(byteq_hdl_t const hdl, + uint8_t * const p_byte) +{ +#if (BYTEQ_CFG_PARAM_CHECKING_ENABLE == 1) + if (NULL == hdl) + { + return BYTEQ_ERR_NULL_PTR; // return if no handle + } + if (NULL == p_byte) + { + return BYTEQ_ERR_INVALID_ARG; // return if invalid location + } +#endif + + if (0 == hdl->count) + { + return BYTEQ_ERR_QUEUE_EMPTY; // return if queue empty + } + +#if ((BYTEQ_CFG_CRITICAL_SECTION == 1)||(BYTEQ_CFG_PROTECT_QUEUE == 1)) + uint32_t psw_bit_i_val; + /* Get current value bit I of PSW register. */ + psw_bit_i_val = (R_BSP_GET_PSW() & 0x00010000); +#endif + +#if (BYTEQ_CFG_CRITICAL_SECTION == 1) + if(0 != psw_bit_i_val) + { + R_BSP_InterruptsDisable(); + *p_byte = hdl->buffer[hdl->out_index++]; // get byte + R_BSP_InterruptsEnable(); + + R_BSP_InterruptsDisable(); + if (hdl->out_index >= hdl->size) // adjust index + { + hdl->out_index = 0; + } + R_BSP_InterruptsEnable(); + } + else + { + *p_byte = hdl->buffer[hdl->out_index++]; // get byte + if (hdl->out_index >= hdl->size) // adjust index + { + hdl->out_index = 0; + } + } +#else + *p_byte = hdl->buffer[hdl->out_index++]; // get byte + if (hdl->out_index >= hdl->size) // adjust index + { + hdl->out_index = 0; + } +#endif + +#if (BYTEQ_CFG_PROTECT_QUEUE == 1) + if(0 != psw_bit_i_val) + { + R_BSP_InterruptsDisable(); + hdl->count--; // adjust count + R_BSP_InterruptsEnable(); + } + else + { + hdl->count--; // adjust count + } +#else + hdl->count--; // adjust count +#endif + + return BYTEQ_SUCCESS; +} + + +/*********************************************************************************************************************** +* Function Name: R_BYTEQ_Flush +*******************************************************************************************************************/ /** +* @brief This function resets a queue to an empty state. +* @param[in,out] hdl Handle for queue. +* @retval BYTEQ_SUCCESS: Successful; queue reset +* @retval BYTEQ_ERR_NULL_PTR: hdl is NULL. +* @details This function resets the queue identified by \e hdl to an empty state. +* @note None +*/ +byteq_err_t R_BYTEQ_Flush(byteq_hdl_t const hdl) +{ +#if (BYTEQ_CFG_PARAM_CHECKING_ENABLE == 1) + if (NULL == hdl) + { + return BYTEQ_ERR_NULL_PTR; + } +#endif + +#if (BYTEQ_CFG_PROTECT_QUEUE == 1) + uint32_t psw_bit_i_val; + + /* Get current value bit I of PSW register. */ + psw_bit_i_val = (R_BSP_GET_PSW() & 0x00010000); + + if(0 != psw_bit_i_val) + { + R_BSP_InterruptsDisable(); + + /* RESET QUEUE */ + hdl->in_index = 0; + hdl->out_index = 0; + hdl->count = 0; + + R_BSP_InterruptsEnable(); + } + else + { + /* RESET QUEUE */ + + hdl->in_index = 0; + hdl->out_index = 0; + hdl->count = 0; + } +#else + /* RESET QUEUE */ + + hdl->in_index = 0; + hdl->out_index = 0; + hdl->count = 0; +#endif + + return BYTEQ_SUCCESS; +} + + +/*********************************************************************************************************************** +* Function Name: R_BYTEQ_Used +*******************************************************************************************************************/ /** +* @brief This function provides the number of data bytes in the queue. +* @param[in] hdl Handle for queue. +* @param[in,out] p_cnt Pointer to load queue data count to. +* @retval BYTEQ_SUCCESS: Successful; *p_cnt loaded with the number of bytes in the queue +* @retval BYTEQ_ERR_NULL_PTR: hdl is NULL. +* @retval BYTEQ_ERR_INVALID_ARG: p_cnt is NULL. +* @details This function loads the number of bytes in the queue associated with \e hdl and into the location pointed +* to by \e p_cnt. +* @note None +*/ +byteq_err_t R_BYTEQ_Used(byteq_hdl_t const hdl, + uint16_t * const p_cnt) +{ +#if (BYTEQ_CFG_PARAM_CHECKING_ENABLE == 1) + if (NULL == hdl) + { + return BYTEQ_ERR_NULL_PTR; + } + if (NULL == p_cnt) + { + return BYTEQ_ERR_INVALID_ARG; // return if invalid location + } +#endif + +#if (BYTEQ_CFG_PROTECT_QUEUE == 1) + uint32_t psw_bit_i_val; + + /* Get current value bit I of PSW register. */ + psw_bit_i_val = (R_BSP_GET_PSW() & 0x00010000); + + if(0 != psw_bit_i_val) + { + R_BSP_InterruptsDisable(); + *p_cnt = hdl->count; + R_BSP_InterruptsEnable(); + } + else + { + *p_cnt = hdl->count; + } +#else + *p_cnt = hdl->count; +#endif + return BYTEQ_SUCCESS; +} + + +/*********************************************************************************************************************** +* Function Name: R_BYTEQ_Unused +*******************************************************************************************************************/ /** +* @brief This function provides the number of data bytes available for storage in the queue. +* @param[in] hdl Handle for queue. +* @param[in,out] p_cnt Pointer to load queue unused byte count to. +* @retval BYTEQ_SUCCESS: Successful; *p_cnt loaded with the number of bytes not used in the queue +* @retval BYTEQ_ERR_NULL_PTR: hdl is NULL. +* @retval BYTEQ_ERR_INVALID_ARG: p_cnt is NULL. +* @details This function loads the number of unused bytes in the queue associated with \e hdl and into the location +* pointed to by \e p_cnt. +* @note None +*/ +byteq_err_t R_BYTEQ_Unused(byteq_hdl_t const hdl, + uint16_t * const p_cnt) +{ +#if (BYTEQ_CFG_PARAM_CHECKING_ENABLE == 1) + if (NULL == hdl) + { + return BYTEQ_ERR_NULL_PTR; + } + if (NULL == p_cnt) + { + return BYTEQ_ERR_INVALID_ARG; // return if invalid location + } +#endif + +#if (BYTEQ_CFG_PROTECT_QUEUE == 1) + uint32_t psw_bit_i_val; + + /* Get current value bit I of PSW register. */ + psw_bit_i_val = (R_BSP_GET_PSW() & 0x00010000); + + if(0 != psw_bit_i_val) + { + R_BSP_InterruptsDisable(); + + /* Get p_cnt. */ + *p_cnt = (uint16_t) (hdl->size - hdl->count); + R_BSP_InterruptsEnable(); + } + else + { + /* Get p_cnt. */ + *p_cnt = (uint16_t) (hdl->size - hdl->count); + } +#else + *p_cnt = (uint16_t) (hdl->size - hdl->count); +#endif + + return BYTEQ_SUCCESS; +} + + +/*********************************************************************************************************************** +* Function Name: R_BYTEQ_Close +*******************************************************************************************************************/ /** +* @brief This function releases the queue control block associated with a handle. +* @param[in,out] hdl Handle for queue. +* @retval BYTEQ_SUCCESS: Successful; control block released. +* @retval BYTEQ_ERR_NULL_PTR: hdl is NULL. +* @details If the control block associated with this Handle was allocated dynamically at run time +* (BYTEQ_USE_HEAP_FOR_CTRL_BLKS set to 1 in config.h), then that memory is freed by this function. If the +* control block was statically allocated at compile time (BYTEQ_USE_HEAP_FOR_CTRL_BLKS set to 0 in config.h), +* then this function marks the control block as available for use by another buffer. Nothing is done to the +* contents of the buffer referenced by this Handle. +* @note None +*/ +byteq_err_t R_BYTEQ_Close(byteq_hdl_t const hdl) +{ +#if (BYTEQ_CFG_PARAM_CHECKING_ENABLE == 1) + if (NULL == hdl) + { + return BYTEQ_ERR_NULL_PTR; + } +#endif + +#if BYTEQ_CFG_USE_HEAP_FOR_CTRL_BLKS + free(hdl); // free QCB memory +#else + hdl->buffer = NULL; // mark QCB as free +#endif + + return BYTEQ_SUCCESS; +} + + +/*********************************************************************************************************************** +* Function Name: R_BYTEQ_GetVersion +*******************************************************************************************************************/ /** +* @brief This function returns the driver version number at runtime. +* @return Version number. +* @details Returns the version of this module. The version number is encoded such that the top 2 bytes are the major +* version number and the bottom 2 bytes are the minor version number. +* @note None +*/ +uint32_t R_BYTEQ_GetVersion(void) +{ + + uint32_t const version = (BYTEQ_VERSION_MAJOR << 16) | BYTEQ_VERSION_MINOR; + return version; +} diff --git a/drivers/rx/rdp/src/r_byteq/src/r_byteq_private.h b/drivers/rx/rdp/src/r_byteq/src/r_byteq_private.h new file mode 100644 index 00000000..8f14acce --- /dev/null +++ b/drivers/rx/rdp/src/r_byteq/src/r_byteq_private.h @@ -0,0 +1,58 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_private.h +* Description : Definitions internal to byte queue module +************************************************************************************************************************ +* History : DD.MM.YYYY Version Description +* : 24.07.2013 1.0 Initial Release +* : 30.09.2015 1.50 Added dependency to BSP +***********************************************************************************************************************/ + +#ifndef BYTEQ_PRIVATE_H +#define BYTEQ_PRIVATE_H + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "platform.h" + + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + + +/***************************************************************************** +Typedef definitions +******************************************************************************/ + +/* QUEUE CONTROL BLOCK */ + +typedef struct st_byteq_ctrl // Byte Queue Control Block (for handle) +{ + uint8_t *buffer; // pointer to buffer + uint16_t size; // buffer size + uint16_t count; // number data bytes in queue + uint16_t in_index; // index used by Put function to add data + uint16_t out_index; // index used by Get function to remove data +} byteq_ctrl_t; + + +#endif /* BYTEQ_PRIVATE_H */ diff --git a/drivers/rx/rdp/src/r_pincfg/Pin.c b/drivers/rx/rdp/src/r_pincfg/Pin.c new file mode 100644 index 00000000..fe675991 --- /dev/null +++ b/drivers/rx/rdp/src/r_pincfg/Pin.c @@ -0,0 +1,128 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2018 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : Pin.c +* Version : 1.0.2 +* Device(s) : R5F51308AxFP +* Description : This file implements SMC pin code generation. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +* Function Name: R_Pins_Create +* Description : This function initializes Smart Configurator pins +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ + +void R_Pins_Create(void) +{ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_MPC); + + /* Set RXD0 pin */ + MPC.P21PFS.BYTE = 0x0AU; + PORT2.PMR.BYTE |= 0x02U; + + /* Set RXD1 pin */ + MPC.P30PFS.BYTE = 0x0AU; + PORT3.PMR.BYTE |= 0x01U; + + /* Set RXD5 pin */ + MPC.PA3PFS.BYTE = 0x0AU; + PORTA.PMR.BYTE |= 0x08U; + + /* Set RXD8 pin */ + MPC.PC6PFS.BYTE = 0x0AU; + PORTC.PMR.BYTE |= 0x40U; + + /* Set RXD9 pin */ + MPC.PB6PFS.BYTE = 0x0AU; + PORTB.PMR.BYTE |= 0x40U; + + /* Set RXD12 pin */ + MPC.PE2PFS.BYTE = 0x0CU; + PORTE.PMR.BYTE |= 0x04U; + + /* Set SMISO6 pin */ + MPC.PB0PFS.BYTE = 0x0BU; + PORTB.PMR.BYTE |= 0x01U; + + /* Set SMOSI6 pin */ + MPC.PB1PFS.BYTE = 0x0BU; + PORTB.PMR.BYTE |= 0x02U; + + /* Set TXD0 pin */ + PORT2.PODR.BYTE |= 0x01U; + MPC.P20PFS.BYTE = 0x0AU; + PORT2.PDR.BYTE |= 0x01U; + // PORT2.PMR.BIT.B0 = 1U; // Please set the PMR bit after TE bit is set to 1. + + /* Set TXD1 pin */ + PORT2.PODR.BYTE |= 0x40U; + MPC.P26PFS.BYTE = 0x0AU; + PORT2.PDR.BYTE |= 0x40U; + // PORT2.PMR.BIT.B6 = 1U; // Please set the PMR bit after TE bit is set to 1. + + /* Set TXD5 pin */ + PORTA.PODR.BYTE |= 0x10U; + MPC.PA4PFS.BYTE = 0x0AU; + PORTA.PDR.BYTE |= 0x10U; + // PORTA.PMR.BIT.B4 = 1U; // Please set the PMR bit after TE bit is set to 1. + + /* Set TXD8 pin */ + PORTC.PODR.BYTE |= 0x80U; + MPC.PC7PFS.BYTE = 0x0AU; + PORTC.PDR.BYTE |= 0x80U; + // PORTC.PMR.BIT.B7 = 1U; // Please set the PMR bit after TE bit is set to 1. + + /* Set TXD9 pin */ + PORTB.PODR.BYTE |= 0x80U; + MPC.PB7PFS.BYTE = 0x0AU; + PORTB.PDR.BYTE |= 0x80U; + // PORTB.PMR.BIT.B7 = 1U; // Please set the PMR bit after TE bit is set to 1. + + /* Set TXD12 pin */ + PORTE.PODR.BYTE |= 0x02U; + MPC.PE1PFS.BYTE = 0x0CU; + PORTE.PDR.BYTE |= 0x02U; + // PORTE.PMR.BIT.B1 = 1U; // Please set the PMR bit after TE bit is set to 1. + + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_MPC); +} + diff --git a/drivers/rx/rdp/src/r_pincfg/Pin.h b/drivers/rx/rdp/src/r_pincfg/Pin.h new file mode 100644 index 00000000..7d2d81c6 --- /dev/null +++ b/drivers/rx/rdp/src/r_pincfg/Pin.h @@ -0,0 +1,83 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2018 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : Pin.h +* Version : 1.0.2 +* Device(s) : R5F51308AxFP +* Description : This file implements SMC pin code generation. +***********************************************************************************************************************/ + +#ifndef PIN_H +#define PIN_H + +/*********************************************************************************************************************** +Macro definitions (Register bit) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/* User's guide for symbolic name. + * The generated symbolic names can be used in the user application as follows: + * + * Example: Toggle LED1 at Pin P54. + * There are 2 ways to toggle LED1 + * 1) Using symbolic name macro + * Assuming the symbolic name for P54 is "LED1", the generated macro definition will be: + * #define LED1 5,4 + * + * To use this macro defintion to toggle the LED1, call the symbolic name APIs: + * PIN_WRITE(LED1) = ~PIN_READ(LED1) + * + * 2) Not using symbolic name macro + * Call the symbolic name APIs directly + * PIN_WRITE(5,4) = ~PIN_READ(5,4) + */ + +/* Pin write helper */ +#define PIN_WRITE_HELPER(x,y) ((PORT##x.PODR.BIT.B##y)) +/* Pin read helper */ +#define PIN_READ_HELPER(x,y) ((PORT##x.PIDR.BIT.B##y)) + +#if !(defined(__CCRX__) && defined(__cplusplus)) +/* Pin write API */ +#define PIN_WRITE(...) (PIN_WRITE_HELPER(__VA_ARGS__)) +/* Pin read API */ +#define PIN_READ(...) (PIN_READ_HELPER(__VA_ARGS__)) +#else +/* CC-RX' C++ mode does not support variadic macros */ +/* Pin write API */ +#define PIN_WRITE(args) (PIN_WRITE_HELPER(args)) +/* Pin read API */ +#define PIN_READ(args) (PIN_READ_HELPER(args)) +#endif + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Global functions +***********************************************************************************************************************/ +void R_Pins_Create(void); +/* Start user code for function. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#endif diff --git a/drivers/rx/rdp/src/r_pincfg/r_pinset.h b/drivers/rx/rdp/src/r_pincfg/r_pinset.h new file mode 100644 index 00000000..ab770829 --- /dev/null +++ b/drivers/rx/rdp/src/r_pincfg/r_pinset.h @@ -0,0 +1,33 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2024 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_pinset.h.h +* Version : 1.0.1 +* Description : Declares all pin code headers into a single file +***********************************************************************************************************************/ + +#ifndef R_PINSET_H +#define R_PINSET_H + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_sci_rx_pinset.h" + +#endif /* R_PINSET_H */ diff --git a/drivers/rx/rdp/src/r_pincfg/r_sci_rx_pinset.c b/drivers/rx/rdp/src/r_pincfg/r_sci_rx_pinset.c new file mode 100644 index 00000000..0c487ed6 --- /dev/null +++ b/drivers/rx/rdp/src/r_pincfg/r_sci_rx_pinset.c @@ -0,0 +1,183 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2024 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_sci_rx_pinset.c +* Version : 1.0.2 +* Device(s) : R5F51308AxFP +* Tool-Chain : RXC toolchain +* Description : Setting of port and mpc registers +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_sci_rx_pinset.h" +#include "platform.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* Function Name: R_SCI_PinSet_SCI0 +* Description : This function initializes pins for r_sci_rx module +* Arguments : none +* Return Value : none +***********************************************************************************************************************/ +void R_SCI_PinSet_SCI0() +{ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_MPC); + + /* Set RXD0/SMISO0/SSCL0 pin */ + MPC.P21PFS.BYTE = 0x0AU; + PORT2.PMR.BIT.B1 = 1U; + + /* Set TXD0/SMOSI0/SSDA0 pin */ + MPC.P20PFS.BYTE = 0x0AU; + PORT2.PMR.BIT.B0 = 1U; + + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_MPC); +} + +/*********************************************************************************************************************** +* Function Name: R_SCI_PinSet_SCI1 +* Description : This function initializes pins for r_sci_rx module +* Arguments : none +* Return Value : none +***********************************************************************************************************************/ +void R_SCI_PinSet_SCI1() +{ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_MPC); + + /* Set RXD1/SMISO1/SSCL1 pin */ + MPC.P30PFS.BYTE = 0x0AU; + PORT3.PMR.BIT.B0 = 1U; + + /* Set TXD1/SMOSI1/SSDA1 pin */ + MPC.P26PFS.BYTE = 0x0AU; + PORT2.PMR.BIT.B6 = 1U; + + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_MPC); +} + +/*********************************************************************************************************************** +* Function Name: R_SCI_PinSet_SCI5 +* Description : This function initializes pins for r_sci_rx module +* Arguments : none +* Return Value : none +***********************************************************************************************************************/ +void R_SCI_PinSet_SCI5() +{ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_MPC); + + /* Set RXD5/SMISO5/SSCL5 pin */ + MPC.PA3PFS.BYTE = 0x0AU; + PORTA.PMR.BIT.B3 = 1U; + + /* Set TXD5/SMOSI5/SSDA5 pin */ + MPC.PA4PFS.BYTE = 0x0AU; + PORTA.PMR.BIT.B4 = 1U; + + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_MPC); +} + +/*********************************************************************************************************************** +* Function Name: R_SCI_PinSet_SCI6 +* Description : This function initializes pins for r_sci_rx module +* Arguments : none +* Return Value : none +***********************************************************************************************************************/ +void R_SCI_PinSet_SCI6() +{ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_MPC); + + /* Set RXD6/SMISO6/SSCL6 pin */ + MPC.PB0PFS.BYTE = 0x0BU; + PORTB.PMR.BIT.B0 = 1U; + + /* Set TXD6/SMOSI6/SSDA6 pin */ + MPC.PB1PFS.BYTE = 0x0BU; + PORTB.PMR.BIT.B1 = 1U; + + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_MPC); +} + +/*********************************************************************************************************************** +* Function Name: R_SCI_PinSet_SCI8 +* Description : This function initializes pins for r_sci_rx module +* Arguments : none +* Return Value : none +***********************************************************************************************************************/ +void R_SCI_PinSet_SCI8() +{ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_MPC); + + /* Set RXD8/SMISO8/SSCL8 pin */ + MPC.PC6PFS.BYTE = 0x0AU; + PORTC.PMR.BIT.B6 = 1U; + + /* Set TXD8/SMOSI8/SSDA8 pin */ + MPC.PC7PFS.BYTE = 0x0AU; + PORTC.PMR.BIT.B7 = 1U; + + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_MPC); +} + +/*********************************************************************************************************************** +* Function Name: R_SCI_PinSet_SCI9 +* Description : This function initializes pins for r_sci_rx module +* Arguments : none +* Return Value : none +***********************************************************************************************************************/ +void R_SCI_PinSet_SCI9() +{ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_MPC); + + /* Set RXD9/SMISO9/SSCL9 pin */ + MPC.PB6PFS.BYTE = 0x0AU; + PORTB.PMR.BIT.B6 = 1U; + + /* Set TXD9/SMOSI9/SSDA9 pin */ + MPC.PB7PFS.BYTE = 0x0AU; + PORTB.PMR.BIT.B7 = 1U; + + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_MPC); +} + +/*********************************************************************************************************************** +* Function Name: R_SCI_PinSet_SCI12 +* Description : This function initializes pins for r_sci_rx module +* Arguments : none +* Return Value : none +***********************************************************************************************************************/ +void R_SCI_PinSet_SCI12() +{ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_MPC); + + /* Set RXD12/SMISO12/SSCL12 pin */ + MPC.PE2PFS.BYTE = 0x0CU; + PORTE.PMR.BIT.B2 = 1U; + + /* Set TXD12/SMOSI12/SSDA12 pin */ + MPC.PE1PFS.BYTE = 0x0CU; + PORTE.PMR.BIT.B1 = 1U; + + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_MPC); +} + diff --git a/drivers/rx/rdp/src/r_pincfg/r_sci_rx_pinset.h b/drivers/rx/rdp/src/r_pincfg/r_sci_rx_pinset.h new file mode 100644 index 00000000..81a977a4 --- /dev/null +++ b/drivers/rx/rdp/src/r_pincfg/r_sci_rx_pinset.h @@ -0,0 +1,46 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2024 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_sci_rx_pinset.h +* Version : 1.0.2 +* Device(s) : R5F51308AxFP +* Tool-Chain : RXC toolchain +* Description : Setting of port and mpc registers +***********************************************************************************************************************/ + +#ifndef R_SCI_RX_H +#define R_SCI_RX_H + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ + +void R_SCI_PinSet_SCI0(); +void R_SCI_PinSet_SCI1(); +void R_SCI_PinSet_SCI5(); +void R_SCI_PinSet_SCI6(); +void R_SCI_PinSet_SCI8(); +void R_SCI_PinSet_SCI9(); +void R_SCI_PinSet_SCI12(); + +#endif diff --git a/drivers/rx/rdp/src/r_sci_rx/r_sci_rx_if.h b/drivers/rx/rdp/src/r_sci_rx/r_sci_rx_if.h new file mode 100644 index 00000000..5d9a1f08 --- /dev/null +++ b/drivers/rx/rdp/src/r_sci_rx/r_sci_rx_if.h @@ -0,0 +1,485 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013-2024 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_sci_rx_if.h +* Description : Functions for using SCI on RX devices. +************************************************************************************************************************ +* History : DD.MM.YYYY Version Description +* 25.09.2013 1.00 Initial Release +* 17.04.2014 1.20 Bumped revision for RX110 support. +* 02.07.2014 1.30 Fixed bug that caused Group12 rx errors to only be enabled for channel 2. +* 25.11.2014 1.40 Added RX113 support +* 11.03.2015 1.40 Consolidated with r_sci_rx64m and added support for RX71M +* 11.05.2015 1.60 Added RX231 support +* 30.09.2015 1.70 Added RX23T support +* 01.10.2016 1.80 Added support for RX65N (comments and TX/RX FIFO THRESHOLD options) +* 19.12.2016 1.90 Added RX24U support +* SCI_CMD_EN_TEI was Changed to ineffective, because it is meaningless command. +* 07.03.2017 2.00 Fixed a bug that send/receive is incorrect when changed setting when FIFO enabled. +* Fixed a bug that callback function work many times at receive interrupt +* when FIFO(async) enabled. +* Fixed a bug that the interrupt priority level can be changed only in async mode. +* 31.10.2017 2.01 Added the demo for RX65N, RX65N-2M. +* 28.09.2018 2.10 Added support RX66T +* Added SCI_CMD_COMPARE_RECEIVED_DATA command +* Added SCI_EVT_RX_CHAR_MATCH for receiving data match event +* Fixed section layout follow GSCE 5.0 +* 16.11.2018 2.11 Added XML document number +* 01.02.2019 2.20 Added support RX72T, RX65N-64pin +* 20.05.2019 3.00 Added support for GNUC and ICCRX. +* 28.06.2019 3.10 Added support RX23W +* 15.08.2019 3.20 Added support RX72M +* 16.09.2019 3.21 Fixed issue in RX631/RX63N sci_initialize_ints() +* 25.11.2019 3.30 Added support RX13T. +* 30.12.2019 3.40 Added support RX66N, RX72N. +* 31.03.2020 3.50 Added support RX23E-A. +* 25.08.2020 3.60 Added feature using DTC/DMAC in SCI transfer. +* Merged IrDA functionality to SCI FIT. +* 30.09.2020 3.70 Fixed issue of duplicate device group for SCI11 in MDF file. +* Fixed issue of missing SSCL, SSDA in MDF file. +* 31.03.2021 3.80 Added support for RX671. +* Added support circular buffer in mode asynchronous. +* 15.04.2021 3.90 Added support for RX140 +* 16.08.2021 3.91 Updated Application Notes +* R_SCI_Send() function: Added notes to describe using TEI callback function. +* 13.09.2021 4.00 Added the demo for RX671. +* 15.11.2021 4.10 Added command SCI_CMD_SET_TXI_RXI_PRIORITY in R_SCI_Control() +* for changing TXI and RXI priority level simultaneously. +* Added support command SCI_CMD_SET_TXI_PRIORITY and SCI_CMD_SET_RXI_PRIORITY +* in R_SCI_Control() for Series RX100 and RX200. +* 29.12.2021 4.20 Added support for RX140-256KB. +* 14.03.2022 4.30 Added support for RX66T-48Pin. +* 31.03.2022 4.40 Fixed the issue with DTC mode which incorrectly uses the same transfer information +* for all channels. +* Fixed issue of consecutively calling R_SCI_Receive() function in using DTC/DMAC. +* Added support for RX660. +* 28.06.2022 4.50 Updated demo projects. +* 27.12.2022 4.60 Fixed the issue that rx_idle is not changed to true when reception is complete +* in DMAC mode. +* Updated macro definition enable and disable nested interrupt for TXI, RXI, ERI, TEI. +* 16.02.2023 4.70 Fixed a bug that return wrong value in sci_init_bit_rate() function. +* Fixed a bug in sci_send_sync_data() function with DTC mode. +* 31.03.2023 4.80 Added support for RX26T. +* Fixed to comply with GSCE Coding Standards Rev.6.5.0. +* Removed byteq header include in SYNC mode and SSPI mode. +* Moved the source code which checks for IRDA mode support to MDF file. +* 29.05.2023 4.90 Added support for RX23E-B. +* Fixed to comply with GSCE Coding Standards Rev.6.5.0. +* 12.06.2023 5.00 Fixed bugs in sci_send_sync_data(), sci_receive_sync_data() and +* sci_receive_async_data() function in using DTC/DMAC. +* 31.01.2024 5.10 Modified misleading description in "r_sci_rx_config.h" and MDF files. +* Removed the attribute constraint at Channel 1 and 5 of the DATA MATCH parameters +* in the MDF file. +* Added WAIT_LOOP comments. +* 13.03.2024 5.20 Fixed the issue that repeat_block_side had an unexpected value +* in the sci_tx_dmaca_create() and sci_rx_dmaca_create() functions. +***********************************************************************************************************************/ + +#ifndef SCI_IF_H +#define SCI_IF_H + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "platform.h" +#include "r_sci_rx_config.h" /* SCI config definitions */ +#if (SCI_CFG_ASYNC_INCLUDED && SCI_CFG_USE_CIRCULAR_BUFFER) +#include "r_byteq_config.h" +#endif +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +#if R_BSP_VERSION_MAJOR < 5 + #error "This module must use BSP module of Rev.5.00 or higher. Please use the BSP module of Rev.5.00 or higher." +#endif + +#if (SCI_CFG_ASYNC_INCLUDED && SCI_CFG_USE_CIRCULAR_BUFFER) +#if (BYTEQ_CFG_PROTECT_QUEUE == 0) + #error "Circular buffer must be protected." +#endif +#endif + +/* Version Number of API. */ +#define SCI_VERSION_MAJOR (5) +#define SCI_VERSION_MINOR (20) + +#define SCI_DTC_DMACA_DISABLE (0x0) +#define SCI_DTC_ENABLE (0x1) +#define SCI_DMACA_ENABLE (0x2) + +#define TX_DTC_DMACA_ENABLE (SCI_CFG_CH8_TX_DTC_DMACA_ENABLE | SCI_CFG_CH9_TX_DTC_DMACA_ENABLE | \ + SCI_CFG_CH10_TX_DTC_DMACA_ENABLE | SCI_CFG_CH11_TX_DTC_DMACA_ENABLE | \ + SCI_CFG_CH1_TX_DTC_DMACA_ENABLE | SCI_CFG_CH2_TX_DTC_DMACA_ENABLE | \ + SCI_CFG_CH3_TX_DTC_DMACA_ENABLE | SCI_CFG_CH4_TX_DTC_DMACA_ENABLE | \ + SCI_CFG_CH5_TX_DTC_DMACA_ENABLE | SCI_CFG_CH6_TX_DTC_DMACA_ENABLE | \ + SCI_CFG_CH7_TX_DTC_DMACA_ENABLE | SCI_CFG_CH12_TX_DTC_DMACA_ENABLE | \ + SCI_CFG_CH0_TX_DTC_DMACA_ENABLE) +#define RX_DTC_DMACA_ENABLE (SCI_CFG_CH8_RX_DTC_DMACA_ENABLE | SCI_CFG_CH9_RX_DTC_DMACA_ENABLE | \ + SCI_CFG_CH10_RX_DTC_DMACA_ENABLE | SCI_CFG_CH11_RX_DTC_DMACA_ENABLE | \ + SCI_CFG_CH1_RX_DTC_DMACA_ENABLE | SCI_CFG_CH2_RX_DTC_DMACA_ENABLE | \ + SCI_CFG_CH3_RX_DTC_DMACA_ENABLE | SCI_CFG_CH4_RX_DTC_DMACA_ENABLE | \ + SCI_CFG_CH5_RX_DTC_DMACA_ENABLE | SCI_CFG_CH6_RX_DTC_DMACA_ENABLE | \ + SCI_CFG_CH7_RX_DTC_DMACA_ENABLE | SCI_CFG_CH12_RX_DTC_DMACA_ENABLE | \ + SCI_CFG_CH0_RX_DTC_DMACA_ENABLE) + +#define SCI_CLK_INT (0x00U) /* use internal clock for baud generation */ +#define SCI_CLK_EXT8X (0x03U) /* use external clock 8x baud rate (ASYNC) */ +#define SCI_CLK_EXT16X (0x02U) /* use external clock 16x baud rate (ASYNC) */ +#define SCI_DATA_7BIT (0x40U) +#define SCI_DATA_8BIT (0x00U) +#define SCI_PARITY_ON (0x20U) +#define SCI_PARITY_OFF (0x00U) +#define SCI_ODD_PARITY (0x10U) +#define SCI_EVEN_PARITY (0x00U) +#define SCI_STOPBITS_2 (0x08U) +#define SCI_STOPBITS_1 (0x00U) + +#if SCI_CFG_IRDA_INCLUDED +/* IrDA Output Pulse Width Select Data (do NOT change values) */ +#define SCI_IRDA_OUT_WIDTH_3_16 (0x00U) +#define SCI_IRDA_OUT_WIDTH_2 (0x01U) +#define SCI_IRDA_OUT_WIDTH_4 (0x02U) +#define SCI_IRDA_OUT_WIDTH_8 (0x03U) +#define SCI_IRDA_OUT_WIDTH_16 (0x04U) +#define SCI_IRDA_OUT_WIDTH_32 (0x05U) +#define SCI_IRDA_OUT_WIDTH_64 (0x06U) +#define SCI_IRDA_OUT_WIDTH_128 (0x07U) +#endif + +/***************************************************************************** +Typedef definitions +******************************************************************************/ +typedef enum e_sci_ch // SCI channel numbers +{ + SCI_CH0=0, + SCI_CH1, + SCI_CH2, + SCI_CH3, + SCI_CH4, + SCI_CH5, + SCI_CH6, + SCI_CH7, + SCI_CH8, + SCI_CH9, + SCI_CH10, + SCI_CH11, + SCI_CH12, + SCI_NUM_CH +} sci_ch_t; + + +typedef enum e_sci_mode // SCI operational modes +{ + SCI_MODE_OFF=0, // channel not in use + SCI_MODE_ASYNC, // Asynchronous + SCI_MODE_SSPI, // Simple SPI + SCI_MODE_SYNC, // Synchronous + SCI_MODE_IRDA, // Infrared Data Association + SCI_MODE_MAX // End of modes currently supported +} sci_mode_t; + + +typedef enum e_sci_err /* SCI API error codes */ +{ + SCI_SUCCESS=0, + SCI_ERR_BAD_CHAN, // non-existent channel number + SCI_ERR_OMITTED_CHAN, // SCI_CHx_INCLUDED is 0 in config.h + SCI_ERR_CH_NOT_CLOSED, // chan still running in another mode + SCI_ERR_BAD_MODE, // unsupported or incorrect mode for channel + SCI_ERR_INVALID_ARG, // argument is not one of the predefined values + SCI_ERR_NULL_PTR, // received null ptr; missing required argument + SCI_ERR_XCVR_BUSY, // cannot start data transfer; transceiver busy + + /* Asynchronous/IrDA mode only */ + SCI_ERR_QUEUE_UNAVAILABLE, // can't open tx or rx queue or both + SCI_ERR_INSUFFICIENT_SPACE, // not enough space in transmit queue + SCI_ERR_INSUFFICIENT_DATA, // not enough data in receive queue + + /* Synchronous/SSPI modes only */ + SCI_ERR_XFER_NOT_DONE, // data transfer still in progress + + /* DTC/DMAC error */ + SCI_ERR_DTC, + SCI_ERR_DMACA, + + /* Not support when use DTC/DMAC */ + SCI_ERR_DTC_DMACA_NOT_SUPPORT + +} sci_err_t; + + +/* CHANNEL CONTROL BLOCK HANDLE */ + +typedef struct st_sci_ch_ctrl * sci_hdl_t; + + +/* SCI_OPEN() ARGUMENT DEFINITIONS (do NOT change values) */ + +typedef enum e_sci_spi_mode +{ + SCI_SPI_MODE_OFF = 1, /* channel is in synchronous mode */ + + SCI_SPI_MODE_0 = 0x80, /* SPMR Register CKPH=1, CKPOL=0 + Mode 0: 00 CPOL=0 resting lo, CPHA=0 leading edge/rising */ + SCI_SPI_MODE_1 = 0x40, /* SPMR Register CKPH=0, CKPOL=1 + Mode 1: 01 CPOL=0 resting lo, CPHA=1 trailing edge/falling */ + SCI_SPI_MODE_2 = 0xC0, /* SPMR Register CKPH=1, CKPOL=1 + Mode 2: 10 CPOL=1 resting hi, CPHA=0 leading edge/falling */ + SCI_SPI_MODE_3 = 0x00 /* SPMR Register CKPH=0, CKPOL=0 + Mode 3: 11 CPOL=1 resting hi, CPHA=1 trailing edge/rising */ +} sci_spi_mode_t; + + +/* Open() p_cfg structure when mode=SCI_MODE_ASYNC */ +typedef struct st_sci_uart +{ + uint32_t baud_rate; // ie 9600, 19200, 115200 + uint8_t clk_src; // use SCI_CLK_INT/EXT8X/EXT16X + uint8_t data_size; // use SCI_DATA_nBIT + uint8_t parity_en; // use SCI_PARITY_ON/OFF + uint8_t parity_type; // use SCI_ODD/EVEN_PARITY + uint8_t stop_bits; // use SCI_STOPBITS_1/2 + uint8_t int_priority; // interrupt priority; 1=low, 15=high +} sci_uart_t; + +/* Open() p_cfg structure when mode=SCI_MODE_IRDA */ +typedef struct st_sci_irda +{ + uint32_t baud_rate; /* ie 9600, 19200, 115200 */ + uint8_t clk_out_width; /* IrDA Output Pulse Width */ + uint8_t int_priority; /* txi, tei, rxi INT priority; 1=low, 15=high */ +} sci_irda_t; + + +/* Open() p_cfg structure when mode = SCI_MODE_SYNC or SCI_MODE_SSPI */ +typedef struct st_sci_sync_sspi +{ + sci_spi_mode_t spi_mode; // clock polarity and phase; unused for sync + uint32_t bit_rate; // ie 1000000 for 1Mbps + bool msb_first; + bool invert_data; + uint8_t int_priority; // interrupt priority; 1=low, 15=high +} sci_sync_sspi_t; + +typedef union +{ + sci_uart_t async; + sci_sync_sspi_t sync; + sci_sync_sspi_t sspi; + sci_irda_t irda; +} sci_cfg_t; + + +/* CALLBACK FUNCTION ARGUMENT DEFINITIONS */ + +typedef enum e_sci_cb_evt // callback function events +{ + /* Async/Irda Events */ + SCI_EVT_TEI, // TEI interrupt occurred; transmitter is idle + SCI_EVT_RX_CHAR, // received a character; already placed in queue + SCI_EVT_RXBUF_OVFL, // rx queue is full; can't save anymore data + SCI_EVT_FRAMING_ERR, // receiver hardware framing error + + /* Async Events */ + SCI_EVT_PARITY_ERR, // receiver hardware parity error + SCI_EVT_RX_CHAR_MATCH, // received a matched character; already placed in queue + + /* SSPI/Sync Events */ + SCI_EVT_XFER_DONE, // transfer completed + SCI_EVT_XFER_ABORTED, // transfer aborted + + /* Common Events */ + SCI_EVT_OVFL_ERR, // receiver hardware overrun error + + /* Receive Sync Done */ + SCI_EVT_RX_SYNC_DONE, + + /* Receive Async Done */ + SCI_EVT_RX_DONE +} sci_cb_evt_t; + +typedef struct st_sci_cb_args // callback arguments +{ + sci_hdl_t hdl; + sci_cb_evt_t event; + uint8_t byte; // byte read when error occurred (unused for TEI, XFER_DONE) + uint8_t num; // Number of bytes were stored to queue (used only async(FIFO)) +} sci_cb_args_t; + + +/* SCI_CONTROL() ARGUMENT DEFINITIONS */ + +/* commands */ +typedef enum e_sci_cmd +{ + /* All modes */ + SCI_CMD_CHANGE_BAUD, /* change baud/bit rate */ +#if ((SCI_CFG_CH7_FIFO_INCLUDED) || (SCI_CFG_CH8_FIFO_INCLUDED) || (SCI_CFG_CH9_FIFO_INCLUDED) || \ + (SCI_CFG_CH10_FIFO_INCLUDED) || (SCI_CFG_CH11_FIFO_INCLUDED)) + SCI_CMD_CHANGE_TX_FIFO_THRESH, /* change TX FIFO threshold */ + SCI_CMD_CHANGE_RX_FIFO_THRESH, /* change RX FIFO threshold */ +#endif + SCI_CMD_SET_RXI_PRIORITY, /* change RXI priority level */ + SCI_CMD_SET_TXI_PRIORITY, /* change TXI priority level */ + SCI_CMD_SET_TXI_RXI_PRIORITY, /* change TXI and RXI priority level simultaneously */ + + /* Async commands */ + SCI_CMD_EN_NOISE_CANCEL, /* enable noise cancellation */ + SCI_CMD_EN_TEI, /* SCI_CMD_EN_TEI is obsolete command, + but it exists only for compatibility with older version. */ + SCI_CMD_OUTPUT_BAUD_CLK, /* output baud clock on the SCK pin */ + SCI_CMD_START_BIT_EDGE, /* detect start bit as falling edge of RXDn pin + (default detect as low level on RXDn pin) */ + SCI_CMD_GENERATE_BREAK, /* generate break condition */ + SCI_CMD_COMPARE_RECEIVED_DATA, /* Compare received data with comparison data */ + + /* Async/IrDA commands */ + SCI_CMD_TX_Q_FLUSH, /* flush transmit queue */ + SCI_CMD_RX_Q_FLUSH, /* flush receive queue */ + SCI_CMD_TX_Q_BYTES_FREE, /* get count of unused transmit queue bytes */ + SCI_CMD_RX_Q_BYTES_AVAIL_TO_READ, /* get num bytes ready for reading */ + + /* Async/Sync commands */ + SCI_CMD_EN_CTS_IN, /* enable CTS input (default RTS output) */ + + /* SSPI/Sync commands */ + SCI_CMD_CHECK_XFER_DONE, /* see if send, rcv, or both are done; SCI_SUCCESS if yes */ + SCI_CMD_ABORT_XFER, + SCI_CMD_XFER_LSB_FIRST, /* start from LSB bit when sending */ + SCI_CMD_XFER_MSB_FIRST, /* start from MSB bit when sending */ + SCI_CMD_INVERT_DATA, /* logic level of send/receive data is invert */ + + /* SSPI commands */ + SCI_CMD_CHANGE_SPI_MODE, /* change clock polarity and phase in SSPI mode */ + SCI_CMD_CHECK_TX_DONE, /* see if tx requests complete; SCI_SUCCESS if yes */ + SCI_CMD_CHECK_RX_DONE, /* see if rx request complete in sync mode; SCI_SUCCESS if yes */ + SCI_CMD_CHECK_RX_SYNC_DONE, + + /*Sampling/transition timing adjust commands*/ + SCI_CMD_RX_SAMPLING_ENABLE, + SCI_CMD_RX_SAMPLING_DISABLE, + SCI_CMD_TX_TRANSITION_TIMING_ENABLE, + SCI_CMD_TX_TRANSITION_TIMING_DISABLE, + SCI_CMD_SAMPLING_TIMING_ADJUST, + SCI_CMD_TRANSITION_TIMING_ADJUST +} sci_cmd_t; + +/* SCI_CMD_CHANGE_BAUD/CHANGE_BITRATE take a ptr to this structure for *p_args */ +typedef struct st_sci_baud +{ + uint32_t pclk; // peripheral clock speed; e.g. 24000000 is 24MHz + uint32_t rate; // e.g. 9600, 19200, 115200 +} sci_baud_t; + +/* SCI_CMD_TX_Q_BYTES_FREE and SCI_CMD_RX_Q_BYTES_AVAIL_TO_READ take a pointer + to a uint16_t for p_args */ + +/* SCI_CMD_SET_RXI_PRIORITY and SCI_CMD_SET_TXI_PRIORITY take a pointer to a + uint8_t for p_args */ + +/* SCI_CMD_CHANGE_SPI_MODE takes a pointer to an sci_spi_mode_t for p_args */ + +/***************************************************************************** +Public Functions +******************************************************************************/ +/****************************************************************************** + * Function Name: R_SCI_Open + * Description : . + * Arguments : chan + * : mode + * : p_cfg + * : p_args + * : p_hdl + * Return Value : . + *****************************************************************************/ +sci_err_t R_SCI_Open (uint8_t const chan, + sci_mode_t const mode, + sci_cfg_t * const p_cfg, + void (* const p_callback)(void *p_args), + sci_hdl_t * const p_hdl); + +/****************************************************************************** + * Function Name: R_SCI_Send + * Description : . + * Arguments : hdl + * : p_src + * : length + * Return Value : . + *****************************************************************************/ +sci_err_t R_SCI_Send (sci_hdl_t const hdl, + uint8_t *p_src, + uint16_t const length); + +/****************************************************************************** + * Function Name: R_SCI_SendReceive + * Description : . + * Arguments : hdl + * : p_src + * : p_dst + * : length + * Return Value : . + *****************************************************************************/ +sci_err_t R_SCI_SendReceive (sci_hdl_t const hdl, /* SSPI/SYNC only */ + uint8_t *p_src, + uint8_t *p_dst, + uint16_t const length); + +/****************************************************************************** + * Function Name: R_SCI_Receive + * Description : . + * Arguments : hdl + * : p_dst + * : length + * Return Value : . + *****************************************************************************/ +sci_err_t R_SCI_Receive (sci_hdl_t const hdl, + uint8_t *p_dst, + uint16_t const length); + +/****************************************************************************** + * Function Name: R_SCI_Control + * Description : . + * Arguments : hdl + * : cmd + * : p_args + * Return Value : . + *****************************************************************************/ +sci_err_t R_SCI_Control (sci_hdl_t const hdl, + sci_cmd_t const cmd, + void *p_args); + +/****************************************************************************** + * Function Name: R_SCI_Close + * Description : . + * Argument : hdl + * Return Value : . + *****************************************************************************/ +sci_err_t R_SCI_Close (sci_hdl_t const hdl); + +/****************************************************************************** + * Function Name: R_SCI_GetVersion + * Description : . + * Return Value : . + *****************************************************************************/ +uint32_t R_SCI_GetVersion (void); + + +#endif /* SCI_IF_H */ + diff --git a/drivers/rx/rdp/src/r_sci_rx/src/r_sci_rx.c b/drivers/rx/rdp/src/r_sci_rx/src/r_sci_rx.c new file mode 100644 index 00000000..9b2f1d40 --- /dev/null +++ b/drivers/rx/rdp/src/r_sci_rx/src/r_sci_rx.c @@ -0,0 +1,3536 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2016-2024 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* File Name : r_sci_rx.c +* Description : Functions for using SCI on RX devices. +*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* 01.10.2016 1.80 Initial Release. (The remake of the r01an1815ju0170 to the base.) +* 19.12.2016 1.90 FIT_NO_PTR check added to NULL check. +* Fixed a bug that may receive data more than the specified number of bytes +* on Clock Synchronous Mode. +* Fixed that R_SCI_Control function returns SCI_ERR_INVALID_ARG +* when using SCI_CMD_EN_CTS_IN on Simple SPI mode. +* Fix to clear error flag even if callback function is not set. +* Deleted unnecessary bit mask of SSR register from sci_error function. +* 07.03.2017 2.00 Fixed a bug that error condition not clear when FIFO enabled. +* Fixed a bug that where commands used only when FIFO mode is enable did not NULL check. +* Fixed a bug that sending data is overwrote by new R_SCI_Send() when FIFO(async) enabled. +* Fixed a bug that sending data is break up by new R_SCI_Send() when FIFO(sync) enabled. +* Fixed a bug that the new FIFO threshold was retained only on first receive. +* Fixed a bug that callback function work many times at receive interrupt +* when FIFO(async) enabled. +* Fixed a bug that the interrupt priority level can be changed only in async mode. +* 28.09.2018 2.10 Added support RX66T +* Add WAIT_LOOP comments. +* Fixed a bug that leaking memory in R_SCI_Open() when FIFO(async) enabled. +* Fix GSCE Code Checker errors. +* 01.02.2019 2.20 Added support RX72T, RX65N-64pin. +* Fix GSCE Code Checker errors. +* 20.05.2019 3.00 Added support for GNUC and ICCRX. +* 28.06.2019 3.10 Added support for RX23W +* 15.08.2019 3.20 Added support for RX72M +* 25.11.2019 3.30 Added support RX13T. +* Modified comment of API function to Doxygen style. +* Added support for atomic control. +* Fixed to comply with GSCE Coding Standards Rev.6.00. +* Fixed a bug that error when a reception interrupt occurs before incrementing "u_tx_data.buf" +* in "sci_send_sync_data" and "sci_receive" functions +* 30.12.2019 3.40 Added support RX66N, RX72N. +* 25.08.2020 3.60 Added feature using DTC/DMAC in SCI transfer. +* Merged IrDA functionality to SCI FIT. +* 31.03.2021 3.80 Added support for RX671. +* Added support circular buffer in mode asynchronous. +* Removed usage of BYTEQ in DMAC/DTC mode. +* 15.11.2021 4.10 Added command SCI_CMD_SET_TXI_RXI_PRIORITY in R_SCI_Control() +* for changing TXI and RXI priority level simultaneously. +* Added support command SCI_CMD_SET_TXI_PRIORITY and SCI_CMD_SET_RXI_PRIORITY +* in R_SCI_Control() for Series RX100 and RX200. +* 31.03.2022 4.40 Fixed the issue with DTC mode which incorrectly uses the same transfer information +* for all channels. +* Fixed issue of consecutively calling R_SCI_Receive() function in using DTC/DMAC. +* Added support for RX660. +* 27.12.2022 4.60 Fixed the issue that rx_idle is not changed to true when reception is complete +* in DMAC mode. +* 16.02.2023 4.70 Fixed a bug in sci_send_sync_data() function with DTC mode. +* 31.03.2023 4.80 Added support for RX26T. +* Fixed to comply with GSCE Coding Standards Rev.6.5.0. +* Moved the source code which checks for IRDA mode support to MDF file. +* 29.05.2023 4.90 Added support for RX23E-B. +* Fixed to comply with GSCE Coding Standards Rev.6.5.0. +* 12.06.2023 5.00 Fixed a bug in sci_send_sync_data(), sci_receive_sync_data() and +* sci_receive_async_data() function in using DTC/DMAC. +* 31.01.2024 5.10 Added WAIT_LOOP comments. +***********************************************************************************************************************/ + +/***************************************************************************** +Includes , "Project Includes" +******************************************************************************/ +#include "platform.h" + +/* Defines for SCI support */ +#include "r_sci_rx_private.h" + +/* Include specifics for chosen MCU. */ +#include "r_sci_rx_platform.h" + +#if (SCI_CFG_ASYNC_INCLUDED || SCI_CFG_IRDA_INCLUDED) +#include "r_byteq_if.h" +#endif + + + +/***************************************************************************** +Typedef definitions +******************************************************************************/ + +/***************************************************************************** +Macro definitions +******************************************************************************/ + +/***************************************************************************** +Private global variables and functions +******************************************************************************/ +#if (SCI_CFG_ASYNC_INCLUDED) +static sci_err_t sci_init_async (sci_hdl_t const hdl, + sci_uart_t * const p_cfg, + uint8_t * const p_priority); + +static sci_err_t sci_init_queues (uint8_t const chan); +#endif + +#if (SCI_CFG_ASYNC_INCLUDED || SCI_CFG_IRDA_INCLUDED) +static sci_err_t sci_send_async_data (sci_hdl_t const hdl, + uint8_t *p_src, + uint16_t const length); + +static byteq_err_t sci_put_byte (sci_hdl_t const hdl, + uint8_t const byte); + +static void sci_transfer (sci_hdl_t const hdl); + +#if SCI_CFG_FIFO_INCLUDED +static void sci_fifo_transfer (sci_hdl_t const hdl); +#endif + +static sci_err_t sci_receive_async_data (sci_hdl_t const hdl, + uint8_t *p_dst, + uint16_t const length); +#endif + +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) +static sci_err_t sci_init_sync (sci_hdl_t const hdl, + sci_sync_sspi_t * const p_cfg, + uint8_t * const p_priority); + +static sci_err_t sci_send_sync_data (sci_hdl_t const hdl, + uint8_t *p_src, + uint8_t *p_dst, + uint16_t const length, + bool save_rx_data); + +static sci_err_t sci_receive_sync_data (sci_hdl_t const hdl, + uint8_t *p_dst, + uint16_t const length); +#endif + +static void power_on (sci_hdl_t const hdl); +static void power_off (sci_hdl_t const hdl); + +#if SCI_CFG_FIFO_INCLUDED +static sci_err_t sci_init_fifo (sci_hdl_t const hdl); +#endif + +static void sci_receive (sci_hdl_t const hdl); + +#if SCI_CFG_FIFO_INCLUDED + +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) +static void sci_fifo_receive_sync (sci_hdl_t const hdl); +#endif + +static void sci_fifo_receive (sci_hdl_t const hdl); + +#endif + +#if SCI_CFG_DATA_MATCH_INCLUDED +static void sci_receive_data_match (sci_hdl_t const hdl); +#endif + +#if ((SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) && TX_DTC_DMACA_ENABLE) +static sci_err_t sci_send_sync_data_dma_dtc (sci_hdl_t const hdl, uint8_t *p_src, uint8_t *p_dst, uint16_t const length); +#endif + +#if ((SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) && SCI_CFG_FIFO_INCLUDED && TX_DTC_DMACA_ENABLE) +static sci_err_t sci_send_sync_data_fifo_dma_dtc (sci_hdl_t const hdl, uint8_t *p_src, uint8_t *p_dst, uint16_t const length, bool save_rx_data); +#endif + +#if ((TX_DTC_DMACA_ENABLE & 0x01) && (SCI_CFG_FIFO_INCLUDED)) +static void sci_fifo_transfer_dtc (sci_hdl_t const hdl); +#endif + +#if ((TX_DTC_DMACA_ENABLE & 0x02) && (SCI_CFG_FIFO_INCLUDED)) +static void sci_fifo_transfer_dmac (sci_hdl_t const hdl); +#endif + +static void sci_error (sci_hdl_t const hdl); + +#if SCI_CFG_FIFO_INCLUDED +static void sci_fifo_error (sci_hdl_t const hdl); +#endif + +/* queue buffers */ +#if (SCI_CFG_ASYNC_INCLUDED) + +#if SCI_CFG_CH0_INCLUDED +static uint8_t ch0_tx_buf[SCI_CFG_CH0_TX_BUFSIZ]; +static uint8_t ch0_rx_buf[SCI_CFG_CH0_RX_BUFSIZ]; +#endif + +#if SCI_CFG_CH1_INCLUDED +static uint8_t ch1_tx_buf[SCI_CFG_CH1_TX_BUFSIZ]; +static uint8_t ch1_rx_buf[SCI_CFG_CH1_RX_BUFSIZ]; +#endif + +#if SCI_CFG_CH2_INCLUDED +static uint8_t ch2_tx_buf[SCI_CFG_CH2_TX_BUFSIZ]; +static uint8_t ch2_rx_buf[SCI_CFG_CH2_RX_BUFSIZ]; +#endif + +#if SCI_CFG_CH3_INCLUDED +static uint8_t ch3_tx_buf[SCI_CFG_CH3_TX_BUFSIZ]; +static uint8_t ch3_rx_buf[SCI_CFG_CH3_RX_BUFSIZ]; +#endif + +#if SCI_CFG_CH4_INCLUDED +static uint8_t ch4_tx_buf[SCI_CFG_CH4_TX_BUFSIZ]; +static uint8_t ch4_rx_buf[SCI_CFG_CH4_RX_BUFSIZ]; +#endif + +#if SCI_CFG_CH5_INCLUDED +static uint8_t ch5_tx_buf[SCI_CFG_CH5_TX_BUFSIZ]; +static uint8_t ch5_rx_buf[SCI_CFG_CH5_RX_BUFSIZ]; +#endif + +#if SCI_CFG_CH6_INCLUDED +static uint8_t ch6_tx_buf[SCI_CFG_CH6_TX_BUFSIZ]; +static uint8_t ch6_rx_buf[SCI_CFG_CH6_RX_BUFSIZ]; +#endif + +#if SCI_CFG_CH7_INCLUDED +static uint8_t ch7_tx_buf[SCI_CFG_CH7_TX_BUFSIZ]; +static uint8_t ch7_rx_buf[SCI_CFG_CH7_RX_BUFSIZ]; +#endif + +#if SCI_CFG_CH8_INCLUDED +static uint8_t ch8_tx_buf[SCI_CFG_CH8_TX_BUFSIZ]; +static uint8_t ch8_rx_buf[SCI_CFG_CH8_RX_BUFSIZ]; +#endif + +#if SCI_CFG_CH9_INCLUDED +static uint8_t ch9_tx_buf[SCI_CFG_CH9_TX_BUFSIZ]; +static uint8_t ch9_rx_buf[SCI_CFG_CH9_RX_BUFSIZ]; +#endif + +#if SCI_CFG_CH10_INCLUDED +static uint8_t ch10_tx_buf[SCI_CFG_CH10_TX_BUFSIZ]; +static uint8_t ch10_rx_buf[SCI_CFG_CH10_RX_BUFSIZ]; +#endif + +#if SCI_CFG_CH11_INCLUDED +static uint8_t ch11_tx_buf[SCI_CFG_CH11_TX_BUFSIZ]; +static uint8_t ch11_rx_buf[SCI_CFG_CH11_RX_BUFSIZ]; +#endif + +#if SCI_CFG_CH12_INCLUDED +static uint8_t ch12_tx_buf[SCI_CFG_CH12_TX_BUFSIZ]; +static uint8_t ch12_rx_buf[SCI_CFG_CH12_RX_BUFSIZ]; +#endif + +#endif /* #if (SCI_CFG_ASYNC_INCLUDED) */ + +extern const sci_hdl_t g_handles[SCI_NUM_CH]; + + +/*********************************************************************************************************************** +* Function Name: R_SCI_Open +********************************************************************************************************************//** +* @brief This function applies power to the SCI channel, initializes the associated registers, enables interrupts, and +* provides the channel handle for use with other API functions. This function must be called before calling any +* other API functions +* @param[in] chan Channel to initialize. +* +* @param[in] mode Operational mode (see enumeration below) +* @code +typedef enum e_sci_mode // SCI operational modes +{ + SCI_MODE_OFF=0, // channel not in use + SCI_MODE_ASYNC, // Asynchronous + SCI_MODE_SSPI, // Simple SPI + SCI_MODE_SYNC, // Synchronous + SCI_MODE_IRDA, // Infrared Data Association + SCI_MODE_MAX // End of modes currently supported +} sci_mode_t; +* @endcode +* @param[in] p_cfg Pointer to configuration union, structure elements (see below) are specific to mode +* @code +typedef union +{ + sci_uart_t async; + sci_sync_sspi_t sync; + sci_sync_sspi_t sspi; + sci_irda_t irda; +} sci_cfg_t; +* @endcode +* +* @param[in] p_callback Pointer to function called from interrupt when an RXI or receiver error is detected or +* for transmit end (TEI) condition. See Section 2.11 Callback Function in application note for details. +* +* @param[in] p_hdl Pointer to a handle for channel (value set here) +* Confirm the return value from R_SCI_Open is “SCI_SUCCESS” and then set the first parameter for the +* other APIs except R_SCI_GetVersion(). See Section 2.9 Parameters in the application note for details. +* +* +* @retval SCI_SUCCESS Successful; channel initialized +* +* @retval SCI_ERR_BAD_CHAN Channel number is invalid for part +* +* @retval SCI_ERR_OMITTED_CHAN Corresponding SCI_CHx_INCLUDED is invalid (0) +* +* @retval SCI_ERR_CH_NOT_CLOSED Channel currently in operation; Perform R_SCI_Close() first +* +* @retval SCI_ERR_BAD_MODE Mode specified not currently supported +* +* @retval SCI_ERR_NULL_PTR p_cfg pointer is NULL +* +* @retval SCI_ERR_INVALID_ARG An element of the p_cfg structure contains an invalid value. +* +* @retval SCI_ERR_QUEUE_UNAVAILABLE Cannot open transmit or receive queue or both (Asynchronous mode). +* @details Initializes an SCI channel for a particular mode and provides a Handle in *p_hdl for use with other API +* functions. RXI and ERI interrupts are enabled in all modes. TXI is enabled in Asynchronous mode +* @note The driver calculates the optimum values for BRR, SEMR.ABCS, and SMR.CKS using BSP_PCLKA_HZ and +* BSP_PCLKB_HZ as defined in mcu_info.h of the board support package. This however does not guarantee +* a low bit error rate for all peripheral clock/baud rate combinations. +* If an external clock is used in Asynchronous mode, the pin direction must be selected before calling the +* R_SCI_Open() function, and the pin function and mode must be selected after calling the R_SCI_Open() +* function. See Section 3. R_SCI_Open() in the application note for details. +*/ +sci_err_t R_SCI_Open (uint8_t const chan, + sci_mode_t const mode, + sci_cfg_t * const p_cfg, + void (* const p_callback)(void *p_args), + sci_hdl_t * const p_hdl) +{ + sci_err_t err = SCI_SUCCESS; + uint8_t priority = 1; + + /* CHECK ARGUMENTS */ +#if SCI_CFG_PARAM_CHECKING_ENABLE + err = sci_mcu_param_check(chan); + if (SCI_SUCCESS != err) + { + return err; + } + + /* Check argument g_handles */ + if ((NULL == g_handles[chan]) || (FIT_NO_PTR == g_handles[chan])) + { + return SCI_ERR_OMITTED_CHAN; + } + if (SCI_MODE_OFF != g_handles[chan]->mode) + { + return SCI_ERR_CH_NOT_CLOSED; + } + if ((SCI_MODE_OFF == mode) || (SCI_MODE_MAX <= mode)) + { + return SCI_ERR_BAD_MODE; + } + + /* Check argument p_cfg, p_hdl */ + if (((NULL == p_cfg) || (NULL == p_hdl)) || ((FIT_NO_PTR == p_cfg) || (FIT_NO_PTR == p_hdl))) + { + return SCI_ERR_NULL_PTR; + } +#endif + + /* INITIALIZE MODE SPECIFIC FEATURES */ + g_handles[chan]->mode = mode; + + /* APPLY POWER TO CHANNEL */ + power_on(g_handles[chan]); + + /* INITIALIZE REGISTER */ + sci_init_register(g_handles[chan]); + + /* INITIALIZE MODE SPECIFIC FEATURES */ + if (SCI_MODE_ASYNC == mode) + { +#if (SCI_CFG_ASYNC_INCLUDED) + /* Casting sci_cfg_t type to sci_uart_t type is valid */ + err = sci_init_async(g_handles[chan], (sci_uart_t *)p_cfg, &priority); +#endif + } + else if (SCI_MODE_IRDA == mode) + { +#if (SCI_CFG_IRDA_INCLUDED) + /* Casting sci_cfg_t type to sci_irda_t type is valid */ + err = sci_irda_open(chan, (sci_irda_t *)p_cfg, &priority, g_handles[chan]); +#endif + } + else + { +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + /* Casting sci_cfg_t type to sci_sync_sspi_t type is valid */ + err = sci_init_sync(g_handles[chan], (sci_sync_sspi_t *)p_cfg, &priority); +#endif + } + + if (SCI_SUCCESS != err) + { + g_handles[chan]->mode = SCI_MODE_OFF; + return err; + } + g_handles[chan]->callback = p_callback; + + /* INITIALIZE TX AND RX QUEUES ASYNC */ +#if (SCI_CFG_ASYNC_INCLUDED) + if (SCI_MODE_ASYNC == mode) + { +#if (TX_DTC_DMACA_ENABLE & 0x01 || TX_DTC_DMACA_ENABLE & 0x02) + /* DTC/DMAC don't use the queue */ + if ((SCI_DTC_ENABLE != g_handles[chan]->rom->dtc_dmaca_tx_enable) && (SCI_DMACA_ENABLE != g_handles[chan]->rom->dtc_dmaca_tx_enable)) + { + err = sci_init_queues(chan); + } +#else + err = sci_init_queues(chan); +#endif + if (SCI_SUCCESS != err) + { + g_handles[chan]->mode = SCI_MODE_OFF; + return err; + } + } +#endif + +#if SCI_CFG_FIFO_INCLUDED + if (true == g_handles[chan]->fifo_ctrl) + { + /* INITIALIZE TX AND RX FIFO */ + err = sci_init_fifo(g_handles[chan]); + if (SCI_SUCCESS != err) + { +#if (SCI_CFG_ASYNC_INCLUDED) + /* DE-INITIALIZE TX AND RX QUEUES */ + if (SCI_MODE_ASYNC == mode) + { +#if (TX_DTC_DMACA_ENABLE & 0x01 || TX_DTC_DMACA_ENABLE & 0x02) + /* DTC/DMAC don't use the queue */ + if ((SCI_DTC_ENABLE != g_handles[chan]->rom->dtc_dmaca_tx_enable) && (SCI_DMACA_ENABLE != g_handles[chan]->rom->dtc_dmaca_tx_enable)) + { + R_BYTEQ_Close(g_handles[chan]->u_tx_data.que); + R_BYTEQ_Close(g_handles[chan]->u_rx_data.que); + } +#else + R_BYTEQ_Close(g_handles[chan]->u_tx_data.que); + R_BYTEQ_Close(g_handles[chan]->u_rx_data.que); +#endif + } +#endif + g_handles[chan]->mode = SCI_MODE_OFF; + return err; + } + } +#endif + + /* ENABLE INTERRUPTS */ + sci_initialize_ints(g_handles[chan], priority); + + /* FINISH */ + *p_hdl = g_handles[chan]; + + return SCI_SUCCESS; +} /* End of function R_SCI_Open() */ + +/***************************************************************************** +* Function Name: power_on +* Description : This function provides power to the channel referenced by +* the handle by taking it out of the module stop state. +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* Return Value : none +******************************************************************************/ +static void power_on(sci_hdl_t const hdl) +{ +#if ((R_BSP_VERSION_MAJOR == 5) && (R_BSP_VERSION_MINOR >= 30)) || (R_BSP_VERSION_MAJOR >= 6) + bsp_int_ctrl_t int_ctrl; +#endif + + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_LPC_CGC_SWR); + +#if ((R_BSP_VERSION_MAJOR == 5) && (R_BSP_VERSION_MINOR >= 30)) || (R_BSP_VERSION_MAJOR >= 6) + R_BSP_InterruptControl(BSP_INT_SRC_EMPTY, BSP_INT_CMD_FIT_INTERRUPT_DISABLE, &int_ctrl); +#endif + + (*hdl->rom->mstp) &= (~hdl->rom->stop_mask); + if (SCI_MODE_IRDA == hdl->mode) + { +#if (SCI_CFG_IRDA_INCLUDED) + (*hdl->rom->mstp_irda) &= (~hdl->rom->stop_mask_irda); +#endif + } +#if ((R_BSP_VERSION_MAJOR == 5) && (R_BSP_VERSION_MINOR >= 30)) || (R_BSP_VERSION_MAJOR >= 6) + R_BSP_InterruptControl(BSP_INT_SRC_EMPTY, BSP_INT_CMD_FIT_INTERRUPT_ENABLE, &int_ctrl); +#endif + + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LPC_CGC_SWR); + + return; +} /* End of function power_on() */ + +/***************************************************************************** +* Function Name: power_off +* Description : This function removes power to the channel referenced by +* handle by putting it into the module stop state. +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* Return Value : none +******************************************************************************/ +static void power_off(sci_hdl_t const hdl) +{ +#if ((R_BSP_VERSION_MAJOR == 5) && (R_BSP_VERSION_MINOR >= 30)) || (R_BSP_VERSION_MAJOR >= 6) + bsp_int_ctrl_t int_ctrl; +#endif + + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_LPC_CGC_SWR); + +#if ((R_BSP_VERSION_MAJOR == 5) && (R_BSP_VERSION_MINOR >= 30)) || (R_BSP_VERSION_MAJOR >= 6) + R_BSP_InterruptControl(BSP_INT_SRC_EMPTY, BSP_INT_CMD_FIT_INTERRUPT_DISABLE, &int_ctrl); +#endif + + (*hdl->rom->mstp) |= (hdl->rom->stop_mask); + if (SCI_MODE_IRDA == hdl->mode) + { +#if (SCI_CFG_IRDA_INCLUDED) + (*hdl->rom->mstp_irda) |= (hdl->rom->stop_mask_irda); +#endif + } +#if ((R_BSP_VERSION_MAJOR == 5) && (R_BSP_VERSION_MINOR >= 30)) || (R_BSP_VERSION_MAJOR >= 6) + R_BSP_InterruptControl(BSP_INT_SRC_EMPTY, BSP_INT_CMD_FIT_INTERRUPT_ENABLE, &int_ctrl); +#endif + + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LPC_CGC_SWR); + + return; +} /* End of function power_off() */ + +#if (SCI_CFG_ASYNC_INCLUDED) +/***************************************************************************** +* Function Name: sci_init_queues +* Description : This function attaches transmit and receive queues to the +* channel. +* +* Arguments : chan - +* channel (ptr to chan control block) +* Return Value : SCI_SUCCESS - +* channel initialized successfully +* SCI_ERR_QUEUE_UNAVAILABLE - +* no queue control blocks available +******************************************************************************/ +static sci_err_t sci_init_queues(uint8_t const chan) +{ + byteq_err_t q_err1 = BYTEQ_ERR_INVALID_ARG; + byteq_err_t q_err2 = BYTEQ_ERR_INVALID_ARG; + sci_err_t err = SCI_SUCCESS; + + /* channel number verified as legal prior to calling this function */ + switch (chan) + { +#if SCI_CFG_CH0_INCLUDED + case (SCI_CH0): + { + q_err1 = R_BYTEQ_Open(ch0_tx_buf, SCI_CFG_CH0_TX_BUFSIZ, &g_handles[SCI_CH0]->u_tx_data.que); + q_err2 = R_BYTEQ_Open(ch0_rx_buf, SCI_CFG_CH0_RX_BUFSIZ, &g_handles[SCI_CH0]->u_rx_data.que); + break; + } +#endif +#if SCI_CFG_CH1_INCLUDED + case (SCI_CH1): + { + q_err1 = R_BYTEQ_Open(ch1_tx_buf, SCI_CFG_CH1_TX_BUFSIZ, &g_handles[SCI_CH1]->u_tx_data.que); + q_err2 = R_BYTEQ_Open(ch1_rx_buf, SCI_CFG_CH1_RX_BUFSIZ, &g_handles[SCI_CH1]->u_rx_data.que); + break; + } +#endif +#if SCI_CFG_CH2_INCLUDED + case (SCI_CH2): + { + q_err1 = R_BYTEQ_Open(ch2_tx_buf, SCI_CFG_CH2_TX_BUFSIZ, &g_handles[SCI_CH2]->u_tx_data.que); + q_err2 = R_BYTEQ_Open(ch2_rx_buf, SCI_CFG_CH2_RX_BUFSIZ, &g_handles[SCI_CH2]->u_rx_data.que); + break; + } +#endif +#if SCI_CFG_CH3_INCLUDED + case (SCI_CH3): + { + q_err1 = R_BYTEQ_Open(ch3_tx_buf, SCI_CFG_CH3_TX_BUFSIZ, &g_handles[SCI_CH3]->u_tx_data.que); + q_err2 = R_BYTEQ_Open(ch3_rx_buf, SCI_CFG_CH3_RX_BUFSIZ, &g_handles[SCI_CH3]->u_rx_data.que); + break; + } +#endif +#if SCI_CFG_CH4_INCLUDED + case (SCI_CH4): + { + q_err1 = R_BYTEQ_Open(ch4_tx_buf, SCI_CFG_CH4_TX_BUFSIZ, &g_handles[SCI_CH4]->u_tx_data.que); + q_err2 = R_BYTEQ_Open(ch4_rx_buf, SCI_CFG_CH4_RX_BUFSIZ, &g_handles[SCI_CH4]->u_rx_data.que); + break; + } +#endif +#if SCI_CFG_CH5_INCLUDED + case (SCI_CH5): + { + q_err1 = R_BYTEQ_Open(ch5_tx_buf, SCI_CFG_CH5_TX_BUFSIZ, &g_handles[SCI_CH5]->u_tx_data.que); + q_err2 = R_BYTEQ_Open(ch5_rx_buf, SCI_CFG_CH5_RX_BUFSIZ, &g_handles[SCI_CH5]->u_rx_data.que); + break; + } +#endif +#if SCI_CFG_CH6_INCLUDED + case (SCI_CH6): + { + q_err1 = R_BYTEQ_Open(ch6_tx_buf, SCI_CFG_CH6_TX_BUFSIZ, &g_handles[SCI_CH6]->u_tx_data.que); + q_err2 = R_BYTEQ_Open(ch6_rx_buf, SCI_CFG_CH6_RX_BUFSIZ, &g_handles[SCI_CH6]->u_rx_data.que); + break; + } +#endif +#if SCI_CFG_CH7_INCLUDED + case (SCI_CH7): + { + q_err1 = R_BYTEQ_Open(ch7_tx_buf, SCI_CFG_CH7_TX_BUFSIZ, &g_handles[SCI_CH7]->u_tx_data.que); + q_err2 = R_BYTEQ_Open(ch7_rx_buf, SCI_CFG_CH7_RX_BUFSIZ, &g_handles[SCI_CH7]->u_rx_data.que); + break; + } +#endif +#if SCI_CFG_CH8_INCLUDED + case (SCI_CH8): + { + q_err1 = R_BYTEQ_Open(ch8_tx_buf, SCI_CFG_CH8_TX_BUFSIZ, &g_handles[SCI_CH8]->u_tx_data.que); + q_err2 = R_BYTEQ_Open(ch8_rx_buf, SCI_CFG_CH8_RX_BUFSIZ, &g_handles[SCI_CH8]->u_rx_data.que); + break; + } +#endif +#if SCI_CFG_CH9_INCLUDED + case (SCI_CH9): + { + q_err1 = R_BYTEQ_Open(ch9_tx_buf, SCI_CFG_CH9_TX_BUFSIZ, &g_handles[SCI_CH9]->u_tx_data.que); + q_err2 = R_BYTEQ_Open(ch9_rx_buf, SCI_CFG_CH9_RX_BUFSIZ, &g_handles[SCI_CH9]->u_rx_data.que); + break; + } +#endif +#if SCI_CFG_CH10_INCLUDED + case (SCI_CH10): + { + q_err1 = R_BYTEQ_Open(ch10_tx_buf, SCI_CFG_CH10_TX_BUFSIZ, &g_handles[SCI_CH10]->u_tx_data.que); + q_err2 = R_BYTEQ_Open(ch10_rx_buf, SCI_CFG_CH10_RX_BUFSIZ, &g_handles[SCI_CH10]->u_rx_data.que); + break; + } +#endif +#if SCI_CFG_CH11_INCLUDED + case (SCI_CH11): + { + q_err1 = R_BYTEQ_Open(ch11_tx_buf, SCI_CFG_CH11_TX_BUFSIZ, &g_handles[SCI_CH11]->u_tx_data.que); + q_err2 = R_BYTEQ_Open(ch11_rx_buf, SCI_CFG_CH11_RX_BUFSIZ, &g_handles[SCI_CH11]->u_rx_data.que); + break; + } +#endif +#if SCI_CFG_CH12_INCLUDED + case (SCI_CH12): + { + q_err1 = R_BYTEQ_Open(ch12_tx_buf, SCI_CFG_CH12_TX_BUFSIZ, &g_handles[SCI_CH12]->u_tx_data.que); + q_err2 = R_BYTEQ_Open(ch12_rx_buf, SCI_CFG_CH12_RX_BUFSIZ, &g_handles[SCI_CH12]->u_rx_data.que); + break; + } +#endif + default: + { + err = SCI_ERR_QUEUE_UNAVAILABLE; + break; + } + } + + if ((BYTEQ_SUCCESS != q_err1) || (BYTEQ_SUCCESS != q_err2)) + { + err = SCI_ERR_QUEUE_UNAVAILABLE; + } + return err; +} /* End of function sci_init_queues() */ +#endif /* End of SCI_CFG_ASYNC_INCLUDED */ + +#if SCI_CFG_FIFO_INCLUDED +/***************************************************************************** +* Function Name: sci_init_fifo +* Description : This function the setting of the FIFO mode, reset of the +* TX/RX FIFO, and the threshold setting of the TX/RX FIFO. +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* Return Value : SCI_SUCCESS - +* fifo initialized successfully +* SCI_ERR_INVALID_ARG - +* element of hdl contains illegal value +******************************************************************************/ +static sci_err_t sci_init_fifo(sci_hdl_t const hdl) +{ + /* CHECK ARGUMENTS */ +#if SCI_CFG_PARAM_CHECKING_ENABLE + if (hdl->tx_dflt_thresh > 15) + { + return SCI_ERR_INVALID_ARG; + } + if ((hdl->rx_dflt_thresh < 1) || (hdl->rx_dflt_thresh > 15)) + { + return SCI_ERR_INVALID_ARG; + } +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + if (hdl->tx_dflt_thresh != hdl->rx_dflt_thresh) + { + return SCI_ERR_INVALID_ARG; + } +#endif +#endif + + /* FIFO Mode Select (1:FIFO mode) */ + hdl->rom->regs->FCR.BIT.FM = 0x01; + + /* reset TX/RX FIFO */ + hdl->rom->regs->FCR.BIT.TFRST = 0x01; + hdl->rom->regs->FCR.BIT.RFRST = 0x01; + + /* set TX/RX FIFO threshold initial value */ + hdl->rom->regs->FCR.BIT.TTRG = hdl->tx_dflt_thresh; + hdl->rom->regs->FCR.BIT.RTRG = hdl->rx_dflt_thresh; + + return SCI_SUCCESS; +} /* End of function sci_init_fifo() */ +#endif /* End of SCI_CFG_FIFO_INCLUDED */ + +#if (SCI_CFG_ASYNC_INCLUDED) +/***************************************************************************** +* Function Name: sci_init_async +* Description : This function initializes the control block and UART +* registers for an SCI channel. +* +* NOTE: p_cfg is checked to be non-NULL prior to this function. +* The TE and RE bits in SCR must be 0 prior to calling this function. +* +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* p_cfg - +* ptr to Uart configuration argument structure +* p_priority - +* pointer to location to load interrupt priority into +* Return Value : SCI_SUCCESS - +* channel initialized successfully +* SCI_ERR_INVALID_ARG - +* element of p_cfg contains illegal value +******************************************************************************/ +static sci_err_t sci_init_async(sci_hdl_t const hdl, + sci_uart_t * const p_cfg, + uint8_t * const p_priority) +{ + sci_err_t err=SCI_SUCCESS; + int32_t bit_err; + + /* Check arguments */ + +#if SCI_CFG_PARAM_CHECKING_ENABLE + if (((SCI_DATA_8BIT != p_cfg->data_size) && (SCI_DATA_7BIT != p_cfg->data_size)) + || ((SCI_STOPBITS_1 != p_cfg->stop_bits) && (SCI_STOPBITS_2 != p_cfg->stop_bits)) + || ((p_cfg->int_priority < (BSP_MCU_IPL_MIN+1)) || (p_cfg->int_priority > BSP_MCU_IPL_MAX))) + { + return SCI_ERR_INVALID_ARG; + } + + if (SCI_PARITY_ON == p_cfg->parity_en) + { + if ((SCI_EVEN_PARITY != p_cfg->parity_type) && (SCI_ODD_PARITY != p_cfg->parity_type)) + { + return SCI_ERR_INVALID_ARG; + } + } + else if (SCI_PARITY_OFF != p_cfg->parity_en) + { + return SCI_ERR_INVALID_ARG; + } + else + { + /* Do Nothing */ + } + if (SCI_CLK_INT == p_cfg->clk_src) + { + if (0 == p_cfg->baud_rate) + { + return SCI_ERR_INVALID_ARG; + } + } + else if ((SCI_CLK_EXT8X != p_cfg->clk_src) && (SCI_CLK_EXT16X != p_cfg->clk_src)) + { + return SCI_ERR_INVALID_ARG; + } + else + { + /* Do Nothing */ + } +#endif /* End of SCI_CFG_PARAM_CHECKING_ENABLE */ + + + /* Initialize channel control block flags */ + hdl->tx_idle = true; + +#if (RX_DTC_DMACA_ENABLE & 0x01 || RX_DTC_DMACA_ENABLE & 0x02) + /* Initialize receive flag when using DTC/DMAC */ + if ((SCI_DTC_ENABLE == hdl->rom->dtc_dmaca_rx_enable) || (SCI_DMACA_ENABLE == hdl->rom->dtc_dmaca_rx_enable)) + { + hdl->rx_idle = true; + } +#endif + + /* Configure SMR for asynchronous mode, single processor, and user settings */ + if (SCI_PARITY_OFF == p_cfg->parity_en) + { + p_cfg->parity_type = 0; // ensure random value is not ORed into SMR + } + + /* Configure SMR */ + hdl->rom->regs->SMR.BYTE = (uint8_t)((p_cfg->data_size | p_cfg->stop_bits) | (p_cfg->parity_en | p_cfg->parity_type)); + + /* SETUP CLOCK FOR BAUD RATE */ + + if (SCI_CLK_INT == p_cfg->clk_src) + { + /* Use internal clock for baud rate */ + bit_err = sci_init_bit_rate(hdl, hdl->pclk_speed, p_cfg->baud_rate); + if (1000 == bit_err) + { + err = SCI_ERR_INVALID_ARG; // impossible baud rate; 100% error + } + else + { + hdl->baud_rate = p_cfg->baud_rate; // save baud rate for break generation + } +#if SCI_CFG_RX_DATA_SAMPLING_TIMING_INCLUDED + hdl->rom->regs->SPTR.BIT.RTADJ = 1; /* Enable receive data sampling timing adjust*/ +#endif + +#if SCI_CFG_TX_SIGNAL_TRANSITION_TIMING_INCLUDED + hdl->rom->regs->SPTR.BIT.TTADJ = 1; /* Enable transmit signal transition timing adjust*/ +#endif + } + else + { + /* Use external clock for baud rate */ + hdl->rom->regs->SCR.BIT.CKE = 0x02; + hdl->rom->regs->SEMR.BIT.ABCS = (SCI_CLK_EXT8X == p_cfg->clk_src) ? 1 : 0; + } + + *p_priority = p_cfg->int_priority; + return err; +} /* End of function sci_init_async() */ +#endif /* End of SCI_CFG_ASYNC_INCLUDED */ + +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) +/***************************************************************************** +* Function Name: sci_init_sync +* Description : This function initializes the control block and SYNC/SSPI +* registers for an SCI channel. +* +* NOTE: p_cfg is checked to be non-NULL prior to this function. +* The TE and RE bits in SCR must be 0 prior to calling this function. +* +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* p_cfg - +* ptr to SSPI configuration argument structure +* p_priority - +* pointer to location to load interrupt priority into +* Return Value : SCI_SUCCESS - +* channel initialized successfully +* SCI_ERR_INVALID_ARG - +* element of p_cfg contains illegal value +******************************************************************************/ +static sci_err_t sci_init_sync (sci_hdl_t const hdl, + sci_sync_sspi_t * const p_cfg, + uint8_t * const p_priority) +{ + sci_err_t err = SCI_SUCCESS; + int32_t bit_err; + + + /* Check arguments */ + +#if SCI_CFG_PARAM_CHECKING_ENABLE + if ((SCI_MODE_SSPI == hdl->mode) + && (SCI_SPI_MODE_0 != p_cfg->spi_mode) && (SCI_SPI_MODE_1 != p_cfg->spi_mode) + && (SCI_SPI_MODE_2 != p_cfg->spi_mode) && (SCI_SPI_MODE_3 != p_cfg->spi_mode)) + { + return SCI_ERR_INVALID_ARG; + } + else if ((SCI_MODE_SYNC == hdl->mode) && (SCI_SPI_MODE_OFF != p_cfg->spi_mode)) + { + return SCI_ERR_INVALID_ARG; + } + else + { + /* Do Nothing */ + } + + if (0 == p_cfg->bit_rate) + { + return SCI_ERR_INVALID_ARG; + } + + if ((0 == p_cfg->int_priority) || (p_cfg->int_priority > BSP_MCU_IPL_MAX)) + { + return SCI_ERR_INVALID_ARG; + } +#endif + + /* Initialize channel control block flags */ + hdl->tx_idle = true; + hdl->tx_dummy = false; + + /* Configure SMR for SSPI/SYNC mode */ + hdl->rom->regs->SMR.BYTE = 0x80; + hdl->rom->regs->SCMR.BIT.SMIF = 0; /* default */ + hdl->rom->regs->SIMR1.BIT.IICM = 0; /* default */ + + /* Configure SPI register for clock polarity/phase and single master */ + if (SCI_MODE_SSPI == hdl->mode) + { + hdl->rom->regs->SPMR.BYTE = p_cfg->spi_mode; + } + else /* synchronous operation */ + { + hdl->rom->regs->SPMR.BYTE = 0; + } + + /* Configure data inversion */ + hdl->rom->regs->SCMR.BIT.SINV = (uint8_t)((true == p_cfg->invert_data) ? 1 : 0); + + /* Configure bit order */ + hdl->rom->regs->SCMR.BIT.SDIR = (uint8_t)((true == p_cfg->msb_first) ? 1 : 0); + + + /* SETUP CLOCK FOR BIT RATE */ + + /* Use internal clock for bit rate (master) */ + bit_err = sci_init_bit_rate(hdl, hdl->pclk_speed, p_cfg->bit_rate); + if (1000 == bit_err) + { + err = SCI_ERR_INVALID_ARG; /* impossible bit rate; 100% error */ + } + + *p_priority = p_cfg->int_priority; + return err; +} /* End of function sci_init_sync() */ +#endif /* End of SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED */ + + +/*********************************************************************************************************************** +* Function Name: R_SCI_Send +********************************************************************************************************************//** +* @brief When Asynchronous Mode and DTC/DMAC are not used, queues data for later transmit. In other modes initiates +* transmit if transmitter is not in use. +* +* @param[in] hdl Handle for channel. Set hdl when R_SCI_Open() is successfully processed. +* +* @param[in] p_src Pointer to data to transmit +* +* @param[in] length Number of bytes to send +* +* @retval SCI_SUCCESS Transmit initiated or loaded into queue (When Asynchronous Mode and DTC/DMAC are not used) +* +* @retval SCI_ERR_NULL_PTR hdl value is NULL +* +* @retval SCI_ERR_BAD_MODE Mode specified not currently supported +* +* @retval SCI_ERR_INSUFFICIENT_SPACE Insufficient space in queue to load all data (When Asynchronous Mode and +* DTC/DMAC are not used) +* +* @retval SCI_ERR_XCVR_BUSY Channel currently busy (SSPI/Synchronous/When Asynchronous Mode and circular buffer is +* not used/When Asynchronous Mode and DTC/DMAC are used) +* +* +* @details When Asynchronous Mode and DTC/DMAC are not used, this function places data into a transmit queue if the +* transmitter for the SCI channel referenced by the handle is not in use. When circular buffer +* (SCI_CFG_USE_CIRCULAR_BUFFER (1)) is used, the function allows data to be put on a transmit queue during transmission. +* When Asynchronous Mode and DTC/DMAC are used, this function registers DTC/DMAC setting and specifies to the TXI and +* transmission begins immediately if the transmitter is not already in use. +* In SSPI and Synchronous modes, no data is queued and transmission begins immediately if the transceiver +* is not already in use.\n +* Note that the toggling of Slave Select lines when in SSPI mode is not handled by this driver. The Slave Select line +* for the target device must be enabled prior to calling this function. +* Also, toggling of the CTS/RTS pin in Synchronous/Asynchronous mode is not handled by this driver. +* @note None +*/ +sci_err_t R_SCI_Send(sci_hdl_t const hdl, + uint8_t *p_src, + uint16_t const length) +{ + sci_err_t err=SCI_SUCCESS; + + /* Check arguments */ + +#if SCI_CFG_PARAM_CHECKING_ENABLE + /* Check argument hdl, p_src */ + if (((NULL == hdl) || (FIT_NO_PTR == hdl)) || ((NULL == p_src) || (FIT_NO_PTR == p_src))) + { + return SCI_ERR_NULL_PTR; + } + if ((SCI_MODE_OFF == hdl->mode) || (SCI_MODE_MAX <= hdl->mode)) + { + return SCI_ERR_BAD_MODE; + } + if (0 == length) + { + return SCI_ERR_INVALID_ARG; + } +#endif + + if ((SCI_MODE_ASYNC == hdl->mode) || (SCI_MODE_IRDA == hdl->mode)) + { + /* ASYNC or IRDA */ +#if (SCI_CFG_ASYNC_INCLUDED || SCI_CFG_IRDA_INCLUDED) + err = sci_send_async_data(hdl, p_src, length); +#endif + } + else + { + /* SSPI or SYNC */ +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + err = sci_send_sync_data(hdl, p_src, NULL, length, false); +#endif + } + + return err; +} /* End of function R_SCI_Send() */ + + +#if (SCI_CFG_ASYNC_INCLUDED || SCI_CFG_IRDA_INCLUDED) +/***************************************************************************** +* Function Name: sci_send_async_data +* Description : This function determines if the tx byte queue of the channel +* referenced by the handle is not full, and call the byte +* transmission function. +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* p_src - +* ptr to data to transmit +* length - +* number of bytes to send and possibly receive +* Return Value : SCI_SUCCESS - +* data transfer started +* SCI_ERR_XCVR_BUSY - +* channel currently busy +* SCI_ERR_INSUFFICIENT_SPACE - +* not enough space in tx queue to store data (Async) +******************************************************************************/ +static sci_err_t sci_send_async_data(sci_hdl_t const hdl, + uint8_t *p_src, + uint16_t const length) +{ + sci_err_t err = SCI_SUCCESS; + uint16_t cnt; + byteq_err_t byteq_err = BYTEQ_ERR_QUEUE_FULL; +#if (SCI_CFG_USE_CIRCULAR_BUFFER == 1) +#if (TX_DTC_DMACA_ENABLE & 0x01 || TX_DTC_DMACA_ENABLE & 0x02) + /* Keep checking tx_idle when using DTC/DMAC */ + if (SCI_DTC_ENABLE == hdl->rom->dtc_dmaca_tx_enable || SCI_DMACA_ENABLE == hdl->rom->dtc_dmaca_tx_enable) + { + if (true != hdl->tx_idle ) + { + return SCI_ERR_XCVR_BUSY; + } + } +#endif +#else + if (true != hdl->tx_idle) + { + return SCI_ERR_XCVR_BUSY; + } +#endif +#if SCI_CFG_FIFO_INCLUDED + if (true == hdl->fifo_ctrl) + { +#if (SCI_CFG_USE_CIRCULAR_BUFFER == 1) +#if (TX_DTC_DMACA_ENABLE & 0x01 || TX_DTC_DMACA_ENABLE & 0x02) + /* Keep checking tx_idle when using DTC/DMAC */ + if (SCI_DTC_ENABLE == hdl->rom->dtc_dmaca_tx_enable || SCI_DMACA_ENABLE == hdl->rom->dtc_dmaca_tx_enable) + { + /* TX FIFO use check */ + if (0x00 < hdl->rom->regs->FDR.BIT.T) + { + return SCI_ERR_XCVR_BUSY; + } + /* reset TX FIFO */ + hdl->rom->regs->FCR.BIT.TFRST = 0x01; + } +#endif +#else + /* TX FIFO use check */ + if (0x00 < hdl->rom->regs->FDR.BIT.T) + { + return SCI_ERR_XCVR_BUSY; + } + + /* reset TX FIFO */ + hdl->rom->regs->FCR.BIT.TFRST = 0x01; +#endif + +#if (TX_DTC_DMACA_ENABLE != 0) + sci_fifo_ctrl_t *p_tctrl; + p_tctrl = &hdl->queue[hdl->qindex_app_tx]; + p_tctrl->p_tx_buf = p_src; /* dummy byte sent when NULL (Sync) */ + p_tctrl->tx_cnt = length; /* length must be set after buf ptr */ + p_tctrl->total_length = length; /* used for dtc in txi_handler */ + +#if (TX_DTC_DMACA_ENABLE) + p_tctrl->p_tx_fraction_buf = p_src; + p_tctrl->tx_fraction = length; +#endif +#endif + +#if (TX_DTC_DMACA_ENABLE & 0x01) + + if (SCI_DTC_ENABLE == hdl->rom->dtc_dmaca_tx_enable) + { + err = sci_txfifo_dtc_create(hdl, p_src, length); + } + else +#endif + { +#if (TX_DTC_DMACA_ENABLE & 0x02) + if (SCI_DMACA_ENABLE == hdl->rom->dtc_dmaca_tx_enable) + { + err = sci_txfifo_dmaca_create(hdl, p_src, length); + } + else +#endif + { + /* Determine amount of space left in tx queue */ + R_BYTEQ_Unused(hdl->u_tx_data.que, &cnt); + if (cnt < length) + { + /* If can't fit, return */ + return SCI_ERR_INSUFFICIENT_SPACE; + } + + /* Else load bytes into tx queue for transmission */ + /* WAIT_LOOP */ + for (cnt = 0; cnt < length; cnt++) + { +#if (SCI_CFG_USE_CIRCULAR_BUFFER == 1) + byteq_err = sci_put_byte(hdl, *p_src++); + + /* Allow TX interrupt occur */ + ENABLE_TXI_INT; +#else + byteq_err = sci_put_byte(hdl, *p_src++); +#endif + if (BYTEQ_SUCCESS != byteq_err) + { + /* If the return value is not BYTEQ_SUCCESS. */ + err = SCI_ERR_INSUFFICIENT_SPACE; + break; + } + } + } + } + } + else /*that channel do not use FIFO but SCI_CFG_FIFO_INCLUDED == true*/ +#endif /* SCI_CFG_FIFO_INCLUDED */ + { +#if (TX_DTC_DMACA_ENABLE & 0x01) + if (SCI_DTC_ENABLE == hdl->rom->dtc_dmaca_tx_enable) + { + err = sci_tx_dtc_create(hdl, p_src, length); + } + else + +#endif + { +#if (TX_DTC_DMACA_ENABLE & 0x02) + if (SCI_DMACA_ENABLE == hdl->rom->dtc_dmaca_tx_enable) + { + err = sci_tx_dmaca_create(hdl, p_src, length); + } + else +#endif + { + /* Determine amount of space left in tx queue */ + R_BYTEQ_Unused(hdl->u_tx_data.que, &cnt); + + if (cnt < length) + { + /* If can't fit, return */ + return SCI_ERR_INSUFFICIENT_SPACE; + } + + /* Else load bytes into tx queue for transmission */ + /* WAIT_LOOP */ + for (cnt = 0; cnt < length; cnt++) + { +#if (SCI_CFG_USE_CIRCULAR_BUFFER == 1) + byteq_err = sci_put_byte(hdl, *p_src++); + ENABLE_TXI_INT; +#else + byteq_err = sci_put_byte(hdl, *p_src++); +#endif + if (BYTEQ_SUCCESS != byteq_err) + { + /* If the return value is not BYTEQ_SUCCESS. */ + err = SCI_ERR_INSUFFICIENT_SPACE; + break; + } + } + } + } + } +#if (SCI_CFG_USE_CIRCULAR_BUFFER == 1) +#if (TX_DTC_DMACA_ENABLE & 0x01 || TX_DTC_DMACA_ENABLE & 0x02) + /* Keep checking tx_idle when using DTC/DMAC */ + if (SCI_DTC_ENABLE == hdl->rom->dtc_dmaca_tx_enable || SCI_DMACA_ENABLE == hdl->rom->dtc_dmaca_tx_enable) + { + if (SCI_SUCCESS == err) + { + hdl->tx_idle = false; + ENABLE_TXI_INT; + } + } +#endif +#else + if (SCI_SUCCESS == err) + { + hdl->tx_idle = false; + ENABLE_TXI_INT; + } +#endif + + + return err; +} /* End of function sci_send_async_data() */ + +/***************************************************************************** +* Function Name: sci_put_byte +* Description : Transmits byte if channel is not busy. Otherwise, byte is +* stored in tx queue until can transmit. If buffer is full +* and cannot store it, an error code is returned. +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* byte - +* byte to transmit +* Return Value : SCI_SUCCESS - +* data transfer started +* SCI_ERR_INSUFFICIENT_SPACE - +* not enough space in tx queue to store data (Async) +******************************************************************************/ +static byteq_err_t sci_put_byte(sci_hdl_t const hdl, + uint8_t const byte) +{ + byteq_err_t err = BYTEQ_ERR_QUEUE_FULL; + + /* else load next byte into tx queue (space checked in calling func) */ + err = R_BYTEQ_Put(hdl->u_tx_data.que, byte); + + return err; +} /* End of function sci_put_byte() */ +#endif /* SCI_CFG_ASYNC_INCLUDED || SCI_CFG_IRDA_INCLUDED */ + + +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) +/***************************************************************************** +* Function Name: sci_send_sync_data +* Description : This function determines if the channel referenced by the +* handle is not busy, and begins the data transfer process +* (both sending and receiving data). +* +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* p_src - +* ptr to data to transmit +* p_dst - +* ptr to buffer to store receive data (optional) +* length - +* number of bytes to send and possibly receive +* save_rx_data - +* true if data clocked in should be saved to p_dst. +* Return Value : SCI_SUCCESS - +* data transfer started +* SCI_ERR_XCVR_BUSY - +* channel currently busy +******************************************************************************/ +static sci_err_t sci_send_sync_data(sci_hdl_t const hdl, + uint8_t *p_src, + uint8_t *p_dst, + uint16_t const length, + bool save_rx_data) +{ +#if SCI_CFG_FIFO_INCLUDED + uint8_t cnt; + volatile uint8_t thresh_cnt; +#endif + sci_err_t err = SCI_SUCCESS; + + if (true == hdl->tx_idle) + { + + if (true == save_rx_data) + { + hdl->u_rx_data.buf = p_dst; + } + hdl->save_rx_data = save_rx_data; + + hdl->u_tx_data.buf = p_src; + hdl->tx_cnt = length; + hdl->rx_cnt = length; + hdl->tx_dummy = false; + +#if SCI_CFG_FIFO_INCLUDED + if (true == hdl->fifo_ctrl) + { + /* reset TX FIFO */ + hdl->rom->regs->FCR.BIT.TFRST = 0x01; + + /* reset RX FIFO */ + hdl->rom->regs->FCR.BIT.RFRST = 0x01; + +#if (TX_DTC_DMACA_ENABLE && RX_DTC_DMACA_ENABLE) + if ((SCI_DTC_ENABLE == hdl->rom->dtc_dmaca_rx_enable) || (SCI_DMACA_ENABLE == hdl->rom->dtc_dmaca_rx_enable)) + { + err = sci_send_sync_data_fifo_dma_dtc(hdl, p_src, p_dst, length, false); + } + else +#endif + { + /* Transmitter is in use */ + hdl->tx_idle = false; + + /* If length is lower than SCI_CFG_CHXX_RX_FIFO_THRESH, FCR.BIT.RTRG register is set to length */ + if (length < hdl->rx_curr_thresh) + { + hdl->rom->regs->FCR.BIT.RTRG = length; + } + + thresh_cnt = hdl->rom->regs->FCR.BIT.RTRG; + + hdl->tx_cnt -= thresh_cnt; + + /* Repeated FIFO RX threshold count */ + /* WAIT_LOOP */ + for (cnt = 0; cnt < thresh_cnt; cnt++) + { + if(0 != cnt) + { + hdl->u_tx_data.buf++; + } + SCI_TDR(*hdl->u_tx_data.buf); /* start transmit */ + } + } + } + else +#endif /* SCI_CFG_FIFO_INCLUDED */ + { +#if (TX_DTC_DMACA_ENABLE & 0x01) + if (SCI_DTC_ENABLE == hdl->rom->dtc_dmaca_tx_enable) + { + if(true == hdl->save_rx_data) + { + err = sci_send_sync_data_dma_dtc(hdl, p_src, p_dst, length); + } + else + { + err = sci_send_sync_data_dma_dtc(hdl, p_src, NULL, length); + } + return err; + } + else +#endif + { +#if (TX_DTC_DMACA_ENABLE & 0x02) + if (SCI_DMACA_ENABLE == hdl->rom->dtc_dmaca_tx_enable) + { + if(true == hdl->save_rx_data) + { + err = sci_send_sync_data_dma_dtc(hdl, p_src, p_dst, length); + } + else + { + err = sci_send_sync_data_dma_dtc(hdl, p_src, NULL, length); + } + + return err; + } + else +#endif + { + /* Transmitter is in use */ + hdl->tx_idle = false; + + hdl->tx_cnt--; + SCI_TDR(*hdl->u_tx_data.buf); /* start transmit */ + } + } + } + return err; + } + return SCI_ERR_XCVR_BUSY; +} /* End of function sci_send_sync_data() */ +#endif /* SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED */ + +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) +/*********************************************************************************************************************** +* Function Name: R_SCI_SendReceive +********************************************************************************************************************//** +* @brief For Synchronous and SSPI modes only. Transmits and receives data simultaneously if the transceiver is not +* in use. +* +* @param[in] hdl Handle for channel. Set hdl when R_SCI_Open() is successfully processed. +* @param[in] p_src Pointer to data to transmit +* +* @param[in] p_dst Pointer to buffer to load data into +* +* @param[in] length Number of bytes to send +* +* @retval SCI_SUCCESS Data transfer initiated +* +* @retval SCI_ERR_NULL_PTR hdl value is NULL +* +* @retval SCI_ERR_BAD_MODE Channel mode not SSPI or Synchronous +* +* @retval SCI_ERR_XCVR_BUSY Channel currently busy +* @details If the transceiver is not in use, this function clocks out data from the p_src buffer while simultaneously +* clocking in data and placing it in the p_dst buffer. +* Note that the toggling of Slave Select lines for SSPI is not handled by this driver. The Slave Select line for +* the target device must be enabled prior to calling this function. +* Also, toggling of the CTS/RTS pin in Synchronous/Asynchronous mode is not handled by this driver. +* +* @note See section 2.11 Callback Function in application note for values passed to arguments of the callback function. +*/ +sci_err_t R_SCI_SendReceive(sci_hdl_t const hdl, + uint8_t *p_src, + uint8_t *p_dst, + uint16_t const length) +{ + sci_err_t err; + +#if SCI_CFG_PARAM_CHECKING_ENABLE + /* Check arguments */ + if ((((NULL == hdl) || (FIT_NO_PTR == hdl)) /* Check if hdl is available or not */ + || ((NULL == p_src) || (FIT_NO_PTR == p_src))) /* Check if p_src is available or not */ + || ((NULL == p_dst) || (FIT_NO_PTR == p_dst))) /* Check if p_dst is available or not */ + { + return SCI_ERR_NULL_PTR; + } + + if ((SCI_MODE_SSPI != hdl->mode) && (SCI_MODE_SYNC != hdl->mode)) + { + return SCI_ERR_BAD_MODE; + } + + if (0 == length) + { + return SCI_ERR_INVALID_ARG; + } +#endif + + err = sci_send_sync_data(hdl, p_src, p_dst, length, true); + + return err; +} /* End of function R_SCI_SendReceive() */ +#endif /* End of SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED */ + + +#if (SCI_CFG_ASYNC_INCLUDED || SCI_CFG_IRDA_INCLUDED) +/***************************************************************************** +* Function Name: sci_transfer +* Description : Transfer for SCI +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* Return Value : none +******************************************************************************/ +static void sci_transfer(sci_hdl_t const hdl) +{ + uint16_t num; + uint8_t byte; + byteq_err_t err; + + /* Get bytes from tx queue */ + err = R_BYTEQ_Get(hdl->u_tx_data.que, (uint8_t *)&byte); + if (BYTEQ_SUCCESS == err) + { + /* TDR/FTDR register write access */ + SCI_TDR(byte); + } + + /* Get data byte number from que and if the number of data bytes is 0, to disable the transfer */ + R_BYTEQ_Used(hdl->u_tx_data.que, &num); + if (0 >= num) + { + /* Disable transmit interrupt */ + DISABLE_TXI_INT; +#if SCI_CFG_TEI_INCLUDED + /* Enable transmit end interrupt */ + hdl->rom->regs->SCR.BIT.TEIE = 1; + ENABLE_TEI_INT; +#endif + hdl->tx_idle = true; // set flag if queue empty + } +} /* End of function sci_transfer() */ +#endif /* SCI_CFG_ASYNC_INCLUDED || SCI_CFG_IRDA_INCLUDED */ + +#if (SCI_CFG_ASYNC_INCLUDED) +#if SCI_CFG_FIFO_INCLUDED +/***************************************************************************** +* Function Name: sci_fifo_transfer +* Description : FIFO Transfer for SCI +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* Return Value : none +******************************************************************************/ +static void sci_fifo_transfer(sci_hdl_t const hdl) +{ + uint8_t cnt; + uint8_t fifo_num; + + /* Repeated empty FIFO buffer count */ + fifo_num = SCI_FIFO_FRAME_SIZE - hdl->rom->regs->FDR.BIT.T; + + /* WAIT_LOOP */ + for (cnt = 0; cnt < fifo_num; cnt++) + { + /* SCI Transfer */ + sci_transfer(hdl); + + /* If the queue is empty(true == hdl->tx_idle), exit from FIFO transfer loop */ + if (true == hdl->tx_idle) + { + break; + } + } + + /* When the settings of transmit data are completed, set the SSRFIFO.TDFE flag to 0. */ + if (1 == hdl->rom->regs->SSRFIFO.BIT.TDFE) + { + /* Casting register 8 bits to unsigned char type is valid */ + hdl->rom->regs->SSRFIFO.BYTE = (unsigned char)~SCI_SSRFIFO_TDFE_MASK; + } +} /* End of function sci_fifo_transfer() */ +#endif /*End of SCI_CFG_FIFO_INCLUDED */ +#endif /* SCI_CFG_ASYNC_INCLUDED */ + +#if ((SCI_CFG_ASYNC_INCLUDED) || (TX_DTC_DMACA_ENABLE | RX_DTC_DMACA_ENABLE) || (SCI_CFG_IRDA_INCLUDED)) +/***************************************************************************** +* Function Name: txi_handler +* Description : TXI interrupt handler for SCI +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* Return Value : none +******************************************************************************/ +void txi_handler(sci_hdl_t const hdl) +{ +#if SCI_CFG_FIFO_INCLUDED + if (true == hdl->fifo_ctrl) + { +#if (TX_DTC_DMACA_ENABLE) + if((SCI_DTC_ENABLE == hdl->rom->dtc_dmaca_tx_enable) || (SCI_DMACA_ENABLE == hdl->rom->dtc_dmaca_tx_enable)) + { +#if(TX_DTC_DMACA_ENABLE & 0x02) + if (SCI_DMACA_ENABLE == hdl->rom->dtc_dmaca_tx_enable) + { + if((4 == hdl->rom->dmaca_tx_channel) || (5 == hdl->rom->dmaca_tx_channel) || (6 == hdl->rom->dmaca_tx_channel) || (7 == hdl->rom->dmaca_tx_channel)) + { + dmaca_stat_t stat_dmaca; + R_DMACA_Control(hdl->rom->dmaca_tx_channel, DMACA_CMD_DTIF_STATUS_CLR, &stat_dmaca); + } + + R_DMACA_Close(hdl->rom->dmaca_tx_channel); + } +#endif +#if (TX_DTC_DMACA_ENABLE & 0x01) + if (SCI_DTC_ENABLE == hdl->rom->dtc_dmaca_tx_enable) + { + sci_fifo_transfer_dtc(hdl); + return; + } +#endif +#if(TX_DTC_DMACA_ENABLE & 0x02) + if (SCI_DMACA_ENABLE == hdl->rom->dtc_dmaca_tx_enable) + { + sci_fifo_transfer_dmac(hdl); + } +#endif + } + else +#endif + { +#if (SCI_CFG_ASYNC_INCLUDED) + /* SCI FIFO Transfer */ + sci_fifo_transfer(hdl); +#endif + } + } + else +#endif /* SCI_CFG_FIFO_INCLUDED */ + { +#if (TX_DTC_DMACA_ENABLE) + if((SCI_DTC_ENABLE == hdl->rom->dtc_dmaca_tx_enable) || (SCI_DMACA_ENABLE == hdl->rom->dtc_dmaca_tx_enable)) + { +#if (SCI_CFG_ASYNC_INCLUDED || SCI_CFG_IRDA_INCLUDED) + if ((SCI_MODE_ASYNC == hdl->mode) || (SCI_MODE_IRDA == hdl->mode)) + { + hdl->tx_idle = true; + } +#endif +#if SCI_CFG_TEI_INCLUDED + /* Enable transmit end interrupt */ + hdl->rom->regs->SCR.BIT.TEIE = 1; + ENABLE_TEI_INT; +#endif + DISABLE_TXI_INT; + +#if(TX_DTC_DMACA_ENABLE & 0x02) + if(SCI_DMACA_ENABLE == hdl->rom->dtc_dmaca_tx_enable) + { + if((4 == hdl->rom->dmaca_tx_channel) || (5 == hdl->rom->dmaca_tx_channel) || (6 == hdl->rom->dmaca_tx_channel) || (7 == hdl->rom->dmaca_tx_channel)) + { + dmaca_stat_t stat_dmaca; + R_DMACA_Control(hdl->rom->dmaca_tx_channel, DMACA_CMD_DTIF_STATUS_CLR, &stat_dmaca); + } + + R_DMACA_Int_Disable(hdl->rom->dmaca_tx_channel); + R_DMACA_Close(hdl->rom->dmaca_tx_channel); + *hdl->rom->ir_txi = 1; + } +#endif + return; + } + else +#endif /* (TX_DTC_DMACA_ENABLE) */ + { +#if (SCI_CFG_ASYNC_INCLUDED || SCI_CFG_IRDA_INCLUDED) + /* SCI Transfer */ + sci_transfer(hdl); +#endif + } + } +} /* End of function txi_handler() */ +#endif /* ((SCI_CFG_ASYNC_INCLUDED) || (TX_DTC_DMACA_ENABLE | RX_DTC_DMACA_ENABLE) || (SCI_CFG_IRDA_INCLUDED) */ + + +#if SCI_CFG_TEI_INCLUDED +/***************************************************************************** +* Function Name: tei_handler +* Description : TEI interrupt handler for SCI +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* Return Value : none +******************************************************************************/ +void tei_handler(sci_hdl_t const hdl) +{ + sci_cb_args_t args; + + /* Disable transmit end interrupt */ + DISABLE_TEI_INT; + hdl->rom->regs->SCR.BIT.TEIE = 0; + + /* Activate callback function if available */ + if ((NULL != hdl->callback) && (FIT_NO_FUNC != hdl->callback)) + { + args.hdl = hdl; + args.event = SCI_EVT_TEI; + + /* Activate callback function */ + hdl->callback((void *)&args); + } +} /* End of function tei_handler() */ +#endif + + +/*********************************************************************************************************************** +* Function Name: R_SCI_Receive +********************************************************************************************************************//** +* @brief When Asynchronous Mode and DTC/DMAC are not used, fetches data from a queue which is filled by RXI interrupts. +* In other modes, initiates reception if transceiver is not in use. +* @param[in] hdl Handle for channel. Set hdl when R_SCI_Open() is successfully processed. +* +* @param[in] p_dst Pointer to buffer to load data into +* +* @param[in] length Number of bytes to read +* +* @retval SCI_SUCCESS Requested number of bytes were loaded into p_dst (Asynchronous) Clocking in of data initiated +* (SSPI/Synchronous) +* +* @retval SCI_ERR_NULL_PTR hdl value is NULL +* +* @retval SCI_ERR_BAD_MODE Mode specified not currently supported +* +* @retval SCI_ERR_INSUFFICIENT_DATA Insufficient data in receive queue to fetch all data (When Asynchronous Mode and +* DTC/DMAC are not used) +* +* @retval SCI_ERR_XCVR_BUSY Channel currently busy (SSPI/Synchronous/When Asynchronous Mode and DTC/DMAC are used) +* +* @details When Asynchronous Mode and DTC/DMAC are not used, this function gets data received on an SCI channel +* referenced by the handle from its receive queue. This function will not block if the requested number of bytes is not +* available. +* When Asynchronous Mode and DTC/DMAC are used, this function registers DTC/DMAC setting and specifies to the RXI and +* data is passed to *p_dst by DTC/DMAC each time the RXI interrupt occurs. +* In SSPI/Synchronous modes, the clocking in of data begins immediately if the transceiver is not already in use. +* The value assigned to SCI_CFG_DUMMY_TX_BYTE in r_sci_config.h is clocked out while the receive data is being clocked in.\n +* If any errors occurred during reception, the callback function specified in R_SCI_Open() is executed. Check +* an event passed with the argument of the callback function to see if the reception has been successfully +* completed. See Section 2.11 Callback Function in application note for details.\n +* Note that the toggling of Slave Select lines when in SSPI mode is not handled by this driver. The Slave +* Select line for the target device must be enabled prior to calling this function. +* @note See section 2.11 Callback Function in application note for values passed to arguments of the callback function. +* In Asynchronous mode, when data match detected, received data stored in a queue and notify to user by callback function +* with event SCI_EVT_RX_CHAR_MATCH. +*/ +sci_err_t R_SCI_Receive(sci_hdl_t const hdl, + uint8_t *p_dst, + uint16_t const length) +{ +sci_err_t err = SCI_SUCCESS; + + + /* Check arguments */ + +#if SCI_CFG_PARAM_CHECKING_ENABLE + /* Check argument hdl, p_dst */ + if (((NULL == hdl) || (FIT_NO_PTR == hdl))|| ((NULL == p_dst) || (FIT_NO_PTR == p_dst))) + { + return SCI_ERR_NULL_PTR; + } + if ((SCI_MODE_OFF == hdl->mode) || (SCI_MODE_MAX <= hdl->mode)) + { + return SCI_ERR_BAD_MODE; + } + if (0 == length) + { + return SCI_ERR_INVALID_ARG; + } +#endif + + if ((SCI_MODE_ASYNC == hdl->mode) || (SCI_MODE_IRDA == hdl->mode)) + { + /* mode is ASYNC/IRDA */ +#if (SCI_CFG_ASYNC_INCLUDED || SCI_CFG_IRDA_INCLUDED) + err = sci_receive_async_data(hdl, p_dst, length); +#endif + } + + else + { + /* mode is SSPI/SYNC */ +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + err = sci_receive_sync_data(hdl, p_dst, length); +#endif + } + + return err; +} /* End of function R_SCI_Receive() */ + +#if (SCI_CFG_ASYNC_INCLUDED || SCI_CFG_IRDA_INCLUDED) +/***************************************************************************** +* Function Name: sci_receive_async_data +* Description : This function determines if the rx byte queue of the channel +* referenced by the handle, the requested number of bytes +* is available, and get the data from the rx byte queue. +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* p_dst - +* ptr to buffer to load data into +* length - +* number of bytes to read +* Return Value : SCI_SUCCESS - +* requested number of byte loaded into p_dst +* SCI_ERR_INSUFFICIENT_DATA - +* rx queue does not contain requested amount of data +******************************************************************************/ +static sci_err_t sci_receive_async_data(sci_hdl_t const hdl, + uint8_t *p_dst, + uint16_t const length) +{ + sci_err_t err = SCI_SUCCESS; +#if (RX_DTC_DMACA_ENABLE & 0x01) + if (SCI_DTC_ENABLE == hdl->rom->dtc_dmaca_rx_enable) + { + if(true == hdl->rx_idle) + { + sci_fifo_ctrl_t *p_ctrl; + p_ctrl = &hdl->queue[hdl->qindex_app_rx]; + p_ctrl->p_rx_buf = p_dst; + p_ctrl->rx_cnt = length; /* length must be set after buf ptr */ + p_ctrl->p_rx_fraction_buf = p_dst; + p_ctrl->rx_fraction = length; +#if SCI_CFG_FIFO_INCLUDED + if (true == hdl->fifo_ctrl) + { + err = sci_rxfifo_dtc_create(hdl, p_dst, length); + } + else +#endif + { + err = sci_rx_dtc_create(hdl, p_dst, length); + } + + if(SCI_SUCCESS == err) + { + hdl->rx_idle = false; + } + } + else + { + return SCI_ERR_XCVR_BUSY; + } + } + else +#endif + { +#if (RX_DTC_DMACA_ENABLE & 0x02) + if (SCI_DMACA_ENABLE == hdl->rom->dtc_dmaca_rx_enable) + { + if(true == hdl->rx_idle) + { + sci_fifo_ctrl_t *p_ctrl; + p_ctrl = &hdl->queue[hdl->qindex_app_rx]; + p_ctrl->p_rx_buf = p_dst; + p_ctrl->rx_cnt = length; /* length must be set after buf ptr */ + p_ctrl->p_rx_fraction_buf = p_dst; + p_ctrl->rx_fraction = length; +#if (SCI_CFG_FIFO_INCLUDED) + if (true == hdl->fifo_ctrl) + { + err = sci_rxfifo_dmaca_create(hdl, p_dst, length); + } + else +#endif + { + err = sci_rx_dmaca_create(hdl, p_dst, length); + } + + if(SCI_SUCCESS == err) + { + hdl->rx_idle = false; + } + } + else + { + return SCI_ERR_XCVR_BUSY; + } + } + else +#endif + { + uint16_t cnt; + byteq_err_t byteq_err = BYTEQ_SUCCESS; + + /* CHECK FOR SUFFICIENT DATA IN QUEUE, AND FETCH IF AVAILABLE */ + R_BYTEQ_Used(hdl->u_rx_data.que, &cnt); + + if (cnt < length) + { + return SCI_ERR_INSUFFICIENT_DATA; + } + + /* Get bytes from rx queue */ + /* WAIT_LOOP */ + for (cnt = 0; cnt < length; cnt++) + { +#if (SCI_CFG_USE_CIRCULAR_BUFFER == 1) + byteq_err = R_BYTEQ_Get(hdl->u_rx_data.que, p_dst++); +#else + /* Disable RXI Interrupt */ + DISABLE_RXI_INT; + byteq_err = R_BYTEQ_Get(hdl->u_rx_data.que, p_dst++); + ENABLE_RXI_INT; +#endif + if (BYTEQ_SUCCESS != byteq_err) + { + err = SCI_ERR_INSUFFICIENT_DATA; + break; + } + } + } + } + return err; +} /* End of function sci_receive_async_data() */ +#endif /* SCI_CFG_ASYNC_INCLUDED || SCI_CFG_IRDA_INCLUDED */ + +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) +/***************************************************************************** +* Function Name: sci_receive_sync_data +* Description : This function determines if the channel referenced by the +* handle is not busy, and dummy data send. +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* p_dst - +* ptr to buffer to load data into +* length - +* number of bytes to read +* Return Value : SCI_SUCCESS - +* requested number of byte loaded into p_dst +* SCI_ERR_XCVR_BUSY - +* channel currently busy +******************************************************************************/ +static sci_err_t sci_receive_sync_data(sci_hdl_t const hdl, + uint8_t *p_dst, + uint16_t const length) +{ +#if SCI_CFG_FIFO_INCLUDED + uint8_t cnt; + uint8_t thresh_cnt; +#endif + + /* IF TRANCEIVER NOT IN USE, START DUMMY TRANSMIT TO CLOCK IN DATA */ + if (true == hdl->tx_idle) + { + hdl->u_rx_data.buf = p_dst; + hdl->save_rx_data = true; /* save the data clocked in */ + hdl->tx_cnt = length; + hdl->rx_cnt = length; + hdl->tx_dummy = true; + +#if SCI_CFG_FIFO_INCLUDED + if (true == hdl->fifo_ctrl) + { + /* reset TX FIFO */ + hdl->rom->regs->FCR.BIT.TFRST = 0x01; + + /* reset RX FIFO */ + hdl->rom->regs->FCR.BIT.RFRST = 0x01; +#if (SCI_DTC_DMACA_DISABLE != RX_DTC_DMACA_ENABLE) + if((SCI_DMACA_ENABLE == hdl->rom->dtc_dmaca_rx_enable) || (SCI_DTC_ENABLE == hdl->rom->dtc_dmaca_rx_enable)) + { + sci_fifo_ctrl_t *p_ctrl; + p_ctrl = &hdl->queue[hdl->qindex_app_rx]; + p_ctrl->p_rx_buf = p_dst; + p_ctrl->rx_cnt = length; /* length must be set after buf ptr */ + p_ctrl->p_rx_fraction_buf = p_dst; + p_ctrl->rx_fraction = length; + return sci_send_sync_data_fifo_dma_dtc(hdl, NULL, p_dst, length, false); + } + else +#endif + { + /* Transmitter is in use */ + hdl->tx_idle = false; + + if (length > SCI_FIFO_FRAME_SIZE) + { + thresh_cnt = SCI_FIFO_FRAME_SIZE; + } + else + { + /* If length is lower than SCI_CFG_CHXX_RX_FIFO_THRESH, FCR.BIT.RTRG register is set to length */ + if (length < hdl->rx_curr_thresh) + { + hdl->rom->regs->FCR.BIT.RTRG = length; + } + thresh_cnt = length; + } + + hdl->tx_cnt -= thresh_cnt; + + /* WAIT_LOOP */ + for (cnt = 0; cnt < thresh_cnt; cnt++) + { + SCI_TDR(SCI_CFG_DUMMY_TX_BYTE); /* start transmit */ + } + } + } + else +#endif /* End of SCI_CFG_FIFO_INCLUDED */ + { +#if (SCI_DTC_DMACA_DISABLE != RX_DTC_DMACA_ENABLE) + if((SCI_DMACA_ENABLE == hdl->rom->dtc_dmaca_rx_enable) || (SCI_DTC_ENABLE == hdl->rom->dtc_dmaca_rx_enable)) + { + return sci_send_sync_data_dma_dtc(hdl, NULL, p_dst, length); + } + else +#endif + { + /* Transmitter is in use */ + hdl->tx_idle = false; + + hdl->tx_cnt--; + SCI_TDR(SCI_CFG_DUMMY_TX_BYTE); /* start transfer */ + } + } + return SCI_SUCCESS; + } + + return SCI_ERR_XCVR_BUSY; +} /* End of function sci_receive_sync_data() */ +#endif /* End of SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED */ + +/***************************************************************************** +* Function Name: sci_receive +* Description : Receive for SCI +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* Return Value : none +******************************************************************************/ +static void sci_receive(sci_hdl_t const hdl) +{ + sci_cb_args_t args; + uint8_t byte; + + /* Read byte */ + SCI_RDR(byte); + if ((SCI_MODE_ASYNC == hdl->mode) || (SCI_MODE_IRDA == hdl->mode)) + { +#if (SCI_CFG_ASYNC_INCLUDED || SCI_CFG_IRDA_INCLUDED) + + /* Place byte in queue */ + if (R_BYTEQ_Put(hdl->u_rx_data.que, byte) == BYTEQ_SUCCESS) + { + args.event = SCI_EVT_RX_CHAR; + } + else + { + args.event = SCI_EVT_RXBUF_OVFL; + } + + /* Do callback if available */ + if ((NULL != hdl->callback) && (FIT_NO_FUNC != hdl->callback)) + { + args.hdl = hdl; + args.byte = byte; + + /* Casting to void type is valid */ + hdl->callback((void *)&args); + } +#endif + } + else + { +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + hdl->rx_cnt--; + + /* Place byte in buffer if Receive() or SendReceive() */ + if (true == hdl->save_rx_data) + { + *hdl->u_rx_data.buf++ = byte; + } + + /* See if more bytes to transfer */ + if (0 < hdl->rx_cnt) + { + if (0 < hdl->tx_cnt) + { + /* send another byte */ + if (true == hdl->tx_dummy) + { + hdl->tx_cnt--; + SCI_TDR(SCI_CFG_DUMMY_TX_BYTE); + } + else + { + hdl->tx_cnt--; + hdl->u_tx_data.buf++; + SCI_TDR(*hdl->u_tx_data.buf); + } + } + } + else + { + hdl->tx_idle = true; + + /* Do callback if available */ + if ((NULL != hdl->callback) && (FIT_NO_FUNC != hdl->callback)) + { + args.hdl = hdl; + args.event = SCI_EVT_XFER_DONE; + + /* Casting to void type is valid */ + hdl->callback((void *)&args); + } + } +#endif /* End of SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED */ + } +} /* End of function sci_receive() */ + +#if ((SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) && TX_DTC_DMACA_ENABLE) +/***************************************************************************** +* Function Name: sci_send_sync_data_dma_dtc +* Description : Send and receive data when using DTC/DMAC with non FIFO +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* p_src - +* Pointer to source address +* p_dst - +* Pointer to dst address +* length - +* Data length +* Return Value : SCI_SUCCESS if process is successful, else process is failed. +******************************************************************************/ +static sci_err_t sci_send_sync_data_dma_dtc(sci_hdl_t const hdl, uint8_t *p_src, uint8_t *p_dst, uint16_t const length) +{ + sci_err_t err; + + err = SCI_SUCCESS; + + if (SCI_SUCCESS == err) + { + /* Do NOT attempt to load fifo at application level. + * Set up arguments and enable transmitter to kick off transmit. */ + #if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + /* Set up rx control. Data ignored when p_dst is NULL. */ + if ((SCI_MODE_SYNC == hdl->mode) || (SCI_MODE_SSPI == hdl->mode)) + { + + #if (RX_DTC_DMACA_ENABLE & 0x01) + if (SCI_DTC_ENABLE == hdl->rom->dtc_dmaca_rx_enable) + { + sci_fifo_ctrl_t *p_rctrl; + p_rctrl = &hdl->queue[hdl->qindex_app_rx]; + p_rctrl->p_rx_buf = p_dst; + p_rctrl->rx_cnt = length; + err = sci_rx_dtc_create(hdl, p_dst, length); + } + #endif + #if (RX_DTC_DMACA_ENABLE & 0x02) + if (SCI_DMACA_ENABLE == hdl->rom->dtc_dmaca_rx_enable) + { + sci_fifo_ctrl_t *p_rctrl; + p_rctrl = &hdl->queue[hdl->qindex_app_rx]; + p_rctrl->p_rx_buf = p_dst; + p_rctrl->rx_cnt = length; + err = sci_rx_dmaca_create(hdl, p_dst, length); + } + #endif + } + #endif /* (SCI_CFG_SYNC_INCLUDED) */ + } + + if (SCI_SUCCESS == err) + { + #if (TX_DTC_DMACA_ENABLE & 0x01) + if (SCI_DTC_ENABLE == hdl->rom->dtc_dmaca_tx_enable) + { + err = sci_tx_dtc_create(hdl, p_src, length); + } + #endif + #if (TX_DTC_DMACA_ENABLE & 0x02) + if (SCI_DMACA_ENABLE == hdl->rom->dtc_dmaca_tx_enable) + { + err = sci_tx_dmaca_create(hdl, p_src, length); + } + #endif + } + + if (SCI_SUCCESS == err) + { + DISABLE_TXI_INT; /* disable interrupt in icu */ + hdl->tx_idle = false; + ENABLE_TXI_INT; + } + + return err; +} /* End of function sci_send_sync_data_dma_dtc() */ +#endif /* ((SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) && TX_DTC_DMACA_ENABLE) */ + +#if SCI_CFG_FIFO_INCLUDED +#if ((SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) && TX_DTC_DMACA_ENABLE) +/***************************************************************************** +* Function Name: sci_send_sync_data_fifo_dma_dtc +* Description : Send and receive data when using DTC/DMAC with FIFO +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* p_src - +* Pointer to source address +* p_dst - +* Pointer to dst address +* length - +* Data length +* save_rx_data - +* Save Rx data in Sync mode ir not. +* Return Value : SCI_SUCCESS if process is successful, else process is failed. +******************************************************************************/ +static sci_err_t sci_send_sync_data_fifo_dma_dtc(sci_hdl_t const hdl, uint8_t *p_src, uint8_t *p_dst, uint16_t const length, bool save_rx_data) +{ + #if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + sci_fifo_ctrl_t *p_rctrl; + #endif + sci_fifo_ctrl_t *p_tctrl; + sci_err_t err; + + err = SCI_SUCCESS; + + /* If two requests outstanding or Async break in progress, return busy */ + p_tctrl = &hdl->queue[hdl->qindex_app_tx]; + + p_tctrl->total_length = length; /* Used for DTC in txi_handler() */ + + if (SCI_SUCCESS == err) + { + /* Do NOT attempt to load fifo at application level. + * Set up arguments and enable transmitter to kick off transmit. */ + #if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + /* Set up rx control. Data ignored when p_dst is NULL. */ + if ((SCI_MODE_SYNC == hdl->mode) || (SCI_MODE_SSPI == hdl->mode)) + { + p_rctrl = &hdl->queue[hdl->qindex_app_rx]; + p_rctrl->p_rx_buf = p_dst; + p_rctrl->rx_cnt = length; + + #if (RX_DTC_DMACA_ENABLE & 0x01) + if (SCI_DTC_ENABLE == hdl->rom->dtc_dmaca_rx_enable) + { + err = sci_rxfifo_dtc_create(hdl, p_dst, length); + } + #endif + #if (RX_DTC_DMACA_ENABLE & 0x02) + if (SCI_DMACA_ENABLE == hdl->rom->dtc_dmaca_rx_enable) + { + err = sci_rxfifo_dmaca_create(hdl, p_dst, length); + } + #endif + } + #endif /* (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) */ + } + + if (SCI_SUCCESS == err) + { + p_tctrl->p_tx_buf = p_src; /* dummy byte sent when NULL (Sync) */ + p_tctrl->tx_cnt = length; /* length must be set after buf ptr */ + +#if (TX_DTC_DMACA_ENABLE & 0x01) + if (SCI_DTC_ENABLE == hdl->rom->dtc_dmaca_tx_enable) + { + err = sci_txfifo_dtc_create(hdl, p_src, length); + } +#endif +#if (TX_DTC_DMACA_ENABLE & 0x02) + if (SCI_DMACA_ENABLE == hdl->rom->dtc_dmaca_tx_enable) + { + err = sci_txfifo_dmaca_create(hdl, p_src, length); + } +#endif + } + + if (SCI_SUCCESS == err) + { + #if ((RX_DTC_DMACA_ENABLE) && (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED)) + hdl->rom->regs->SSRFIFO.BIT.RDF = 0; + #endif + DISABLE_TXI_INT; /* disable interrupt in icu */ + + hdl->tx_idle = false; + + ENABLE_TXI_INT; + } + + return err; +} /* End of function sci_send_sync_data_fifo_dma_dtc() */ +#endif /* ((SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) && TX_DTC_DMACA_ENABLE) */ +#endif /* SCI_CFG_FIFO_INCLUDED */ + + +#if SCI_CFG_FIFO_INCLUDED +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) +/***************************************************************************** +* Function Name: sci_fifo_receive_sync +* Description : FIFO Receive for SCI mode is SYNC and SSPI +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* Return Value : none +******************************************************************************/ +static void sci_fifo_receive_sync(sci_hdl_t const hdl) +{ + uint8_t cnt; + uint8_t fifo_num_rx; + uint8_t fifo_num_tx; + sci_cb_args_t args; + uint8_t byte_rx[SCI_FIFO_FRAME_SIZE]; +#if(RX_DTC_DMACA_ENABLE) + if((SCI_DTC_ENABLE == hdl->rom->dtc_dmaca_rx_enable) || (SCI_DMACA_ENABLE == hdl->rom->dtc_dmaca_rx_enable)) + { + if((SCI_DTC_ENABLE == hdl->rom->dtc_dmaca_rx_enable) || (SCI_DMACA_ENABLE == hdl->rom->dtc_dmaca_rx_enable)) + { + sci_fifo_ctrl_t *p_rctrl; + volatile uint8_t byte; /* volatile to remove "not used" warning */ + volatile uint8_t tmp_reg_frdr; + +#if (RX_DTC_DMACA_ENABLE & 0x02) + if (SCI_DMACA_ENABLE == hdl->rom->dtc_dmaca_rx_enable) + { + R_DMACA_Int_Disable(hdl->rom->dmaca_rx_channel); + R_DMACA_Close(hdl->rom->dmaca_rx_channel); + } +#endif + + p_rctrl = &hdl->queue[hdl->qindex_int_rx]; + +#if (RX_DTC_DMACA_ENABLE) + if (SCI_DTC_DMACA_DISABLE != hdl->rom->dtc_dmaca_rx_enable) + { + if (NULL != p_rctrl->p_rx_fraction_buf) + { + p_rctrl->p_rx_buf = p_rctrl->p_rx_fraction_buf; + p_rctrl->p_rx_fraction_buf = NULL; + } + + if (p_rctrl->rx_cnt > p_rctrl->rx_fraction) + { + p_rctrl->rx_cnt = p_rctrl->rx_fraction; + } + } +#endif + + if (0 != SCI_PRV_RX_FIFO_USED_CNT) + { + + /* loop until request completed or no more data in FIFO */ + /* WAIT_LOOP */ + while ((0 != SCI_PRV_RX_FIFO_USED_CNT) && (0 != p_rctrl->rx_cnt)) + { + if (NULL == p_rctrl->p_rx_buf) /* ignore data for Sync Send() */ + { + byte = hdl->rom->regs->FRDR.BYTE.L; + } + else + { + + tmp_reg_frdr = hdl->rom->regs->FRDR.BYTE.L; /* read byte */ + *p_rctrl->p_rx_buf = tmp_reg_frdr; /* read byte */ + p_rctrl->p_rx_buf++; + } + p_rctrl->rx_cnt--; /* decrement number of bytes yet to read */ + } + } + + if (0 == p_rctrl->rx_cnt) + { + hdl->tx_idle = true; + + /* Do callback if available */ + if ((NULL != hdl->callback) && (FIT_NO_FUNC != hdl->callback)) + { + args.hdl = hdl; + args.event = SCI_EVT_RX_SYNC_DONE; + + /* Casting pointer to void* type is valid */ + hdl->callback((void *)&args); + } + } + + /* If remaining data to read is less than threshold, adjust threshold */ + else + { + if (p_rctrl->rx_cnt < hdl->rx_dflt_thresh) + { + SCI_PRV_RX_FIFO_THRESHOLD = p_rctrl->rx_cnt; + } + else + { + SCI_PRV_RX_FIFO_THRESHOLD = hdl->rx_dflt_thresh; + } + } + + /* If at threshold level, clear bit so can get another RXIF interrupt. + * Do not re-arm if Receive() request not outstanding (Async) + */ + if ((1 == hdl->rom->regs->SSRFIFO.BIT.RDF) && (0 != p_rctrl->rx_cnt)) + { + hdl->rom->regs->SSRFIFO.BIT.RDF = 0; + } + + } + } + else +#endif /* (RX_DTC_DMACA_ENABLE) */ + { + fifo_num_rx = hdl->rom->regs->FDR.BIT.R; + + /* WAIT_LOOP */ + for (cnt = 0; cnt < fifo_num_rx; cnt++) + { + SCI_RDR(byte_rx[cnt]); + } + + hdl->rx_cnt -= fifo_num_rx; + + /* Place byte in buffer if Receive() or SendReceive() */ + if (true == hdl->save_rx_data) + { + /* WAIT_LOOP */ + for (cnt = 0; cnt < fifo_num_rx; cnt++) + { + /* SCI Receive */ + *hdl->u_rx_data.buf++ = byte_rx[cnt]; + } + } + + /* See if more bytes to transfer */ + if (0 < hdl->rx_cnt) + { + if (hdl->rom->regs->FCR.BIT.RTRG > hdl->rx_cnt) + { + hdl->rom->regs->FCR.BIT.RTRG = hdl->rx_cnt; + } + + if (0 < hdl->tx_cnt) + { + if (hdl->tx_cnt > fifo_num_rx) + { + fifo_num_tx = fifo_num_rx; + hdl->tx_cnt -= fifo_num_rx; + } + else + { + fifo_num_tx = hdl->tx_cnt; + hdl->tx_cnt = 0; + } + + /* send another byte */ + if (true == hdl->tx_dummy) + { + /* WAIT_LOOP */ + for (cnt = 0; cnt < fifo_num_tx; cnt++) + { + SCI_TDR(SCI_CFG_DUMMY_TX_BYTE); + } + } + else + { + /* WAIT_LOOP */ + for (cnt = 0; cnt < fifo_num_tx; cnt++) + { + hdl->u_tx_data.buf++; + SCI_TDR(*hdl->u_tx_data.buf); + } + } + } + } + else + { + hdl->rom->regs->FCR.BIT.RTRG = hdl->rx_curr_thresh; + hdl->tx_idle = true; + + /* Do callback if available */ + if ((NULL != hdl->callback) && (FIT_NO_FUNC != hdl->callback)) + { + args.hdl = hdl; + args.event = SCI_EVT_XFER_DONE; + + /* Casting pointer to void* type is valid */ + hdl->callback((void *)&args); + } + } + } + +} /* End of function sci_fifo_receive_sync() */ +#endif /* End of SCI_CFG_FIFO_INCLUDED */ +#endif /* End of SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED */ + +#if SCI_CFG_FIFO_INCLUDED +/***************************************************************************** +* Function Name: sci_fifo_receive +* Description : FIFO Receive for SCI +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* Return Value : none +******************************************************************************/ +static void sci_fifo_receive(sci_hdl_t const hdl) +{ +#if (SCI_CFG_ASYNC_INCLUDED) + uint16_t cnt; + uint16_t fifo_num; + sci_cb_args_t args; + uint8_t byte_rx[SCI_FIFO_FRAME_SIZE]; +#endif + if (SCI_MODE_ASYNC == hdl->mode) + { +#if (SCI_CFG_ASYNC_INCLUDED) +#if(RX_DTC_DMACA_ENABLE) + if((SCI_DTC_ENABLE == hdl->rom->dtc_dmaca_rx_enable) || (SCI_DMACA_ENABLE == hdl->rom->dtc_dmaca_rx_enable)) + { + sci_fifo_ctrl_t *p_rctrl; + volatile uint8_t byte; /* volatile to remove "not used" warning */ + uint8_t tmp_reg_frdr; + sci_cb_args_t args; +#if (RX_DTC_DMACA_ENABLE & 0x02) + if (SCI_DMACA_ENABLE == hdl->rom->dtc_dmaca_rx_enable) + { + R_DMACA_Int_Disable(hdl->rom->dmaca_rx_channel); + R_DMACA_Close(hdl->rom->dmaca_rx_channel); + } +#endif + p_rctrl = &hdl->queue[hdl->qindex_app_rx]; + + if (NULL != p_rctrl->p_rx_fraction_buf) + { + p_rctrl->p_rx_buf = p_rctrl->p_rx_fraction_buf; + p_rctrl->p_rx_fraction_buf = NULL; + } + + if (p_rctrl->rx_cnt > p_rctrl->rx_fraction) + { + p_rctrl->rx_cnt = p_rctrl->rx_fraction; + } + + if (0 != SCI_PRV_RX_FIFO_USED_CNT) + { + /* loop until request completed or no more data in FIFO */ + /* WAIT_LOOP */ + while ((0 != SCI_PRV_RX_FIFO_USED_CNT) && (0 != p_rctrl->rx_cnt)) + { + if (NULL == p_rctrl->p_rx_buf) /* ignore data for Sync Send() */ + { + byte = hdl->rom->regs->FRDR.BYTE.L; + } + else + { + tmp_reg_frdr = hdl->rom->regs->FRDR.BYTE.L; /* read byte */ + *p_rctrl->p_rx_buf = tmp_reg_frdr; /* read byte */ + p_rctrl->p_rx_buf++; + } + p_rctrl->rx_cnt--; /* decrement number of bytes yet to read */ + } + } + if (0 == p_rctrl->rx_cnt) + { + hdl->rx_idle = true; + + /* call callback function if available */ + if ((NULL != hdl->callback) && (FIT_NO_FUNC != hdl->callback)) + { + args.hdl = hdl; + args.event = SCI_EVT_RX_DONE; + hdl->callback(&args); + } + } + + /* If remaining data to read is less than threshold, adjust threshold */ + else // DTC will do here + { + if (p_rctrl->rx_fraction < hdl->rx_dflt_thresh) + { + SCI_PRV_RX_FIFO_THRESHOLD = p_rctrl->rx_fraction; + } + else + { + SCI_PRV_RX_FIFO_THRESHOLD = hdl->rx_dflt_thresh; + } + } + } + else + #endif /* (RX_DTC_DMACA_ENABLE) */ + { + /* Casting unsigned char type to uint16_t type is valid */ + fifo_num = (uint16_t)hdl->rom->regs->FDR.BIT.R; + + /* RX FIFO flush */ + /* WAIT_LOOP */ + for (cnt = 0; cnt < fifo_num; cnt++) + { + /* Read byte */ + SCI_RDR(byte_rx[cnt]); + } + + /* Determine amount of space left in rx queue */ + (void)R_BYTEQ_Unused(hdl->u_rx_data.que, &cnt); + if (cnt >= fifo_num) + { + /* free space is enough */ + args.event = SCI_EVT_RX_CHAR; + } + else + { + /* insufficient free space, store as much as possible */ + fifo_num = cnt; + args.event = SCI_EVT_RXBUF_OVFL; + } + + /* WAIT_LOOP */ + for (cnt = 0; cnt < fifo_num; cnt++) + { + /* store bytes to rx queue for R_SCI_Receive */ + (void)R_BYTEQ_Put(hdl->u_rx_data.que, byte_rx[cnt]); + } + + /* Do callback if available */ + if ((NULL != hdl->callback) && (FIT_NO_FUNC != hdl->callback)) + { + args.hdl = hdl; + + /* Number of bytes were stored to queue */ + args.num = (uint8_t)fifo_num; + + /* Casting pointer to void* type is valid */ + hdl->callback((void *)&args); + } + } +#endif /* End of SCI_CFG_ASYNC_INCLUDED*/ + } + else + { +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + /* SCI Receive */ + sci_fifo_receive_sync(hdl); +#endif + } + + /* When the readings of receive data are completed, set the SSRFIFO.RDF flag to 0. */ + if (1 == hdl->rom->regs->SSRFIFO.BIT.RDF) + { + /* Casting 8 bits to unsigned char type is valid */ + hdl->rom->regs->SSRFIFO.BYTE = (unsigned char)~SCI_SSRFIFO_RDF_MASK; + } + + if (SCI_MODE_ASYNC == hdl->mode) + { + if (1 == hdl->rom->regs->SSRFIFO.BIT.DR) + { + /* Casting 8 bits to unsigned char type is valid */ + hdl->rom->regs->SSRFIFO.BYTE = (unsigned char)~SCI_SSRFIFO_DR_MASK; + } + } +} /* End of function sci_fifo_receive() */ +#endif /* End of SCI_CFG_FIFO_INCLUDED */ + +#if SCI_CFG_DATA_MATCH_INCLUDED +/***************************************************************************** +* Function Name: sci_receive_data_match +* Description : SCI receive data match +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* Return Value : none +******************************************************************************/ +static void sci_receive_data_match(sci_hdl_t const hdl) +{ + volatile sci_cb_args_t args; + volatile uint8_t byte; + + if (SCI_MODE_ASYNC == hdl->mode) + { +#if (SCI_CFG_ASYNC_INCLUDED) + if (0 == hdl->rom->regs->DCCR.BIT.DCME) /* DCME automatically set 0 when data matched */ + { + hdl->rom->regs->DCCR.BIT.DCMF = 0; /* Clear Data Match Flag */ + + if ((0 == hdl->rom->regs->DCCR.BIT.DFER ) && (0 == hdl->rom->regs->DCCR.BIT.DPER )) /* Check framing error and parity error */ + { + /* Casting unsigned char type to unin8_t type is valid */ + byte = (uint8_t)(hdl->rom->regs->CDR.BYTE.L); /* Read data from comparison data register */ + + /* Place byte in queue */ + if (R_BYTEQ_Put(hdl->u_rx_data.que, byte) == BYTEQ_SUCCESS) + { + args.event = SCI_EVT_RX_CHAR_MATCH; + } + else + { + args.event = SCI_EVT_RXBUF_OVFL; + } + + /* Do callback if available */ + if ((NULL != hdl->callback) && (FIT_NO_FUNC != hdl->callback)) + { + args.hdl = hdl; + args.byte = byte; + + /* Casting to void* type is valid */ + hdl->callback((void *)&args); + } + } + } +#endif /* End of SCI_CFG_ASYNC_INCLUDED */ + } +} /* End of function sci_receive_data_match() */ +#endif /* End of SCI_CFG_DATA_MATCH_INCLUDED */ + +/***************************************************************************** +* Function Name: rxi_handler +* Description : RXI interrupt handler for SCI +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* Return Value : none +******************************************************************************/ +void rxi_handler(sci_hdl_t const hdl) +{ +#if SCI_CFG_DATA_MATCH_INCLUDED + if (1 == hdl->rom->regs->DCCR.BIT.DCMF) /* Check Data match flag */ + { + sci_receive_data_match(hdl); + } + else +#endif + { +#if SCI_CFG_FIFO_INCLUDED + if (true == hdl->fifo_ctrl) + { + /* SCI FIFO Receive */ + sci_fifo_receive(hdl); + } + else +#endif + { +#if (RX_DTC_DMACA_ENABLE) + if((SCI_DTC_ENABLE == hdl->rom->dtc_dmaca_rx_enable) || (SCI_DMACA_ENABLE == hdl->rom->dtc_dmaca_rx_enable)) + { + sci_fifo_ctrl_t *p_rctrl; + p_rctrl = &hdl->queue[hdl->qindex_app_rx]; + sci_cb_args_t args; +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + if ((SCI_MODE_SYNC == hdl->mode) || (SCI_MODE_SSPI == hdl->mode)) + { + hdl->tx_idle = true; + } +#endif +#if (SCI_CFG_ASYNC_INCLUDED) + if (SCI_MODE_ASYNC == hdl->mode) + { + hdl->rx_idle = true; + } +#endif + if (NULL != p_rctrl->p_rx_fraction_buf) + { + p_rctrl->p_rx_buf = p_rctrl->p_rx_fraction_buf; + p_rctrl->p_rx_fraction_buf = NULL; + } + + if (p_rctrl->rx_cnt > p_rctrl->rx_fraction) + { + p_rctrl->rx_cnt = p_rctrl->rx_fraction; + } + + /* Do callback if available */ + if ((NULL != hdl->callback) && (FIT_NO_FUNC != hdl->callback)) + { + args.hdl = hdl; +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + if ((SCI_MODE_SYNC == hdl->mode) || (SCI_MODE_SSPI == hdl->mode)) + { + args.event = SCI_EVT_RX_SYNC_DONE; + } + else +#endif + { + args.event = SCI_EVT_RX_DONE; + } + + /* Casting to void type is valid */ + hdl->callback((void *)&args); + } + + } + else +#endif /* (RX_DTC_DMACA_ENABLE) */ + { + /* SCI Receive */ + sci_receive(hdl); + } + } + } +} /* End of function rxi_handler() */ + + +/***************************************************************************** +* Function Name: sci_error +* Description : Error for SCI +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* Return Value : none +******************************************************************************/ +static void sci_error(sci_hdl_t const hdl) +{ + sci_cb_args_t args; + uint8_t byte; + uint8_t reg; + + reg = SCI_SSR; + if (0 != (reg & SCI_RCVR_ERR_MASK)) + { + if (0 != (reg & SCI_SSR_ORER_MASK)) + { + args.event = SCI_EVT_OVFL_ERR; + } +#if (SCI_CFG_ASYNC_INCLUDED || SCI_CFG_IRDA_INCLUDED) +#if (SCI_CFG_ASYNC_INCLUDED) + else if (0 != (reg & SCI_SSR_PER_MASK)) + { + args.event = SCI_EVT_PARITY_ERR; + } +#endif + else if (0 != (reg & SCI_SSR_FER_MASK)) + { + args.event = SCI_EVT_FRAMING_ERR; + } +#endif + else + { + /* Do Nothing */ + } + + /* Flush register */ + SCI_RDR(byte); + + /* Clear error condition */ + /* WAIT_LOOP */ + while (0 != (SCI_SSR & SCI_RCVR_ERR_MASK)) + { + SCI_RDR(byte); + + reg = SCI_SSR; + reg &= (~SCI_RCVR_ERR_MASK); + reg |= SCI_SSR_CLR_MASK; + SCI_SSR = reg; + + if (0 != (SCI_SSR & SCI_RCVR_ERR_MASK)) + { + R_BSP_NOP(); /* read and Compare */ + } + } + +#if ((RX_DTC_DMACA_ENABLE & 0x01) || (RX_DTC_DMACA_ENABLE & 0x02) && SCI_CFG_ASYNC_INCLUDED) + /* Clear rx_idle flag when using Async mode with DTC/DMAC */ + if ((SCI_DTC_ENABLE == hdl->rom->dtc_dmaca_rx_enable) || (SCI_DMACA_ENABLE == hdl->rom->dtc_dmaca_rx_enable)) + { + if (SCI_MODE_ASYNC == hdl->mode) + { + hdl->rx_idle = true; + } + } +#endif + + /* Do callback for error */ + if ((NULL != hdl->callback) && (FIT_NO_FUNC != hdl->callback)) + { + args.hdl = hdl; + args.byte = byte; + + /* Casting to void* type is valid */ + hdl->callback((void *)&args); + } + } + +} /* End of function sci_error() */ + +#if SCI_CFG_FIFO_INCLUDED +/***************************************************************************** +* Function Name: sci_fifo_error +* Description : FIFO Error for SCI +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* Return Value : none +******************************************************************************/ +static void sci_fifo_error(sci_hdl_t const hdl) +{ + sci_cb_args_t args; + uint8_t reg; + volatile uint8_t ssrfifo_data; + volatile uint16_t dummy; + + reg = SCI_SSRFIFO; + if (0 != (reg & SCI_RCVR_ERR_MASK)) + { + if (0 != (reg & SCI_SSR_ORER_MASK)) + { + args.event = SCI_EVT_OVFL_ERR; + } +#if (SCI_CFG_ASYNC_INCLUDED) + else if (0 != (reg & SCI_SSR_PER_MASK)) + { + args.event = SCI_EVT_PARITY_ERR; + } + else if (0 != (reg & SCI_SSR_FER_MASK)) + { + args.event = SCI_EVT_FRAMING_ERR; + } +#endif + else + { + /* Do Nothing */ + } + +#if ((RX_DTC_DMACA_ENABLE & 0x01) || (RX_DTC_DMACA_ENABLE & 0x02) && SCI_CFG_ASYNC_INCLUDED) + /* Clear rx_idle flag when using Async mode with DTC/DMAC */ + if ((SCI_DTC_ENABLE == hdl->rom->dtc_dmaca_rx_enable) || (SCI_DMACA_ENABLE == hdl->rom->dtc_dmaca_rx_enable)) + { + if (SCI_MODE_ASYNC == hdl->mode) + { + hdl->rx_idle = true; + } + } +#endif + + /* Do callback for error */ + if ((NULL != hdl->callback) && (FIT_NO_FUNC != hdl->callback)) + { + args.hdl = hdl; + args.byte = 0; + + /* Casting pointer to void* type is valid */ + hdl->callback((void *)&args); + } + + /* if error condition don't clear in callback when it clear at here */ + reg = SCI_SSRFIFO; + if (0 != (reg & SCI_RCVR_ERR_MASK)) + { + /* Flush register */ + /* WAIT_LOOP */ + while (0 != hdl->rom->regs->FDR.BIT.R) + { + dummy = hdl->rom->regs->FRDR.WORD; /* FRDR dummy read */ + } + + /* Clear error condition */ + /* WAIT_LOOP */ + while (0x00 != (SCI_SSRFIFO & SCI_RCVR_ERR_MASK)) /* Check PER, FER, ORER flags */ + { + ssrfifo_data = SCI_SSRFIFO; /* SSRFIFO dummy read */ + SCI_SSRFIFO = (uint8_t)~SCI_RCVR_ERR_MASK; /* PER, FER, ORER clear */ + if (0x00 != (SCI_SSRFIFO & SCI_RCVR_ERR_MASK)) + { + R_BSP_NOP(); /* read and Compare */ + } + } + } + } + + return; +} /* End of function sci_fifo_error() */ +#endif /* End of SCI_CFG_FIFO_INCLUDED */ + +/***************************************************************************** +* Function Name: eri_handler +* Description : ERI interrupt handler for SCI UART mode +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* Return Value : none +******************************************************************************/ +void eri_handler(sci_hdl_t const hdl) +{ +#if SCI_CFG_FIFO_INCLUDED + if (true == hdl->fifo_ctrl) + { + /* SCI FIFO Error */ + sci_fifo_error(hdl); + } + else +#endif + { + /* SCI error */ + sci_error(hdl); + } +} /* End of function eri_handler() */ + +/*********************************************************************************************************************** +* Function Name: R_SCI_Control +********************************************************************************************************************//** +* @brief This function configures and controls the operating mode for the SCI channel. +* +* @param[in] hdl Handle for channel. Set hdl when R_SCI_Open() is successfully processed. +* +* @param[in] cmd Command to run (see Section 3. R_SCI_Control() in application note for details) +* +* @param[in] p_args Pointer to arguments (see Section 3. R_SCI_Control() in application note for details) specific to +* command, casted to void * +* +* @retval SCI_SUCCESS Successful; channel initialized. +* +* @retval SCI_ERR_NULL_PTR hdl or p_args pointer is NULL (when required) +* +* @retval SCI_ERR_BAD_MODE Mode specified not currently supported +* +* @retval SCI_ERR_INVALID_ARG +* The cmd value or an element of p_args contains an invalid value. +* @details This function is used for configuring special hardware features such as changing driver configuration and +* obtaining driver status. +* The CTS/ RTS pin functions as RTS by default hardware control. By issuing an SCI_CMD_EN_CTS_IN, the pin functions as CTS. +* @note When SCI_CMD_CHANGE_BAUD is used, the optimum values for BRR, SEMR.ABCS, and SMR.CKS is calculated based on +* the bit rate specified. This however does not guarantee a low bit error rate for all peripheral clock/baud rate +* combinations.\n +* If the command SCI_CMD_EN_CTS_IN is to be used, the pin direction must be selected before calling the +* R_SCI_Open() function, and the pin function and mode must be selected after calling the R_SCI_Open() +* function. See Section 3. R_SCI_Control() for details. +*/ +sci_err_t R_SCI_Control(sci_hdl_t const hdl, + sci_cmd_t const cmd, + void *p_args) +{ + sci_err_t err = SCI_SUCCESS; + sci_baud_t *baud; + int32_t bit_err; + + +#if SCI_CFG_PARAM_CHECKING_ENABLE + /* Check argument hdl */ + if ((NULL == hdl) || (FIT_NO_PTR == hdl)) + { + return SCI_ERR_NULL_PTR; + } + + /* Check argument p_args*/ + if ((NULL == p_args) || (FIT_NO_PTR == p_args)) + { + if (SCI_CMD_CHANGE_BAUD == cmd) + { + return SCI_ERR_NULL_PTR; + } +#if SCI_CFG_FIFO_INCLUDED + if ((SCI_CMD_CHANGE_TX_FIFO_THRESH == cmd) || (SCI_CMD_CHANGE_RX_FIFO_THRESH == cmd)) + { + return SCI_ERR_NULL_PTR; + } +#endif + if ((SCI_CMD_SET_TXI_PRIORITY == cmd) || (SCI_CMD_SET_RXI_PRIORITY == cmd) || (SCI_CMD_SET_TXI_RXI_PRIORITY == cmd)) + { + return SCI_ERR_NULL_PTR; + } + } + if ((SCI_MODE_OFF == hdl->mode) || (SCI_MODE_MAX <= hdl->mode)) + { + return SCI_ERR_BAD_MODE; + } +#if SCI_CFG_FIFO_INCLUDED + if (SCI_CMD_CHANGE_TX_FIFO_THRESH == cmd) + { + /* Casting void* type is valid */ + if (15 < (*(uint8_t *)p_args)) + { + return SCI_ERR_INVALID_ARG; + } + } + if (SCI_CMD_CHANGE_RX_FIFO_THRESH == cmd) + { + /* Casting void* type is valid */ + if ((1 > (*(uint8_t *)p_args)) || (15 < (*(uint8_t *)p_args))) + { + return SCI_ERR_INVALID_ARG; + } + } +#endif + if ((SCI_CMD_SET_TXI_PRIORITY == cmd) || (SCI_CMD_SET_RXI_PRIORITY == cmd) || (SCI_CMD_SET_TXI_RXI_PRIORITY == cmd)) + { + /* Casting void* type is valid */ + if ((1 > (*(uint8_t *)p_args)) || (BSP_MCU_IPL_MAX < (*(uint8_t *)p_args))) + { + return SCI_ERR_INVALID_ARG; + } + } +#endif /* End of SCI_CFG_PARAM_CHECKING_ENABLE */ + + /* COMMANDS COMMON TO ALL MODES */ + + switch (cmd) + { + case (SCI_CMD_CHANGE_BAUD): + { + /* Casting void* type is valid */ + baud = (sci_baud_t *)p_args; + #if (SCI_CFG_ASYNC_INCLUDED) + hdl->pclk_speed = baud->pclk; // save for break generation + #endif + hdl->rom->regs->SCR.BYTE &= (~SCI_EN_XCVR_MASK); + SCI_SCR_DUMMY_READ; + bit_err = sci_init_bit_rate(hdl, baud->pclk, baud->rate); + SCI_IR_TXI_CLEAR; + hdl->rom->regs->SCR.BYTE |= SCI_EN_XCVR_MASK; + if (1000 == bit_err) + { + err = SCI_ERR_INVALID_ARG; // impossible baud rate; 100% error + } + else + { + hdl->baud_rate = baud->rate; // save for break generation + } + break; + } + + case (SCI_CMD_EN_CTS_IN): + { + if (SCI_MODE_SSPI != hdl->mode) + { + /* PFS & port pins must be configured for CTS prior to calling this */ + hdl->rom->regs->SCR.BYTE &= (~SCI_EN_XCVR_MASK); + SCI_SCR_DUMMY_READ; + hdl->rom->regs->SPMR.BIT.CTSE = 1; // enable CTS input + SCI_IR_TXI_CLEAR; + hdl->rom->regs->SCR.BYTE |= SCI_EN_XCVR_MASK; + } + else + { + /* Can not use CTS in smart card interface mode, simple SPI mode, and simple I2C mode */ + err = SCI_ERR_INVALID_ARG; + } + break; + } + +#if SCI_CFG_FIFO_INCLUDED + case (SCI_CMD_CHANGE_TX_FIFO_THRESH): + { + if (true == hdl->fifo_ctrl) + { + #if ((SCI_DTC_DMACA_DISABLE != RX_DTC_DMACA_ENABLE) || (SCI_DTC_DMACA_DISABLE != TX_DTC_DMACA_ENABLE)) + if((SCI_DMACA_ENABLE == hdl->rom->dtc_dmaca_tx_enable) || (SCI_DTC_ENABLE == hdl->rom->dtc_dmaca_tx_enable)) + { + return SCI_ERR_DTC_DMACA_NOT_SUPPORT; + } + #endif + /* save current TX FIFO threshold */ + hdl->tx_curr_thresh = *((uint8_t *)p_args); + + /* change TX FIFO threshold */ + hdl->rom->regs->SCR.BYTE &= (~SCI_EN_XCVR_MASK); + SCI_SCR_DUMMY_READ; + + /* Casting void* type is valid */ + hdl->rom->regs->FCR.BIT.TTRG = *((uint8_t *)p_args); + SCI_IR_TXI_CLEAR; + hdl->rom->regs->SCR.BYTE |= SCI_EN_XCVR_MASK; + } + else + { + err = SCI_ERR_INVALID_ARG; + } + break; + } + + case (SCI_CMD_CHANGE_RX_FIFO_THRESH): + { + if (true == hdl->fifo_ctrl) + { + #if ((SCI_DTC_DMACA_DISABLE != RX_DTC_DMACA_ENABLE) || (SCI_DTC_DMACA_DISABLE != TX_DTC_DMACA_ENABLE)) + if((SCI_DMACA_ENABLE == hdl->rom->dtc_dmaca_rx_enable) || (SCI_DTC_ENABLE == hdl->rom->dtc_dmaca_rx_enable)) + { + return SCI_ERR_DTC_DMACA_NOT_SUPPORT; + } + #endif + /* save current RX FIFO threshold */ + hdl->rx_curr_thresh = *((uint8_t *)p_args); + + /* change RX FIFO threshold */ + hdl->rom->regs->SCR.BYTE &= (~SCI_EN_XCVR_MASK); + SCI_SCR_DUMMY_READ; + + /* Casting void* type is valid */ + hdl->rom->regs->FCR.BIT.RTRG = *((uint8_t *)p_args); + SCI_IR_TXI_CLEAR; + hdl->rom->regs->SCR.BYTE |= SCI_EN_XCVR_MASK; + } + else + { + err = SCI_ERR_INVALID_ARG; + } + break; + } +#endif /* End of SCI_CFG_FIFO_INCLUDED */ + + case (SCI_CMD_SET_TXI_PRIORITY): + { +#if defined(BSP_MCU_RX64M) || defined(BSP_MCU_RX71M) || defined(BSP_MCU_RX65N) || defined(BSP_MCU_RX66T) || defined(BSP_MCU_RX72T) || defined(BSP_MCU_RX72M) || defined(BSP_MCU_RX72N) || defined(BSP_MCU_RX66N)|| defined(BSP_MCU_RX671)|| defined(BSP_MCU_RX660) || defined(BSP_MCU_RX26T) + /* Casting void type to uint8_t type is valid */ + *hdl->rom->ipr_txi = *((uint8_t *)p_args); + break; +#else + /* Casting void type to uint8_t type is valid */ + *hdl->rom->ipr = *((uint8_t *)p_args); + break; +#endif + } + case (SCI_CMD_SET_RXI_PRIORITY): + { +#if defined(BSP_MCU_RX64M) || defined(BSP_MCU_RX71M) || defined(BSP_MCU_RX65N) || defined(BSP_MCU_RX66T) || defined(BSP_MCU_RX72T) || defined(BSP_MCU_RX72M) || defined(BSP_MCU_RX72N) || defined(BSP_MCU_RX66N)|| defined(BSP_MCU_RX671)|| defined(BSP_MCU_RX660) || defined(BSP_MCU_RX26T) + /* Casting void type to uint8_t type is valid */ + *hdl->rom->ipr_rxi = *((uint8_t *)p_args); + break; +#else + /* Casting void type to uint8_t type is valid */ + *hdl->rom->ipr = *((uint8_t *)p_args); + break; +#endif + } + case (SCI_CMD_SET_TXI_RXI_PRIORITY): + { +#if defined(BSP_MCU_RX64M) || defined(BSP_MCU_RX71M) || defined(BSP_MCU_RX65N) || defined(BSP_MCU_RX66T) || defined(BSP_MCU_RX72T) || defined(BSP_MCU_RX72M) || defined(BSP_MCU_RX72N) || defined(BSP_MCU_RX66N)|| defined(BSP_MCU_RX671)|| defined(BSP_MCU_RX660) || defined(BSP_MCU_RX26T) + /* Casting void type to uint8_t type is valid */ + *hdl->rom->ipr_txi = *((uint8_t *)p_args); + *hdl->rom->ipr_rxi = *((uint8_t *)p_args); + break; +#else + /* Casting void type to uint8_t type is valid */ + *hdl->rom->ipr = *((uint8_t *)p_args); + break; +#endif + } + default: + { + /* ASYNC-SPECIFIC COMMANDS */ + if (SCI_MODE_ASYNC == hdl->mode) + { + #if (SCI_CFG_ASYNC_INCLUDED) + err = sci_async_cmds(hdl, cmd, p_args); + #endif + } + /* IRDA-SPECIFIC COMMANDS */ + else if (SCI_MODE_IRDA == hdl->mode) + { + #if (SCI_CFG_IRDA_INCLUDED) + err = sci_irda_cmds(hdl, cmd, p_args); + #endif + } + /* SSPI/SYNC-SPECIFIC COMMANDS */ + else + { + #if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + err = sci_sync_cmds(hdl, cmd, p_args); + #endif + } + break; + } + } + + return err; +} /* End of function R_SCI_Control() */ + +/*********************************************************************************************************************** +* Function Name: R_SCI_Close +********************************************************************************************************************//** +* @brief This function removes power from the SCI channel and disables the associated interrupts. +* +* @param[in] hdl Handle for channel. Set hdl when R_SCI_Open() is successfully processed. +* +* @retval SCI_SUCCESS Successful; channel closed +* +* @retval SCI_ERR_NULL_PTR hdl is NULL +* +* @details Disables the SCI channel designated by the handle and enters module-stop state. +* @note This function will abort any transmission or reception that may be in progress. +*/ +sci_err_t R_SCI_Close(sci_hdl_t const hdl) +{ + +#if SCI_CFG_PARAM_CHECKING_ENABLE + /* Check argument hdl */ + if ((NULL == hdl) || (FIT_NO_PTR == hdl)) + { + return SCI_ERR_NULL_PTR; + } +#endif + + /* disable ICU interrupts */ + sci_disable_ints(hdl); + + /* stop IrDA function */ + if (SCI_MODE_IRDA == hdl->mode) + { +#if (SCI_CFG_IRDA_INCLUDED) + sci_irda_close(hdl); +#endif + } + + /* free tx and rx queues */ +#if (SCI_CFG_ASYNC_INCLUDED || SCI_CFG_IRDA_INCLUDED) + if ((SCI_MODE_ASYNC == hdl->mode) || (SCI_MODE_IRDA == hdl->mode)) + { +#if (TX_DTC_DMACA_ENABLE & 0x01 || TX_DTC_DMACA_ENABLE & 0x02) + /* DTC/DMAC don't use the queue */ + if ((SCI_DTC_ENABLE != hdl->rom->dtc_dmaca_tx_enable) && (SCI_DMACA_ENABLE != hdl->rom->dtc_dmaca_tx_enable)) + { + R_BYTEQ_Close(hdl->u_tx_data.que); + R_BYTEQ_Close(hdl->u_rx_data.que); + } +#else + R_BYTEQ_Close(hdl->u_tx_data.que); + R_BYTEQ_Close(hdl->u_rx_data.que); +#endif + } +#endif +#if (TX_DTC_DMACA_ENABLE & 0x01 || RX_DTC_DMACA_ENABLE & 0x01) + if (SCI_DTC_ENABLE == hdl->rom->dtc_dmaca_tx_enable) + { + sci_dtc_info_transfer_delete(hdl); + } +#endif +#if SCI_CFG_FIFO_INCLUDED + if (true == hdl->fifo_ctrl) + { + /* reset FIFO threshold */ + hdl->rx_curr_thresh = hdl->rx_dflt_thresh; + hdl->tx_curr_thresh = hdl->tx_dflt_thresh; + } +#endif + + /* mark the channel as not in use and power down */ + power_off(hdl); + hdl->mode = SCI_MODE_OFF; + + return SCI_SUCCESS; +} /* End of function R_SCI_Close() */ + + +/*********************************************************************************************************************** +* Function Name: R_SCI_GetVersion +********************************************************************************************************************//** +* @brief This function returns the driver version number at runtime. +* @return Version number. +* @details Returns the version of this module. The version number is encoded such that the top 2 bytes are the major +* version number and the bottom 2 bytes are the minor version number. +* @note None +*/ +uint32_t R_SCI_GetVersion(void) +{ + uint32_t const version = (SCI_VERSION_MAJOR << 16) | SCI_VERSION_MINOR; + + return version; +} /* End of function R_SCI_GetVersion() */ + +#if ((TX_DTC_DMACA_ENABLE & 0x02) && (SCI_CFG_FIFO_INCLUDED)) +/***************************************************************************** +* Function Name: sci_fifo_transfer_dmac +* Description : Handle txi in case this channel use DMAC for transferring. +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* Return Value : none +******************************************************************************/ +static void sci_fifo_transfer_dmac(sci_hdl_t const hdl) +{ + sci_fifo_ctrl_t *p_tctrl = &hdl->queue[hdl->qindex_app_rx]; + if (NULL != p_tctrl->p_tx_fraction_buf) + { + p_tctrl->p_tx_buf = p_tctrl->p_tx_fraction_buf; + p_tctrl->p_tx_fraction_buf = NULL; + } + + if (p_tctrl->tx_cnt > p_tctrl->tx_fraction) + { + p_tctrl->tx_cnt = p_tctrl->tx_fraction; + } + + if (0 != p_tctrl->tx_cnt) + { + /* loop until no more data to send or fifo becomes full */ + /* WAIT_LOOP */ + while ((0 != p_tctrl->tx_cnt) && (SCI_FIFO_FRAME_SIZE != hdl->rom->regs->FDR.BIT.T)) + { + if (NULL == p_tctrl->p_tx_buf) /* Sync only */ + { + hdl->rom->regs->FTDR.BYTE.L = SCI_CFG_DUMMY_TX_BYTE; + } + else + { + hdl->rom->regs->FTDR.BYTE.L = *p_tctrl->p_tx_buf; + p_tctrl->p_tx_buf++; + } + + p_tctrl->tx_cnt--; + + /* if all of current message loaded, set index to next message */ + if (0 == p_tctrl->tx_cnt) + { +#if (SCI_CFG_ASYNC_INCLUDED) + if (SCI_MODE_ASYNC == hdl->mode) + { + hdl->tx_idle = true; + } +#endif + DISABLE_TXI_INT; + } + } + } + + if (1 == hdl->rom->regs->SSRFIFO.BIT.TDFE) + { + /* Casting register 8 bits to unsigned char type is valid */ +#if((TX_DTC_DMACA_ENABLE & 0x02)) + if (SCI_DMACA_ENABLE == hdl->rom->dtc_dmaca_tx_enable) + { + hdl->rom->regs->SSRFIFO.BYTE = (unsigned char)~SCI_SSRFIFO_TDFE_MASK; + } +#endif + } + + if(0 == p_tctrl->tx_cnt) + { +#if (SCI_CFG_ASYNC_INCLUDED) + if (SCI_MODE_ASYNC == hdl->mode) + { + hdl->tx_idle = true; + } +#endif +#if SCI_CFG_TEI_INCLUDED + /* Enable transmit end interrupt */ + hdl->rom->regs->SCR.BIT.TEIE = 1; + ENABLE_TEI_INT; +#endif + DISABLE_TXI_INT; + } +} /* End of function sci_fifo_transfer_dmac() */ +#endif /* ((TX_DTC_DMACA_ENABLE & 0x02) && (SCI_CFG_FIFO_INCLUDED)) */ + +#if ((TX_DTC_DMACA_ENABLE & 0x01) && (SCI_CFG_FIFO_INCLUDED)) + /***************************************************************************** +* Function Name: sci_fifo_transfer_dtc +* Description : Handle txi in case this channel use DTC for transferring. +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* Return Value : none +******************************************************************************/ +static void sci_fifo_transfer_dtc(sci_hdl_t const hdl) +{ + if (SCI_DTC_ENABLE == hdl->rom->dtc_dmaca_tx_enable) + { + sci_fifo_ctrl_t *p_tctrl = &hdl->queue[hdl->qindex_app_rx]; + + hdl->qindex_int_tx ++; + + if (1 == hdl->qindex_int_tx) + { + if ((0 != p_tctrl->tx_fraction) && (hdl->rom->dtc_dmaca_tx_block_size > p_tctrl->total_length)) + { + hdl->qindex_int_tx = 0; + if (0 == p_tctrl->tx_cnt) + { + if (1 == hdl->rom->regs->SSRFIFO.BIT.TDFE) + { + hdl->rom->regs->SSRFIFO.BYTE = (unsigned char)~SCI_SSRFIFO_TDFE_MASK; + } + DISABLE_TXI_INT; + } + else + { + if (NULL != p_tctrl->p_tx_fraction_buf) + { + p_tctrl->p_tx_buf = p_tctrl->p_tx_fraction_buf; + p_tctrl->p_tx_fraction_buf = NULL; + } + if (p_tctrl->tx_cnt > p_tctrl->tx_fraction) + { + p_tctrl->tx_cnt = p_tctrl->tx_fraction; + } + + /* WAIT_LOOP */ + while ((0 != p_tctrl->tx_cnt) && (SCI_FIFO_FRAME_SIZE != hdl->rom->regs->FDR.BIT.T)) + { + if (NULL == p_tctrl->p_tx_buf) /* Sync only */ + { + hdl->rom->regs->FTDR.BYTE.L = SCI_CFG_DUMMY_TX_BYTE; + } + else + { + hdl->rom->regs->FTDR.BYTE.L = *p_tctrl->p_tx_buf; + p_tctrl->p_tx_buf++; + } + p_tctrl->tx_cnt--; + } + + DISABLE_TXI_INT; +#if SCI_CFG_TEI_INCLUDED + /* Enable transmit end interrupt */ + hdl->rom->regs->SCR.BIT.TEIE = 1; + ENABLE_TEI_INT; +#endif + +#if (SCI_CFG_ASYNC_INCLUDED) + if (SCI_MODE_ASYNC == hdl->mode) + { + hdl->tx_idle = true; + } +#endif + if (1 == hdl->rom->regs->SSRFIFO.BIT.TDFE) + { + hdl->rom->regs->SSRFIFO.BYTE = (unsigned char)~SCI_SSRFIFO_TDFE_MASK; + } + } + } + } + else if(2 == hdl->qindex_int_tx) //The second time is SCI interrupt, will clear TDFE bit here. + { + hdl->qindex_int_tx = 0; + if (NULL != p_tctrl->p_tx_fraction_buf) + { + p_tctrl->p_tx_buf = p_tctrl->p_tx_fraction_buf; + p_tctrl->p_tx_fraction_buf = NULL; + } + + if (p_tctrl->tx_cnt > p_tctrl->tx_fraction) + { + p_tctrl->tx_cnt = p_tctrl->tx_fraction; + } + + if (0 != p_tctrl->tx_cnt) + { + /* loop until no more data to send or fifo becomes full */ + /* WAIT_LOOP */ + while ((0 != p_tctrl->tx_cnt) && (SCI_FIFO_FRAME_SIZE != hdl->rom->regs->FDR.BIT.T)) + { + if (NULL == p_tctrl->p_tx_buf) /* Sync only */ + { + hdl->rom->regs->FTDR.BYTE.L = SCI_CFG_DUMMY_TX_BYTE; + } + else + { + hdl->rom->regs->FTDR.BYTE.L = *p_tctrl->p_tx_buf; + p_tctrl->p_tx_buf++; + } + + p_tctrl->tx_cnt--; + + /* if all of current message loaded, set index to next message */ + if (0 == p_tctrl->tx_cnt) + { +#if (SCI_CFG_ASYNC_INCLUDED) + if (SCI_MODE_ASYNC == hdl->mode) + { + hdl->tx_idle = true; + } +#endif + DISABLE_TXI_INT; + } + } + } + + if (1 == hdl->rom->regs->SSRFIFO.BIT.TDFE) + { + /* Casting register 8 bits to unsigned char type is valid */ + + hdl->rom->regs->SSRFIFO.BYTE = (unsigned char)~SCI_SSRFIFO_TDFE_MASK; + } + + if(0 == p_tctrl->tx_cnt) + { +#if (SCI_CFG_ASYNC_INCLUDED) + if (SCI_MODE_ASYNC == hdl->mode) + { + hdl->tx_idle = true; + } +#endif +#if SCI_CFG_TEI_INCLUDED + /* Enable transmit end interrupt */ + hdl->rom->regs->SCR.BIT.TEIE = 1; + ENABLE_TEI_INT; +#endif + DISABLE_TXI_INT; + } + } + } +} /* End of function sci_fifo_transfer_dmac() */ +#endif /* ((TX_DTC_DMACA_ENABLE & 0x01) && (SCI_CFG_FIFO_INCLUDED)) */ diff --git a/drivers/rx/rdp/src/r_sci_rx/src/r_sci_rx_dmaca.c b/drivers/rx/rdp/src/r_sci_rx/src/r_sci_rx_dmaca.c new file mode 100644 index 00000000..210b2653 --- /dev/null +++ b/drivers/rx/rdp/src/r_sci_rx/src/r_sci_rx_dmaca.c @@ -0,0 +1,1277 @@ +/********************************************************************************************************************** + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No + * other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all + * applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM + * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES + * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO + * THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of + * this software. By using this software, you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * + * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. + *********************************************************************************************************************/ +/********************************************************************************************************************** +* File Name : r_sci_rx_dmaca.c +* Description : +*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* 25.08.2020 1.00 Initial Release +* 31.03.2021 3.80 Added support for RX671. +* 31.03.2022 4.40 Added support for RX660. +* 27.12.2022 4.60 Fixed the issue that rx_idle is not changed to true when reception is complete +* in DMAC mode. +* 31.03.2023 4.80 Added support for RX26T. +* Fixed to comply with GSCE Coding Standards Rev.6.5.0. +* 13.03.2024 5.20 Fixed the issue that repeat_block_side had an unexpected value +* in the sci_tx_dmaca_create() and sci_rx_dmaca_create() functions. +***********************************************************************************************************************/ + +/********************************************************************************************************************** + Includes , "Project Includes" + *********************************************************************************************************************/ +#include "platform.h" +#include "r_sci_rx_private.h" +#include "r_sci_rx_if.h" +#if ((TX_DTC_DMACA_ENABLE & 0x02) || (RX_DTC_DMACA_ENABLE & 0x02)) +#include "r_dmaca_rx_if.h" +#include "r_sci_rx_dmaca.h" +#include "r_sci_rx_platform.h" + +/********************************************************************************************************************** + Macro definitions + *********************************************************************************************************************/ +#define SCI_PRV_RX_FIFO_THRESHOLD (hdl->rom->regs->FCR.BIT.RTRG) + +/********************************************************************************************************************** + Typedef definitions + *********************************************************************************************************************/ + +/********************************************************************************************************************** + Exported global variables + *********************************************************************************************************************/ + + +/********************************************************************************************************************** + Private (static) variables and functions + *********************************************************************************************************************/ +static void sci0_dmac_rx_callback(void); +static void sci1_dmac_rx_callback(void); +static void sci2_dmac_rx_callback(void); +static void sci3_dmac_rx_callback(void); +static void sci4_dmac_rx_callback(void); +static void sci5_dmac_rx_callback(void); +static void sci6_dmac_rx_callback(void); +static void sci7_dmac_rx_callback(void); +static void sci8_dmac_rx_callback(void); +static void sci9_dmac_rx_callback(void); +static void sci10_dmac_rx_callback(void); +static void sci11_dmac_rx_callback(void); +static void sci12_dmac_rx_callback(void); +static void sci_dmac_rx_handler(sci_hdl_t const hdl); + +static void sci0_dmac_tx_callback(void); +static void sci1_dmac_tx_callback(void); +static void sci2_dmac_tx_callback(void); +static void sci3_dmac_tx_callback(void); +static void sci4_dmac_tx_callback(void); +static void sci5_dmac_tx_callback(void); +static void sci6_dmac_tx_callback(void); +static void sci7_dmac_tx_callback(void); +static void sci8_dmac_tx_callback(void); +static void sci9_dmac_tx_callback(void); +static void sci10_dmac_tx_callback(void); +static void sci11_dmac_tx_callback(void); +static void sci12_dmac_tx_callback(void); +static void sci_dmac_tx_handler(sci_hdl_t const hdl); + +static uint8_t tx_dummy_buf = SCI_CFG_DUMMY_TX_BYTE; +static uint8_t rx_dummy_buf; + +#if SCI_CFG_FIFO_INCLUDED +/********************************************************************************************************************** +* Function Name: sci_txfifo_dmaca_create +* Description : This function create DMAC to transmit data from p_src to SCI TX FIFO (by DMAC without CPU) +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* p_src - +* The address of source data need to be sent +* lenght - +* The number of data need to be sent +* Return Value : SCI_SUCCESS - +* Create DMAC successfully +* SCI_ERR_DMACA - +* Create DMAC NOT successfully + *********************************************************************************************************************/ +sci_err_t sci_txfifo_dmaca_create(sci_hdl_t const hdl, uint8_t *p_src, uint16_t const length) +{ + sci_err_t err_sci = SCI_SUCCESS; + dmaca_return_t err_dmaca = DMACA_SUCCESS; + dmaca_stat_t stat_dmaca; + dmaca_transfer_data_cfg_t tx_cfg_dmaca; + sci_fifo_ctrl_t *p_tctrl_dma; + p_tctrl_dma = &hdl->queue[hdl->qindex_app_tx]; + + tx_cfg_dmaca.act_source = hdl->rom->dmaca_tx_act_src; + tx_cfg_dmaca.transfer_mode = DMACA_TRANSFER_MODE_BLOCK; + tx_cfg_dmaca.data_size = DMACA_DATA_SIZE_BYTE; + tx_cfg_dmaca.dtie_request = DMACA_TRANSFER_END_INTERRUPT_ENABLE; + tx_cfg_dmaca.interrupt_sel = DMACA_CLEAR_INTERRUPT_FLAG_BEGINNING_TRANSFER; + tx_cfg_dmaca.des_addr_mode = DMACA_DES_ADDR_FIXED; + tx_cfg_dmaca.p_des_addr = (void *)&hdl->rom->regs->FTDR.BYTE.L; + + tx_cfg_dmaca.request_source = DMACA_TRANSFER_REQUEST_PERIPHERAL; + tx_cfg_dmaca.esie_request = DMACA_TRANSFER_ESCAPE_END_INTERRUPT_DISABLE; + tx_cfg_dmaca.rptie_request = DMACA_REPEAT_SIZE_END_INTERRUPT_DISABLE; + tx_cfg_dmaca.sarie_request = DMACA_SRC_ADDR_EXT_REP_AREA_OVER_INTERRUPT_DISABLE; + tx_cfg_dmaca.darie_request = DMACA_DES_ADDR_EXT_REP_AREA_OVER_INTERRUPT_DISABLE; + tx_cfg_dmaca.src_addr_repeat_area = DMACA_SRC_ADDR_EXT_REP_AREA_NONE; + tx_cfg_dmaca.des_addr_repeat_area = DMACA_DES_ADDR_EXT_REP_AREA_NONE; + tx_cfg_dmaca.offset_value = 0; + + if (NULL == p_src) + { + tx_cfg_dmaca.repeat_block_side = DMACA_REPEAT_BLOCK_SOURCE; + tx_cfg_dmaca.src_addr_mode = DMACA_SRC_ADDR_FIXED; + tx_cfg_dmaca.p_src_addr = (void *)&tx_dummy_buf; + } + else + { + tx_cfg_dmaca.repeat_block_side = DMACA_REPEAT_BLOCK_DESTINATION; + tx_cfg_dmaca.src_addr_mode = DMACA_SRC_ADDR_INCR; + tx_cfg_dmaca.p_src_addr = (void *)p_src; + } + + tx_cfg_dmaca.transfer_count = (uint32_t)(length / hdl->rom->dtc_dmaca_tx_block_size); + tx_cfg_dmaca.block_size = hdl->rom->dtc_dmaca_tx_block_size; + + err_dmaca = R_DMACA_Open(hdl->rom->dmaca_tx_channel); + if (DMACA_SUCCESS == err_dmaca) + { + err_dmaca = R_DMACA_Control(hdl->rom->dmaca_tx_channel, DMACA_CMD_DISABLE, &stat_dmaca); + } + + if (DMACA_SUCCESS == err_dmaca) + { + if (length >= tx_cfg_dmaca.block_size) + { + if (NULL == p_src) + { + p_tctrl_dma->p_tx_fraction_buf = NULL; + } + else + { + p_tctrl_dma->p_tx_fraction_buf = (uint8_t*)((uint32_t)tx_cfg_dmaca.p_src_addr + (tx_cfg_dmaca.transfer_count * tx_cfg_dmaca.block_size)); + } + + p_tctrl_dma->tx_fraction = (length - (tx_cfg_dmaca.transfer_count * tx_cfg_dmaca.block_size)); + + if (SCI_CH0 == hdl->rom->chan) + { + err_dmaca = R_DMACA_Int_Callback(hdl->rom->dmaca_tx_channel,(void *)sci0_dmac_tx_callback); + } + else if (SCI_CH1 == hdl->rom->chan) + { + err_dmaca = R_DMACA_Int_Callback(hdl->rom->dmaca_tx_channel,(void *)sci1_dmac_tx_callback); + } + else if (SCI_CH2 == hdl->rom->chan) + { + err_dmaca = R_DMACA_Int_Callback(hdl->rom->dmaca_tx_channel,(void *)sci2_dmac_tx_callback); + } + else if (SCI_CH3 == hdl->rom->chan) + { + err_dmaca = R_DMACA_Int_Callback(hdl->rom->dmaca_tx_channel,(void *)sci3_dmac_tx_callback); + } + else if (SCI_CH4 == hdl->rom->chan) + { + err_dmaca = R_DMACA_Int_Callback(hdl->rom->dmaca_tx_channel,(void *)sci4_dmac_tx_callback); + } + else if (SCI_CH5 == hdl->rom->chan) + { + err_dmaca = R_DMACA_Int_Callback(hdl->rom->dmaca_tx_channel,(void *)sci5_dmac_tx_callback); + } + else if (SCI_CH6 == hdl->rom->chan) + { + err_dmaca = R_DMACA_Int_Callback(hdl->rom->dmaca_tx_channel,(void *)sci6_dmac_tx_callback); + } + else if (SCI_CH7 == hdl->rom->chan) + { + err_dmaca = R_DMACA_Int_Callback(hdl->rom->dmaca_tx_channel,(void *)sci7_dmac_tx_callback); + } + else if (SCI_CH8 == hdl->rom->chan) + { + err_dmaca = R_DMACA_Int_Callback(hdl->rom->dmaca_tx_channel,(void *)sci8_dmac_tx_callback); + } + else if (SCI_CH9 == hdl->rom->chan) + { + err_dmaca = R_DMACA_Int_Callback(hdl->rom->dmaca_tx_channel,(void *)sci9_dmac_tx_callback); + } + else if (SCI_CH10 == hdl->rom->chan) + { + err_dmaca = R_DMACA_Int_Callback(hdl->rom->dmaca_tx_channel,(void *)sci10_dmac_tx_callback); + } + else if (SCI_CH11 == hdl->rom->chan) + { + err_dmaca = R_DMACA_Int_Callback(hdl->rom->dmaca_tx_channel,(void *)sci11_dmac_tx_callback); + } + else if (SCI_CH12 == hdl->rom->chan) + { + err_dmaca = R_DMACA_Int_Callback(hdl->rom->dmaca_tx_channel,(void *)sci12_dmac_tx_callback); + } + else + { + err_dmaca = DMACA_ERR_INTERNAL; + } + + if (DMACA_SUCCESS == err_dmaca) + { + err_dmaca = R_DMACA_Create(hdl->rom->dmaca_tx_channel, &tx_cfg_dmaca); + } + +#if defined(BSP_MCU_RX64M) || defined(BSP_MCU_RX71M) || defined(BSP_MCU_RX65N) || defined(BSP_MCU_RX66T) || defined(BSP_MCU_RX72T) || defined(BSP_MCU_RX72M) || defined(BSP_MCU_RX72N) || defined(BSP_MCU_RX66N)|| defined(BSP_MCU_RX671) || defined(BSP_MCU_RX660) || defined(BSP_MCU_RX26T) + err_dmaca = R_DMACA_Int_Enable(hdl->rom->dmaca_tx_channel, *hdl->rom->ipr_txi); +#else + err_dmaca = R_DMACA_Int_Enable(hdl->rom->dmaca_tx_channel, *hdl->rom->ipr); +#endif + if (DMACA_SUCCESS == err_dmaca) + { + err_dmaca = R_DMACA_Control(hdl->rom->dmaca_tx_channel, DMACA_CMD_ENABLE, &stat_dmaca); + } + } + else + { + p_tctrl_dma->p_tx_fraction_buf = p_src; + p_tctrl_dma->tx_fraction = length; + } + } + + if (DMACA_SUCCESS != err_dmaca) + { + err_sci = SCI_ERR_DMACA; + } + + return err_sci; +} +/********************************************************************************************************************** + End of function sci_txfifo_dmaca_create + *********************************************************************************************************************/ + +/********************************************************************************************************************** +* Function Name: sci_rxfifo_dmaca_create +* Description : This function create DMAC to receive data from SCI RX FIFO and save to p_dst (by DMAC without CPU) +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* p_dst - +* The address of destination need to be saved +* lenght - +* The number of data need to be received +* Return Value : SCI_SUCCESS - +* Create DMAC successfully +* SCI_ERR_DMACA - +* Create DMAC NOT successfully + *********************************************************************************************************************/ +sci_err_t sci_rxfifo_dmaca_create(sci_hdl_t const hdl, uint8_t *p_dst, uint16_t const length) +{ + sci_fifo_ctrl_t *p_rctrl_dma; + dmaca_transfer_data_cfg_t rx_cfg_dmaca; + sci_err_t err_sci = SCI_SUCCESS; + dmaca_return_t err_dmaca = DMACA_SUCCESS; + dmaca_stat_t stat_dmaca; + p_rctrl_dma = &hdl->queue[hdl->qindex_app_rx]; + + rx_cfg_dmaca.act_source = hdl->rom->dmaca_rx_act_src; + rx_cfg_dmaca.transfer_mode = DMACA_TRANSFER_MODE_BLOCK; + rx_cfg_dmaca.data_size = DMACA_DATA_SIZE_BYTE; + rx_cfg_dmaca.dtie_request = DMACA_TRANSFER_END_INTERRUPT_ENABLE; + rx_cfg_dmaca.interrupt_sel = DMACA_CLEAR_INTERRUPT_FLAG_BEGINNING_TRANSFER; + rx_cfg_dmaca.src_addr_mode = DMACA_SRC_ADDR_FIXED; + rx_cfg_dmaca.p_src_addr = (void *)&hdl->rom->regs->FRDR.BYTE.L; + + rx_cfg_dmaca.request_source = DMACA_TRANSFER_REQUEST_PERIPHERAL; + rx_cfg_dmaca.esie_request = DMACA_TRANSFER_ESCAPE_END_INTERRUPT_DISABLE; + rx_cfg_dmaca.rptie_request = DMACA_REPEAT_SIZE_END_INTERRUPT_DISABLE; + rx_cfg_dmaca.sarie_request = DMACA_SRC_ADDR_EXT_REP_AREA_OVER_INTERRUPT_DISABLE; + rx_cfg_dmaca.darie_request = DMACA_DES_ADDR_EXT_REP_AREA_OVER_INTERRUPT_DISABLE; + rx_cfg_dmaca.src_addr_repeat_area = DMACA_SRC_ADDR_EXT_REP_AREA_NONE; + rx_cfg_dmaca.des_addr_repeat_area = DMACA_DES_ADDR_EXT_REP_AREA_NONE; + rx_cfg_dmaca.offset_value = 0; + + if (NULL == p_dst) + { + rx_cfg_dmaca.repeat_block_side = DMACA_REPEAT_BLOCK_DESTINATION; + rx_cfg_dmaca.des_addr_mode = DMACA_DES_ADDR_FIXED; + rx_cfg_dmaca.p_des_addr = (void *)&rx_dummy_buf; + } + else + { + rx_cfg_dmaca.repeat_block_side = DMACA_REPEAT_BLOCK_SOURCE; + rx_cfg_dmaca.des_addr_mode = DMACA_DES_ADDR_INCR; + rx_cfg_dmaca.p_des_addr = (void *)p_dst; + } + + rx_cfg_dmaca.transfer_count = (uint32_t)(length / hdl->rom->dtc_dmaca_rx_block_size); + rx_cfg_dmaca.block_size = hdl->rom->dtc_dmaca_rx_block_size; + + err_dmaca = R_DMACA_Open(hdl->rom->dmaca_rx_channel); + if (DMACA_SUCCESS == err_dmaca) + { + err_dmaca = R_DMACA_Control(hdl->rom->dmaca_rx_channel, DMACA_CMD_DISABLE, &stat_dmaca); + } + + if (DMACA_SUCCESS == err_dmaca) + { + if (length >= hdl->rx_dflt_thresh) + { + if (NULL == p_dst) + { + p_rctrl_dma->p_rx_fraction_buf = NULL; + } + else + { + p_rctrl_dma->p_rx_fraction_buf = (uint8_t*)((uint32_t)rx_cfg_dmaca.p_des_addr + (rx_cfg_dmaca.transfer_count * rx_cfg_dmaca.block_size)); + } + + p_rctrl_dma->rx_fraction = (length - (rx_cfg_dmaca.transfer_count * rx_cfg_dmaca.block_size)); + SCI_PRV_RX_FIFO_THRESHOLD = hdl->rx_dflt_thresh; + + if (SCI_CH0 == hdl->rom->chan) + { + err_dmaca = R_DMACA_Int_Callback(hdl->rom->dmaca_rx_channel,(void *)sci0_dmac_rx_callback); + } + else if (SCI_CH1 == hdl->rom->chan) + { + err_dmaca = R_DMACA_Int_Callback(hdl->rom->dmaca_rx_channel,(void *)sci1_dmac_rx_callback); + } + else if (SCI_CH2 == hdl->rom->chan) + { + err_dmaca = R_DMACA_Int_Callback(hdl->rom->dmaca_rx_channel,(void *)sci2_dmac_rx_callback); + } + else if (SCI_CH3 == hdl->rom->chan) + { + err_dmaca = R_DMACA_Int_Callback(hdl->rom->dmaca_rx_channel,(void *)sci3_dmac_rx_callback); + } + else if (SCI_CH4 == hdl->rom->chan) + { + err_dmaca = R_DMACA_Int_Callback(hdl->rom->dmaca_rx_channel,(void *)sci4_dmac_rx_callback); + } + else if (SCI_CH5 == hdl->rom->chan) + { + err_dmaca = R_DMACA_Int_Callback(hdl->rom->dmaca_rx_channel,(void *)sci5_dmac_rx_callback); + } + else if (SCI_CH6 == hdl->rom->chan) + { + err_dmaca = R_DMACA_Int_Callback(hdl->rom->dmaca_rx_channel,(void *)sci6_dmac_rx_callback); + } + else if (SCI_CH7 == hdl->rom->chan) + { + err_dmaca = R_DMACA_Int_Callback(hdl->rom->dmaca_rx_channel,(void *)sci7_dmac_rx_callback); + } + else if (SCI_CH8 == hdl->rom->chan) + { + err_dmaca = R_DMACA_Int_Callback(hdl->rom->dmaca_rx_channel,(void *)sci8_dmac_rx_callback); + } + else if (SCI_CH9 == hdl->rom->chan) + { + err_dmaca = R_DMACA_Int_Callback(hdl->rom->dmaca_rx_channel,(void *)sci9_dmac_rx_callback); + } + else if (SCI_CH10 == hdl->rom->chan) + { + err_dmaca = R_DMACA_Int_Callback(hdl->rom->dmaca_rx_channel,(void *)sci10_dmac_rx_callback); + } + else if (SCI_CH11 == hdl->rom->chan) + { + err_dmaca = R_DMACA_Int_Callback(hdl->rom->dmaca_rx_channel,(void *)sci11_dmac_rx_callback); + } + else if (SCI_CH12 == hdl->rom->chan) + { + err_dmaca = R_DMACA_Int_Callback(hdl->rom->dmaca_rx_channel,(void *)sci12_dmac_rx_callback); + } + else + { + err_dmaca = DMACA_ERR_INTERNAL; + } + + if (DMACA_SUCCESS == err_dmaca) + { + err_dmaca = R_DMACA_Create(hdl->rom->dmaca_rx_channel, &rx_cfg_dmaca); + } + if (DMACA_SUCCESS == err_dmaca) + { + err_dmaca = R_DMACA_Int_Enable(hdl->rom->dmaca_rx_channel, *hdl->rom->ipr_rxi); + } + if (DMACA_SUCCESS == err_dmaca) + { + err_dmaca = R_DMACA_Control(hdl->rom->dmaca_rx_channel, DMACA_CMD_ENABLE, &stat_dmaca); + } + } + else + { + p_rctrl_dma->p_rx_fraction_buf = p_dst; + p_rctrl_dma->rx_fraction = length; + SCI_PRV_RX_FIFO_THRESHOLD = length; + } + } + + if (DMACA_SUCCESS != err_dmaca) + { + err_sci = SCI_ERR_DMACA; + } + + return err_sci; +} +/********************************************************************************************************************** + End of function sci_rxfifo_dmaca_create + *********************************************************************************************************************/ + +#endif /* End of SCI_CFG_FIFO_INCLUDED */ + + +/********************************************************************************************************************** +* Function Name: sci_tx_dmaca_create +* Description : This function create DMAC to transmit data from p_src to SCI TDR (by DMAC without CPU) +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* p_src - +* The address of source data need to be sent +* lenght - +* The number of data need to be sent +* Return Value : SCI_SUCCESS - +* Create DMAC successfully +* SCI_ERR_DMACA - +* Create DMAC NOT successfully + *********************************************************************************************************************/ +sci_err_t sci_tx_dmaca_create(sci_hdl_t const hdl, uint8_t *p_src, uint16_t const length) +{ + sci_fifo_ctrl_t *p_tctrl_dma; + dmaca_transfer_data_cfg_t tx_cfg_dmaca; + sci_err_t err_sci = SCI_SUCCESS; + dmaca_return_t err_dmaca = DMACA_SUCCESS; + dmaca_stat_t stat_dmaca; + + + p_tctrl_dma = &hdl->queue[hdl->qindex_app_tx]; + + tx_cfg_dmaca.act_source = hdl->rom->dmaca_tx_act_src; + tx_cfg_dmaca.transfer_mode = DMACA_TRANSFER_MODE_NORMAL; + tx_cfg_dmaca.data_size = DMACA_DATA_SIZE_BYTE; + tx_cfg_dmaca.dtie_request = DMACA_TRANSFER_END_INTERRUPT_ENABLE; + tx_cfg_dmaca.interrupt_sel = DMACA_CLEAR_INTERRUPT_FLAG_BEGINNING_TRANSFER; + tx_cfg_dmaca.des_addr_mode = DMACA_DES_ADDR_FIXED; + tx_cfg_dmaca.p_des_addr = (void *)&hdl->rom->regs->TDR; + + tx_cfg_dmaca.request_source = DMACA_TRANSFER_REQUEST_PERIPHERAL; + tx_cfg_dmaca.esie_request = DMACA_TRANSFER_ESCAPE_END_INTERRUPT_DISABLE; + tx_cfg_dmaca.rptie_request = DMACA_REPEAT_SIZE_END_INTERRUPT_DISABLE; + tx_cfg_dmaca.sarie_request = DMACA_SRC_ADDR_EXT_REP_AREA_OVER_INTERRUPT_DISABLE; + tx_cfg_dmaca.darie_request = DMACA_DES_ADDR_EXT_REP_AREA_OVER_INTERRUPT_DISABLE; + tx_cfg_dmaca.src_addr_repeat_area = DMACA_SRC_ADDR_EXT_REP_AREA_NONE; + tx_cfg_dmaca.des_addr_repeat_area = DMACA_DES_ADDR_EXT_REP_AREA_NONE; + tx_cfg_dmaca.offset_value = 0; + + if (NULL == p_src) + { + tx_cfg_dmaca.repeat_block_side = DMACA_REPEAT_BLOCK_DESTINATION; + tx_cfg_dmaca.src_addr_mode = DMACA_SRC_ADDR_FIXED; + tx_cfg_dmaca.p_src_addr = (void *)&tx_dummy_buf; + } + else + { + tx_cfg_dmaca.repeat_block_side = DMACA_REPEAT_BLOCK_DESTINATION; + tx_cfg_dmaca.src_addr_mode = DMACA_SRC_ADDR_INCR; + tx_cfg_dmaca.p_src_addr = (void *)p_src; + } + + tx_cfg_dmaca.transfer_count = (uint32_t)(length); + + err_dmaca = R_DMACA_Open(hdl->rom->dmaca_tx_channel); + if (DMACA_SUCCESS == err_dmaca) + { + err_dmaca = R_DMACA_Control(hdl->rom->dmaca_tx_channel, DMACA_CMD_DISABLE, &stat_dmaca); + } + + if (DMACA_SUCCESS == err_dmaca) + { + if (length > 0) + { + if (NULL == p_src) + { + p_tctrl_dma->p_tx_fraction_buf = NULL; + } + else + { + p_tctrl_dma->p_tx_fraction_buf = (uint8_t*)((uint32_t)tx_cfg_dmaca.p_src_addr); + } + + p_tctrl_dma->tx_fraction = 0; + if (SCI_CH0 == hdl->rom->chan) + { + err_dmaca = R_DMACA_Int_Callback(hdl->rom->dmaca_tx_channel,(void *)sci0_dmac_tx_callback); + } + else if (SCI_CH1 == hdl->rom->chan) + { + err_dmaca = R_DMACA_Int_Callback(hdl->rom->dmaca_tx_channel,(void *)sci1_dmac_tx_callback); + } + else if (SCI_CH2 == hdl->rom->chan) + { + err_dmaca = R_DMACA_Int_Callback(hdl->rom->dmaca_tx_channel,(void *)sci2_dmac_tx_callback); + } + else if (SCI_CH3 == hdl->rom->chan) + { + err_dmaca = R_DMACA_Int_Callback(hdl->rom->dmaca_tx_channel,(void *)sci3_dmac_tx_callback); + } + else if (SCI_CH4 == hdl->rom->chan) + { + err_dmaca = R_DMACA_Int_Callback(hdl->rom->dmaca_tx_channel,(void *)sci4_dmac_tx_callback); + } + else if (SCI_CH5 == hdl->rom->chan) + { + err_dmaca = R_DMACA_Int_Callback(hdl->rom->dmaca_tx_channel,(void *)sci5_dmac_tx_callback); + } + else if (SCI_CH6 == hdl->rom->chan) + { + err_dmaca = R_DMACA_Int_Callback(hdl->rom->dmaca_tx_channel,(void *)sci6_dmac_tx_callback); + } + else if (SCI_CH7 == hdl->rom->chan) + { + err_dmaca = R_DMACA_Int_Callback(hdl->rom->dmaca_tx_channel,(void *)sci7_dmac_tx_callback); + } + else if (SCI_CH8 == hdl->rom->chan) + { + err_dmaca = R_DMACA_Int_Callback(hdl->rom->dmaca_tx_channel,(void *)sci8_dmac_tx_callback); + } + else if (SCI_CH9 == hdl->rom->chan) + { + err_dmaca = R_DMACA_Int_Callback(hdl->rom->dmaca_tx_channel,(void *)sci9_dmac_tx_callback); + } + else if (SCI_CH10 == hdl->rom->chan) + { + err_dmaca = R_DMACA_Int_Callback(hdl->rom->dmaca_tx_channel,(void *)sci10_dmac_tx_callback); + } + else if (SCI_CH11 == hdl->rom->chan) + { + err_dmaca = R_DMACA_Int_Callback(hdl->rom->dmaca_tx_channel,(void *)sci11_dmac_tx_callback); + } + else if (SCI_CH12 == hdl->rom->chan) + { + err_dmaca = R_DMACA_Int_Callback(hdl->rom->dmaca_tx_channel,(void *)sci12_dmac_tx_callback); + } + else + { + err_dmaca = DMACA_ERR_INTERNAL; + } + + if (DMACA_SUCCESS == err_dmaca) + { + err_dmaca = R_DMACA_Create(hdl->rom->dmaca_tx_channel, &tx_cfg_dmaca); + } + +#if defined(BSP_MCU_RX64M) || defined(BSP_MCU_RX71M) || defined(BSP_MCU_RX65N) || defined(BSP_MCU_RX66T) || defined(BSP_MCU_RX72T) || defined(BSP_MCU_RX72M) || defined(BSP_MCU_RX72N) || defined(BSP_MCU_RX66N)|| defined(BSP_MCU_RX671)|| defined(BSP_MCU_RX660) || defined(BSP_MCU_RX26T) + err_dmaca = R_DMACA_Int_Enable(hdl->rom->dmaca_tx_channel, *hdl->rom->ipr_txi); +#else + err_dmaca = R_DMACA_Int_Enable(hdl->rom->dmaca_tx_channel, *hdl->rom->ipr); +#endif + if (DMACA_SUCCESS == err_dmaca) + { + err_dmaca = R_DMACA_Control(hdl->rom->dmaca_tx_channel, DMACA_CMD_ENABLE, &stat_dmaca); + } + } + else + { + + } + } + + if (DMACA_SUCCESS != err_dmaca) + { + err_sci = SCI_ERR_DMACA; + } + + return err_sci; +} +/********************************************************************************************************************** + End of function sci_tx_dmaca_create + *********************************************************************************************************************/ + +/********************************************************************************************************************** +* Function Name: sci_rx_dmaca_create +* Description : This function create DMAC to receive data from SCI RDR and save to p_dst (by DMAC without CPU) +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* p_dst - +* The address of destination need to be saved +* lenght - +* The number of data need to be received +* Return Value : SCI_SUCCESS - +* Create DMAC successfully +* SCI_ERR_DMACA - +* Create DMAC NOT successfully + *********************************************************************************************************************/ +sci_err_t sci_rx_dmaca_create(sci_hdl_t const hdl, uint8_t *p_dst, uint16_t const length) +{ + sci_fifo_ctrl_t *p_rctrl_dma; + sci_err_t err_sci = SCI_SUCCESS; + dmaca_return_t err_dmaca = DMACA_SUCCESS; + dmaca_stat_t stat_dmaca; + dmaca_transfer_data_cfg_t rx_cfg_dmaca; + + p_rctrl_dma = &hdl->queue[hdl->qindex_app_rx]; + + rx_cfg_dmaca.act_source = hdl->rom->dmaca_rx_act_src; + rx_cfg_dmaca.transfer_mode = DMACA_TRANSFER_MODE_NORMAL; + rx_cfg_dmaca.data_size = DMACA_DATA_SIZE_BYTE; + rx_cfg_dmaca.dtie_request = DMACA_TRANSFER_END_INTERRUPT_ENABLE; + rx_cfg_dmaca.interrupt_sel = DMACA_CLEAR_INTERRUPT_FLAG_BEGINNING_TRANSFER; + rx_cfg_dmaca.src_addr_mode = DMACA_SRC_ADDR_FIXED; + rx_cfg_dmaca.p_src_addr = (void *)&hdl->rom->regs->RDR; + + rx_cfg_dmaca.request_source = DMACA_TRANSFER_REQUEST_PERIPHERAL; + rx_cfg_dmaca.esie_request = DMACA_TRANSFER_ESCAPE_END_INTERRUPT_DISABLE; + rx_cfg_dmaca.rptie_request = DMACA_REPEAT_SIZE_END_INTERRUPT_DISABLE; + rx_cfg_dmaca.sarie_request = DMACA_SRC_ADDR_EXT_REP_AREA_OVER_INTERRUPT_DISABLE; + rx_cfg_dmaca.darie_request = DMACA_DES_ADDR_EXT_REP_AREA_OVER_INTERRUPT_DISABLE; + rx_cfg_dmaca.src_addr_repeat_area = DMACA_SRC_ADDR_EXT_REP_AREA_NONE; + rx_cfg_dmaca.des_addr_repeat_area = DMACA_DES_ADDR_EXT_REP_AREA_NONE; + rx_cfg_dmaca.offset_value = 0; + + if (NULL == p_dst) + { + rx_cfg_dmaca.repeat_block_side = DMACA_REPEAT_BLOCK_DESTINATION; + rx_cfg_dmaca.des_addr_mode = DMACA_DES_ADDR_FIXED; + rx_cfg_dmaca.p_des_addr = (void *)&rx_dummy_buf; + } + else + { + rx_cfg_dmaca.repeat_block_side = DMACA_REPEAT_BLOCK_DESTINATION; + rx_cfg_dmaca.des_addr_mode = DMACA_DES_ADDR_INCR; + rx_cfg_dmaca.p_des_addr = (void *)p_dst; + } + + rx_cfg_dmaca.transfer_count = (uint32_t)(length); + + err_dmaca = R_DMACA_Open(hdl->rom->dmaca_rx_channel); + if (DMACA_SUCCESS == err_dmaca) + { + err_dmaca = R_DMACA_Control(hdl->rom->dmaca_rx_channel, DMACA_CMD_DISABLE, &stat_dmaca); + } + + if (DMACA_SUCCESS == err_dmaca) + { + if (length > 0) + { + if (NULL == p_dst) + { + p_rctrl_dma->p_rx_fraction_buf = NULL; + } + else + { + p_rctrl_dma->p_rx_fraction_buf = (uint8_t*)((uint32_t)rx_cfg_dmaca.p_des_addr); + } + + p_rctrl_dma->rx_fraction = 0; + + if (SCI_CH0 == hdl->rom->chan) + { + err_dmaca = R_DMACA_Int_Callback(hdl->rom->dmaca_rx_channel,(void *)sci0_dmac_rx_callback); + } + else if (SCI_CH1 == hdl->rom->chan) + { + err_dmaca = R_DMACA_Int_Callback(hdl->rom->dmaca_rx_channel,(void *)sci1_dmac_rx_callback); + } + else if (SCI_CH2 == hdl->rom->chan) + { + err_dmaca = R_DMACA_Int_Callback(hdl->rom->dmaca_rx_channel,(void *)sci2_dmac_rx_callback); + } + else if (SCI_CH3 == hdl->rom->chan) + { + err_dmaca = R_DMACA_Int_Callback(hdl->rom->dmaca_rx_channel,(void *)sci3_dmac_rx_callback); + } + else if (SCI_CH4 == hdl->rom->chan) + { + err_dmaca = R_DMACA_Int_Callback(hdl->rom->dmaca_rx_channel,(void *)sci4_dmac_rx_callback); + } + else if (SCI_CH5 == hdl->rom->chan) + { + err_dmaca = R_DMACA_Int_Callback(hdl->rom->dmaca_rx_channel,(void *)sci5_dmac_rx_callback); + } + else if (SCI_CH6 == hdl->rom->chan) + { + err_dmaca = R_DMACA_Int_Callback(hdl->rom->dmaca_rx_channel,(void *)sci6_dmac_rx_callback); + } + else if (SCI_CH7 == hdl->rom->chan) + { + err_dmaca = R_DMACA_Int_Callback(hdl->rom->dmaca_rx_channel,(void *)sci7_dmac_rx_callback); + } + else if (SCI_CH8 == hdl->rom->chan) + { + err_dmaca = R_DMACA_Int_Callback(hdl->rom->dmaca_rx_channel,(void *)sci8_dmac_rx_callback); + } + else if (SCI_CH9 == hdl->rom->chan) + { + err_dmaca = R_DMACA_Int_Callback(hdl->rom->dmaca_rx_channel,(void *)sci9_dmac_rx_callback); + } + else if (SCI_CH10 == hdl->rom->chan) + { + err_dmaca = R_DMACA_Int_Callback(hdl->rom->dmaca_rx_channel,(void *)sci10_dmac_rx_callback); + } + else if (SCI_CH11 == hdl->rom->chan) + { + err_dmaca = R_DMACA_Int_Callback(hdl->rom->dmaca_rx_channel,(void *)sci11_dmac_rx_callback); + } + else if (SCI_CH12 == hdl->rom->chan) + { + err_dmaca = R_DMACA_Int_Callback(hdl->rom->dmaca_rx_channel,(void *)sci12_dmac_rx_callback); + } + else + { + err_dmaca = DMACA_ERR_INTERNAL; + } + + if (DMACA_SUCCESS == err_dmaca) + { + err_dmaca = R_DMACA_Create(hdl->rom->dmaca_rx_channel, &rx_cfg_dmaca); + } + if (DMACA_SUCCESS == err_dmaca) + { +#if defined(BSP_MCU_RX64M) || defined(BSP_MCU_RX71M) || defined(BSP_MCU_RX65N) || defined(BSP_MCU_RX66T) || defined(BSP_MCU_RX72T) || defined(BSP_MCU_RX72M) || defined(BSP_MCU_RX72N) || defined(BSP_MCU_RX66N)|| defined(BSP_MCU_RX671)|| defined(BSP_MCU_RX660) || defined(BSP_MCU_RX26T) + err_dmaca = R_DMACA_Int_Enable(hdl->rom->dmaca_rx_channel, *hdl->rom->ipr_rxi); +#else + err_dmaca = R_DMACA_Int_Enable(hdl->rom->dmaca_rx_channel, *hdl->rom->ipr); +#endif + } + if (DMACA_SUCCESS == err_dmaca) + { + err_dmaca = R_DMACA_Control(hdl->rom->dmaca_rx_channel, DMACA_CMD_ENABLE, &stat_dmaca); + } + } + } + + if (DMACA_SUCCESS != err_dmaca) + { + err_sci = SCI_ERR_DMACA; + } + + return err_sci; +} +/********************************************************************************************************************** + End of function sci_tx_dmaca_create + *********************************************************************************************************************/ + +/********************************************************************************************************************** +* Function Name: sci0_dmac_rx_callback +* Description : DMAC interrupt routines for SCI0 channel +* Return Value : None + *********************************************************************************************************************/ +static void sci0_dmac_rx_callback(void) +{ +#if SCI_CFG_CH0_INCLUDED + sci_dmac_rx_handler(&ch0_ctrl); +#endif +} +/********************************************************************************************************************** + End of function sci0_dmac_rx_callback + *********************************************************************************************************************/ + +/********************************************************************************************************************** +* Function Name: sci1_dmac_rx_callback +* Description : DMAC interrupt routines for SCI1 channel +* Return Value : None + *********************************************************************************************************************/ +static void sci1_dmac_rx_callback(void) +{ +#if SCI_CFG_CH1_INCLUDED + sci_dmac_rx_handler(&ch1_ctrl); +#endif +} +/********************************************************************************************************************** + End of function sci1_dmac_rx_callback + *********************************************************************************************************************/ + +/********************************************************************************************************************** +* Function Name: sci2_dmac_rx_callback +* Description : DMAC interrupt routines for SCI2 channel +* Return Value : None + *********************************************************************************************************************/ +static void sci2_dmac_rx_callback(void) +{ +#if SCI_CFG_CH2_INCLUDED + sci_dmac_rx_handler(&ch2_ctrl); +#endif +} +/********************************************************************************************************************** + End of function sci2_dmac_rx_callback + *********************************************************************************************************************/ + +/********************************************************************************************************************** +* Function Name: sci3_dmac_rx_callback +* Description : DMAC interrupt routines for SCI3 channel +* Return Value : None + *********************************************************************************************************************/ +static void sci3_dmac_rx_callback(void) +{ +#if SCI_CFG_CH3_INCLUDED + sci_dmac_rx_handler(&ch3_ctrl); +#endif +} +/********************************************************************************************************************** + End of function sci3_dmac_rx_callback + *********************************************************************************************************************/ + +/********************************************************************************************************************** +* Function Name: sci4_dmac_rx_callback +* Description : DMAC interrupt routines for SCI4 channel +* Return Value : None + *********************************************************************************************************************/ +static void sci4_dmac_rx_callback(void) +{ +#if SCI_CFG_CH4_INCLUDED + sci_dmac_rx_handler(&ch4_ctrl); +#endif +} +/********************************************************************************************************************** + End of function sci_dmac_rx_callback + *********************************************************************************************************************/ + +/********************************************************************************************************************** +* Function Name: sci5_dmac_rx_callback +* Description : DMAC interrupt routines for SCI5 channel +* Return Value : None + *********************************************************************************************************************/ +static void sci5_dmac_rx_callback(void) +{ +#if SCI_CFG_CH5_INCLUDED + sci_dmac_rx_handler(&ch5_ctrl); +#endif +} +/********************************************************************************************************************** + End of function sci_dmac_rx_callback + *********************************************************************************************************************/ + +/********************************************************************************************************************** +* Function Name: sci6_dmac_rx_callback +* Description : DMAC interrupt routines for SCI6 channel +* Return Value : None + *********************************************************************************************************************/ +static void sci6_dmac_rx_callback(void) +{ +#if SCI_CFG_CH6_INCLUDED + sci_dmac_rx_handler(&ch6_ctrl); +#endif +} +/********************************************************************************************************************** + End of function sci_dmac_rx_callback + *********************************************************************************************************************/ + +/********************************************************************************************************************** +* Function Name: sci7_dmac_rx_callback +* Description : DMAC interrupt routines for SCI7 channel +* Return Value : None + *********************************************************************************************************************/ +static void sci7_dmac_rx_callback(void) +{ +#if SCI_CFG_CH7_INCLUDED + sci_dmac_rx_handler(&ch7_ctrl); +#endif +} +/********************************************************************************************************************** + End of function sci_dmac_rx_callback + *********************************************************************************************************************/ + +/********************************************************************************************************************** +* Function Name: sci8_dmac_rx_callback +* Description : DMAC interrupt routines for SCI8 channel +* Return Value : None + *********************************************************************************************************************/ +static void sci8_dmac_rx_callback(void) +{ +#if SCI_CFG_CH8_INCLUDED + sci_dmac_rx_handler(&ch8_ctrl); +#endif +} +/********************************************************************************************************************** + End of function sci8_dmac_rx_callback + *********************************************************************************************************************/ + +/********************************************************************************************************************** +* Function Name: sci9_dmac_rx_callback +* Description : DMAC interrupt routines for SCI9 channel +* Return Value : None + *********************************************************************************************************************/ +static void sci9_dmac_rx_callback(void) +{ +#if SCI_CFG_CH9_INCLUDED + sci_dmac_rx_handler(&ch9_ctrl); +#endif +} +/********************************************************************************************************************** + End of function sci9_dmac_rx_callback + *********************************************************************************************************************/ + +/********************************************************************************************************************** +* Function Name: sci10_dmac_rx_callback +* Description : DMAC interrupt routines for SCI10 channel +* Return Value : None + *********************************************************************************************************************/ +static void sci10_dmac_rx_callback(void) +{ +#if SCI_CFG_CH10_INCLUDED + sci_dmac_rx_handler(&ch10_ctrl); +#endif +} +/********************************************************************************************************************** + End of function sci10_dmac_rx_callback + *********************************************************************************************************************/ + +/********************************************************************************************************************** +* Function Name: sci11_dmac_rx_callback +* Description : DMAC interrupt routines for SCI11 channel +* Return Value : None + *********************************************************************************************************************/ +static void sci11_dmac_rx_callback(void) +{ +#if SCI_CFG_CH11_INCLUDED + sci_dmac_rx_handler(&ch11_ctrl); +#endif +} +/********************************************************************************************************************** + End of function sci11_dmac_rx_callback + *********************************************************************************************************************/ + +/********************************************************************************************************************** +* Function Name: sci12_dmac_rx_callback +* Description : DMAC interrupt routines for SCI12 channel +* Return Value : None + *********************************************************************************************************************/ +static void sci12_dmac_rx_callback(void) +{ +#if SCI_CFG_CH12_INCLUDED + sci_dmac_rx_handler(&ch12_ctrl); +#endif +} +/********************************************************************************************************************** + End of function sci12_dmac_rx_callback + *********************************************************************************************************************/ + +/********************************************************************************************************************** +* Function Name: sci_dmac_rx_handler +* Description : This function is called to close and disable interrupt for DMAC channel, + when SCI receive data completely by DMAC or remain fraction data need to be receive by CPU. + If remain fraction data need to be receive by CPU (in FIFO mode), + this function set threshold of RX FIFO to number of fraction data. +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* Return Value : None + *********************************************************************************************************************/ +static void sci_dmac_rx_handler(sci_hdl_t const hdl) +{ + volatile sci_fifo_ctrl_t *p_ctrl; + + sci_cb_args_t args; + + +#if (RX_DTC_DMACA_ENABLE & 0x02) + if (SCI_DMACA_ENABLE == hdl->rom->dtc_dmaca_rx_enable) + { + if(4 == hdl->rom->dmaca_rx_channel || 5 == hdl->rom->dmaca_rx_channel || 6 == hdl->rom->dmaca_rx_channel || 7 == hdl->rom->dmaca_rx_channel) + { + dmaca_stat_t stat_dmaca; + R_DMACA_Control(hdl->rom->dmaca_rx_channel, DMACA_CMD_DTIF_STATUS_CLR, &stat_dmaca); + } + + R_DMACA_Int_Disable(hdl->rom->dmaca_rx_channel); + R_DMACA_Close(hdl->rom->dmaca_rx_channel); + } +#endif + p_ctrl = &hdl->queue[hdl->qindex_int_rx]; + + if (0 == p_ctrl->rx_fraction) + { +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + if ((SCI_MODE_SYNC == hdl->mode) || (SCI_MODE_SSPI == hdl->mode)) + { + hdl->tx_idle = true; + } +#endif +#if (SCI_CFG_ASYNC_INCLUDED) + if (SCI_MODE_ASYNC == hdl->mode) + { + hdl->rx_idle = true; + } +#endif + p_ctrl->rx_cnt = p_ctrl->rx_fraction; + + /* If at threshold level, clear bit so can get another RXIF interrupt. + * Do not re-arm if Receive() request not outstanding (Async) + */ +#if SCI_CFG_FIFO_INCLUDED + if (true == hdl->fifo_ctrl) + { + if ((1 == hdl->rom->regs->SSRFIFO.BIT.RDF) && (0 != p_ctrl->rx_cnt)) + { + hdl->rom->regs->SSRFIFO.BIT.RDF = 0; + } + } +#endif +#if (RX_DTC_DMACA_ENABLE & 0x02) + if (SCI_DMACA_ENABLE == hdl->rom->dtc_dmaca_rx_enable) + { + + /* Do callback if available */ + if ((NULL != hdl->callback) && (FIT_NO_FUNC != hdl->callback)) + { + args.hdl = hdl; +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + if (SCI_MODE_SYNC == hdl->mode || SCI_MODE_SSPI == hdl->mode) + { + args.event = SCI_EVT_RX_SYNC_DONE; + } + else +#endif + { + args.event = SCI_EVT_RX_DONE; + } + + /* Casting to void type is valid */ + hdl->callback((void *)&args); + } + } +#endif + } + else + { +#if SCI_CFG_FIFO_INCLUDED + if (true == hdl->fifo_ctrl) + { + SCI_PRV_RX_FIFO_THRESHOLD = p_ctrl->rx_fraction; + } +#endif + } +} +/********************************************************************************************************************** + End of function sci_dmac_rx_handler + *********************************************************************************************************************/ + +/********************************************************************************************************************** +* Function Name: sci0_dmac_tx_callback +* Description : DMAC interrupt routines for SCI0 channel +* Return Value : None + *********************************************************************************************************************/ +static void sci0_dmac_tx_callback(void) +{ +#if SCI_CFG_CH0_INCLUDED + sci_dmac_tx_handler(&ch0_ctrl); +#endif +} +/********************************************************************************************************************** + End of function sci0_dmac_tx_callback + *********************************************************************************************************************/ + +/********************************************************************************************************************** +* Function Name: sci1_dmac_tx_callback +* Description : DMAC interrupt routines for SCI1 channel +* Return Value : None + *********************************************************************************************************************/ +static void sci1_dmac_tx_callback(void) +{ +#if SCI_CFG_CH1_INCLUDED + sci_dmac_tx_handler(&ch1_ctrl); +#endif +} +/********************************************************************************************************************** + End of function sci1_dmac_tx_callback + *********************************************************************************************************************/ + +/********************************************************************************************************************** +* Function Name: sci2_dmac_tx_callback +* Description : DMAC interrupt routines for SCI2 channel +* Return Value : None + *********************************************************************************************************************/ +static void sci2_dmac_tx_callback(void) +{ +#if SCI_CFG_CH2_INCLUDED + sci_dmac_tx_handler(&ch2_ctrl); +#endif +} +/********************************************************************************************************************** + End of function sci2_dmac_tx_callback + *********************************************************************************************************************/ + +/********************************************************************************************************************** +* Function Name: sci3_dmac_tx_callback +* Description : DMAC interrupt routines for SCI3 channel +* Return Value : None + *********************************************************************************************************************/ +static void sci3_dmac_tx_callback(void) +{ +#if SCI_CFG_CH3_INCLUDED + sci_dmac_tx_handler(&ch3_ctrl); +#endif +} +/********************************************************************************************************************** + End of function sci3_dmac_tx_callback + *********************************************************************************************************************/ + +/********************************************************************************************************************** +* Function Name: sci4_dmac_tx_callback +* Description : DMAC interrupt routines for SCI4 channel +* Return Value : None + *********************************************************************************************************************/ +static void sci4_dmac_tx_callback(void) +{ +#if SCI_CFG_CH4_INCLUDED + sci_dmac_tx_handler(&ch4_ctrl); +#endif +} +/********************************************************************************************************************** + End of function sci_dmac_tx_callback + *********************************************************************************************************************/ + +/********************************************************************************************************************** +* Function Name: sci5_dmac_tx_callback +* Description : DMAC interrupt routines for SCI5 channel +* Return Value : None + *********************************************************************************************************************/ +static void sci5_dmac_tx_callback(void) +{ +#if SCI_CFG_CH5_INCLUDED + sci_dmac_tx_handler(&ch5_ctrl); +#endif +} +/********************************************************************************************************************** + End of function sci_dmac_tx_callback + *********************************************************************************************************************/ + +/********************************************************************************************************************** +* Function Name: sci6_dmac_tx_callback +* Description : DMAC interrupt routines for SCI6 channel +* Return Value : None + *********************************************************************************************************************/ +static void sci6_dmac_tx_callback(void) +{ +#if SCI_CFG_CH6_INCLUDED + sci_dmac_tx_handler(&ch6_ctrl); +#endif +} +/********************************************************************************************************************** + End of function sci_dmac_tx_callback + *********************************************************************************************************************/ + +/********************************************************************************************************************** +* Function Name: sci7_dmac_tx_callback +* Description : DMAC interrupt routines for SCI7 channel +* Return Value : None + *********************************************************************************************************************/ +static void sci7_dmac_tx_callback(void) +{ +#if SCI_CFG_CH7_INCLUDED + sci_dmac_tx_handler(&ch7_ctrl); +#endif +} +/********************************************************************************************************************** + End of function sci_dmac_tx_callback + *********************************************************************************************************************/ + +/********************************************************************************************************************** +* Function Name: sci8_dmac_tx_callback +* Description : DMAC interrupt routines for SCI8 channel +* Return Value : None + *********************************************************************************************************************/ +static void sci8_dmac_tx_callback(void) +{ +#if SCI_CFG_CH8_INCLUDED + sci_dmac_tx_handler(&ch8_ctrl); +#endif +} +/********************************************************************************************************************** + End of function sci8_dmac_tx_callback + *********************************************************************************************************************/ + +/********************************************************************************************************************** +* Function Name: sci9_dmac_tx_callback +* Description : DMAC interrupt routines for SCI9 channel +* Return Value : None + *********************************************************************************************************************/ +static void sci9_dmac_tx_callback(void) +{ +#if SCI_CFG_CH9_INCLUDED + sci_dmac_tx_handler(&ch9_ctrl); +#endif +} +/********************************************************************************************************************** + End of function sci9_dmac_tx_callback + *********************************************************************************************************************/ + +/********************************************************************************************************************** +* Function Name: sci10_dmac_tx_callback +* Description : DMAC interrupt routines for SCI10 channel +* Return Value : None + *********************************************************************************************************************/ +static void sci10_dmac_tx_callback(void) +{ +#if SCI_CFG_CH10_INCLUDED + sci_dmac_tx_handler(&ch10_ctrl); +#endif +} +/********************************************************************************************************************** + End of function sci10_dmac_tx_callback + *********************************************************************************************************************/ + +/********************************************************************************************************************** +* Function Name: sci11_dmac_tx_callback +* Description : DMAC interrupt routines for SCI11 channel +* Return Value : None + *********************************************************************************************************************/ +static void sci11_dmac_tx_callback(void) +{ +#if SCI_CFG_CH11_INCLUDED + sci_dmac_tx_handler(&ch11_ctrl); +#endif +} +/********************************************************************************************************************** + End of function sci11_dmac_tx_callback + *********************************************************************************************************************/ + +/********************************************************************************************************************** +* Function Name: sci12_dmac_tx_callback +* Description : DMAC interrupt routines for SCI12 channel +* Return Value : None + *********************************************************************************************************************/ +static void sci12_dmac_tx_callback(void) +{ +#if SCI_CFG_CH12_INCLUDED + sci_dmac_tx_handler(&ch12_ctrl); +#endif +} +/********************************************************************************************************************** + End of function sci12_dmac_tx_callback + *********************************************************************************************************************/ + +/********************************************************************************************************************** +* Function Name: sci_dmac_tx_handler +* Description : This function is called to close and disable interrupt for DMAC channel, + when SCI transmit data completely by DMAC. +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* Return Value : None + *********************************************************************************************************************/ +static void sci_dmac_tx_handler(sci_hdl_t const hdl) +{ +#if (RX_DTC_DMACA_ENABLE & 0x02) + if (SCI_DMACA_ENABLE == hdl->rom->dtc_dmaca_rx_enable) + { + if(4 == hdl->rom->dmaca_tx_channel || 5 == hdl->rom->dmaca_tx_channel || 6 == hdl->rom->dmaca_tx_channel || 7 == hdl->rom->dmaca_tx_channel) + { + dmaca_stat_t stat_dmaca; + R_DMACA_Control(hdl->rom->dmaca_tx_channel, DMACA_CMD_DTIF_STATUS_CLR, &stat_dmaca); + } + } +#endif +} +/********************************************************************************************************************** + End of function sci_dmac_tx_handler +*/ +#endif /* ((TX_DTC_DMACA_ENABLE & 0x02) || (RX_DTC_DMACA_ENABLE & 0x02)) */ diff --git a/drivers/rx/rdp/src/r_sci_rx/src/r_sci_rx_dmaca.h b/drivers/rx/rdp/src/r_sci_rx/src/r_sci_rx_dmaca.h new file mode 100644 index 00000000..12b4a96d --- /dev/null +++ b/drivers/rx/rdp/src/r_sci_rx/src/r_sci_rx_dmaca.h @@ -0,0 +1,88 @@ +/********************************************************************************************************************** + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No + * other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all + * applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM + * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES + * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO + * THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of + * this software. By using this software, you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * + * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. + *********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_sci_rx_dmaca.h +* Description : +************************************************************************************************************************ +* History : DD.MM.YYYY Version Description +* 25.08.2020 1.00 Initial Release +* 31.03.2023 4.80 Fixed to comply with GSCE Coding Standards Rev.6.5.0. +* 29.05.2023 4.90 Fixed to comply with GSCE Coding Standards Rev.6.5.0. +***********************************************************************************************************************/ + +/********************************************************************************************************************** + Includes , "Project Includes" + *********************************************************************************************************************/ +#include "platform.h" +#include "r_sci_rx_if.h" + +/********************************************************************************************************************** + Macro definitions + *********************************************************************************************************************/ + +/********************************************************************************************************************** + Global Typedef definitions + *********************************************************************************************************************/ + +/********************************************************************************************************************** + External global variables + *********************************************************************************************************************/ + +/********************************************************************************************************************** + Exported global functions + *********************************************************************************************************************/ +/****************************************************************************** + * Function Name: sci_txfifo_dmaca_create + * Description : . + * Arguments : hdl + * : p_src + * : length + * Return Value : . + *****************************************************************************/ +sci_err_t sci_txfifo_dmaca_create (sci_hdl_t const hdl, uint8_t *p_src, uint16_t const length); + +/****************************************************************************** + * Function Name: sci_rxfifo_dmaca_create + * Description : . + * Arguments : hdl + * : p_dst + * : length + * Return Value : . + *****************************************************************************/ +sci_err_t sci_rxfifo_dmaca_create (sci_hdl_t const hdl, uint8_t *p_dst, uint16_t const length); + +/****************************************************************************** + * Function Name: sci_tx_dmaca_create + * Description : . + * Arguments : hdl + * : p_src + * : length + * Return Value : . + *****************************************************************************/ +sci_err_t sci_tx_dmaca_create (sci_hdl_t const hdl, uint8_t *p_src, uint16_t const length); + +/****************************************************************************** + * Function Name: sci_rx_dmaca_create + * Description : . + * Arguments : hdl + * : p_dst + * : length + * Return Value : . + *****************************************************************************/ +sci_err_t sci_rx_dmaca_create (sci_hdl_t const hdl, uint8_t *p_dst, uint16_t const length); diff --git a/drivers/rx/rdp/src/r_sci_rx/src/r_sci_rx_dtc.c b/drivers/rx/rdp/src/r_sci_rx/src/r_sci_rx_dtc.c new file mode 100644 index 00000000..e558dbe5 --- /dev/null +++ b/drivers/rx/rdp/src/r_sci_rx/src/r_sci_rx_dtc.c @@ -0,0 +1,561 @@ +/********************************************************************************************************************** + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No + * other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all + * applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM + * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES + * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO + * THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of + * this software. By using this software, you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * + * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. + *********************************************************************************************************************/ +/********************************************************************************************************************** +* File Name : r_sci_rx_dtc.c +* Description : +*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* 25.08.2020 1.00 Initial Release +* 31.03.2022 4.40 Fixed the issue with DTC mode which incorrectly uses the same transfer information +* for all channels. +* 31.03.2023 4.80 Fixed to comply with GSCE Coding Standards Rev.6.5.0. +* 31.01.2024 5.10 Added WAIT_LOOP comments. +***********************************************************************************************************************/ + +/********************************************************************************************************************** + Includes , "Project Includes" + *********************************************************************************************************************/ +#include "platform.h" +#include "r_sci_rx_private.h" +#include "r_sci_rx_if.h" +#if ((TX_DTC_DMACA_ENABLE & 0x01) || (RX_DTC_DMACA_ENABLE & 0x01)) +#include +#include "r_dtc_rx_if.h" +#include "r_sci_rx_dtc.h" +#include "r_sci_rx_platform.h" + +/********************************************************************************************************************** + Macro definitions + *********************************************************************************************************************/ +#define SCI_PRV_RX_FIFO_THRESHOLD (hdl->rom->regs->FCR.BIT.RTRG) +#define SCI_PRV_TX_FIFO_THRESHOLD (hdl->rom->regs->FCR.BIT.TTRG) + +/********************************************************************************************************************** + Typedef definitions + *********************************************************************************************************************/ + +/********************************************************************************************************************** + Exported global variables + *********************************************************************************************************************/ +dtc_cmd_arg_t tx_args_dtc; +dtc_transfer_data_cfg_t tx_cfg_dtc; +dtc_cmd_arg_t rx_args_dtc; +dtc_transfer_data_cfg_t rx_cfg_dtc; +sci_dtc_info_transfer_t *gp_dtc_info_head = NULL; + +/********************************************************************************************************************** + Private (static) variables and functions + *********************************************************************************************************************/ +sci_err_t sci_dtc_info_transfer_create(sci_hdl_t const hdl, sci_dtc_info_transfer_t **p_info_transfer); +static uint8_t tx_dummy_buf = SCI_CFG_DUMMY_TX_BYTE; +static uint8_t rx_dummy_buf = 0; + +#if (SCI_CFG_FIFO_INCLUDED) +/********************************************************************************************************************** +* Function Name: sci_txfifo_dtc_create +* Description : This function create DTC to transmit data from p_src to SCI TX FIFO (by DTC without CPU) +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* p_src - +* The address of source data need to be sent +* lenght - +* The number of data need to be sent +* Return Value : SCI_SUCCESS - +* Create DTC successfully +* SCI_ERR_DTC - +* Create DTC NOT successfully + *********************************************************************************************************************/ +sci_err_t sci_txfifo_dtc_create(sci_hdl_t const hdl, uint8_t *p_src, uint16_t const length) +{ + sci_fifo_ctrl_t *p_tctrl; + sci_err_t err_sci = SCI_SUCCESS; + dtc_err_t err_dtc = DTC_SUCCESS; + sci_dtc_info_transfer_t *p_info_transfer = NULL; + + p_tctrl = &hdl->queue[hdl->qindex_app_tx]; + + tx_args_dtc.act_src = hdl->rom->dtc_tx_act_src; + tx_args_dtc.chain_transfer_nr = 0; + tx_args_dtc.p_data_cfg = &tx_cfg_dtc; + + err_sci = sci_dtc_info_transfer_create(hdl, &p_info_transfer); + if(SCI_SUCCESS != err_sci) + { + return err_sci; + } + tx_args_dtc.p_transfer_data = &p_info_transfer->tx_info_dtc; + + tx_cfg_dtc.transfer_mode = DTC_TRANSFER_MODE_BLOCK; + tx_cfg_dtc.data_size = DTC_DATA_SIZE_BYTE; + tx_cfg_dtc.chain_transfer_enable = DTC_CHAIN_TRANSFER_DISABLE; + tx_cfg_dtc.response_interrupt = DTC_INTERRUPT_AFTER_ALL_COMPLETE; + tx_cfg_dtc.dest_addr_mode = DTC_DES_ADDR_FIXED; + tx_cfg_dtc.dest_addr = (uint32_t)&hdl->rom->regs->FTDR.BYTE.L; + + if (NULL == p_src) + { + tx_cfg_dtc.repeat_block_side = DTC_REPEAT_BLOCK_SOURCE; + tx_cfg_dtc.src_addr_mode = DTC_SRC_ADDR_FIXED; + tx_cfg_dtc.source_addr = (uint32_t)&tx_dummy_buf; + } + else + { + tx_cfg_dtc.repeat_block_side = DTC_REPEAT_BLOCK_DESTINATION; + tx_cfg_dtc.src_addr_mode = DTC_SRC_ADDR_INCR; + tx_cfg_dtc.source_addr = (uint32_t)p_src; + } + + tx_cfg_dtc.transfer_count = (uint32_t)(length / hdl->rom->dtc_dmaca_tx_block_size); + tx_cfg_dtc.block_size = hdl->rom->dtc_dmaca_tx_block_size; + + if (length >= tx_cfg_dtc.block_size) + { + if (NULL == p_src) + { + p_tctrl->p_tx_fraction_buf = NULL; + } + else + { + p_tctrl->p_tx_fraction_buf = (uint8_t*)(tx_cfg_dtc.source_addr + (tx_cfg_dtc.transfer_count * tx_cfg_dtc.block_size)); + } + + p_tctrl->tx_fraction = (length - (tx_cfg_dtc.transfer_count * tx_cfg_dtc.block_size)); + + err_dtc = R_DTC_Create(tx_args_dtc.act_src, &p_info_transfer->tx_info_dtc, &tx_cfg_dtc, 0); + if (DTC_SUCCESS == err_dtc) + { + err_dtc = R_DTC_Control(DTC_CMD_ACT_SRC_ENABLE, NULL, &tx_args_dtc); + } + if (DTC_SUCCESS == err_dtc) + { + R_DTC_Control(DTC_CMD_DTC_START, NULL, NULL); + } + } + else + { + p_tctrl->p_tx_fraction_buf = p_src; + p_tctrl->tx_fraction = length; + + err_dtc = R_DTC_Control(DTC_CMD_ACT_SRC_DISABLE, NULL, &tx_args_dtc); + } + + if (DTC_SUCCESS != err_dtc) + { + err_sci = SCI_ERR_DTC; + } + + return err_sci; +} +/********************************************************************************************************************** + End of function sci_txfifo_dtc_create + *********************************************************************************************************************/ +#endif /* End of (SCI_CFG_FIFO_INCLUDED)*/ + +#if (SCI_CFG_FIFO_INCLUDED) +/********************************************************************************************************************** +* Function Name: sci_rxfifo_dtc_create +* Description : This function create DTC to receive data from SCI RX FIFO (by DTC without CPU) +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* p_dst - +* The address of destination need to be saved +* lenght - +* The number of data need to be saved +* Return Value : SCI_SUCCESS - +* Create DTC successfully +* SCI_ERR_DTC - +* Create DTC NOT successfully + *********************************************************************************************************************/ +sci_err_t sci_rxfifo_dtc_create(sci_hdl_t const hdl, uint8_t *p_dst, uint16_t const length) +{ + sci_fifo_ctrl_t *p_rctrl; + sci_err_t err_sci = SCI_SUCCESS; + dtc_err_t err_dtc = DTC_SUCCESS; + sci_dtc_info_transfer_t *p_info_transfer = NULL; + + p_rctrl = &hdl->queue[hdl->qindex_app_rx]; + + rx_args_dtc.act_src = hdl->rom->dtc_rx_act_src; + rx_args_dtc.chain_transfer_nr = 0; + rx_args_dtc.p_data_cfg = &rx_cfg_dtc; + + err_sci = sci_dtc_info_transfer_create(hdl, &p_info_transfer); + if(SCI_SUCCESS != err_sci) + { + return err_sci; + } + rx_args_dtc.p_transfer_data = &p_info_transfer->rx_info_dtc; + + rx_cfg_dtc.transfer_mode = DTC_TRANSFER_MODE_BLOCK; + rx_cfg_dtc.data_size = DTC_DATA_SIZE_BYTE; + rx_cfg_dtc.src_addr_mode = DTC_SRC_ADDR_FIXED; + rx_cfg_dtc.chain_transfer_enable = DTC_CHAIN_TRANSFER_DISABLE; + rx_cfg_dtc.response_interrupt = DTC_INTERRUPT_AFTER_ALL_COMPLETE; + rx_cfg_dtc.source_addr = (uint32_t)&hdl->rom->regs->FRDR.BYTE.L; + + if (NULL == p_dst) + { + rx_cfg_dtc.repeat_block_side = DTC_REPEAT_BLOCK_DESTINATION; + rx_cfg_dtc.dest_addr_mode = DTC_DES_ADDR_FIXED; + rx_cfg_dtc.dest_addr = (uint32_t)&rx_dummy_buf; + } + else + { + rx_cfg_dtc.repeat_block_side = DTC_REPEAT_BLOCK_SOURCE; + rx_cfg_dtc.dest_addr_mode = DTC_DES_ADDR_INCR; + rx_cfg_dtc.dest_addr = (uint32_t)p_dst; + } + + rx_cfg_dtc.transfer_count = (uint32_t)(length / hdl->rom->dtc_dmaca_rx_block_size); + rx_cfg_dtc.block_size = hdl->rom->dtc_dmaca_rx_block_size; + + if (length >= hdl->rx_dflt_thresh) + { + if (NULL == p_dst) + { + p_rctrl->p_rx_fraction_buf = NULL; + } + else + { + p_rctrl->p_rx_fraction_buf = (uint8_t*)(rx_cfg_dtc.dest_addr + (rx_cfg_dtc.transfer_count * rx_cfg_dtc.block_size)); + } + + p_rctrl->rx_fraction = (length - (rx_cfg_dtc.transfer_count * rx_cfg_dtc.block_size)); + SCI_PRV_RX_FIFO_THRESHOLD = hdl->rx_dflt_thresh; + + err_dtc = R_DTC_Create(rx_args_dtc.act_src, &p_info_transfer->rx_info_dtc, &rx_cfg_dtc, 0); + if (DTC_SUCCESS == err_dtc) + { + err_dtc = R_DTC_Control(DTC_CMD_ACT_SRC_ENABLE, NULL, &rx_args_dtc); + } + if (DTC_SUCCESS == err_dtc) + { + R_DTC_Control(DTC_CMD_DTC_START, NULL, NULL); + } + } + else + { + p_rctrl->p_rx_fraction_buf = p_dst; + p_rctrl->rx_fraction = length; + + SCI_PRV_RX_FIFO_THRESHOLD = p_rctrl->rx_fraction; + err_dtc = R_DTC_Control(DTC_CMD_ACT_SRC_DISABLE, NULL, &rx_args_dtc); + } + + if (DTC_SUCCESS != err_dtc) + { + err_sci = SCI_ERR_DTC; + } + + return err_sci; +} +/********************************************************************************************************************** + End of function sci_rxfifo_dtc_create + *********************************************************************************************************************/ +#endif /* End of (SCI_CFG_FIFO_INCLUDED)*/ + +/********************************************************************************************************************** +* Function Name: sci_rx_dtc_create +* Description : This function create DTC to receive data from RDR (by DTC without CPU) +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* p_dst - +* The address of destination need to be saved +* lenght - +* The number of data need to be saved +* Return Value : SCI_SUCCESS - +* Create DTC successfully +* SCI_ERR_DTC - +* Create DTC NOT successfully + *********************************************************************************************************************/ +sci_err_t sci_rx_dtc_create(sci_hdl_t const hdl, uint8_t *p_dst, uint16_t const length) +{ + sci_fifo_ctrl_t *p_rctrl; + sci_err_t err_sci = SCI_SUCCESS; + dtc_err_t err_dtc = DTC_SUCCESS; + sci_dtc_info_transfer_t *p_info_transfer = NULL; + + p_rctrl = &hdl->queue[hdl->qindex_app_rx]; + + rx_args_dtc.act_src = hdl->rom->dtc_rx_act_src; + rx_args_dtc.chain_transfer_nr = 0; + rx_args_dtc.p_data_cfg = &rx_cfg_dtc; + + err_sci = sci_dtc_info_transfer_create(hdl, &p_info_transfer); + if(SCI_SUCCESS != err_sci) + { + return err_sci; + } + rx_args_dtc.p_transfer_data = &p_info_transfer->rx_info_dtc; + + + rx_cfg_dtc.transfer_mode = DTC_TRANSFER_MODE_NORMAL; + rx_cfg_dtc.data_size = DTC_DATA_SIZE_BYTE; + rx_cfg_dtc.src_addr_mode = DTC_SRC_ADDR_FIXED; + rx_cfg_dtc.chain_transfer_enable = DTC_CHAIN_TRANSFER_DISABLE; + rx_cfg_dtc.response_interrupt = DTC_INTERRUPT_AFTER_ALL_COMPLETE; + rx_cfg_dtc.source_addr = (uint32_t)&hdl->rom->regs->RDR; + + if (NULL == p_dst) + { + rx_cfg_dtc.dest_addr_mode = DTC_DES_ADDR_FIXED; + rx_cfg_dtc.dest_addr = (uint32_t)&rx_dummy_buf; + } + else + { + rx_cfg_dtc.dest_addr_mode = DTC_DES_ADDR_INCR; + rx_cfg_dtc.dest_addr = (uint32_t)p_dst; + } + + rx_cfg_dtc.transfer_count = (uint32_t)(length); + + if (0 < length) + { + if (NULL == p_dst) + { + p_rctrl->p_rx_fraction_buf = NULL; + } + else + { + p_rctrl->p_rx_fraction_buf = (uint8_t*)rx_cfg_dtc.dest_addr; + } + + p_rctrl->rx_fraction = 0; + + err_dtc = R_DTC_Create(rx_args_dtc.act_src, &p_info_transfer->rx_info_dtc, &rx_cfg_dtc, 0); + if (DTC_SUCCESS == err_dtc) + { + err_dtc = R_DTC_Control(DTC_CMD_ACT_SRC_ENABLE, NULL, &rx_args_dtc); + } + if (DTC_SUCCESS == err_dtc) + { + R_DTC_Control(DTC_CMD_DTC_START, NULL, NULL); + } + } + else + { + err_dtc = R_DTC_Control(DTC_CMD_ACT_SRC_DISABLE, NULL, &rx_args_dtc); + } + + if (DTC_SUCCESS != err_dtc) + { + err_sci = SCI_ERR_DTC; + } + + return err_sci; +} +/********************************************************************************************************************** + End of function sci_rx_dtc_create + *********************************************************************************************************************/ + +/********************************************************************************************************************** +* Function Name: sci_tx_dtc_create +* Description : This function create DTC to transmit data from p_src to TDR (by DTC without CPU) +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* p_src - +* The address of source data need to be sent +* lenght - +* The number of data need to be sent +* Return Value : SCI_SUCCESS - +* Create DTC successfully +* SCI_ERR_DTC - +* Create DTC NOT successfully + *********************************************************************************************************************/ +sci_err_t sci_tx_dtc_create(sci_hdl_t const hdl, uint8_t *p_src, uint16_t const length) +{ + sci_fifo_ctrl_t *p_tctrl; + sci_err_t err_sci = SCI_SUCCESS; + dtc_err_t err_dtc = DTC_SUCCESS; + sci_dtc_info_transfer_t *p_info_transfer = NULL; + + p_tctrl = &hdl->queue[hdl->qindex_app_tx]; + + tx_args_dtc.act_src = hdl->rom->dtc_tx_act_src; + tx_args_dtc.chain_transfer_nr = 0; + tx_args_dtc.p_data_cfg = &tx_cfg_dtc; + + err_sci = sci_dtc_info_transfer_create(hdl, &p_info_transfer); + if(SCI_SUCCESS != err_sci) + { + return err_sci; + } + tx_args_dtc.p_transfer_data = &p_info_transfer->tx_info_dtc; + + tx_cfg_dtc.transfer_mode = DTC_TRANSFER_MODE_NORMAL; + tx_cfg_dtc.data_size = DTC_DATA_SIZE_BYTE; + tx_cfg_dtc.chain_transfer_enable = DTC_CHAIN_TRANSFER_DISABLE; + tx_cfg_dtc.response_interrupt = DTC_INTERRUPT_AFTER_ALL_COMPLETE; + tx_cfg_dtc.dest_addr_mode = DTC_DES_ADDR_FIXED; + tx_cfg_dtc.dest_addr = (uint32_t)&hdl->rom->regs->TDR; + + if (NULL == p_src) + { + tx_cfg_dtc.src_addr_mode = DTC_SRC_ADDR_FIXED; + tx_cfg_dtc.source_addr = (uint32_t)&tx_dummy_buf; + } + else + { + tx_cfg_dtc.src_addr_mode = DTC_SRC_ADDR_INCR; + tx_cfg_dtc.source_addr = (uint32_t)p_src; + } + + tx_cfg_dtc.transfer_count = (uint32_t)(length); + + if (length > 0) + { + if (NULL == p_src) + { + p_tctrl->p_tx_fraction_buf = NULL; + } + else + { + p_tctrl->p_tx_fraction_buf = (uint8_t*)tx_cfg_dtc.source_addr; + } + + p_tctrl->tx_fraction = 0; + + err_dtc = R_DTC_Create(tx_args_dtc.act_src, &p_info_transfer->tx_info_dtc, &tx_cfg_dtc, 0); + if (DTC_SUCCESS == err_dtc) + { + err_dtc = R_DTC_Control(DTC_CMD_ACT_SRC_ENABLE, NULL, &tx_args_dtc); + } + if (DTC_SUCCESS == err_dtc) + { + R_DTC_Control(DTC_CMD_DTC_START, NULL, NULL); + } + } + else + { + err_dtc = R_DTC_Control(DTC_CMD_ACT_SRC_DISABLE, NULL, &tx_args_dtc); + } + + if (DTC_SUCCESS != err_dtc) + { + err_sci = SCI_ERR_DTC; + } + + return err_sci; +} +/********************************************************************************************************************** + End of function sci_tx_dtc_create + *********************************************************************************************************************/ + +/********************************************************************************************************************** +* Function Name: sci_dtc_info_transfer_create +* Description : This function creates a allocated memory for information transfer address for DTC transfer +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* p_info_transfer - +* pointer to information transfer address of DTC +* Return Value : SCI_SUCCESS - +* Create allocated memory for information transfer address successfully +* SCI_ERR_DTC - +* Create allocated memory for information transfer address NOT successfully + *********************************************************************************************************************/ +sci_err_t sci_dtc_info_transfer_create(sci_hdl_t const hdl, sci_dtc_info_transfer_t **p_info_transfer) +{ + sci_err_t err_sci = SCI_SUCCESS; + sci_dtc_info_transfer_t **p_current_info = &gp_dtc_info_head; + sci_dtc_info_transfer_t *p_new_info = NULL; + uint8_t chan = hdl->rom->chan; + + /* Check allocated memory for start pointer */ + if(NULL == *p_current_info) + { + p_new_info = (sci_dtc_info_transfer_t *) malloc(sizeof(sci_dtc_info_transfer_t)); + if(NULL == p_new_info) + { + return SCI_ERR_DTC; + } + p_new_info->chan = chan; + p_new_info->next = NULL; + *p_current_info = p_new_info; + *p_info_transfer = *p_current_info; + } + else /* Allocated memory */ + { + /* Check allocated memory for current channel */ + /* WAIT_LOOP */ + while (NULL != *p_current_info) + { + if(chan == (*p_current_info)->chan) + { + *p_info_transfer = *p_current_info; + return err_sci; + } + p_current_info = &((*p_current_info)->next); + } + + /* Create new allocated memory for a channel */ + p_new_info = (sci_dtc_info_transfer_t *) malloc(sizeof(sci_dtc_info_transfer_t)); + if(NULL == p_new_info) + { + return SCI_ERR_DTC; + } + p_new_info->chan = chan; + p_new_info->next = NULL; + *p_current_info = p_new_info; + *p_info_transfer = *p_current_info; + } + return err_sci; +} + +/********************************************************************************************************************** + End of function sci_dtc_info_transfer_create + *********************************************************************************************************************/ + +/********************************************************************************************************************** +* Function Name: sci_dtc_info_transfer_delete +* Description : This function deletes the allocated memory of information transfer address for the current channel +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* Return Value : None- + *********************************************************************************************************************/ +void sci_dtc_info_transfer_delete(sci_hdl_t const hdl) +{ + sci_dtc_info_transfer_t **p_current_info = &gp_dtc_info_head; + sci_dtc_info_transfer_t *p_next_info = NULL; + uint8_t chan = hdl->rom->chan; + + /* Check allocated memory for current channel */ + /* WAIT_LOOP */ + while (NULL != *p_current_info) + { + if(chan == (*p_current_info)->chan) + { + /* Store the next pointer of current list */ + p_next_info = (*p_current_info)->next; + + /*Destroy allocated memory for the current channel */ + free(*p_current_info); + *p_current_info = NULL; + + /* Re-assign the position current list for the next list */ + *p_current_info = p_next_info; + break; + } + p_current_info = &((*p_current_info)->next); + } +} +/********************************************************************************************************************** + End of function sci_dtc_info_transfer_delete + *********************************************************************************************************************/ + +#endif /* ((TX_DTC_DMACA_ENABLE & 0x01) || (RX_DTC_DMACA_ENABLE & 0x01)) */ diff --git a/drivers/rx/rdp/src/r_sci_rx/src/r_sci_rx_dtc.h b/drivers/rx/rdp/src/r_sci_rx/src/r_sci_rx_dtc.h new file mode 100644 index 00000000..c99bbb13 --- /dev/null +++ b/drivers/rx/rdp/src/r_sci_rx/src/r_sci_rx_dtc.h @@ -0,0 +1,109 @@ +/********************************************************************************************************************** + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No + * other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all + * applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM + * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES + * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO + * THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of + * this software. By using this software, you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * + * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. + *********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_sci_rx_dtc.h +* Description : +************************************************************************************************************************ +* History : DD.MM.YYYY Version Description +* 25.08.2020 1.00 Initial Release +* 31.03.2022 4.40 Fixed the issue with DTC mode which incorrectly uses the same transfer information +* for all channels. +* 31.03.2023 4.80 Fixed to comply with GSCE Coding Standards Rev.6.5.0. +* 29.05.2023 4.90 Fixed to comply with GSCE Coding Standards Rev.6.5.0. +***********************************************************************************************************************/ +#ifndef SCI_RX_DTC_H +#define SCI_RX_DTC_H + +/********************************************************************************************************************** + Includes , "Project Includes" + *********************************************************************************************************************/ +#include "platform.h" +#include "r_sci_rx_if.h" + +/********************************************************************************************************************** + Macro definitions + *********************************************************************************************************************/ + +/********************************************************************************************************************** + Global Typedef definitions + *********************************************************************************************************************/ +typedef struct st_sci_dtc_info_transfer +{ + uint8_t chan; /* Channel SCI is used */ + dtc_transfer_data_t tx_info_dtc; /* Transfer data address for TX */ + dtc_transfer_data_t rx_info_dtc; /* Transfer data address for RX */ + struct st_sci_dtc_info_transfer * next; /* Pointer used to link one node to the next node */ +} sci_dtc_info_transfer_t; + +/********************************************************************************************************************** + External global variables + *********************************************************************************************************************/ + +/********************************************************************************************************************** + Exported global functions + *********************************************************************************************************************/ +/****************************************************************************** + * Function Name: sci_txfifo_dtc_create + * Description : . + * Arguments : hdl + * : p_src + * : length + * Return Value : . + *****************************************************************************/ +sci_err_t sci_txfifo_dtc_create (sci_hdl_t const hdl, uint8_t *p_src, uint16_t const length); + +/****************************************************************************** + * Function Name: sci_rxfifo_dtc_create + * Description : . + * Arguments : hdl + * : p_dst + * : length + * Return Value : . + *****************************************************************************/ +sci_err_t sci_rxfifo_dtc_create (sci_hdl_t const hdl, uint8_t *p_dst, uint16_t const length); + +/****************************************************************************** + * Function Name: sci_tx_dtc_create + * Description : . + * Arguments : hdl + * : p_src + * : length + * Return Value : . + *****************************************************************************/ +sci_err_t sci_tx_dtc_create (sci_hdl_t const hdl, uint8_t *p_src, uint16_t const length); + +/****************************************************************************** + * Function Name: sci_rx_dtc_create + * Description : . + * Arguments : hdl + * : p_dst + * : length + * Return Value : . + *****************************************************************************/ +sci_err_t sci_rx_dtc_create (sci_hdl_t const hdl, uint8_t *p_dst, uint16_t const length); + +/****************************************************************************** + * Function Name: sci_dtc_info_transfer_delete + * Description : . + * Argument : hdl + * Return Value : . + *****************************************************************************/ +void sci_dtc_info_transfer_delete (sci_hdl_t const hdl); + +#endif /* SCI_RX_DTC_H */ diff --git a/drivers/rx/rdp/src/r_sci_rx/src/r_sci_rx_platform.h b/drivers/rx/rdp/src/r_sci_rx/src/r_sci_rx_platform.h new file mode 100644 index 00000000..08430e07 --- /dev/null +++ b/drivers/rx/rdp/src/r_sci_rx/src/r_sci_rx_platform.h @@ -0,0 +1,105 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2016 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_sci_rx_platform.h +* Description : Functions for using SCI on the RX devices. +************************************************************************************************************************ +* History : DD.MM.YYYY Version Description +* 01.10.2016 1.80 Initial Release. (The remake of the r01an1815ju0170 to the base.) +* 19.12.2016 1.90 Added RX24U support +* 28.09.2018 2.10 Added RX66T support +* 01.02.2019 2.20 Added RX72T, RX65N-64pin support +* 28.06.2019 3.10 Added RX23W support +* 15.08.2019 3.20 Added RX72M support +* 25.11.2019 3.30 Added support RX13T. +* Removed support for Generation 1 devices. +* 30.12.2019 3.40 Added support RX66N, RX72N. +* 31.03.2020 3.50 Added support RX23E-A. +* 31.03.2021 3.80 Added support for RX671. +* 15.04.2021 3.90 Added support for RX140. +* 31.03.2022 4.40 Added support for RX660. +* 31.03.2023 4.80 Added support for RX26T. +* Fixed to comply with GSCE Coding Standards Rev.6.5.0. +* 29.05.2023 4.90 Added support for RX23E-B. +***********************************************************************************************************************/ + +#ifndef SCI_RX_PLATFORM_H +#define SCI_RX_PLATFORM_H + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sci_rx_if.h" + +#if defined(BSP_MCU_RX110) +#include "./targets/rx110/r_sci_rx110_private.h" /* RX110 */ +#elif defined(BSP_MCU_RX111) +#include "./targets/rx111/r_sci_rx111_private.h" /* RX111 */ +#elif defined(BSP_MCU_RX113) +#include "./targets/rx113/r_sci_rx113_private.h" /* RX113 */ +#elif defined(BSP_MCU_RX130) +#include "./targets/rx130/r_sci_rx130_private.h" /* RX130 */ +#elif defined(BSP_MCU_RX13T) +#include "./targets/rx13t/r_sci_rx13t_private.h" /* RX13T */ +#elif defined(BSP_MCU_RX140) +#include "./targets/rx140/r_sci_rx140_private.h" /* RX140 */ +#elif defined(BSP_MCU_RX230) +#include "./targets/rx230/r_sci_rx230_private.h" /* RX230 */ +#elif defined(BSP_MCU_RX231) +#include "./targets/rx231/r_sci_rx231_private.h" /* RX231 */ +#elif defined(BSP_MCU_RX23E_A) +#include "./targets/rx23e-a/r_sci_rx23e-a_private.h" /* RX23E-A */ +#elif defined(BSP_MCU_RX23E_B) +#include "./targets/rx23e-b/r_sci_rx23e-b_private.h" /* RX23E-B */ +#elif defined(BSP_MCU_RX23T) +#include "./targets/rx23t/r_sci_rx23t_private.h" /* RX23T */ +#elif defined(BSP_MCU_RX23W) +#include "./targets/rx23w/r_sci_rx23w_private.h" /* RX23W */ +#elif defined(BSP_MCU_RX24T) +#include "./targets/rx24t/r_sci_rx24t_private.h" /* RX24T */ +#elif defined(BSP_MCU_RX24U) +#include "./targets/rx24u/r_sci_rx24u_private.h" /* RX24U */ +#elif defined(BSP_MCU_RX26T) +#include "./targets/rx26t/r_sci_rx26t_private.h" /* RX26T */ +#elif defined(BSP_MCU_RX64M) +#include "./targets/rx64m/r_sci_rx64m_private.h" /* RX64M */ +#elif defined(BSP_MCU_RX65N) +#include "./targets/rx65n/r_sci_rx65n_private.h" /* RX65N */ +#elif defined(BSP_MCU_RX66T) +#include "./targets/rx66t/r_sci_rx66t_private.h" /* RX66T */ +#elif defined(BSP_MCU_RX66N) +#include "./targets/rx66n/r_sci_rx66n_private.h" /* RX66N */ +#elif defined(BSP_MCU_RX671) +#include "./targets/rx671/r_sci_rx671_private.h" /* RX671 */ +#elif defined(BSP_MCU_RX660) +#include "./targets/rx660/r_sci_rx660_private.h" /* RX660 */ +#elif defined(BSP_MCU_RX71M) +#include "./targets/rx71m/r_sci_rx71m_private.h" /* RX71M */ +#elif defined(BSP_MCU_RX72T) +#include "./targets/rx72t/r_sci_rx72t_private.h" /* RX72T */ +#elif defined(BSP_MCU_RX72M) +#include "./targets/rx72m/r_sci_rx72m_private.h" /* RX72M */ +#elif defined(BSP_MCU_RX72N) +#include "./targets/rx72n/r_sci_rx72n_private.h" /* RX72N */ +#else +#error "ERROR - r_sci_rxXXX_private.h not included." +#endif + +#endif /* SCI_RX_PLATFORM_H */ + diff --git a/drivers/rx/rdp/src/r_sci_rx/src/r_sci_rx_private.h b/drivers/rx/rdp/src/r_sci_rx/src/r_sci_rx_private.h new file mode 100644 index 00000000..4574e9e8 --- /dev/null +++ b/drivers/rx/rdp/src/r_sci_rx/src/r_sci_rx_private.h @@ -0,0 +1,311 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2016 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_sci_rx_private.h +* Description : Functions for using SCI on the RX devices. +************************************************************************************************************************ +* History : DD.MM.YYYY Version Description +* 01.10.2016 1.80 Initial Release. (The remake of the r01an1815ju0170 to the base.) +* 28.09.2018 2.10 Added SCI_CFG_DATA_MATCH_INCLUDED for configuration data match function. +* Fix GSCE Code Checker errors. +* 01.02.2019 2.20 Added support received data match function for RX65N (SCI10 and SCI11). +* 20.05.2019 3.00 Added support for GNUC and ICCRX. +* 28.06.2019 3.10 Added support for RX23W +* 15.08.2019 3.20 Added support received data match function for RX72M (SCI0 to SCI11). +* Added support FIFO mode for RX72M (SCI7 to SCI11). +* 25.08.2020 3.60 Added feature using DTC/DMAC in SCI transfer. +* Merged IrDA functionality to SCI FIT. +* 31.03.2021 3.80 Added support for RX671. +* Added support for bit number of SCI FIT. +* 15.04.2021 3.90 Added support for RX140. +* 31.03.2023 4.80 Fixed to comply with GSCE Coding Standards Rev.6.5.0. +***********************************************************************************************************************/ + +#ifndef SCI_RX_H +#define SCI_RX_H + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "../r_sci_rx_if.h" +#if ((TX_DTC_DMACA_ENABLE & 0x01) || (RX_DTC_DMACA_ENABLE & 0x01)) +#include "r_dtc_rx_if.h" +#include "r_sci_rx_dtc.h" +#endif +#if ((TX_DTC_DMACA_ENABLE & 0x02) || (RX_DTC_DMACA_ENABLE & 0x02)) +#include "r_dmaca_rx_if.h" +#include "r_sci_rx_dmaca.h" +#endif + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Bit number */ +#define SCI_BIT0 (0) +#define SCI_BIT1 (1) +#define SCI_BIT2 (2) +#define SCI_BIT3 (3) +#define SCI_BIT4 (4) +#define SCI_BIT5 (5) +#define SCI_BIT6 (6) +#define SCI_BIT7 (7) +#define SCI_BIT8 (8) +#define SCI_BIT9 (9) +#define SCI_BIT10 (10) +#define SCI_BIT11 (11) +#define SCI_BIT12 (12) +#define SCI_BIT13 (13) +#define SCI_BIT14 (14) +#define SCI_BIT15 (15) +#define SCI_BIT16 (16) +#define SCI_BIT17 (17) +#define SCI_BIT18 (18) +#define SCI_BIT19 (19) +#define SCI_BIT20 (20) +#define SCI_BIT21 (21) +#define SCI_BIT22 (22) +#define SCI_BIT23 (23) +#define SCI_BIT24 (24) +#define SCI_BIT25 (25) +#define SCI_BIT26 (26) +#define SCI_BIT27 (27) +#define SCI_BIT28 (28) +#define SCI_BIT29 (29) +#define SCI_BIT30 (30) +#define SCI_BIT31 (31) + +/* Bit position masks */ +#define BIT0_MASK (0x00000001U) +#define BIT1_MASK (0x00000002U) +#define BIT2_MASK (0x00000004U) +#define BIT3_MASK (0x00000008U) +#define BIT4_MASK (0x00000010U) +#define BIT5_MASK (0x00000020U) +#define BIT6_MASK (0x00000040U) +#define BIT7_MASK (0x00000080U) +#define BIT8_MASK (0x00000100U) +#define BIT9_MASK (0x00000200U) +#define BIT10_MASK (0x00000400U) +#define BIT11_MASK (0x00000800U) +#define BIT12_MASK (0x00001000U) +#define BIT13_MASK (0x00002000U) +#define BIT14_MASK (0x00004000U) +#define BIT15_MASK (0x00008000U) +#define BIT16_MASK (0x00010000U) +#define BIT17_MASK (0x00020000U) +#define BIT18_MASK (0x00040000U) +#define BIT19_MASK (0x00080000U) +#define BIT20_MASK (0x00100000U) +#define BIT21_MASK (0x00200000U) +#define BIT22_MASK (0x00400000U) +#define BIT23_MASK (0x00800000U) +#define BIT24_MASK (0x01000000U) +#define BIT25_MASK (0x02000000U) +#define BIT26_MASK (0x04000000U) +#define BIT27_MASK (0x08000000U) +#define BIT28_MASK (0x10000000U) +#define BIT29_MASK (0x20000000U) +#define BIT30_MASK (0x40000000U) +#define BIT31_MASK (0x80000000U) + +#ifndef NULL /* Resolves e2studio code analyzer false error message. */ + #define NULL (0) +#endif + +#if ((SCI_CFG_CH7_FIFO_INCLUDED) || \ + (SCI_CFG_CH8_FIFO_INCLUDED) || \ + (SCI_CFG_CH9_FIFO_INCLUDED) || \ + (SCI_CFG_CH10_FIFO_INCLUDED) || \ + (SCI_CFG_CH11_FIFO_INCLUDED)) + #define SCI_CFG_FIFO_INCLUDED (1) +#endif + +#if ((SCI_CFG_CH0_DATA_MATCH_INCLUDED) || \ + (SCI_CFG_CH1_DATA_MATCH_INCLUDED) || \ + (SCI_CFG_CH2_DATA_MATCH_INCLUDED) || \ + (SCI_CFG_CH3_DATA_MATCH_INCLUDED) || \ + (SCI_CFG_CH4_DATA_MATCH_INCLUDED) || \ + (SCI_CFG_CH5_DATA_MATCH_INCLUDED) || \ + (SCI_CFG_CH6_DATA_MATCH_INCLUDED) || \ + (SCI_CFG_CH7_DATA_MATCH_INCLUDED) || \ + (SCI_CFG_CH8_DATA_MATCH_INCLUDED) || \ + (SCI_CFG_CH9_DATA_MATCH_INCLUDED) || \ + (SCI_CFG_CH10_DATA_MATCH_INCLUDED) || \ + (SCI_CFG_CH11_DATA_MATCH_INCLUDED)) + #define SCI_CFG_DATA_MATCH_INCLUDED (1) +#endif + +#if ((SCI_CFG_CH0_RX_DATA_SAMPLING_TIMING_INCLUDED) || \ + (SCI_CFG_CH1_RX_DATA_SAMPLING_TIMING_INCLUDED) || \ + (SCI_CFG_CH2_RX_DATA_SAMPLING_TIMING_INCLUDED) || \ + (SCI_CFG_CH3_RX_DATA_SAMPLING_TIMING_INCLUDED) || \ + (SCI_CFG_CH4_RX_DATA_SAMPLING_TIMING_INCLUDED) || \ + (SCI_CFG_CH5_RX_DATA_SAMPLING_TIMING_INCLUDED) || \ + (SCI_CFG_CH6_RX_DATA_SAMPLING_TIMING_INCLUDED) || \ + (SCI_CFG_CH7_RX_DATA_SAMPLING_TIMING_INCLUDED) || \ + (SCI_CFG_CH8_RX_DATA_SAMPLING_TIMING_INCLUDED) || \ + (SCI_CFG_CH9_RX_DATA_SAMPLING_TIMING_INCLUDED) || \ + (SCI_CFG_CH10_RX_DATA_SAMPLING_TIMING_INCLUDED) || \ + (SCI_CFG_CH11_RX_DATA_SAMPLING_TIMING_INCLUDED)) + #define SCI_CFG_RX_DATA_SAMPLING_TIMING_INCLUDED (1) +#endif + +#if ((SCI_CFG_CH0_TX_SIGNAL_TRANSITION_TIMING_INCLUDED) || \ + (SCI_CFG_CH1_TX_SIGNAL_TRANSITION_TIMING_INCLUDED) || \ + (SCI_CFG_CH2_TX_SIGNAL_TRANSITION_TIMING_INCLUDED) || \ + (SCI_CFG_CH3_TX_SIGNAL_TRANSITION_TIMING_INCLUDED) || \ + (SCI_CFG_CH4_TX_SIGNAL_TRANSITION_TIMING_INCLUDED) || \ + (SCI_CFG_CH5_TX_SIGNAL_TRANSITION_TIMING_INCLUDED) || \ + (SCI_CFG_CH6_TX_SIGNAL_TRANSITION_TIMING_INCLUDED) || \ + (SCI_CFG_CH7_TX_SIGNAL_TRANSITION_TIMING_INCLUDED) || \ + (SCI_CFG_CH8_TX_SIGNAL_TRANSITION_TIMING_INCLUDED) || \ + (SCI_CFG_CH9_TX_SIGNAL_TRANSITION_TIMING_INCLUDED) || \ + (SCI_CFG_CH10_TX_SIGNAL_TRANSITION_TIMING_INCLUDED) || \ + (SCI_CFG_CH11_TX_SIGNAL_TRANSITION_TIMING_INCLUDED)) + #define SCI_CFG_TX_SIGNAL_TRANSITION_TIMING_INCLUDED (1) +#endif + +#if SCI_CFG_FIFO_INCLUDED +#define SCI_SSRFIFO_ORER (hdl->rom->regs->SSRFIFO.BIT.ORER) +#define SCI_SSRFIFO_PER (hdl->rom->regs->SSRFIFO.BIT.PER) +#define SCI_SSRFIFO_FER (hdl->rom->regs->SSRFIFO.BIT.FER) +#define SCI_SSRFIFO_RDF (hdl->rom->regs->SSRFIFO.BIT.RDF) +#define SCI_SSRFIFO (hdl->rom->regs->SSRFIFO.BYTE) +#define SCI_PRV_RX_FIFO_THRESHOLD (hdl->rom->regs->FCR.BIT.RTRG) +#define SCI_PRV_RX_FIFO_USED_CNT (hdl->rom->regs->FDR.BIT.R) +#define SCI_PRV_TX_FIFO_USED_CNT (hdl->rom->regs->FDR.BIT.T) +#endif +#define SCI_SSR_ORER (hdl->rom->regs->SSR.BIT.ORER) +#define SCI_SSR_PER (hdl->rom->regs->SSR.BIT.PER) +#define SCI_SSR_FER (hdl->rom->regs->SSR.BIT.FER) +#define SCI_SSR (hdl->rom->regs->SSR.BYTE) + +#if SCI_CFG_FIFO_INCLUDED +#define SCI_FIFO_FRAME_SIZE (16) +#endif + +/* SCR register dummy read */ +#define SCI_SCR_DUMMY_READ \ + if (0x00 == hdl->rom->regs->SCR.BYTE) \ + { \ + R_BSP_NOP(); \ + } + +/* Interrupt Request register flag clear */ +#define SCI_IR_TXI_CLEAR (*hdl->rom->ir_txi = 0) + +/* TDR/FTDR register write access */ +#if SCI_CFG_FIFO_INCLUDED +#define SCI_TDR(byte) \ + if (true == hdl->fifo_ctrl) \ + { \ + hdl->rom->regs->FTDR.BYTE.L = (byte); \ + } \ + else \ + { \ + hdl->rom->regs->TDR = (byte); \ + } +#else +#define SCI_TDR(byte) \ + hdl->rom->regs->TDR = (byte); +#endif + +/* RDR/FRDR register read access */ +#if SCI_CFG_FIFO_INCLUDED +#define SCI_RDR(byte) \ + if (true == hdl->fifo_ctrl) \ + { \ + (byte) = hdl->rom->regs->FRDR.BYTE.L; \ + } \ + else \ + { \ + (byte) = hdl->rom->regs->RDR; \ + } +#else +#define SCI_RDR(byte) \ + (byte) = hdl->rom->regs->RDR; +#endif + +/***************************************************************************** +Typedef definitions +******************************************************************************/ + +/***************************************************************************** +Private global variables and functions +******************************************************************************/ +#if ((SCI_CFG_ASYNC_INCLUDED) || (TX_DTC_DMACA_ENABLE | RX_DTC_DMACA_ENABLE) || (SCI_CFG_IRDA_INCLUDED)) +extern void txi_handler (sci_hdl_t const hdl); +#endif + +#if SCI_CFG_TEI_INCLUDED +extern void tei_handler(sci_hdl_t const hdl); +#endif + +extern void rxi_handler (sci_hdl_t const hdl); + +extern void eri_handler (sci_hdl_t const hdl); + +#endif /* SCI_RX_H */ + +#if defined(BSP_MCU_RX23T) + #if ((SCI_DMACA_ENABLE == (TX_DTC_DMACA_ENABLE & SCI_DMACA_ENABLE)) || (SCI_DMACA_ENABLE == (RX_DTC_DMACA_ENABLE & SCI_DMACA_ENABLE))) + #error "This MCU does not have DMAC module." + #error "Change to SCI_CFG_CHxx_TX_DTC_DMACA_ENABLE and SCI_CFG_CHxx_RX_DTC_DMACA_ENABLE (1) or (0) in r_sci_rx_config.h." + #endif +#elif defined(BSP_MCU_RX24T) + #if ((SCI_DMACA_ENABLE == (TX_DTC_DMACA_ENABLE & SCI_DMACA_ENABLE)) || (SCI_DMACA_ENABLE == (RX_DTC_DMACA_ENABLE & SCI_DMACA_ENABLE))) + #error "This MCU does not have DMAC module." + #error "Change to SCI_CFG_CHxx_TX_DTC_DMACA_ENABLE and SCI_CFG_CHxx_RX_DTC_DMACA_ENABLE (1) or (0) in r_sci_rx_config.h." + #endif +#elif defined(BSP_MCU_RX24U) + #if ((SCI_DMACA_ENABLE == (TX_DTC_DMACA_ENABLE & SCI_DMACA_ENABLE)) || (SCI_DMACA_ENABLE == (RX_DTC_DMACA_ENABLE & SCI_DMACA_ENABLE))) + #error "This MCU does not have DMAC module." + #error "Change to SCI_CFG_CHxx_TX_DTC_DMACA_ENABLE and SCI_CFG_CHxx_RX_DTC_DMACA_ENABLE (1) or (0) in r_sci_rx_config.h." + #endif +#elif defined(BSP_MCU_RX130) + #if ((SCI_DMACA_ENABLE == (TX_DTC_DMACA_ENABLE & SCI_DMACA_ENABLE)) || (SCI_DMACA_ENABLE == (RX_DTC_DMACA_ENABLE & SCI_DMACA_ENABLE))) + #error "This MCU does not have DMAC module." + #error "Change to SCI_CFG_CHxx_TX_DTC_DMACA_ENABLE and SCI_CFG_CHxx_RX_DTC_DMACA_ENABLE (1) or (0) in r_sci_rx_config.h." + #endif +#elif defined(BSP_MCU_RX13T) + #if ((SCI_DMACA_ENABLE == (TX_DTC_DMACA_ENABLE & SCI_DMACA_ENABLE)) || (SCI_DMACA_ENABLE == (RX_DTC_DMACA_ENABLE & SCI_DMACA_ENABLE))) + #error "This MCU does not have DMAC module." + #error "Change to SCI_CFG_CHxx_TX_DTC_DMACA_ENABLE and SCI_CFG_CHxx_RX_DTC_DMACA_ENABLE (1) or (0) in r_sci_rx_config.h." + #endif +#elif defined(BSP_MCU_RX113) + #if ((SCI_DMACA_ENABLE == (TX_DTC_DMACA_ENABLE & SCI_DMACA_ENABLE)) || (SCI_DMACA_ENABLE == (RX_DTC_DMACA_ENABLE & SCI_DMACA_ENABLE))) + #error "This MCU does not have DMAC module." + #error "Change to SCI_CFG_CHxx_TX_DTC_DMACA_ENABLE and SCI_CFG_CHxx_RX_DTC_DMACA_ENABLE (1) or (0) in r_sci_rx_config.h." + #endif +#elif defined(BSP_MCU_RX111) + #if ((SCI_DMACA_ENABLE == (TX_DTC_DMACA_ENABLE & SCI_DMACA_ENABLE)) || (SCI_DMACA_ENABLE == (RX_DTC_DMACA_ENABLE & SCI_DMACA_ENABLE))) + #error "This MCU does not have DMAC module." + #error "Change to SCI_CFG_CHxx_TX_DTC_DMACA_ENABLE and SCI_CFG_CHxx_RX_DTC_DMACA_ENABLE (1) or (0) in r_sci_rx_config.h." + #endif +#elif defined(BSP_MCU_RX110) + #if ((SCI_DMACA_ENABLE == (TX_DTC_DMACA_ENABLE & SCI_DMACA_ENABLE)) || (SCI_DMACA_ENABLE == (RX_DTC_DMACA_ENABLE & SCI_DMACA_ENABLE))) + #error "This MCU does not have DMAC module." + #error "Change to SCI_CFG_CHxx_TX_DTC_DMACA_ENABLE and SCI_CFG_CHxx_RX_DTC_DMACA_ENABLE (1) or (0) in r_sci_rx_config.h." + #endif +#elif defined(BSP_MCU_RX140) + #if ((SCI_DMACA_ENABLE == (TX_DTC_DMACA_ENABLE & SCI_DMACA_ENABLE)) || (SCI_DMACA_ENABLE == (RX_DTC_DMACA_ENABLE & SCI_DMACA_ENABLE))) + #error "This MCU does not have DMAC module." + #error "Change to SCI_CFG_CHxx_TX_DTC_DMACA_ENABLE and SCI_CFG_CHxx_RX_DTC_DMACA_ENABLE (1) or (0) in r_sci_rx_config.h." + #endif +#endif diff --git a/drivers/rx/rdp/src/r_sci_rx/src/targets/rx130/r_sci_rx130.c b/drivers/rx/rdp/src/r_sci_rx/src/targets/rx130/r_sci_rx130.c new file mode 100644 index 00000000..76ec96c1 --- /dev/null +++ b/drivers/rx/rdp/src/r_sci_rx/src/targets/rx130/r_sci_rx130.c @@ -0,0 +1,1199 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2016 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* File Name : r_sci_rx.c +* Description : Functions for using SCI on the RX130 device. +*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* 27.05.2016 1.00 Initial Release. +* 19.12.2016 1.10 FIT_NO_PTR check added to NULL check. +* SCI_CMD_EN_TEI was changed to ineffective, because it is meaningless command. +* 07.03.2017 2.00 Added RX130-512KB support +* 20.05.2019 3.00 Added support for GNUC and ICCRX. +* 15.08.2019 3.20 Fixed warnings in IAR. +* 25.08.2020 3.60 Added feature using DTC/DMAC in SCI transfer. +* 31.03.2021 3.80 Added support circular buffer in mode asynchronous. +* 27.12.2022 4.60 Updated macro definition enable and disable nested interrupt for TXI, RXI, ERI, TEI. +* 31.01.2024 5.10 Added WAIT_LOOP comments. +***********************************************************************************************************************/ + +/***************************************************************************** +Includes , "Project Includes" +******************************************************************************/ +#include "platform.h" + +#include "r_sci_rx130_private.h" + +/***************************************************************************** +Typedef definitions +******************************************************************************/ + +/***************************************************************************** +Macro definitions +******************************************************************************/ + +/***************************************************************************** +Private global variables and functions +******************************************************************************/ +#if SCI_CFG_CH0_INCLUDED +R_BSP_PRAGMA_STATIC_INTERRUPT(sci0_txi0_isr, VECT(SCI0,TXI0)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci0_txi0_isr(void); +R_BSP_PRAGMA_STATIC_INTERRUPT(sci0_rxi0_isr, VECT(SCI0,RXI0)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci0_rxi0_isr(void); +R_BSP_PRAGMA_STATIC_INTERRUPT(sci0_tei0_isr, VECT(SCI0,TEI0)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci0_tei0_isr(void); +R_BSP_PRAGMA_STATIC_INTERRUPT(sci0_eri0_isr, VECT(SCI0,ERI0)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci0_eri0_isr(void); + +#endif + +#if SCI_CFG_CH1_INCLUDED +R_BSP_PRAGMA_STATIC_INTERRUPT(sci1_txi1_isr, VECT(SCI1,TXI1)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci1_txi1_isr(void); +R_BSP_PRAGMA_STATIC_INTERRUPT(sci1_rxi1_isr, VECT(SCI1,RXI1)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci1_rxi1_isr(void); +R_BSP_PRAGMA_STATIC_INTERRUPT(sci1_tei1_isr, VECT(SCI1,TEI1)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci1_tei1_isr(void); +R_BSP_PRAGMA_STATIC_INTERRUPT(sci1_eri1_isr, VECT(SCI1,ERI1)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci1_eri1_isr(void); + +#endif + +#if SCI_CFG_CH5_INCLUDED +R_BSP_PRAGMA_STATIC_INTERRUPT(sci5_txi5_isr, VECT(SCI5,TXI5)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci5_txi5_isr(void); +R_BSP_PRAGMA_STATIC_INTERRUPT(sci5_rxi5_isr, VECT(SCI5,RXI5)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci5_rxi5_isr(void); +R_BSP_PRAGMA_STATIC_INTERRUPT(sci5_tei5_isr, VECT(SCI5,TEI5)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci5_tei5_isr(void); +R_BSP_PRAGMA_STATIC_INTERRUPT(sci5_eri5_isr, VECT(SCI5,ERI5)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci5_eri5_isr(void); + + +#endif + +#if SCI_CFG_CH6_INCLUDED +R_BSP_PRAGMA_STATIC_INTERRUPT(sci6_txi6_isr, VECT(SCI6,TXI6)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci6_txi6_isr(void); +R_BSP_PRAGMA_STATIC_INTERRUPT(sci6_rxi6_isr, VECT(SCI6,RXI6)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci6_rxi6_isr(void); +R_BSP_PRAGMA_STATIC_INTERRUPT(sci6_tei6_isr, VECT(SCI6,TEI6)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci6_tei6_isr(void); +R_BSP_PRAGMA_STATIC_INTERRUPT(sci6_eri6_isr, VECT(SCI6,ERI6)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci6_eri6_isr(void); + +#endif + +#if SCI_CFG_CH8_INCLUDED +R_BSP_PRAGMA_STATIC_INTERRUPT(sci8_txi8_isr, VECT(SCI8,TXI8)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci8_txi8_isr(void); +R_BSP_PRAGMA_STATIC_INTERRUPT(sci8_rxi8_isr, VECT(SCI8,RXI8)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci8_rxi8_isr(void); +R_BSP_PRAGMA_STATIC_INTERRUPT(sci8_tei8_isr, VECT(SCI8,TEI8)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci8_tei8_isr(void); +R_BSP_PRAGMA_STATIC_INTERRUPT(sci8_eri8_isr, VECT(SCI8,ERI8)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci8_eri8_isr(void); + +#endif + +#if SCI_CFG_CH9_INCLUDED +R_BSP_PRAGMA_STATIC_INTERRUPT(sci9_txi9_isr, VECT(SCI9,TXI9)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci9_txi9_isr(void); +R_BSP_PRAGMA_STATIC_INTERRUPT(sci9_rxi9_isr, VECT(SCI9,RXI9)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci9_rxi9_isr(void); +R_BSP_PRAGMA_STATIC_INTERRUPT(sci9_tei9_isr, VECT(SCI9,TEI9)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci9_tei9_isr(void); +R_BSP_PRAGMA_STATIC_INTERRUPT(sci9_eri9_isr, VECT(SCI9,ERI9)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci9_eri9_isr(void); + +#endif + +#if SCI_CFG_CH12_INCLUDED +R_BSP_PRAGMA_STATIC_INTERRUPT(sci12_txi12_isr, VECT(SCI12,TXI12)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci12_txi12_isr(void); +R_BSP_PRAGMA_STATIC_INTERRUPT(sci12_rxi12_isr, VECT(SCI12,RXI12)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci12_rxi12_isr(void); +R_BSP_PRAGMA_STATIC_INTERRUPT(sci12_tei12_isr, VECT(SCI12,TEI12)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci12_tei12_isr(void); +R_BSP_PRAGMA_STATIC_INTERRUPT(sci12_eri12_isr, VECT(SCI12,ERI12)) +R_BSP_ATTRIB_STATIC_INTERRUPT void sci12_eri12_isr(void); + +#endif + +/***************************************************************************** +* Function Name: sci_mcu_param_check +* Description : This function parameters check on MCU. +* (channel range, interrupt priority, etc...) +* Arguments : chan - +* channel to check +* Return Value : SCI_SUCCESS - +* parameter check all successfully +* SCI_ERR_BAD_CHAN - +* channel number invalid for part +* SCI_ERR_INVALID_ARG - +* interrupt priority out of range +******************************************************************************/ +sci_err_t sci_mcu_param_check(uint8_t const chan) +{ + /* channel range parameter check */ + if ((chan != SCI_CH0) && (chan != SCI_CH1) + && (chan != SCI_CH5) && (chan != SCI_CH6) + && (chan != SCI_CH8) && (chan != SCI_CH9) + && (chan != SCI_CH12)) + { + return SCI_ERR_BAD_CHAN; + } + + return SCI_SUCCESS; +} /* End of function sci_mcu_param_check() */ + +/***************************************************************************** +* Function Name: sci_init_register +* Description : This function initializes the register for SCI. +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* Return Value : none +******************************************************************************/ +void sci_init_register(sci_hdl_t const hdl) +{ + /* SCI transmit enable bit and receive enable bit check & disable */ + /* WAIT_LOOP */ + while ((0 != hdl->rom->regs->SCR.BIT.TE) || (0 != hdl->rom->regs->SCR.BIT.RE)) + { + if (0 != hdl->rom->regs->SCR.BIT.TE) + { + hdl->rom->regs->SCR.BIT.TE = 0; // transmit disable + } + if (0 != hdl->rom->regs->SCR.BIT.RE) + { + hdl->rom->regs->SCR.BIT.RE = 0; // receive disable + } + } + + /* SMR register initialize */ + hdl->rom->regs->SMR.BYTE = 0x00; + + /* SCR register initialize */ + hdl->rom->regs->SCR.BYTE = 0x00; + + /* SSR register initialize */ + if (1 == SCI_SSR_ORER) + { + SCI_SSR_ORER = 0; + } + if (1 == SCI_SSR_PER) + { + SCI_SSR_PER = 0; + } + if (1 == SCI_SSR_FER) + { + SCI_SSR_FER = 0; + } + + /* SCMR register initialize */ + hdl->rom->regs->SCMR.BIT.SMIF = 0; + hdl->rom->regs->SCMR.BIT.SINV = 0; + hdl->rom->regs->SCMR.BIT.SDIR = 0; + + /* BRR register initialize */ + hdl->rom->regs->BRR = 0xFF; + + /* SEMR register initialize */ + hdl->rom->regs->SEMR.BIT.BRME = 0; + hdl->rom->regs->SEMR.BIT.ABCS = 0; + hdl->rom->regs->SEMR.BIT.NFEN = 0; + hdl->rom->regs->SEMR.BIT.BGDM = 0; + hdl->rom->regs->SEMR.BIT.RXDESEL = 0; + + /* SNFR register initialize */ + hdl->rom->regs->SNFR.BYTE = 0; + + /* SPMR register initialize */ + hdl->rom->regs->SPMR.BIT.CTSE = 0; + hdl->rom->regs->SPMR.BIT.CKPOL = 0; + hdl->rom->regs->SPMR.BIT.CKPH = 0; + + return; +} /* End of function sci_init_register() */ + +/***************************************************************************** +* Function Name: sci_init_bit_rate +* Description : This function determines the best possible settings for the +* baud rate registers for the specified peripheral clock speed +* and baud rate. Note that this does not guarantee a low bit +* error rate, just the best possible one. The bit rate error is +* returned in .1% increments. If the hardware cannot support +* the specified combination, a value of 1000 (100% error) is +* returned. +* +* NOTE: The transmitter and receiver (TE and RE bits in SCR) must be disabled +* prior to calling this function. +* +* The application must pause for 1 bit time after the BRR register +* is loaded before transmitting/receiving to allow time for the clock +* to settle. +* +* Arguments : hdl - +* Handle for channel (ptr to chan control block) +* NOTE: mode element must be already set +* pclk - +* Peripheral clock speed; e.g. 24000000 for 24MHz +* baud - +* Baud rate; 19200, 57600, 115200, etc. +* Return Value : bit error in .1% increments; e.g. 16 = 1.6% bit rate error +* a value of 1000 denotes 100% error; no registers set +******************************************************************************/ +int32_t sci_init_bit_rate(sci_hdl_t const hdl, + uint32_t const pclk, + uint32_t const baud) +{ + uint32_t i; + uint32_t num_divisors = 0; + uint32_t ratio; + uint32_t tmp; + baud_divisor_t const *p_baud_info=NULL; + + uint32_t divisor; + uint32_t int_M; + float float_M; + float error; + float abs_error; + +#if SCI_CFG_PARAM_CHECKING_ENABLE + if ((0 == pclk) || (0 == baud)) + { + return 1000; + } +#endif + + /* SELECT PROPER TABLE BASED UPON MODE */ + if (hdl->mode == SCI_MODE_ASYNC) + { +#if (SCI_CFG_ASYNC_INCLUDED) + p_baud_info = async_baud; + num_divisors = NUM_DIVISORS_ASYNC; +#endif + } + else + { /* SYNC or SSPI */ +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + p_baud_info = sync_baud; + num_divisors = NUM_DIVISORS_SYNC; +#endif + } + + /* FIND DIVISOR; table has associated ABCS, BGDM and CKS values */ + /* BRR must be 255 or less */ + /* the "- 1" is ignored in some steps for approximations */ + /* BRR = (PCLK/(divisor * baud)) - 1 */ + /* BRR = (ratio / divisor) - 1 */ + ratio = pclk/baud; + + /* WAIT_LOOP */ + for (i=0; i < num_divisors; i++) + { + if (ratio < (uint32_t)(p_baud_info[i].divisor * 256)) + { + break; + } + } + + /* RETURN IF BRR WILL BE >255 OR LESS THAN 0 */ + if (i == num_divisors) + { + return(1000); // impossible baud rate requested; return 100% error + } + + divisor = (uint32_t)p_baud_info[i].divisor; + tmp = ratio/(divisor); // tmp = PCLK/(baud * divisor) = BRR+1 = N+1 + if(0 == tmp) + { + return(1000); // illegal value; return 100% error + } + + /* SET BRR, ABCS, BDGM, and CKS */ + tmp = ratio / (divisor/2); // divide by half the divisor + + /* if odd, "round up" by ignoring -1; divide by 2 again for rest of divisor */ + hdl->rom->regs->BRR = (uint8_t)((tmp & 0x01) ? (tmp/2) : ((tmp/2)-1)); + hdl->rom->regs->SEMR.BIT.ABCS = p_baud_info[i].abcs; + hdl->rom->regs->SEMR.BIT.BGDM = p_baud_info[i].bgdm; + hdl->rom->regs->SMR.BIT.CKS = p_baud_info[i].cks; + + /* CALCULATE BIT RATE ERROR. + * RETURN IF ERROR LESS THAN 1% OR IF IN SYNCHRONOUS/SSPI MODE. + */ + tmp = ratio/(divisor); // tmp = PCLK/(baud * divisor) = BRR+1 = N+1 + error = ( ((float)pclk / ((baud * divisor) * tmp)) - 1) * 100; + abs_error = (error < 0) ? (-error) : error; + + if ((abs_error <= 1.0) || (hdl->mode != SCI_MODE_ASYNC)) + { + hdl->rom->regs->SEMR.BIT.BRME = 0; // disable MDDR + return (uint32_t)(error*10); + } + + /* CALCULATE M ASSUMING A 0% ERROR then WRITE REGISTER */ + hdl->rom->regs->BRR = (uint8_t)(tmp-1); + float_M = ((float)((baud * divisor) * 256) * tmp) / pclk; + float_M *= 2; + int_M = (uint32_t)float_M; + int_M = (int_M & 0x01) ? ((int_M/2) + 1) : (int_M/2); + + hdl->rom->regs->MDDR = (uint8_t)int_M; // write M + hdl->rom->regs->SEMR.BIT.BRME = 1; // enable MDDR + error = (( (float)(pclk) / (((divisor * tmp) * baud) * ((float)(256)/int_M)) ) - 1) * 100; + + /* Casting float to int32_t */ + return (int32_t)(error*10); +} /* End of function sci_init_bit_rate() */ + +/***************************************************************************** +* Function Name: sci_initialize_ints +* Description : This function sets priority, clears flags, and sets +* interrupts in both the ICU and SCI peripheral. These include +* RXI, TXI, TEI, and ERI interrupts. +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* priority - +* priority for interrupts +* Return Value : none +******************************************************************************/ +void sci_initialize_ints(sci_hdl_t const hdl, + uint8_t const priority) +{ + /* SET PRIORITY FOR INTERRUPTS */ + *hdl->rom->ipr = priority; + + /* DISABLE INTERRUPTS */ + DISABLE_ERI_INT; + DISABLE_RXI_INT; + DISABLE_TXI_INT; + DISABLE_TEI_INT; + + /* CLEAR INTERRUPT FLAGS */ + *hdl->rom->ir_rxi = 0; + *hdl->rom->ir_txi = 0; + *hdl->rom->ir_tei = 0; + *hdl->rom->ir_eri = 0; + + /* ENABLE ERI AND RXI INTERRUPTS REQUESTS */ + ENABLE_ERI_INT; + ENABLE_RXI_INT; + + /* ENABLE INTERRUPTS IN SCI PERIPHERAL */ + /* Note: Enable interrupts after xcvr or will get "extra" interrupt */ + hdl->rom->regs->SCR.BYTE |= SCI_EN_XCVR_MASK; // enable TE, RE, TXI, and RXI/ERI + + return; +} /* End of function sci_initialize_ints() */ + +/***************************************************************************** +* Function Name: sci_disable_ints +* Description : This function disable interrupts in both the ICU and SCI +* peripheral. These include RXI, TXI, TEI, and ERI interrupts. +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* Return Value : none +******************************************************************************/ +void sci_disable_ints(sci_hdl_t const hdl) +{ + /* disable ICU interrupts */ + DISABLE_RXI_INT; + DISABLE_TXI_INT; + DISABLE_ERI_INT; + DISABLE_TEI_INT; + + /* disable peripheral interrupts and xcvr (TE and RE) */ + hdl->rom->regs->SCR.BYTE = 0; + + return; +} /* End of function sci_disable_ints() */ + +/***************************************************************************** +ISRs +******************************************************************************/ + +#if ((SCI_CFG_ASYNC_INCLUDED) || (TX_DTC_DMACA_ENABLE | RX_DTC_DMACA_ENABLE)) +/***************************************************************************** +* sciN_txiN_isr +* +* Description : TXI interrupt routines for every SCI channel. +******************************************************************************/ + +#if SCI_CFG_CH0_INCLUDED +R_BSP_ATTRIB_STATIC_INTERRUPT void sci0_txi0_isr(void) +{ +#if SCI_CFG_CH0_EN_TXI_NESTED_INT == 1 + /* set bit PSW.I = 1 to allow nested interrupt */ + R_BSP_SETPSW_I(); +#endif + + txi_handler(&ch0_ctrl); +} /* End of function sci0_txi0_isr() */ + +#endif + +#if SCI_CFG_CH1_INCLUDED +R_BSP_ATTRIB_STATIC_INTERRUPT void sci1_txi1_isr(void) +{ +#if SCI_CFG_CH1_EN_TXI_NESTED_INT == 1 + /* set bit PSW.I = 1 to allow nested interrupt */ + R_BSP_SETPSW_I(); +#endif + + txi_handler(&ch1_ctrl); +} /* End of function sci1_txi1_isr() */ + +#endif + +#if SCI_CFG_CH5_INCLUDED +R_BSP_ATTRIB_STATIC_INTERRUPT void sci5_txi5_isr(void) +{ +#if SCI_CFG_CH5_EN_TXI_NESTED_INT == 1 + /* set bit PSW.I = 1 to allow nested interrupt */ + R_BSP_SETPSW_I(); +#endif + + txi_handler(&ch5_ctrl); +} /* End of function sci5_txi5_isr() */ + +#endif + +#if SCI_CFG_CH6_INCLUDED +R_BSP_ATTRIB_STATIC_INTERRUPT void sci6_txi6_isr(void) +{ +#if SCI_CFG_CH6_EN_TXI_NESTED_INT == 1 + /* set bit PSW.I = 1 to allow nested interrupt */ + R_BSP_SETPSW_I(); +#endif + + txi_handler(&ch6_ctrl); +} /* End of function sci6_txi6_isr() */ + +#endif + +#if SCI_CFG_CH8_INCLUDED +R_BSP_ATTRIB_STATIC_INTERRUPT void sci8_txi8_isr(void) +{ +#if SCI_CFG_CH8_EN_TXI_NESTED_INT == 1 + /* set bit PSW.I = 1 to allow nested interrupt */ + R_BSP_SETPSW_I(); +#endif + + txi_handler(&ch8_ctrl); +} /* End of function sci8_txi8_isr() */ + +#endif + +#if SCI_CFG_CH9_INCLUDED +R_BSP_ATTRIB_STATIC_INTERRUPT void sci9_txi9_isr(void) +{ +#if SCI_CFG_CH9_EN_TXI_NESTED_INT == 1 + /* set bit PSW.I = 1 to allow nested interrupt */ + R_BSP_SETPSW_I(); +#endif + + txi_handler(&ch9_ctrl); +} /* End of function sci9_txi9_isr() */ + +#endif + +#if SCI_CFG_CH12_INCLUDED +R_BSP_ATTRIB_STATIC_INTERRUPT void sci12_txi12_isr(void) +{ +#if SCI_CFG_CH12_EN_TXI_NESTED_INT == 1 + /* set bit PSW.I = 1 to allow nested interrupt */ + R_BSP_SETPSW_I(); +#endif + + txi_handler(&ch12_ctrl); +} /* End of function sci12_txi12_isr() */ + +#endif + +#endif /* End of ((SCI_CFG_ASYNC_INCLUDED) || (TX_DTC_DMACA_ENABLE | RX_DTC_DMACA_ENABLE)) */ + +#if SCI_CFG_TEI_INCLUDED +/***************************************************************************** +* sciN_teiN_isr +* +* Description : TEI interrupt routines for every SCI channel. +******************************************************************************/ + +#if SCI_CFG_CH0_INCLUDED +R_BSP_ATTRIB_STATIC_INTERRUPT void sci0_tei0_isr(void) +{ +#if SCI_CFG_CH0_EN_TEI_NESTED_INT == 1 + /* set bit PSW.I = 1 to allow nested interrupt */ + R_BSP_SETPSW_I(); +#endif + + tei_handler(&ch0_ctrl); +} /* End of function sci0_tei0_isr() */ + +#endif + +#if SCI_CFG_CH1_INCLUDED +R_BSP_ATTRIB_STATIC_INTERRUPT void sci1_tei1_isr(void) +{ +#if SCI_CFG_CH1_EN_TEI_NESTED_INT == 1 + /* set bit PSW.I = 1 to allow nested interrupt */ + R_BSP_SETPSW_I(); +#endif + + tei_handler(&ch1_ctrl); +} /* End of function sci1_tei1_isr() */ + +#endif + +#if SCI_CFG_CH5_INCLUDED +R_BSP_ATTRIB_STATIC_INTERRUPT void sci5_tei5_isr(void) +{ +#if SCI_CFG_CH5_EN_TEI_NESTED_INT == 1 + /* set bit PSW.I = 1 to allow nested interrupt */ + R_BSP_SETPSW_I(); +#endif + + tei_handler(&ch5_ctrl); +} /* End of function sci5_tei5_isr() */ + +#endif + +#if SCI_CFG_CH6_INCLUDED +R_BSP_ATTRIB_STATIC_INTERRUPT void sci6_tei6_isr(void) +{ +#if SCI_CFG_CH6_EN_TEI_NESTED_INT == 1 + /* set bit PSW.I = 1 to allow nested interrupt */ + R_BSP_SETPSW_I(); +#endif + + tei_handler(&ch6_ctrl); +} /* End of function sci6_tei6_isr() */ + +#endif + +#if SCI_CFG_CH8_INCLUDED +R_BSP_ATTRIB_STATIC_INTERRUPT void sci8_tei8_isr(void) +{ +#if SCI_CFG_CH8_EN_TEI_NESTED_INT == 1 + /* set bit PSW.I = 1 to allow nested interrupt */ + R_BSP_SETPSW_I(); +#endif + + tei_handler(&ch8_ctrl); +} /* End of function sci8_tei8_isr() */ + +#endif + +#if SCI_CFG_CH9_INCLUDED +R_BSP_ATTRIB_STATIC_INTERRUPT void sci9_tei9_isr(void) +{ +#if SCI_CFG_CH9_EN_TEI_NESTED_INT == 1 + /* set bit PSW.I = 1 to allow nested interrupt */ + R_BSP_SETPSW_I(); +#endif + + tei_handler(&ch9_ctrl); +} /* End of function sci9_tei9_isr() */ + +#endif + +#if SCI_CFG_CH12_INCLUDED +R_BSP_ATTRIB_STATIC_INTERRUPT void sci12_tei12_isr(void) +{ +#if SCI_CFG_CH12_EN_TEI_NESTED_INT == 1 + /* set bit PSW.I = 1 to allow nested interrupt */ + R_BSP_SETPSW_I(); +#endif + + tei_handler(&ch12_ctrl); +} /* End of function sci12_tei12_isr() */ + +#endif + +#endif + +/***************************************************************************** +* sciN_rxiN_isr +* +* Description : RXI interrupt routines for every SCI channel. +******************************************************************************/ + +#if SCI_CFG_CH0_INCLUDED +R_BSP_ATTRIB_STATIC_INTERRUPT void sci0_rxi0_isr(void) +{ +#if SCI_CFG_CH0_EN_RXI_NESTED_INT == 1 + /* set bit PSW.I = 1 to allow nested interrupt */ + R_BSP_SETPSW_I(); +#endif + + rxi_handler(&ch0_ctrl); +} /* End of function sci0_rxi0_isr() */ + +#endif + +#if SCI_CFG_CH1_INCLUDED +R_BSP_ATTRIB_STATIC_INTERRUPT void sci1_rxi1_isr(void) +{ +#if SCI_CFG_CH1_EN_RXI_NESTED_INT == 1 + /* set bit PSW.I = 1 to allow nested interrupt */ + R_BSP_SETPSW_I(); +#endif + + rxi_handler(&ch1_ctrl); +} /* End of function sci1_rxi1_isr() */ + +#endif + +#if SCI_CFG_CH5_INCLUDED +R_BSP_ATTRIB_STATIC_INTERRUPT void sci5_rxi5_isr(void) +{ +#if SCI_CFG_CH5_EN_RXI_NESTED_INT == 1 + /* set bit PSW.I = 1 to allow nested interrupt */ + R_BSP_SETPSW_I(); +#endif + + rxi_handler(&ch5_ctrl); +} /* End of function sci5_rxi5_isr() */ + +#endif + +#if SCI_CFG_CH6_INCLUDED +R_BSP_ATTRIB_STATIC_INTERRUPT void sci6_rxi6_isr(void) +{ +#if SCI_CFG_CH6_EN_RXI_NESTED_INT == 1 + /* set bit PSW.I = 1 to allow nested interrupt */ + R_BSP_SETPSW_I(); +#endif + + rxi_handler(&ch6_ctrl); +} /* End of function sci6_rxi6_isr() */ + +#endif + +#if SCI_CFG_CH8_INCLUDED +R_BSP_ATTRIB_STATIC_INTERRUPT void sci8_rxi8_isr(void) +{ +#if SCI_CFG_CH8_EN_RXI_NESTED_INT == 1 + /* set bit PSW.I = 1 to allow nested interrupt */ + R_BSP_SETPSW_I(); +#endif + + rxi_handler(&ch8_ctrl); +} /* End of function sci8_rxi8_isr() */ + +#endif + +#if SCI_CFG_CH9_INCLUDED +R_BSP_ATTRIB_STATIC_INTERRUPT void sci9_rxi9_isr(void) +{ +#if SCI_CFG_CH9_EN_RXI_NESTED_INT == 1 + /* set bit PSW.I = 1 to allow nested interrupt */ + R_BSP_SETPSW_I(); +#endif + + rxi_handler(&ch9_ctrl); +} /* End of function sci9_rxi9_isr() */ + +#endif + +#if SCI_CFG_CH12_INCLUDED +R_BSP_ATTRIB_STATIC_INTERRUPT void sci12_rxi12_isr(void) +{ +#if SCI_CFG_CH12_EN_RXI_NESTED_INT == 1 + /* set bit PSW.I = 1 to allow nested interrupt */ + R_BSP_SETPSW_I(); +#endif + + rxi_handler(&ch12_ctrl); +} /* End of function sci12_rxi12_isr() */ + +#endif + +/***************************************************************************** +* sciN_eriN_isr +* +* Description : ERI interrupt routines for every SCI channel. +******************************************************************************/ + +#if SCI_CFG_CH0_INCLUDED +R_BSP_ATTRIB_STATIC_INTERRUPT void sci0_eri0_isr(void) +{ +#if SCI_CFG_CH0_EN_ERI_NESTED_INT == 1 + /* set bit PSW.I = 1 to allow nested interrupt */ + R_BSP_SETPSW_I(); +#endif + + eri_handler(&ch0_ctrl); +} /* End of function sci0_eri0_isr() */ + +#endif + +#if SCI_CFG_CH1_INCLUDED +R_BSP_ATTRIB_STATIC_INTERRUPT void sci1_eri1_isr(void) +{ +#if SCI_CFG_CH1_EN_ERI_NESTED_INT == 1 + /* set bit PSW.I = 1 to allow nested interrupt */ + R_BSP_SETPSW_I(); +#endif + + eri_handler(&ch1_ctrl); +} /* End of function sci1_eri1_isr() */ + +#endif + +#if SCI_CFG_CH5_INCLUDED +R_BSP_ATTRIB_STATIC_INTERRUPT void sci5_eri5_isr(void) +{ +#if SCI_CFG_CH5_EN_ERI_NESTED_INT == 1 + /* set bit PSW.I = 1 to allow nested interrupt */ + R_BSP_SETPSW_I(); +#endif + + eri_handler(&ch5_ctrl); +} /* End of function sci5_eri5_isr() */ +#endif + +#if SCI_CFG_CH6_INCLUDED +R_BSP_ATTRIB_STATIC_INTERRUPT void sci6_eri6_isr(void) +{ +#if SCI_CFG_CH6_EN_ERI_NESTED_INT == 1 + /* set bit PSW.I = 1 to allow nested interrupt */ + R_BSP_SETPSW_I(); +#endif + + eri_handler(&ch6_ctrl); +} /* End of function sci6_eri6_isr() */ + +#endif + +#if SCI_CFG_CH8_INCLUDED +R_BSP_ATTRIB_STATIC_INTERRUPT void sci8_eri8_isr(void) +{ +#if SCI_CFG_CH8_EN_ERI_NESTED_INT == 1 + /* set bit PSW.I = 1 to allow nested interrupt */ + R_BSP_SETPSW_I(); +#endif + + eri_handler(&ch8_ctrl); +} /* End of function sci8_eri8_isr() */ + +#endif + +#if SCI_CFG_CH9_INCLUDED +R_BSP_ATTRIB_STATIC_INTERRUPT void sci9_eri9_isr(void) +{ +#if SCI_CFG_CH9_EN_ERI_NESTED_INT == 1 + /* set bit PSW.I = 1 to allow nested interrupt */ + R_BSP_SETPSW_I(); +#endif + + eri_handler(&ch9_ctrl); +} /* End of function sci9_eri9_isr() */ + +#endif + +#if SCI_CFG_CH12_INCLUDED +R_BSP_ATTRIB_STATIC_INTERRUPT void sci12_eri12_isr(void) +{ +#if SCI_CFG_CH12_EN_ERI_NESTED_INT == 1 + /* set bit PSW.I = 1 to allow nested interrupt */ + R_BSP_SETPSW_I(); +#endif + + eri_handler(&ch12_ctrl); +} /* End of function sci12_eri12_isr() */ + +#endif + +#if (SCI_CFG_ASYNC_INCLUDED) +/***************************************************************************** +* Function Name: sci_async_cmds +* Description : This function configures non-standard UART hardware and +* performs special software operations. +* +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* cmd - +* command to run +* p_args - +* pointer argument(s) specific to command +* Return Value : SCI_SUCCESS - +* Command completed successfully. +* SCI_ERR_NULL_PTR - +* p_args is NULL when required for cmd +* SCI_ERR_INVALID_ARG - +* The cmd value or p_args contains an invalid value. +******************************************************************************/ +sci_err_t sci_async_cmds(sci_hdl_t const hdl, + sci_cmd_t const cmd, + void *p_args) +{ + sci_err_t err=SCI_SUCCESS; + int32_t bit_err; + uint32_t slow_baud; + +#if SCI_CFG_PARAM_CHECKING_ENABLE + if (((NULL == p_args) || (FIT_NO_PTR == p_args)) + && ((SCI_CMD_TX_Q_BYTES_FREE == cmd) || (SCI_CMD_RX_Q_BYTES_AVAIL_TO_READ == cmd))) + { + return SCI_ERR_NULL_PTR; + } +#endif + + switch(cmd) + { + case (SCI_CMD_EN_NOISE_CANCEL): + hdl->rom->regs->SCR.BYTE &= (~SCI_EN_XCVR_MASK); + SCI_SCR_DUMMY_READ; + hdl->rom->regs->SEMR.BIT.NFEN = 1; /* enable noise filter */ + hdl->rom->regs->SNFR.BYTE = 0; /* clock divided by 1 (default) */ + SCI_IR_TXI_CLEAR; + hdl->rom->regs->SCR.BYTE |= SCI_EN_XCVR_MASK; + break; + + case (SCI_CMD_OUTPUT_BAUD_CLK): + hdl->rom->regs->SCR.BYTE &= (~SCI_EN_XCVR_MASK); + SCI_SCR_DUMMY_READ; + hdl->rom->regs->SCR.BIT.CKE = 0x01; /* output baud clock on SCK pin */ + SCI_IR_TXI_CLEAR; + hdl->rom->regs->SCR.BYTE |= SCI_EN_XCVR_MASK; + break; + + case (SCI_CMD_START_BIT_EDGE): + hdl->rom->regs->SCR.BYTE &= (~SCI_EN_XCVR_MASK); + SCI_SCR_DUMMY_READ; + hdl->rom->regs->SEMR.BIT.RXDESEL = 1; /* detect start bit on falling edge */ + SCI_IR_TXI_CLEAR; + hdl->rom->regs->SCR.BYTE |= SCI_EN_XCVR_MASK; + break; + +#if SCI_CFG_TEI_INCLUDED + case (SCI_CMD_EN_TEI): /* SCI_CMD_EN_TEI is obsolete command, but it exists only for compatibility with older version. */ + break; +#endif +#if TX_DTC_DMACA_ENABLE + case (SCI_CMD_CHECK_TX_DONE): + { + if((SCI_DTC_ENABLE == hdl->rom->dtc_dmaca_tx_enable) || (SCI_DMACA_ENABLE == hdl->rom->dtc_dmaca_tx_enable)) + { + if (false == hdl->tx_idle) + { + err = SCI_ERR_XCVR_BUSY; + } + } + break; + } +#endif + +#if RX_DTC_DMACA_ENABLE + case (SCI_CMD_CHECK_RX_DONE): + { + if((SCI_DTC_ENABLE == hdl->rom->dtc_dmaca_rx_enable) || (SCI_DMACA_ENABLE == hdl->rom->dtc_dmaca_rx_enable)) + { + if (0 != hdl->queue[0].rx_cnt) + { + err = SCI_ERR_XCVR_BUSY; + } + } + break; + } +#endif + case (SCI_CMD_TX_Q_FLUSH): + { +#if (SCI_CFG_USE_CIRCULAR_BUFFER == 1) + R_BYTEQ_Flush(hdl->u_tx_data.que); +#else + /* Disable TXI interrupt */ + DISABLE_TXI_INT; + R_BYTEQ_Flush(hdl->u_tx_data.que); + ENABLE_TXI_INT; +#endif + break; + } + + case (SCI_CMD_RX_Q_FLUSH): + { +#if (SCI_CFG_USE_CIRCULAR_BUFFER == 1) + R_BYTEQ_Flush(hdl->u_rx_data.que); +#else + /* Disable RXI interrupt */ + DISABLE_RXI_INT; + R_BYTEQ_Flush(hdl->u_rx_data.que); + ENABLE_RXI_INT; +#endif + break; + } + + case (SCI_CMD_TX_Q_BYTES_FREE): + R_BYTEQ_Unused(hdl->u_tx_data.que, (uint16_t *) p_args); + break; + + case (SCI_CMD_RX_Q_BYTES_AVAIL_TO_READ): + R_BYTEQ_Used(hdl->u_rx_data.que, (uint16_t *) p_args); + break; + + case (SCI_CMD_GENERATE_BREAK): + + /* flush transmit queue */ + DISABLE_TXI_INT; + R_BYTEQ_Flush(hdl->u_tx_data.que); +#if(TX_DTC_DMACA_ENABLE) + if((SCI_DTC_ENABLE == hdl->rom->dtc_dmaca_tx_enable) || (SCI_DMACA_ENABLE == hdl->rom->dtc_dmaca_tx_enable)) + { + sci_fifo_ctrl_t *p_tctrl = &hdl->queue[hdl->qindex_app_rx]; + p_tctrl->tx_cnt = 0; + p_tctrl->tx_fraction = 0; +#if ((TX_DTC_DMACA_ENABLE & 0x01) || (RX_DTC_DMACA_ENABLE & 0x01)) + if(SCI_DTC_ENABLE == hdl->rom->dtc_dmaca_tx_enable) + { + dtc_cmd_arg_t args_dtc; + args_dtc.act_src = hdl->rom->dtc_tx_act_src; + R_DTC_Control(DTC_CMD_ACT_SRC_DISABLE, NULL, &args_dtc); + + } +#endif + + } +#endif + ENABLE_TXI_INT; + + /* NOTE: the following steps will abort anything being sent */ + + /* set baud rate 1.5x slower */ + slow_baud = (hdl->baud_rate << 1) / 3; + hdl->rom->regs->SCR.BYTE &= (~SCI_EN_XCVR_MASK); + SCI_SCR_DUMMY_READ; + bit_err = sci_init_bit_rate(hdl, hdl->pclk_speed, slow_baud); + SCI_IR_TXI_CLEAR; + hdl->rom->regs->SCR.BYTE |= SCI_EN_XCVR_MASK; + if (1000 == bit_err) + { + err = SCI_ERR_INVALID_ARG; + } + else + { + /* transmit "0" and wait for completion */ + SCI_TDR(0); + + /* WAIT_LOOP */ + while (0 == hdl->rom->regs->SSR.BIT.TEND) + { + R_BSP_NOP(); + } + + /* restore original baud rate */ + hdl->rom->regs->SCR.BYTE &= (~SCI_EN_XCVR_MASK); + SCI_SCR_DUMMY_READ; + sci_init_bit_rate(hdl, hdl->pclk_speed, hdl->baud_rate); + SCI_IR_TXI_CLEAR; + hdl->rom->regs->SCR.BYTE |= SCI_EN_XCVR_MASK; + } + break; + + default: + err = SCI_ERR_INVALID_ARG; + break; + } + + return err; +} /* End of function sci_async_cmds() */ +#endif + +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) +/***************************************************************************** +* Function Name: sci_sync_cmds +* Description : This function performs special software operations specific +* to the SSPI and SYNC protocols. +* +* Arguments : hdl - +* handle for channel (ptr to chan control block) +* cmd - +* command to run +* p_args - +* pointer argument(s) specific to command +* Return Value : SCI_SUCCESS - +* Command completed successfully. +* SCI_ERR_NULL_PTR - +* p_args is NULL when required for cmd +* SCI_ERR_INVALID_ARG - +* The cmd value or p_args contains an invalid value. +* May be due to mode channel is operating in. +******************************************************************************/ +sci_err_t sci_sync_cmds(sci_hdl_t const hdl, + sci_cmd_t const cmd, + void *p_args) +{ + sci_spi_mode_t spi_mode; + sci_cb_args_t args; + sci_err_t err=SCI_SUCCESS; + + switch (cmd) + { + case (SCI_CMD_CHECK_XFER_DONE): + if (hdl->tx_idle == false) + { + err = SCI_ERR_XFER_NOT_DONE; + } + break; + + case (SCI_CMD_XFER_LSB_FIRST): + hdl->rom->regs->SCR.BYTE &= ~SCI_EN_XCVR_MASK; + SCI_SCR_DUMMY_READ; + hdl->rom->regs->SCMR.BIT.SDIR = 0; + SCI_IR_TXI_CLEAR; + hdl->rom->regs->SCR.BYTE |= SCI_EN_XCVR_MASK; + break; + + case (SCI_CMD_XFER_MSB_FIRST): + hdl->rom->regs->SCR.BYTE &= ~SCI_EN_XCVR_MASK; + SCI_SCR_DUMMY_READ; + hdl->rom->regs->SCMR.BIT.SDIR = 1; + SCI_IR_TXI_CLEAR; + hdl->rom->regs->SCR.BYTE |= SCI_EN_XCVR_MASK; + break; + + case (SCI_CMD_INVERT_DATA): + hdl->rom->regs->SCR.BYTE &= ~SCI_EN_XCVR_MASK; + SCI_SCR_DUMMY_READ; + hdl->rom->regs->SCMR.BIT.SINV ^= 1; + SCI_IR_TXI_CLEAR; + hdl->rom->regs->SCR.BYTE |= SCI_EN_XCVR_MASK; + break; + + case (SCI_CMD_ABORT_XFER): + + /* disable receive interrupts in ICU and peripheral */ + DISABLE_RXI_INT; + DISABLE_ERI_INT; +#if(TX_DTC_DMACA_ENABLE) + if((SCI_DTC_ENABLE == hdl->rom->dtc_dmaca_tx_enable) || (SCI_DMACA_ENABLE == hdl->rom->dtc_dmaca_tx_enable)) + { + sci_fifo_ctrl_t *p_tctrl = &hdl->queue[hdl->qindex_app_rx]; + p_tctrl->tx_cnt = 0; + p_tctrl->tx_fraction = 0; +#if ((TX_DTC_DMACA_ENABLE & 0x01) || (RX_DTC_DMACA_ENABLE & 0x01)) + if((SCI_DTC_ENABLE == hdl->rom->dtc_dmaca_tx_enable) && (SCI_DTC_ENABLE == hdl->rom->dtc_dmaca_rx_enable)) + { + // Set condition for reset TDFR to generate interrupt in next time + hdl->qindex_int_tx = 1; + dtc_cmd_arg_t args_dtc; + args_dtc.act_src = hdl->rom->dtc_tx_act_src; + R_DTC_Control(DTC_CMD_ACT_SRC_DISABLE, NULL, &args_dtc); + + args_dtc.act_src = hdl->rom->dtc_rx_act_src; + R_DTC_Control(DTC_CMD_ACT_SRC_DISABLE, NULL, &args_dtc); + } +#endif + } +#endif + hdl->rom->regs->SCR.BYTE &= ~(SCI_SCR_REI_MASK | SCI_SCR_RE_MASK | SCI_SCR_TE_MASK); + + hdl->tx_cnt = 0; + hdl->tx_dummy = false; + hdl->tx_idle = true; + + /* Do callback if available */ + if ((hdl->callback != NULL) && (hdl->callback != FIT_NO_FUNC)) + { + args.hdl = hdl; + args.event = SCI_EVT_XFER_ABORTED; + hdl->callback((void *)&args); + } + + *hdl->rom->ir_rxi = 0; /* clear rxi interrupt flag */ +#if SCI_CFG_FIFO_INCLUDED +#if(TX_DTC_DMACA_ENABLE) + if((SCI_DTC_DMACA_DISABLE != hdl->rom->dtc_dmaca_tx_enable) && (true != hdl->fifo_ctrl)) + { + *hdl->rom->ir_txi = 0; + } +#endif +#else +#if(TX_DTC_DMACA_ENABLE) + if((SCI_DTC_DMACA_DISABLE != hdl->rom->dtc_dmaca_tx_enable)) + { + *hdl->rom->ir_txi = 0; + } +#endif +#endif + *hdl->rom->ir_eri = 0; /* clear eri interrupt flag */ + + ENABLE_ERI_INT; /* enable rx err interrupts in ICU */ + ENABLE_RXI_INT; /* enable receive interrupts in ICU */ + + /* Enable receive interrupt in peripheral after rcvr or will get "extra" interrupt */ + hdl->rom->regs->SCR.BYTE |= SCI_SCR_RE_MASK | SCI_SCR_TE_MASK; + hdl->rom->regs->SCR.BYTE |= SCI_SCR_REI_MASK; + break; + +#if RX_DTC_DMACA_ENABLE + case (SCI_CMD_CHECK_RX_SYNC_DONE): + { + if((SCI_DTC_ENABLE == hdl->rom->dtc_dmaca_rx_enable) || (SCI_DMACA_ENABLE == hdl->rom->dtc_dmaca_rx_enable)) + { + if (0 != hdl->queue[0].rx_cnt) + { + err = SCI_ERR_XCVR_BUSY; + } + } + break; + } +#endif + case (SCI_CMD_CHANGE_SPI_MODE): +#if SCI_CFG_PARAM_CHECKING_ENABLE + + if (hdl->mode != SCI_MODE_SSPI) + { + return SCI_ERR_INVALID_ARG; + } + + /* Check parameters */ + if ((p_args == NULL) || (p_args == FIT_NO_PTR)) + { + return SCI_ERR_NULL_PTR; + } + + /* Casting pointer void* type is valid */ + spi_mode = *((sci_spi_mode_t *)p_args); + + if ((spi_mode != SCI_SPI_MODE_0) && (spi_mode != SCI_SPI_MODE_1) + && (spi_mode != SCI_SPI_MODE_2) && (spi_mode != SCI_SPI_MODE_3)) + { + return SCI_ERR_INVALID_ARG; + } +#endif + hdl->rom->regs->SCR.BYTE &= ~SCI_EN_XCVR_MASK; + SCI_SCR_DUMMY_READ; + hdl->rom->regs->SPMR.BYTE &= 0x3F; /* clear previous mode */ + hdl->rom->regs->SPMR.BYTE |= *((uint8_t *)p_args); + SCI_IR_TXI_CLEAR; + hdl->rom->regs->SCR.BYTE |= SCI_EN_XCVR_MASK; + break; + + default: + err = SCI_ERR_INVALID_ARG; + break; + } + + return err; +} /* End of function sci_sync_cmds() */ +#endif + diff --git a/drivers/rx/rdp/src/r_sci_rx/src/targets/rx130/r_sci_rx130_data.c b/drivers/rx/rdp/src/r_sci_rx/src/targets/rx130/r_sci_rx130_data.c new file mode 100644 index 00000000..b7a9a7dc --- /dev/null +++ b/drivers/rx/rdp/src/r_sci_rx/src/targets/rx130/r_sci_rx130_data.c @@ -0,0 +1,419 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2016 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/********************************************************************************************************************** +* File Name : r_sci_rx130_data.c +* Description : Functions for using SCI on the RX130 device. +*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* 27.05.2016 1.00 Initial Release. +* 07.03.2017 2.00 Added RX130-512KB support. +* 20.05.2019 3.00 Added support for GNUC and ICCRX. +* 25.08.2020 3.60 Added feature using DTC/DMAC in SCI transfer. +* 31.03.2021 3.80 Updated macro definition enable and disable TXI, RXI, ERI, TEI. +* 31.03.2022 4.40 Added receive flag when using DTC/DMAC. +* Updated channel variables in struct st_sci_ch_rom. +***********************************************************************************************************************/ + +/***************************************************************************** +Includes , "Project Includes" +******************************************************************************/ +#include "platform.h" + +#include "r_sci_rx130_private.h" + +/***************************************************************************** +Typedef definitions +******************************************************************************/ + +/***************************************************************************** +Macro definitions +******************************************************************************/ + +/***************************************************************************** +Private global variables and functions +******************************************************************************/ + +/* BAUD DIVISOR INFO */ + +#if (SCI_CFG_ASYNC_INCLUDED) +/* + * Asynchronous + * BRR = (PCLK/(divisor * baud)) - 1 + * when: bgdm,abcs=11, divisor = 16*pow(2,2n-1) + * bgdm,abcs=01, divisor = 32*pow(2,2n-1) + * bgdm,abcs=10, divisor = 32*pow(2,2n-1) + * bgdm,abcs=00, divisor = 64*pow(2,2n-1) + */ +const baud_divisor_t async_baud[NUM_DIVISORS_ASYNC]= +{ + /* divisor result, bgdm, abcs, n */ + {8, 1, 1, 0}, + {16, 1, 0, 0}, + {32, 0, 0, 0}, + {64, 1, 0, 1}, + {128, 0, 0, 1}, + {256, 1, 0, 2}, + {512, 0, 0, 2}, + {1024, 1, 0, 3}, + {2048, 0, 0, 3} +}; +#endif + +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) +/* Synchronous and Simple SPI */ +/* BRR = (PCLK/(divisor * baud)) - 1 */ +/* abcs=0, bdgm=0, divisor = 8*pow(2,2n-1) */ + +const baud_divisor_t sync_baud[NUM_DIVISORS_SYNC]= +{ + /* divisor result, abcs, bgdm, n */ + {4, 0, 0, 0}, + {16, 0, 0, 1}, + {64, 0, 0, 2}, + {256, 0, 0, 3} +}; +#endif + + +/* CHANNEL MEMORY ALLOCATIONS */ + +#if SCI_CFG_CH0_INCLUDED + +/* rom info */ +const sci_ch_rom_t ch0_rom = {(volatile struct st_sci12 R_BSP_EVENACCESS_SFR *)&SCI0, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&SYSTEM.MSTPCRB.LONG, BIT31_MASK, + &ICU.IPR[IPR_SCI0_RXI0].BYTE, + &ICU.IR[IR_SCI0_RXI0].BYTE, + &ICU.IR[IR_SCI0_TXI0].BYTE, + &ICU.IR[IR_SCI0_TEI0].BYTE, + &ICU.IR[IR_SCI0_ERI0].BYTE, + &ICU.IER[IER_SCI0_RXI0].BYTE, + &ICU.IER[IER_SCI0_TXI0].BYTE, + &ICU.IER[IER_SCI0_TEI0].BYTE, + &ICU.IER[IER_SCI0_ERI0].BYTE, + SCI_BIT6, SCI_BIT7, SCI_BIT0, SCI_BIT1 + #if ((TX_DTC_DMACA_ENABLE || RX_DTC_DMACA_ENABLE)) + , SCI_CFG_CH0_TX_DTC_DMACA_ENABLE + , SCI_CFG_CH0_RX_DTC_DMACA_ENABLE + #endif + #if ((TX_DTC_DMACA_ENABLE & 0x01) || (RX_DTC_DMACA_ENABLE & 0x01)) + , DTCE_SCI0_TXI0 + , DTCE_SCI0_RXI0 + /* Casting to uint8_t type is valid */ + , (uint8_t)SCI_CH0 + #endif + }; +/* channel control block */ +sci_ch_ctrl_t ch0_ctrl = {&ch0_rom, SCI_MODE_OFF, 0, NULL, NULL, NULL, true + #if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + , true, 0, 0, false + #endif + , BSP_PCLKB_HZ + #if ((TX_DTC_DMACA_ENABLE || RX_DTC_DMACA_ENABLE)) + , true, 0, 0, 0, 0, 0 + #endif + }; +#endif + + +#if SCI_CFG_CH1_INCLUDED + +/* rom info */ +const sci_ch_rom_t ch1_rom = {(volatile struct st_sci12 R_BSP_EVENACCESS_SFR *)&SCI1, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&SYSTEM.MSTPCRB.LONG, BIT30_MASK, + &ICU.IPR[IPR_SCI1_RXI1].BYTE, + &ICU.IR[IR_SCI1_RXI1].BYTE, + &ICU.IR[IR_SCI1_TXI1].BYTE, + &ICU.IR[IR_SCI1_TEI1].BYTE, + &ICU.IR[IR_SCI1_ERI1].BYTE, + &ICU.IER[IER_SCI1_RXI1].BYTE, + &ICU.IER[IER_SCI1_TXI1].BYTE, + &ICU.IER[IER_SCI1_TEI1].BYTE, + &ICU.IER[IER_SCI1_ERI1].BYTE, + SCI_BIT2, SCI_BIT3, SCI_BIT4, SCI_BIT5 + #if ((TX_DTC_DMACA_ENABLE || RX_DTC_DMACA_ENABLE)) + , SCI_CFG_CH1_TX_DTC_DMACA_ENABLE + , SCI_CFG_CH1_RX_DTC_DMACA_ENABLE + #endif + #if ((TX_DTC_DMACA_ENABLE & 0x01) || (RX_DTC_DMACA_ENABLE & 0x01)) + , DTCE_SCI1_TXI1 + , DTCE_SCI1_RXI1 + /* Casting to uint8_t type is valid */ + , (uint8_t)SCI_CH1 + #endif + }; +/* channel control block */ +sci_ch_ctrl_t ch1_ctrl = {&ch1_rom, SCI_MODE_OFF, 0, NULL, NULL, NULL, true + #if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + , true, 0, 0, false + #endif + , BSP_PCLKB_HZ + #if ((TX_DTC_DMACA_ENABLE || RX_DTC_DMACA_ENABLE)) + , true, 0, 0, 0, 0, 0 + #endif + }; +#endif + + +#if SCI_CFG_CH5_INCLUDED + +/* rom info */ +const sci_ch_rom_t ch5_rom = {(volatile struct st_sci12 R_BSP_EVENACCESS_SFR *)&SCI5, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&SYSTEM.MSTPCRB.LONG, BIT26_MASK, + &ICU.IPR[IPR_SCI5_RXI5].BYTE, + &ICU.IR[IR_SCI5_RXI5].BYTE, + &ICU.IR[IR_SCI5_TXI5].BYTE, + &ICU.IR[IR_SCI5_TEI5].BYTE, + &ICU.IR[IR_SCI5_ERI5].BYTE, + &ICU.IER[IER_SCI5_RXI5].BYTE, + &ICU.IER[IER_SCI5_TXI5].BYTE, + &ICU.IER[IER_SCI5_TEI5].BYTE, + &ICU.IER[IER_SCI5_ERI5].BYTE, + SCI_BIT6, SCI_BIT7, SCI_BIT0, SCI_BIT1 + #if ((TX_DTC_DMACA_ENABLE || RX_DTC_DMACA_ENABLE)) + , SCI_CFG_CH5_TX_DTC_DMACA_ENABLE + , SCI_CFG_CH5_RX_DTC_DMACA_ENABLE + #endif + #if ((TX_DTC_DMACA_ENABLE & 0x01) || (RX_DTC_DMACA_ENABLE & 0x01)) + , DTCE_SCI5_TXI5 + , DTCE_SCI5_RXI5 + /* Casting to uint8_t type is valid */ + , (uint8_t)SCI_CH5 + #endif + }; +/* channel control block */ +sci_ch_ctrl_t ch5_ctrl = {&ch5_rom, SCI_MODE_OFF, 0, NULL, NULL, NULL, true + #if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + , true, 0, 0, false + #endif + , BSP_PCLKB_HZ + #if ((TX_DTC_DMACA_ENABLE || RX_DTC_DMACA_ENABLE)) + , true, 0, 0, 0, 0, 0 + #endif + }; +#endif + +#if SCI_CFG_CH6_INCLUDED + +/* rom info */ +const sci_ch_rom_t ch6_rom = {(volatile struct st_sci12 R_BSP_EVENACCESS_SFR *)&SCI6, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&SYSTEM.MSTPCRB.LONG, BIT25_MASK, + &ICU.IPR[IPR_SCI6_RXI6].BYTE, + &ICU.IR[IR_SCI6_RXI6].BYTE, + &ICU.IR[IR_SCI6_TXI6].BYTE, + &ICU.IR[IR_SCI6_TEI6].BYTE, + &ICU.IR[IR_SCI6_ERI6].BYTE, + &ICU.IER[IER_SCI6_RXI6].BYTE, + &ICU.IER[IER_SCI6_TXI6].BYTE, + &ICU.IER[IER_SCI6_TEI6].BYTE, + &ICU.IER[IER_SCI6_ERI6].BYTE, + SCI_BIT2, SCI_BIT3, SCI_BIT4, SCI_BIT5 + #if ((TX_DTC_DMACA_ENABLE || RX_DTC_DMACA_ENABLE)) + , SCI_CFG_CH6_TX_DTC_DMACA_ENABLE + , SCI_CFG_CH6_RX_DTC_DMACA_ENABLE + #endif + #if ((TX_DTC_DMACA_ENABLE & 0x01) || (RX_DTC_DMACA_ENABLE & 0x01)) + , DTCE_SCI6_TXI6 + , DTCE_SCI6_RXI6 + /* Casting to uint8_t type is valid */ + , (uint8_t)SCI_CH6 + #endif + }; +/* channel control block */ +sci_ch_ctrl_t ch6_ctrl = {&ch6_rom, SCI_MODE_OFF, 0, NULL, NULL, NULL, true + #if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + , true, 0, 0, false + #endif + , BSP_PCLKB_HZ + #if ((TX_DTC_DMACA_ENABLE || RX_DTC_DMACA_ENABLE)) + , true, 0, 0, 0, 0, 0 + #endif + }; +#endif + + +#if SCI_CFG_CH8_INCLUDED + +/* rom info */ +const sci_ch_rom_t ch8_rom = {(volatile struct st_sci12 R_BSP_EVENACCESS_SFR *)&SCI8, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&SYSTEM.MSTPCRC.LONG, BIT27_MASK, + &ICU.IPR[IPR_SCI8_RXI8].BYTE, + &ICU.IR[IR_SCI8_RXI8].BYTE, + &ICU.IR[IR_SCI8_TXI8].BYTE, + &ICU.IR[IR_SCI8_TEI8].BYTE, + &ICU.IR[IR_SCI8_ERI8].BYTE, + &ICU.IER[IER_SCI8_RXI8].BYTE, + &ICU.IER[IER_SCI8_TXI8].BYTE, + &ICU.IER[IER_SCI8_TEI8].BYTE, + &ICU.IER[IER_SCI8_ERI8].BYTE, + SCI_BIT6, SCI_BIT7, SCI_BIT0, SCI_BIT1 + #if ((TX_DTC_DMACA_ENABLE || RX_DTC_DMACA_ENABLE)) + , SCI_CFG_CH8_TX_DTC_DMACA_ENABLE + , SCI_CFG_CH8_RX_DTC_DMACA_ENABLE + #endif + #if ((TX_DTC_DMACA_ENABLE & 0x01) || (RX_DTC_DMACA_ENABLE & 0x01)) + , DTCE_SCI8_TXI8 + , DTCE_SCI8_RXI8 + /* Casting to uint8_t type is valid */ + , (uint8_t)SCI_CH8 + #endif + }; +/* channel control block */ +sci_ch_ctrl_t ch8_ctrl = {&ch8_rom, SCI_MODE_OFF, 0, NULL, NULL, NULL, true + #if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + , true, 0, 0, false + #endif + , BSP_PCLKB_HZ + #if ((TX_DTC_DMACA_ENABLE || RX_DTC_DMACA_ENABLE)) + , true, 0, 0, 0, 0, 0 + #endif + }; +#endif + + +#if SCI_CFG_CH9_INCLUDED + +/* rom info */ +const sci_ch_rom_t ch9_rom = {(volatile struct st_sci12 R_BSP_EVENACCESS_SFR *)&SCI9, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&SYSTEM.MSTPCRC.LONG, BIT26_MASK, + &ICU.IPR[IPR_SCI9_RXI9].BYTE, + &ICU.IR[IR_SCI9_RXI9].BYTE, + &ICU.IR[IR_SCI9_TXI9].BYTE, + &ICU.IR[IR_SCI9_TEI9].BYTE, + &ICU.IR[IR_SCI9_ERI9].BYTE, + &ICU.IER[IER_SCI9_RXI9].BYTE, + &ICU.IER[IER_SCI9_TXI9].BYTE, + &ICU.IER[IER_SCI9_TEI9].BYTE, + &ICU.IER[IER_SCI9_ERI9].BYTE, + SCI_BIT2, SCI_BIT3, SCI_BIT4, SCI_BIT5 + #if ((TX_DTC_DMACA_ENABLE || RX_DTC_DMACA_ENABLE)) + , SCI_CFG_CH9_TX_DTC_DMACA_ENABLE + , SCI_CFG_CH9_RX_DTC_DMACA_ENABLE + #endif + #if ((TX_DTC_DMACA_ENABLE & 0x01) || (RX_DTC_DMACA_ENABLE & 0x01)) + , DTCE_SCI9_TXI9 + , DTCE_SCI9_RXI9 + /* Casting to uint8_t type is valid */ + , (uint8_t)SCI_CH9 + #endif + }; +/* channel control block */ +sci_ch_ctrl_t ch9_ctrl = {&ch9_rom, SCI_MODE_OFF, 0, NULL, NULL, NULL, true + #if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + , true, 0, 0, false + #endif + , BSP_PCLKB_HZ + #if ((TX_DTC_DMACA_ENABLE || RX_DTC_DMACA_ENABLE)) + , true, 0, 0, 0, 0, 0 + #endif + }; +#endif + +#if SCI_CFG_CH12_INCLUDED + +/* rom info */ +const sci_ch_rom_t ch12_rom = {(volatile struct st_sci12 R_BSP_EVENACCESS_SFR *)&SCI12, + (volatile uint32_t R_BSP_EVENACCESS_SFR*)&SYSTEM.MSTPCRB.LONG, BIT4_MASK, + &ICU.IPR[IPR_SCI12_RXI12].BYTE, + &ICU.IR[IR_SCI12_RXI12].BYTE, + &ICU.IR[IR_SCI12_TXI12].BYTE, + &ICU.IR[IR_SCI12_TEI12].BYTE, + &ICU.IR[IR_SCI12_ERI12].BYTE, + &ICU.IER[IER_SCI12_RXI12].BYTE, + &ICU.IER[IER_SCI12_TXI12].BYTE, + &ICU.IER[IER_SCI12_TEI12].BYTE, + &ICU.IER[IER_SCI12_ERI12].BYTE, + SCI_BIT6, SCI_BIT7, SCI_BIT0, SCI_BIT1 + #if ((TX_DTC_DMACA_ENABLE || RX_DTC_DMACA_ENABLE)) + , SCI_CFG_CH12_TX_DTC_DMACA_ENABLE + , SCI_CFG_CH12_RX_DTC_DMACA_ENABLE + #endif + #if ((TX_DTC_DMACA_ENABLE & 0x01) || (RX_DTC_DMACA_ENABLE & 0x01)) + , DTCE_SCI12_TXI12 + , DTCE_SCI12_RXI12 + /* Casting to uint8_t type is valid */ + , (uint8_t)SCI_CH12 + #endif + }; +/* channel control block */ +sci_ch_ctrl_t ch12_ctrl = {&ch12_rom, SCI_MODE_OFF, 0, NULL, NULL, NULL, true + #if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + , true, 0, 0, false + #endif + , BSP_PCLKB_HZ + #if ((TX_DTC_DMACA_ENABLE || RX_DTC_DMACA_ENABLE)) + , true, 0, 0, 0, 0, 0 + #endif + }; +#endif + + +/* SCI HANDLE-ARRAY DECLARATION */ + +const sci_hdl_t g_handles[SCI_NUM_CH] = +{ +#if SCI_CFG_CH0_INCLUDED + &ch0_ctrl, +#else + NULL, +#endif + +#if SCI_CFG_CH1_INCLUDED + &ch1_ctrl, +#else + NULL, +#endif + + NULL, /* ch2 */ + NULL, /* ch3 */ + NULL, /* ch4 */ + +#if SCI_CFG_CH5_INCLUDED + &ch5_ctrl, +#else + NULL, +#endif +#if SCI_CFG_CH6_INCLUDED + &ch6_ctrl, +#else + NULL, +#endif + + NULL, /* ch7 */ +#if SCI_CFG_CH8_INCLUDED + &ch8_ctrl, +#else + NULL, +#endif +#if SCI_CFG_CH9_INCLUDED + &ch9_ctrl, +#else + NULL, +#endif + + NULL, /* ch10 */ + NULL, /* ch11 */ + +#if SCI_CFG_CH12_INCLUDED + &ch12_ctrl +#else + NULL +#endif +}; + diff --git a/drivers/rx/rdp/src/r_sci_rx/src/targets/rx130/r_sci_rx130_private.h b/drivers/rx/rdp/src/r_sci_rx/src/targets/rx130/r_sci_rx130_private.h new file mode 100644 index 00000000..2f3d5755 --- /dev/null +++ b/drivers/rx/rdp/src/r_sci_rx/src/targets/rx130/r_sci_rx130_private.h @@ -0,0 +1,286 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2016 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_sci_rx130.h +* Description : Functions for using SCI on the RX130 device. +************************************************************************************************************************ +* History : DD.MM.YYYY Version Description +* 27.05.2016 1.00 Initial Release. +* 07.03.2017 2.00 Added RX130-512KB support. +* 20.05.2019 3.00 Added support for GNUC and ICCRX. +* 25.08.2020 3.60 Added feature using DTC/DMAC in SCI transfer. +* 31.03.2021 3.80 Updated macro definition enable and disable TXI, RXI, ERI, TEI. +* 31.03.2022 4.40 Added receive flag when using DTC/DMAC. +* Updated channel variables in struct st_sci_ch_rom. +***********************************************************************************************************************/ + +#ifndef SCI_RX130_H +#define SCI_RX130_H + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "../../r_sci_rx_private.h" + +#if (SCI_CFG_ASYNC_INCLUDED) +#include "r_byteq_if.h" +#endif + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/* SCI channel include Check */ +#if (SCI_CFG_CH2_INCLUDED != 0) || (SCI_CFG_CH3_INCLUDED != 0) || \ + (SCI_CFG_CH4_INCLUDED != 0) || (SCI_CFG_CH7_INCLUDED != 0) || \ + (SCI_CFG_CH10_INCLUDED != 0) || (SCI_CFG_CH11_INCLUDED != 0) + #error "ERROR - Unsupported channel chosen in r_sci_config.h" +#endif + +/* Mask of all active channels */ +#define SCI_CFG_CH_INCLUDED_MASK ((SCI_CFG_CH0_INCLUDED << 0) | \ + (SCI_CFG_CH1_INCLUDED << 1) | \ + (SCI_CFG_CH5_INCLUDED << 5) | \ + (SCI_CFG_CH6_INCLUDED << 6) | \ + (SCI_CFG_CH8_INCLUDED << 8) | \ + (SCI_CFG_CH9_INCLUDED << 9) | \ + (SCI_CFG_CH12_INCLUDED << 12)) + +/* SCI SCR register masks */ +#define SCI_SCR_TEI_MASK (0x80U) /* transmit interrupt enable */ +#define SCI_SCR_REI_MASK (0x40U) /* receive interrupt enable */ +#define SCI_SCR_TE_MASK (0x20U) /* transmitter enable */ +#define SCI_SCR_RE_MASK (0x10U) /* receiver enable */ +#define SCI_EN_XCVR_MASK (SCI_SCR_RE_MASK | SCI_SCR_TE_MASK | SCI_SCR_REI_MASK | SCI_SCR_TEI_MASK) + +/* SCI SSR register receiver error masks */ +#define SCI_SSR_ORER_MASK (0x20U) /* overflow error */ +#define SCI_SSR_FER_MASK (0x10U) /* framing error */ +#define SCI_SSR_PER_MASK (0x08U) /* parity err */ +#define SCI_RCVR_ERR_MASK (SCI_SSR_ORER_MASK | SCI_SSR_FER_MASK | SCI_SSR_PER_MASK) +#define SCI_SSR_CLR_MASK (0xC0U) /* SSR register cleare mask (11000000b) */ + +/* Macros to enable and disable ICU interrupts */ +#define ENABLE_RXI_INT (R_BSP_BIT_SET(hdl->rom->icu_rxi, hdl->rom->rxi_bit_num)) +#define DISABLE_RXI_INT (R_BSP_BIT_CLEAR(hdl->rom->icu_rxi, hdl->rom->rxi_bit_num)) +#define ENABLE_TXI_INT (R_BSP_BIT_SET(hdl->rom->icu_txi, hdl->rom->txi_bit_num)) +#define DISABLE_TXI_INT (R_BSP_BIT_CLEAR(hdl->rom->icu_txi, hdl->rom->txi_bit_num)) + +#define ENABLE_ERI_INT (R_BSP_BIT_SET(hdl->rom->icu_eri, hdl->rom->eri_bit_num)) +#define DISABLE_ERI_INT (R_BSP_BIT_CLEAR(hdl->rom->icu_eri, hdl->rom->eri_bit_num)) +#define ENABLE_TEI_INT (R_BSP_BIT_SET(hdl->rom->icu_tei, hdl->rom->tei_bit_num)) +#define DISABLE_TEI_INT (R_BSP_BIT_CLEAR(hdl->rom->icu_tei, hdl->rom->tei_bit_num)) + +/***************************************************************************** +Typedef definitions +******************************************************************************/ + +typedef struct st_scif_fifo_ctrl +{ + uint8_t *p_tx_buf; /* user's buffer */ + uint8_t *p_rx_buf; /* user's buffer */ + uint16_t tx_cnt; /* bytes remaining to add to FIFO */ + uint16_t rx_cnt; /* bytes waiting to receive from FIFO */ +#if (TX_DTC_DMACA_ENABLE) || (RX_DTC_DMACA_ENABLE) + uint8_t *p_tx_fraction_buf; + uint8_t *p_rx_fraction_buf; + uint16_t tx_fraction; + uint16_t rx_fraction; +#endif + uint16_t total_length; /* used for DTC in txi_handler */ +} sci_fifo_ctrl_t; + +/* CHANNEL CONTROL BLOCK */ + +/* ROM INFO */ + +typedef struct st_sci_ch_rom /* SCI ROM info for channel control block */ +{ + volatile struct st_sci12 R_BSP_EVENACCESS_SFR *regs; /* base ptr to ch registers */ + volatile uint32_t R_BSP_EVENACCESS_SFR *mstp; /* ptr to mstp register */ + uint32_t stop_mask; /* mstp mask to disable ch */ + volatile uint8_t R_BSP_EVENACCESS_SFR *ipr; /* ptr to IPR register */ + volatile uint8_t R_BSP_EVENACCESS_SFR *ir_rxi; /* ptr to RXI IR register */ + volatile uint8_t R_BSP_EVENACCESS_SFR *ir_txi; /* ptr to TXI IR register */ + volatile uint8_t R_BSP_EVENACCESS_SFR *ir_tei; /* ptr to TEI IR register */ + volatile uint8_t R_BSP_EVENACCESS_SFR *ir_eri; /* ptr to ERI IR register */ + + /* + * DO NOT use the enable/disable interrupt bits in the SCR + * register. Pending interrupts can be lost that way. + */ + volatile uint8_t R_BSP_EVENACCESS_SFR *icu_rxi; /* ptr to ICU register */ + volatile uint8_t R_BSP_EVENACCESS_SFR *icu_txi; + volatile uint8_t R_BSP_EVENACCESS_SFR *icu_tei; + volatile uint8_t R_BSP_EVENACCESS_SFR *icu_eri; + uint8_t eri_bit_num; /* ICU enable/disable eri bit number */ + uint8_t rxi_bit_num; /* ICU enable/disable rxi bit number */ + uint8_t txi_bit_num; /* ICU enable/disable txi bit number */ + uint8_t tei_bit_num; /* ICU enable/disable tei bit number */ + + /* + * In case using DTC/DMAC + */ +#if ((TX_DTC_DMACA_ENABLE || RX_DTC_DMACA_ENABLE)) + uint8_t dtc_dmaca_tx_enable; + uint8_t dtc_dmaca_rx_enable; +#endif +#if ((TX_DTC_DMACA_ENABLE & 0x01) || (RX_DTC_DMACA_ENABLE & 0x01)) + dtc_activation_source_t dtc_tx_act_src; + dtc_activation_source_t dtc_rx_act_src; + uint8_t chan; /* Channel SCI is used*/ +#endif +} sci_ch_rom_t; + + +/* CHANNEL CONTROL BLOCK */ + +typedef struct st_sci_ch_ctrl /* SCI channel control (for handle) */ +{ + sci_ch_rom_t const *rom; /* pointer to rom info */ + sci_mode_t mode; /* operational mode */ + uint32_t baud_rate; /* baud rate */ + void (*callback)(void *p_args); /* function ptr for rcvr errs */ + union + { +#if (SCI_CFG_ASYNC_INCLUDED) + byteq_hdl_t que; /* async transmit queue handle */ +#endif + uint8_t *buf; /* sspi/sync tx buffer ptr */ + } u_tx_data; + union + { +#if (SCI_CFG_ASYNC_INCLUDED) + byteq_hdl_t que; /* async receive queue handle */ +#endif + uint8_t *buf; /* sspi/sync rx buffer ptr */ + } u_rx_data; + bool tx_idle; /* TDR is empty (async); TSR is empty (sync/sspi) */ +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) + bool save_rx_data; /* save the data that is clocked in */ + uint16_t tx_cnt; /* number of bytes to transmit */ + uint16_t rx_cnt; /* number of bytes to receive */ + bool tx_dummy; /* transmit dummy byte, not buffer */ +#endif + uint32_t pclk_speed; /* saved peripheral clock speed for break generation */ +#if ((TX_DTC_DMACA_ENABLE || RX_DTC_DMACA_ENABLE)) + bool rx_idle; + uint8_t qindex_app_tx; + uint8_t qindex_int_tx; + uint8_t qindex_app_rx; + uint8_t qindex_int_rx; + sci_fifo_ctrl_t queue[2]; +#endif +} sci_ch_ctrl_t; + + +/* BAUD DIVISOR INFO */ + +/* BRR = (PCLK/(divisor * baud)) - 1 */ +/* when: bgdm,abcs=11, divisor = 16*pow(2,2n-1) */ +/* bgdm,abcs=01, divisor = 32*pow(2,2n-1) */ +/* bgdm,abcs=10, divisor = 32*pow(2,2n-1) */ +/* bgdm,abcs=00, divisor = 64*pow(2,2n-1) */ + +typedef struct st_baud_divisor +{ + int16_t divisor; // clock divisor + uint8_t abcs; // abcs value to get divisor + uint8_t bgdm; // bdgm value to get divisor + uint8_t cks; // cks value to get divisor (cks = n) +} baud_divisor_t; + +#define NUM_DIVISORS_ASYNC (9) +#define NUM_DIVISORS_SYNC (4) + + +/***************************************************************************** +Private global variables and functions +******************************************************************************/ +#if (SCI_CFG_ASYNC_INCLUDED) +extern const baud_divisor_t async_baud[]; +#endif +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) +extern const baud_divisor_t sync_baud[]; +#endif + +#if (SCI_CFG_CH0_INCLUDED) +extern const sci_ch_rom_t ch0_rom; +extern sci_ch_ctrl_t ch0_ctrl; +#endif + +#if (SCI_CFG_CH1_INCLUDED) +extern const sci_ch_rom_t ch1_rom; +extern sci_ch_ctrl_t ch1_ctrl; +#endif + +#if (SCI_CFG_CH5_INCLUDED) +extern const sci_ch_rom_t ch5_rom; +extern sci_ch_ctrl_t ch5_ctrl; +#endif + +#if (SCI_CFG_CH6_INCLUDED) +extern const sci_ch_rom_t ch6_rom; +extern sci_ch_ctrl_t ch6_ctrl; +#endif + +#if (SCI_CFG_CH8_INCLUDED) +extern const sci_ch_rom_t ch8_rom; +extern sci_ch_ctrl_t ch8_ctrl; +#endif + +#if (SCI_CFG_CH9_INCLUDED) +extern const sci_ch_rom_t ch9_rom; +extern sci_ch_ctrl_t ch9_ctrl; +#endif + +#if (SCI_CFG_CH12_INCLUDED) +extern const sci_ch_rom_t ch12_rom; +extern sci_ch_ctrl_t ch12_ctrl; +#endif + +extern const sci_hdl_t g_sci_handles[]; + +extern void sci_init_register(sci_hdl_t const hdl); + +#if (SCI_CFG_ASYNC_INCLUDED) +extern sci_err_t sci_async_cmds(sci_hdl_t const hdl, + sci_cmd_t const cmd, + void *p_args); +#endif + +#if (SCI_CFG_SSPI_INCLUDED || SCI_CFG_SYNC_INCLUDED) +extern sci_err_t sci_sync_cmds(sci_hdl_t const hdl, + sci_cmd_t const cmd, + void *p_args); +#endif + +extern sci_err_t sci_mcu_param_check(uint8_t const chan); + +extern int32_t sci_init_bit_rate(sci_hdl_t const hdl, + uint32_t const pclk, + uint32_t const baud); + +extern void sci_initialize_ints(sci_hdl_t const hdl, + uint8_t const priority); + +extern void sci_disable_ints(sci_hdl_t const hdl); + +#endif /* SCI_RX130_H */ + diff --git a/zephyr/rx/rdp_cfg/r_config/r_byteq_config.h b/zephyr/rx/rdp_cfg/r_config/r_byteq_config.h new file mode 100644 index 00000000..f1be4466 --- /dev/null +++ b/zephyr/rx/rdp_cfg/r_config/r_byteq_config.h @@ -0,0 +1,68 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_byteq_config.h +* Description : Configures the byte queue memory allocation +************************************************************************************************************************ +* History : DD.MM.YYYY Version Description +* : 24.07.2013 1.00 Initial Release +* : 11.21.2014 1.20 Removed dependency to BSP +* : 30.09.2015 1.50 Added dependency to BSP +* : 01.06.2018 1.70 Changed the default value of the following macro definition. +* - BYTEQ_CFG_MAX_CTRL_BLKS - Changed the default value from 4 to 32. +* : 31.03.2021 1.90 Updated for queue protection. +* : 29.10.2021 2.00 Updated for critical section protection. +***********************************************************************************************************************/ +#ifndef BYTEQ_CONFIG_H +#define BYTEQ_CONFIG_H + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "platform.h" + +/*********************************************************************************************************************** +Configuration Options +***********************************************************************************************************************/ + +/* SPECIFY WHETHER TO INCLUDE CODE FOR API PARAMETER CHECKING + Available settings: + BSP_CFG_PARAM_CHECKING_ENABLE: + Utilizes the system default setting + 1: + Includes parameter checking + 0: + Compiles out parameter checking +*/ +#define BYTEQ_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +/* SPECIFY IF SHOULD USE MALLOC() TO ALLOCATE MEMORY FOR QUEUE CONTROL BLOCKS */ +#define BYTEQ_CFG_USE_HEAP_FOR_CTRL_BLKS (0) + +/* SPECIFY NUMBER OF STATIC QUEUE CONTROL BLOCKS TO SUPPORT */ +/* valid only when BYTEQ_USE_HEAP_FOR_CTRL_BLKS is set to 0 */ +#define BYTEQ_CFG_MAX_CTRL_BLKS (32) + +/* Selects to use disable interrupt to protect queue. */ +#define BYTEQ_CFG_PROTECT_QUEUE (0) + +/* Selects to use disable interrupt to protect critical section. */ +#define BYTEQ_CFG_CRITICAL_SECTION (0) + +#endif /* BYTEQ_CONFIG_H */ diff --git a/zephyr/rx/rdp_cfg/r_config/rx130/r_sci_rx_config.h b/zephyr/rx/rdp_cfg/r_config/rx130/r_sci_rx_config.h new file mode 100644 index 00000000..667762af --- /dev/null +++ b/zephyr/rx/rdp_cfg/r_config/rx130/r_sci_rx_config.h @@ -0,0 +1,383 @@ +/* Generated configuration header file - do not edit */ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013-2024 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_sci_rx_config.h +* Description : Configures the SCI driver +************************************************************************************************************************ +* History : DD.MM.YYYY Version Description +* 25.09.2013 1.00 Initial Release +* 17.04.2014 1.20 Added comments for new RX110 support. +* 02.07.2014 1.30 Fixed bug that caused Group12 rx errors to only be enabled for channel 2. +* 25.11.2014 1.40 Added comments for RX113 support +* 30.09.2015 1.70 Added comments for RX23T support +* 01.10.2016 1.80 Added support for RX65N (comments and TX/RX FIFO THRESHOLD options) +* 19.12.2016 1.90 Added comments for RX24U support +* 07.03.2017 2.00 Added comments for RX130-512KB support +* 28.09.2018 2.10 Added comments for RX66T support +* 01.02.2019 2.20 Added comments for RX72T, RX65N-64pin support +* Added support received data match function for RX65N +* 28.06.2019 3.10 Added comments for RX23W support +* 15.08.2019 3.20 Added support received data match function for RX72M (SCI0- SCI11) +* Added support FIFO mode for RX72M (SCI7 - SCI11) +* 25.11.2019 3.30 Added support RX13T. +* Removed support for Generation 1 devices. +* 30.12.2019 3.40 Added support RX66N, RX72N. +* 31.03.2020 3.50 Added support RX23E-A. +* 25.08.2020 3.60 Added feature using DTC/DMAC in SCI transfer. +* Merged IrDA functionality to SCI FIT. +* 31.03.2021 3.80 Added support for RX671. +* Added support circular buffer in mode asynchronous. +* 15.04.2021 3.90 Added support for RX140. +* 31.03.2022 4.40 Added support for RX660. +* 27.12.2022 4.60 Updated macro definition enable and disable nested interrupt for TXI, RXI, ERI, TEI. +* 31.03.2023 4.80 Added support for RX26T. +* Fixed to comply with GSCE Coding Standards Rev.6.5.0. +* 29.05.2023 4.90 Added support for RX23E-B. +* 31.01.2024 5.10 Modified comments in Data Match parameters. +***********************************************************************************************************************/ +#ifndef SCI_CONFIG_H +#define SCI_CONFIG_H + +#include +#include "platform.h" + +/*********************************************************************************************************************** +Configuration Options +***********************************************************************************************************************/ + +/* SPECIFY WHETHER TO INCLUDE CODE FOR API PARAMETER CHECKING */ +/* Setting to BSP_CFG_PARAM_CHECKING_ENABLE utilizes the system default setting */ +/* Setting to 1 includes parameter checking; 0 compiles out parameter checking */ +#define SCI_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +/* SPECIFY WHETHER TO INCLUDE CODE FOR DIFFERENT SCI MODES */ +/* Setting an equate to 1 includes code specific to that mode. */ +#define SCI_CFG_ASYNC_INCLUDED (CONFIG_USE_RX_RDP_SCI_UART) +#define SCI_CFG_SYNC_INCLUDED (0) +#define SCI_CFG_SSPI_INCLUDED (0) +#define SCI_CFG_IRDA_INCLUDED (0) + +/* Use circular buffer in mode asynchronous */ +/* 1=Use , 0=Unused */ +/* When SCI_CFG_USE_CIRCULAR is 1, please set BSP_CFG_RUN_IN_USER_MODE = 0 and BYTEQ_CFG_PROTECT_QUEUE = 1*/ +#define SCI_CFG_USE_CIRCULAR_BUFFER (0) + +/* SPECIFY BYTE VALUE TO TRANSMIT WHILE CLOCKING IN DATA IN SSPI MODES */ +#define SCI_CFG_DUMMY_TX_BYTE (0xFF) + +/* SPECIFY CHANNELS TO INCLUDE SOFTWARE SUPPORT FOR 1=included, 0=not */ +/* + * NOTE: If using ASYNC mode, adjust BYTEQ_CFG_MAX_CTRL_BLKS in r_byteq_config.h + * to provide 2 queues per channel (static mode only). + * * = port connector RSKRX11x + * u = channel used by the USB-UART port (G1CUSB0) + * a = this channel is used only for RX130-512KB + * n = this channel is not available for RX65N-64pin. + * s = this channel is not available in simple SPI mode. + * i = this channel is available in IrDA interface. + * RX MCU supported channels + * + * CH# 110 111 113 130 140 230 231 23T 24T 24U 64M 71M 65N 66T 72T 23W 72M 13T 72N 66N 23E-A 671 660 26T 23E-B + * --- --- --- --- --- --- --- ----- --- --- --- --- --- --- --- --- --- --- --- --- --- ----- --- --- --- ----- + * CH0 X Xa X X X X Xn X X X X X X + * CH1 X X* X* Xu X X X Xu Xu Xu X X Xs X X X X X X X Xu X X X X + * CH2 X X X Xu X X X X X + * CH3 X X Xs X X X X X + * CH4 X X Xn X X X X X + * CH5 X X Xi X X Xi Xu,i X X X X X X X X Xi X X X X X X X X X + * CH6 X X X X X X X X X Xn X X Xu X X X X X X X + * CH7 Xu Xu Xn X X X X X + * CH8 X Xa X X X X X X X Xu X X X X X X + * CH9 X Xa X X X X Xs X X X X X X X X + * CH10 X X X X X X + * CH11 X Xs X X X X X X X + * CH12 X X X X X X X X X Xs X X X X X X X X X X X X +*/ + +#define SCI_CFG_CH0_INCLUDED (DT_NODE_HAS_STATUS(DT_NODELABEL(sci0), okay)) +#define SCI_CFG_CH1_INCLUDED (DT_NODE_HAS_STATUS(DT_NODELABEL(sci1), okay)) +#define SCI_CFG_CH2_INCLUDED (0) +#define SCI_CFG_CH3_INCLUDED (0) +#define SCI_CFG_CH4_INCLUDED (0) +#define SCI_CFG_CH5_INCLUDED (DT_NODE_HAS_STATUS(DT_NODELABEL(sci5), okay)) +#define SCI_CFG_CH6_INCLUDED (DT_NODE_HAS_STATUS(DT_NODELABEL(sci6), okay)) +#define SCI_CFG_CH7_INCLUDED (0) +#define SCI_CFG_CH8_INCLUDED (DT_NODE_HAS_STATUS(DT_NODELABEL(sci8), okay)) +#define SCI_CFG_CH9_INCLUDED (DT_NODE_HAS_STATUS(DT_NODELABEL(sci9), okay)) +#define SCI_CFG_CH10_INCLUDED (0) +#define SCI_CFG_CH11_INCLUDED (0) +#define SCI_CFG_CH12_INCLUDED (0) + +/* SPECIFY WHETHER TO INCLUDE CODE FOR NESTED INTERRUPT TXI */ +/* 1=included, 0=not */ +#define SCI_CFG_CH0_EN_TXI_NESTED_INT (0) +#define SCI_CFG_CH1_EN_TXI_NESTED_INT (0) +#define SCI_CFG_CH2_EN_TXI_NESTED_INT (0) +#define SCI_CFG_CH3_EN_TXI_NESTED_INT (0) +#define SCI_CFG_CH4_EN_TXI_NESTED_INT (0) +#define SCI_CFG_CH5_EN_TXI_NESTED_INT (0) +#define SCI_CFG_CH6_EN_TXI_NESTED_INT (0) +#define SCI_CFG_CH7_EN_TXI_NESTED_INT (0) +#define SCI_CFG_CH8_EN_TXI_NESTED_INT (0) +#define SCI_CFG_CH9_EN_TXI_NESTED_INT (0) +#define SCI_CFG_CH10_EN_TXI_NESTED_INT (0) +#define SCI_CFG_CH11_EN_TXI_NESTED_INT (0) +#define SCI_CFG_CH12_EN_TXI_NESTED_INT (0) + +/* SPECIFY WHETHER TO INCLUDE CODE FOR NESTED INTERRUPT RXI */ +/* 1=included, 0=not */ +#define SCI_CFG_CH0_EN_RXI_NESTED_INT (0) +#define SCI_CFG_CH1_EN_RXI_NESTED_INT (0) +#define SCI_CFG_CH2_EN_RXI_NESTED_INT (0) +#define SCI_CFG_CH3_EN_RXI_NESTED_INT (0) +#define SCI_CFG_CH4_EN_RXI_NESTED_INT (0) +#define SCI_CFG_CH5_EN_RXI_NESTED_INT (0) +#define SCI_CFG_CH6_EN_RXI_NESTED_INT (0) +#define SCI_CFG_CH7_EN_RXI_NESTED_INT (0) +#define SCI_CFG_CH8_EN_RXI_NESTED_INT (0) +#define SCI_CFG_CH9_EN_RXI_NESTED_INT (0) +#define SCI_CFG_CH10_EN_RXI_NESTED_INT (0) +#define SCI_CFG_CH11_EN_RXI_NESTED_INT (0) +#define SCI_CFG_CH12_EN_RXI_NESTED_INT (0) + +/* SPECIFY WHETHER TO INCLUDE CODE FOR NESTED INTERRUPT TEI */ +/* 1=included, 0=not */ +#define SCI_CFG_CH0_EN_TEI_NESTED_INT (0) +#define SCI_CFG_CH1_EN_TEI_NESTED_INT (0) +#define SCI_CFG_CH2_EN_TEI_NESTED_INT (0) +#define SCI_CFG_CH3_EN_TEI_NESTED_INT (0) +#define SCI_CFG_CH4_EN_TEI_NESTED_INT (0) +#define SCI_CFG_CH5_EN_TEI_NESTED_INT (0) +#define SCI_CFG_CH6_EN_TEI_NESTED_INT (0) +#define SCI_CFG_CH7_EN_TEI_NESTED_INT (0) +#define SCI_CFG_CH8_EN_TEI_NESTED_INT (0) +#define SCI_CFG_CH9_EN_TEI_NESTED_INT (0) +#define SCI_CFG_CH10_EN_TEI_NESTED_INT (0) +#define SCI_CFG_CH11_EN_TEI_NESTED_INT (0) +#define SCI_CFG_CH12_EN_TEI_NESTED_INT (0) + +/* SPECIFY WHETHER TO INCLUDE CODE FOR NESTED INTERRUPT ERI */ +/* 1=included, 0=not */ +#define SCI_CFG_CH0_EN_ERI_NESTED_INT (0) +#define SCI_CFG_CH1_EN_ERI_NESTED_INT (0) +#define SCI_CFG_CH2_EN_ERI_NESTED_INT (0) +#define SCI_CFG_CH3_EN_ERI_NESTED_INT (0) +#define SCI_CFG_CH4_EN_ERI_NESTED_INT (0) +#define SCI_CFG_CH5_EN_ERI_NESTED_INT (0) +#define SCI_CFG_CH6_EN_ERI_NESTED_INT (0) +#define SCI_CFG_CH7_EN_ERI_NESTED_INT (0) +#define SCI_CFG_CH8_EN_ERI_NESTED_INT (0) +#define SCI_CFG_CH9_EN_ERI_NESTED_INT (0) +#define SCI_CFG_CH10_EN_ERI_NESTED_INT (0) +#define SCI_CFG_CH11_EN_ERI_NESTED_INT (0) +#define SCI_CFG_CH12_EN_ERI_NESTED_INT (0) + +/* SPECIFY ASYNC MODE TX QUEUE BUFFER SIZES (will not allocate if chan not enabled */ +#define SCI_CFG_CH0_TX_BUFSIZ (80) +#define SCI_CFG_CH1_TX_BUFSIZ (80) +#define SCI_CFG_CH2_TX_BUFSIZ (80) +#define SCI_CFG_CH3_TX_BUFSIZ (80) +#define SCI_CFG_CH4_TX_BUFSIZ (80) +#define SCI_CFG_CH5_TX_BUFSIZ (80) +#define SCI_CFG_CH6_TX_BUFSIZ (80) +#define SCI_CFG_CH7_TX_BUFSIZ (80) +#define SCI_CFG_CH8_TX_BUFSIZ (80) +#define SCI_CFG_CH9_TX_BUFSIZ (80) +#define SCI_CFG_CH10_TX_BUFSIZ (80) +#define SCI_CFG_CH11_TX_BUFSIZ (80) +#define SCI_CFG_CH12_TX_BUFSIZ (80) + +/* SPECIFY ASYNC MODE RX QUEUE BUFFER SIZES (will not allocate if chan not enabled */ +#define SCI_CFG_CH0_RX_BUFSIZ (80) +#define SCI_CFG_CH1_RX_BUFSIZ (80) +#define SCI_CFG_CH2_RX_BUFSIZ (80) +#define SCI_CFG_CH3_RX_BUFSIZ (80) +#define SCI_CFG_CH4_RX_BUFSIZ (80) +#define SCI_CFG_CH5_RX_BUFSIZ (80) +#define SCI_CFG_CH6_RX_BUFSIZ (80) +#define SCI_CFG_CH7_RX_BUFSIZ (80) +#define SCI_CFG_CH8_RX_BUFSIZ (80) +#define SCI_CFG_CH9_RX_BUFSIZ (80) +#define SCI_CFG_CH10_RX_BUFSIZ (80) +#define SCI_CFG_CH11_RX_BUFSIZ (80) +#define SCI_CFG_CH12_RX_BUFSIZ (80) + +/* +* ENABLE TRANSMIT END INTERRUPT (ASYNCHRONOUS) +* This interrupt only occurs when the last bit of the last byte of data +* has been sent and the transmitter has become idle. The interrupt calls +* the user's callback function specified in R_SCI_Open() and passes it an +* SCI_EVT_TEI event. A typical use of this feature is to disable an external +* transceiver to save power. It would then be up to the user's code to +* re-enable the transceiver before sending again. Not including this feature +* reduces code space used by the interrupt. Note that this equate is only +* for including the TEI code. The interrupt itself must be enabled using an +* R_SCI_Control(hdl, SCI_CMD_EN_TEI, NULL) call. +*/ +#define SCI_CFG_TEI_INCLUDED (CONFIG_USE_RX_RDP_SCI_UART) /* 1=included, 0=not */ + +/* +* SET GROUPBL0 (ERI, TEI) INTERRUPT PRIORITY; RX64M/RX71M/RX65N/RX72M/RX72N/RX66N/RX671/RX660/RX26T ONLY +* SET GROUPBL1; RX65N ONLY +* SET GROUPAL0 (ERI,TEI) INTERRUPT PRIORITY; RX65N, RX72M, RX72N, RX66N ONLY +* This sets the priority level for receiver overrun, framing, and parity errors +* as well as TEI interrupts for all SCI channels. +*/ +/* (RX64M/RX71M/RX65N/RX72M/RX72N/RX66N/RX671/RX660/RX26T ONLY) 1 lowest, 15 highest */ +#define SCI_CFG_ERI_TEI_PRIORITY (3) + +/* ENABLE TX/RX FIFO; (SCIi supported MCU ONLY) 1=included, 0=not */ +#define SCI_CFG_CH7_FIFO_INCLUDED (0) +#define SCI_CFG_CH8_FIFO_INCLUDED (0) +#define SCI_CFG_CH9_FIFO_INCLUDED (0) +#define SCI_CFG_CH10_FIFO_INCLUDED (0) +#define SCI_CFG_CH11_FIFO_INCLUDED (0) + +/* SET TX FIFO THRESHOLD; (SCIi supported MCU ONLY) 0 lowest, 15 highest */ +/* TX FIFO THRESHOLD is invalid in Clock Synchronous Mode and Simple SPI Mode. */ +/* Set the same value for TX FIFO THRESHOLD and RX FIFO THRESHOLD in Clock Synchronous Mode and Simple SPI Mode. */ +#define SCI_CFG_CH7_TX_FIFO_THRESH (8) +#define SCI_CFG_CH8_TX_FIFO_THRESH (8) +#define SCI_CFG_CH9_TX_FIFO_THRESH (8) +#define SCI_CFG_CH10_TX_FIFO_THRESH (8) +#define SCI_CFG_CH11_TX_FIFO_THRESH (8) + +/* SET RX FIFO THRESHOLD; (SCIi supported MCU ONLY) 1 lowest, 15 highest */ +#define SCI_CFG_CH7_RX_FIFO_THRESH (8) +#define SCI_CFG_CH8_RX_FIFO_THRESH (8) +#define SCI_CFG_CH9_RX_FIFO_THRESH (8) +#define SCI_CFG_CH10_RX_FIFO_THRESH (8) +#define SCI_CFG_CH11_RX_FIFO_THRESH (8) + +/* ENABLE Received Data match function (SCIj supported MCU RX66T/RX72T/RX72M/RX72N/RX66N ONLY) 1=included, 0=not */ +/*(SCIi supported MCU RX65N/RX66T/RX72T/RX72M/RX72N/RX66N ONLY) 1=included, 0=not */ +/*(SCIk supported MCU RX671/RX660/RX140/RX26T ONLY) 1=included, 0=not */ +/*(SCIm supported MCU RX671/RX660 ONLY) 1=included, 0=not */ +#define SCI_CFG_CH0_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_CH1_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_CH2_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_CH3_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_CH4_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_CH5_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_CH6_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_CH7_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_CH8_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_CH9_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_CH10_DATA_MATCH_INCLUDED (0) +#define SCI_CFG_CH11_DATA_MATCH_INCLUDED (0) + +/* 0=Disable, 1=DTC, 2=DMAC */ +#define SCI_CFG_CH0_TX_DTC_DMACA_ENABLE (0) +#define SCI_CFG_CH1_TX_DTC_DMACA_ENABLE (0) +#define SCI_CFG_CH2_TX_DTC_DMACA_ENABLE (0) +#define SCI_CFG_CH3_TX_DTC_DMACA_ENABLE (0) +#define SCI_CFG_CH4_TX_DTC_DMACA_ENABLE (0) +#define SCI_CFG_CH5_TX_DTC_DMACA_ENABLE (0) +#define SCI_CFG_CH6_TX_DTC_DMACA_ENABLE (0) +#define SCI_CFG_CH7_TX_DTC_DMACA_ENABLE (0) +#define SCI_CFG_CH8_TX_DTC_DMACA_ENABLE (0) +#define SCI_CFG_CH9_TX_DTC_DMACA_ENABLE (0) +#define SCI_CFG_CH10_TX_DTC_DMACA_ENABLE (0) +#define SCI_CFG_CH11_TX_DTC_DMACA_ENABLE (0) +#define SCI_CFG_CH12_TX_DTC_DMACA_ENABLE (0) + +#define SCI_CFG_CH0_RX_DTC_DMACA_ENABLE (0) +#define SCI_CFG_CH1_RX_DTC_DMACA_ENABLE (0) +#define SCI_CFG_CH2_RX_DTC_DMACA_ENABLE (0) +#define SCI_CFG_CH3_RX_DTC_DMACA_ENABLE (0) +#define SCI_CFG_CH4_RX_DTC_DMACA_ENABLE (0) +#define SCI_CFG_CH5_RX_DTC_DMACA_ENABLE (0) +#define SCI_CFG_CH6_RX_DTC_DMACA_ENABLE (0) +#define SCI_CFG_CH7_RX_DTC_DMACA_ENABLE (0) +#define SCI_CFG_CH8_RX_DTC_DMACA_ENABLE (0) +#define SCI_CFG_CH9_RX_DTC_DMACA_ENABLE (0) +#define SCI_CFG_CH10_RX_DTC_DMACA_ENABLE (0) +#define SCI_CFG_CH11_RX_DTC_DMACA_ENABLE (0) +#define SCI_CFG_CH12_RX_DTC_DMACA_ENABLE (0) + +/* 0~7 8 channels dmac, but maximum of SCI channel is 13 channel => cost 13*2 = 26 dmac channels in case all of sci channels run simultaneously */ +#define SCI_CFG_CH0_TX_DMACA_CH_NUM (0) +#define SCI_CFG_CH1_TX_DMACA_CH_NUM (0) +#define SCI_CFG_CH2_TX_DMACA_CH_NUM (0) +#define SCI_CFG_CH3_TX_DMACA_CH_NUM (0) +#define SCI_CFG_CH4_TX_DMACA_CH_NUM (0) +#define SCI_CFG_CH5_TX_DMACA_CH_NUM (0) +#define SCI_CFG_CH6_TX_DMACA_CH_NUM (0) +#define SCI_CFG_CH7_TX_DMACA_CH_NUM (0) +#define SCI_CFG_CH8_TX_DMACA_CH_NUM (0) +#define SCI_CFG_CH9_TX_DMACA_CH_NUM (0) +#define SCI_CFG_CH10_TX_DMACA_CH_NUM (0) +#define SCI_CFG_CH11_TX_DMACA_CH_NUM (0) +#define SCI_CFG_CH12_TX_DMACA_CH_NUM (0) + +#define SCI_CFG_CH0_RX_DMACA_CH_NUM (1) +#define SCI_CFG_CH1_RX_DMACA_CH_NUM (1) +#define SCI_CFG_CH2_RX_DMACA_CH_NUM (1) +#define SCI_CFG_CH3_RX_DMACA_CH_NUM (1) +#define SCI_CFG_CH4_RX_DMACA_CH_NUM (1) +#define SCI_CFG_CH5_RX_DMACA_CH_NUM (1) +#define SCI_CFG_CH6_RX_DMACA_CH_NUM (1) +#define SCI_CFG_CH7_RX_DMACA_CH_NUM (1) +#define SCI_CFG_CH8_RX_DMACA_CH_NUM (1) +#define SCI_CFG_CH9_RX_DMACA_CH_NUM (1) +#define SCI_CFG_CH10_RX_DMACA_CH_NUM (1) +#define SCI_CFG_CH11_RX_DMACA_CH_NUM (1) +#define SCI_CFG_CH12_RX_DMACA_CH_NUM (1) + +/* Set enable/ disable transmit signal transition timing adjust feature for each channel*/ +#define SCI_CFG_CH0_TX_SIGNAL_TRANSITION_TIMING_INCLUDED (0) +#define SCI_CFG_CH1_TX_SIGNAL_TRANSITION_TIMING_INCLUDED (0) +#define SCI_CFG_CH2_TX_SIGNAL_TRANSITION_TIMING_INCLUDED (0) +#define SCI_CFG_CH3_TX_SIGNAL_TRANSITION_TIMING_INCLUDED (0) +#define SCI_CFG_CH4_TX_SIGNAL_TRANSITION_TIMING_INCLUDED (0) +#define SCI_CFG_CH5_TX_SIGNAL_TRANSITION_TIMING_INCLUDED (0) +#define SCI_CFG_CH6_TX_SIGNAL_TRANSITION_TIMING_INCLUDED (0) +#define SCI_CFG_CH7_TX_SIGNAL_TRANSITION_TIMING_INCLUDED (0) +#define SCI_CFG_CH8_TX_SIGNAL_TRANSITION_TIMING_INCLUDED (0) +#define SCI_CFG_CH9_TX_SIGNAL_TRANSITION_TIMING_INCLUDED (0) +#define SCI_CFG_CH10_TX_SIGNAL_TRANSITION_TIMING_INCLUDED (0) +#define SCI_CFG_CH11_TX_SIGNAL_TRANSITION_TIMING_INCLUDED (0) + +/* Set enable/ disable receive data sampling timing adjust feature for each channel*/ +#define SCI_CFG_CH0_RX_DATA_SAMPLING_TIMING_INCLUDED (0) +#define SCI_CFG_CH1_RX_DATA_SAMPLING_TIMING_INCLUDED (0) +#define SCI_CFG_CH2_RX_DATA_SAMPLING_TIMING_INCLUDED (0) +#define SCI_CFG_CH3_RX_DATA_SAMPLING_TIMING_INCLUDED (0) +#define SCI_CFG_CH4_RX_DATA_SAMPLING_TIMING_INCLUDED (0) +#define SCI_CFG_CH5_RX_DATA_SAMPLING_TIMING_INCLUDED (0) +#define SCI_CFG_CH6_RX_DATA_SAMPLING_TIMING_INCLUDED (0) +#define SCI_CFG_CH7_RX_DATA_SAMPLING_TIMING_INCLUDED (0) +#define SCI_CFG_CH8_RX_DATA_SAMPLING_TIMING_INCLUDED (0) +#define SCI_CFG_CH9_RX_DATA_SAMPLING_TIMING_INCLUDED (0) +#define SCI_CFG_CH10_RX_DATA_SAMPLING_TIMING_INCLUDED (0) +#define SCI_CFG_CH11_RX_DATA_SAMPLING_TIMING_INCLUDED (0) + +/* SPECIFY IRDA CHANNELS TO INCLUDE SOFTWARE (SUPPORTED MCU RX113/RX23W/RX231/RX230 ONLY) 1=included, 0=not */ +#define SCI_CFG_CH5_IRDA_INCLUDED (0) + +/* Set the non-active level of the TXD pin */ +/* 1=High , 0=Low */ +#define SCI_CFG_CH5_IRDA_IRTXD_INACTIVE_LEVEL (1) + +/* Set the non-active level of the RXD pin */ +/* 1=High , 0=Low */ +#define SCI_CFG_CH5_IRDA_IRRXD_INACTIVE_LEVEL (1) + +#endif /* SCI_CONFIG_H */ From 20840c18180424694cafcee61bab7b67d48bb52b Mon Sep 17 00:00:00 2001 From: Tran Van Quy Date: Fri, 4 Oct 2024 15:52:47 +0700 Subject: [PATCH 5/9] hal: renesas: Update PLL multiple config for RX130 This update is to update marco of PLL multiple to adapt the change Signed-off-by: Tran Van Quy --- zephyr/rx/rdp_cfg/r_config/rx130/r_bsp_config.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/zephyr/rx/rdp_cfg/r_config/rx130/r_bsp_config.h b/zephyr/rx/rdp_cfg/r_config/rx130/r_bsp_config.h index c0571640..044048e0 100644 --- a/zephyr/rx/rdp_cfg/r_config/rx130/r_bsp_config.h +++ b/zephyr/rx/rdp_cfg/r_config/rx130/r_bsp_config.h @@ -357,8 +357,7 @@ Configuration Options Available multipliers = x4, x4.5, x5, x5.5, x6, x6.5, x7, x7.5, x8 */ -#define BSP_CFG_PLL_MUL ((DT_PROP_BY_IDX(DT_NODELABEL(pll), mul, 0)) + \ - ((DT_PROP_BY_IDX(DT_NODELABEL(pll), mul, 1)) / (10.0))) +#define BSP_CFG_PLL_MUL (RX_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll), mul, 15) + 1) / (2.0) /* System Clock Divider (ICK). Available divisors = /1 (no division), /2, /4, /8, /16, /32, /64 From eeaa15396979fe40a8634636e1f8f7817246a6b3 Mon Sep 17 00:00:00 2001 From: Tran Van Quy Date: Thu, 10 Oct 2024 14:20:20 +0700 Subject: [PATCH 6/9] hal: renesas: Update bsp config for Renesas RX Update BSP configurations for Renesas RX Signed-off-by: Tran Van Quy --- zephyr/rx/rdp_cfg/r_config/rx130/r_bsp_config.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/zephyr/rx/rdp_cfg/r_config/rx130/r_bsp_config.h b/zephyr/rx/rdp_cfg/r_config/rx130/r_bsp_config.h index 044048e0..18897ad3 100644 --- a/zephyr/rx/rdp_cfg/r_config/rx130/r_bsp_config.h +++ b/zephyr/rx/rdp_cfg/r_config/rx130/r_bsp_config.h @@ -296,7 +296,7 @@ Configuration Options 1 = IWDT 2 = LPT non use */ -#define BSP_CFG_LPT_CLOCK_SOURCE RX_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(lptclk), mosel, 2) +#define BSP_CFG_LPT_CLOCK_SOURCE RX_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(lptclk), lpt_clk, 2) /* Main clock Oscillator Switching (MOSEL). 0 = Resonator @@ -433,7 +433,7 @@ Configuration Options /* Sub-Clock Oscillator Wait Time (Use R_BSP_SoftwareDelay). Setting delay unit is in milliseconds. */ -#define BSP_CFG_SOSC_WAIT_TIME (1482) +#define BSP_CFG_SOSC_WAIT_TIME RX_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(subclk), sub_clk_osc, 500) /* Configure IWDT settings. OFS0 - Option Function Select Register 0 From 227ec4a3ed3e605f805907812db0c31cba2ab759 Mon Sep 17 00:00:00 2001 From: Keita Kashima Date: Fri, 1 Nov 2024 09:46:13 +0000 Subject: [PATCH 7/9] hal: renesas: rx : Add the mcu_locks.c file to initialize the lock status variables Update CMakelists file to add mcu_locks.c for SOC early intialization Signed-off-by: Keita Kashima --- drivers/rx/CMakeLists.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/rx/CMakeLists.txt b/drivers/rx/CMakeLists.txt index 7efd678b..a5f45786 100644 --- a/drivers/rx/CMakeLists.txt +++ b/drivers/rx/CMakeLists.txt @@ -18,6 +18,7 @@ set(srcs rdp/src/r_bsp/mcu/all/r_bsp_interrupts.c rdp/src/r_bsp/mcu/all/r_bsp_software_interrupt.c rdp/src/r_bsp/mcu/all/r_rx_intrinsic_functions.c + rdp/src/r_bsp/mcu/all/mcu_locks.c rdp/src/r_bsp/mcu/${CONFIG_SOC_SERIES}/mcu_clocks.c rdp/src/r_bsp/mcu/${CONFIG_SOC_SERIES}/mcu_init.c rdp/src/r_bsp/mcu/${CONFIG_SOC_SERIES}/mcu_interrupts.c From 070a08d3f34adb55aa4a421caba51d33403bc0e3 Mon Sep 17 00:00:00 2001 From: Tran Van Quy Date: Tue, 12 Nov 2024 14:01:04 +0700 Subject: [PATCH 8/9] hal: renesas: rx: Add LICENSE file for Renesas RX HAL Add LICENSE file for Renesas RX HAL Signed-off-by: Tran Van Quy --- drivers/rx/LICENSE | 21 +++++++++++++++++++++ drivers/rx/README | 14 ++++++++++---- 2 files changed, 31 insertions(+), 4 deletions(-) create mode 100644 drivers/rx/LICENSE diff --git a/drivers/rx/LICENSE b/drivers/rx/LICENSE new file mode 100644 index 00000000..d2ef8985 --- /dev/null +++ b/drivers/rx/LICENSE @@ -0,0 +1,21 @@ +MIT License + +Copyright (c) 2021 Renesas Electronics Corporation: RX MCUs team + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all +copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +SOFTWARE. diff --git a/drivers/rx/README b/drivers/rx/README index b05e2d7e..a3761491 100644 --- a/drivers/rx/README +++ b/drivers/rx/README @@ -12,11 +12,11 @@ Purpose: Firmware Integration Technology (FIT) for Renesas RX MCU Family. Description: - This package is a snapshot from the RX FSP software released by Renesas Electronics Corporation + This package is a snapshot from the RX FIT software released by Renesas Electronics Corporation It contain the HAL and a set of CMSIS headers files for the Renesas RX MCUs Dependencies: - None. + None. URL: https://github.com/renesas/rx-driver-package @@ -28,7 +28,13 @@ Maintained-by: Renesas Electronics Corporation License: - BSD-3-Clause + These software: + - can be used for any users. + - can be re-distributed by any users. (excluding r_emwin_rx) + - can be integrated with specified open source code. + - Amazon FreeRTOS has been now allowed, Renesas would accept other open source. + - use condition is basically MIT License, and details are shown in PDF file in FIT Modules directory. + - are generated by SmartConfigurator as well, the generated code (each FIT Modules and Code Generator parts) license is same as previous link. License Link: - https://opensource.org/licenses/BSD-3-Clause + https://github.com/renesas/rx-driver-package/blob/master/LICENSE From 197eb8cca184d3324bb7bc451c256bf3b85bec1e Mon Sep 17 00:00:00 2001 From: Tran Van Quy Date: Thu, 14 Nov 2024 16:43:43 +0700 Subject: [PATCH 9/9] hal: renesas: rx: update CMakeLists file for RX HAL Update CMakeLists file for RX HAL to remove duplicate dirs Signed-off-by: Tran Van Quy --- drivers/rx/CMakeLists.txt | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/rx/CMakeLists.txt b/drivers/rx/CMakeLists.txt index a5f45786..95fee9d0 100644 --- a/drivers/rx/CMakeLists.txt +++ b/drivers/rx/CMakeLists.txt @@ -1,9 +1,7 @@ # SPDX-License-Identifier: Apache-2.0 set(include_dirs - rdp_cfg rdp/src/r_bsp - rdp_cfg/r_config rdp/src/r_bsp/mcu rdp/src/r_bsp/mcu/all rdp/src/r_bsp/board