From 546c255abdcab50e281efe2d5f466f077e17cf99 Mon Sep 17 00:00:00 2001
From: zifeihan <caogui@iscas.ac.cn>
Date: Mon, 20 May 2024 23:08:18 +0800
Subject: [PATCH] 8332533: RISC-V: Enable
 Matcher::supports_vector_variable_shifts with UseRVV

---
 src/hotspot/cpu/riscv/matcher_riscv.hpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/hotspot/cpu/riscv/matcher_riscv.hpp b/src/hotspot/cpu/riscv/matcher_riscv.hpp
index 32665f5922cf5..deb2af1c82422 100644
--- a/src/hotspot/cpu/riscv/matcher_riscv.hpp
+++ b/src/hotspot/cpu/riscv/matcher_riscv.hpp
@@ -129,7 +129,7 @@
 
   // Does the CPU supports vector variable shift instructions?
   static constexpr bool supports_vector_variable_shifts(void) {
-    return false;
+    return UseRVV;
   }
 
   // Does target support predicated operation emulation.