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all: rename riscv to riscv64
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This follows the MIPS model where cmd/internal/obj/riscv retains the riscv name.
Everything that is riscv64 specific gets named appropriately.
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4a6f656c committed May 9, 2019
1 parent e4b74ec commit 534b254
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Showing 83 changed files with 1,785 additions and 9,264 deletions.
4 changes: 2 additions & 2 deletions riscvtest/run.go
Original file line number Diff line number Diff line change
Expand Up @@ -64,7 +64,7 @@ func main() {
}

cmd := exec.Command("go", "install", "os")
cmd.Env = append(os.Environ(), "GOOS=linux", "GOARCH=riscv")
cmd.Env = append(os.Environ(), "GOOS=linux", "GOARCH=riscv64")
out, err := cmd.CombinedOutput()
if err != nil {
log.Printf("runtime precompilation failed:\n%s\n", out)
Expand All @@ -76,7 +76,7 @@ func main() {
for _, test := range tests {
// build
cmd := exec.Command("go", "build", "-o", tmp)
cmd.Env = append(os.Environ(), "GOOS=linux", "GOARCH=riscv")
cmd.Env = append(os.Environ(), "GOOS=linux", "GOARCH=riscv64")
if test.dir {
// Build everything in directory.
cmd.Dir = filepath.Join(cwd, test.name)
Expand Down
8 changes: 4 additions & 4 deletions src/cmd/asm/internal/arch/arch.go
Original file line number Diff line number Diff line change
Expand Up @@ -86,8 +86,8 @@ func Set(GOARCH string) *Arch {
a := archPPC64()
a.LinkArch = &ppc64.Linkppc64le
return a
case "riscv":
return archRiscv()
case "riscv64":
return archRISCV64()
case "s390x":
a := archS390x()
a.LinkArch = &s390x.Links390x
Expand Down Expand Up @@ -552,14 +552,14 @@ var riscvJumps = map[string]bool{
"JMP": true,
}

func archRiscv() *Arch {
func archRISCV64() *Arch {
// Pseudo-registers.
riscv.Registers["SB"] = RSB
riscv.Registers["FP"] = RFP
riscv.Registers["PC"] = RPC

return &Arch{
LinkArch: &riscv.LinkRISCV,
LinkArch: &riscv.LinkRISCV64,
Instructions: riscv.Instructions,
Register: riscv.Registers,
RegisterPrefix: nil,
Expand Down
4 changes: 2 additions & 2 deletions src/cmd/asm/internal/asm/asm.go
Original file line number Diff line number Diff line change
Expand Up @@ -411,7 +411,7 @@ func (p *Parser) asmJump(op obj.As, cond string, a []obj.Addr) {
prog.Reg = p.getRegister(prog, op, &a[1])
break
}
if p.arch.Family == sys.RISCV {
if p.arch.Family == sys.RISCV64 {
// 3-operand jumps.
// First two must be registers
target = &a[2]
Expand Down Expand Up @@ -658,7 +658,7 @@ func (p *Parser) asmInstruction(op obj.As, cond string, a []obj.Addr) {
p.errorf("invalid addressing modes for %s instruction", op)
return
}
case sys.RISCV:
case sys.RISCV64:
prog.From = a[0]
prog.SetFrom3(*newAddr(a[1]))
prog.To = a[2]
Expand Down
4 changes: 2 additions & 2 deletions src/cmd/asm/internal/asm/endtoend_test.go
Original file line number Diff line number Diff line change
Expand Up @@ -442,8 +442,8 @@ func TestPPC64Encoder(t *testing.T) {
}

func TestRISCVEncoder(t *testing.T) {
testEndToEnd(t, "riscv", "riscvenc")
testEndToEnd(t, "riscv", "riscvfarbranch")
testEndToEnd(t, "riscv64", "riscvenc")
testEndToEnd(t, "riscv64", "riscvfarbranch")
}

func TestS390XEndToEnd(t *testing.T) {
Expand Down
2 changes: 0 additions & 2 deletions src/cmd/cgo/main.go
Original file line number Diff line number Diff line change
Expand Up @@ -180,7 +180,6 @@ var ptrSizeMap = map[string]int64{
"mips64le": 8,
"ppc64": 8,
"ppc64le": 8,
"riscv": 8,
"riscv64": 8,
"s390": 4,
"s390x": 8,
Expand All @@ -198,7 +197,6 @@ var intSizeMap = map[string]int64{
"mips64le": 8,
"ppc64": 8,
"ppc64le": 8,
"riscv": 8,
"riscv64": 8,
"s390": 4,
"s390x": 8,
Expand Down
2 changes: 1 addition & 1 deletion src/cmd/compile/internal/gc/plive.go
Original file line number Diff line number Diff line change
Expand Up @@ -683,7 +683,7 @@ func (lv *Liveness) markUnsafePoints() {
v = v.Args[0]
continue
}
case ssa.OpRISCVSUB: /* XXX */
case ssa.OpRISCV64SUB: /* XXX */
v = v.Args[0]
continue
case ssa.Op386MOVLload, ssa.OpARM64MOVWUload, ssa.OpPPC64MOVWZload, ssa.OpWasmI64Load32U:
Expand Down
6 changes: 3 additions & 3 deletions src/cmd/compile/internal/gc/ssa.go
Original file line number Diff line number Diff line change
Expand Up @@ -5566,12 +5566,12 @@ func (s *SSAGenState) Call(v *ssa.Value) *obj.Prog {
p.To.Type = obj.TYPE_REG
case sys.ARM, sys.ARM64, sys.MIPS, sys.MIPS64:
p.To.Type = obj.TYPE_MEM
case sys.RISCV:
case sys.RISCV64:
switch v.Op {
case ssa.OpRISCVCALLstatic:
case ssa.OpRISCV64CALLstatic:
p.To.Name = obj.NAME_EXTERN
p.To.Sym = v.Aux.(*obj.LSym)
case ssa.OpRISCVCALLclosure, ssa.OpRISCVCALLinter:
case ssa.OpRISCV64CALLclosure, ssa.OpRISCV64CALLinter:
p.To.Type = obj.TYPE_REG
}
default:
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -2,15 +2,15 @@
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.

package riscv
package riscv64

import (
"cmd/compile/internal/gc"
"cmd/internal/obj/riscv"
)

func Init(arch *gc.Arch) {
arch.LinkArch = &riscv.LinkRISCV
arch.LinkArch = &riscv.LinkRISCV64

arch.REGSP = riscv.REG_SP
// TODO(prattmic): all the other arches use 50 bits, even though
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,7 @@
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.

package riscv
package riscv64

import (
"cmd/compile/internal/gc"
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,7 @@
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.

package riscv
package riscv64

import (
"cmd/compile/internal/gc"
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,7 @@
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.

package riscv
package riscv64

import (
"math"
Expand Down Expand Up @@ -192,7 +192,7 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
// input args need no code
case ssa.OpPhi:
gc.CheckLoweredPhi(v)
case ssa.OpCopy, ssa.OpRISCVMOVconvert:
case ssa.OpCopy, ssa.OpRISCV64MOVconvert:
if v.Type.IsMemory() {
return
}
Expand Down Expand Up @@ -230,16 +230,16 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
gc.AddrAuto(&p.To, v)
case ssa.OpSP, ssa.OpSB, ssa.OpGetG:
// nothing to do
case ssa.OpRISCVADD, ssa.OpRISCVSUB, ssa.OpRISCVXOR, ssa.OpRISCVOR, ssa.OpRISCVAND,
ssa.OpRISCVSLL, ssa.OpRISCVSRA, ssa.OpRISCVSRL,
ssa.OpRISCVSLT, ssa.OpRISCVSLTU, ssa.OpRISCVMUL, ssa.OpRISCVMULW, ssa.OpRISCVMULH,
ssa.OpRISCVMULHU, ssa.OpRISCVDIV, ssa.OpRISCVDIVU, ssa.OpRISCVDIVW,
ssa.OpRISCVDIVUW, ssa.OpRISCVREM, ssa.OpRISCVREMU, ssa.OpRISCVREMW,
ssa.OpRISCVREMUW,
ssa.OpRISCVFADDS, ssa.OpRISCVFSUBS, ssa.OpRISCVFMULS, ssa.OpRISCVFDIVS,
ssa.OpRISCVFEQS, ssa.OpRISCVFNES, ssa.OpRISCVFLTS, ssa.OpRISCVFLES,
ssa.OpRISCVFADDD, ssa.OpRISCVFSUBD, ssa.OpRISCVFMULD, ssa.OpRISCVFDIVD,
ssa.OpRISCVFEQD, ssa.OpRISCVFNED, ssa.OpRISCVFLTD, ssa.OpRISCVFLED:
case ssa.OpRISCV64ADD, ssa.OpRISCV64SUB, ssa.OpRISCV64XOR, ssa.OpRISCV64OR, ssa.OpRISCV64AND,
ssa.OpRISCV64SLL, ssa.OpRISCV64SRA, ssa.OpRISCV64SRL,
ssa.OpRISCV64SLT, ssa.OpRISCV64SLTU, ssa.OpRISCV64MUL, ssa.OpRISCV64MULW, ssa.OpRISCV64MULH,
ssa.OpRISCV64MULHU, ssa.OpRISCV64DIV, ssa.OpRISCV64DIVU, ssa.OpRISCV64DIVW,
ssa.OpRISCV64DIVUW, ssa.OpRISCV64REM, ssa.OpRISCV64REMU, ssa.OpRISCV64REMW,
ssa.OpRISCV64REMUW,
ssa.OpRISCV64FADDS, ssa.OpRISCV64FSUBS, ssa.OpRISCV64FMULS, ssa.OpRISCV64FDIVS,
ssa.OpRISCV64FEQS, ssa.OpRISCV64FNES, ssa.OpRISCV64FLTS, ssa.OpRISCV64FLES,
ssa.OpRISCV64FADDD, ssa.OpRISCV64FSUBD, ssa.OpRISCV64FMULD, ssa.OpRISCV64FDIVD,
ssa.OpRISCV64FEQD, ssa.OpRISCV64FNED, ssa.OpRISCV64FLTD, ssa.OpRISCV64FLED:
r := v.Reg()
r1 := v.Args[0].Reg()
r2 := v.Args[1].Reg()
Expand All @@ -249,39 +249,39 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
p.SetFrom3(obj.Addr{Type: obj.TYPE_REG, Reg: r1})
p.To.Type = obj.TYPE_REG
p.To.Reg = r
case ssa.OpRISCVFSQRTS, ssa.OpRISCVFNEGS, ssa.OpRISCVFSQRTD, ssa.OpRISCVFNEGD,
ssa.OpRISCVFMVSX, ssa.OpRISCVFMVDX,
ssa.OpRISCVFCVTSW, ssa.OpRISCVFCVTSL, ssa.OpRISCVFCVTWS, ssa.OpRISCVFCVTLS,
ssa.OpRISCVFCVTDW, ssa.OpRISCVFCVTDL, ssa.OpRISCVFCVTWD, ssa.OpRISCVFCVTLD, ssa.OpRISCVFCVTDS, ssa.OpRISCVFCVTSD:
case ssa.OpRISCV64FSQRTS, ssa.OpRISCV64FNEGS, ssa.OpRISCV64FSQRTD, ssa.OpRISCV64FNEGD,
ssa.OpRISCV64FMVSX, ssa.OpRISCV64FMVDX,
ssa.OpRISCV64FCVTSW, ssa.OpRISCV64FCVTSL, ssa.OpRISCV64FCVTWS, ssa.OpRISCV64FCVTLS,
ssa.OpRISCV64FCVTDW, ssa.OpRISCV64FCVTDL, ssa.OpRISCV64FCVTWD, ssa.OpRISCV64FCVTLD, ssa.OpRISCV64FCVTDS, ssa.OpRISCV64FCVTSD:
p := s.Prog(v.Op.Asm())
p.From.Type = obj.TYPE_REG
p.From.Reg = v.Args[0].Reg()
p.To.Type = obj.TYPE_REG
p.To.Reg = v.Reg()
case ssa.OpRISCVADDI, ssa.OpRISCVXORI, ssa.OpRISCVORI, ssa.OpRISCVANDI,
ssa.OpRISCVSLLI, ssa.OpRISCVSRAI, ssa.OpRISCVSRLI, ssa.OpRISCVSLTI,
ssa.OpRISCVSLTIU:
case ssa.OpRISCV64ADDI, ssa.OpRISCV64XORI, ssa.OpRISCV64ORI, ssa.OpRISCV64ANDI,
ssa.OpRISCV64SLLI, ssa.OpRISCV64SRAI, ssa.OpRISCV64SRLI, ssa.OpRISCV64SLTI,
ssa.OpRISCV64SLTIU:
p := s.Prog(v.Op.Asm())
p.From.Type = obj.TYPE_CONST
p.From.Offset = v.AuxInt
p.SetFrom3(obj.Addr{Type: obj.TYPE_REG, Reg: v.Args[0].Reg()})
p.To.Type = obj.TYPE_REG
p.To.Reg = v.Reg()
case ssa.OpRISCVMOVBconst, ssa.OpRISCVMOVHconst, ssa.OpRISCVMOVWconst, ssa.OpRISCVMOVDconst:
case ssa.OpRISCV64MOVBconst, ssa.OpRISCV64MOVHconst, ssa.OpRISCV64MOVWconst, ssa.OpRISCV64MOVDconst:
p := s.Prog(v.Op.Asm())
p.From.Type = obj.TYPE_CONST
p.From.Offset = v.AuxInt
p.To.Type = obj.TYPE_REG
p.To.Reg = v.Reg()
case ssa.OpRISCVMOVSconst:
case ssa.OpRISCV64MOVSconst:
p := s.Prog(v.Op.Asm())
// Convert the float to the equivalent integer literal so we can
// move it using existing infrastructure.
p.From.Type = obj.TYPE_CONST
p.From.Offset = int64(int32(math.Float32bits(float32(math.Float64frombits(uint64(v.AuxInt))))))
p.To.Type = obj.TYPE_REG
p.To.Reg = v.Reg()
case ssa.OpRISCVMOVaddr:
case ssa.OpRISCV64MOVaddr:
p := s.Prog(v.Op.Asm())
p.From.Type = obj.TYPE_ADDR
p.To.Type = obj.TYPE_REG
Expand All @@ -307,37 +307,37 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
if reg := v.Args[0].RegName(); reg != wantreg {
v.Fatalf("bad reg %s for symbol type %T, want %s", reg, v.Aux, wantreg)
}
case ssa.OpRISCVMOVBload, ssa.OpRISCVMOVHload, ssa.OpRISCVMOVWload, ssa.OpRISCVMOVDload,
ssa.OpRISCVMOVBUload, ssa.OpRISCVMOVHUload, ssa.OpRISCVMOVWUload,
ssa.OpRISCVFMOVWload, ssa.OpRISCVFMOVDload:
case ssa.OpRISCV64MOVBload, ssa.OpRISCV64MOVHload, ssa.OpRISCV64MOVWload, ssa.OpRISCV64MOVDload,
ssa.OpRISCV64MOVBUload, ssa.OpRISCV64MOVHUload, ssa.OpRISCV64MOVWUload,
ssa.OpRISCV64FMOVWload, ssa.OpRISCV64FMOVDload:
p := s.Prog(v.Op.Asm())
p.From.Type = obj.TYPE_MEM
p.From.Reg = v.Args[0].Reg()
gc.AddAux(&p.From, v)
p.To.Type = obj.TYPE_REG
p.To.Reg = v.Reg()
case ssa.OpRISCVMOVBstore, ssa.OpRISCVMOVHstore, ssa.OpRISCVMOVWstore, ssa.OpRISCVMOVDstore,
ssa.OpRISCVFMOVWstore, ssa.OpRISCVFMOVDstore:
case ssa.OpRISCV64MOVBstore, ssa.OpRISCV64MOVHstore, ssa.OpRISCV64MOVWstore, ssa.OpRISCV64MOVDstore,
ssa.OpRISCV64FMOVWstore, ssa.OpRISCV64FMOVDstore:
p := s.Prog(v.Op.Asm())
p.From.Type = obj.TYPE_REG
p.From.Reg = v.Args[1].Reg()
p.To.Type = obj.TYPE_MEM
p.To.Reg = v.Args[0].Reg()
gc.AddAux(&p.To, v)
case ssa.OpRISCVSEQZ, ssa.OpRISCVSNEZ:
case ssa.OpRISCV64SEQZ, ssa.OpRISCV64SNEZ:
p := s.Prog(v.Op.Asm())
p.From.Type = obj.TYPE_REG
p.From.Reg = v.Args[0].Reg()
p.To.Type = obj.TYPE_REG
p.To.Reg = v.Reg()
case ssa.OpRISCVCALLstatic, ssa.OpRISCVCALLclosure, ssa.OpRISCVCALLinter:
case ssa.OpRISCV64CALLstatic, ssa.OpRISCV64CALLclosure, ssa.OpRISCV64CALLinter:
s.Call(v)
case ssa.OpRISCVLoweredWB:
case ssa.OpRISCV64LoweredWB:
p := s.Prog(obj.ACALL)
p.To.Type = obj.TYPE_MEM
p.To.Name = obj.NAME_EXTERN
p.To.Sym = v.Aux.(*obj.LSym)
case ssa.OpRISCVLoweredZero:
case ssa.OpRISCV64LoweredZero:
mov, sz := largestMove(v.AuxInt)

// mov ZERO, (Rarg0)
Expand All @@ -363,7 +363,7 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
p3.From.Reg = v.Args[1].Reg()
gc.Patch(p3, p)

case ssa.OpRISCVLoweredMove:
case ssa.OpRISCV64LoweredMove:
mov, sz := largestMove(v.AuxInt)

// mov (Rarg1), T2
Expand Down Expand Up @@ -403,7 +403,7 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
p5.From.Reg = v.Args[2].Reg()
gc.Patch(p5, p)

case ssa.OpRISCVLoweredNilCheck:
case ssa.OpRISCV64LoweredNilCheck:
// Issue a load which will fault if arg is nil.
// TODO: optimizations. See arm and amd64 LoweredNilCheck.
p := s.Prog(riscv.AMOVB)
Expand All @@ -416,11 +416,11 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
gc.Warnl(v.Pos, "generated nil check")
}

case ssa.OpRISCVLoweredGetClosurePtr:
case ssa.OpRISCV64LoweredGetClosurePtr:
// Closure pointer is S4 (riscv.REG_CTXT).
gc.CheckLoweredGetClosurePtr(v)

case ssa.OpRISCVLoweredGetCallerSP:
case ssa.OpRISCV64LoweredGetCallerSP:
// caller's SP is FixedFrameSize below the address of the first arg
p := s.Prog(riscv.AMOV)
p.From.Type = obj.TYPE_ADDR
Expand All @@ -429,7 +429,7 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
p.To.Type = obj.TYPE_REG
p.To.Reg = v.Reg()

case ssa.OpRISCVLoweredGetCallerPC:
case ssa.OpRISCV64LoweredGetCallerPC:
p := s.Prog(obj.AGETCALLERPC)
p.To.Type = obj.TYPE_REG
p.To.Reg = v.Reg()
Expand Down Expand Up @@ -473,7 +473,7 @@ func ssaGenBlock(s *gc.SSAGenState, b, next *ssa.Block) {
p.To.Type = obj.TYPE_MEM
p.To.Name = obj.NAME_EXTERN
p.To.Sym = b.Aux.(*obj.LSym)
case ssa.BlockRISCVBNE:
case ssa.BlockRISCV64BNE:
var p *obj.Prog
switch next {
case b.Succs[0].Block():
Expand Down
14 changes: 7 additions & 7 deletions src/cmd/compile/internal/ssa/config.go
Original file line number Diff line number Diff line change
Expand Up @@ -312,15 +312,15 @@ func NewConfig(arch string, types Types, ctxt *obj.Link, optimize bool) *Config
c.LinkReg = linkRegMIPS
c.hasGReg = true
c.noDuffDevice = true
case "riscv":
case "riscv64":
c.PtrSize = 8
c.RegSize = 8
c.lowerBlock = rewriteBlockRISCV
c.lowerValue = rewriteValueRISCV
c.registers = registersRISCV[:]
c.gpRegMask = gpRegMaskRISCV
c.fpRegMask = fpRegMaskRISCV
c.FPReg = framepointerRegRISCV
c.lowerBlock = rewriteBlockRISCV64
c.lowerValue = rewriteValueRISCV64
c.registers = registersRISCV64[:]
c.gpRegMask = gpRegMaskRISCV64
c.fpRegMask = fpRegMaskRISCV64
c.FPReg = framepointerRegRISCV64
c.hasGReg = true
case "wasm":
c.PtrSize = 8
Expand Down
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