Update UART comm Project

UARTCOMM/BL_UART/README.md

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+FPGA UART LoopBack 
+by Brandon Lam
+Files:
+baudgen_tx.v & baudgen_rx.v:
+  Generates the baud for serial transmission
+echo.v:
+  Top level for the UART module
+uart_rx.v & uart_tx.v
+  Rx an Tx lines 
+baudgen.vh 
+  Constants used in the baudrate
+echo.pcf:
+  Pin placements

UARTCOMM/BL_UART/baudgen.vh

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+/*Upduino: 12000000 / BAUDRATE  (and the result is rounded to an integer number)*/
+
+`define B115200 104
+`define B57600  208
+`define B38400  313
+`define B19200  625
+`define B9600   1250
+`define B4800   2500
+`define B2400   5000
+`define B1200   10000
+`define B600    20000
+`define B300    40000

UARTCOMM/BL_UART/baudgen_rx.v

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+`include "baudgen.vh"
+module baudgen_rx #(
+         parameter BAUDRATE = `B115200  //-- Default baudrate
+)(
+         input wire rstn,
+         input wire clk, 
+         input wire clk_ena,
+         output wire clk_out 
+);
+
+localparam N = $clog2(BAUDRATE);
+
+localparam M2 = (BAUDRATE >> 1);
+
+reg [N-1:0] divcounter = 0;
+
+always @(posedge clk)
+
+  if (!rstn)
+    divcounter <= 0;
+
+  else if (clk_ena)
+    divcounter <= (divcounter == BAUDRATE - 1) ? 0 : divcounter + 1;
+  else
+    divcounter <= BAUDRATE - 1;
+
+assign clk_out = (divcounter == M2) ? clk_ena : 0;
+
+
+endmodule

UARTCOMM/BL_UART/baudgen_tx.v

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+`default_nettype none
+`include "baudgen.vh"
+module baudgen_tx #(
+          parameter BAUDRATE = `B115200 
+)(
+          input wire rstn,            
+          input wire clk,            
+          input wire clk_ena,       
+          output wire clk_out      
+);
+
+localparam N = $clog2(BAUDRATE);
+
+reg [N-1:0] divcounter = 0;
+
+always @(posedge clk)
+
+  if (!rstn)
+    divcounter <= 0;
+
+  else if (clk_ena)
+    divcounter <= (divcounter == BAUDRATE - 1) ? 0 : divcounter + 1;
+  else
+    divcounter <= BAUDRATE - 1;
+
+assign clk_out = (divcounter == 0) ? clk_ena : 0;
+
+
+endmodule

UARTCOMM/BL_UART/echo.pcf

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+set_io rx   9
+set_io tx   8

UARTCOMM/BL_UART/echo.v

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+/*TOP LEVEL DESIGN*/
+
+`default_nettype none
+`include "baudgen.vh"
+
+module echo #(
+         parameter BAUDRATE = `B115200
+)(
+         input wire rx,
+         output wire tx
+);
+
+wire clk;
+SB_HFOSC inthosc (
+  .CLKHFPU(1'b1),
+  .CLKHFEN(1'b1),
+  .CLKHF(clk)
+);
+
+wire rcv;
+wire [7:0] data;
+reg rstn = 0;
+wire ready;
+
+always @(posedge clk)
+  rstn <= 1;
+
+uart_rx #(.BAUDRATE(BAUDRATE))
+  RX0 (.clk(clk),
+       .rstn(rstn),
+       .rx(rx),
+       .rcv(rcv),
+       .data(data)
+      );
+
+uart_tx #(.BAUDRATE(BAUDRATE))
+  TX0 ( .clk(clk),
+         .rstn(rstn),
+         .start(rcv),
+         .data(data),
+         .tx(tx),
+         .ready(ready)
+       );
+
+
+endmodule

UARTCOMM/BL_UART/uart_rx.v

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+`default_nettype none
+
+`include "baudgen.vh"
+
+module uart_rx #(parameter BAUDRATE = `B115200)(
+         input wire clk,   
+         input wire rstn, 
+         input wire rx,  
+         output reg rcv,
+         output reg [7:0] data 
+);
+
+wire clk_baud;
+
+reg bauden;  
+reg clear;  
+reg load;  
+
+/*----------------------------------------------------------------------------*/
+/*Rx register*/
+reg rx_r;
+always @(posedge clk)
+  rx_r <= rx;
+
+/*Baud generator*/
+baudgen_rx #(BAUDRATE)
+  baudgen0 (
+    .rstn(rstn),
+    .clk(clk),
+    .clk_ena(bauden),
+    .clk_out(clk_baud)
+);
+
+/*Bit counter*/
+reg [3:0] bitc;
+always @(posedge clk)
+  if (clear)
+    bitc <= 4'd0;	/*clear the bit counter 4 bits all 0*/
+  else if (clear == 0 && clk_baud == 1)
+    bitc <= bitc + 1;
+
+
+/*shift register*/
+reg [9:0] raw_data;
+always @(posedge clk)
+  if (clk_baud == 1)
+    raw_data <= {rx_r, raw_data[9:1]}; /*curly braces = concatenation*/
+
+/*Data register*/
+always @(posedge clk)
+  if (rstn == 0)
+    data <= 0;
+  else if (load)
+    data <= raw_data[8:1];
+
+
+/*----------------------------------------------------------------------------*/
+/*Declate the states*/
+localparam IDLE = 2'd0;
+localparam RECV = 2'd1;
+localparam LOAD = 2'd2;
+localparam DAV = 2'd3;
+
+/*State storage*/
+reg [1:0] state;
+reg [1:0] next_state;
+
+/*Rst*/
+always @(posedge clk)
+  if (!rstn)
+    state <= IDLE;
+  else
+    state <= next_state;
+
+always @(*) begin /*Create sensitivity list to curr_state*/
+  next_state = curr_state;
+  bauden = 0;
+  clear = 0;
+  load = 0;
+
+  case(curr_state)
+	  IDLE: begin
+		  clear = 1;
+		  rcv = 0;
+		  load = 0;
+		  baud_en = 0;
+		  if (rx_r == 0)
+			  next_state = RECV;
+	  end
+	ECV: begin
+		clear = 0;
+      		rcv = 0;
+		load = 0;
+		baud_en = 1;
+      		if (bitc == 4'd10)
+        		next_state = LOAD;
+		else
+			next_state = ECV;
+	end
+
+	LOAD: begin
+		clear = 0;
+      		rcv = 0;
+		load = 1;
+		baud_en = 0;
+      		next_state = DAV;
+    	end
+
+    	DAV: begin
+		clear = 0;
+      		rcv = 1;
+		load = 0;
+		baud_en = 0;
+      		next_state = IDLE;
+    	end
+
+    	default:
+      	rcv = 0;
+
+  endcase
+
+end
+
+endmodule

UARTCOMM/BL_UART/uart_tx.v

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+`default_nettype none
+
+`include "baudgen.vh"
+
+module uart_tx #(
+         parameter BAUDRATE = `B115200
+)(
+         input wire clk,       
+         input wire rstn,     
+         input wire start,   
+         input wire [7:0] data,
+         output reg tx,       
+         output reg ready    
+);
+
+
+wire clk_baud;
+
+reg [3:0] bitc;
+
+reg [7:0] data_r;
+
+reg load; 
+reg baud_en;
+
+always @(posedge clk)
+  if (start == 1 && state == IDLE)
+    data_r <= data;
+
+reg [9:0] shifter;
+
+always @(posedge clk)
+  if (rstn == 0)
+    shifter <= 10'b11_1111_1111;
+
+  else if (load == 1)
+    shifter <= {data_r,2'b01};
+
+  else if (load == 0 && clk_baud == 1)
+    shifter <= {1'b1, shifter[9:1]};
+
+always @(posedge clk)
+  if (!rstn)
+    bitc <= 0;
+
+  else if (load == 1)
+    bitc <= 0;
+  else if (load == 0 && clk_baud == 1)
+    bitc <= bitc + 1;
+
+always @(posedge clk)
+  tx <= shifter[0];
+
+baudgen_tx #( .BAUDRATE(BAUDRATE))
+BAUD0 (
+    .rstn(rstn),
+    .clk(clk),
+    .clk_ena(baud_en),
+    .clk_out(clk_baud)
+  );
+
+localparam IDLE  = 0;
+localparam START = 1;
+localparam TRANS = 2;
+
+reg [1:0] state;
+reg [1:0] next_state;
+
+always @(posedge clk)
+  if (!rstn)
+    state <= IDLE;
+  else
+    state <= next_state;
+
+always @(*) begin
+  next_state = state;
+  load = 0;
+  baud_en = 0;
+  case (state)
+    IDLE: begin
+      ready = 1;
+      if (start == 1)
+        next_state = START;
+    end
+
+    START: begin
+      load = 1;
+      baud_en = 1;
+      ready = 0;
+      next_state = TRANS;
+    end
+
+    TRANS: begin
+      baud_en = 1;
+      ready = 0;
+      if (bitc == 11)
+        next_state = IDLE;
+    end
+
+    default:
+      ready = 0;
+
+  endcase
+end
+
+endmodule