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uploaded fpga camera and fpga accelerometer project
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tritainguyen98
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Mar 12, 2020
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# IceStick-Accelerometer | ||
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Loads SPI controller onto IceStick and reads accelerometer data. Leds will turn on/off according to orientation. | ||
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Using open source toolchain, (Yosys, arachne-pnr, and IceStorm) load verilog files onto Icestick, and connect accelerometer. The leds on the IceStick should turn on/off to indicate the direction of tilt with respect to gravity. |
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# ############################################################################## | ||
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# iCEcube PCF | ||
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# Version: 2012.09SP1.22498 | ||
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# File Generated: Jun 13 2013 14:14:52 | ||
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# Family & Device: iCE40HX1K | ||
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# Package: TQ144 | ||
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# ############################################################################## | ||
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###IOSet List 12 | ||
set_io clk_in 21 | ||
set_io LED 95 | ||
set_io LED_MINUS[0] 99 | ||
set_io LED_PLUS[1] 96 | ||
set_io SCLK 81 -pullup yes | ||
set_io SDI 80 -pullup yes | ||
set_io SDO 79 -pullup yes | ||
set_io test2 45 | ||
set_io LED_MINUS[1] 98 | ||
set_io LED_PLUS[0] 97 | ||
set_io SS 78 -pullup yes | ||
set_io test1 47 | ||
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`timescale 1ns / 1ps | ||
// Created By: Tritai Nguyen | ||
// Create Date: 03/07/2020 | ||
// Module Name: ClkDiv_5Hz | ||
// Project Name: PmodACL_Demo | ||
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// ==================================================================================== | ||
// Define Module | ||
// ==================================================================================== | ||
module ClkDiv_5Hz( | ||
CLK, | ||
RST, | ||
CLKOUT | ||
); | ||
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// ==================================================================================== | ||
// Port Declarations | ||
// ==================================================================================== | ||
input CLK; // 100MHz onboard clock | ||
input RST; // Reset | ||
output CLKOUT; // New clock output | ||
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// ==================================================================================== | ||
// Parameters, Registers, and Wires | ||
// ==================================================================================== | ||
reg CLKOUT; | ||
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// Current count value | ||
reg [23:0] clkCount = 24'h000000; | ||
// Value to toggle output clock at | ||
parameter [23:0] cntEndVal = 24'h989680; | ||
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// =================================================================================== | ||
// Implementation | ||
// =================================================================================== | ||
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//------------------------------------------------ | ||
// 5Hz Clock Divider Generates Send/Receive signal | ||
//------------------------------------------------ | ||
always @(posedge CLK or posedge RST) | ||
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// Reset clock | ||
if (RST == 1'b1) begin | ||
CLKOUT <= 1'b0; | ||
clkCount <= 24'h000000; | ||
end | ||
else begin | ||
if (clkCount == cntEndVal) begin | ||
CLKOUT <= (~CLKOUT); | ||
clkCount <= 24'h000000; | ||
end | ||
else begin | ||
clkCount <= clkCount + 1'b1; | ||
end | ||
end | ||
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endmodule |
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module ice_pll(REFERENCECLK, | ||
PLLOUTCORE, | ||
PLLOUTGLOBAL, | ||
RESET); | ||
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input REFERENCECLK; | ||
input RESET; /* To initialize the simulation properly, the RESET signal (Active Low) must be asserted at the beginning of the simulation */ | ||
output PLLOUTCORE; | ||
output PLLOUTGLOBAL; | ||
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SB_PLL40_CORE ice_pll_inst(.REFERENCECLK(REFERENCECLK), | ||
.PLLOUTCORE(PLLOUTCORE), | ||
.PLLOUTGLOBAL(PLLOUTGLOBAL), | ||
.EXTFEEDBACK(), | ||
.DYNAMICDELAY(), | ||
.RESETB(RESET), | ||
.BYPASS(1'b0), | ||
.LATCHINPUTVALUE(), | ||
.LOCK(), | ||
.SDI(), | ||
.SDO(), | ||
.SCLK()); | ||
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//\\ Fin=12, Fout=88; | ||
defparam ice_pll_inst.DIVR = 4'b0000; | ||
defparam ice_pll_inst.DIVF = 7'b0111010; | ||
defparam ice_pll_inst.DIVQ = 3'b011; | ||
defparam ice_pll_inst.FILTER_RANGE = 3'b001; | ||
defparam ice_pll_inst.FEEDBACK_PATH = "SIMPLE"; | ||
defparam ice_pll_inst.DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED"; | ||
defparam ice_pll_inst.FDA_FEEDBACK = 4'b0000; | ||
defparam ice_pll_inst.DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED"; | ||
defparam ice_pll_inst.FDA_RELATIVE = 4'b0000; | ||
defparam ice_pll_inst.SHIFTREG_DIV_MODE = 2'b00; | ||
defparam ice_pll_inst.PLLOUT_SELECT = "GENCLK"; | ||
defparam ice_pll_inst.ENABLE_ICEGATE = 1'b0; | ||
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endmodule |
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ice_pll ice_pll_inst(.REFERENCECLK(), | ||
.PLLOUTCORE(), | ||
.PLLOUTGLOBAL(), | ||
.RESET()); |
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