update OV7670_CAMERA verilog codes

src/OV7670_Camera/I2C_Interface.v

@@ -9,64 +9,81 @@
 // --------------------------------------------------------------------------------------
 
 
-module I2C_INTERFACE(
+module I2C_INTERFACE
+#(	
+	parameter write_ID = 8'h42,
+	parameter read_ID = 8'h43
+)
+(
 	input wire GLOBAL_CLK		,
 	input wire START_TRANSFER 	,
-	input wire [7:0] SDATA 		,
-	inout reg SIOD				,
+	input wire [7:0] SUBADDRESS ,
+	input wire [7:0] VALUE		,
+	inout wire SIOD				,
 	output reg SIOC				,
 	output reg READY
 );
 
 
 reg transmitting = 1'b0;
 reg [5:0] counter = 6'b0;
-reg [3:0] bits_sent = 4'b0;
-reg [7:0] q_data;
+reg [4:0] bits_sent = 4'b0;
+reg [26:0] q_data;
+
+reg SIOD_temp;
+assign SIOD = SIOD_temp;
 
 always @(*)
 begin
 	if (!transmitting) begin
 		READY = 1'b1;
 		counter = 6'b0;
-		bits_sent = 4'b0;
+		bits_sent = 5'b0;
 		SIOC = 1'b1;
-		SIOD = 1'bz;
+		SIOD_temp = 1'b1;
 		if (START_TRANSFER) begin
 			transmitting = 1'b1;
-			SIOD = 1'b0;
-			q_data = SDATA;
+			SIOD_temp = 1'b0;
+			q_data = {write_ID, 1'b0 ,SUBADDRESS, 1'b0 , VALUE , 1'b0};
 			READY = 1'b0;
 		end
 	end
 end
 
+always @(posedge GLOBAL_CLK)
+begin
+	if (transmitting) begin
+		if (counter == 6'b111111)
+			counter = 6'b0;
+		else
+			counter = counter + 1;	
+	end
+end
 
-always @(negedge SIOC)
+reg loaded = 1'b0;
+always @(negedge GLOBAL_CLK)
 begin
-	if (bits_sent == 4'b1000)
+	if (bits_sent == 5'b11011 && SIOC == 1'b1) begin	// 27 bits are all sent out through SIOD
+		SIOD_temp = 1'b1;
 		transmitting = 1'b0;
-		READY = 1'b1;
-	else begin
+	end
+	else if (SIOC == 1'b0 && loaded == 1'b0) begin
 		if (transmitting) begin
-			SIOD = q_data[0];
-			q_data = q_data >> 1;
+			SIOD_temp = q_data[26];
+			q_data = q_data << 1;
 			bits_sent = bits_sent + 1;
+			loaded = 1'b1;
 		end
 	end
 end
 
-
-always @(posedge GLOBAL_CLK)
+always @(posedge SIOC)
 begin
-	if (transmitting) begin
-		if (counter == 6'b111111)
-			counter = 6'b0;
-		else
-			counter = counter + 1;	
-	end
+	loaded <= 1'b0;
 end
 
+
+
 // Create a 187.5 KHz SIOC serial clock in the following block
 always @(*)
 begin

src/OV7670_Camera/camera_config.v

@@ -13,33 +13,43 @@ module CAMERA_CONFIG(
 	input wire NEXT						,
 	output reg [7:0] CTRL_ADDR			,	// specify the control register address in the camera chip
 	output reg [7:0] CTRL_VALUE  		,	// specify the control value in the camera chip
+	output reg READY					,	// specify whether the CURRENT control value is ready or not
+	output reg FINISHED						// specify whether the ENTIRE configuration if finished or not
 );
 
 reg [7:0] address;
 
 always @(posedge NEXT)
 begin
-	if (START_CONFIG == 1'b1)
+
+	READY = 1'b0;
+
+	if (START_CONFIG == 1'b1) begin
 		address = 8'b0;
-	else
+		FINISHED = 1'b0;
+	end
+	else if (!FINISHED) begin
 		address = address + 1;
+	end
 
 
 	case (address)
 		0:	begin
-				CTRL_ADDR <= 8'h12;
-				CTRL_VALUE <= 8'h80;
+				CTRL_ADDR = 8'h12;
+				CTRL_VALUE = 8'h80;
 			end
 
-		/* More Control Features can be added here if wanted */
+		/* More Control	Commands can be added here if wanted */
 
 		default: begin
-					CTRL_ADDR <= 8'hFF
-					CTRL_VALUE <= 8'hFF
+					CTRL_ADDR = 8'hFF;
+					CTRL_VALUE = 8'hFF;
+					FINISHED = 1'b1;
 				end
+	endcase
 
 
-			
+	READY = 1'b1;
 end
 
 

src/OV7670_Camera/camera_controller.v

@@ -12,11 +12,9 @@
 module CAMERA_CONTROLLER(
 	input wire GLOBAL_CLK	,
 	input wire RESET		,
-	input wire VSYNC		,
-	input wire HREF			,
-	input wire PCLK			,
 	inout wire SIOD			,	// Serial Data
 	output wire SIOC		,	// Serial Clock
+	output wire CONFIG_FINISHED
 
 );
 
@@ -26,44 +24,67 @@ wire [7:0] ctrl_addr;
 wire [7:0] ctrl_value;
 reg next;
 reg start_config;
-CAMERA_CONFIG cfg_inst
-(
+wire config_ready;
+wire CONFIG_FINISHED;
+CAMERA_CONFIG cfg_inst(
 	.START_CONFIG(start_config),
 	.NEXT(next),
 	.CTRL_ADDR(ctrl_addr),
-	.CTRL_VALUE(ctrl_value)
+	.CTRL_VALUE(ctrl_value),
+	.READY(config_ready),
+	.FINISHED(CONFIG_FINISHED)
 );
 
+
+
 reg start_transfer;
-wire ready;
-I2C_INTERFACE i2c_inst
-(
+wire I2C_ready;
+I2C_INTERFACE i2c_inst(
 	.GLOBAL_CLK(GLOBAL_CLK),
 	.START_TRANSFER(start_transfer),
-	.SDATA(),
+	.SUBADDRESS(ctrl_addr),
+	.VALUE(ctrl_value),
 	.SIOD(SIOD),
 	.SIOC(SIOC),
-	.READY(ready)
+	.READY(I2C_ready)
 );
 
+
+
 reg resetting = 1'b0;
 always @(*)
 begin
 	next = 1'b0;
-	if (!resetting and RESET)
+	start_config = 1'b0;
+	start_transfer = 1'b0;
+	if (!resetting && RESET) begin
 		start_config = 1'b1;
-		start_transfer = 1'b1;
+		next = 1'b1;
 		resetting = 1'b1;
-	else if (resetting)
-		start_config = 1'b0;
-		start_transfer = 1'b0;
+	end
 end
 
-always @(posedge ready)
+always @(posedge config_ready)
 begin
-
+	start_config <= 1'b0;
+	next <= 1'b0;
+	start_transfer <= 1'b1;
 end
 
+always @(negedge I2C_ready)
+begin
+	start_transfer = 1'b0;
+end
+
+always @(posedge I2C_ready)
+begin
+	if (!CONFIG_FINISHED) begin
+		next <= 1'b1;
+	end
+end
+
+
+
 
 
 endmodule

src/OV7670_Camera/camera_image.v

@@ -0,0 +1,37 @@
+// --------------------------------------------------------------------------------------
+// Organization: CALPLUG-FPGA
+// Project Name:
+// Date: Winter 2019
+// FPGA Board: iCE40 UltraPlus SG48I
+// --------------------------------------------------------------------------------------
+// File Name: camera_image.v
+// File Description: This is the camera module that implements the algorithm for capturing image from the camera
+// --------------------------------------------------------------------------------------
+
+module CAMERA_IMAGE
+#(
+	parameter RESOLUTION_W = 640;
+	parameter RESOLUTION_H = 480;
+)
+(
+	input wire [7:0] PIXEL		,		// 8 bits pixel data
+	input wire VSYNC			,		// if VSYNC is high, that means all ENTIRE image pixels have been captured 
+	input wire HREF				,		// if HREF is high, that means ONE SEPARATE ROW of the image pixels have been captured
+	input wire PCLK				
+);
+
+wire capturing_image = !VSYNC;
+
+
+
+
+
+
+
+
+
+
+
+
+
+endmodule;