Skip to content

Commit

Permalink
Update Golden Settings to Adrenalin 23.10.2
Browse files Browse the repository at this point in the history 
And add Golden settings for Navi 21 and Navi 23 as well
Signed-off-by: ExtremeXT <[email protected]>
  • Loading branch information
@ExtremeXT
ExtremeXT committed Oct 19, 2023
1 parent 71986a2 commit 373ed8a
Show file tree
Hide file tree
Showing 2 changed files with 225 additions and 49 deletions.
252 changes: 208 additions & 44 deletions NootRX/AMDCommon.hpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -13,6 +13,16 @@ constexpr UInt32 mmPCIE_DATA2 = 0xF;

//-------- GC Registers --------//

constexpr UInt32 mmCB_CGTT_SCLK_CTRL = 0x50A8;
constexpr UInt32 mmCB_CGTT_SCLK_CTRL_BASE_IDX = 1;
constexpr UInt32 mmCGTT_GS_NGG_CLK_CTRL = 0x5087;
constexpr UInt32 mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX = 1;
constexpr UInt32 mmCGTT_SC_CLK_CTRL0 = 0x5089;
constexpr UInt32 mmCGTT_SC_CLK_CTRL0_BASE_IDX = 1;
constexpr UInt32 mmCGTT_SC_CLK_CTRL1 = 0x508A;
constexpr UInt32 mmCGTT_SC_CLK_CTRL1_BASE_IDX = 1;
constexpr UInt32 mmCGTT_SC_CLK_CTRL2 = 0x508B;
constexpr UInt32 mmCGTT_SC_CLK_CTRL2_BASE_IDX = 1;
constexpr UInt32 mmCGTT_SPI_CS_CLK_CTRL = 0x507C;
constexpr UInt32 mmCGTT_SPI_CS_CLK_CTRL_BASE_IDX = 1;
constexpr UInt32 mmCGTT_SPI_PS_CLK_CTRL = 0x507D;
Expand All @@ -21,30 +31,56 @@ constexpr UInt32 mmCGTT_SPI_RA0_CLK_CTRL = 0x507A;
constexpr UInt32 mmCGTT_SPI_RA0_CLK_CTRL_BASE_IDX = 1;
constexpr UInt32 mmCGTT_SPI_RA1_CLK_CTRL = 0x507B;
constexpr UInt32 mmCGTT_SPI_RA1_CLK_CTRL_BASE_IDX = 1;
constexpr UInt32 mmCGTT_SX_CLK_CTRL0 = 0x5094;
constexpr UInt32 mmCGTT_SX_CLK_CTRL0_BASE_IDX = 1;
constexpr UInt32 mmCGTT_SX_CLK_CTRL1 = 0x5095;
constexpr UInt32 mmCGTT_SX_CLK_CTRL1_BASE_IDX = 1;
constexpr UInt32 mmCGTT_SX_CLK_CTRL2 = 0x5096;
constexpr UInt32 mmCGTT_SX_CLK_CTRL2_BASE_IDX = 1;
constexpr UInt32 mmCGTT_SX_CLK_CTRL3 = 0x5097;
constexpr UInt32 mmCGTT_SX_CLK_CTRL3_BASE_IDX = 1;
constexpr UInt32 mmCGTT_SX_CLK_CTRL4 = 0x5098;
constexpr UInt32 mmCGTT_SX_CLK_CTRL4_BASE_IDX = 1;
constexpr UInt32 mmCGTT_VGT_CLK_CTRL = 0x5084;
constexpr UInt32 mmCGTT_VGT_CLK_CTRL_BASE_IDX = 1;
constexpr UInt32 mmCGTT_WD_CLK_CTRL = 0x5086;
constexpr UInt32 mmCGTT_WD_CLK_CTRL_BASE_IDX = 1;
constexpr UInt32 mmCPF_GCR_CNTL = 0x1F53;
constexpr UInt32 mmCPF_GCR_CNTL_BASE_IDX = 0;
constexpr UInt32 mmDB_CGTT_CLK_CTRL_0 = 0x50A4;
constexpr UInt32 mmDB_CGTT_CLK_CTRL_0_BASE_IDX = 1;
constexpr UInt32 mmDB_DEBUG3 = 0x13AE;
constexpr UInt32 mmDB_DEBUG3_BASE_IDX = 0;
constexpr UInt32 mmDB_DEBUG4 = 0x13AF;
constexpr UInt32 mmDB_DEBUG4_BASE_IDX = 0;
constexpr UInt32 mmDB_EXCEPTION_CONTROL = 0x13BF;
constexpr UInt32 mmDB_EXCEPTION_CONTROL_BASE_IDX = 0;
constexpr UInt32 mmGCR_GENERAL_CNTL_Sienna_Cichlid = 0x1580;
constexpr UInt32 mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX = 0;
constexpr UInt32 mmGCEA_SDP_TAG_RESERVE0 = 0x189B;
constexpr UInt32 mmGCEA_SDP_TAG_RESERVE0_BASE_IDX = 1;
constexpr UInt32 mmGCEA_SDP_TAG_RESERVE1 = 0x189C;
constexpr UInt32 mmGCEA_SDP_TAG_RESERVE1_BASE_IDX = 1;
constexpr UInt32 mmGCR_GENERAL_CNTL = 0x1580;
constexpr UInt32 mmGCR_GENERAL_CNTL_BASE_IDX = 0;
constexpr UInt32 mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid = 0x16F3;
constexpr UInt32 mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX = 0;
constexpr UInt32 mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX = 1;
constexpr UInt32 mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid = 0x15DB;
constexpr UInt32 mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX = 0;
constexpr UInt32 mmGE_PC_CNTL = 0x0FE5;
constexpr UInt32 mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX = 1;
constexpr UInt32 mmGC_UNKNOWN1 = 0x50A9;
constexpr UInt32 mmGC_UNKNOWN1_BASE_IDX = 1;
constexpr UInt32 mmGE_PC_CNTL = 0xFE5;
constexpr UInt32 mmGE_PC_CNTL_BASE_IDX = 0;
constexpr UInt32 mmGL2A_ADDR_MATCH_MASK = 0x2E21;
constexpr UInt32 mmGL2A_ADDR_MATCH_MASK_BASE_IDX = 1;
constexpr UInt32 mmGL2C_ADDR_MATCH_MASK = 0x2E03;
constexpr UInt32 mmGL2C_ADDR_MATCH_MASK_BASE_IDX = 1;
constexpr UInt32 mmGL2C_CGTT_SCLK_CTRL = 0x50FC;
constexpr UInt32 mmGL2C_CGTT_SCLK_CTRL_BASE_IDX = 1;
constexpr UInt32 mmGL2C_CM_CTRL1 = 0x2E08;
constexpr UInt32 mmGL2C_CM_CTRL1_BASE_IDX = 1;
constexpr UInt32 mmGL2C_CTRL3 = 0x2E0C;
constexpr UInt32 mmGL2C_CTRL3_BASE_IDX = 1;
constexpr UInt32 mmLDS_CONFIG = 0x10A2;
constexpr UInt32 mmLDS_CONFIG_BASE_IDX = 0;
constexpr UInt32 mmPA_CL_ENHANCE = 0x1025;
constexpr UInt32 mmPA_CL_ENHANCE_BASE_IDX = 0;
constexpr UInt32 mmPA_SC_BINNER_TIMEOUT_COUNTER = 0x1070;
Expand All @@ -59,8 +95,6 @@ constexpr UInt32 mmSQ_CONFIG = 0x10A0;
constexpr UInt32 mmSQ_CONFIG_BASE_IDX = 0;
constexpr UInt32 mmSQ_PERFCOUNTER0_SELECT = 0x39C0;
constexpr UInt32 mmSQ_PERFCOUNTER0_SELECT_BASE_IDX = 1;
constexpr UInt32 mmSQ_PERFCOUNTER1_SELECT = 0x39C1;
constexpr UInt32 mmSQ_PERFCOUNTER1_SELECT_BASE_IDX = 1;
constexpr UInt32 mmSQ_PERFCOUNTER10_SELECT = 0x39CA;
constexpr UInt32 mmSQ_PERFCOUNTER10_SELECT_BASE_IDX = 1;
constexpr UInt32 mmSQ_PERFCOUNTER11_SELECT = 0x39CB;
Expand All @@ -73,6 +107,8 @@ constexpr UInt32 mmSQ_PERFCOUNTER14_SELECT = 0x39CE;
constexpr UInt32 mmSQ_PERFCOUNTER14_SELECT_BASE_IDX = 1;
constexpr UInt32 mmSQ_PERFCOUNTER15_SELECT = 0x39CF;
constexpr UInt32 mmSQ_PERFCOUNTER15_SELECT_BASE_IDX = 1;
constexpr UInt32 mmSQ_PERFCOUNTER1_SELECT = 0x39C1;
constexpr UInt32 mmSQ_PERFCOUNTER1_SELECT_BASE_IDX = 1;
constexpr UInt32 mmSQ_PERFCOUNTER2_SELECT = 0x39C2;
constexpr UInt32 mmSQ_PERFCOUNTER2_SELECT_BASE_IDX = 1;
constexpr UInt32 mmSQ_PERFCOUNTER3_SELECT = 0x39C3;
Expand All @@ -89,14 +125,14 @@ constexpr UInt32 mmSQ_PERFCOUNTER8_SELECT = 0x39C8;
constexpr UInt32 mmSQ_PERFCOUNTER8_SELECT_BASE_IDX = 1;
constexpr UInt32 mmSQ_PERFCOUNTER9_SELECT = 0x39C9;
constexpr UInt32 mmSQ_PERFCOUNTER9_SELECT_BASE_IDX = 1;
constexpr UInt32 mmSX_DEBUG_1 = 0x11B8;
constexpr UInt32 mmSX_DEBUG_1_BASE_IDX = 0;
constexpr UInt32 mmTA_CNTL_AUX = 0x12E2;
constexpr UInt32 mmTA_CNTL_AUX_BASE_IDX = 0;
constexpr UInt32 mmTA_CNTL_AUX_BASE_IDX = 1;
constexpr UInt32 mmUTCL1_CTRL = 0x1588;
constexpr UInt32 mmUTCL1_CTRL_BASE_IDX = 0;
constexpr UInt32 mmVGT_GS_MAX_WAVE_ID = 0x1009;
constexpr UInt32 mmVGT_GS_MAX_WAVE_ID_BASE_IDX = 0;
constexpr UInt32 mmLDS_CONFIG = 0x10A2;
constexpr UInt32 mmLDS_CONFIG_BASE_IDX = 0;

//-------- AMD Catalyst Data Types --------//

Expand Down Expand Up @@ -220,53 +256,181 @@ static const UInt32 ddiCapsNavi22[16] = {0x800001, 0x1FE, 0x0, 0x0, 0x200, 0x800

//---- Golden Settings ----//

static const CAILIPGoldenRegister gcGoldenSettingsNavi21[] = {
GOLDEN_REGISTER(mmCB_CGTT_SCLK_CTRL, 0xFFFFFFFF, 0xFF000100),
GOLDEN_REGISTER(mmGC_UNKNOWN1, 0xFFFFFFFF, 0xFF000100),
GOLDEN_REGISTER(mmCGTT_SC_CLK_CTRL0, 0xFFFFFFFF, 0xFFFF0100),
GOLDEN_REGISTER(mmCGTT_SC_CLK_CTRL1, 0xFFFFFFFF, 0xFFFF0100),
GOLDEN_REGISTER(mmCGTT_SC_CLK_CTRL2, 0xFFFFFFFF, 0x78000100),
GOLDEN_REGISTER(mmDB_CGTT_CLK_CTRL_0, 0xFFFFFFFF, 0xFF400100),
GOLDEN_REGISTER(mmCGTT_GS_NGG_CLK_CTRL, 0xFFFFFFFF, 0xFFFF8100),
GOLDEN_REGISTER(mmCGTT_VGT_CLK_CTRL, 0xFFFFFFFF, 0xFFFF0100),
GOLDEN_REGISTER(mmCGTT_WD_CLK_CTRL, 0xFFFFFFFF, 0xFFFF0100),
GOLDEN_REGISTER(mmCGTT_SX_CLK_CTRL0, 0xFFFFFFFF, 0xFE400100),
GOLDEN_REGISTER(mmCGTT_SX_CLK_CTRL1, 0xFFFFFFFF, 0xFE400100),
GOLDEN_REGISTER(mmCGTT_SX_CLK_CTRL2, 0xFFFFFFFF, 0xFE600100),
GOLDEN_REGISTER(mmCGTT_SX_CLK_CTRL3, 0xFFFFFFFF, 0xFE400100),
GOLDEN_REGISTER(mmCGTT_SX_CLK_CTRL4, 0xFFFFFFFF, 0xFE400100),
GOLDEN_REGISTER(mmGL2C_CGTT_SCLK_CTRL, 0xFFFFFFFF, 0xFF000100),
GOLDEN_REGISTER(mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
GOLDEN_REGISTER(mmCGTT_SPI_PS_CLK_CTRL, 0xFF7F0FFF, 0x78000100),
GOLDEN_REGISTER(mmCGTT_SPI_RA0_CLK_CTRL, 0xFF7F0FFF, 0x30000100),
GOLDEN_REGISTER(mmCGTT_SPI_RA1_CLK_CTRL, 0xFF7F0FFF, 0x7E000100),
GOLDEN_REGISTER(mmCPF_GCR_CNTL, 0x7FFFF, 0xC000),
GOLDEN_REGISTER(mmDB_DEBUG3, 0xFFFFFFFF, 0x280),
GOLDEN_REGISTER(mmDB_DEBUG4, 0xFFFFFFFF, 0x800000),
GOLDEN_REGISTER(mmDB_EXCEPTION_CONTROL, 0x7FFF0F1F, 0xB80000),
GOLDEN_REGISTER(mmGCEA_SDP_TAG_RESERVE0, 0xFFFFFFFF, 0x10100100),
GOLDEN_REGISTER(mmGCEA_SDP_TAG_RESERVE1, 0xFFFFFFFF, 0x17000088),
GOLDEN_REGISTER(mmGCR_GENERAL_CNTL, 0x1FF1FFFF, 0x500),
GOLDEN_REGISTER(mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xFF000000, 0xFF008080),
GOLDEN_REGISTER(mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xFF000000, 0xFF008080),
GOLDEN_REGISTER(mmGE_PC_CNTL, 0x3FFFFF, 0x280400),
GOLDEN_REGISTER(mmGL2A_ADDR_MATCH_MASK, 0xFFFFFFFF, 0xFFFFFFCF),
GOLDEN_REGISTER(mmGL2C_ADDR_MATCH_MASK, 0xFFFFFFFF, 0xFFFFFFCF),
GOLDEN_REGISTER(mmGL2C_CM_CTRL1, 0xFF8FFF0F, 0x580F1008),
GOLDEN_REGISTER(mmGL2C_CTRL3, 0xF7FFFFFF, 0x10F80988),
GOLDEN_REGISTER(mmLDS_CONFIG, 0x20, 0x20),
GOLDEN_REGISTER(mmPA_CL_ENHANCE, 0xF17FFFFF, 0x1200007),
GOLDEN_REGISTER(mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xFFFFFFFF, 0x800),
GOLDEN_REGISTER(mmPA_SC_ENHANCE_2, 0xFFFFFFBF, 0x820),
GOLDEN_REGISTER(mmSPI_CONFIG_CNTL_1, 0xFFFFFFFF, 0x70104),
GOLDEN_REGISTER(mmSQ_CONFIG, 0xE07DF47F, 0x180070),
GOLDEN_REGISTER(mmSQ_PERFCOUNTER0_SELECT, 0xF0F001FF, 0x0),
GOLDEN_REGISTER(mmSQ_PERFCOUNTER1_SELECT, 0xF0F001FF, 0x0),
GOLDEN_REGISTER(mmSQ_PERFCOUNTER10_SELECT, 0xF0F001FF, 0x0),
GOLDEN_REGISTER(mmSQ_PERFCOUNTER11_SELECT, 0xF0F001FF, 0x0),
GOLDEN_REGISTER(mmSQ_PERFCOUNTER12_SELECT, 0xF0F001FF, 0x0),
GOLDEN_REGISTER(mmSQ_PERFCOUNTER13_SELECT, 0xF0F001FF, 0x0),
GOLDEN_REGISTER(mmSQ_PERFCOUNTER14_SELECT, 0xF0F001FF, 0x0),
GOLDEN_REGISTER(mmSQ_PERFCOUNTER15_SELECT, 0xF0F001FF, 0x0),
GOLDEN_REGISTER(mmSQ_PERFCOUNTER2_SELECT, 0xF0F001FF, 0x0),
GOLDEN_REGISTER(mmSQ_PERFCOUNTER3_SELECT, 0xF0F001FF, 0x0),
GOLDEN_REGISTER(mmSQ_PERFCOUNTER4_SELECT, 0xF0F001FF, 0x0),
GOLDEN_REGISTER(mmSQ_PERFCOUNTER5_SELECT, 0xF0F001FF, 0x0),
GOLDEN_REGISTER(mmSQ_PERFCOUNTER6_SELECT, 0xF0F001FF, 0x0),
GOLDEN_REGISTER(mmSQ_PERFCOUNTER7_SELECT, 0xF0F001FF, 0x0),
GOLDEN_REGISTER(mmSQ_PERFCOUNTER8_SELECT, 0xF0F001FF, 0x0),
GOLDEN_REGISTER(mmSQ_PERFCOUNTER9_SELECT, 0xF0F001FF, 0x0),
GOLDEN_REGISTER(mmSX_DEBUG_1, 0x10000, 0x10020),
GOLDEN_REGISTER(mmTA_CNTL_AUX, 0xFFF7FFFF, 0x1030000),
GOLDEN_REGISTER(mmUTCL1_CTRL, 0xFFBFFFFF, 0xA00000),
GOLDEN_REGISTER_TERMINATOR,
};

static const CAILIPGoldenRegister gcGoldenSettingsNavi22[] = {
GOLDEN_REGISTER(mmCB_CGTT_SCLK_CTRL, 0xFFFF0FFF, 0xFF000100),
GOLDEN_REGISTER(mmGC_UNKNOWN1, 0xFFFF0FFF, 0xFF000100),
GOLDEN_REGISTER(mmCGTT_GS_NGG_CLK_CTRL, 0xFFFF8FFF, 0xFFFF8100),
GOLDEN_REGISTER(mmCGTT_SC_CLK_CTRL0, 0xFFFF0FFF, 0xFFFF0100),
GOLDEN_REGISTER(mmCGTT_SC_CLK_CTRL1, 0xFFFF0FFF, 0xFFFF0100),
GOLDEN_REGISTER(mmCGTT_SC_CLK_CTRL2, 0x7C000FFF, 0x78000100),
GOLDEN_REGISTER(mmCGTT_SX_CLK_CTRL0, 0xFFFFFFFF, 0xFE400100),
GOLDEN_REGISTER(mmCGTT_SX_CLK_CTRL1, 0xFFFFFFFF, 0xFE400100),
GOLDEN_REGISTER(mmCGTT_SX_CLK_CTRL2, 0xFFFFEFFF, 0xFE600100),
GOLDEN_REGISTER(mmCGTT_SX_CLK_CTRL3, 0xFFFFEFFF, 0xFE400100),
GOLDEN_REGISTER(mmCGTT_SX_CLK_CTRL4, 0xFFFFFFFF, 0xFE400100),
GOLDEN_REGISTER(mmCGTT_VGT_CLK_CTRL, 0xFFFF8FFF, 0xFFFF0100),
GOLDEN_REGISTER(mmCGTT_WD_CLK_CTRL, 0xFFFF8FFF, 0xFFFF0100),
GOLDEN_REGISTER(mmDB_CGTT_CLK_CTRL_0, 0xFFFFFFFF, 0xFF400100),
GOLDEN_REGISTER(mmGL2C_CGTT_SCLK_CTRL, 0xFFFF0FFF, 0xFF000100),
GOLDEN_REGISTER(mmCGTT_SPI_CS_CLK_CTRL, 0xFF7F0FFF, 0x78000100),
GOLDEN_REGISTER(mmCGTT_SPI_PS_CLK_CTRL, 0xFF7F0FFF, 0x78000100),
GOLDEN_REGISTER(mmCGTT_SPI_RA0_CLK_CTRL, 0xFF7F0FFF, 0x30000100),
GOLDEN_REGISTER(mmCGTT_SPI_RA1_CLK_CTRL, 0xFF7F0FFF, 0x7E000100),
GOLDEN_REGISTER(mmCPF_GCR_CNTL, 0x0007FFFF, 0x0000C000),
GOLDEN_REGISTER(mmDB_DEBUG3, 0xFFFFFFFF, 0x00000280),
GOLDEN_REGISTER(mmDB_DEBUG4, 0xFFFFFFFF, 0x00800000),
GOLDEN_REGISTER(mmDB_EXCEPTION_CONTROL, 0x7FFF0F1F, 0x00B80000),
GOLDEN_REGISTER(mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1FF1FFFF, 0x00000500),
GOLDEN_REGISTER(mmCPF_GCR_CNTL, 0x7FFFF, 0xC000),
GOLDEN_REGISTER(mmDB_DEBUG3, 0xFFFFFFFF, 0x280),
GOLDEN_REGISTER(mmDB_DEBUG4, 0xFFFFFFFF, 0x800000),
GOLDEN_REGISTER(mmDB_EXCEPTION_CONTROL, 0x7FFF0F1F, 0xB80000),
GOLDEN_REGISTER(mmGCR_GENERAL_CNTL, 0x1FF1FFFF, 0x500),
GOLDEN_REGISTER(mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xFFFFFFFF, 0xFF008080),
GOLDEN_REGISTER(mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xFFFF8FFF, 0xFF008080),
GOLDEN_REGISTER(mmGE_PC_CNTL, 0x003FFFFF, 0x00280400),
GOLDEN_REGISTER(mmGE_PC_CNTL, 0x3FFFFF, 0x280400),
GOLDEN_REGISTER(mmGL2A_ADDR_MATCH_MASK, 0xFFFFFFFF, 0xFFFFFFCF),
GOLDEN_REGISTER(mmGL2C_ADDR_MATCH_MASK, 0xFFFFFFFF, 0xFFFFFFCF),
GOLDEN_REGISTER(mmGL2C_CM_CTRL1, 0xFF8FFF0F, 0x580F1008),
GOLDEN_REGISTER(mmGL2C_CTRL3, 0xF7FFFFFF, 0x00F80988),
GOLDEN_REGISTER(mmPA_CL_ENHANCE, 0xF17FFFFF, 0x01200007),
GOLDEN_REGISTER(mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xFFFFFFFF, 0x00000800),
GOLDEN_REGISTER(mmPA_SC_ENHANCE_2, 0xFFFFFFBF, 0x00000820),
GOLDEN_REGISTER(mmSPI_CONFIG_CNTL_1, 0xFFFFFFFF, 0x00070104),
GOLDEN_REGISTER(mmSPI_START_PHASE, 0x000000FF, 0x00000004),
GOLDEN_REGISTER(mmSQ_CONFIG, 0xE07DF47F, 0x00180070),
GOLDEN_REGISTER(mmSQ_PERFCOUNTER0_SELECT, 0xF0F001FF, 0x00000000),
GOLDEN_REGISTER(mmSQ_PERFCOUNTER1_SELECT, 0xF0F001FF, 0x00000000),
GOLDEN_REGISTER(mmSQ_PERFCOUNTER10_SELECT, 0xF0F001FF, 0x00000000),
GOLDEN_REGISTER(mmSQ_PERFCOUNTER11_SELECT, 0xF0F001FF, 0x00000000),
GOLDEN_REGISTER(mmSQ_PERFCOUNTER12_SELECT, 0xF0F001FF, 0x00000000),
GOLDEN_REGISTER(mmSQ_PERFCOUNTER13_SELECT, 0xF0F001FF, 0x00000000),
GOLDEN_REGISTER(mmSQ_PERFCOUNTER14_SELECT, 0xF0F001FF, 0x00000000),
GOLDEN_REGISTER(mmSQ_PERFCOUNTER15_SELECT, 0xF0F001FF, 0x00000000),
GOLDEN_REGISTER(mmSQ_PERFCOUNTER2_SELECT, 0xF0F001FF, 0x00000000),
GOLDEN_REGISTER(mmSQ_PERFCOUNTER3_SELECT, 0xF0F001FF, 0x00000000),
GOLDEN_REGISTER(mmSQ_PERFCOUNTER4_SELECT, 0xF0F001FF, 0x00000000),
GOLDEN_REGISTER(mmSQ_PERFCOUNTER5_SELECT, 0xF0F001FF, 0x00000000),
GOLDEN_REGISTER(mmSQ_PERFCOUNTER6_SELECT, 0xF0F001FF, 0x00000000),
GOLDEN_REGISTER(mmSQ_PERFCOUNTER7_SELECT, 0xF0F001FF, 0x00000000),
GOLDEN_REGISTER(mmSQ_PERFCOUNTER8_SELECT, 0xF0F001FF, 0x00000000),
GOLDEN_REGISTER(mmSQ_PERFCOUNTER9_SELECT, 0xF0F001FF, 0x00000000),
GOLDEN_REGISTER(mmTA_CNTL_AUX, 0xFFF7FFFF, 0x01030000),
GOLDEN_REGISTER(mmUTCL1_CTRL, 0xFFBFFFFF, 0x00A00000),
GOLDEN_REGISTER(mmVGT_GS_MAX_WAVE_ID, 0x00000FFF, 0x000003FF),
GOLDEN_REGISTER(mmLDS_CONFIG, 0x00000020, 0x00000020),
GOLDEN_REGISTER(mmGL2C_CTRL3, 0xF7FFFFFF, 0xF80988),
GOLDEN_REGISTER(mmLDS_CONFIG, 0x1FF, 0x20),
GOLDEN_REGISTER(mmPA_CL_ENHANCE, 0xF17FFFFF, 0x1200007),
GOLDEN_REGISTER(mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xFFFFFFFF, 0x800),
GOLDEN_REGISTER(mmPA_SC_ENHANCE_2, 0xFFFFFFBF, 0x820),
GOLDEN_REGISTER(mmSPI_CONFIG_CNTL_1, 0xFFFFFFFF, 0x70104),
GOLDEN_REGISTER(mmSPI_START_PHASE, 0xFF, 0x4),
GOLDEN_REGISTER(mmSQ_CONFIG, 0xE07DF47F, 0x180070),
GOLDEN_REGISTER(mmSQ_PERFCOUNTER0_SELECT, 0xF0F001FF, 0x0),
GOLDEN_REGISTER(mmSQ_PERFCOUNTER1_SELECT, 0xF0F001FF, 0x0),
GOLDEN_REGISTER(mmSQ_PERFCOUNTER10_SELECT, 0xF0F001FF, 0x0),
GOLDEN_REGISTER(mmSQ_PERFCOUNTER11_SELECT, 0xF0F001FF, 0x0),
GOLDEN_REGISTER(mmSQ_PERFCOUNTER12_SELECT, 0xF0F001FF, 0x0),
GOLDEN_REGISTER(mmSQ_PERFCOUNTER13_SELECT, 0xF0F001FF, 0x0),
GOLDEN_REGISTER(mmSQ_PERFCOUNTER14_SELECT, 0xF0F001FF, 0x0),
GOLDEN_REGISTER(mmSQ_PERFCOUNTER15_SELECT, 0xF0F001FF, 0x0),
GOLDEN_REGISTER(mmSQ_PERFCOUNTER2_SELECT, 0xF0F001FF, 0x0),
GOLDEN_REGISTER(mmSQ_PERFCOUNTER3_SELECT, 0xF0F001FF, 0x0),
GOLDEN_REGISTER(mmSQ_PERFCOUNTER4_SELECT, 0xF0F001FF, 0x0),
GOLDEN_REGISTER(mmSQ_PERFCOUNTER5_SELECT, 0xF0F001FF, 0x0),
GOLDEN_REGISTER(mmSQ_PERFCOUNTER6_SELECT, 0xF0F001FF, 0x0),
GOLDEN_REGISTER(mmSQ_PERFCOUNTER7_SELECT, 0xF0F001FF, 0x0),
GOLDEN_REGISTER(mmSQ_PERFCOUNTER8_SELECT, 0xF0F001FF, 0x0),
GOLDEN_REGISTER(mmSQ_PERFCOUNTER9_SELECT, 0xF0F001FF, 0x0),
GOLDEN_REGISTER(mmSX_DEBUG_1, 0xFFFFFF7F, 0x10020),
GOLDEN_REGISTER(mmTA_CNTL_AUX, 0xFFF7FFFF, 0x1030000),
GOLDEN_REGISTER(mmUTCL1_CTRL, 0xFFBFFFFF, 0xA00000),
GOLDEN_REGISTER(mmVGT_GS_MAX_WAVE_ID, 0xFFF, 0x3FF),
GOLDEN_REGISTER_TERMINATOR,
};

static const CAILASICGoldenRegisters goldenSettingsNavi22[] = {
static const CAILIPGoldenRegister gcGoldenSettingsNavi23[] = {
GOLDEN_REGISTER(mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
GOLDEN_REGISTER(mmCGTT_SPI_RA0_CLK_CTRL, 0x30000000, 0x30000100),
GOLDEN_REGISTER(mmCGTT_SPI_RA1_CLK_CTRL, 0x7E000000, 0x7E000100),
GOLDEN_REGISTER(mmCPF_GCR_CNTL, 0x7FFFF, 0xC000),
GOLDEN_REGISTER(mmDB_DEBUG3, 0x280, 0x280),
GOLDEN_REGISTER(mmDB_DEBUG4, 0x7800000, 0x800000),
GOLDEN_REGISTER(mmGCR_GENERAL_CNTL, 0x1D00, 0x500),
GOLDEN_REGISTER(mmGE_PC_CNTL, 0x3C0000, 0x280400),
GOLDEN_REGISTER(mmGL2A_ADDR_MATCH_MASK, 0xFFFFFFFF, 0xFFFFFFCF),
GOLDEN_REGISTER(mmGL2C_ADDR_MATCH_MASK, 0xFFFFFFFF, 0xFFFFFFCF),
GOLDEN_REGISTER(mmGL2C_CM_CTRL1, 0x40000000, 0x580F1008),
GOLDEN_REGISTER(mmGL2C_CTRL3, 0x40000, 0xF80988),
GOLDEN_REGISTER(mmLDS_CONFIG, 0x20, 0x20),
GOLDEN_REGISTER(mmPA_CL_ENHANCE, 0x1000000, 0x1200007),
GOLDEN_REGISTER(mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xFFFFFFFF, 0x800),
GOLDEN_REGISTER(mmPA_SC_ENHANCE_2, 0x800, 0x820),
GOLDEN_REGISTER(mmSQ_CONFIG, 0x1F, 0x180070),
GOLDEN_REGISTER(mmSQ_PERFCOUNTER0_SELECT, 0xF0F001FF, 0x0),
GOLDEN_REGISTER(mmSQ_PERFCOUNTER1_SELECT, 0xF0F001FF, 0x0),
GOLDEN_REGISTER(mmSQ_PERFCOUNTER10_SELECT, 0xF0F001FF, 0x0),
GOLDEN_REGISTER(mmSQ_PERFCOUNTER11_SELECT, 0xF0F001FF, 0x0),
GOLDEN_REGISTER(mmSQ_PERFCOUNTER12_SELECT, 0xF0F001FF, 0x0),
GOLDEN_REGISTER(mmSQ_PERFCOUNTER13_SELECT, 0xF0F001FF, 0x0),
GOLDEN_REGISTER(mmSQ_PERFCOUNTER14_SELECT, 0xF0F001FF, 0x0),
GOLDEN_REGISTER(mmSQ_PERFCOUNTER15_SELECT, 0xF0F001FF, 0x0),
GOLDEN_REGISTER(mmSQ_PERFCOUNTER2_SELECT, 0xF0F001FF, 0x0),
GOLDEN_REGISTER(mmSQ_PERFCOUNTER3_SELECT, 0xF0F001FF, 0x0),
GOLDEN_REGISTER(mmSQ_PERFCOUNTER4_SELECT, 0xF0F001FF, 0x0),
GOLDEN_REGISTER(mmSQ_PERFCOUNTER5_SELECT, 0xF0F001FF, 0x0),
GOLDEN_REGISTER(mmSQ_PERFCOUNTER6_SELECT, 0xF0F001FF, 0x0),
GOLDEN_REGISTER(mmSQ_PERFCOUNTER7_SELECT, 0xF0F001FF, 0x0),
GOLDEN_REGISTER(mmSQ_PERFCOUNTER8_SELECT, 0xF0F001FF, 0x0),
GOLDEN_REGISTER(mmSQ_PERFCOUNTER9_SELECT, 0xF0F001FF, 0x0),
GOLDEN_REGISTER(mmSX_DEBUG_1, 0x10000, 0x10020),
GOLDEN_REGISTER(mmTA_CNTL_AUX, 0x1030000, 0x1030000),
GOLDEN_REGISTER(mmUTCL1_CTRL, 0x3A00000, 0xA00000),
GOLDEN_REGISTER_TERMINATOR,
};

static const CAILASICGoldenRegisters goldenSettingsNavi21[] = {
GOLDEN_REGISTERS(GC, 0, gcGoldenSettingsNavi22),
GOLDEN_REGISTERS_TERMINATOR,
};

static const CAILASICGoldenRegisters goldenSettingsNavi22[] = {
GOLDEN_REGISTERS(GC, 0, gcGoldenSettingsNavi21),
GOLDEN_REGISTERS_TERMINATOR,
};

static const CAILASICGoldenRegisters goldenSettingsNavi23[] = {
GOLDEN_REGISTERS(GC, 0, gcGoldenSettingsNavi23),
GOLDEN_REGISTERS_TERMINATOR,
};
Loading

0 comments on commit 373ed8a

Please sign in to comment.