hb: Speed up SD reads

Closes #58
DS-Homebrew · Mar 17, 2024 · ad180ab · ad180ab
1 parent 91d60a6
commit ad180ab
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Showing 9 changed files with 200 additions and 132 deletions.
diff --git a/hb/bootloader/include/patch.h b/hb/bootloader/include/patch.h
@@ -4,11 +4,15 @@
 #include <nds/ndstypes.h>
 #include <nds/memory.h> // tNDSHeader
 
+#define patchOffsetCacheFileVersion 4	// Change when new functions are being patched, some offsets removed
+										// the offset order changed, and/or the function signatures changed
 typedef struct patchOffsetCacheContents {
     u16 ver;
     u16 type;
 	u32 dldiOffset;
 	u32 dldiChecked;
+	u32* mpuRegionOffset;
+	u32 mpuRegionChecked;
 	u32* wordCommandOffset;
 	u32* bootloaderOffset;
 	u32 bootloaderChecked;
@@ -20,9 +24,10 @@ typedef struct patchOffsetCacheContents {
 	u32 swi00Checked;
 } patchOffsetCacheContents;
 
-extern u16 patchOffsetCacheFileVersion;
+extern u16 patchOffsetCacheFilePrevCrc;
+extern u16 patchOffsetCacheFileNewCrc;
+
 extern patchOffsetCacheContents patchOffsetCache;
-extern bool patchOffsetCacheChanged;
 extern void rsetPatchCache(const tNDSHeader* ndsHeader);
 
 extern void patchBinary(const tNDSHeader* ndsHeader);

diff --git a/hb/bootloader/source/arm7/dldi_patcher.c b/hb/bootloader/source/arm7/dldi_patcher.c
@@ -130,9 +130,7 @@ bool dldiPatchBinary (data_t *binData, u32 binSize, bool ramDisk) {
 		// does not have a DLDI section
 		return false;
 	} else {
-		extern bool patchOffsetCacheChanged;
 		patchOffsetCache.dldiOffset = (u32)patchOffset;
-		patchOffsetCacheChanged = true;
 	}
 
 	data_t *pDH = (data_t*)(((u32*)(&_io_dldi)) - 24);

diff --git a/hb/bootloader/source/arm7/hook.c b/hb/bootloader/source/arm7/hook.c
@@ -128,6 +128,8 @@ static const u32 swi00Patched[3] = {
 	0x4770DF05   , // SWI 0X05
 };*/
 
+static u32 mpuRegionSignature = 0x04000033;
+
 //static const int MAX_HANDLER_SIZE = 50;
 
 static u32* hookInterruptHandlerHomebrew (u32* addr, size_t size) {
@@ -198,6 +200,24 @@ static u32* hookAccelIPCHomebrew2010(u32* addr, size_t size) {
 	return addr;
 }
 
+static u32* hookMpu(u32* addr, size_t size) {
+	u32* end = addr + size/sizeof(u32);
+
+	while (addr < end) {
+		if (*addr == mpuRegionSignature)
+		{
+			break;
+		}
+		addr++;
+	}
+
+	if (addr >= end) {
+		return NULL;
+	}
+
+	return addr;
+}
+
 static u16* hookSwi00(u16* addr, size_t size) {
 	u16* end = addr + size/sizeof(u16);
 
@@ -283,11 +303,25 @@ const u16* generateA7InstrThumb(int arg1, int arg2) {
 int hookNds (const tNDSHeader* ndsHeader, u32* sdEngineLocation, u32* wordCommandAddr) {
 	u32* hookLocation = patchOffsetCache.a7IrqHookOffset;
 	u32* hookAccel = patchOffsetCache.a7IrqHookAccelOffset;
+	u32* mpuRegionLocation = patchOffsetCache.mpuRegionOffset;
 	u16* a9Swi12Location = patchOffsetCache.a9Swi12Offset;
 	u16* swi00Location = patchOffsetCache.swi00Offset;
 
 	nocashMessage("hookNds");
 
+	if (patchOffsetCache.dldiOffset) {
+		if (!patchOffsetCache.mpuRegionChecked) {
+			mpuRegionLocation = hookMpu((u32*)ndsHeader->arm9destination, ndsHeader->arm9binarySize);
+			if (mpuRegionLocation) {
+				patchOffsetCache.mpuRegionOffset = mpuRegionLocation;
+			}
+			patchOffsetCache.mpuRegionChecked = true;
+		}
+		if (mpuRegionLocation) {
+			*mpuRegionLocation = 0x00000035; // Patch MPU to allow DSi WRAM access
+		}
+	}
+
 	if (!patchOffsetCache.a9Swi12Checked) {
 		a9Swi12Location = hookSwi12((u16*)ndsHeader->arm9destination, ndsHeader->arm9binarySize);
 		if (a9Swi12Location) {

diff --git a/hb/bootloader/source/arm7/main.arm7.c b/hb/bootloader/source/arm7/main.arm7.c
@@ -180,19 +180,19 @@ static void passArgs_ARM7 (void) {
 static void initMBK(void) {
 	// This function has no effect with ARM7 SCFG locked
 
-	// arm7 is master of WRAM-A, arm9 of WRAM-B & C
-	REG_MBK9=0x3000000F;
+	// ARM7 is master of WRAM-A, arm9 of WRAM-B & C
+	REG_MBK9 = 0x3000000F;
 
-	// WRAM-A fully mapped to arm7
-	*((vu32*)REG_MBK1)=0x8D898581; // same as dsiware
+	// WRAM-A fully mapped to ARM7
+	*(vu32*)REG_MBK1 = 0x8185898D; // Same as DSiWare
 
-	// WRAM-B fully mapped to arm9 // inverted order
-	*((vu32*)REG_MBK2)=0x8C888480;
-	*((vu32*)REG_MBK3)=0x9C989490;
+	// WRAM-B fully mapped to ARM7 // inverted order
+	*(vu32*)REG_MBK2 = 0x9195999D;
+	*(vu32*)REG_MBK3 = 0x8185898D;
 
-	// WRAM-C fully mapped to arm9 // inverted order
-	*((vu32*)REG_MBK4)=0x8C888480;
-	*((vu32*)REG_MBK5)=0x9C989490;
+	// WRAM-C fully mapped to arm7 // inverted order
+	*(vu32*)REG_MBK4 = 0x9195999D;
+	*(vu32*)REG_MBK5 = 0x8185898D;
 
 	// WRAM mapped to the 0x3700000 - 0x37FFFFF area 
 	// WRAM-A mapped to the 0x3000000 - 0x303FFFF area : 256k
@@ -697,8 +697,16 @@ int arm7_main (void) {
 
 	// File containing cached patch offsets
 	aFile patchOffsetCacheFile = getFileFromCluster(patchOffsetCacheFileCluster);
-	fileRead((char*)&patchOffsetCache, patchOffsetCacheFile, 0, sizeof(patchOffsetCacheContents));
-	u16 prevPatchOffsetCacheFileVersion = patchOffsetCache.ver;
+	fileRead((char*)&patchOffsetCache, patchOffsetCacheFile, 0, 4);
+	if (patchOffsetCache.ver == patchOffsetCacheFileVersion
+	 && patchOffsetCache.type == 2) {	// 0 = Regular, 1 = B4DS, 2 = HB
+		fileRead((char*)&patchOffsetCache, patchOffsetCacheFile, 0, sizeof(patchOffsetCacheContents));
+	} else {
+		patchOffsetCache.ver = patchOffsetCacheFileVersion;
+		patchOffsetCache.type = 2;
+	}
+
+	patchOffsetCacheFilePrevCrc = swiCRC16(0xFFFF, &patchOffsetCache, sizeof(patchOffsetCacheContents));
 
 	rsetPatchCache(ndsHeader);
 
@@ -725,7 +733,6 @@ int arm7_main (void) {
 				patchOffsetCache.dldiOffset = patchOffset;
 			}
 			patchOffsetCache.dldiChecked = true;
-			patchOffsetCacheChanged = true;
 		}
 		u32* wordCommandAddr = (u32 *) (((u32)((u32*)NDS_HEADER)[0x0A])+patchOffset+0x80);
 
@@ -747,7 +754,6 @@ int arm7_main (void) {
 				}
 			}
 			patchOffsetCache.bootloaderChecked = true;
-			patchOffsetCacheChanged = true;
 		}
 		if (patchOffsetCache.bootloaderOffset) {
 			//toncset(patchOffsetCache.bootloaderOffset, 0, 0x9C98);
@@ -759,7 +765,8 @@ int arm7_main (void) {
 	}
 	toncset((char*)0x06000000, 0, 0x8000);
 
-	if (prevPatchOffsetCacheFileVersion != patchOffsetCacheFileVersion || patchOffsetCacheChanged) {
+	patchOffsetCacheFileNewCrc = swiCRC16(0xFFFF, &patchOffsetCache, sizeof(patchOffsetCacheContents));
+	if (patchOffsetCacheFileNewCrc != patchOffsetCacheFilePrevCrc) {
 		fileWrite((char*)&patchOffsetCache, patchOffsetCacheFile, 0, sizeof(patchOffsetCacheContents));
 	}
 

diff --git a/hb/bootloader/source/arm7/patch_common.c b/hb/bootloader/source/arm7/patch_common.c
@@ -23,13 +23,11 @@
 #include "common.h"
 #include "tonccpy.h"
 
-u16 patchOffsetCacheFileVersion = 3;	// Change when new functions are being patched, some offsets removed
-										// the offset order changed, and/or the function signatures changed
+u16 patchOffsetCacheFilePrevCrc = 0;
+u16 patchOffsetCacheFileNewCrc = 0;
 
 patchOffsetCacheContents patchOffsetCache;
 
-bool patchOffsetCacheChanged = false;
-
 void rsetPatchCache(const tNDSHeader* ndsHeader)
 {
 	if (patchOffsetCache.ver != patchOffsetCacheFileVersion

diff --git a/hb/bootloader/source/arm9/main.arm9.c b/hb/bootloader/source/arm9/main.arm9.c
@@ -53,13 +53,13 @@ volatile u32 arm9_ramDiskCluster = 0;
 void initMBKARM9(void) {
 	// Default DSiWare settings
 
-	// WRAM-B fully mapped to arm9 // inverted order
-	*((vu32*)REG_MBK2)=0x8C888480;
-	*((vu32*)REG_MBK3)=0x9C989490;
+	// WRAM-B fully mapped to arm7 // inverted order
+	*(vu32*)REG_MBK2 = 0x9195999D;
+	*(vu32*)REG_MBK3 = 0x8185898D;
 
-	// WRAM-C fully mapped to arm9 // inverted order
-	*((vu32*)REG_MBK4)=0x8C888480;
-	*((vu32*)REG_MBK5)=0x9C989490;
+	// WRAM-C fully mapped to arm7 // inverted order
+	*(vu32*)REG_MBK4 = 0x9195999D;
+	*(vu32*)REG_MBK5 = 0x8185898D;
 
 	// WRAM-A not mapped (reserved to arm7)
 	REG_MBK6=0x00000000;

diff --git a/hb/common/include/locations.h b/hb/common/include/locations.h
@@ -25,6 +25,6 @@
 #define RAM_DISK_LOCATION_LZ77ROM      0x0C900000
 #define RAM_DISK_LOCATION_DSIMODE      0x0D000000
 
-#define CACHE_ADRESS_START             0x0C800000
+#define CACHE_ADRESS_START             0x03700000
 
 #endif // LOCATIONS_H