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Mtl dgpu #62

Merged
merged 29 commits into from
Dec 3, 2024
Merged

Mtl dgpu #62

merged 29 commits into from
Dec 3, 2024

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mkopec
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@mkopec mkopec commented Jul 29, 2024

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@mkopec mkopec marked this pull request as ready for review August 5, 2024 08:36
@mkopec mkopec force-pushed the mtl_dgpu branch 2 times, most recently from 1d0f69c to 3105fdd Compare August 16, 2024 10:53
@mkopec mkopec self-assigned this Aug 22, 2024
src/board/novacustom/v540tnx/board.c Outdated Show resolved Hide resolved
src/board/novacustom/v560tnx/board.c Outdated Show resolved Hide resolved
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The ADC can be configured for 0 - AVCC range with ADCIVMFSCS1. It doesn't have to be in range of 0 - AVCC/1.1

src/board/novacustom/v540tnx/board.mk Outdated Show resolved Hide resolved
GCR15 = BIT(4);
// Set GPB5 and GPD2 to 1.8V
GCR19 = BIT(7) | BIT(0);
// Set GPD3 to 1.8V, GPF2 and GPF3 to 3.3V
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Schematics says GPF2 and GPF3 is 1.8V

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@mkopec mkopec Sep 11, 2024

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GPF3 thankfully goes to U56 which accepts 1.2 ~ 5V, but yeah this probably needs to be fixed.

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miczyg1 commented Sep 11, 2024

The GPIO voltage settings do not seem to cover all GPIOs annotated as 1.8V in schematics. List of GPIO that are marked 1.8V on schematics:

  • GPD {0,1,2,3,4,}
  • GPE {0,6, 7}
  • GPF {2,3,4,5,6, 7}
  • GPC {0,1,2}
  • GPH0 (GPH1 should be 1.8V as well, discussed in separate thread)
  • GPB5
  • GPA {4,5}

GPIO set to 1.8V by the code (according to comments):

  • GPB5
  • GPD {2,3}
  • GPF {6,7}
  • GPH {0,1}

So there is a lot of GPIOs with incorrect voltage probably:

  • GPD {0,1} - GCR19 bits 2 and 1, GPD4 - GCR29 bit 6
  • GPE {0,6,7} - GCR20 bits 5,4,3
  • GPF {2,3,4} - GCR20 bits 2,1,0; GPF5 - GCR21 bit 7
  • GPC {1,2} - GCR19 bits 5,4; GPC0 does not seem to have voltage selection, although it should be 1.8V, because it is connected to an AND gate supplied by 1.8V power
  • GPA {4,5} - GCR22 bits 3,2

Same comments apply to both dGPU variants

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miczyg1 commented Sep 16, 2024

Are we goign to fix those 1.8V pins as in my above comment? @mkopec

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mkopec commented Sep 16, 2024

We are, I just need to review the schematics again to confirm these 100%. Do note that this config was dumped from Clevo firmware so it's probably not going to cause overvoltage issues outright. It's also possible the schematics are wrong...

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miczyg1 commented Sep 16, 2024

We are, I just need to review the schematics again to confirm these 100%. Do note that this config was dumped from Clevo firmware so it's probably not going to cause overvoltage issues outright. It's also possible the schematics are wrong...

I just did that for you in the above comment. Again, if you lower the voltage of the pins from 3.3V to 1.8V it won't cause overvoltage, maybe undervoltage... I also have been checking what the signals are used for and what their voltage should be.

@mkopec mkopec force-pushed the mtl_dgpu branch 3 times, most recently from a69d160 to 8728cc7 Compare October 18, 2024 16:31
mkopec added 20 commits December 3, 2024 14:01
It's been observed that polling GN21 too often results in throttling.

Signed-off-by: Michał Kopeć <[email protected]>
15% is too much and impacts performance

Signed-off-by: Michał Kopeć <[email protected]>
These power limits work on CPU only, but the GPU is the major power
consumer on these boards. Applying Psys power limits only results in CPU
being stuck at 400MHz while GPU is doing anything.

Signed-off-by: Michał Kopeć <[email protected]>
@mkopec mkopec merged commit 7fedef6 into master Dec 3, 2024
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3 participants