Predicate cache alternative implementation #4292
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| @@ -822,6 +824,10 @@ void Arm64Emitter::FillStaticRegs(bool FPRs, uint32_t GPRFillMask, uint32_t FPRF | |||
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| if (FillP2) { | |||
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Perhaps you can drop this and change to a simple sve supported check, as is it'll not work for the FillSRA in dispatcher and a single ptrue is cheap enough not to matter
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But if we always fill p2 when SVE is supported this whole optimization makes no longer sense from a size pov. If we do it without actually needing to use p2 for the SVE store optimization then we are definitely pessimizing things.
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Spills are rare enough that a ptrue certainly isn't going to change anything, the opt still works within code blocks which is where it matters as they can be much hotter
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Humm, I still didn't manage to get SRA to work. The RA algo is still allocating the wrong register to the predicate register, i.e. p5. It should be p2, which is the SRA register I selected to use in DecodeSRAReg but it's not working. First time I am looking at this code so slightly confused about this.
At the same time, i am wondering if this is necessary. What's the advantage of using SRA over just hardcoding p2 usage in the instructions, like done with PRED_TMP_16B for example?
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Humm, I still didn't manage to get SRA to work. The RA algo is still allocating the wrong register to the predicate register, i.e. p5. It should be p2, which is the SRA register I selected to use in DecodeSRAReg but it's not working. First time I am looking at this code so slightly confused about this.
At the same time, i am wondering if this is necessary. What's the advantage of using SRA over just hardcoding p2 usage in the instructions, like done with
PRED_TMP_16Bfor example?
I don't think there are any, that would work fine too you'd just need to modify the store op to have some way to indicate that and you can drop LoadSVEOptPredicate and rely on it being set in FillSpecialRegs as PRED_TMP_16B is (you probably want to keep InitPredicate for other future users)
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(can drop this as it's called in FillSpecialRegs)
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Whenever the control float leaves the block, it might clobber the predicate register so we reset the cache whenever that happens. The difficulty here is that the cache is valid only during IR generation so we need to make sure we catch all the cases during this pass where the execution might leave the block. Fixes FEX-Emu#4264
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| @@ -1631,9 +1631,13 @@ DEF_OP(StoreMemPredicate) { | |||
| DEF_OP(LoadMemPredicate) { | |||
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I think it makes sense to introduce a new op here, or at least rename/fixup the description as appropriate
| @@ -822,6 +824,10 @@ void Arm64Emitter::FillStaticRegs(bool FPRs, uint32_t GPRFillMask, uint32_t FPRF | |||
| } | |||
| } | |||
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| if (FillP2) { | |||
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(can drop this as it's called in FillSpecialRegs)
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| if (FillP2) { | ||
| ptrue(ARMEmitter::SubRegSize::i16Bit, PRED_X87_SVEOPT, ARMEmitter::PredicatePattern::SVE_VL5); | ||
| } |
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you can just move this into the above if and drop the FillP2 check
Alternative implementation to #4274
In draft mode as it's incomplete and broken.