#1318: fix documentation

JonathanSalwan · Jul 25, 2024 · 93e493a · 93e493a
1 parent 6ee4e2c
commit 93e493a
Show file tree

Hide file tree

Showing 4 changed files with 14 additions and 21 deletions.
diff --git a/.build_number b/.build_number
@@ -1 +1 @@
-1592
+1593
diff --git a/doc/extract_doc.py b/doc/extract_doc.py
@@ -68,7 +68,7 @@
         for line in f.readlines():
             if line.startswith("REG_SPEC") or line.startswith("SYS_REG_SPEC"):
                 args = line[line.find("(") + 1: line.find(")")].split(", ")
-                rv64_regs.append(args[0])
+                rv64_regs.append(args[1])
 
     with open(os.path.join(BUILD_DIR, "rv64_reg"), "w") as out:
         out.write('<ul>\n')
@@ -83,7 +83,7 @@
         for line in f.readlines():
             if line.startswith("REG_SPEC") or line.startswith("SYS_REG_SPEC"):
                 args = line[line.find("(") + 1: line.find(")")].split(", ")
-                rv32_regs.append(args[0])
+                rv32_regs.append(args[1])
 
     with open(os.path.join(BUILD_DIR, "rv32_reg"), "w") as out:
         out.write('<ul>\n')

diff --git a/src/libtriton/arch/riscv/riscvSemantics.cpp b/src/libtriton/arch/riscv/riscvSemantics.cpp
@@ -13,17 +13,6 @@
 
 
 
-/*! \page SMT_Semantics_Supported_page SMT Semantics Supported
-    \brief [**internal**] All information about the supported semantics.
-
-- \ref SMT_aarch64_Semantics_Supported_page
-- \ref SMT_arm32_Semantics_Supported_page
-- \ref SMT_riscv_Semantics_Supported_page
-- \ref SMT_x86_Semantics_Supported_page
-
-*/
-
-
 /*! \page SMT_riscv_Semantics_Supported_page RV32 and RV64 SMT semantics supported
     \brief [**internal**] List of the supported semantics for the RV32 and RV64 architectures.
 
@@ -92,8 +81,10 @@ SUBW  (pseudo: NEGW)          | Subtract word / 64-bit only /
 SW                            | Store register word
 XOR                           | Exclusive or (register)
 XORI (pseudo: NOT)            | Exclusive or (immediate)
-------------------------------|------------
-                    Compressed instructions
+
+&nbsp;
+
+Mnemonic (compressed inst.)   | Description
 ------------------------------|------------
 C.ADD                         | Add (register)
 C.ADDI                        | Add (immediate)
@@ -1604,11 +1595,12 @@ namespace triton {
 
 
       void riscvSemantics::jalr_s(triton::arch::Instruction& inst) {
-        /* x[rd] := pc + 4; pc := (x[rs] + imm) & ~1
-        /* Check for possible pseudo instructions
-           ret     -- [jalr x0, x1, 0] -- Return from subroutine
-           jr rs   -- [jalr x0, rs, 0] -- Jump register
-           jalr rs -- [jalr x1, rs, 0] -- Jump and link register
+        /*
+         * x[rd] := pc + 4; pc := (x[rs] + imm) & ~1
+         * Check for possible pseudo instructions
+         * ret     -- [jalr x0, x1, 0] -- Return from subroutine
+         * jr rs   -- [jalr x0, rs, 0] -- Jump register
+         * jalr rs -- [jalr x1, rs, 0] -- Jump and link register
          */
         auto mnem = inst.getDisassembly();
         if (mnem[2] != 'l') { jalr_no_link_s(inst); return; } // ret & jr semantics

diff --git a/src/libtriton/arch/x86/x86Semantics.cpp b/src/libtriton/arch/x86/x86Semantics.cpp
@@ -18,6 +18,7 @@
 
 - \ref SMT_aarch64_Semantics_Supported_page
 - \ref SMT_arm32_Semantics_Supported_page
+- \ref SMT_riscv_Semantics_Supported_page
 - \ref SMT_x86_Semantics_Supported_page
 
 */