pyfmt

KULeuven-MICAS · Feb 18, 2025 · 2a66e7d · 2a66e7d
1 parent 11e4dc7
commit 2a66e7d
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Showing 2 changed files with 6 additions and 2 deletions.
diff --git a/target/snitch_cluster/sw/apps/snax-gemmx-conv/data/datagen.py b/target/snitch_cluster/sw/apps/snax-gemmx-conv/data/datagen.py
@@ -131,7 +131,9 @@ def emit_conv_data(**kwargs):
     if broadcast_C == 1:
         assert meshCol * output_data_width % bankWidth == 0
         # Note: if C is hanged to wide ports, the mimimum number of bits to enable is multipliers of 8 (8 narrow channels equal to 1 wide channel)
-        channel_en_C_1_bits = int((meshCol * output_data_width / bankWidth + 7 ) // 8 * 8)
+        channel_en_C_1_bits = int(
+            (meshCol * output_data_width / bankWidth + 7) // 8 * 8
+        )
         # Generate the elements
         channel_en_C = [0] * enabled_channel_CSR_num  # Initialize with zeros
 

diff --git a/target/snitch_cluster/sw/apps/snax-gemmx-matmul/data/datagen.py b/target/snitch_cluster/sw/apps/snax-gemmx-matmul/data/datagen.py
@@ -257,7 +257,9 @@ def emit_matmul_data(**kwargs):
     if broadcast_C == 1:
         assert meshCol * output_data_width % bankWidth == 0
         # Note: if C is hanged to wide ports, the mimimum number of bits to enable is multipliers of 8 (8 narrow channels equal to 1 wide channel)
-        channel_en_C_1_bits = int((meshCol * output_data_width / bankWidth + 7 ) // 8 * 8)
+        channel_en_C_1_bits = int(
+            (meshCol * output_data_width / bankWidth + 7) // 8 * 8
+        )
         # Generate the elements
         channel_en_C = [0] * enabled_channel_CSR_num  # Initialize with zeros