#94: Fixed specs reference for constants

sxpat/synthesis.py

@@ -389,7 +389,7 @@ def __intact_part_assigns(self):
         # write constants that are not output constants
         for n_idx, n_name in self.graph.constant_dict.items():
             const_succs = list(self.graph.graph.successors(n_name))
-            if len(const_succs) == 1 and const_succs[0] in self.graph.output_dict.values() and self.__template_specs.constants == ConstantsType.ALWAYS:
+            if len(const_succs) == 1 and const_succs[0] in self.graph.output_dict.values() and self.specs.constants == ConstantsType.ALWAYS:
                 # skip if it is a constant output
                 continue
 
@@ -710,7 +710,7 @@ def __annotated_graph_to_verilog_shared(self):
             output_assigns = self.__output_assigns()
 
             #
-            json_model_constants_rewrite = self.__json_model_output_constants_assign(idx) if self.__template_specs.constants == ConstantsType.ALWAYS else ''
+            json_model_constants_rewrite = self.__json_model_output_constants_assign(idx) if self.specs.constants == ConstantsType.ALWAYS else ''
 
             ver_str += (
                 module_signature
@@ -777,7 +777,7 @@ def __annotated_graph_to_verilog(self) -> List[AnyStr]:
             json_model_and_subgraph_outputs_assigns = self.__json_model_lpp_and_subgraph_output_assigns(idx)
 
             #
-            json_model_constants_rewrite = self.__json_model_output_constants_assign(idx) if self.__template_specs.constants == ConstantsType.ALWAYS else ''
+            json_model_constants_rewrite = self.__json_model_output_constants_assign(idx) if self.specs.constants == ConstantsType.ALWAYS else ''
 
             # 11. the intact assigns
             intact_assigns = self.__intact_part_assigns()