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VM with basic riscv32i support #13

Merged
merged 9 commits into from
Sep 13, 2024
Merged

VM with basic riscv32i support #13

merged 9 commits into from
Sep 13, 2024

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bigspider
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@bigspider bigspider commented Sep 2, 2024

Adds a trait hierarchy, and basic implementations, for the main objects that will be used in the VM.

The objects are generic, so they are part of the common module. This will allow to easily test and develop the VM natively, while the Vanadium VM can reuse the same VM while just plugging the implementation of the OutsourcedMemory.

The CPU has support for all the opcodes in the riscv32i instruction set, except FENCE, PAUSE, BREAK and ECALL. Implementations of Ecalls will be done in followups.

The Risc-V CPU was integrated in the Vanadium app. At this time, running the vnd-test V-App continues until the first ECALL, and crashes there.

Closes: #5

@bigspider bigspider mentioned this pull request Sep 4, 2024
@bigspider bigspider changed the title Opcodes in riscv32i VM with basic riscv32i support Sep 4, 2024
@bigspider bigspider marked this pull request as ready for review September 4, 2024 15:58
@bigspider bigspider merged commit d8b2afd into master Sep 13, 2024
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@bigspider bigspider deleted the riscv32i branch September 13, 2024 12:51
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Implement the basic Risc-V VM in the Vanadium VM app
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