Skip to content
This repository has been archived by the owner on Jul 22, 2022. It is now read-only.

Commit

Permalink
要提交的变更:
Browse files Browse the repository at this point in the history
	新文件:   reference/stackframe/stackframe.cpp
	新文件:   reference/stackframe/stackframe.rs
  • Loading branch information
u8cat committed Jul 3, 2022
1 parent 1242d41 commit e5ec248
Show file tree
Hide file tree
Showing 2 changed files with 150 additions and 0 deletions.
76 changes: 76 additions & 0 deletions reference/stackframe/stackframe.cpp
Original file line number Diff line number Diff line change
@@ -0,0 +1,76 @@
#include <fmt/core.h>
#include <utility>

struct RegGenExcept {
size_t t0; //0
size_t t1; //8
size_t t2; //16
size_t t3; //24
size_t t4; //32
size_t t5; //40
size_t t6; //48
size_t a0; //56
size_t a1; //64
size_t a2; //72
size_t a3; //80
size_t a4; //88
size_t a5; //96
size_t a6; //104
size_t a7; //112
size_t ra; //120
size_t pc; //128
size_t sstatus; //136
size_t sp; //144
};

extern "C" {
void __rkplat_exception_handle(size_t cause, RegGenExcept &regs);
}

void __rkplat_exception_handle(size_t cause, RegGenExcept &regs) {
using std::make_pair;
auto [description,panic] = [&]{ switch (cause) {
case 0: return make_pair ("Instruction address misaligned.",true);
case 1 : return make_pair("Instruction access fault.",true);
case 2 : return make_pair("Illegal instruction.",true);
case 3 : return make_pair("Breakpoint.",false);
case 4 : return make_pair("Load address misaligned.",true);
case 5 : return make_pair("Load access fault.",true);
case 6 : return make_pair("Store/AMO address misaligned.",true);
case 7 : return make_pair("Store/AMO access fault.",true);
case 8 : return make_pair("Environment call from U-mode.",false);
case 9 : return make_pair("Environment call from S-mode.",false);
case 12: return make_pair("Instruction page fault.",true);
case 13: return make_pair("Load page fault.",true);
case 15: return make_pair("Store/AMO page fault.",true);
default: return make_pair("Unknown error.",true);
}}();
fmt::print("{} (code=0x{:02x})\n",description,cause);
fmt::print("registers:\n");
fmt::print("a0 = 0x{:016x}\n",regs.a0);
fmt::print("a1 = 0x{:016x}\n",regs.a1);
fmt::print("a2 = 0x{:016x}\n",regs.a2);
fmt::print("a3 = 0x{:016x}\n",regs.a3);
fmt::print("a4 = 0x{:016x}\n",regs.a4);
fmt::print("a5 = 0x{:016x}\n",regs.a5);
fmt::print("a6 = 0x{:016x}\n",regs.a6);
fmt::print("a7 = 0x{:016x}\n",regs.a7);
fmt::print("t0 = 0x{:016x}\n",regs.t0);
fmt::print("t1 = 0x{:016x}\n",regs.t1);
fmt::print("t2 = 0x{:016x}\n",regs.t2);
fmt::print("t3 = 0x{:016x}\n",regs.t3);
fmt::print("t4 = 0x{:016x}\n",regs.t4);
fmt::print("t5 = 0x{:016x}\n",regs.t5);
fmt::print("t6 = 0x{:016x}\n",regs.t6);
fmt::print("ra = 0x{:016x}\n",regs.ra);
fmt::print("sp = 0x{:016x}\n",regs.sp);
fmt::print("pc = 0x{:016x}\n",regs.pc);
if(cause != 1)
fmt::print("instruction = 0x{:016x}\n",*(reinterpret_cast<size_t*>(regs.pc)));
if(panic)
abort();
}

int main() {

}
74 changes: 74 additions & 0 deletions reference/stackframe/stackframe.rs
Original file line number Diff line number Diff line change
@@ -0,0 +1,74 @@
#[repr(C)]
#[derive(Debug)]
#[derive(Default)]
pub struct RegGenExcept {
pub t0: usize, //0
pub t1: usize, //8
pub t2: usize, //16
pub t3: usize, //24
pub t4: usize, //32
pub t5: usize, //40
pub t6: usize, //48
pub a0: usize, //56
pub a1: usize, //64
pub a2: usize, //72
pub a3: usize, //80
pub a4: usize, //88
pub a5: usize, //96
pub a6: usize, //104
pub a7: usize, //112
pub ra: usize, //120
pub pc: usize, //128
pub sstatus: usize, //136
pub sp: usize, //144
}

#[no_mangle]
unsafe extern "C" fn __rkplat_exception_handle(cause: usize, regs: &mut RegGenExcept) {
let (description,panic) = match cause {
0 => ("Instruction address misaligned.",true),
1 => ("Instruction access fault.",true),
2 => ("Illegal instruction.",true),
3 => ("Breakpoint.",false),
4 => ("Load address misaligned.",true),
5 => ("Load access fault.",true),
6 => ("Store/AMO address misaligned.",true),
7 => ("Store/AMO access fault.",true),
8 => ("Environment call from U-mode.",false),
9 => ("Environment call from S-mode.",false),
12 => ("Instruction page fault.",true),
13 => ("Load page fault.",true),
15 => ("Store/AMO page fault.",true),
_ => ("Unknown error.",true),
};
println!("{} (code=0x{:02x})",description,cause);
println!("registers:");
println!("a0 = 0x{:016x}",regs.a0);
println!("a1 = 0x{:016x}",regs.a1);
println!("a2 = 0x{:016x}",regs.a2);
println!("a3 = 0x{:016x}",regs.a3);
println!("a4 = 0x{:016x}",regs.a4);
println!("a5 = 0x{:016x}",regs.a5);
println!("a6 = 0x{:016x}",regs.a6);
println!("a7 = 0x{:016x}",regs.a7);
println!("t0 = 0x{:016x}",regs.t0);
println!("t1 = 0x{:016x}",regs.t1);
println!("t2 = 0x{:016x}",regs.t2);
println!("t3 = 0x{:016x}",regs.t3);
println!("t4 = 0x{:016x}",regs.t4);
println!("t5 = 0x{:016x}",regs.t5);
println!("t6 = 0x{:016x}",regs.t6);
println!("ra = 0x{:016x}",regs.ra);
println!("sp = 0x{:016x}",regs.sp);
println!("pc = 0x{:016x}",regs.pc);
if cause != 1 {
println!("instruction = 0x{:016x}",*(regs.pc as *const usize));
}
if panic {
panic!();
}
}

fn main() {

}

0 comments on commit e5ec248

Please sign in to comment.