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Add some bsp drivers for HC32F448 and provide test examples for the bsp drivers. #9857

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Add some bsp drivers for HC32F448 and provide test examples for the bsp drivers. #9857

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41c781d
Add some bsp drivers for HC32F448.
Jan 2, 2025
a8b5ab7
Modify function return value.
Jan 2, 2025
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274 changes: 246 additions & 28 deletions bsp/hc32/ev_hc32f448_lqfp80/.config
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22 changes: 15 additions & 7 deletions bsp/hc32/ev_hc32f448_lqfp80/.cproject
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10 changes: 10 additions & 0 deletions bsp/hc32/ev_hc32f448_lqfp80/.project
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Expand Up @@ -64,5 +64,15 @@
<type>2</type>
<locationURI>$%7BPARENT-1-PROJECT_LOC%7D/libraries</locationURI>
</link>
<link>
<name>rt-thread/bsp/hc32/platform</name>
<type>2</type>
<locationURI>PARENT-1-PROJECT_LOC/platform</locationURI>
</link>
<link>
<name>rt-thread/bsp/hc32/tests</name>
<type>2</type>
<locationURI>PARENT-1-PROJECT_LOC/tests</locationURI>
</link>
</linkedResources>
</projectDescription>
12 changes: 11 additions & 1 deletion bsp/hc32/ev_hc32f448_lqfp80/README.md
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Expand Up @@ -57,11 +57,21 @@ EV_F448_LQ80_Rev1.0 开发板常用 **板载资源** 如下：

| **片上外设** | **支持情况** | **备注** |
| :------------ | :-----------: | :-----------------------------------: |
| Crypto | 支持 | AES, CRC, HASH, RNG, UID |
| DAC | 支持 | |
| ADC | 支持 | ADC1: CH10, CH11, <br>ADC3: CH1 |
| CAN | 支持 | CAN1、CAN2 |
| GPIO | 支持 | PA0, PA1... PH2 ---> PIN: 0, 1...82 |
| I2C | 支持 | 软件模拟<br>硬件I2C1~2<br>I2C1支持EEPROM（BL24C256） |
| PM | 支持 | |
| Lptimer | 支持 | |
| Hwtimer | 支持 | Hwtimer1~5 |
| Pulse_encoder | 支持 | |
| PWM | 支持 | |
| RTC | 支持 | 闹钟精度为1分钟 |
| WDT | 支持 | |
| I2C | 支持 | 软件、硬件 I2C |
| QSPI | 支持 | |
| SPI | 支持 | SPI1~3<br>SPI1支持W25Q |
| UART | 支持 | UART1~6<br>UART2为console使用 |

Expand Down Expand Up @@ -125,4 +135,4 @@ msh >

维护人:

- [小华半导体MCU](https://www.xhsc.com.cn)，邮箱：<xhsc_mcu@xhsc.com.cn>
- [小华半导体MCU](https://www.xhsc.com.cn)，邮箱：<xhsc_ae_cd_ap@xhsc.com.cn>
8 changes: 7 additions & 1 deletion bsp/hc32/ev_hc32f448_lqfp80/SConstruct
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Expand Up @@ -56,7 +56,13 @@ objs.extend(SConscript(os.path.join(libraries_path_prefix, hc32_library, 'SConsc
# include drivers
objs.extend(SConscript(os.path.join(libraries_path_prefix, 'hc32_drivers', 'SConscript')))

objs.extend(SConscript(os.path.join(os.getcwd(), 'board', 'ports', 'SConscript')))
# include platform
platform_path_prefix = os.path.dirname(SDK_ROOT) + '/platform'
objs.extend(SConscript(os.path.join(platform_path_prefix, 'SConscript')))

# include tests
test_path_prefix = os.path.dirname(SDK_ROOT) + '/tests'
objs.extend(SConscript(os.path.join(test_path_prefix, 'SConscript')))

# make a building
DoBuilding(TARGET, objs)
23 changes: 14 additions & 9 deletions bsp/hc32/ev_hc32f448_lqfp80/board/Kconfig
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Expand Up @@ -42,12 +42,17 @@ menu "Onboard Peripheral Drivers"
select RT_USING_MTD_NOR
default n

config BSP_USING_EXT_IO
bool
default y

endmenu

menu "On-chip Peripheral Drivers"
config BSP_USING_GPIO
bool "Enable GPIO"
select RT_USING_PIN
select BSP_USING_TCA9539
default y

menuconfig BSP_USING_UART
Expand Down Expand Up @@ -212,12 +217,12 @@ menu "On-chip Peripheral Drivers"
if BSP_USING_I2C1_SW
config BSP_I2C1_SCL_PIN
int "i2c1 scl pin number"
range 1 176
default 51
range 1 80
default 10
config BSP_I2C1_SDA_PIN
int "I2C1 sda pin number"
range 1 176
default 90
range 1 80
default 9
endif
endif

Expand Down Expand Up @@ -368,9 +373,6 @@ menu "On-chip Peripheral Drivers"
config BSP_USING_DAC1
bool "using dac1"
default n
config BSP_USING_DAC2
bool "using dac2"
default n
endif

menuconfig BSP_USING_CAN
Expand Down Expand Up @@ -418,10 +420,13 @@ menu "On-chip Peripheral Drivers"
default BSP_RTC_USING_XTAL32

config BSP_RTC_USING_XTAL32
bool "RTC USING XTAL32"
bool "RTC Using XTAL32"

config BSP_RTC_USING_LRC
bool "RTC USING LRC"
bool "RTC Using LRC"

config BSP_RTC_USING_XTAL_DIV
bool "RTC Using XTAL Division"
endchoice
endif

Expand Down
12 changes: 3 additions & 9 deletions bsp/hc32/ev_hc32f448_lqfp80/board/SConscript
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Expand Up @@ -12,24 +12,18 @@ board.c
board_config.c
''')

if GetDepend(['BSP_USING_TCA9539']):
src += Glob('ports/tca9539.c')

if GetDepend(['BSP_USING_SPI_FLASH']):
src += Glob('ports/drv_spi_flash.c')

path = [cwd]
path += [cwd + '/ports']
path += [cwd + '/config']

startup_path_prefix = SDK_LIB

if rtconfig.PLATFORM in ['gcc']:
src += [startup_path_prefix + '/hc32f448_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/GCC/startup_hc32f448.S']
src += [startup_path_prefix + '/hc32f448_ddl/cmsis/Device/HDSC/hc32f4xx/Source/GCC/startup_hc32f448.S']
elif rtconfig.PLATFORM in ['armcc', 'armclang']:
src += [startup_path_prefix + '/hc32f448_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/ARM/startup_hc32f448.s']
src += [startup_path_prefix + '/hc32f448_ddl/cmsis/Device/HDSC/hc32f4xx/Source/ARM/startup_hc32f448.s']
elif rtconfig.PLATFORM in ['iccarm']:
src += [startup_path_prefix + '/hc32f448_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/startup_hc32f448.s']
src += [startup_path_prefix + '/hc32f448_ddl/cmsis/Device/HDSC/hc32f4xx/Source/IAR/startup_hc32f448.s']

CPPDEFINES = ['HC32F448', '__DEBUG']
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
Expand Down
14 changes: 14 additions & 0 deletions bsp/hc32/ev_hc32f448_lqfp80/board/board.c
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Expand Up @@ -7,6 +7,7 @@
* Change Logs:
* Date Author Notes
* 2024-02-20 CDT first version
* 2024-06-07 CDT Add XTAL divider config code for RTC
*/

#include "board.h"
Expand Down Expand Up @@ -41,6 +42,9 @@ void SystemClock_Config(void)
#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM)
stc_clock_xtal32_init_t stcXtal32Init;
#endif
#if defined(BSP_RTC_USING_XTAL_DIV)
stc_clock_xtaldiv_init_t stcXtaldivInit;
#endif

/* PCLK0, HCLK Max 200MHz */
/* PCLK1, PCLK4 Max 100MHz */
Expand Down Expand Up @@ -87,6 +91,16 @@ void SystemClock_Config(void)
stcXtal32Init.u8Filter = CLK_XTAL32_FILTER_RUN_MD;
(void)CLK_Xtal32Init(&stcXtal32Init);
#endif

#if defined(BSP_RTC_USING_XTAL_DIV)
/* Xtal Div config */
(void)CLK_XtalDivStructInit(&stcXtaldivInit);
/* 8000000Hz / 32768Hz = 0x7A12 / 0x80 */
stcXtaldivInit.u32Num = 0x7A12UL;
stcXtaldivInit.u32Den = 0x80UL;
stcXtaldivInit.u32State = CLK_XTALDIV_ON;
(void)CLK_XtalDivInit(&stcXtaldivInit);
#endif
}

/** Peripheral Clock Configuration
Expand Down
4 changes: 2 additions & 2 deletions bsp/hc32/ev_hc32f448_lqfp80/board/board_config.c
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Expand Up @@ -11,7 +11,7 @@

#include <rtdevice.h>
#include "board_config.h"
#include "tca9539.h"
#include "tca9539_port.h"

/**
* The below functions will initialize HC32 board.
Expand Down Expand Up @@ -130,7 +130,7 @@ rt_err_t rt_hw_board_dac_init(CM_DAC_TypeDef *DACx)
switch ((rt_uint32_t)DACx)
{
#if defined(BSP_USING_DAC1)
case (rt_uint32_t)CM_DAC1:
case (rt_uint32_t)CM_DAC:
(void)GPIO_Init(DAC1_CH1_PORT, DAC1_CH1_PIN, &stcGpioInit);
(void)GPIO_Init(DAC1_CH2_PORT, DAC1_CH2_PIN, &stcGpioInit);
break;
Expand Down
16 changes: 8 additions & 8 deletions bsp/hc32/ev_hc32f448_lqfp80/board/board_config.h
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Expand Up @@ -78,17 +78,17 @@

/*********** ADC configure *********/
#if defined(BSP_USING_ADC1)
#define ADC1_CH_PORT (GPIO_PORT_C)
#define ADC1_CH_PORT (GPIO_PORT_C) /* Default ADC12_IN10 */
#define ADC1_CH_PIN (GPIO_PIN_00)
#endif

#if defined(BSP_USING_ADC2)
#define ADC2_CH_PORT (GPIO_PORT_C)
#define ADC2_CH_PIN (GPIO_PIN_01)
#define ADC2_CH_PORT (GPIO_PORT_A) /* Default ADC12_IN4 */
#define ADC2_CH_PIN (GPIO_PIN_04)
#endif

#if defined(BSP_USING_ADC3)
#define ADC3_CH_PORT (GPIO_PORT_E)
#define ADC3_CH_PORT (GPIO_PORT_E) /* Default ADC3_IN1 */
#define ADC3_CH_PIN (GPIO_PIN_03)
#endif

Expand Down Expand Up @@ -296,11 +296,11 @@

#if defined(BSP_USING_TMR6_PULSE_ENCODER)
#if defined(BSP_USING_PULSE_ENCODER_TMR6_1)
#define PULSE_ENCODER_TMR6_1_A_PORT (GPIO_PORT_A)
#define PULSE_ENCODER_TMR6_1_A_PIN (GPIO_PIN_08)
#define PULSE_ENCODER_TMR6_1_A_PORT (GPIO_PORT_B)
#define PULSE_ENCODER_TMR6_1_A_PIN (GPIO_PIN_05)
#define PULSE_ENCODER_TMR6_1_A_PIN_FUNC (GPIO_FUNC_3)
#define PULSE_ENCODER_TMR6_1_B_PORT (GPIO_PORT_A)
#define PULSE_ENCODER_TMR6_1_B_PIN (GPIO_PIN_07)
#define PULSE_ENCODER_TMR6_1_B_PORT (GPIO_PORT_B)
#define PULSE_ENCODER_TMR6_1_B_PIN (GPIO_PIN_13)
#define PULSE_ENCODER_TMR6_1_B_PIN_FUNC (GPIO_FUNC_3)
#endif /* BSP_USING_PULSE_ENCODER_TMR6_1 */
#endif /* BSP_USING_TMR6_PULSE_ENCODER */
Expand Down
7 changes: 3 additions & 4 deletions bsp/hc32/ev_hc32f448_lqfp80/board/config/adc_config.h
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@@ -1,5 +1,4 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
* Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
Expand Down Expand Up @@ -32,7 +31,7 @@ extern "C" {
.hard_trig_src = ADC_HARDTRIG_EVT0, \
.internal_trig0_comtrg0_enable = RT_FALSE, \
.internal_trig0_comtrg1_enable = RT_FALSE, \
.internal_trig0_sel = EVT_SRC_TMR0_1_CMP_A, \
.internal_trig0_sel = EVT_SRC_TMR0_1_CMP_B, \
.internal_trig1_comtrg0_enable = RT_FALSE, \
.internal_trig1_comtrg1_enable = RT_FALSE, \
.internal_trig1_sel = EVT_SRC_MAX, \
Expand Down Expand Up @@ -75,7 +74,7 @@ extern "C" {
.hard_trig_src = ADC_HARDTRIG_EVT0, \
.internal_trig0_comtrg0_enable = RT_FALSE, \
.internal_trig0_comtrg1_enable = RT_FALSE, \
.internal_trig0_sel = EVT_SRC_TMR0_1_CMP_A, \
.internal_trig0_sel = EVT_SRC_TMR0_1_CMP_B, \
.internal_trig1_comtrg0_enable = RT_FALSE, \
.internal_trig1_comtrg1_enable = RT_FALSE, \
.internal_trig1_sel = EVT_SRC_MAX, \
Expand Down Expand Up @@ -118,7 +117,7 @@ extern "C" {
.hard_trig_src = ADC_HARDTRIG_EVT0, \
.internal_trig0_comtrg0_enable = RT_FALSE, \
.internal_trig0_comtrg1_enable = RT_FALSE, \
.internal_trig0_sel = EVT_SRC_TMR0_1_CMP_A, \
.internal_trig0_sel = EVT_SRC_TMR0_1_CMP_B, \
.internal_trig1_comtrg0_enable = RT_FALSE, \
.internal_trig1_comtrg1_enable = RT_FALSE, \
.internal_trig1_sel = EVT_SRC_MAX, \
Expand Down
12 changes: 1 addition & 11 deletions bsp/hc32/ev_hc32f448_lqfp80/board/config/dac_config.h
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@@ -1,6 +1,5 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
* Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
Expand All @@ -27,15 +26,6 @@ extern "C" {
#endif /* DAC1_INIT_PARAMS */
#endif /* BSP_USING_DAC1 */

#ifdef BSP_USING_DAC2
#ifndef DAC2_INIT_PARAMS
#define DAC2_INIT_PARAMS \
{ \
.name = "dac2", \
}
#endif /* DAC2_INIT_PARAMS */
#endif /* BSP_USING_DAC2 */

#ifdef __cplusplus
}
#endif
Expand Down
10 changes: 10 additions & 0 deletions bsp/hc32/ev_hc32f448_lqfp80/board/config/dma_config.h
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Expand Up @@ -193,6 +193,16 @@ extern "C" {
#define UART1_RX_DMA_IRQn BSP_DMA2_CH0_IRQ_NUM
#define UART1_RX_DMA_INT_PRIO BSP_DMA2_CH0_IRQ_PRIO
#define UART1_RX_DMA_INT_SRC INT_SRC_DMA2_TC0

#elif defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_INSTANCE)
#define QSPI_DMA_INSTANCE CM_DMA2
#define QSPI_DMA_CHANNEL DMA_CH0
#define QSPI_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
#define QSPI_DMA_TRIG_SELECT AOS_DMA2_0
#define QSPI_DMA_TRANS_FLAG DMA_FLAG_TC_CH0
#define QSPI_DMA_IRQn BSP_DMA2_CH0_IRQ_NUM
#define QSPI_DMA_INT_PRIO BSP_DMA2_CH0_IRQ_PRIO
#define QSPI_DMA_INT_SRC INT_SRC_DMA2_TC0
#endif

/* DMA2 ch1 */
Expand Down
49 changes: 49 additions & 0 deletions bsp/hc32/ev_hc32f448_lqfp80/board/config/irq_config.h
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Expand Up @@ -158,6 +158,11 @@ extern "C" {
#define BSP_SPI3_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif

#if defined (BSP_USING_QSPI)
#define BSP_QSPI_ERR_IRQ_NUM QSPI_IRQn
#define BSP_QSPI_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif /* BSP_USING_QSPI */

#if defined(BSP_USING_TMRA_1)
#define BSP_USING_TMRA_1_IRQ_NUM TMRA_1_OVF_UDF_IRQn
#define BSP_USING_TMRA_1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
Expand Down Expand Up @@ -193,6 +198,50 @@ extern "C" {
#define BSP_RTC_ALARM_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* RT_USING_ALARM */

#if defined(BSP_USING_PULSE_ENCODER_TMRA_1)
#define BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_NUM TMRA_1_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_NUM TMRA_1_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* BSP_USING_PULSE_ENCODER_TMRA_1 */
#if defined(BSP_USING_PULSE_ENCODER_TMRA_2)
#define BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_NUM TMRA_2_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_NUM TMRA_2_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* BSP_USING_PULSE_ENCODER_TMRA_2 */
#if defined(BSP_USING_PULSE_ENCODER_TMRA_3)
#define BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_NUM TMRA_3_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_NUM TMRA_3_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* BSP_USING_PULSE_ENCODER_TMRA_3 */
#if defined(BSP_USING_PULSE_ENCODER_TMRA_4)
#define BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_NUM TMRA_4_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_NUM TMRA_4_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* BSP_USING_PULSE_ENCODER_TMRA_4 */
#if defined(BSP_USING_PULSE_ENCODER_TMRA_5)
#define BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_NUM TMRA_5_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_NUM TMRA_5_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* BSP_USING_PULSE_ENCODER_TMRA_5 */

#if defined(BSP_USING_PULSE_ENCODER_TMR6_1)
#define BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_NUM TMR6_1_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_NUM TMR6_1_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* BSP_USING_PULSE_ENCODER_TMR6_1 */
#if defined(BSP_USING_PULSE_ENCODER_TMR6_2)
#define BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_NUM TMR6_2_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_NUM TMR6_2_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* BSP_USING_PULSE_ENCODER_TMR6_2 */

#ifdef __cplusplus
}
#endif
Expand Down
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