This is NOT a project but merely a collection of the exams for a course I took back in my bachelor programme.
Source codes may be either uncommented, or commented in Italian, or in a relatively broken English. I translated the original exam descriptions into English.
For these exams we were asked to provide a project which included multiple simulations (testbenches). So these solutions were all tested and working properly. We used Xilinx ISE to write the projects and Modelsim Simulation for the testbenches. I'm not sure these still exist. I'm only sharing the source code, not the procedure to set up a simulation.
I hope this may be useful to anyone who wants to learn VHDL.
PS. If you think these are too simple to be final exams, notice that the VHDL part was only 10% of the whole exam.