8318225: RISC-V: C2 UModI

8318226: RISC-V: C2 UModL Reviewed-by: luhenry, rehn, fyang
SAP · Oct 28, 2023 · 1ec0d02 · 1ec0d02
1 parent 96bec35
commit 1ec0d02
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Showing 2 changed files with 46 additions and 2 deletions.
diff --git a/src/hotspot/cpu/riscv/macroAssembler_riscv.cpp b/src/hotspot/cpu/riscv/macroAssembler_riscv.cpp
@@ -2408,7 +2408,12 @@ int MacroAssembler::corrected_idivl(Register result, Register rs1, Register rs2,
       divuw(result, rs1, rs2);
     }
   } else {
-    remw(result, rs1, rs2); // result = rs1 % rs2;
+    // result = rs1 % rs2;
+    if (is_signed) {
+      remw(result, rs1, rs2);
+    } else {
+      remuw(result, rs1, rs2);
+    }
   }
   return idivl_offset;
 }
@@ -2435,7 +2440,12 @@ int MacroAssembler::corrected_idivq(Register result, Register rs1, Register rs2,
       divu(result, rs1, rs2);
     }
   } else {
-    rem(result, rs1, rs2); // result = rs1 % rs2;
+    // result = rs1 % rs2;
+    if (is_signed) {
+      rem(result, rs1, rs2);
+    } else {
+      remu(result, rs1, rs2);
+    }
   }
   return idivq_offset;
 }

diff --git a/src/hotspot/cpu/riscv/riscv.ad b/src/hotspot/cpu/riscv/riscv.ad
@@ -2478,6 +2478,14 @@ encode %{
     __ corrected_idivl(dst_reg, src1_reg, src2_reg, /* want_remainder */ true, /* is_signed */ true);
   %}
 
+  enc_class riscv_enc_moduw(iRegI dst, iRegI src1, iRegI src2) %{
+    C2_MacroAssembler _masm(&cbuf);
+    Register dst_reg = as_Register($dst$$reg);
+    Register src1_reg = as_Register($src1$$reg);
+    Register src2_reg = as_Register($src2$$reg);
+    __ corrected_idivl(dst_reg, src1_reg, src2_reg, /* want_remainder */ true, /* is_signed */ false);
+  %}
+
   enc_class riscv_enc_mod(iRegI dst, iRegI src1, iRegI src2) %{
     C2_MacroAssembler _masm(&cbuf);
     Register dst_reg = as_Register($dst$$reg);
@@ -2486,6 +2494,14 @@ encode %{
     __ corrected_idivq(dst_reg, src1_reg, src2_reg, /* want_remainder */ true, /* is_signed */ true);
   %}
 
+  enc_class riscv_enc_modu(iRegI dst, iRegI src1, iRegI src2) %{
+    C2_MacroAssembler _masm(&cbuf);
+    Register dst_reg = as_Register($dst$$reg);
+    Register src1_reg = as_Register($src1$$reg);
+    Register src2_reg = as_Register($src2$$reg);
+    __ corrected_idivq(dst_reg, src1_reg, src2_reg, /* want_remainder */ true, /* is_signed */ false);
+  %}
+
   enc_class riscv_enc_tail_call(iRegP jump_target) %{
     C2_MacroAssembler _masm(&cbuf);
     Register target_reg = as_Register($jump_target$$reg);
@@ -6752,6 +6768,15 @@ instruct modI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
   ins_pipe(ialu_reg_reg);
 %}
 
+instruct UmodI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
+  match(Set dst (UModI src1 src2));
+  ins_cost(IDIVSI_COST);
+  format %{ "remuw  $dst, $src1, $src2\t#@UmodI" %}
+
+  ins_encode(riscv_enc_moduw(dst, src1, src2));
+  ins_pipe(ialu_reg_reg);
+%}
+
 // Long Remainder
 
 instruct modL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
@@ -6763,6 +6788,15 @@ instruct modL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
   ins_pipe(ialu_reg_reg);
 %}
 
+instruct UmodL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
+  match(Set dst (UModL src1 src2));
+  ins_cost(IDIVDI_COST);
+  format %{ "remu  $dst, $src1, $src2\t#@UmodL" %}
+
+  ins_encode(riscv_enc_modu(dst, src1, src2));
+  ins_pipe(ialu_reg_reg);
+%}
+
 // Integer Shifts
 
 // Shift Left Register