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4 changes: 2 additions & 2 deletions source/locale/gettext/SpinalHDL/Data types/Int.pot
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Expand Up @@ -8,7 +8,7 @@ msgid ""
msgstr ""
"Project-Id-Version: SpinalHDL \n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2024-07-20 14:42+0000\n"
"POT-Creation-Date: 2024-08-19 09:12+0000\n"
"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
"Language-Team: LANGUAGE <[email protected]>\n"
Expand Down Expand Up @@ -353,7 +353,7 @@ msgid "Set all bits to the given Bool value"
msgstr ""

#: ../../SpinalHDL/Data types/Int.rst:142
msgid "Notice the difference in behaviour between ``x >> 2`` (result 2 bit narrower than x) and ``x >> U(2)`` (keeping width) due to the Scala type of :code:`y`."
msgid "Notice the difference in behavior between ``x >> 2`` (result 2 bit narrower than x) and ``x >> U(2)`` (keeping width) due to the Scala type of :code:`y`."
msgstr ""

#: ../../SpinalHDL/Data types/Int.rst:145
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6 changes: 3 additions & 3 deletions source/locale/gettext/SpinalHDL/Data types/Vec.pot
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Expand Up @@ -8,7 +8,7 @@ msgid ""
msgstr ""
"Project-Id-Version: SpinalHDL \n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2024-02-13 17:23+0000\n"
"POT-Creation-Date: 2024-08-19 09:12+0000\n"
"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
"Language-Team: LANGUAGE <[email protected]>\n"
Expand Down Expand Up @@ -167,7 +167,7 @@ msgid "x.sCount(condition: T => Bool)"
msgstr ""

#: ../../SpinalHDL/Data types/Vec.rst:150
msgid "Count the number of occurence matching a given condition in the Vec."
msgid "Count the number of occurrence matching a given condition in the Vec."
msgstr ""

#: ../../SpinalHDL/Data types/Vec.rst:151
Expand All @@ -180,7 +180,7 @@ msgid "x.sCount(value: T)"
msgstr ""

#: ../../SpinalHDL/Data types/Vec.rst:153
msgid "Count the number of occurence of a value in the Vec."
msgid "Count the number of occurrence of a value in the Vec."
msgstr ""

#: ../../SpinalHDL/Data types/Vec.rst:155
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4 changes: 2 additions & 2 deletions source/locale/gettext/SpinalHDL/Data types/bool.pot
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Expand Up @@ -8,7 +8,7 @@ msgid ""
msgstr ""
"Project-Id-Version: SpinalHDL \n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2024-01-02 16:09+0000\n"
"POT-Creation-Date: 2024-08-19 09:12+0000\n"
"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
"Language-Team: LANGUAGE <[email protected]>\n"
Expand Down Expand Up @@ -57,7 +57,7 @@ msgid "The ``Bool`` type corresponds to a boolean value (True or False) or a sin
msgstr ""

#: ../../SpinalHDL/Data types/bool.rst:14
msgid "An important concept and rule-of-thumb to understand is that the Scala `Boolean` type is used in places where elaboration-time HDL code-generation decision making is occuring in Scala code. Like any regular program it affects execution of the Scala program that is SpinalHDL at the time the program is being run to perform HDL code generation."
msgid "An important concept and rule-of-thumb to understand is that the Scala `Boolean` type is used in places where elaboration-time HDL code-generation decision making is occurring in Scala code. Like any regular program it affects execution of the Scala program that is SpinalHDL at the time the program is being run to perform HDL code generation."
msgstr ""

#: ../../SpinalHDL/Data types/bool.rst:20
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4 changes: 2 additions & 2 deletions source/locale/gettext/SpinalHDL/Data types/index.pot
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Expand Up @@ -8,7 +8,7 @@ msgid ""
msgstr ""
"Project-Id-Version: SpinalHDL \n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2024-01-26 16:21+0000\n"
"POT-Creation-Date: 2024-08-19 09:12+0000\n"
"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
"Language-Team: LANGUAGE <[email protected]>\n"
Expand Down Expand Up @@ -49,7 +49,7 @@ msgid ":ref:`Floating-point <Floating>` numbers (experimental support)"
msgstr ""

#: ../../SpinalHDL/Data types/index.rst:22
msgid "Additionaly, if you want to assign a don't care value to some hardware, for instance, to provide a default value, you can use the assignDontCare API to do so."
msgid "Additionally, if you want to assign a don't care value to some hardware, for instance, to provide a default value, you can use the assignDontCare API to do so."
msgstr ""

#: ../../SpinalHDL/Data types/index.rst:31
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6 changes: 3 additions & 3 deletions source/locale/gettext/SpinalHDL/Developers area/spinalhdl_datamodel.pot
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Expand Up @@ -8,7 +8,7 @@ msgid ""
msgstr ""
"Project-Id-Version: SpinalHDL \n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2024-01-02 16:09+0000\n"
"POT-Creation-Date: 2024-08-19 09:12+0000\n"
"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
"Language-Team: LANGUAGE <[email protected]>\n"
Expand Down Expand Up @@ -81,7 +81,7 @@ msgid "There are also utilities like *myExpression.remapExpressions(Expression =
msgstr ""

#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:44
msgid "More generaly, most of the graph checks and transformations done by SpinalHDL are located in <https://github.com/SpinalHDL/SpinalHDL/blob/dev/core/src/main/scala/spinal/core/internals/Phase.scala>"
msgid "More generally, most of the graph checks and transformations done by SpinalHDL are located in <https://github.com/SpinalHDL/SpinalHDL/blob/dev/core/src/main/scala/spinal/core/internals/Phase.scala>"
msgstr ""

#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:47
Expand Down Expand Up @@ -133,7 +133,7 @@ msgid "mySignal.removeAssignments : Will remove all previous `:=` affecting the
msgstr ""

#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:157
msgid "mySignal.removeStatement : Will void the existance of the signal"
msgid "mySignal.removeStatement : Will void the existence of the signal"
msgstr ""

#: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:158
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4 changes: 2 additions & 2 deletions source/locale/gettext/SpinalHDL/Developers area/types.pot
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Expand Up @@ -8,7 +8,7 @@ msgid ""
msgstr ""
"Project-Id-Version: SpinalHDL \n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2024-01-02 16:09+0000\n"
"POT-Creation-Date: 2024-08-19 09:12+0000\n"
"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
"Language-Team: LANGUAGE <[email protected]>\n"
Expand Down Expand Up @@ -955,7 +955,7 @@ msgid "Then you can also incorporate a Bundle inside Bundle as deeply as you wan
msgstr ""

#: ../../SpinalHDL/Developers area/types.rst:494
msgid "And finaly instantiate your Bundles inside the hardware :"
msgid "And finally instantiate your Bundles inside the hardware :"
msgstr ""

#: ../../SpinalHDL/Developers area/types.rst:504
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6 changes: 3 additions & 3 deletions source/locale/gettext/SpinalHDL/Examples/Advanced ones/slots.pot
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Expand Up @@ -8,7 +8,7 @@ msgid ""
msgstr ""
"Project-Id-Version: SpinalHDL \n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2024-01-02 16:09+0000\n"
"POT-Creation-Date: 2024-08-19 09:12+0000\n"
"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
"Language-Team: LANGUAGE <[email protected]>\n"
Expand Down Expand Up @@ -37,7 +37,7 @@ msgid "This implementation avoid the use of Vec. Instead, it use Area which allo
msgstr ""

#: ../../SpinalHDL/Examples/Advanced ones/slots.rst:17
msgid "Note that the `reader` API is for SpinalHDL version comming after 1.9.1"
msgid "Note that the `reader` API is for SpinalHDL version coming after 1.9.1"
msgstr ""

#: ../../SpinalHDL/Examples/Advanced ones/slots.rst:24
Expand All @@ -53,7 +53,7 @@ msgid "https://github.com/SpinalHDL/SpinalHDL/blob/008c73f1ce18e294f137efe7a1442
msgstr ""

#: ../../SpinalHDL/Examples/Advanced ones/slots.rst:30
msgid "As well in the DRAM / SDR / DDR memory controller to implement the handeling of multiple memory transactions at once (having multiple precharge / active / read / write running at the same time to improve performances) :"
msgid "As well in the DRAM / SDR / DDR memory controller to implement the handling of multiple memory transactions at once (having multiple precharge / active / read / write running at the same time to improve performances) :"
msgstr ""

#: ../../SpinalHDL/Examples/Advanced ones/slots.rst:32
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6 changes: 3 additions & 3 deletions source/locale/gettext/SpinalHDL/Examples/Advanced ones/timer.pot
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Expand Up @@ -8,7 +8,7 @@ msgid ""
msgstr ""
"Project-Id-Version: SpinalHDL \n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2024-01-02 16:09+0000\n"
"POT-Creation-Date: 2024-08-19 09:12+0000\n"
"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
"Language-Team: LANGUAGE <[email protected]>\n"
Expand Down Expand Up @@ -268,7 +268,7 @@ msgid "0"
msgstr ""

#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:126
msgid "Each ``ticks`` bool can be actived if the corresponding ``ticksEnable`` bit is high."
msgid "Each ``ticks`` bool can be activated if the corresponding ``ticksEnable`` bit is high."
msgstr ""

#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:127
Expand All @@ -284,7 +284,7 @@ msgid "16"
msgstr ""

#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:132
msgid "Each ``clears`` bool can be actived if the corresponding ``clearsEnable`` bit is high."
msgid "Each ``clears`` bool can be activated if the corresponding ``clearsEnable`` bit is high."
msgstr ""

#: ../../SpinalHDL/Examples/Advanced ones/timer.rst:136
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6 changes: 3 additions & 3 deletions source/locale/gettext/SpinalHDL/Examples/Intermediates ones/vga.pot
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Expand Up @@ -8,7 +8,7 @@ msgid ""
msgstr ""
"Project-Id-Version: SpinalHDL \n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2024-01-02 16:09+0000\n"
"POT-Creation-Date: 2024-08-19 09:12+0000\n"
"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
"Language-Team: LANGUAGE <[email protected]>\n"
Expand Down Expand Up @@ -225,11 +225,11 @@ msgid "Horizontal and vertical logic"
msgstr ""

#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:148
msgid "The logic that generates horizontal and vertical synchronization signals is quite the same. It kind of resembles ~PWM~. The horizontal one counts up each cycle, while the vertical one use the horizontal syncronization signal as to increment."
msgid "The logic that generates horizontal and vertical synchronization signals is quite the same. It kind of resembles ~PWM~. The horizontal one counts up each cycle, while the vertical one use the horizontal synchronization signal as to increment."
msgstr ""

#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:150
msgid "Let's define ``HVArea``\\ , which represents one ~PWM~ and then instantiate it two times: one for both horizontal and vertical syncronization."
msgid "Let's define ``HVArea``\\ , which represents one ~PWM~ and then instantiate it two times: one for both horizontal and vertical synchronization."
msgstr ""

#: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:160
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4 changes: 2 additions & 2 deletions source/locale/gettext/SpinalHDL/Foreword/index.pot
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Expand Up @@ -8,7 +8,7 @@ msgid ""
msgstr ""
"Project-Id-Version: SpinalHDL \n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2024-01-02 16:09+0000\n"
"POT-Creation-Date: 2024-08-19 09:12+0000\n"
"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
"Language-Team: LANGUAGE <[email protected]>\n"
Expand All @@ -33,7 +33,7 @@ msgid "For conciseness, let's assume that SystemVerilog is a recent revision of
msgstr ""

#: ../../SpinalHDL/Foreword/index.rst:12
msgid "When reading this, we should not underestimate how much our attachment for our favourite HDL will bias our judgement."
msgid "When reading this, we should not underestimate how much our attachment for our favorite HDL will bias our judgement."
msgstr ""

#: ../../SpinalHDL/Foreword/index.rst:17
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8 changes: 4 additions & 4 deletions source/locale/gettext/SpinalHDL/Formal verification/index.pot
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Expand Up @@ -8,7 +8,7 @@ msgid ""
msgstr ""
"Project-Id-Version: SpinalHDL \n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2024-01-02 16:09+0000\n"
"POT-Creation-Date: 2024-08-19 09:12+0000\n"
"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
"Language-Team: LANGUAGE <[email protected]>\n"
Expand Down Expand Up @@ -145,7 +145,7 @@ msgid "Specifying the initial value of a signal"
msgstr ""

#: ../../SpinalHDL/Formal verification/index.rst:226
msgid "For instance, for the reset signal of the current clockdomain (usefull at the top)"
msgid "For instance, for the reset signal of the current clockdomain (useful at the top)"
msgstr ""

#: ../../SpinalHDL/Formal verification/index.rst:233
Expand Down Expand Up @@ -271,7 +271,7 @@ msgid "``pastValidAfterReset()``"
msgstr ""

#: ../../SpinalHDL/Formal verification/index.rst:309
msgid "Simliar to ``pastValid``, where only difference is that this would take reset into account. Can be understood as ``pastValid & past(!reset)``."
msgid "Similar to ``pastValid``, where only difference is that this would take reset into account. Can be understood as ``pastValid & past(!reset)``."
msgstr ""

#: ../../SpinalHDL/Formal verification/index.rst:311
Expand Down Expand Up @@ -307,5 +307,5 @@ msgid "For interfaces implement IMasterSlave"
msgstr ""

#: ../../SpinalHDL/Formal verification/index.rst:337
msgid "There could be functions in name ``formalAssertsMaster``, ``formalAssertsSlave``, ``formalAssumesMaster``, ``formalAssumesSlave`` or ``formalCovers``. Master/Slave are target interface type, so that ``formalAssertsMaster`` can be understand as \"formal verfication assertions for master interface\"."
msgid "There could be functions in name ``formalAssertsMaster``, ``formalAssertsSlave``, ``formalAssumesMaster``, ``formalAssumesSlave`` or ``formalCovers``. Master/Slave are target interface type, so that ``formalAssertsMaster`` can be understand as \"formal verification assertions for master interface\"."
msgstr ""
4 changes: 2 additions & 2 deletions source/locale/gettext/SpinalHDL/Getting Started/Install and setup.pot
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Expand Up @@ -8,7 +8,7 @@ msgid ""
msgstr ""
"Project-Id-Version: SpinalHDL \n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2024-04-19 10:29+0000\n"
"POT-Creation-Date: 2024-08-19 09:12+0000\n"
"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
"Language-Team: LANGUAGE <[email protected]>\n"
Expand Down Expand Up @@ -117,7 +117,7 @@ msgid "Go to the oss-cad-suite `release page <https://github.com/YosysHQ/oss-cad
msgstr ""

#: ../../SpinalHDL/Getting Started/Install and setup.rst:83
msgid "To use oss-cad-suite in a shell you need to load it's environment, e.g. via ``souce <path to oss-cad-suite>/environment``."
msgid "To use oss-cad-suite in a shell you need to load it's environment, e.g. via ``source <path to oss-cad-suite>/environment``."
msgstr ""

#: ../../SpinalHDL/Getting Started/Install and setup.rst:87
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4 changes: 2 additions & 2 deletions source/locale/gettext/SpinalHDL/Introduction/Projects using SpinalHDL.pot
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Expand Up @@ -8,7 +8,7 @@ msgid ""
msgstr ""
"Project-Id-Version: SpinalHDL \n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2024-01-02 16:09+0000\n"
"POT-Creation-Date: 2024-08-19 09:12+0000\n"
"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
"Language-Team: LANGUAGE <[email protected]>\n"
Expand All @@ -21,7 +21,7 @@ msgid "Projects using SpinalHDL"
msgstr ""

#: ../../SpinalHDL/Introduction/Projects using SpinalHDL.rst:4
msgid "Note that the following lists are very incompletes."
msgid "Note that the following lists are very incomplete."
msgstr ""

#: ../../SpinalHDL/Introduction/Projects using SpinalHDL.rst:9
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4 changes: 2 additions & 2 deletions source/locale/gettext/SpinalHDL/Legacy/pinsec/hardware_toplevel.pot
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Expand Up @@ -8,7 +8,7 @@ msgid ""
msgstr ""
"Project-Id-Version: SpinalHDL \n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2024-01-02 16:09+0000\n"
"POT-Creation-Date: 2024-08-19 09:12+0000\n"
"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
"Language-Team: LANGUAGE <[email protected]>\n"
Expand Down Expand Up @@ -319,7 +319,7 @@ msgid "This bridge will be used to connect low bandwidth peripherals to the AXI
msgstr ""

#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:411
msgid "The AXI4 crossbar that interconnect AXI4 masters and slaves together is generated by using an factory. The concept of this factory is to create it, then call many function on it to configure it, and finaly call the ``build`` function to ask the factory to generate the corresponding hardware :"
msgid "The AXI4 crossbar that interconnect AXI4 masters and slaves together is generated by using an factory. The concept of this factory is to create it, then call many function on it to configure it, and finally call the ``build`` function to ask the factory to generate the corresponding hardware :"
msgstr ""

#: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:421
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4 changes: 2 additions & 2 deletions source/locale/gettext/SpinalHDL/Legacy/pinsec/introduction.pot
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Expand Up @@ -8,7 +8,7 @@ msgid ""
msgstr ""
"Project-Id-Version: SpinalHDL \n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2024-01-02 16:09+0000\n"
"POT-Creation-Date: 2024-08-19 09:12+0000\n"
"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
"Language-Team: LANGUAGE <[email protected]>\n"
Expand All @@ -22,7 +22,7 @@ msgid "Introduction"
msgstr ""

#: ../../SpinalHDL/Legacy/pinsec/introduction.rst:10
msgid "This page only documents the SoC implemented with the first generation of RISC-V CPU created in SpinalHDL. This page does not document the VexRiscV CPU, which is the second generation of this SoC (and CPU) is available `here <https://github.com/SpinalHDL/VexRiscv>`__ and offers better perforance/area/features."
msgid "This page only documents the SoC implemented with the first generation of RISC-V CPU created in SpinalHDL. This page does not document the VexRiscV CPU, which is the second generation of this SoC (and CPU) is available `here <https://github.com/SpinalHDL/VexRiscv>`__ and offers better performance/area/features."
msgstr ""

#: ../../SpinalHDL/Legacy/pinsec/introduction.rst:17
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4 changes: 2 additions & 2 deletions source/locale/gettext/SpinalHDL/Legacy/riscv.pot
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Expand Up @@ -8,7 +8,7 @@ msgid ""
msgstr ""
"Project-Id-Version: SpinalHDL \n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2024-01-02 16:09+0000\n"
"POT-Creation-Date: 2024-08-19 09:12+0000\n"
"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
"Language-Team: LANGUAGE <[email protected]>\n"
Expand Down Expand Up @@ -157,7 +157,7 @@ msgid "Documentation"
msgstr ""

#: ../../SpinalHDL/Legacy/riscv.rst:80
msgid "Optimise instruction/data caches FMax by moving line hit condition forward into combinatorial paths."
msgid "Optimize instruction/data caches FMax by moving line hit condition forward into combinatorial paths."
msgstr ""

#: ../../SpinalHDL/Legacy/riscv.rst:82
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4 changes: 2 additions & 2 deletions source/locale/gettext/SpinalHDL/Libraries/Bus/amba3/ahblite3.pot
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Expand Up @@ -8,7 +8,7 @@ msgid ""
msgstr ""
"Project-Id-Version: SpinalHDL \n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2024-01-02 16:09+0000\n"
"POT-Creation-Date: 2024-08-19 09:12+0000\n"
"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
"Language-Team: LANGUAGE <[email protected]>\n"
Expand All @@ -21,7 +21,7 @@ msgid "AHB-Lite3"
msgstr ""

#: ../../SpinalHDL/Libraries/Bus/amba3/ahblite3.rst:6
msgid "Configuration and instanciation"
msgid "Configuration and instantiation"
msgstr ""

#: ../../SpinalHDL/Libraries/Bus/amba3/ahblite3.rst:8
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4 changes: 2 additions & 2 deletions source/locale/gettext/SpinalHDL/Libraries/Bus/amba3/apb3.pot
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Expand Up @@ -8,7 +8,7 @@ msgid ""
msgstr ""
"Project-Id-Version: SpinalHDL \n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2024-01-02 16:09+0000\n"
"POT-Creation-Date: 2024-08-19 09:12+0000\n"
"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
"Language-Team: LANGUAGE <[email protected]>\n"
Expand All @@ -25,7 +25,7 @@ msgid "The AMBA3-APB bus is commonly used to interface low bandwidth peripherals
msgstr ""

#: ../../SpinalHDL/Libraries/Bus/amba3/apb3.rst:8
msgid "Configuration and instanciation"
msgid "Configuration and instantiation"
msgstr ""

#: ../../SpinalHDL/Libraries/Bus/amba3/apb3.rst:10
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4 changes: 2 additions & 2 deletions source/locale/gettext/SpinalHDL/Libraries/Bus/amba4/axi4.pot
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Expand Up @@ -8,7 +8,7 @@ msgid ""
msgstr ""
"Project-Id-Version: SpinalHDL \n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2024-01-02 16:09+0000\n"
"POT-Creation-Date: 2024-08-19 09:12+0000\n"
"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
"Language-Team: LANGUAGE <[email protected]>\n"
Expand All @@ -25,7 +25,7 @@ msgid "The AXI4 is a high bandwidth bus defined by ARM."
msgstr ""

#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:7
msgid "Configuration and instanciation"
msgid "Configuration and instantiation"
msgstr ""

#: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:9
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