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Signed-off-by: eddieh-xlnx <[email protected]> Signed-off-by: Eddie Hung <[email protected]>
Xilinx · Jan 2, 2025 · 2a96896 · 2a96896
1 parent c76aa4d
commit 2a96896
Showing 1 changed file with 4 additions and 12 deletions.
diff --git a/test/src/com/xilinx/rapidwright/design/TestDesignTools.java b/test/src/com/xilinx/rapidwright/design/TestDesignTools.java
@@ -1476,12 +1476,8 @@ public void testGetConnectedCellsVersal() {
             Assertions.assertEquals("[processor/zero_flag_flop(BEL: DFF2)]",
                     DesignTools.getConnectedCells(spi).stream().map(Cell::toString).sorted().collect(Collectors.toList()).toString());
         }
-        // This design has no site routing for CLK
-        // {
-        //     SitePinInst spi = si.getSitePinInst("CLK");
-        //     Assertions.assertEquals("[]",
-        //             DesignTools.getConnectedCells(spi).stream().map(Cell::toString).sorted().collect(Collectors.toList()).toString());
-        // }
+        // This design has no intra-site routing for CLK so this test
+        // does not check for connected cells as done in other tests
     }
 
     @Test
@@ -1508,12 +1504,8 @@ public void testGetConnectedBELPinsVersal() {
             Assertions.assertEquals("[DFF2.CE]",
                     DesignTools.getConnectedBELPins(spi).stream().map(BELPin::toString).sorted().collect(Collectors.toList()).toString());
         }
-        // This design has no site routing for CLK
-        // {
-        //     SitePinInst spi = si.getSitePinInst("CLK");
-        //     Assertions.assertEquals("[]",
-        //             DesignTools.getConnectedBELPins(spi).stream().map(BELPin::toString).sorted().collect(Collectors.toList()).toString());
-        // }
+        // This design has no intra-site routing for CLK so this test
+        // does not check for connected cells as done in other tests
     }
 
     @ParameterizedTest