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Merge branch '2024.2.1' into test_is_site_inst_empty
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Signed-off-by: Chris Lavin <[email protected]>
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@clavin-xlnx
clavin-xlnx committed Jan 3, 2025
2 parents f4cdafa + f6ac9f9 commit 8af6bc7
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Showing 9 changed files with 150 additions and 34 deletions.
4 changes: 2 additions & 2 deletions .classpath
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Expand Up @@ -33,9 +33,9 @@
<classpathentry kind="lib" path="jars/kryo-5.2.1.jar"/>
<classpathentry kind="lib" path="jars/minlog-1.3.1.jar"/>
<classpathentry kind="lib" path="jars/jython-standalone-2.7.2.jar"/>
<classpathentry kind="lib" path="jars/rapidwright-api-lib-2024.2.0.jar">
<classpathentry kind="lib" path="jars/rapidwright-api-lib-2024.2.1-rc3.jar">
<attributes>
<attribute name="javadoc_location" value="jar:platform:/resource/RapidWright/jars/rapidwright-api-lib-2024.2.0-javadoc.jar!/"/>
<attribute name="javadoc_location" value="jar:platform:/resource/RapidWright/jars/rapidwright-api-lib-2024.2.1-rc3-javadoc.jar!/"/>
</attributes>
</classpathentry>
<classpathentry kind="lib" path="jars/jgrapht-core-1.3.0.jar"/>
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2 changes: 1 addition & 1 deletion .github/workflows/build.yml
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Expand Up @@ -5,7 +5,7 @@ on:
pull_request:

env:
RAPIDWRIGHT_VERSION: v2024.2.0-beta
RAPIDWRIGHT_VERSION: v2024.2.1-rc3-beta

jobs:
build:
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56 changes: 42 additions & 14 deletions src/com/xilinx/rapidwright/design/DesignTools.java
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Expand Up @@ -2003,7 +2003,8 @@ public static boolean stampPlacement(Design design, Module stamp, Map<String,Sit
}

/**
* Looks in the site instance for BEL pins connected to this site pin.
* Looks in the site instance for used BEL pins connected to this site pin.
* Will walk through used SitePIPs and routethru cells (e.g. LUTs, IMR registers, etc.)
* @param pin The BELPin to examine for connected BEL pins.
* @param si The SiteInst to examine for connected cells.
* @param action Perform this action on each connected BELPin.
Expand All @@ -2020,21 +2021,31 @@ private static void foreachConnectedBELPin(BELPin pin, SiteInst si, Consumer<BEL
p = pip.getInputPin().getSiteConns().get(0);
action.accept(p);
} else {
for (BELPin snk : pip.getOutputPin().getSiteConns()) {
action.accept(snk);
}
// Walk through any used SitePIPs
foreachConnectedBELPin(pip.getOutputPin(), si, action);
}
} else {
Cell c = si.getCell(p.getBELName());
if (c != null && c.getLogicalPinMapping(p.getName()) != null) {
if (c == null) {
continue;
}
if (c.getLogicalPinMapping(p.getName()) == null) {
continue;
}
BEL bel = c.getBEL();
if ((bel.isIMR() || bel.isSRIMR() || bel.isCEIMR()) && c.isRoutethru()) {
// Walk through IMR registers
foreachConnectedBELPin(bel.getPin("Q"), si, action);
} else {
action.accept(p);
}
}
}
}

/**
* Looks in the site instance for cells connected to this BEL pin and SiteInst.
* Looks in the site instance for cells connected (i.e. with a logical pin mapping) to this BEL pin and SiteInst.
* Will walk through used SitePIPs and routethru cells (e.g. LUTs, IMR registers, etc.)
* @param pin The BELPin to examine for connected cells.
* @param si The SiteInst to examine for connected cells.
* @return Set of connected cells to this pin.
Expand All @@ -2051,7 +2062,8 @@ public static Set<Cell> getConnectedCells(BELPin pin, SiteInst si) {
}

/**
* Looks in the site instance for cells connected to this site pin.
* Looks in the site instance for cells connected (i.e. with a logical pin mapping) to this site pin.
* Will walk through used SitePIPs and routethru cells (e.g. LUTs, IMR registers, etc.)
* @param pin The SitePinInst to examine for connected cells.
* @return Set of connected cells to this pin.
*/
Expand All @@ -2061,6 +2073,7 @@ public static Set<Cell> getConnectedCells(SitePinInst pin) {

/**
* Looks in the site instance for BEL pins connected to this BEL pin and SiteInst.
* Will walk through used SitePIPs and routethru cells (e.g. LUTs, IMR registers, etc.)
* @param pin The SitePinInst to examine for connected BEL pins.
* @param si The SiteInst to examine for connected cells.
* @return Set of BEL pins to this site pin.
Expand Down Expand Up @@ -2297,8 +2310,7 @@ public static List<String> getAllRoutedSitePinsFromPhysicalPin(Cell cell, Net ne
} else if (bel.isLUT() ||
bel.getBELType().endsWith("MUX") || // F[789]MUX
// Versal
bel.isSliceFFClkMod() ||
bel.getName().endsWith("_IMR")) {
bel.isSliceFFClkMod() || bel.isIMR() || bel.isSRIMR() || bel.isCEIMR()) {
Cell possibleRouteThru = inst.getCell(bel);
if (possibleRouteThru == null) {
BELPin clkBelPin = bel.isSliceFFClkMod() ? bel.getPin("CLK") : null;
Expand Down Expand Up @@ -4367,13 +4379,18 @@ public static void addProhibitConstraint(Design design, List<String> belLocation
* tied to GND or VCC) when following the Net's PIPs.
* A source pin will be marked as being routed if it drives at least one PIP.
* @param net Net on which pins are to be updated.
* @return Number of unrouted sink pins on net.
*/
public static void updatePinsIsRouted(Net net) {
public static int updatePinsIsRouted(Net net) {
int numUnroutedSinkPins = 0;
for (SitePinInst spi : net.getPins()) {
spi.setRouted(false);
if (!spi.isOutPin()) {
numUnroutedSinkPins++;
}
}
if (!net.hasPIPs()) {
return;
return numUnroutedSinkPins;
}

Map<Node, SitePinInst> node2spi = new HashMap<>();
Expand All @@ -4392,23 +4409,34 @@ public static void updatePinsIsRouted(Net net) {
}
while (!queue.isEmpty()) {
NetTools.NodeTree node = queue.poll();
SitePinInst spi = node2spi.get(node);
SitePinInst spi = node2spi.remove(node);
if (spi != null) {
spi.setRouted(true);
if (!spi.isOutPin()) {
assert(numUnroutedSinkPins > 0);
numUnroutedSinkPins--;
}
}
queue.addAll(node.fanouts);
}
return numUnroutedSinkPins;
}

/**
* Update the SitePinInst.isRouted() value of all sink pins in the given
* Design. See {@link #updatePinsIsRouted(Net)}.
* @param design Design in which pins are to be updated.
* @return Number of unrouted sink pins (not driven by hierarchical ports) across design.
*/
public static void updatePinsIsRouted(Design design) {
public static int updatePinsIsRouted(Design design) {
int totalUnroutedSinkPins = 0;
for (Net net : design.getNets()) {
updatePinsIsRouted(net);
int numUnroutedSinkPins = updatePinsIsRouted(net);
if (!DesignTools.isNetDrivenByHierPort(net)) {
totalUnroutedSinkPins += numUnroutedSinkPins;
}
}
return totalUnroutedSinkPins;
}

/**
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19 changes: 9 additions & 10 deletions src/com/xilinx/rapidwright/rwroute/RouterHelper.java
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Expand Up @@ -360,20 +360,19 @@ public static Set<SitePinInst> invertPossibleGndPinsToVccPins(Design design,
SiteInst si = spi.getSiteInst();
String siteWireName = spi.getSiteWireName();
if (invertLutInputs && spi.isLUTInputPin()) {
BELPin spiBelPin;
if (isVersal) {
// Walk through IMR before checking for connected cells
spiBelPin = si.getBELPin(spi.getSiteWireName() + "_IMR", "Q");
} else {
spiBelPin = spi.getBELPin();
}
Collection<Cell> connectedCells = DesignTools.getConnectedCells(spiBelPin, si);
Collection<Cell> connectedCells = DesignTools.getConnectedCells(spi);
if (connectedCells.isEmpty()) {
for (BELPin belPin : si.getSiteWirePins(spiBelPin.getSiteWireName())) {
for (BELPin belPin : si.getSiteWirePins(spi.getSiteWireName())) {
if (belPin.isSitePort()) {
continue;
}
BEL bel = belPin.getBEL();
if (isVersal && bel.isIMR()) {
// Since DesignTools.getConnectedCells() will only return cells
// for which a logical pin mapping exists, for the purpose of
// identifying SRL16s walk through this IMR
bel = si.getBEL(bel.getName().substring(0,1) + "6LUT");
}
Cell cell = si.getCell(bel);
if (cell == null) {
continue;
Expand Down Expand Up @@ -411,7 +410,7 @@ public static Set<SitePinInst> invertPossibleGndPinsToVccPins(Design design,
toInvertPins.add(spi);
// Re-paint the intra-site routing from GND to VCC
// (no intra site routing will occur during Net.addPin() later)
si.routeIntraSiteNet(vccNet, spi.getBELPin(), spiBelPin);
si.routeIntraSiteNet(vccNet, spi.getBELPin(), spi.getBELPin());

for (Cell cell : connectedCells) {
// Find the logical pin name
Expand Down
32 changes: 32 additions & 0 deletions test/src/com/xilinx/rapidwright/design/TestDesign.java
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Expand Up @@ -515,4 +515,36 @@ public void testNetOrder(String dcpFileName) {
Assertions.assertTrue(Arrays.equals(nets1, nets2));
}
}

@Test
public void testPlaceCellPinMappings() {
final EDIFNetlist netlist = TestEDIF.createEmptyNetlist();
final Design design = new Design(netlist);

final Cell myCell = design.createCell("myCell", Unisim.FDRE);
Assertions.assertTrue(myCell.getPinMappingsL2P().isEmpty());

final Site site = design.getDevice().getSite(SITE);
design.createSiteInst(site);
BEL bel = site.getBEL("AFF");
Assertions.assertNotNull(bel);
design.placeCell(myCell, site, bel);

// Check that L2P and P2L are consistent
for (String logPin : new String[]{"CE", "C", "D", "R", "Q"}) {
String physPin = myCell.getPhysicalPinMapping(logPin);
Assertions.assertEquals(logPin, myCell.getLogicalPinMapping(physPin));
}

// Move the Cell to another BEL
myCell.unplace();
bel = site.getBEL("BFF");
design.placeCell(myCell, site, bel);

// Check that L2P and P2L remain consistent
for (String logPin : new String[]{"CE", "C", "D", "R", "Q"}) {
String physPin = myCell.getPhysicalPinMapping(logPin);
Assertions.assertEquals(logPin, myCell.getLogicalPinMapping(physPin));
}
}
}
59 changes: 58 additions & 1 deletion test/src/com/xilinx/rapidwright/design/TestDesignTools.java
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Expand Up @@ -1446,11 +1446,68 @@ public void testGetConnectedBELPins() {
{
DesignTools.createMissingSitePinInsts(design, design.getNet("clk"));
SitePinInst spi = si.getSitePinInst("CLK2");
Assertions.assertEquals("[EFF.CLK, EFF2.CLK, FFF.CLK, FFF2.CLK, GFF.CLK, GFF2.CLK, HFF.CLK, HFF2.CLK]",
Assertions.assertNull(si.getCell("EFF2"));
Assertions.assertEquals("[EFF.CLK, FFF.CLK, FFF2.CLK, GFF.CLK, GFF2.CLK, HFF.CLK, HFF2.CLK]",
DesignTools.getConnectedBELPins(spi).stream().map(BELPin::toString).sorted().collect(Collectors.toList()).toString());
}
}

@Test
public void testGetConnectedCellsVersal() {
Design design = RapidWrightDCP.loadDCP("picoblaze_2022.2.dcp");
SiteInst si = design.getSiteInstFromSiteName("SLICE_X140Y3");
{
SitePinInst spi = si.getSitePinInst("F6");
Assertions.assertEquals("[processor/address_loop[5].upper_pc.high_int_vector.pc_lut(BEL: F6LUT)]",
DesignTools.getConnectedCells(spi).stream().map(Cell::toString).sorted().collect(Collectors.toList()).toString());
}
{
SitePinInst spi = si.getSitePinInst("D3");
Assertions.assertEquals("[processor/init_zero_muxcy_CARRY4_CARRY8_LUT6CY_3/LUTCY1_INST(BEL: D5LUT), processor/init_zero_muxcy_CARRY4_CARRY8_LUT6CY_3/LUTCY2_INST(BEL: D6LUT)]",
DesignTools.getConnectedCells(spi).stream().map(Cell::toString).sorted().collect(Collectors.toList()).toString());
}
{
SitePinInst spi = si.getSitePinInst("EX");
Assertions.assertEquals("[processor/carry_flag_flop(BEL: EFF)]",
DesignTools.getConnectedCells(spi).stream().map(Cell::toString).sorted().collect(Collectors.toList()).toString());
}
{
SitePinInst spi = si.getSitePinInst("CKEN2");
Assertions.assertEquals("[processor/zero_flag_flop(BEL: DFF2)]",
DesignTools.getConnectedCells(spi).stream().map(Cell::toString).sorted().collect(Collectors.toList()).toString());
}
// This design has no intra-site routing for CLK so this test
// does not check for connected cells as done in other tests
}

@Test
public void testGetConnectedBELPinsVersal() {
Design design = RapidWrightDCP.loadDCP("picoblaze_2022.2.dcp");
SiteInst si = design.getSiteInstFromSiteName("SLICE_X140Y3");
{
SitePinInst spi = si.getSitePinInst("F6");
Assertions.assertEquals("[F6LUT.A6]",
DesignTools.getConnectedBELPins(spi).stream().map(BELPin::toString).sorted().collect(Collectors.toList()).toString());
}
{
SitePinInst spi = si.getSitePinInst("D3");
Assertions.assertEquals("[D5LUT.A3, D6LUT.A3]",
DesignTools.getConnectedBELPins(spi).stream().map(BELPin::toString).sorted().collect(Collectors.toList()).toString());
}
{
SitePinInst spi = si.getSitePinInst("EX");
Assertions.assertEquals("[EFF.D]",
DesignTools.getConnectedBELPins(spi).stream().map(BELPin::toString).sorted().collect(Collectors.toList()).toString());
}
{
SitePinInst spi = si.getSitePinInst("CKEN2");
Assertions.assertEquals("[DFF2.CE]",
DesignTools.getConnectedBELPins(spi).stream().map(BELPin::toString).sorted().collect(Collectors.toList()).toString());
}
// This design has no intra-site routing for CLK so this test
// does not check for connected cells as done in other tests
}

@ParameterizedTest
@CsvSource({
// Cell pin placed onto a D6LUT/O6 -- its net does exit the site
Expand Down
8 changes: 4 additions & 4 deletions test/src/com/xilinx/rapidwright/eco/TestECOTools.java
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Expand Up @@ -187,7 +187,7 @@ public void testConnectNetSwapSinks() {
EDIFNetlist netlist = design.getNetlist();
Map<Net, Set<SitePinInst>> deferredRemovals = new HashMap<>();

DesignTools.updatePinsIsRouted(design);
Assertions.assertEquals(0, DesignTools.updatePinsIsRouted(design));

// Disconnect the ILA inputs
List<EDIFHierPortInst> disconnectPins = new ArrayList<>();
Expand Down Expand Up @@ -253,7 +253,7 @@ public void testConnectNetSwapSource() {
EDIFNetlist netlist = design.getNetlist();
Map<Net, Set<SitePinInst>> deferredRemovals = new HashMap<>();

DesignTools.updatePinsIsRouted(design);
Assertions.assertEquals(0, DesignTools.updatePinsIsRouted(design));

// Disconnect the outputs
List<EDIFHierPortInst> disconnectPins = new ArrayList<>();
Expand Down Expand Up @@ -386,7 +386,7 @@ public void testCreateCell() {
Design design = RapidWrightDCP.loadDCP("picoblaze_ooc_X10Y235.dcp");
EDIFNetlist netlist = design.getNetlist();

DesignTools.updatePinsIsRouted(design);
Assertions.assertEquals(0, DesignTools.updatePinsIsRouted(design));

EDIFCell reference = netlist.getCell("kcpsm6");
List<String> instNames = Arrays.asList("processor2", "processor3");
Expand Down Expand Up @@ -474,7 +474,7 @@ public void testCreateNet() {
Design design = RapidWrightDCP.loadDCP("picoblaze_ooc_X10Y235.dcp");
EDIFNetlist netlist = design.getNetlist();

DesignTools.updatePinsIsRouted(design);
Assertions.assertEquals(0, DesignTools.updatePinsIsRouted(design));

List<String> netNames = Arrays.asList("processor/foo", "your_program/bar");
ECOTools.createNet(design, netNames);
Expand Down
2 changes: 1 addition & 1 deletion test/src/com/xilinx/rapidwright/interchange/TestPhysNetlistWriter.java
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Expand Up @@ -331,7 +331,7 @@ public void testSimulateSwappedLutPinsWithRWRoute(String path, @TempDir Path tem
inputDesign = null;

Assertions.assertTrue(LUTTools.swapLutPinsFromPIPs(outputDesign) > 0);
DesignTools.updatePinsIsRouted(outputDesign);
Assertions.assertEquals(0, DesignTools.updatePinsIsRouted(outputDesign));
TestRWRoute.assertAllSourcesRoutedFlagSet(outputDesign);
TestRWRoute.assertAllPinsRouted(outputDesign);
VivadoToolsHelper.assertFullyRouted(outputDesign);
Expand Down
2 changes: 1 addition & 1 deletion test/src/com/xilinx/rapidwright/rwroute/TestGlobalSignalRouting.java
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Expand Up @@ -339,7 +339,7 @@ public void testSymmetricClkRouting() {
if (node != null) used.add(node);
}
}
DesignTools.updatePinsIsRouted(net);
Assertions.assertEquals(0, DesignTools.updatePinsIsRouted(net));
for (SitePinInst spi : net.getPins()) {
Assertions.assertTrue(spi.isRouted());
}
Expand Down

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