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Provide the equivalent of write_checkpoint -cell in RapidWright
enhancement
#386
opened Apr 13, 2022 by
clavin-xlnx
Adding an API to insert a buffer cell (LUT1 or FF) on a module's ports
enhancement
#356
opened Mar 4, 2022 by
clavin-xlnx
Basic Router does not route across SLRs correctly
enhancement
#354
opened Mar 4, 2022 by
clavin-xlnx
DesignTools.copyImplementation() not reproducing SitePinInst objects on copied nets correctly
bug
#347
opened Feb 23, 2022 by
clavin-xlnx
ModuleImpls requires pointer identical netlist for Modules
enhancement
#301
opened Dec 2, 2021 by
clavin-xlnx
DRC to identify missing SitePinInst-s in a design
enhancement
#282
opened Nov 2, 2021 by
eddieh-xlnx
Standardize and make clear when to unique-ify cell names
enhancement
#278
opened Oct 29, 2021 by
clavin-xlnx
Add examples to :/test to be run during CI
enhancement
help wanted
#247
opened Sep 28, 2021 by
eddieh-xlnx
ModuleInstanceScene does not deal with relocation correctly
help wanted
#230
opened Sep 17, 2021 by
jakobwenzel
Wire w/ Null Tile included in tile.getWireConnections(wire) for Wires with FAKE_SM_VALUE Speed Model
#80
opened Sep 28, 2020 by
GTRI-Dallon
EDIFCellInst.equals() returns True for instances of different type in different parents
enhancement
#42
opened Jul 25, 2019 by
cfib
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