[RWRoute] Clock router for Versal architecture

[WenhaoLin-AMD]

The clock router for Versal architecture is based on the symmetric clock routing flow for UltraScale/UltraScale+. The main differences between them are listed below:

UltraScale/UltraScale+	Versal
First compute the centroid clock region (CR) of all target CRs, then route the clock buffer to an HROUTE node in centroid.	Vivado routes the signal from the clock buffer to a VROUTE node in a nearby CR, and we follow this behavior.
Use two VROUTE nodes: vrouteUp (for the target CRs above the centroid ) and vrouteDown (for the target CRs below the centroid)	Only use one VROUTE node. It uses VDISTR_LVL{1,2} nodes to go up and down.
First map the sink pins to leaf clock buffers (LCBs) with a simple heuristic, then route LCBs to sinks	Directly route the sinks to LCBs.
Operate on Wire objects, using RouteNode.getWireConnections() to search downhill	Operate on Node objects, using Node.getAllDownhillNodes() (since RouteNode.getWireConnections() relies on tile.getWireConnections() which doesn't work correctly on Versal devices, see #1096). Specifically, we replace RouteNode with RouterHelper.NodeWithPrev.