IO_Design

Versal™ Adaptive SoC Architecture Tutorials See Vivado™ Development Environment on amd.com

XPHY I/O Source Synchronous Interfaces in Versal Adaptive SoCs

Summary

This tutorial describes how to construct source synchronous high-speed I/O interfaces using the Advanced I/O Wizard (AIOW) on Versal™ devices. The wizard instantiates and configures I/O and clocking logic such as XPHY nibbles and XPLL blocks that are included in the physical-side interface (PHY) architecture. The designs in this tutorial are tested on the VCK190 evaluation board using the FMC XM107 loopback card.

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Introduction

This tutorial covers two designs for a source-synchronous application using the AIOW:

• Single-bank source synchronous design
• Multi-bank source synchronous design

The AIOW provides the option to choose the number of banks, but not to exceed three banks. The wizard creates one bank instance for each bank. Both designs use low-voltage differential signaling (LVDS) for data transmission speeds at 1800 Mb/s. See the Versal AI Core Series Data Sheet: DC and AC Switching Characteristics (DS957) for the speeds supported that can transmit and receive the LVDS standard. The underlying I/O and XPLL clocking architecture for these designs can be found in the Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010) and Versal Adaptive SoC Clocking Resources Architecture Manual (AM003), respectively.

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Single-Bank Source Synchronous Design

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Multi-Bank Source Synchronous Design

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References

These documents provide supplemental material useful with this tutorial:

1. Versal Architecture and Product Data Sheet: Overview (DS950)
2. Versal AI Core Series Data Sheet: DC and AC Switching Characteristics (DS957)
3. Versal Adaptive SoC Clocking Resources Architecture Manual (AM003)
4. Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010)
5. Advanced I/O Wizard LogiCORE IP Product Guide (PG320)
6. VCK190 Evaluation Board User Guide (UG1366)

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