Merge pull request #95 from Xilinx/fix/mobilenetv1

Enable LUTRAM for RTL thresholding memory
Xilinx · May 15, 2024 · 311ce5e · 311ce5e
2 parents 229867e + 94a4f74
commit 311ce5e
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Showing 6 changed files with 96 additions and 384 deletions.
diff --git a/build/mobilenet-v1/build.py b/build/mobilenet-v1/build.py
@@ -124,20 +124,13 @@ def select_build_steps(platform):
         # for Zynq, use the board name as the release name
         # e.g. ZCU104
         release_platform_name = platform_name
-        # for ZCU104 we provide a specialize layer json
-        specialize_layer_file = (
-            "specialize_layers_config/ZCU104_specialize_layers_config.json"
-            if platform_name == "ZCU104"
-            else None
-        )
     platform_dir = "release/%s" % release_platform_name
     os.makedirs(platform_dir, exist_ok=True)
 
     cfg = build_cfg.DataflowBuildConfig(
         steps=select_build_steps(platform_name),
         output_dir="output_%s_%s" % (model_name, release_platform_name),
         folding_config_file="folding_config/%s_folding_config.json" % platform_name,
-        specialize_layers_config_file=specialize_layer_file,
         synth_clk_period_ns=select_clk_period(platform_name),
         board=platform_name,
         shell_flow_type=shell_flow_type,