[FIFO] call get_simkernel_so for xsicpp FIFO sizing too

src/finn/core/rtlsim_exec.py

@@ -218,6 +218,8 @@ def rtlsim_exec_cppxsi(model, execution_context, dummy_data_mode=False, postproc
         "TRACE_CMD": "" if trace_file is None else "top->trace_all();",
         # code to post-process final sim status to extract more data
         "POSTPROC_CPP": postproc_cpp,
+        # sim kernel .so to use (depends on Vivado version)
+        "SIMKERNEL_SO": pyxsi_utils.get_simkernel_so(),
     }
     for key, val in template_dict.items():
         fifosim_cpp_template = fifosim_cpp_template.replace(f"@{key}@", str(val))

src/finn/qnn-data/cpp/xsi_simdriver.cpp

@@ -218,7 +218,7 @@ void reset() {
 
 int main(int argc, char *argv[]) {
     // load pre-compiled rtl simulation
-    std::string simengine_libname = "librdi_simulator_kernel.so";
+    std::string simengine_libname = "@SIMKERNEL_SO@";
     std::string design_libname = "xsim.dir/@TOP_MODULE_NAME@/xsimk.so";
     top = new Xsi::Loader(design_libname, simengine_libname);
     s_xsi_setup_info info;